target/linux/s3c24xx/patches-2.6.30/060-spi-gpio-non-blocking.patch

   1 --- a/arch/arm/mach-s3c2410/include/mach/spi-gpio.h
   2 +++ b/arch/arm/mach-s3c2410/include/mach/spi-gpio.h
   3 @@ -21,7 +21,8 @@ struct s3c2410_spigpio_info {
   4         int                      num_chipselect;
   5         int                      bus_num;
   6
   7 -       void (*chip_select)(struct s3c2410_spigpio_info *spi, int cs);
   8 +       int                      non_blocking_transfer;
   9 +       void (*chip_select)(struct s3c2410_spigpio_info *spi, int csid, int cs);
  10  };
  11
  12
  13 --- a/drivers/spi/spi_bitbang.c
  14 +++ b/drivers/spi/spi_bitbang.c
  15 @@ -264,6 +264,123 @@ static int spi_bitbang_bufs(struct spi_d
  16   * Drivers can provide word-at-a-time i/o primitives, or provide
  17   * transfer-at-a-time ones to leverage dma or fifo hardware.
  18   */
  19 +
  20 +/* Synchronous non blocking transfer */
  21 +int
  22 +spi_bitbang_transfer_sync(struct spi_device *spi, struct spi_message *m)
  23 +{
  24 +       struct spi_bitbang *bitbang = spi_master_get_devdata(spi->master);
  25 +       struct spi_transfer *t;
  26 +       unsigned long flags;
  27 +       int cs_change = 1;
  28 +       int status;
  29 +       int nsecs;
  30 +       int (*setup_transfer)(struct spi_device *, struct spi_transfer *);
  31 +
  32 +       /* FIXME this is made-up ... the correct value is known to
  33 +        * word-at-a-time bitbang code, and presumably chipselect()
  34 +        * should enforce these requirements too?
  35 +        */
  36 +       nsecs = 100;
  37 +       cs_change = 1;
  38 +       status = 0;
  39 +       setup_transfer = NULL;
  40 +
  41 +       local_irq_save(flags);
  42 +       list_for_each_entry (t, &m->transfers, transfer_list) {
  43 +               /* override or restore speed and wordsize */
  44 +               if (t->speed_hz || t->bits_per_word) {
  45 +                       setup_transfer = bitbang->setup_transfer;
  46 +                       if (!setup_transfer) {
  47 +                               status = -ENOPROTOOPT;
  48 +                               break;
  49 +                       }
  50 +               }
  51 +               if (setup_transfer) {
  52 +                       status = setup_transfer(spi, t);
  53 +                       if (status < 0)
  54 +                               break;
  55 +               }
  56 +
  57 +               /* set up default clock polarity, and activate chip;
  58 +                * this implicitly updates clock and spi modes as
  59 +                * previously recorded for this device via setup().
  60 +                * (and also deselects any other chip that might be
  61 +                * selected ...)
  62 +                */
  63 +
  64 +               if (cs_change) {
  65 +                       bitbang->chipselect(spi, BITBANG_CS_ACTIVE);
  66 +                       ndelay(nsecs);
  67 +               }
  68 +
  69 +               cs_change = t->cs_change;
  70 +               if (!t->tx_buf && !t->rx_buf && t->len) {
  71 +                       status = -EINVAL;
  72 +                       break;
  73 +               }
  74 +
  75 +               /* transfer data.  the lower level code handles any
  76 +                * new dma mappings it needs. our caller always gave
  77 +                * us dma-safe buffers.
  78 +                */
  79 +               if (t->len) {
  80 +                       /* REVISIT dma API still needs a designated
  81 +                        * DMA_ADDR_INVALID; ~0 might be better.
  82 +                        */
  83 +                       if (!m->is_dma_mapped)
  84 +                               t->rx_dma = t->tx_dma = 0;
  85 +                       status = bitbang->txrx_bufs(spi, t);
  86 +               }
  87 +
  88 +               if (status > 0)
  89 +                       m->actual_length += status;
  90 +               if (status != t->len) {
  91 +                       /* always report some kind of error */
  92 +                       if (status >= 0)
  93 +                               status = -EREMOTEIO;
  94 +                       break;
  95 +               }
  96 +               status = 0;
  97 +                       /* protocol tweaks before next transfer */
  98 +               if (t->delay_usecs)
  99 +                       udelay(t->delay_usecs);
 100 +                       if (!cs_change)
 101 +                       continue;
 102 +               if (t->transfer_list.next == &m->transfers)
 103 +                       break;
 104 +                       /* sometimes a short mid-message deselect of the chip
 105 +                * may be needed to terminate a mode or command
 106 +                */
 107 +               ndelay(nsecs);
 108 +               bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
 109 +               ndelay(nsecs);
 110 +       }
 111 +
 112 +       m->status = status;
 113 +       if (m->complete)
 114 +               m->complete(m->context);
 115 +
 116 +       /* restore speed and wordsize */
 117 +       if (setup_transfer)
 118 +               setup_transfer(spi, NULL);
 119 +
 120 +       /* normally deactivate chipselect ... unless no error and
 121 +        * cs_change has hinted that the next message will probably
 122 +        * be for this chip too.
 123 +        */
 124 +       if (!(status == 0 && cs_change)) {
 125 +               ndelay(nsecs);
 126 +               bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
 127 +               ndelay(nsecs);
 128 +       }
 129 +
 130 +       local_irq_restore(flags);
 131 +
 132 +       return status;
 133 +}
 134 +EXPORT_SYMBOL_GPL(spi_bitbang_transfer_sync);
 135 +
 136  static void bitbang_work(struct work_struct *work)
 137  {
 138         struct spi_bitbang      *bitbang =
 139 @@ -274,120 +391,13 @@ static void bitbang_work(struct work_str
 140         bitbang->busy = 1;
 141         while (!list_empty(&bitbang->queue)) {
 142                 struct spi_message      *m;
 143 -               struct spi_device       *spi;
 144 -               unsigned                nsecs;
 145 -               struct spi_transfer     *t = NULL;
 146 -               unsigned                tmp;
 147 -               unsigned                cs_change;
 148 -               int                     status;
 149 -               int                     (*setup_transfer)(struct spi_device *,
 150 -                                               struct spi_transfer *);
 151
 152                 m = container_of(bitbang->queue.next, struct spi_message,
 153                                 queue);
 154                 list_del_init(&m->queue);
 155 -               spin_unlock_irqrestore(&bitbang->lock, flags);
 156 -
 157 -               /* FIXME this is made-up ... the correct value is known to
 158 -                * word-at-a-time bitbang code, and presumably chipselect()
 159 -                * should enforce these requirements too?
 160 -                */
 161 -               nsecs = 100;
 162 -
 163 -               spi = m->spi;
 164 -               tmp = 0;
 165 -               cs_change = 1;
 166 -               status = 0;
 167 -               setup_transfer = NULL;
 168 -
 169 -               list_for_each_entry (t, &m->transfers, transfer_list) {
 170 -
 171 -                       /* override or restore speed and wordsize */
 172 -                       if (t->speed_hz || t->bits_per_word) {
 173 -                               setup_transfer = bitbang->setup_transfer;
 174 -                               if (!setup_transfer) {
 175 -                                       status = -ENOPROTOOPT;
 176 -                                       break;
 177 -                               }
 178 -                       }
 179 -                       if (setup_transfer) {
 180 -                               status = setup_transfer(spi, t);
 181 -                               if (status < 0)
 182 -                                       break;
 183 -                       }
 184 -
 185 -                       /* set up default clock polarity, and activate chip;
 186 -                        * this implicitly updates clock and spi modes as
 187 -                        * previously recorded for this device via setup().
 188 -                        * (and also deselects any other chip that might be
 189 -                        * selected ...)
 190 -                        */
 191 -                       if (cs_change) {
 192 -                               bitbang->chipselect(spi, BITBANG_CS_ACTIVE);
 193 -                               ndelay(nsecs);
 194 -                       }
 195 -                       cs_change = t->cs_change;
 196 -                       if (!t->tx_buf && !t->rx_buf && t->len) {
 197 -                               status = -EINVAL;
 198 -                               break;
 199 -                       }
 200 -
 201 -                       /* transfer data.  the lower level code handles any
 202 -                        * new dma mappings it needs. our caller always gave
 203 -                        * us dma-safe buffers.
 204 -                        */
 205 -                       if (t->len) {
 206 -                               /* REVISIT dma API still needs a designated
 207 -                                * DMA_ADDR_INVALID; ~0 might be better.
 208 -                                */
 209 -                               if (!m->is_dma_mapped)
 210 -                                       t->rx_dma = t->tx_dma = 0;
 211 -                               status = bitbang->txrx_bufs(spi, t);
 212 -                       }
 213 -                       if (status > 0)
 214 -                               m->actual_length += status;
 215 -                       if (status != t->len) {
 216 -                               /* always report some kind of error */
 217 -                               if (status >= 0)
 218 -                                       status = -EREMOTEIO;
 219 -                               break;
 220 -                       }
 221 -                       status = 0;
 222 -
 223 -                       /* protocol tweaks before next transfer */
 224 -                       if (t->delay_usecs)
 225 -                               udelay(t->delay_usecs);
 226 -
 227 -                       if (!cs_change)
 228 -                               continue;
 229 -                       if (t->transfer_list.next == &m->transfers)
 230 -                               break;
 231 -
 232 -                       /* sometimes a short mid-message deselect of the chip
 233 -                        * may be needed to terminate a mode or command
 234 -                        */
 235 -                       ndelay(nsecs);
 236 -                       bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
 237 -                       ndelay(nsecs);
 238 -               }
 239 -
 240 -               m->status = status;
 241 -               m->complete(m->context);
 242 -
 243 -               /* restore speed and wordsize */
 244 -               if (setup_transfer)
 245 -                       setup_transfer(spi, NULL);
 246 -
 247 -               /* normally deactivate chipselect ... unless no error and
 248 -                * cs_change has hinted that the next message will probably
 249 -                * be for this chip too.
 250 -                */
 251 -               if (!(status == 0 && cs_change)) {
 252 -                       ndelay(nsecs);
 253 -                       bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
 254 -                       ndelay(nsecs);
 255 -               }
 256
 257 +               spin_unlock_irqrestore(&bitbang->lock, flags);
 258 +               spi_bitbang_transfer_sync(m->spi, m);
 259                 spin_lock_irqsave(&bitbang->lock, flags);
 260         }
 261         bitbang->busy = 0;
 262 @@ -459,6 +469,9 @@ int spi_bitbang_start(struct spi_bitbang
 263
 264         if (!bitbang->master->transfer)
 265                 bitbang->master->transfer = spi_bitbang_transfer;
 266 +       if (!bitbang->master->transfer_sync && bitbang->non_blocking_transfer)
 267 +               bitbang->master->transfer_sync = spi_bitbang_transfer_sync;
 268 +
 269         if (!bitbang->txrx_bufs) {
 270                 bitbang->use_dma = 0;
 271                 bitbang->txrx_bufs = spi_bitbang_bufs;
 272 --- a/drivers/spi/spi_s3c24xx_gpio.c
 273 +++ b/drivers/spi/spi_s3c24xx_gpio.c
 274 @@ -91,7 +91,7 @@ static void s3c2410_spigpio_chipselect(s
 275         struct s3c2410_spigpio *sg = spidev_to_sg(dev);
 276
 277         if (sg->info && sg->info->chip_select)
 278 -               (sg->info->chip_select)(sg->info, value);
 279 +               (sg->info->chip_select)(sg->info, dev->chip_select, value);
 280  }
 281
 282  static int s3c2410_spigpio_probe(struct platform_device *dev)
 283 @@ -112,14 +112,17 @@ static int s3c2410_spigpio_probe(struct
 284
 285         platform_set_drvdata(dev, sp);
 286
 287 -       /* copy in the plkatform data */
 288 +       /* copy in the platform data */
 289         info = sp->info = dev->dev.platform_data;
 290
 291 +       master->num_chipselect = info->num_chipselect;
 292 +
 293         /* setup spi bitbang adaptor */
 294         sp->bitbang.master = spi_master_get(master);
 295         sp->bitbang.master->bus_num = info->bus_num;
 296         sp->bitbang.master->num_chipselect = info->num_chipselect;
 297         sp->bitbang.chipselect = s3c2410_spigpio_chipselect;
 298 +       sp->bitbang.non_blocking_transfer = info->non_blocking_transfer;
 299
 300         sp->bitbang.txrx_word[SPI_MODE_0] = s3c2410_spigpio_txrx_mode0;
 301         sp->bitbang.txrx_word[SPI_MODE_1] = s3c2410_spigpio_txrx_mode1;
 302 --- a/include/linux/mmc/core.h
 303 +++ b/include/linux/mmc/core.h
 304 @@ -129,6 +129,8 @@ struct mmc_request {
 305  struct mmc_host;
 306  struct mmc_card;
 307
 308 +extern void mmc_flush_scheduled_work(void);
 309 +
 310  extern void mmc_wait_for_req(struct mmc_host *, struct mmc_request *);
 311  extern int mmc_wait_for_cmd(struct mmc_host *, struct mmc_command *, int);
 312  extern int mmc_wait_for_app_cmd(struct mmc_host *, struct mmc_card *,
 313 --- a/include/linux/mmc/sdio_ids.h
 314 +++ b/include/linux/mmc/sdio_ids.h
 315 @@ -25,5 +25,9 @@
 316
 317  #define SDIO_VENDOR_ID_MARVELL                 0x02df
 318  #define SDIO_DEVICE_ID_MARVELL_LIBERTAS                0x9103
 319 +#define SDIO_DEVICE_ID_MARVELL_88W8688         0x9104
 320 +#define SDIO_VENDOR_ID_ATHEROS                 0x0271
 321 +#define SDIO_DEVICE_ID_ATHEROS_AR6001          0x0100
 322 +#define SDIO_DEVICE_ID_ATHEROS_AR6002          0x0200
 323
 324  #endif
 325 --- a/include/linux/spi/spi_bitbang.h
 326 +++ b/include/linux/spi/spi_bitbang.h
 327 @@ -31,6 +31,9 @@ struct spi_bitbang {
 328         u8                      use_dma;
 329         u8                      flags;          /* extra spi->mode support */
 330
 331 +       /* Support for synchronous non blocking transfers */
 332 +       int                     non_blocking_transfer;
 333 +
 334         struct spi_master       *master;
 335
 336         /* setup_transfer() changes clock and/or wordsize to match settings
 337 @@ -62,6 +65,8 @@ extern void spi_bitbang_cleanup(struct s
 338  extern int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m);
 339  extern int spi_bitbang_setup_transfer(struct spi_device *spi,
 340                                       struct spi_transfer *t);
 341 +extern int spi_bitbang_transfer_sync(struct spi_device *spi,
 342 +                                     struct spi_message *m);
 343
 344  /* start or stop queue processing */
 345  extern int spi_bitbang_start(struct spi_bitbang *spi);
 346 --- a/include/linux/spi/spi.h
 347 +++ b/include/linux/spi/spi.h
 348 @@ -204,7 +204,6 @@ static inline void spi_unregister_driver
 349   *     SPI slaves, and are numbered from zero to num_chipselects.
 350   *     each slave has a chipselect signal, but it's common that not
 351   *     every chipselect is connected to a slave.
 352 - * @dma_alignment: SPI controller constraint on DMA buffers alignment.
 353   * @setup: updates the device mode and clocking records used by a
 354   *     device's SPI controller; protocol code may call this.  This
 355   *     must fail if an unrecognized or unsupported mode is requested.
 356 @@ -240,17 +239,7 @@ struct spi_master {
 357          */
 358         u16                     num_chipselect;
 359
 360 -       /* some SPI controllers pose alignment requirements on DMAable
 361 -        * buffers; let protocol drivers know about these requirements.
 362 -        */
 363 -       u16                     dma_alignment;
 364 -
 365 -       /* Setup mode and clock, etc (spi driver may call many times).
 366 -        *
 367 -        * IMPORTANT:  this may be called when transfers to another
 368 -        * device are active.  DO NOT UPDATE SHARED REGISTERS in ways
 369 -        * which could break those transfers.
 370 -        */
 371 +       /* setup mode and clock, etc (spi driver may call many times) */
 372         int                     (*setup)(struct spi_device *spi);
 373
 374         /* bidirectional bulk transfers
 375 @@ -275,6 +264,13 @@ struct spi_master {
 376         int                     (*transfer)(struct spi_device *spi,
 377                                                 struct spi_message *mesg);
 378
 379 +       /*
 380 +        * Synchronous non blocking transfer function. Should guarantee
 381 +        * data availability when it returns
 382 +        */
 383 +       int                     (*transfer_sync)(struct spi_device *spi,
 384 +                                               struct spi_message *mesg);
 385 +
 386         /* called on release() to free memory provided by spi_master */
 387         void                    (*cleanup)(struct spi_device *spi);
 388  };
 389 @@ -584,6 +580,29 @@ spi_async(struct spi_device *spi, struct
 390         return spi->master->transfer(spi, message);
 391  }
 392
 393 +/**
 394 + * spi_non_blocking_transfer - Synchronous, non blocking transfer
 395 + * @spi: device with which data will be exchanged
 396 + * @message: describes the data transfers with optional completion handlers
 397 + * Context: any (irqs may be blocked, etc)
 398 + *
 399 + * Data is guaranteed to be written or read when this function returns.
 400 + *
 401 + * Note : This may not be supported by all spi masters.
 402 + */
 403 +
 404 +static inline int
 405 +spi_non_blocking_transfer(struct spi_device *spi, struct spi_message *message)
 406 +{
 407 +       if (unlikely(!spi->master->transfer_sync)) {
 408 +               dev_err(&spi->master->dev,
 409 +                               "non-blocking transfers not supported\n");
 410 +               return -EIO;
 411 +       }
 412 +
 413 +       return spi->master->transfer_sync(spi, message);
 414 +}
 415 +
 416  /*---------------------------------------------------------------------------*/
 417
 418  /* All these synchronous SPI transfer routines are utilities layered