target/linux/aruba-2.6/patches/002-irq.patch

   1 diff -Nur linux-2.6.17/arch/mips/aruba/irq.c linux-2.6.17-openwrt/arch/mips/aruba/irq.c
   2 --- linux-2.6.17/arch/mips/aruba/irq.c  1970-01-01 01:00:00.000000000 +0100
   3 +++ linux-2.6.17-openwrt/arch/mips/aruba/irq.c  2006-10-12 14:32:40.026285000 -0700
   4 @@ -0,0 +1,285 @@
   5 +#include <linux/errno.h>
   6 +#include <linux/init.h>
   7 +#include <linux/kernel_stat.h>
   8 +#include <linux/module.h>
   9 +#include <linux/signal.h>
  10 +#include <linux/sched.h>
  11 +#include <linux/types.h>
  12 +#include <linux/interrupt.h>
  13 +#include <linux/ioport.h>
  14 +#include <linux/timex.h>
  15 +#include <linux/slab.h>
  16 +#include <linux/random.h>
  17 +#include <linux/delay.h>
  18 +
  19 +#include <asm/bitops.h>
  20 +#include <asm/bootinfo.h>
  21 +#include <asm/io.h>
  22 +#include <asm/mipsregs.h>
  23 +#include <asm/system.h>
  24 +#include <asm/idt-boards/rc32434/rc32434.h>
  25 +#include <asm/idt-boards/rc32434/rc32434_gpio.h>
  26 +
  27 +#include <asm/irq.h>
  28 +
  29 +extern void aruba_timer_interrupt(struct pt_regs *regs);
  30 +
  31 +typedef struct {
  32 +       u32 mask;
  33 +       volatile u32 *base_addr;
  34 +} intr_group_t;
  35 +
  36 +static const intr_group_t intr_group_merlot[NUM_INTR_GROUPS] = {
  37 +       {0x00000000, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0)},
  38 +};
  39 +
  40 +#define READ_PEND_MERLOT(base) (*((volatile unsigned long *)(0xbc003010)))
  41 +#define READ_MASK_MERLOT(base) (*((volatile unsigned long *)(0xbc003014)))
  42 +#define WRITE_MASK_MERLOT(base, val) ((*((volatile unsigned long *)(0xbc003014))) = (val), READ_MASK_MERLOT())
  43 +
  44 +static const intr_group_t intr_group_muscat[NUM_INTR_GROUPS] = {
  45 +       {0x0000efff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
  46 +       {0x00001fff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)},
  47 +       {0x00000007, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)},
  48 +       {0x0003ffff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)},
  49 +       {0xffffffff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
  50 +};
  51 +
  52 +#define READ_PEND_MUSCAT(base) (*(base))
  53 +#define READ_MASK_MUSCAT(base) (*(base + 2))
  54 +#define WRITE_MASK_MUSCAT(base, val) (*(base + 2) = (val))
  55 +
  56 +static inline int group_to_ip(unsigned int group)
  57 +{
  58 +       switch (mips_machtype) {
  59 +               case MACH_ARUBA_AP70:
  60 +                       return group + 2;
  61 +               case MACH_ARUBA_AP65:
  62 +               case MACH_ARUBA_AP60:
  63 +               default:
  64 +                       return 6;
  65 +       }
  66 +}
  67 +
  68 +static inline void enable_local_irq(unsigned int irq)
  69 +{
  70 +       clear_c0_cause(0x100 << irq);
  71 +       set_c0_status(0x100 << irq);
  72 +       irq_enable_hazard();
  73 +}
  74 +
  75 +static inline void disable_local_irq(unsigned int irq)
  76 +{
  77 +       clear_c0_status(0x100 << irq);
  78 +       clear_c0_cause(0x100 << irq);
  79 +       irq_disable_hazard();
  80 +}
  81 +
  82 +static inline void aruba_irq_enable(unsigned int irq)
  83 +{
  84 +       unsigned long flags;
  85 +       unsigned int  group, intr_bit;
  86 +       volatile unsigned int  *addr;
  87 +
  88 +       local_irq_save(flags);
  89 +
  90 +       if (irq < GROUP0_IRQ_BASE) {
  91 +               enable_local_irq(irq);
  92 +       } else {
  93 +               int ip = irq - GROUP0_IRQ_BASE;
  94 +               switch (mips_machtype) {
  95 +                       case MACH_ARUBA_AP70:
  96 +                               if (irq >= GROUP4_IRQ_BASE)
  97 +                                       idt_gpio->gpioistat &= ~(1 << (irq - GROUP4_IRQ_BASE));
  98 +
  99 +                               // irqs are in groups of 32
 100 +                               // ip is set to the remainder
 101 +                               group = ip >> 5;
 102 +                               ip &= 0x1f;
 103 +
 104 +                               // bit -> 0 = unmask
 105 +                               intr_bit = 1 << ip;
 106 +                               addr = intr_group_muscat[group].base_addr;
 107 +                               WRITE_MASK_MUSCAT(addr, READ_MASK_MUSCAT(addr) & ~intr_bit);
 108 +                               break;
 109 +
 110 +                       case MACH_ARUBA_AP65:
 111 +                       case MACH_ARUBA_AP60:
 112 +                               group = 0;
 113 +
 114 +                               // bit -> 1 = unmasked
 115 +                               intr_bit = 1 << ip;
 116 +                               addr = intr_group_merlot[group].base_addr;
 117 +                               WRITE_MASK_MERLOT(addr, READ_MASK_MERLOT(addr) | intr_bit);
 118 +                               break;
 119 +               }
 120 +               enable_local_irq(group_to_ip(group));
 121 +       }
 122 +
 123 +       back_to_back_c0_hazard();
 124 +       local_irq_restore(flags);
 125 +}
 126 +
 127 +static void aruba_irq_disable(unsigned int irq)
 128 +{
 129 +       unsigned long flags;
 130 +       unsigned int  group, intr_bit, mask;
 131 +       volatile unsigned int  *addr;
 132 +
 133 +       local_irq_save(flags);
 134 +
 135 +       if (irq < GROUP0_IRQ_BASE) {
 136 +               disable_local_irq(irq);
 137 +       } else {
 138 +               int ip = irq - GROUP0_IRQ_BASE;
 139 +               switch (mips_machtype) {
 140 +                       case MACH_ARUBA_AP70:
 141 +                               idt_gpio->gpioistat &= ~(1 << ip);
 142 +
 143 +                               // irqs are in groups of 32
 144 +                               // ip is set to the remainder
 145 +                               group = ip >> 5;
 146 +                               ip &= 0x1f;
 147 +
 148 +                               // bit -> 1 = mask
 149 +                               intr_bit = 1 << ip;
 150 +                               addr = intr_group_muscat[group].base_addr;
 151 +
 152 +                               mask = READ_MASK_MUSCAT(addr);
 153 +                               mask |= intr_bit;
 154 +                               WRITE_MASK_MUSCAT(addr, mask);
 155 +
 156 +                               if (mask == intr_group_muscat[group].mask) {
 157 +                                       disable_local_irq(group_to_ip(group));
 158 +                               }
 159 +                               break;
 160 +
 161 +                       case MACH_ARUBA_AP65:
 162 +                       case MACH_ARUBA_AP60:
 163 +                               group = 0;
 164 +
 165 +                               // bit -> 0 = masked
 166 +                               intr_bit = 1 << ip;
 167 +                               addr = intr_group_merlot[group].base_addr;
 168 +
 169 +                               mask = READ_MASK_MERLOT(addr);
 170 +                               mask &= ~intr_bit;
 171 +                               WRITE_MASK_MERLOT(addr, mask);
 172 +
 173 +                               if (mask == intr_group_merlot[group].mask) {
 174 +                                       disable_local_irq(group_to_ip(group));
 175 +                               }
 176 +                               break;
 177 +               }
 178 +       }
 179 +
 180 +       back_to_back_c0_hazard();
 181 +       local_irq_restore(flags);
 182 +}
 183 +
 184 +static unsigned int aruba_irq_startup(unsigned int irq)
 185 +{
 186 +       aruba_irq_enable(irq);
 187 +       return 0;
 188 +}
 189 +
 190 +#define aruba_irq_shutdown aruba_irq_disable
 191 +
 192 +static void aruba_irq_ack(unsigned int irq)
 193 +{
 194 +       aruba_irq_disable(irq);
 195 +}
 196 +
 197 +static void aruba_irq_end(unsigned int irq)
 198 +{
 199 +       if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 200 +               aruba_irq_enable(irq);
 201 +}
 202 +
 203 +static struct hw_interrupt_type aruba_irq_type = {
 204 +       .typename       = "ARUBA",
 205 +       .startup        = aruba_irq_startup,
 206 +       .shutdown       = aruba_irq_shutdown,
 207 +       .enable         = aruba_irq_enable,
 208 +       .disable        = aruba_irq_disable,
 209 +       .ack            = aruba_irq_ack,
 210 +       .end            = aruba_irq_end,
 211 +};
 212 +
 213 +void __init arch_init_irq(void)
 214 +{
 215 +       int i;
 216 +       printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
 217 +       memset(irq_desc, 0, sizeof(irq_desc));
 218 +
 219 +       for (i = 0; i < RC32434_NR_IRQS; i++) {
 220 +               irq_desc[i].status = IRQ_DISABLED;
 221 +               irq_desc[i].action = NULL;
 222 +               irq_desc[i].depth = 1;
 223 +               irq_desc[i].chip = &aruba_irq_type;
 224 +               spin_lock_init(&irq_desc[i].lock);
 225 +       }
 226 +}
 227 +
 228 +/* Main Interrupt dispatcher */
 229 +
 230 +void plat_irq_dispatch(struct pt_regs *regs)
 231 +{
 232 +       unsigned int pend, group, ip;
 233 +       volatile unsigned int *addr;
 234 +       unsigned long cp0_cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
 235 +
 236 +       if (cp0_cause & CAUSEF_IP7)
 237 +               return aruba_timer_interrupt(regs);
 238 +
 239 +       if(cp0_cause == 0) {
 240 +               printk("INTERRUPT(S) FIRED WHILE MASKED\n");
 241 +#ifdef ARUBA_DEBUG
 242 +               // debuging use -- figure out which interrupt(s) fired
 243 +               cp0_cause = read_c0_cause() & CAUSEF_IP;
 244 +               while (cp0_cause) {
 245 +                       unsigned long intr_bit;
 246 +                       unsigned int irq_nr;
 247 +                       intr_bit = (31 - rc32434_clz(cp0_cause));
 248 +                       irq_nr = intr_bit - GROUP0_IRQ_BASE;
 249 +                       printk(" ---> MASKED IRQ %d\n",irq_nr);
 250 +                       cp0_cause &= ~(1 << intr_bit);
 251 +               }
 252 +#endif
 253 +               return;
 254 +       }
 255 +
 256 +       switch (mips_machtype) {
 257 +               case MACH_ARUBA_AP70:
 258 +                       if ((ip = (cp0_cause & 0x7c00))) {
 259 +                               group = 21 - rc32434_clz(ip);
 260 +
 261 +                               addr = intr_group_muscat[group].base_addr;
 262 +
 263 +                               pend = READ_PEND_MUSCAT(addr);
 264 +                               pend &= ~READ_MASK_MUSCAT(addr); // only unmasked interrupts
 265 +                               pend = 39 - rc32434_clz(pend);
 266 +                               do_IRQ(pend + (group << 5));
 267 +                       }
 268 +                       break;
 269 +               case MACH_ARUBA_AP65:
 270 +               case MACH_ARUBA_AP60:
 271 +               default:
 272 +                       if (cp0_cause & 0x4000) { // 1 << (8 +6) == irq 6
 273 +                               // Misc Interrupt
 274 +                               group = 0;
 275 +
 276 +                               addr = intr_group_merlot[group].base_addr;
 277 +
 278 +                               pend = READ_PEND_MERLOT(addr);
 279 +                               pend &= READ_MASK_MERLOT(addr); // only unmasked interrupts
 280 +                               pend = 31 - rc32434_clz(pend);
 281 +                               do_IRQ(pend + GROUP0_IRQ_BASE);
 282 +                       }
 283 +                       if ((ip = (cp0_cause & 0x3c00))) { // irq 2-5
 284 +                               pend = 31 - rc32434_clz(ip);
 285 +                               do_IRQ(pend - GROUP0_IRQ_BASE);
 286 +                       }
 287 +                       break;
 288 +       }
 289 +}