target/linux/rb532/patches-2.6.27/001-git_diffs.patch

   1 diff -urN a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c
   2 --- a/arch/mips/rb532/devices.c 2008-11-07 18:55:34.000000000 +0100
   3 +++ b/arch/mips/rb532/devices.c 2008-11-15 17:43:28.000000000 +0100
   4 @@ -34,21 +34,11 @@
   5  #include <asm/mach-rc32434/rb.h>
   6  #include <asm/mach-rc32434/integ.h>
   7  #include <asm/mach-rc32434/gpio.h>
   8 -
   9 -#define ETH0_DMA_RX_IRQ        (GROUP1_IRQ_BASE + 0)
  10 -#define ETH0_DMA_TX_IRQ        (GROUP1_IRQ_BASE + 1)
  11 -#define ETH0_RX_OVR_IRQ        (GROUP3_IRQ_BASE + 9)
  12 -#define ETH0_TX_UND_IRQ        (GROUP3_IRQ_BASE + 10)
  13 +#include <asm/mach-rc32434/irq.h>
  14
  15  #define ETH0_RX_DMA_ADDR  (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
  16  #define ETH0_TX_DMA_ADDR  (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
  17
  18 -/* NAND definitions */
  19 -#define GPIO_RDY (1 << 0x08)
  20 -#define GPIO_WPX (1 << 0x09)
  21 -#define GPIO_ALE (1 << 0x0a)
  22 -#define GPIO_CLE (1 << 0x0b)
  23 -
  24  static struct resource korina_dev0_res[] = {
  25         {
  26                 .name = "korina_regs",
  27 @@ -94,15 +84,13 @@
  28  };
  29
  30  static struct platform_device korina_dev0 = {
  31 -       .id = 0,
  32 +       .id = -1,
  33         .name = "korina",
  34         .dev.platform_data = &korina_dev0_data,
  35         .resource = korina_dev0_res,
  36         .num_resources = ARRAY_SIZE(korina_dev0_res),
  37  };
  38
  39 -#define CF_GPIO_NUM 13
  40 -
  41  static struct resource cf_slot0_res[] = {
  42         {
  43                 .name = "cf_membase",
  44 @@ -116,11 +104,11 @@
  45  };
  46
  47  static struct cf_device cf_slot0_data = {
  48 -       .gpio_pin = 13
  49 +       .gpio_pin = CF_GPIO_NUM
  50  };
  51
  52  static struct platform_device cf_slot0 = {
  53 -       .id = 0,
  54 +       .id = -1,
  55         .name = "pata-rb532-cf",
  56         .dev.platform_data = &cf_slot0_data,
  57         .resource = cf_slot0_res,
  58 @@ -130,7 +118,7 @@
  59  /* Resources and device for NAND */
  60  static int rb532_dev_ready(struct mtd_info *mtd)
  61  {
  62 -       return readl(IDT434_REG_BASE + GPIOD) & GPIO_RDY;
  63 +       return gpio_get_value(GPIO_RDY);
  64  }
  65
  66  static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  67 @@ -185,7 +173,7 @@
  68
  69  static struct platform_device rb532_led = {
  70         .name = "rb532-led",
  71 -       .id = 0,
  72 +       .id = -1,
  73  };
  74
  75  static struct gpio_keys_button rb532_gpio_btn[] = {
  76 @@ -292,7 +280,7 @@
  77  {
  78         /* Look for the CF card reader */
  79         if (!readl(IDT434_REG_BASE + DEV1MASK))
  80 -               rb532_devs[1] = NULL;
  81 +               rb532_devs[2] = NULL;   /* disable cf_slot0 at index 2 */
  82         else {
  83                 cf_slot0_res[0].start =
  84                     readl(IDT434_REG_BASE + DEV1BASE);
  85 diff -urN a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c
  86 --- a/arch/mips/rb532/gpio.c    2008-11-07 18:55:34.000000000 +0100
  87 +++ b/arch/mips/rb532/gpio.c    2008-11-15 17:43:28.000000000 +0100
  88 @@ -27,28 +27,27 @@
  89   */
  90
  91  #include <linux/kernel.h>
  92 -#include <linux/gpio.h>
  93  #include <linux/init.h>
  94  #include <linux/types.h>
  95 -#include <linux/pci.h>
  96  #include <linux/spinlock.h>
  97 -#include <linux/io.h>
  98  #include <linux/platform_device.h>
  99 -
 100 -#include <asm/addrspace.h>
 101 +#include <linux/gpio.h>
 102
 103  #include <asm/mach-rc32434/rb.h>
 104 +#include <asm/mach-rc32434/gpio.h>
 105
 106 -struct rb532_gpio_reg __iomem *rb532_gpio_reg0;
 107 -EXPORT_SYMBOL(rb532_gpio_reg0);
 108 +struct rb532_gpio_chip {
 109 +       struct gpio_chip chip;
 110 +       void __iomem     *regbase;
 111 +};
 112
 113  struct mpmc_device dev3;
 114
 115  static struct resource rb532_gpio_reg0_res[] = {
 116         {
 117                 .name   = "gpio_reg0",
 118 -               .start  = (u32)(IDT434_REG_BASE + GPIOBASE),
 119 -               .end    = (u32)(IDT434_REG_BASE + GPIOBASE + sizeof(struct rb532_gpio_reg)),
 120 +               .start  = REGBASE + GPIOBASE,
 121 +               .end    = REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1,
 122                 .flags  = IORESOURCE_MEM,
 123         }
 124  };
 125 @@ -56,8 +55,8 @@
 126  static struct resource rb532_dev3_ctl_res[] = {
 127         {
 128                 .name   = "dev3_ctl",
 129 -               .start  = (u32)(IDT434_REG_BASE + DEV3BASE),
 130 -               .end    = (u32)(IDT434_REG_BASE + DEV3BASE + sizeof(struct dev_reg)),
 131 +               .start  = REGBASE + DEV3BASE,
 132 +               .end    = REGBASE + DEV3BASE + sizeof(struct dev_reg) - 1,
 133                 .flags  = IORESOURCE_MEM,
 134         }
 135  };
 136 @@ -70,7 +69,7 @@
 137
 138         spin_lock_irqsave(&dev3.lock, flags);
 139
 140 -       data = *(volatile unsigned *) (IDT434_REG_BASE + reg_offs);
 141 +       data = readl(IDT434_REG_BASE + reg_offs);
 142         for (i = 0; i != len; ++i) {
 143                 if (val & (1 << i))
 144                         data |= (1 << (i + bit));
 145 @@ -108,114 +107,166 @@
 146  }
 147  EXPORT_SYMBOL(get_latch_u5);
 148
 149 -int rb532_gpio_get_value(unsigned gpio)
 150 +/* rb532_set_bit - sanely set a bit
 151 + *
 152 + * bitval: new value for the bit
 153 + * offset: bit index in the 4 byte address range
 154 + * ioaddr: 4 byte aligned address being altered
 155 + */
 156 +static inline void rb532_set_bit(unsigned bitval,
 157 +               unsigned offset, void __iomem *ioaddr)
 158  {
 159 -       return readl(&rb532_gpio_reg0->gpiod) & (1 << gpio);
 160 -}
 161 -EXPORT_SYMBOL(rb532_gpio_get_value);
 162 +       unsigned long flags;
 163 +       u32 val;
 164
 165 -void rb532_gpio_set_value(unsigned gpio, int value)
 166 -{
 167 -       unsigned tmp;
 168 +       bitval = !!bitval;              /* map parameter to {0,1} */
 169 +
 170 +       local_irq_save(flags);
 171
 172 -       tmp = readl(&rb532_gpio_reg0->gpiod) & ~(1 << gpio);
 173 -       if (value)
 174 -               tmp |= 1 << gpio;
 175 +       val = readl(ioaddr);
 176 +       val &= ~( ~bitval << offset );   /* unset bit if bitval == 0 */
 177 +       val |=  (  bitval << offset );   /* set bit if bitval == 1 */
 178 +       writel(val, ioaddr);
 179
 180 -       writel(tmp, (void *)&rb532_gpio_reg0->gpiod);
 181 +       local_irq_restore(flags);
 182  }
 183 -EXPORT_SYMBOL(rb532_gpio_set_value);
 184
 185 -int rb532_gpio_direction_input(unsigned gpio)
 186 +/* rb532_get_bit - read a bit
 187 + *
 188 + * returns the boolean state of the bit, which may be > 1
 189 + */
 190 +static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr)
 191  {
 192 -       writel(readl(&rb532_gpio_reg0->gpiocfg) & ~(1 << gpio),
 193 -              (void *)&rb532_gpio_reg0->gpiocfg);
 194 -
 195 -       return 0;
 196 +       return (readl(ioaddr) & (1 << offset));
 197  }
 198 -EXPORT_SYMBOL(rb532_gpio_direction_input);
 199
 200 -int rb532_gpio_direction_output(unsigned gpio, int value)
 201 +/*
 202 + * Return GPIO level */
 203 +static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset)
 204  {
 205 -       gpio_set_value(gpio, value);
 206 -       writel(readl(&rb532_gpio_reg0->gpiocfg) | (1 << gpio),
 207 -              (void *)&rb532_gpio_reg0->gpiocfg);
 208 +       struct rb532_gpio_chip  *gpch;
 209
 210 -       return 0;
 211 +       gpch = container_of(chip, struct rb532_gpio_chip, chip);
 212 +       return rb532_get_bit(offset, gpch->regbase + GPIOD);
 213  }
 214 -EXPORT_SYMBOL(rb532_gpio_direction_output);
 215
 216 -void rb532_gpio_set_int_level(unsigned gpio, int value)
 217 +/*
 218 + * Set output GPIO level
 219 + */
 220 +static void rb532_gpio_set(struct gpio_chip *chip,
 221 +                               unsigned offset, int value)
 222  {
 223 -       unsigned tmp;
 224 +       struct rb532_gpio_chip  *gpch;
 225
 226 -       tmp = readl(&rb532_gpio_reg0->gpioilevel) & ~(1 << gpio);
 227 -       if (value)
 228 -               tmp |= 1 << gpio;
 229 -       writel(tmp, (void *)&rb532_gpio_reg0->gpioilevel);
 230 +       gpch = container_of(chip, struct rb532_gpio_chip, chip);
 231 +       rb532_set_bit(value, offset, gpch->regbase + GPIOD);
 232  }
 233 -EXPORT_SYMBOL(rb532_gpio_set_int_level);
 234
 235 -int rb532_gpio_get_int_level(unsigned gpio)
 236 +/*
 237 + * Set GPIO direction to input
 238 + */
 239 +static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 240  {
 241 -       return readl(&rb532_gpio_reg0->gpioilevel) & (1 << gpio);
 242 +       struct rb532_gpio_chip  *gpch;
 243 +
 244 +       gpch = container_of(chip, struct rb532_gpio_chip, chip);
 245 +
 246 +       if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC))
 247 +               return 1;       /* alternate function, GPIOCFG is ignored */
 248 +
 249 +       rb532_set_bit(0, offset, gpch->regbase + GPIOCFG);
 250 +       return 0;
 251  }
 252 -EXPORT_SYMBOL(rb532_gpio_get_int_level);
 253
 254 -void rb532_gpio_set_int_status(unsigned gpio, int value)
 255 +/*
 256 + * Set GPIO direction to output
 257 + */
 258 +static int rb532_gpio_direction_output(struct gpio_chip *chip,
 259 +                                       unsigned offset, int value)
 260  {
 261 -       unsigned tmp;
 262 +       struct rb532_gpio_chip  *gpch;
 263 +
 264 +       gpch = container_of(chip, struct rb532_gpio_chip, chip);
 265
 266 -       tmp = readl(&rb532_gpio_reg0->gpioistat);
 267 -       if (value)
 268 -               tmp |= 1 << gpio;
 269 -       writel(tmp, (void *)&rb532_gpio_reg0->gpioistat);
 270 +       if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC))
 271 +               return 1;       /* alternate function, GPIOCFG is ignored */
 272 +
 273 +       /* set the initial output value */
 274 +       rb532_set_bit(value, offset, gpch->regbase + GPIOD);
 275 +
 276 +       rb532_set_bit(1, offset, gpch->regbase + GPIOCFG);
 277 +       return 0;
 278  }
 279 -EXPORT_SYMBOL(rb532_gpio_set_int_status);
 280
 281 -int rb532_gpio_get_int_status(unsigned gpio)
 282 +static struct rb532_gpio_chip rb532_gpio_chip[] = {
 283 +       [0] = {
 284 +               .chip = {
 285 +                       .label                  = "gpio0",
 286 +                       .direction_input        = rb532_gpio_direction_input,
 287 +                       .direction_output       = rb532_gpio_direction_output,
 288 +                       .get                    = rb532_gpio_get,
 289 +                       .set                    = rb532_gpio_set,
 290 +                       .base                   = 0,
 291 +                       .ngpio                  = 32,
 292 +               },
 293 +       },
 294 +};
 295 +
 296 +/*
 297 + * Set GPIO interrupt level
 298 + */
 299 +void rb532_gpio_set_ilevel(int bit, unsigned gpio)
 300  {
 301 -       return readl(&rb532_gpio_reg0->gpioistat) & (1 << gpio);
 302 +       rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL);
 303  }
 304 -EXPORT_SYMBOL(rb532_gpio_get_int_status);
 305 +EXPORT_SYMBOL(rb532_gpio_set_ilevel);
 306
 307 -void rb532_gpio_set_func(unsigned gpio, int value)
 308 +/*
 309 + * Set GPIO interrupt status
 310 + */
 311 +void rb532_gpio_set_istat(int bit, unsigned gpio)
 312  {
 313 -       unsigned tmp;
 314 -
 315 -       tmp = readl(&rb532_gpio_reg0->gpiofunc);
 316 -       if (value)
 317 -               tmp |= 1 << gpio;
 318 -       writel(tmp, (void *)&rb532_gpio_reg0->gpiofunc);
 319 +       rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT);
 320  }
 321 -EXPORT_SYMBOL(rb532_gpio_set_func);
 322 +EXPORT_SYMBOL(rb532_gpio_set_istat);
 323
 324 -int rb532_gpio_get_func(unsigned gpio)
 325 +/*
 326 + * Configure GPIO alternate function
 327 + */
 328 +static void rb532_gpio_set_func(int bit, unsigned gpio)
 329  {
 330 -       return readl(&rb532_gpio_reg0->gpiofunc) & (1 << gpio);
 331 +       rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOFUNC);
 332  }
 333 -EXPORT_SYMBOL(rb532_gpio_get_func);
 334
 335  int __init rb532_gpio_init(void)
 336  {
 337 -       rb532_gpio_reg0 = ioremap_nocache(rb532_gpio_reg0_res[0].start,
 338 -                               rb532_gpio_reg0_res[0].end -
 339 -                               rb532_gpio_reg0_res[0].start);
 340 +       struct resource *r;
 341 +
 342 +       r = rb532_gpio_reg0_res;
 343 +       rb532_gpio_chip->regbase = ioremap_nocache(r->start, r->end - r->start);
 344
 345 -       if (!rb532_gpio_reg0) {
 346 +       if (!rb532_gpio_chip->regbase) {
 347                 printk(KERN_ERR "rb532: cannot remap GPIO register 0\n");
 348                 return -ENXIO;
 349         }
 350
 351 -       dev3.base = ioremap_nocache(rb532_dev3_ctl_res[0].start,
 352 -                               rb532_dev3_ctl_res[0].end -
 353 -                               rb532_dev3_ctl_res[0].start);
 354 +       /* Register our GPIO chip */
 355 +       gpiochip_add(&rb532_gpio_chip->chip);
 356 +
 357 +       r = rb532_dev3_ctl_res;
 358 +       dev3.base = ioremap_nocache(r->start, r->end - r->start);
 359
 360         if (!dev3.base) {
 361                 printk(KERN_ERR "rb532: cannot remap device controller 3\n");
 362                 return -ENXIO;
 363         }
 364
 365 +       /* configure CF_GPIO_NUM as CFRDY IRQ source */
 366 +       rb532_gpio_set_func(0, CF_GPIO_NUM);
 367 +       rb532_gpio_direction_input(&rb532_gpio_chip->chip, CF_GPIO_NUM);
 368 +       rb532_gpio_set_ilevel(1, CF_GPIO_NUM);
 369 +       rb532_gpio_set_istat(0, CF_GPIO_NUM);
 370 +
 371         return 0;
 372  }
 373  arch_initcall(rb532_gpio_init);
 374 diff -urN a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c
 375 --- a/arch/mips/rb532/irq.c     2008-11-07 18:55:34.000000000 +0100
 376 +++ b/arch/mips/rb532/irq.c     2008-11-15 17:43:28.000000000 +0100
 377 @@ -45,7 +45,7 @@
 378  #include <asm/mipsregs.h>
 379  #include <asm/system.h>
 380
 381 -#include <asm/mach-rc32434/rc32434.h>
 382 +#include <asm/mach-rc32434/irq.h>
 383
 384  struct intr_group {
 385         u32 mask;       /* mask of valid bits in pending/mask registers */
 386 diff -urN a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c
 387 --- a/arch/mips/rb532/prom.c    2008-11-07 18:55:34.000000000 +0100
 388 +++ b/arch/mips/rb532/prom.c    2008-11-15 17:43:28.000000000 +0100
 389 @@ -37,12 +37,8 @@
 390  #include <asm/mach-rc32434/ddr.h>
 391  #include <asm/mach-rc32434/prom.h>
 392
 393 -extern void __init setup_serial_port(void);
 394 -
 395  unsigned int idt_cpu_freq = 132000000;
 396  EXPORT_SYMBOL(idt_cpu_freq);
 397 -unsigned int gpio_bootup_state;
 398 -EXPORT_SYMBOL(gpio_bootup_state);
 399
 400  static struct resource ddr_reg[] = {
 401         {
 402 @@ -108,9 +104,6 @@
 403                                 mips_machtype = MACH_MIKROTIK_RB532;
 404                 }
 405
 406 -               if (match_tag(prom_argv[i], GPIO_TAG))
 407 -                       gpio_bootup_state = tag2ul(prom_argv[i], GPIO_TAG);
 408 -
 409                 strcpy(cp, prom_argv[i]);
 410                 cp += strlen(prom_argv[i]);
 411         }
 412 @@ -122,11 +115,6 @@
 413                 strcpy(cp, arcs_cmdline);
 414                 cp += strlen(arcs_cmdline);
 415         }
 416 -       if (gpio_bootup_state & 0x02)
 417 -               strcpy(cp, GPIO_INIT_NOBUTTON);
 418 -       else
 419 -               strcpy(cp, GPIO_INIT_BUTTON);
 420 -
 421         cmd_line[CL_SIZE-1] = '\0';
 422
 423         strcpy(arcs_cmdline, cmd_line);
 424 diff -urN a/arch/mips/rb532/serial.c b/arch/mips/rb532/serial.c
 425 --- a/arch/mips/rb532/serial.c  2008-11-07 18:55:34.000000000 +0100
 426 +++ b/arch/mips/rb532/serial.c  2008-11-15 17:43:28.000000000 +0100
 427 @@ -31,16 +31,16 @@
 428  #include <linux/serial_8250.h>
 429
 430  #include <asm/serial.h>
 431 -#include <asm/mach-rc32434/rc32434.h>
 432 +#include <asm/mach-rc32434/rb.h>
 433
 434  extern unsigned int idt_cpu_freq;
 435
 436  static struct uart_port rb532_uart = {
 437         .type = PORT_16550A,
 438         .line = 0,
 439 -       .irq = RC32434_UART0_IRQ,
 440 +       .irq = UART0_IRQ,
 441         .iotype = UPIO_MEM,
 442 -       .membase = (char *)KSEG1ADDR(RC32434_UART0_BASE),
 443 +       .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
 444         .regshift = 2
 445  };
 446
 447 diff -urN a/arch/mips/rb532/setup.c b/arch/mips/rb532/setup.c
 448 --- a/arch/mips/rb532/setup.c   2008-11-07 18:55:34.000000000 +0100
 449 +++ b/arch/mips/rb532/setup.c   2008-11-15 17:43:28.000000000 +0100
 450 @@ -9,7 +9,7 @@
 451  #include <asm/time.h>
 452  #include <linux/ioport.h>
 453
 454 -#include <asm/mach-rc32434/rc32434.h>
 455 +#include <asm/mach-rc32434/rb.h>
 456  #include <asm/mach-rc32434/pci.h>
 457
 458  struct pci_reg __iomem *pci_reg;
 459 @@ -27,7 +27,7 @@
 460  static void rb_machine_restart(char *command)
 461  {
 462         /* just jump to the reset vector */
 463 -       writel(0x80000001, (void *)KSEG1ADDR(RC32434_REG_BASE + RC32434_RST));
 464 +       writel(0x80000001, IDT434_REG_BASE + RST);
 465         ((void (*)(void)) KSEG1ADDR(0x1FC00000u))();
 466  }
 467
 468 diff -urN a/arch/mips/rb532/time.c b/arch/mips/rb532/time.c
 469 --- a/arch/mips/rb532/time.c    2008-11-07 18:55:34.000000000 +0100
 470 +++ b/arch/mips/rb532/time.c    2008-11-15 17:43:28.000000000 +0100
 471 @@ -28,7 +28,6 @@
 472  #include <linux/timex.h>
 473
 474  #include <asm/mipsregs.h>
 475 -#include <asm/debug.h>
 476  #include <asm/time.h>
 477  #include <asm/mach-rc32434/rc32434.h>
 478
 479 diff -urN linux-2.6.27.5/arch/mips/Kconfig linux-2.6.27.5.new/arch/mips/Kconfig
 480 --- linux-2.6.27.5/arch/mips/Kconfig    2008-11-07 18:55:34.000000000 +0100
 481 +++ linux-2.6.27.5.new/arch/mips/Kconfig        2008-11-15 17:50:42.000000000 +0100
 482 @@ -568,7 +568,7 @@
 483         select SYS_SUPPORTS_LITTLE_ENDIAN
 484         select SWAP_IO_SPACE
 485         select BOOT_RAW
 486 -       select GENERIC_GPIO
 487 +       select ARCH_REQUIRE_GPIOLIB
 488         help
 489           Support the Mikrotik(tm) RouterBoard 532 series,
 490           based on the IDT RC32434 SoC.
 491 diff -urN a/include/asm-mips/mach-rc32434/gpio.h b/include-mips/asm/mach-rc32434/gpio.h
 492 --- a/include/asm-mips/mach-rc32434/gpio.h      2008-11-07 18:55:34.000000000 +0100
 493 +++ b/include/asm-mips/mach-rc32434/gpio.h      2008-11-15 17:43:28.000000000 +0100
 494 @@ -14,6 +14,16 @@
 495  #define _RC32434_GPIO_H_
 496
 497  #include <linux/types.h>
 498 +#include <asm-generic/gpio.h>
 499 +
 500 +#define NR_BUILTIN_GPIO                32
 501 +
 502 +#define gpio_get_value __gpio_get_value
 503 +#define gpio_set_value __gpio_set_value
 504 +#define gpio_cansleep  __gpio_cansleep
 505 +
 506 +#define gpio_to_irq(gpio)      (8 + 4 * 32 + gpio)
 507 +#define irq_to_gpio(irq)       (irq - (8 + 4 * 32))
 508
 509  struct rb532_gpio_reg {
 510         u32   gpiofunc;   /* GPIO Function Register
 511 @@ -61,66 +71,20 @@
 512  /* PCI messaging unit */
 513  #define RC32434_PCI_MSU_GPIO   (1 << 13)
 514
 515 +/* NAND GPIO signals */
 516 +#define GPIO_RDY               8
 517 +#define GPIO_WPX       9
 518 +#define GPIO_ALE               10
 519 +#define GPIO_CLE               11
 520 +
 521 +/* Compact Flash GPIO pin */
 522 +#define CF_GPIO_NUM            13
 523
 524  extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val);
 525  extern unsigned get_434_reg(unsigned reg_offs);
 526  extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
 527  extern unsigned char get_latch_u5(void);
 528 -
 529 -extern int rb532_gpio_get_value(unsigned gpio);
 530 -extern void rb532_gpio_set_value(unsigned gpio, int value);
 531 -extern int rb532_gpio_direction_input(unsigned gpio);
 532 -extern int rb532_gpio_direction_output(unsigned gpio, int value);
 533 -extern void rb532_gpio_set_int_level(unsigned gpio, int value);
 534 -extern int rb532_gpio_get_int_level(unsigned gpio);
 535 -extern void rb532_gpio_set_int_status(unsigned gpio, int value);
 536 -extern int rb532_gpio_get_int_status(unsigned gpio);
 537 -
 538 -
 539 -/* Wrappers for the arch-neutral GPIO API */
 540 -
 541 -static inline int gpio_request(unsigned gpio, const char *label)
 542 -{
 543 -       /* Not yet implemented */
 544 -       return 0;
 545 -}
 546 -
 547 -static inline void gpio_free(unsigned gpio)
 548 -{
 549 -       /* Not yet implemented */
 550 -}
 551 -
 552 -static inline int gpio_direction_input(unsigned gpio)
 553 -{
 554 -       return rb532_gpio_direction_input(gpio);
 555 -}
 556 -
 557 -static inline int gpio_direction_output(unsigned gpio, int value)
 558 -{
 559 -       return rb532_gpio_direction_output(gpio, value);
 560 -}
 561 -
 562 -static inline int gpio_get_value(unsigned gpio)
 563 -{
 564 -       return rb532_gpio_get_value(gpio);
 565 -}
 566 -
 567 -static inline void gpio_set_value(unsigned gpio, int value)
 568 -{
 569 -       rb532_gpio_set_value(gpio, value);
 570 -}
 571 -
 572 -static inline int gpio_to_irq(unsigned gpio)
 573 -{
 574 -       return gpio;
 575 -}
 576 -
 577 -static inline int irq_to_gpio(unsigned irq)
 578 -{
 579 -       return irq;
 580 -}
 581 -
 582 -/* For cansleep */
 583 -#include <asm-generic/gpio.h>
 584 +extern void rb532_gpio_set_ilevel(int bit, unsigned gpio);
 585 +extern void rb532_gpio_set_istat(int bit, unsigned gpio);
 586
 587  #endif /* _RC32434_GPIO_H_ */
 588 diff -urN a/include/asm-mips/mach-rc32434/irq.h b/include/asm-mips/mach-rc32434/irq.h
 589 --- a/include/asm-mips/mach-rc32434/irq.h       2008-11-07 18:55:34.000000000 +0100
 590 +++ b/include/asm-mips/mach-rc32434/irq.h       2008-11-15 17:43:28.000000000 +0100
 591 @@ -4,5 +4,30 @@
 592  #define NR_IRQS        256
 593
 594  #include <asm/mach-generic/irq.h>
 595 +#include <asm/mach-rc32434/rb.h>
 596 +
 597 +/* Interrupt Controller */
 598 +#define IC_GROUP0_PEND         (REGBASE + 0x38000)
 599 +#define IC_GROUP0_MASK         (REGBASE + 0x38008)
 600 +#define IC_GROUP_OFFSET                0x0C
 601 +
 602 +#define NUM_INTR_GROUPS                5
 603 +
 604 +/* 16550 UARTs */
 605 +#define GROUP0_IRQ_BASE                8       /* GRP2 IRQ numbers start here */
 606 +                                       /* GRP3 IRQ numbers start here */
 607 +#define GROUP1_IRQ_BASE                (GROUP0_IRQ_BASE + 32)
 608 +                                       /* GRP4 IRQ numbers start here */
 609 +#define GROUP2_IRQ_BASE                (GROUP1_IRQ_BASE + 32)
 610 +                                       /* GRP5 IRQ numbers start here */
 611 +#define GROUP3_IRQ_BASE                (GROUP2_IRQ_BASE + 32)
 612 +#define GROUP4_IRQ_BASE                (GROUP3_IRQ_BASE + 32)
 613 +
 614 +#define UART0_IRQ              (GROUP3_IRQ_BASE + 0)
 615 +
 616 +#define ETH0_DMA_RX_IRQ        (GROUP1_IRQ_BASE + 0)
 617 +#define ETH0_DMA_TX_IRQ        (GROUP1_IRQ_BASE + 1)
 618 +#define ETH0_RX_OVR_IRQ        (GROUP3_IRQ_BASE + 9)
 619 +#define ETH0_TX_UND_IRQ        (GROUP3_IRQ_BASE + 10)
 620
 621  #endif  /* __ASM_RC32434_IRQ_H */
 622 diff -urN a/include/asm-mips/mach-rc32434/prom.h b/include/asm-mips/mach-rc32434/prom.h
 623 --- a/include/asm-mips/mach-rc32434/prom.h      2008-11-07 18:55:34.000000000 +0100
 624 +++ b/include/asm-mips/mach-rc32434/prom.h      2008-11-15 17:43:28.000000000 +0100
 625 @@ -28,14 +28,10 @@
 626
 627  #define PROM_ENTRY(x)          (0xbfc00000 + ((x) * 8))
 628
 629 -#define GPIO_INIT_NOBUTTON     ""
 630 -#define GPIO_INIT_BUTTON       " 2"
 631 -
 632  #define SR_NMI                 0x00180000
 633  #define SERIAL_SPEED_ENTRY     0x00000001
 634
 635  #define FREQ_TAG               "HZ="
 636 -#define GPIO_TAG               "gpio="
 637  #define KMAC_TAG               "kmac="
 638  #define MEM_TAG                        "mem="
 639  #define BOARD_TAG              "board="
 640 diff -urN a/include/asm-mips/mach-rc32434/rb.h b/include/asm-mips/mach-rc32434/rb.h
 641 --- a/include/asm-mips/mach-rc32434/rb.h        2008-11-07 18:55:34.000000000 +0100
 642 +++ b/include/asm-mips/mach-rc32434/rb.h        2008-11-15 17:43:28.000000000 +0100
 643 @@ -17,7 +17,10 @@
 644
 645  #include <linux/genhd.h>
 646
 647 -#define IDT434_REG_BASE        ((volatile void *) KSEG1ADDR(0x18000000))
 648 +#define REGBASE                0x18000000
 649 +#define IDT434_REG_BASE        ((volatile void *) KSEG1ADDR(REGBASE))
 650 +#define UART0BASE      0x58000
 651 +#define RST            (1 << 15)
 652  #define DEV0BASE       0x010000
 653  #define DEV0MASK       0x010004
 654  #define DEV0C          0x010008
 655 @@ -37,12 +40,14 @@
 656  #define BTCS           0x010040
 657  #define BTCOMPARE      0x010044
 658  #define GPIOBASE       0x050000
 659 -#define GPIOCFG                0x050004
 660 -#define GPIOD          0x050008
 661 -#define GPIOILEVEL     0x05000C
 662 -#define GPIOISTAT      0x050010
 663 -#define GPIONMIEN      0x050014
 664 -#define IMASK6         0x038038
 665 +/* Offsets relative to GPIOBASE */
 666 +#define GPIOFUNC       0x00
 667 +#define GPIOCFG                0x04
 668 +#define GPIOD          0x08
 669 +#define GPIOILEVEL     0x0C
 670 +#define GPIOISTAT      0x10
 671 +#define GPIONMIEN      0x14
 672 +#define IMASK6         0x38
 673  #define LO_WPX         (1 << 0)
 674  #define LO_ALE         (1 << 1)
 675  #define LO_CLE         (1 << 2)
 676 diff -urN a/include/asm-mips/mach-rc32434/rc32434.h b/include/asm-mips/mach-rc32434/rc32434.h
 677 --- a/include/asm-mips/mach-rc32434/rc32434.h   2008-11-07 18:55:34.000000000 +0100
 678 +++ b/include/asm-mips/mach-rc32434/rc32434.h   2008-11-15 17:43:28.000000000 +0100
 679 @@ -8,37 +8,7 @@
 680  #include <linux/delay.h>
 681  #include <linux/io.h>
 682
 683 -#define RC32434_REG_BASE       0x18000000
 684 -#define RC32434_RST            (1 << 15)
 685 -
 686  #define IDT_CLOCK_MULT         2
 687 -#define MIPS_CPU_TIMER_IRQ     7
 688 -
 689 -/* Interrupt Controller */
 690 -#define IC_GROUP0_PEND         (RC32434_REG_BASE + 0x38000)
 691 -#define IC_GROUP0_MASK         (RC32434_REG_BASE + 0x38008)
 692 -#define IC_GROUP_OFFSET                0x0C
 693 -
 694 -#define NUM_INTR_GROUPS                5
 695 -
 696 -/* 16550 UARTs */
 697 -#define GROUP0_IRQ_BASE                8       /* GRP2 IRQ numbers start here */
 698 -                                       /* GRP3 IRQ numbers start here */
 699 -#define GROUP1_IRQ_BASE                (GROUP0_IRQ_BASE + 32)
 700 -                                       /* GRP4 IRQ numbers start here */
 701 -#define GROUP2_IRQ_BASE                (GROUP1_IRQ_BASE + 32)
 702 -                                       /* GRP5 IRQ numbers start here */
 703 -#define GROUP3_IRQ_BASE                (GROUP2_IRQ_BASE + 32)
 704 -#define GROUP4_IRQ_BASE                (GROUP3_IRQ_BASE + 32)
 705 -
 706 -
 707 -#ifdef __MIPSEB__
 708 -#define RC32434_UART0_BASE     (RC32434_REG_BASE + 0x58003)
 709 -#else
 710 -#define RC32434_UART0_BASE     (RC32434_REG_BASE + 0x58000)
 711 -#endif
 712 -
 713 -#define RC32434_UART0_IRQ      (GROUP3_IRQ_BASE + 0)
 714
 715  /* cpu pipeline flush */
 716  static inline void rc32434_sync(void)
 717 @@ -46,16 +16,4 @@
 718         __asm__ volatile ("sync");
 719  }
 720
 721 -static inline void rc32434_sync_udelay(int us)
 722 -{
 723 -       __asm__ volatile ("sync");
 724 -       udelay(us);
 725 -}
 726 -
 727 -static inline void rc32434_sync_delay(int ms)
 728 -{
 729 -       __asm__ volatile ("sync");
 730 -       mdelay(ms);
 731 -}
 732 -
 733  #endif  /* _ASM_RC32434_RC32434_H_ */
 734 --- a/arch/mips/pci/fixup-rc32434.c     2008-11-07 18:55:34.000000000 +0100
 735 +++ b/arch/mips/pci/fixup-rc32434.c     2008-11-15 17:43:28.000000000 +0100
 736 @@ -30,6 +30,7 @@
 737  #include <linux/init.h>
 738
 739  #include <asm/mach-rc32434/rc32434.h>
 740 +#include <asm/mach-rc32434/irq.h>
 741
 742  static int __devinitdata irq_map[2][12] = {
 743         {0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1},