target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h

   1 /*
   2  *  Ralink RT305 SoC register definitions
   3  *
   4  *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms of the GNU General Public License version 2 as published
   8  *  by the Free Software Foundation.
   9  */
  10
  11 #ifndef _RT305X_REGS_H_
  12 #define _RT305X_REGS_H_
  13
  14 #include <linux/bitops.h>
  15
  16 #define RT305X_SDRAM_BASE       0x00000000
  17 #define RT305X_SYSC_BASE        0x10000000
  18 #define RT305X_TIMER_BASE       0x10000100
  19 #define RT305X_INTC_BASE        0x10000200
  20 #define RT305X_MEMC_BASE        0x10000300
  21 #define RT305X_PCM_BASE         0x10000400
  22 #define RT305X_UART0_BASE       0x10000500
  23 #define RT305X_PIO_BASE         0x10000600
  24 #define RT305X_GDMA_BASE        0x10000700
  25 #define RT305X_NANDC_BASE       0x10000800
  26 #define RT305X_I2C_BASE         0x10000900
  27 #define RT305X_I2S_BASE         0x10000a00
  28 #define RT305X_SPI_BASE         0x10000b00
  29 #define RT305X_UART1_BASE       0x10000c00
  30 #define RT305X_FE_BASE          0x10010000
  31 #define RT305X_SWITCH_BASE      0x10110000
  32 #define RT305X_WMAC_BASE        0x00180000
  33 #define RT305X_OTG_BASE         0x101c0000
  34 #define RT305X_ROM_BASE         0x00400000
  35 #define RT305X_FLASH1_BASE      0x1b000000
  36 #define RT305X_FLASH0_BASE      0x1f000000
  37
  38 #define RT305X_SYSC_SIZE        0x100
  39 #define RT305X_INTC_SIZE        0x100
  40 #define RT305X_MEMC_SIZE        0x100
  41 #define RT305X_UART0_SIZE       0x100
  42 #define RT305X_UART1_SIZE       0x100
  43 #define RT305X_FLASH1_SIZE      (16 * 1024 * 1024)
  44 #define RT305X_FLASH0_SIZE      (4 * 1024 * 1024)
  45
  46 /* SYSC registers */
  47 #define SYSC_REG_CHIP_NAME0     0x000   /* Chip Name 0 */
  48 #define SYSC_REG_CHIP_NAME1     0x004   /* Chip Name 1 */
  49 #define SYSC_REG_CHIP_ID        0x00c   /* Chip Identification */
  50 #define SYSC_REG_SYSTEM_CONFIG  0x010   /* System Configuration */
  51 #define SYSC_REG_RESET_CTRL     0x034   /* Reset Control*/
  52 #define SYSC_REG_RESET_STATUS   0x038   /* Reset Status*/
  53 #define SYSC_REG_IA_ADDRESS     0x310   /* Illegal Access Address */
  54 #define SYSC_REG_IA_TYPE        0x314   /* Illegal Access Type */
  55
  56 #define CHIP_ID_ID_MASK         0xff
  57 #define CHIP_ID_ID_SHIFT        8
  58 #define CHIP_ID_REV_MASK        0xff
  59
  60 #define SYSTEM_CONFIG_CPUCLK_SHIFT      18
  61 #define SYSTEM_CONFIG_CPUCLK_MASK       0x1
  62 #define SYSTEM_CONFIG_CPUCLK_320        0x0
  63 #define SYSTEM_CONFIG_CPUCLK_384        0x1
  64
  65 #define RT305X_RESET_SYSTEM     BIT(0)
  66 #define RT305X_RESET_TIMER      BIT(8)
  67 #define RT305X_RESET_INTC       BIT(9)
  68 #define RT305X_RESET_MEMC       BIT(10)
  69 #define RT305X_RESET_PCM        BIT(11)
  70 #define RT305X_RESET_UART0      BIT(12)
  71 #define RT305X_RESET_PIO        BIT(13)
  72 #define RT305X_RESET_DMA        BIT(14)
  73 #define RT305X_RESET_I2C        BIT(16)
  74 #define RT305X_RESET_I2S        BIT(17)
  75 #define RT305X_RESET_SPI        BIT(18)
  76 #define RT305X_RESET_UART1      BIT(19)
  77 #define RT305X_RESET_WNIC       BIT(20)
  78 #define RT305X_RESET_FE         BIT(21)
  79 #define RT305X_RESET_OTG        BIT(22)
  80 #define RT305X_RESET_ESW        BIT(23)
  81
  82 #define RT305X_INTC_INT_SYSCTL  BIT(0)
  83 #define RT305X_INTC_INT_TIMER0  BIT(1)
  84 #define RT305X_INTC_INT_TIMER1  BIT(2)
  85 #define RT305X_INTC_INT_IA      BIT(3)
  86 #define RT305X_INTC_INT_PCM     BIT(4)
  87 #define RT305X_INTC_INT_UART0   BIT(5)
  88 #define RT305X_INTC_INT_PIO     BIT(6)
  89 #define RT305X_INTC_INT_DMA     BIT(7)
  90 #define RT305X_INTC_INT_NAND    BIT(8)
  91 #define RT305X_INTC_INT_PERFC   BIT(9)
  92 #define RT305X_INTC_INT_I2S     BIT(10)
  93 #define RT305X_INTC_INT_UART1   BIT(12)
  94 #define RT305X_INTC_INT_ESW     BIT(17)
  95 #define RT305X_INTC_INT_OTG     BIT(18)
  96 #define RT305X_INTC_INT_GLOBAL  BIT(31)
  97
  98 /* MEMC registers */
  99 #define MEMC_REG_SDRAM_CFG0     0x00
 100 #define MEMC_REG_SDRAM_CFG1     0x04
 101 #define MEMC_REG_FLASH_CFG0     0x08
 102 #define MEMC_REG_FLASH_CFG1     0x0c
 103 #define MEMC_REG_IA_ADDR        0x10
 104 #define MEMC_REG_IA_TYPE        0x14
 105
 106 #define FLASH_CFG_WIDTH_SHIFT   26
 107 #define FLASH_CFG_WIDTH_MASK    0x3
 108 #define FLASH_CFG_WIDTH_8BIT    0x0
 109 #define FLASH_CFG_WIDTH_16BIT   0x1
 110 #define FLASH_CFG_WIDTH_32BIT   0x2
 111
 112 /* UART registers */
 113 #define UART_REG_RX     0
 114 #define UART_REG_TX     1
 115 #define UART_REG_IER    2
 116 #define UART_REG_IIR    3
 117 #define UART_REG_FCR    4
 118 #define UART_REG_LCR    5
 119 #define UART_REG_MCR    6
 120 #define UART_REG_LSR    7
 121
 122 #endif /* _RT305X_REGS_H_ */