1 #include <linux/ioport.h>
3 #include <rt305x_regs.h>
4 #include <rt305x_esw_platform.h>
6 #define RT305X_ESW_REG_FCT0 0x08
7 #define RT305X_ESW_REG_PFC1 0x14
8 #define RT305X_ESW_REG_PVIDC(_n) (0x48 + 4 * (_n))
9 #define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
10 #define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
11 #define RT305X_ESW_REG_FPA 0x84
12 #define RT305X_ESW_REG_SOCPC 0x8c
13 #define RT305X_ESW_REG_POC1 0x90
14 #define RT305X_ESW_REG_POC2 0x94
15 #define RT305X_ESW_REG_POC3 0x98
16 #define RT305X_ESW_REG_SGC 0x9c
17 #define RT305X_ESW_REG_PCR0 0xc0
18 #define RT305X_ESW_REG_PCR1 0xc4
19 #define RT305X_ESW_REG_FPA2 0xc8
20 #define RT305X_ESW_REG_FCT2 0xcc
21 #define RT305X_ESW_REG_SGC2 0xe4
23 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
24 #define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
25 #define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
27 #define RT305X_ESW_PCR1_WT_DONE BIT(0)
29 #define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
31 #define RT305X_ESW_VLANI_VID_M 0xfff
32 #define RT305X_ESW_VLANI_VID_S 12
34 #define RT305X_ESW_VMSC_MSC_M 0xff
35 #define RT305X_ESW_VMSC_MSC_S 8
37 #define RT305X_ESW_PORT0 0
38 #define RT305X_ESW_PORT1 1
39 #define RT305X_ESW_PORT2 2
40 #define RT305X_ESW_PORT3 3
41 #define RT305X_ESW_PORT4 4
42 #define RT305X_ESW_PORT5 5
43 #define RT305X_ESW_PORT6 6
47 struct rt305x_esw_platform_data
*pdata
;
48 spinlock_t reg_rw_lock
;
52 rt305x_esw_wr(struct rt305x_esw
*esw
, u32 val
, unsigned reg
)
54 __raw_writel(val
, esw
->base
+ reg
);
58 rt305x_esw_rr(struct rt305x_esw
*esw
, unsigned reg
)
60 return __raw_readl(esw
->base
+ reg
);
64 rt305x_esw_rmw_raw(struct rt305x_esw
*esw
, unsigned reg
, unsigned long mask
,
69 t
= __raw_readl(esw
->base
+ reg
) & ~mask
;
70 __raw_writel(t
| val
, esw
->base
+ reg
);
74 rt305x_esw_rmw(struct rt305x_esw
*esw
, unsigned reg
, unsigned long mask
,
79 spin_lock_irqsave(&esw
->reg_rw_lock
, flags
);
80 rt305x_esw_rmw_raw(esw
, reg
, mask
, val
);
81 spin_unlock_irqrestore(&esw
->reg_rw_lock
, flags
);
85 rt305x_mii_write(struct rt305x_esw
*esw
, u32 phy_addr
, u32 phy_register
,
88 unsigned long t_start
= jiffies
;
92 if (!(rt305x_esw_rr(esw
, RT305X_ESW_REG_PCR1
) &
93 RT305X_ESW_PCR1_WT_DONE
))
95 if (time_after(jiffies
, t_start
+ RT305X_ESW_PHY_TIMEOUT
)) {
101 write_data
&= 0xffff;
103 (write_data
<< RT305X_ESW_PCR0_WT_NWAY_DATA_S
) |
104 (phy_register
<< RT305X_ESW_PCR0_CPU_PHY_REG_S
) |
105 (phy_addr
) | RT305X_ESW_PCR0_WT_PHY_CMD
,
106 RT305X_ESW_REG_PCR0
);
110 if (rt305x_esw_rr(esw
, RT305X_ESW_REG_PCR1
) &
111 RT305X_ESW_PCR1_WT_DONE
)
114 if (time_after(jiffies
, t_start
+ RT305X_ESW_PHY_TIMEOUT
)) {
121 printk(KERN_ERR
"ramips_eth: MDIO timeout\n");
126 rt305x_esw_set_vlan_id(struct rt305x_esw
*esw
, unsigned vlan
, unsigned vid
)
130 s
= RT305X_ESW_VLANI_VID_S
* (vlan
% 2);
132 RT305X_ESW_REG_VLANI(vlan
/ 2),
133 RT305X_ESW_VLANI_VID_M
<< s
,
134 (vid
& RT305X_ESW_VLANI_VID_M
) << s
);
138 rt305x_esw_set_vmsc(struct rt305x_esw
*esw
, unsigned vlan
, unsigned msc
)
142 s
= RT305X_ESW_VMSC_MSC_S
* (vlan
% 4);
144 RT305X_ESW_REG_VMSC(vlan
/ 4),
145 RT305X_ESW_VMSC_MSC_M
<< s
,
146 (msc
& RT305X_ESW_VMSC_MSC_M
) << s
);
150 rt305x_esw_hw_init(struct rt305x_esw
*esw
)
154 /* vodoo from original driver */
155 rt305x_esw_wr(esw
, 0xC8A07850, RT305X_ESW_REG_FCT0
);
156 rt305x_esw_wr(esw
, 0x00000000, RT305X_ESW_REG_SGC2
);
157 rt305x_esw_wr(esw
, 0x00405555, RT305X_ESW_REG_PFC1
);
158 rt305x_esw_wr(esw
, 0x00007f7f, RT305X_ESW_REG_POC1
);
159 rt305x_esw_wr(esw
, 0x00007f3f, RT305X_ESW_REG_POC3
);
160 rt305x_esw_wr(esw
, 0x00d6500c, RT305X_ESW_REG_FCT2
);
161 rt305x_esw_wr(esw
, 0x0008a301, RT305X_ESW_REG_SGC
);
162 rt305x_esw_wr(esw
, 0x02404040, RT305X_ESW_REG_SOCPC
);
163 rt305x_esw_wr(esw
, 0x00001002, RT305X_ESW_REG_PVIDC(2));
164 rt305x_esw_wr(esw
, 0x3f502b28, RT305X_ESW_REG_FPA2
);
165 rt305x_esw_wr(esw
, 0x00000000, RT305X_ESW_REG_FPA
);
167 rt305x_mii_write(esw
, 0, 31, 0x8000);
168 for (i
= 0; i
< 5; i
++) {
169 /* TX10 waveform coefficient */
170 rt305x_mii_write(esw
, i
, 0, 0x3100);
171 /* TX10 waveform coefficient */
172 rt305x_mii_write(esw
, i
, 26, 0x1601);
173 /* TX100/TX10 AD/DA current bias */
174 rt305x_mii_write(esw
, i
, 29, 0x7058);
175 /* TX100 slew rate control */
176 rt305x_mii_write(esw
, i
, 30, 0x0018);
180 /* select global register */
181 rt305x_mii_write(esw
, 0, 31, 0x0);
182 /* tune TP_IDL tail and head waveform */
183 rt305x_mii_write(esw
, 0, 22, 0x052f);
184 /* set TX10 signal amplitude threshold to minimum */
185 rt305x_mii_write(esw
, 0, 17, 0x0fe0);
186 /* set squelch amplitude to higher threshold */
187 rt305x_mii_write(esw
, 0, 18, 0x40ba);
188 /* longer TP_IDL tail length */
189 rt305x_mii_write(esw
, 0, 14, 0x65);
190 /* select local register */
191 rt305x_mii_write(esw
, 0, 31, 0x8000);
193 /* set default vlan */
194 rt305x_esw_set_vlan_id(esw
, 0, 1);
195 rt305x_esw_set_vlan_id(esw
, 1, 2);
196 rt305x_esw_set_vmsc(esw
, 0,
197 (BIT(RT305X_ESW_PORT0
) | BIT(RT305X_ESW_PORT1
) |
198 BIT(RT305X_ESW_PORT2
) | BIT(RT305X_ESW_PORT3
) |
199 BIT(RT305X_ESW_PORT6
)));
200 rt305x_esw_set_vmsc(esw
, 1,
201 (BIT(RT305X_ESW_PORT4
) | BIT(RT305X_ESW_PORT6
)));
202 rt305x_esw_set_vmsc(esw
, 2, 0);
203 rt305x_esw_set_vmsc(esw
, 3, 0);
207 rt305x_esw_probe(struct platform_device
*pdev
)
209 struct rt305x_esw_platform_data
*pdata
;
210 struct rt305x_esw
*esw
;
211 struct resource
*res
;
214 pdata
= pdev
->dev
.platform_data
;
218 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
220 dev_err(&pdev
->dev
, "no memory resource found\n");
224 esw
= kzalloc(sizeof(struct rt305x_esw
), GFP_KERNEL
);
226 dev_err(&pdev
->dev
, "no memory for private data\n");
230 esw
->base
= ioremap(res
->start
, resource_size(res
));
232 dev_err(&pdev
->dev
, "ioremap failed\n");
237 platform_set_drvdata(pdev
, esw
);
240 spin_lock_init(&esw
->reg_rw_lock
);
241 rt305x_esw_hw_init(esw
);
251 rt305x_esw_remove(struct platform_device
*pdev
)
253 struct rt305x_esw
*esw
;
255 esw
= platform_get_drvdata(pdev
);
257 platform_set_drvdata(pdev
, NULL
);
265 static struct platform_driver rt305x_esw_driver
= {
266 .probe
= rt305x_esw_probe
,
267 .remove
= rt305x_esw_remove
,
269 .name
= "rt305x-esw",
270 .owner
= THIS_MODULE
,
275 rt305x_esw_init(void)
277 return platform_driver_register(&rt305x_esw_driver
);
281 rt305x_esw_exit(void)
283 platform_driver_unregister(&rt305x_esw_driver
);