target/linux/brcm47xx/patches-3.0/0007-bcma-get-CPU-clock.patch

   1 From bd2bb5fbf1982b18f44b6fd78e45717e0757cdc0 Mon Sep 17 00:00:00 2001
   2 From: Hauke Mehrtens <hauke@hauke-m.de>
   3 Date: Sat, 16 Jul 2011 15:19:38 +0200
   4 Subject: [PATCH 07/26] bcma: get CPU clock
   5
   6 Add method to return the clock of the CPU. This is needed by the arch
   7 code to calculate the mips_hpt_frequency.
   8
   9 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
  10 ---
  11  drivers/bcma/bcma_private.h                 |    1 +
  12  drivers/bcma/driver_chipcommon_pmu.c        |  107 +++++++++++++++++++++++++++
  13  drivers/bcma/driver_mips.c                  |   12 +++
  14  include/linux/bcma/bcma_driver_chipcommon.h |   39 ++++++++++
  15  include/linux/bcma/bcma_driver_mips.h       |    2 +
  16  5 files changed, 161 insertions(+), 0 deletions(-)
  17
  18 --- a/drivers/bcma/bcma_private.h
  19 +++ b/drivers/bcma/bcma_private.h
  20 @@ -36,6 +36,7 @@ void bcma_chipco_serial_init(struct bcma
  21
  22  /* driver_chipcommon_pmu.c */
  23  u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
  24 +u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
  25
  26  #ifdef CONFIG_BCMA_HOST_PCI
  27  /* host_pci.c */
  28 --- a/drivers/bcma/driver_chipcommon_pmu.c
  29 +++ b/drivers/bcma/driver_chipcommon_pmu.c
  30 @@ -11,6 +11,13 @@
  31  #include "bcma_private.h"
  32  #include <linux/bcma/bcma.h>
  33
  34 +static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
  35 +{
  36 +       bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
  37 +       bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
  38 +       return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
  39 +}
  40 +
  41  static void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
  42                                         u32 offset, u32 mask, u32 set)
  43  {
  44 @@ -162,3 +169,103 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
  45         }
  46         return BCMA_CC_PMU_ALP_CLOCK;
  47  }
  48 +
  49 +/* Find the output of the "m" pll divider given pll controls that start with
  50 + * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
  51 + */
  52 +static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
  53 +{
  54 +       u32 tmp, div, ndiv, p1, p2, fc;
  55 +       struct bcma_bus *bus = cc->core->bus;
  56 +
  57 +       BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
  58 +
  59 +       BUG_ON(!m || m > 4);
  60 +
  61 +       if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) {
  62 +               /* Detect failure in clock setting */
  63 +               tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
  64 +               if (tmp & 0x40000)
  65 +                       return 133 * 1000000;
  66 +       }
  67 +
  68 +       tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
  69 +       p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
  70 +       p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;
  71 +
  72 +       tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
  73 +       div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
  74 +               BCMA_CC_PPL_MDIV_MASK;
  75 +
  76 +       tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
  77 +       ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
  78 +
  79 +       /* Do calculation in Mhz */
  80 +       fc = bcma_pmu_alp_clock(cc) / 1000000;
  81 +       fc = (p1 * ndiv * fc) / p2;
  82 +
  83 +       /* Return clock in Hertz */
  84 +       return (fc / div) * 1000000;
  85 +}
  86 +
  87 +/* query bus clock frequency for PMU-enabled chipcommon */
  88 +u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
  89 +{
  90 +       struct bcma_bus *bus = cc->core->bus;
  91 +
  92 +       switch (bus->chipinfo.id) {
  93 +       case 0x4716:
  94 +       case 0x4748:
  95 +       case 47162:
  96 +               return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
  97 +                                     BCMA_CC_PMU5_MAINPLL_SSB);
  98 +       case 0x5356:
  99 +               return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
 100 +                                     BCMA_CC_PMU5_MAINPLL_SSB);
 101 +       case 0x5357:
 102 +       case 0x4749:
 103 +               return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
 104 +                                     BCMA_CC_PMU5_MAINPLL_SSB);
 105 +       case 0x5300:
 106 +               return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
 107 +                                     BCMA_CC_PMU5_MAINPLL_SSB);
 108 +       case 53572:
 109 +               return 75000000;
 110 +       default:
 111 +               pr_warn("No backplane clock specified for %04X device, "
 112 +                       "pmu rev. %d, using default %d Hz\n",
 113 +                       bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
 114 +       }
 115 +       return BCMA_CC_PMU_HT_CLOCK;
 116 +}
 117 +
 118 +/* query cpu clock frequency for PMU-enabled chipcommon */
 119 +u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
 120 +{
 121 +       struct bcma_bus *bus = cc->core->bus;
 122 +
 123 +       if (bus->chipinfo.id == 53572)
 124 +               return 300000000;
 125 +
 126 +       if (cc->pmu.rev >= 5) {
 127 +               u32 pll;
 128 +               switch (bus->chipinfo.id) {
 129 +               case 0x5356:
 130 +                       pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
 131 +                       break;
 132 +               case 0x5357:
 133 +               case 0x4749:
 134 +                       pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
 135 +                       break;
 136 +               default:
 137 +                       pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
 138 +                       break;
 139 +               }
 140 +
 141 +               /* TODO: if (bus->chipinfo.id == 0x5300)
 142 +                 return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
 143 +               return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
 144 +       }
 145 +
 146 +       return bcma_pmu_get_clockcontrol(cc);
 147 +}
 148 --- a/drivers/bcma/driver_mips.c
 149 +++ b/drivers/bcma/driver_mips.c
 150 @@ -166,6 +166,18 @@ static void bcma_core_mips_dump_irq(stru
 151         }
 152  }
 153
 154 +u32 bcma_cpu_clock(struct bcma_drv_mips *mcore)
 155 +{
 156 +       struct bcma_bus *bus = mcore->core->bus;
 157 +
 158 +       if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
 159 +               return bcma_pmu_get_clockcpu(&bus->drv_cc);
 160 +
 161 +       pr_err("No PMU available, need this to get the cpu clock\n");
 162 +       return 0;
 163 +}
 164 +EXPORT_SYMBOL(bcma_cpu_clock);
 165 +
 166  static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
 167  {
 168         struct bcma_bus *bus = mcore->core->bus;
 169 --- a/include/linux/bcma/bcma_driver_chipcommon.h
 170 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
 171 @@ -241,8 +241,47 @@
 172  #define BCMA_CC_SPROM                  0x0800 /* SPROM beginning */
 173  #define BCMA_CC_SPROM_PCIE6            0x0830 /* SPROM beginning on PCIe rev >= 6 */
 174
 175 +/* Divider allocation in 4716/47162/5356 */
 176 +#define BCMA_CC_PMU5_MAINPLL_CPU       1
 177 +#define BCMA_CC_PMU5_MAINPLL_MEM       2
 178 +#define BCMA_CC_PMU5_MAINPLL_SSB       3
 179 +
 180 +/* PLL usage in 4716/47162 */
 181 +#define BCMA_CC_PMU4716_MAINPLL_PLL0   12
 182 +
 183 +/* PLL usage in 5356/5357 */
 184 +#define BCMA_CC_PMU5356_MAINPLL_PLL0   0
 185 +#define BCMA_CC_PMU5357_MAINPLL_PLL0   0
 186 +
 187 +/* 4706 PMU */
 188 +#define BCMA_CC_PMU4706_MAINPLL_PLL0   0
 189 +
 190  /* ALP clock on pre-PMU chips */
 191  #define BCMA_CC_PMU_ALP_CLOCK          20000000
 192 +/* HT clock for systems with PMU-enabled chipcommon */
 193 +#define BCMA_CC_PMU_HT_CLOCK           80000000
 194 +
 195 +/* PMU rev 5 (& 6) */
 196 +#define BCMA_CC_PPL_P1P2_OFF           0
 197 +#define BCMA_CC_PPL_P1_MASK            0x0f000000
 198 +#define BCMA_CC_PPL_P1_SHIFT           24
 199 +#define BCMA_CC_PPL_P2_MASK            0x00f00000
 200 +#define BCMA_CC_PPL_P2_SHIFT           20
 201 +#define BCMA_CC_PPL_M14_OFF            1
 202 +#define BCMA_CC_PPL_MDIV_MASK          0x000000ff
 203 +#define BCMA_CC_PPL_MDIV_WIDTH         8
 204 +#define BCMA_CC_PPL_NM5_OFF            2
 205 +#define BCMA_CC_PPL_NDIV_MASK          0xfff00000
 206 +#define BCMA_CC_PPL_NDIV_SHIFT         20
 207 +#define BCMA_CC_PPL_FMAB_OFF           3
 208 +#define BCMA_CC_PPL_MRAT_MASK          0xf0000000
 209 +#define BCMA_CC_PPL_MRAT_SHIFT         28
 210 +#define BCMA_CC_PPL_ABRAT_MASK         0x08000000
 211 +#define BCMA_CC_PPL_ABRAT_SHIFT                27
 212 +#define BCMA_CC_PPL_FDIV_MASK          0x07ffffff
 213 +#define BCMA_CC_PPL_PLLCTL_OFF         4
 214 +#define BCMA_CC_PPL_PCHI_OFF           5
 215 +#define BCMA_CC_PPL_PCHI_MASK          0x0000003f
 216
 217  /* Data for the PMU, if available.
 218   * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
 219 --- a/include/linux/bcma/bcma_driver_mips.h
 220 +++ b/include/linux/bcma/bcma_driver_mips.h
 221 @@ -44,6 +44,8 @@ extern void bcma_core_mips_init(struct b
 222  static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
 223  #endif
 224
 225 +extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
 226 +
 227  extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
 228
 229  #endif /* LINUX_BCMA_DRIVER_MIPS_H_ */