target/linux/xburst/patches-2.6.34/052-rtc.patch

   1 From 103784e50d565c9e9325a9256e0547a40c6b959c Mon Sep 17 00:00:00 2001
   2 From: Lars-Peter Clausen <lars@metafoo.de>
   3 Date: Sat, 24 Apr 2010 12:12:37 +0200
   4 Subject: [PATCH] Add jz4740 rtc driver
   5
   6 ---
   7  drivers/rtc/Kconfig      |   11 ++
   8  drivers/rtc/Makefile     |    1 +
   9  drivers/rtc/rtc-jz4740.c |  344 ++++++++++++++++++++++++++++++++++++++++++++++
  10  3 files changed, 356 insertions(+), 0 deletions(-)
  11  create mode 100644 drivers/rtc/rtc-jz4740.c
  12
  13 diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
  14 index 6a13037..8210bc7 100644
  15 --- a/drivers/rtc/Kconfig
  16 +++ b/drivers/rtc/Kconfig
  17 @@ -888,4 +888,15 @@ config RTC_DRV_MPC5121
  18           This driver can also be built as a module. If so, the module
  19           will be called rtc-mpc5121.
  20
  21 +config RTC_DRV_JZ4740
  22 +       tristate "Ingenic JZ4740 SoC"
  23 +       depends on RTC_CLASS
  24 +       depends on SOC_JZ4740
  25 +       help
  26 +         If you say yes here you get support for the
  27 +         Ingenic JZ4740 SoC RTC controller.
  28 +
  29 +         This driver can also be buillt as a module. If so, the module
  30 +         will be called rtc-jz4740.
  31 +
  32  endif # RTC_CLASS
  33 diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
  34 index 44ef194..7002033 100644
  35 --- a/drivers/rtc/Makefile
  36 +++ b/drivers/rtc/Makefile
  37 @@ -45,6 +45,7 @@ obj-$(CONFIG_RTC_DRV_EP93XX)  += rtc-ep93xx.o
  38  obj-$(CONFIG_RTC_DRV_FM3130)   += rtc-fm3130.o
  39  obj-$(CONFIG_RTC_DRV_GENERIC)  += rtc-generic.o
  40  obj-$(CONFIG_RTC_DRV_ISL1208)  += rtc-isl1208.o
  41 +obj-$(CONFIG_RTC_DRV_JZ4740)   += rtc-jz4740.o
  42  obj-$(CONFIG_RTC_DRV_M41T80)   += rtc-m41t80.o
  43  obj-$(CONFIG_RTC_DRV_M41T94)   += rtc-m41t94.o
  44  obj-$(CONFIG_RTC_DRV_M48T35)   += rtc-m48t35.o
  45 diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c
  46 new file mode 100644
  47 index 0000000..aac905a
  48 --- /dev/null
  49 +++ b/drivers/rtc/rtc-jz4740.c
  50 @@ -0,0 +1,344 @@
  51 +/*
  52 + *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  53 + *             JZ4720/JZ4740 SoC RTC driver
  54 + *
  55 + *  This program is free software; you can redistribute         it and/or modify it
  56 + *  under  the terms of         the GNU General  Public License as published by the
  57 + *  Free Software Foundation;  either version 2 of the License, or (at your
  58 + *  option) any later version.
  59 + *
  60 + *  You should have received a copy of the  GNU General Public License along
  61 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
  62 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  63 + *
  64 + */
  65 +
  66 +#include <linux/kernel.h>
  67 +#include <linux/module.h>
  68 +#include <linux/platform_device.h>
  69 +#include <linux/rtc.h>
  70 +#include <linux/slab.h>
  71 +#include <linux/spinlock.h>
  72 +
  73 +#define JZ_REG_RTC_CTRL                0x00
  74 +#define JZ_REG_RTC_SEC         0x04
  75 +#define JZ_REG_RTC_SEC_ALARM   0x08
  76 +#define JZ_REG_RTC_REGULATOR   0x0C
  77 +#define JZ_REG_RTC_HIBERNATE   0x20
  78 +#define JZ_REG_RTC_SCRATCHPAD  0x34
  79 +
  80 +#define JZ_RTC_CTRL_WRDY       BIT(7)
  81 +#define JZ_RTC_CTRL_1HZ                BIT(6)
  82 +#define JZ_RTC_CTRL_1HZ_IRQ    BIT(5)
  83 +#define JZ_RTC_CTRL_AF         BIT(4)
  84 +#define JZ_RTC_CTRL_AF_IRQ     BIT(3)
  85 +#define JZ_RTC_CTRL_AE         BIT(2)
  86 +#define JZ_RTC_CTRL_ENABLE     BIT(0)
  87 +
  88 +struct jz4740_rtc {
  89 +       struct resource *mem;
  90 +       void __iomem *base;
  91 +
  92 +       struct rtc_device *rtc;
  93 +
  94 +       unsigned int irq;
  95 +
  96 +       spinlock_t lock;
  97 +};
  98 +
  99 +static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
 100 +{
 101 +       return readl(rtc->base + reg);
 102 +}
 103 +
 104 +static inline void jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
 105 +{
 106 +       uint32_t ctrl;
 107 +       do {
 108 +               ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 109 +       } while (!(ctrl & JZ_RTC_CTRL_WRDY));
 110 +}
 111 +
 112 +
 113 +static inline void jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
 114 +                                       uint32_t val)
 115 +{
 116 +       jz4740_rtc_wait_write_ready(rtc);
 117 +       writel(val, rtc->base + reg);
 118 +}
 119 +
 120 +static void jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
 121 +                                       uint32_t val)
 122 +{
 123 +       unsigned long flags;
 124 +       uint32_t ctrl;
 125 +
 126 +       spin_lock_irqsave(&rtc->lock, flags);
 127 +
 128 +       ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 129 +
 130 +       /* Don't clear interrupt flags by accident */
 131 +       ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
 132 +
 133 +       ctrl &= ~mask;
 134 +       ctrl |= val;
 135 +
 136 +       jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
 137 +
 138 +       spin_unlock_irqrestore(&rtc->lock, flags);
 139 +}
 140 +
 141 +static inline struct jz4740_rtc *dev_to_rtc(struct device *dev)
 142 +{
 143 +       return dev_get_drvdata(dev);
 144 +}
 145 +
 146 +static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
 147 +{
 148 +       struct jz4740_rtc *rtc = dev_to_rtc(dev);
 149 +       uint32_t secs, secs2;
 150 +
 151 +       secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 152 +       secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 153 +
 154 +       while (secs != secs2) {
 155 +               secs = secs2;
 156 +               secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 157 +       }
 158 +
 159 +       rtc_time_to_tm(secs, time);
 160 +
 161 +       return rtc_valid_tm(time);
 162 +}
 163 +
 164 +static int jz4740_rtc_set_mmss(struct device *dev, unsigned long secs)
 165 +{
 166 +       struct jz4740_rtc *rtc = dev_to_rtc(dev);
 167 +
 168 +       if ((uint32_t)secs != secs)
 169 +               return -EINVAL;
 170 +
 171 +       jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, secs);
 172 +
 173 +       return 0;
 174 +}
 175 +
 176 +static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 177 +{
 178 +       struct jz4740_rtc *rtc = dev_to_rtc(dev);
 179 +       uint32_t secs, secs2;
 180 +       uint32_t ctrl;
 181 +
 182 +       secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
 183 +       secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
 184 +
 185 +       while (secs != secs2) {
 186 +               secs = secs2;
 187 +               secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
 188 +       }
 189 +
 190 +       ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 191 +
 192 +       alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
 193 +       alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
 194 +
 195 +       rtc_time_to_tm(secs, &alrm->time);
 196 +
 197 +       return rtc_valid_tm(&alrm->time);
 198 +}
 199 +
 200 +static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 201 +{
 202 +       struct jz4740_rtc *rtc = dev_to_rtc(dev);
 203 +       unsigned long secs;
 204 +
 205 +       rtc_tm_to_time(&alrm->time, &secs);
 206 +
 207 +       if ((uint32_t)secs != secs)
 208 +               return -EINVAL;
 209 +
 210 +       jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, (uint32_t)secs);
 211 +       jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AE,
 212 +                                       alrm->enabled ? JZ_RTC_CTRL_AE : 0);
 213 +
 214 +       return 0;
 215 +}
 216 +
 217 +static int jz4740_rtc_update_irq_enable(struct device *dev, unsigned int enable)
 218 +{
 219 +       struct jz4740_rtc *rtc = dev_to_rtc(dev);
 220 +       jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ_IRQ,
 221 +                                       enable ? JZ_RTC_CTRL_1HZ_IRQ : 0);
 222 +       return 0;
 223 +}
 224 +
 225 +
 226 +static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
 227 +{
 228 +       struct jz4740_rtc *rtc = dev_to_rtc(dev);
 229 +       jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ,
 230 +                                       enable ? JZ_RTC_CTRL_AF_IRQ : 0);
 231 +       return 0;
 232 +}
 233 +
 234 +static struct rtc_class_ops jz4740_rtc_ops = {
 235 +       .read_time      = jz4740_rtc_read_time,
 236 +       .set_mmss       = jz4740_rtc_set_mmss,
 237 +       .read_alarm     = jz4740_rtc_read_alarm,
 238 +       .set_alarm      = jz4740_rtc_set_alarm,
 239 +       .update_irq_enable = jz4740_rtc_update_irq_enable,
 240 +       .alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
 241 +};
 242 +
 243 +static irqreturn_t jz4740_rtc_irq(int irq, void *data)
 244 +{
 245 +       struct jz4740_rtc *rtc = data;
 246 +       uint32_t ctrl;
 247 +       unsigned long events = 0;
 248 +       ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 249 +
 250 +       if (ctrl & JZ_RTC_CTRL_1HZ)
 251 +               events |= (RTC_UF | RTC_IRQF);
 252 +
 253 +       if (ctrl & JZ_RTC_CTRL_AF)
 254 +               events |= (RTC_AF | RTC_IRQF);
 255 +
 256 +       rtc_update_irq(rtc->rtc, 1, events);
 257 +
 258 +       jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, 0);
 259 +
 260 +       return IRQ_HANDLED;
 261 +}
 262 +
 263 +void jz4740_rtc_poweroff(struct device *dev)
 264 +{
 265 +       struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 266 +       jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
 267 +}
 268 +EXPORT_SYMBOL_GPL(jz4740_rtc_poweroff);
 269 +
 270 +static int __devinit jz4740_rtc_probe(struct platform_device *pdev)
 271 +{
 272 +       int ret;
 273 +       struct jz4740_rtc *rtc;
 274 +       uint32_t scratchpad;
 275 +
 276 +       rtc = kmalloc(sizeof(*rtc), GFP_KERNEL);
 277 +
 278 +       rtc->irq = platform_get_irq(pdev, 0);
 279 +
 280 +       if (rtc->irq < 0) {
 281 +               ret = -ENOENT;
 282 +               dev_err(&pdev->dev, "Failed to get platform irq\n");
 283 +               goto err_free;
 284 +       }
 285 +
 286 +       rtc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 287 +       if (!rtc->mem) {
 288 +               ret = -ENOENT;
 289 +               dev_err(&pdev->dev, "Failed to get platform mmio memory\n");
 290 +               goto err_free;
 291 +       }
 292 +
 293 +       rtc->mem = request_mem_region(rtc->mem->start, resource_size(rtc->mem),
 294 +                                       pdev->name);
 295 +
 296 +       if (!rtc->mem) {
 297 +               ret = -EBUSY;
 298 +               dev_err(&pdev->dev, "Failed to request mmio memory region\n");
 299 +               goto err_free;
 300 +       }
 301 +
 302 +       rtc->base = ioremap_nocache(rtc->mem->start, resource_size(rtc->mem));
 303 +
 304 +       if (!rtc->base) {
 305 +               ret = -EBUSY;
 306 +               dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
 307 +               goto err_release_mem_region;
 308 +       }
 309 +
 310 +       spin_lock_init(&rtc->lock);
 311 +
 312 +       platform_set_drvdata(pdev, rtc);
 313 +
 314 +       rtc->rtc = rtc_device_register(pdev->name, &pdev->dev, &jz4740_rtc_ops,
 315 +                                       THIS_MODULE);
 316 +
 317 +       if (IS_ERR(rtc->rtc)) {
 318 +               ret = PTR_ERR(rtc->rtc);
 319 +               dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret);
 320 +               goto err_iounmap;
 321 +       }
 322 +
 323 +       ret = request_irq(rtc->irq, jz4740_rtc_irq, 0,
 324 +                               pdev->name, rtc);
 325 +
 326 +       if (ret) {
 327 +               dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
 328 +               goto err_unregister_rtc;
 329 +       }
 330 +
 331 +       scratchpad = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD);
 332 +       if (scratchpad != 0x12345678) {
 333 +               jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
 334 +               jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, 0);
 335 +       }
 336 +
 337 +       return 0;
 338 +
 339 +err_unregister_rtc:
 340 +       rtc_device_unregister(rtc->rtc);
 341 +err_iounmap:
 342 +       platform_set_drvdata(pdev, NULL);
 343 +       iounmap(rtc->base);
 344 +err_release_mem_region:
 345 +       release_mem_region(rtc->mem->start, resource_size(rtc->mem));
 346 +err_free:
 347 +       kfree(rtc);
 348 +
 349 +       return ret;
 350 +}
 351 +
 352 +static int __devexit jz4740_rtc_remove(struct platform_device *pdev)
 353 +{
 354 +       struct jz4740_rtc *rtc = platform_get_drvdata(pdev);
 355 +
 356 +       free_irq(rtc->irq, rtc);
 357 +
 358 +       rtc_device_unregister(rtc->rtc);
 359 +
 360 +       iounmap(rtc->base);
 361 +       release_mem_region(rtc->mem->start, resource_size(rtc->mem));
 362 +
 363 +       kfree(rtc);
 364 +
 365 +       platform_set_drvdata(pdev, NULL);
 366 +
 367 +       return 0;
 368 +}
 369 +
 370 +struct platform_driver jz4740_rtc_driver = {
 371 +       .probe = jz4740_rtc_probe,
 372 +       .remove = __devexit_p(jz4740_rtc_remove),
 373 +       .driver = {
 374 +               .name = "jz4740-rtc",
 375 +               .owner = THIS_MODULE,
 376 +       },
 377 +};
 378 +
 379 +static int __init jz4740_rtc_init(void)
 380 +{
 381 +       return platform_driver_register(&jz4740_rtc_driver);
 382 +}
 383 +module_init(jz4740_rtc_init);
 384 +
 385 +static void __exit jz4740_rtc_exit(void)
 386 +{
 387 +       platform_driver_unregister(&jz4740_rtc_driver);
 388 +}
 389 +module_exit(jz4740_rtc_exit);
 390 +
 391 +MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 392 +MODULE_LICENSE("GPL");
 393 +MODULE_DESCRIPTION("RTC driver for the JZ4720/JZ4740 SoC\n");
 394 +MODULE_ALIAS("platform:jz4740-rtc");
 395 --
 396 1.5.6.5
 397