target/linux/cavium-octeon/patches/005-register_defs_octeon_mgmt.patch

   1 The MGMT ethernet driver uses the AGL, MIXX and SMIX blocks, so we add
   2 definitions for them.
   3
   4 Signed-off-by: David Daney <ddaney@caviumnetworks.com>
   5 ---
   6  arch/mips/include/asm/octeon/cvmx-agl-defs.h  | 1194 +++++++++++++++++++++++++
   7  arch/mips/include/asm/octeon/cvmx-mixx-defs.h |  248 +++++
   8  arch/mips/include/asm/octeon/cvmx-smix-defs.h |  178 ++++
   9  3 files changed, 1620 insertions(+), 0 deletions(-)
  10  create mode 100644 arch/mips/include/asm/octeon/cvmx-agl-defs.h
  11  create mode 100644 arch/mips/include/asm/octeon/cvmx-mixx-defs.h
  12  create mode 100644 arch/mips/include/asm/octeon/cvmx-smix-defs.h
  13
  14 diff --git a/arch/mips/include/asm/octeon/cvmx-agl-defs.h b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
  15 new file mode 100644
  16 index 0000000..ec94b9a
  17 --- /dev/null
  18 +++ b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
  19 @@ -0,0 +1,1194 @@
  20 +/***********************license start***************
  21 + * Author: Cavium Networks
  22 + *
  23 + * Contact: support@caviumnetworks.com
  24 + * This file is part of the OCTEON SDK
  25 + *
  26 + * Copyright (c) 2003-2008 Cavium Networks
  27 + *
  28 + * This file is free software; you can redistribute it and/or modify
  29 + * it under the terms of the GNU General Public License, Version 2, as
  30 + * published by the Free Software Foundation.
  31 + *
  32 + * This file is distributed in the hope that it will be useful, but
  33 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  34 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  35 + * NONINFRINGEMENT.  See the GNU General Public License for more
  36 + * details.
  37 + *
  38 + * You should have received a copy of the GNU General Public License
  39 + * along with this file; if not, write to the Free Software
  40 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  41 + * or visit http://www.gnu.org/licenses/.
  42 + *
  43 + * This file may also be available under a different license from Cavium.
  44 + * Contact Cavium Networks for more information
  45 + ***********************license end**************************************/
  46 +
  47 +#ifndef __CVMX_AGL_DEFS_H__
  48 +#define __CVMX_AGL_DEFS_H__
  49 +
  50 +#define CVMX_AGL_GMX_BAD_REG \
  51 +        CVMX_ADD_IO_SEG(0x00011800E0000518ull)
  52 +#define CVMX_AGL_GMX_BIST \
  53 +        CVMX_ADD_IO_SEG(0x00011800E0000400ull)
  54 +#define CVMX_AGL_GMX_DRV_CTL \
  55 +        CVMX_ADD_IO_SEG(0x00011800E00007F0ull)
  56 +#define CVMX_AGL_GMX_INF_MODE \
  57 +        CVMX_ADD_IO_SEG(0x00011800E00007F8ull)
  58 +#define CVMX_AGL_GMX_PRTX_CFG(offset) \
  59 +        CVMX_ADD_IO_SEG(0x00011800E0000010ull + (((offset) & 1) * 2048))
  60 +#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) \
  61 +        CVMX_ADD_IO_SEG(0x00011800E0000180ull + (((offset) & 1) * 2048))
  62 +#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) \
  63 +        CVMX_ADD_IO_SEG(0x00011800E0000188ull + (((offset) & 1) * 2048))
  64 +#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) \
  65 +        CVMX_ADD_IO_SEG(0x00011800E0000190ull + (((offset) & 1) * 2048))
  66 +#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) \
  67 +        CVMX_ADD_IO_SEG(0x00011800E0000198ull + (((offset) & 1) * 2048))
  68 +#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) \
  69 +        CVMX_ADD_IO_SEG(0x00011800E00001A0ull + (((offset) & 1) * 2048))
  70 +#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) \
  71 +        CVMX_ADD_IO_SEG(0x00011800E00001A8ull + (((offset) & 1) * 2048))
  72 +#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) \
  73 +        CVMX_ADD_IO_SEG(0x00011800E0000108ull + (((offset) & 1) * 2048))
  74 +#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) \
  75 +        CVMX_ADD_IO_SEG(0x00011800E0000100ull + (((offset) & 1) * 2048))
  76 +#define CVMX_AGL_GMX_RXX_DECISION(offset) \
  77 +        CVMX_ADD_IO_SEG(0x00011800E0000040ull + (((offset) & 1) * 2048))
  78 +#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) \
  79 +        CVMX_ADD_IO_SEG(0x00011800E0000020ull + (((offset) & 1) * 2048))
  80 +#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) \
  81 +        CVMX_ADD_IO_SEG(0x00011800E0000018ull + (((offset) & 1) * 2048))
  82 +#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) \
  83 +        CVMX_ADD_IO_SEG(0x00011800E0000030ull + (((offset) & 1) * 2048))
  84 +#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) \
  85 +        CVMX_ADD_IO_SEG(0x00011800E0000028ull + (((offset) & 1) * 2048))
  86 +#define CVMX_AGL_GMX_RXX_IFG(offset) \
  87 +        CVMX_ADD_IO_SEG(0x00011800E0000058ull + (((offset) & 1) * 2048))
  88 +#define CVMX_AGL_GMX_RXX_INT_EN(offset) \
  89 +        CVMX_ADD_IO_SEG(0x00011800E0000008ull + (((offset) & 1) * 2048))
  90 +#define CVMX_AGL_GMX_RXX_INT_REG(offset) \
  91 +        CVMX_ADD_IO_SEG(0x00011800E0000000ull + (((offset) & 1) * 2048))
  92 +#define CVMX_AGL_GMX_RXX_JABBER(offset) \
  93 +        CVMX_ADD_IO_SEG(0x00011800E0000038ull + (((offset) & 1) * 2048))
  94 +#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) \
  95 +        CVMX_ADD_IO_SEG(0x00011800E0000068ull + (((offset) & 1) * 2048))
  96 +#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) \
  97 +        CVMX_ADD_IO_SEG(0x00011800E0000050ull + (((offset) & 1) * 2048))
  98 +#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) \
  99 +        CVMX_ADD_IO_SEG(0x00011800E0000088ull + (((offset) & 1) * 2048))
 100 +#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) \
 101 +        CVMX_ADD_IO_SEG(0x00011800E0000098ull + (((offset) & 1) * 2048))
 102 +#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) \
 103 +        CVMX_ADD_IO_SEG(0x00011800E00000A8ull + (((offset) & 1) * 2048))
 104 +#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) \
 105 +        CVMX_ADD_IO_SEG(0x00011800E00000B8ull + (((offset) & 1) * 2048))
 106 +#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) \
 107 +        CVMX_ADD_IO_SEG(0x00011800E0000080ull + (((offset) & 1) * 2048))
 108 +#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) \
 109 +        CVMX_ADD_IO_SEG(0x00011800E00000C0ull + (((offset) & 1) * 2048))
 110 +#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) \
 111 +        CVMX_ADD_IO_SEG(0x00011800E0000090ull + (((offset) & 1) * 2048))
 112 +#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) \
 113 +        CVMX_ADD_IO_SEG(0x00011800E00000A0ull + (((offset) & 1) * 2048))
 114 +#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) \
 115 +        CVMX_ADD_IO_SEG(0x00011800E00000B0ull + (((offset) & 1) * 2048))
 116 +#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) \
 117 +        CVMX_ADD_IO_SEG(0x00011800E0000048ull + (((offset) & 1) * 2048))
 118 +#define CVMX_AGL_GMX_RX_BP_DROPX(offset) \
 119 +        CVMX_ADD_IO_SEG(0x00011800E0000420ull + (((offset) & 1) * 8))
 120 +#define CVMX_AGL_GMX_RX_BP_OFFX(offset) \
 121 +        CVMX_ADD_IO_SEG(0x00011800E0000460ull + (((offset) & 1) * 8))
 122 +#define CVMX_AGL_GMX_RX_BP_ONX(offset) \
 123 +        CVMX_ADD_IO_SEG(0x00011800E0000440ull + (((offset) & 1) * 8))
 124 +#define CVMX_AGL_GMX_RX_PRT_INFO \
 125 +        CVMX_ADD_IO_SEG(0x00011800E00004E8ull)
 126 +#define CVMX_AGL_GMX_RX_TX_STATUS \
 127 +        CVMX_ADD_IO_SEG(0x00011800E00007E8ull)
 128 +#define CVMX_AGL_GMX_SMACX(offset) \
 129 +        CVMX_ADD_IO_SEG(0x00011800E0000230ull + (((offset) & 1) * 2048))
 130 +#define CVMX_AGL_GMX_STAT_BP \
 131 +        CVMX_ADD_IO_SEG(0x00011800E0000520ull)
 132 +#define CVMX_AGL_GMX_TXX_APPEND(offset) \
 133 +        CVMX_ADD_IO_SEG(0x00011800E0000218ull + (((offset) & 1) * 2048))
 134 +#define CVMX_AGL_GMX_TXX_CTL(offset) \
 135 +        CVMX_ADD_IO_SEG(0x00011800E0000270ull + (((offset) & 1) * 2048))
 136 +#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) \
 137 +        CVMX_ADD_IO_SEG(0x00011800E0000240ull + (((offset) & 1) * 2048))
 138 +#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) \
 139 +        CVMX_ADD_IO_SEG(0x00011800E0000248ull + (((offset) & 1) * 2048))
 140 +#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) \
 141 +        CVMX_ADD_IO_SEG(0x00011800E0000238ull + (((offset) & 1) * 2048))
 142 +#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) \
 143 +        CVMX_ADD_IO_SEG(0x00011800E0000258ull + (((offset) & 1) * 2048))
 144 +#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) \
 145 +        CVMX_ADD_IO_SEG(0x00011800E0000260ull + (((offset) & 1) * 2048))
 146 +#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) \
 147 +        CVMX_ADD_IO_SEG(0x00011800E0000250ull + (((offset) & 1) * 2048))
 148 +#define CVMX_AGL_GMX_TXX_STAT0(offset) \
 149 +        CVMX_ADD_IO_SEG(0x00011800E0000280ull + (((offset) & 1) * 2048))
 150 +#define CVMX_AGL_GMX_TXX_STAT1(offset) \
 151 +        CVMX_ADD_IO_SEG(0x00011800E0000288ull + (((offset) & 1) * 2048))
 152 +#define CVMX_AGL_GMX_TXX_STAT2(offset) \
 153 +        CVMX_ADD_IO_SEG(0x00011800E0000290ull + (((offset) & 1) * 2048))
 154 +#define CVMX_AGL_GMX_TXX_STAT3(offset) \
 155 +        CVMX_ADD_IO_SEG(0x00011800E0000298ull + (((offset) & 1) * 2048))
 156 +#define CVMX_AGL_GMX_TXX_STAT4(offset) \
 157 +        CVMX_ADD_IO_SEG(0x00011800E00002A0ull + (((offset) & 1) * 2048))
 158 +#define CVMX_AGL_GMX_TXX_STAT5(offset) \
 159 +        CVMX_ADD_IO_SEG(0x00011800E00002A8ull + (((offset) & 1) * 2048))
 160 +#define CVMX_AGL_GMX_TXX_STAT6(offset) \
 161 +        CVMX_ADD_IO_SEG(0x00011800E00002B0ull + (((offset) & 1) * 2048))
 162 +#define CVMX_AGL_GMX_TXX_STAT7(offset) \
 163 +        CVMX_ADD_IO_SEG(0x00011800E00002B8ull + (((offset) & 1) * 2048))
 164 +#define CVMX_AGL_GMX_TXX_STAT8(offset) \
 165 +        CVMX_ADD_IO_SEG(0x00011800E00002C0ull + (((offset) & 1) * 2048))
 166 +#define CVMX_AGL_GMX_TXX_STAT9(offset) \
 167 +        CVMX_ADD_IO_SEG(0x00011800E00002C8ull + (((offset) & 1) * 2048))
 168 +#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) \
 169 +        CVMX_ADD_IO_SEG(0x00011800E0000268ull + (((offset) & 1) * 2048))
 170 +#define CVMX_AGL_GMX_TXX_THRESH(offset) \
 171 +        CVMX_ADD_IO_SEG(0x00011800E0000210ull + (((offset) & 1) * 2048))
 172 +#define CVMX_AGL_GMX_TX_BP \
 173 +        CVMX_ADD_IO_SEG(0x00011800E00004D0ull)
 174 +#define CVMX_AGL_GMX_TX_COL_ATTEMPT \
 175 +        CVMX_ADD_IO_SEG(0x00011800E0000498ull)
 176 +#define CVMX_AGL_GMX_TX_IFG \
 177 +        CVMX_ADD_IO_SEG(0x00011800E0000488ull)
 178 +#define CVMX_AGL_GMX_TX_INT_EN \
 179 +        CVMX_ADD_IO_SEG(0x00011800E0000508ull)
 180 +#define CVMX_AGL_GMX_TX_INT_REG \
 181 +        CVMX_ADD_IO_SEG(0x00011800E0000500ull)
 182 +#define CVMX_AGL_GMX_TX_JAM \
 183 +        CVMX_ADD_IO_SEG(0x00011800E0000490ull)
 184 +#define CVMX_AGL_GMX_TX_LFSR \
 185 +        CVMX_ADD_IO_SEG(0x00011800E00004F8ull)
 186 +#define CVMX_AGL_GMX_TX_OVR_BP \
 187 +        CVMX_ADD_IO_SEG(0x00011800E00004C8ull)
 188 +#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC \
 189 +        CVMX_ADD_IO_SEG(0x00011800E00004A0ull)
 190 +#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE \
 191 +        CVMX_ADD_IO_SEG(0x00011800E00004A8ull)
 192 +
 193 +union cvmx_agl_gmx_bad_reg {
 194 +       uint64_t u64;
 195 +       struct cvmx_agl_gmx_bad_reg_s {
 196 +               uint64_t reserved_38_63:26;
 197 +               uint64_t txpsh1:1;
 198 +               uint64_t txpop1:1;
 199 +               uint64_t ovrflw1:1;
 200 +               uint64_t txpsh:1;
 201 +               uint64_t txpop:1;
 202 +               uint64_t ovrflw:1;
 203 +               uint64_t reserved_27_31:5;
 204 +               uint64_t statovr:1;
 205 +               uint64_t reserved_23_25:3;
 206 +               uint64_t loststat:1;
 207 +               uint64_t reserved_4_21:18;
 208 +               uint64_t out_ovr:2;
 209 +               uint64_t reserved_0_1:2;
 210 +       } s;
 211 +       struct cvmx_agl_gmx_bad_reg_s cn52xx;
 212 +       struct cvmx_agl_gmx_bad_reg_s cn52xxp1;
 213 +       struct cvmx_agl_gmx_bad_reg_cn56xx {
 214 +               uint64_t reserved_35_63:29;
 215 +               uint64_t txpsh:1;
 216 +               uint64_t txpop:1;
 217 +               uint64_t ovrflw:1;
 218 +               uint64_t reserved_27_31:5;
 219 +               uint64_t statovr:1;
 220 +               uint64_t reserved_23_25:3;
 221 +               uint64_t loststat:1;
 222 +               uint64_t reserved_3_21:19;
 223 +               uint64_t out_ovr:1;
 224 +               uint64_t reserved_0_1:2;
 225 +       } cn56xx;
 226 +       struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;
 227 +};
 228 +
 229 +union cvmx_agl_gmx_bist {
 230 +       uint64_t u64;
 231 +       struct cvmx_agl_gmx_bist_s {
 232 +               uint64_t reserved_10_63:54;
 233 +               uint64_t status:10;
 234 +       } s;
 235 +       struct cvmx_agl_gmx_bist_s cn52xx;
 236 +       struct cvmx_agl_gmx_bist_s cn52xxp1;
 237 +       struct cvmx_agl_gmx_bist_s cn56xx;
 238 +       struct cvmx_agl_gmx_bist_s cn56xxp1;
 239 +};
 240 +
 241 +union cvmx_agl_gmx_drv_ctl {
 242 +       uint64_t u64;
 243 +       struct cvmx_agl_gmx_drv_ctl_s {
 244 +               uint64_t reserved_49_63:15;
 245 +               uint64_t byp_en1:1;
 246 +               uint64_t reserved_45_47:3;
 247 +               uint64_t pctl1:5;
 248 +               uint64_t reserved_37_39:3;
 249 +               uint64_t nctl1:5;
 250 +               uint64_t reserved_17_31:15;
 251 +               uint64_t byp_en:1;
 252 +               uint64_t reserved_13_15:3;
 253 +               uint64_t pctl:5;
 254 +               uint64_t reserved_5_7:3;
 255 +               uint64_t nctl:5;
 256 +       } s;
 257 +       struct cvmx_agl_gmx_drv_ctl_s cn52xx;
 258 +       struct cvmx_agl_gmx_drv_ctl_s cn52xxp1;
 259 +       struct cvmx_agl_gmx_drv_ctl_cn56xx {
 260 +               uint64_t reserved_17_63:47;
 261 +               uint64_t byp_en:1;
 262 +               uint64_t reserved_13_15:3;
 263 +               uint64_t pctl:5;
 264 +               uint64_t reserved_5_7:3;
 265 +               uint64_t nctl:5;
 266 +       } cn56xx;
 267 +       struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1;
 268 +};
 269 +
 270 +union cvmx_agl_gmx_inf_mode {
 271 +       uint64_t u64;
 272 +       struct cvmx_agl_gmx_inf_mode_s {
 273 +               uint64_t reserved_2_63:62;
 274 +               uint64_t en:1;
 275 +               uint64_t reserved_0_0:1;
 276 +       } s;
 277 +       struct cvmx_agl_gmx_inf_mode_s cn52xx;
 278 +       struct cvmx_agl_gmx_inf_mode_s cn52xxp1;
 279 +       struct cvmx_agl_gmx_inf_mode_s cn56xx;
 280 +       struct cvmx_agl_gmx_inf_mode_s cn56xxp1;
 281 +};
 282 +
 283 +union cvmx_agl_gmx_prtx_cfg {
 284 +       uint64_t u64;
 285 +       struct cvmx_agl_gmx_prtx_cfg_s {
 286 +               uint64_t reserved_6_63:58;
 287 +               uint64_t tx_en:1;
 288 +               uint64_t rx_en:1;
 289 +               uint64_t slottime:1;
 290 +               uint64_t duplex:1;
 291 +               uint64_t speed:1;
 292 +               uint64_t en:1;
 293 +       } s;
 294 +       struct cvmx_agl_gmx_prtx_cfg_s cn52xx;
 295 +       struct cvmx_agl_gmx_prtx_cfg_s cn52xxp1;
 296 +       struct cvmx_agl_gmx_prtx_cfg_s cn56xx;
 297 +       struct cvmx_agl_gmx_prtx_cfg_s cn56xxp1;
 298 +};
 299 +
 300 +union cvmx_agl_gmx_rxx_adr_cam0 {
 301 +       uint64_t u64;
 302 +       struct cvmx_agl_gmx_rxx_adr_cam0_s {
 303 +               uint64_t adr:64;
 304 +       } s;
 305 +       struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx;
 306 +       struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;
 307 +       struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;
 308 +       struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;
 309 +};
 310 +
 311 +union cvmx_agl_gmx_rxx_adr_cam1 {
 312 +       uint64_t u64;
 313 +       struct cvmx_agl_gmx_rxx_adr_cam1_s {
 314 +               uint64_t adr:64;
 315 +       } s;
 316 +       struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx;
 317 +       struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;
 318 +       struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;
 319 +       struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;
 320 +};
 321 +
 322 +union cvmx_agl_gmx_rxx_adr_cam2 {
 323 +       uint64_t u64;
 324 +       struct cvmx_agl_gmx_rxx_adr_cam2_s {
 325 +               uint64_t adr:64;
 326 +       } s;
 327 +       struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx;
 328 +       struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;
 329 +       struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;
 330 +       struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;
 331 +};
 332 +
 333 +union cvmx_agl_gmx_rxx_adr_cam3 {
 334 +       uint64_t u64;
 335 +       struct cvmx_agl_gmx_rxx_adr_cam3_s {
 336 +               uint64_t adr:64;
 337 +       } s;
 338 +       struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx;
 339 +       struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;
 340 +       struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;
 341 +       struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;
 342 +};
 343 +
 344 +union cvmx_agl_gmx_rxx_adr_cam4 {
 345 +       uint64_t u64;
 346 +       struct cvmx_agl_gmx_rxx_adr_cam4_s {
 347 +               uint64_t adr:64;
 348 +       } s;
 349 +       struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx;
 350 +       struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;
 351 +       struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;
 352 +       struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;
 353 +};
 354 +
 355 +union cvmx_agl_gmx_rxx_adr_cam5 {
 356 +       uint64_t u64;
 357 +       struct cvmx_agl_gmx_rxx_adr_cam5_s {
 358 +               uint64_t adr:64;
 359 +       } s;
 360 +       struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx;
 361 +       struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;
 362 +       struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;
 363 +       struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;
 364 +};
 365 +
 366 +union cvmx_agl_gmx_rxx_adr_cam_en {
 367 +       uint64_t u64;
 368 +       struct cvmx_agl_gmx_rxx_adr_cam_en_s {
 369 +               uint64_t reserved_8_63:56;
 370 +               uint64_t en:8;
 371 +       } s;
 372 +       struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx;
 373 +       struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
 374 +       struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
 375 +       struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
 376 +};
 377 +
 378 +union cvmx_agl_gmx_rxx_adr_ctl {
 379 +       uint64_t u64;
 380 +       struct cvmx_agl_gmx_rxx_adr_ctl_s {
 381 +               uint64_t reserved_4_63:60;
 382 +               uint64_t cam_mode:1;
 383 +               uint64_t mcst:2;
 384 +               uint64_t bcst:1;
 385 +       } s;
 386 +       struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx;
 387 +       struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;
 388 +       struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;
 389 +       struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;
 390 +};
 391 +
 392 +union cvmx_agl_gmx_rxx_decision {
 393 +       uint64_t u64;
 394 +       struct cvmx_agl_gmx_rxx_decision_s {
 395 +               uint64_t reserved_5_63:59;
 396 +               uint64_t cnt:5;
 397 +       } s;
 398 +       struct cvmx_agl_gmx_rxx_decision_s cn52xx;
 399 +       struct cvmx_agl_gmx_rxx_decision_s cn52xxp1;
 400 +       struct cvmx_agl_gmx_rxx_decision_s cn56xx;
 401 +       struct cvmx_agl_gmx_rxx_decision_s cn56xxp1;
 402 +};
 403 +
 404 +union cvmx_agl_gmx_rxx_frm_chk {
 405 +       uint64_t u64;
 406 +       struct cvmx_agl_gmx_rxx_frm_chk_s {
 407 +               uint64_t reserved_9_63:55;
 408 +               uint64_t skperr:1;
 409 +               uint64_t rcverr:1;
 410 +               uint64_t lenerr:1;
 411 +               uint64_t alnerr:1;
 412 +               uint64_t fcserr:1;
 413 +               uint64_t jabber:1;
 414 +               uint64_t maxerr:1;
 415 +               uint64_t reserved_1_1:1;
 416 +               uint64_t minerr:1;
 417 +       } s;
 418 +       struct cvmx_agl_gmx_rxx_frm_chk_s cn52xx;
 419 +       struct cvmx_agl_gmx_rxx_frm_chk_s cn52xxp1;
 420 +       struct cvmx_agl_gmx_rxx_frm_chk_s cn56xx;
 421 +       struct cvmx_agl_gmx_rxx_frm_chk_s cn56xxp1;
 422 +};
 423 +
 424 +union cvmx_agl_gmx_rxx_frm_ctl {
 425 +       uint64_t u64;
 426 +       struct cvmx_agl_gmx_rxx_frm_ctl_s {
 427 +               uint64_t reserved_10_63:54;
 428 +               uint64_t pre_align:1;
 429 +               uint64_t pad_len:1;
 430 +               uint64_t vlan_len:1;
 431 +               uint64_t pre_free:1;
 432 +               uint64_t ctl_smac:1;
 433 +               uint64_t ctl_mcst:1;
 434 +               uint64_t ctl_bck:1;
 435 +               uint64_t ctl_drp:1;
 436 +               uint64_t pre_strp:1;
 437 +               uint64_t pre_chk:1;
 438 +       } s;
 439 +       struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xx;
 440 +       struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xxp1;
 441 +       struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xx;
 442 +       struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xxp1;
 443 +};
 444 +
 445 +union cvmx_agl_gmx_rxx_frm_max {
 446 +       uint64_t u64;
 447 +       struct cvmx_agl_gmx_rxx_frm_max_s {
 448 +               uint64_t reserved_16_63:48;
 449 +               uint64_t len:16;
 450 +       } s;
 451 +       struct cvmx_agl_gmx_rxx_frm_max_s cn52xx;
 452 +       struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;
 453 +       struct cvmx_agl_gmx_rxx_frm_max_s cn56xx;
 454 +       struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;
 455 +};
 456 +
 457 +union cvmx_agl_gmx_rxx_frm_min {
 458 +       uint64_t u64;
 459 +       struct cvmx_agl_gmx_rxx_frm_min_s {
 460 +               uint64_t reserved_16_63:48;
 461 +               uint64_t len:16;
 462 +       } s;
 463 +       struct cvmx_agl_gmx_rxx_frm_min_s cn52xx;
 464 +       struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;
 465 +       struct cvmx_agl_gmx_rxx_frm_min_s cn56xx;
 466 +       struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;
 467 +};
 468 +
 469 +union cvmx_agl_gmx_rxx_ifg {
 470 +       uint64_t u64;
 471 +       struct cvmx_agl_gmx_rxx_ifg_s {
 472 +               uint64_t reserved_4_63:60;
 473 +               uint64_t ifg:4;
 474 +       } s;
 475 +       struct cvmx_agl_gmx_rxx_ifg_s cn52xx;
 476 +       struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;
 477 +       struct cvmx_agl_gmx_rxx_ifg_s cn56xx;
 478 +       struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;
 479 +};
 480 +
 481 +union cvmx_agl_gmx_rxx_int_en {
 482 +       uint64_t u64;
 483 +       struct cvmx_agl_gmx_rxx_int_en_s {
 484 +               uint64_t reserved_20_63:44;
 485 +               uint64_t pause_drp:1;
 486 +               uint64_t reserved_16_18:3;
 487 +               uint64_t ifgerr:1;
 488 +               uint64_t coldet:1;
 489 +               uint64_t falerr:1;
 490 +               uint64_t rsverr:1;
 491 +               uint64_t pcterr:1;
 492 +               uint64_t ovrerr:1;
 493 +               uint64_t reserved_9_9:1;
 494 +               uint64_t skperr:1;
 495 +               uint64_t rcverr:1;
 496 +               uint64_t lenerr:1;
 497 +               uint64_t alnerr:1;
 498 +               uint64_t fcserr:1;
 499 +               uint64_t jabber:1;
 500 +               uint64_t maxerr:1;
 501 +               uint64_t reserved_1_1:1;
 502 +               uint64_t minerr:1;
 503 +       } s;
 504 +       struct cvmx_agl_gmx_rxx_int_en_s cn52xx;
 505 +       struct cvmx_agl_gmx_rxx_int_en_s cn52xxp1;
 506 +       struct cvmx_agl_gmx_rxx_int_en_s cn56xx;
 507 +       struct cvmx_agl_gmx_rxx_int_en_s cn56xxp1;
 508 +};
 509 +
 510 +union cvmx_agl_gmx_rxx_int_reg {
 511 +       uint64_t u64;
 512 +       struct cvmx_agl_gmx_rxx_int_reg_s {
 513 +               uint64_t reserved_20_63:44;
 514 +               uint64_t pause_drp:1;
 515 +               uint64_t reserved_16_18:3;
 516 +               uint64_t ifgerr:1;
 517 +               uint64_t coldet:1;
 518 +               uint64_t falerr:1;
 519 +               uint64_t rsverr:1;
 520 +               uint64_t pcterr:1;
 521 +               uint64_t ovrerr:1;
 522 +               uint64_t reserved_9_9:1;
 523 +               uint64_t skperr:1;
 524 +               uint64_t rcverr:1;
 525 +               uint64_t lenerr:1;
 526 +               uint64_t alnerr:1;
 527 +               uint64_t fcserr:1;
 528 +               uint64_t jabber:1;
 529 +               uint64_t maxerr:1;
 530 +               uint64_t reserved_1_1:1;
 531 +               uint64_t minerr:1;
 532 +       } s;
 533 +       struct cvmx_agl_gmx_rxx_int_reg_s cn52xx;
 534 +       struct cvmx_agl_gmx_rxx_int_reg_s cn52xxp1;
 535 +       struct cvmx_agl_gmx_rxx_int_reg_s cn56xx;
 536 +       struct cvmx_agl_gmx_rxx_int_reg_s cn56xxp1;
 537 +};
 538 +
 539 +union cvmx_agl_gmx_rxx_jabber {
 540 +       uint64_t u64;
 541 +       struct cvmx_agl_gmx_rxx_jabber_s {
 542 +               uint64_t reserved_16_63:48;
 543 +               uint64_t cnt:16;
 544 +       } s;
 545 +       struct cvmx_agl_gmx_rxx_jabber_s cn52xx;
 546 +       struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;
 547 +       struct cvmx_agl_gmx_rxx_jabber_s cn56xx;
 548 +       struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;
 549 +};
 550 +
 551 +union cvmx_agl_gmx_rxx_pause_drop_time {
 552 +       uint64_t u64;
 553 +       struct cvmx_agl_gmx_rxx_pause_drop_time_s {
 554 +               uint64_t reserved_16_63:48;
 555 +               uint64_t status:16;
 556 +       } s;
 557 +       struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx;
 558 +       struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
 559 +       struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
 560 +       struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
 561 +};
 562 +
 563 +union cvmx_agl_gmx_rxx_stats_ctl {
 564 +       uint64_t u64;
 565 +       struct cvmx_agl_gmx_rxx_stats_ctl_s {
 566 +               uint64_t reserved_1_63:63;
 567 +               uint64_t rd_clr:1;
 568 +       } s;
 569 +       struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx;
 570 +       struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;
 571 +       struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;
 572 +       struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;
 573 +};
 574 +
 575 +union cvmx_agl_gmx_rxx_stats_octs {
 576 +       uint64_t u64;
 577 +       struct cvmx_agl_gmx_rxx_stats_octs_s {
 578 +               uint64_t reserved_48_63:16;
 579 +               uint64_t cnt:48;
 580 +       } s;
 581 +       struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx;
 582 +       struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
 583 +       struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
 584 +       struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
 585 +};
 586 +
 587 +union cvmx_agl_gmx_rxx_stats_octs_ctl {
 588 +       uint64_t u64;
 589 +       struct cvmx_agl_gmx_rxx_stats_octs_ctl_s {
 590 +               uint64_t reserved_48_63:16;
 591 +               uint64_t cnt:48;
 592 +       } s;
 593 +       struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx;
 594 +       struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
 595 +       struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
 596 +       struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
 597 +};
 598 +
 599 +union cvmx_agl_gmx_rxx_stats_octs_dmac {
 600 +       uint64_t u64;
 601 +       struct cvmx_agl_gmx_rxx_stats_octs_dmac_s {
 602 +               uint64_t reserved_48_63:16;
 603 +               uint64_t cnt:48;
 604 +       } s;
 605 +       struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx;
 606 +       struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
 607 +       struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
 608 +       struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
 609 +};
 610 +
 611 +union cvmx_agl_gmx_rxx_stats_octs_drp {
 612 +       uint64_t u64;
 613 +       struct cvmx_agl_gmx_rxx_stats_octs_drp_s {
 614 +               uint64_t reserved_48_63:16;
 615 +               uint64_t cnt:48;
 616 +       } s;
 617 +       struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx;
 618 +       struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
 619 +       struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
 620 +       struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
 621 +};
 622 +
 623 +union cvmx_agl_gmx_rxx_stats_pkts {
 624 +       uint64_t u64;
 625 +       struct cvmx_agl_gmx_rxx_stats_pkts_s {
 626 +               uint64_t reserved_32_63:32;
 627 +               uint64_t cnt:32;
 628 +       } s;
 629 +       struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx;
 630 +       struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
 631 +       struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
 632 +       struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
 633 +};
 634 +
 635 +union cvmx_agl_gmx_rxx_stats_pkts_bad {
 636 +       uint64_t u64;
 637 +       struct cvmx_agl_gmx_rxx_stats_pkts_bad_s {
 638 +               uint64_t reserved_32_63:32;
 639 +               uint64_t cnt:32;
 640 +       } s;
 641 +       struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx;
 642 +       struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
 643 +       struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
 644 +       struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
 645 +};
 646 +
 647 +union cvmx_agl_gmx_rxx_stats_pkts_ctl {
 648 +       uint64_t u64;
 649 +       struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s {
 650 +               uint64_t reserved_32_63:32;
 651 +               uint64_t cnt:32;
 652 +       } s;
 653 +       struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx;
 654 +       struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
 655 +       struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
 656 +       struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
 657 +};
 658 +
 659 +union cvmx_agl_gmx_rxx_stats_pkts_dmac {
 660 +       uint64_t u64;
 661 +       struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s {
 662 +               uint64_t reserved_32_63:32;
 663 +               uint64_t cnt:32;
 664 +       } s;
 665 +       struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx;
 666 +       struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
 667 +       struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
 668 +       struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
 669 +};
 670 +
 671 +union cvmx_agl_gmx_rxx_stats_pkts_drp {
 672 +       uint64_t u64;
 673 +       struct cvmx_agl_gmx_rxx_stats_pkts_drp_s {
 674 +               uint64_t reserved_32_63:32;
 675 +               uint64_t cnt:32;
 676 +       } s;
 677 +       struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx;
 678 +       struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
 679 +       struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
 680 +       struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
 681 +};
 682 +
 683 +union cvmx_agl_gmx_rxx_udd_skp {
 684 +       uint64_t u64;
 685 +       struct cvmx_agl_gmx_rxx_udd_skp_s {
 686 +               uint64_t reserved_9_63:55;
 687 +               uint64_t fcssel:1;
 688 +               uint64_t reserved_7_7:1;
 689 +               uint64_t len:7;
 690 +       } s;
 691 +       struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx;
 692 +       struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;
 693 +       struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;
 694 +       struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;
 695 +};
 696 +
 697 +union cvmx_agl_gmx_rx_bp_dropx {
 698 +       uint64_t u64;
 699 +       struct cvmx_agl_gmx_rx_bp_dropx_s {
 700 +               uint64_t reserved_6_63:58;
 701 +               uint64_t mark:6;
 702 +       } s;
 703 +       struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx;
 704 +       struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;
 705 +       struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;
 706 +       struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;
 707 +};
 708 +
 709 +union cvmx_agl_gmx_rx_bp_offx {
 710 +       uint64_t u64;
 711 +       struct cvmx_agl_gmx_rx_bp_offx_s {
 712 +               uint64_t reserved_6_63:58;
 713 +               uint64_t mark:6;
 714 +       } s;
 715 +       struct cvmx_agl_gmx_rx_bp_offx_s cn52xx;
 716 +       struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;
 717 +       struct cvmx_agl_gmx_rx_bp_offx_s cn56xx;
 718 +       struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;
 719 +};
 720 +
 721 +union cvmx_agl_gmx_rx_bp_onx {
 722 +       uint64_t u64;
 723 +       struct cvmx_agl_gmx_rx_bp_onx_s {
 724 +               uint64_t reserved_9_63:55;
 725 +               uint64_t mark:9;
 726 +       } s;
 727 +       struct cvmx_agl_gmx_rx_bp_onx_s cn52xx;
 728 +       struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;
 729 +       struct cvmx_agl_gmx_rx_bp_onx_s cn56xx;
 730 +       struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;
 731 +};
 732 +
 733 +union cvmx_agl_gmx_rx_prt_info {
 734 +       uint64_t u64;
 735 +       struct cvmx_agl_gmx_rx_prt_info_s {
 736 +               uint64_t reserved_18_63:46;
 737 +               uint64_t drop:2;
 738 +               uint64_t reserved_2_15:14;
 739 +               uint64_t commit:2;
 740 +       } s;
 741 +       struct cvmx_agl_gmx_rx_prt_info_s cn52xx;
 742 +       struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1;
 743 +       struct cvmx_agl_gmx_rx_prt_info_cn56xx {
 744 +               uint64_t reserved_17_63:47;
 745 +               uint64_t drop:1;
 746 +               uint64_t reserved_1_15:15;
 747 +               uint64_t commit:1;
 748 +       } cn56xx;
 749 +       struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
 750 +};
 751 +
 752 +union cvmx_agl_gmx_rx_tx_status {
 753 +       uint64_t u64;
 754 +       struct cvmx_agl_gmx_rx_tx_status_s {
 755 +               uint64_t reserved_6_63:58;
 756 +               uint64_t tx:2;
 757 +               uint64_t reserved_2_3:2;
 758 +               uint64_t rx:2;
 759 +       } s;
 760 +       struct cvmx_agl_gmx_rx_tx_status_s cn52xx;
 761 +       struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1;
 762 +       struct cvmx_agl_gmx_rx_tx_status_cn56xx {
 763 +               uint64_t reserved_5_63:59;
 764 +               uint64_t tx:1;
 765 +               uint64_t reserved_1_3:3;
 766 +               uint64_t rx:1;
 767 +       } cn56xx;
 768 +       struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
 769 +};
 770 +
 771 +union cvmx_agl_gmx_smacx {
 772 +       uint64_t u64;
 773 +       struct cvmx_agl_gmx_smacx_s {
 774 +               uint64_t reserved_48_63:16;
 775 +               uint64_t smac:48;
 776 +       } s;
 777 +       struct cvmx_agl_gmx_smacx_s cn52xx;
 778 +       struct cvmx_agl_gmx_smacx_s cn52xxp1;
 779 +       struct cvmx_agl_gmx_smacx_s cn56xx;
 780 +       struct cvmx_agl_gmx_smacx_s cn56xxp1;
 781 +};
 782 +
 783 +union cvmx_agl_gmx_stat_bp {
 784 +       uint64_t u64;
 785 +       struct cvmx_agl_gmx_stat_bp_s {
 786 +               uint64_t reserved_17_63:47;
 787 +               uint64_t bp:1;
 788 +               uint64_t cnt:16;
 789 +       } s;
 790 +       struct cvmx_agl_gmx_stat_bp_s cn52xx;
 791 +       struct cvmx_agl_gmx_stat_bp_s cn52xxp1;
 792 +       struct cvmx_agl_gmx_stat_bp_s cn56xx;
 793 +       struct cvmx_agl_gmx_stat_bp_s cn56xxp1;
 794 +};
 795 +
 796 +union cvmx_agl_gmx_txx_append {
 797 +       uint64_t u64;
 798 +       struct cvmx_agl_gmx_txx_append_s {
 799 +               uint64_t reserved_4_63:60;
 800 +               uint64_t force_fcs:1;
 801 +               uint64_t fcs:1;
 802 +               uint64_t pad:1;
 803 +               uint64_t preamble:1;
 804 +       } s;
 805 +       struct cvmx_agl_gmx_txx_append_s cn52xx;
 806 +       struct cvmx_agl_gmx_txx_append_s cn52xxp1;
 807 +       struct cvmx_agl_gmx_txx_append_s cn56xx;
 808 +       struct cvmx_agl_gmx_txx_append_s cn56xxp1;
 809 +};
 810 +
 811 +union cvmx_agl_gmx_txx_ctl {
 812 +       uint64_t u64;
 813 +       struct cvmx_agl_gmx_txx_ctl_s {
 814 +               uint64_t reserved_2_63:62;
 815 +               uint64_t xsdef_en:1;
 816 +               uint64_t xscol_en:1;
 817 +       } s;
 818 +       struct cvmx_agl_gmx_txx_ctl_s cn52xx;
 819 +       struct cvmx_agl_gmx_txx_ctl_s cn52xxp1;
 820 +       struct cvmx_agl_gmx_txx_ctl_s cn56xx;
 821 +       struct cvmx_agl_gmx_txx_ctl_s cn56xxp1;
 822 +};
 823 +
 824 +union cvmx_agl_gmx_txx_min_pkt {
 825 +       uint64_t u64;
 826 +       struct cvmx_agl_gmx_txx_min_pkt_s {
 827 +               uint64_t reserved_8_63:56;
 828 +               uint64_t min_size:8;
 829 +       } s;
 830 +       struct cvmx_agl_gmx_txx_min_pkt_s cn52xx;
 831 +       struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1;
 832 +       struct cvmx_agl_gmx_txx_min_pkt_s cn56xx;
 833 +       struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1;
 834 +};
 835 +
 836 +union cvmx_agl_gmx_txx_pause_pkt_interval {
 837 +       uint64_t u64;
 838 +       struct cvmx_agl_gmx_txx_pause_pkt_interval_s {
 839 +               uint64_t reserved_16_63:48;
 840 +               uint64_t interval:16;
 841 +       } s;
 842 +       struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx;
 843 +       struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
 844 +       struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
 845 +       struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
 846 +};
 847 +
 848 +union cvmx_agl_gmx_txx_pause_pkt_time {
 849 +       uint64_t u64;
 850 +       struct cvmx_agl_gmx_txx_pause_pkt_time_s {
 851 +               uint64_t reserved_16_63:48;
 852 +               uint64_t time:16;
 853 +       } s;
 854 +       struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx;
 855 +       struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
 856 +       struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
 857 +       struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
 858 +};
 859 +
 860 +union cvmx_agl_gmx_txx_pause_togo {
 861 +       uint64_t u64;
 862 +       struct cvmx_agl_gmx_txx_pause_togo_s {
 863 +               uint64_t reserved_16_63:48;
 864 +               uint64_t time:16;
 865 +       } s;
 866 +       struct cvmx_agl_gmx_txx_pause_togo_s cn52xx;
 867 +       struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
 868 +       struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
 869 +       struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
 870 +};
 871 +
 872 +union cvmx_agl_gmx_txx_pause_zero {
 873 +       uint64_t u64;
 874 +       struct cvmx_agl_gmx_txx_pause_zero_s {
 875 +               uint64_t reserved_1_63:63;
 876 +               uint64_t send:1;
 877 +       } s;
 878 +       struct cvmx_agl_gmx_txx_pause_zero_s cn52xx;
 879 +       struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
 880 +       struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
 881 +       struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
 882 +};
 883 +
 884 +union cvmx_agl_gmx_txx_soft_pause {
 885 +       uint64_t u64;
 886 +       struct cvmx_agl_gmx_txx_soft_pause_s {
 887 +               uint64_t reserved_16_63:48;
 888 +               uint64_t time:16;
 889 +       } s;
 890 +       struct cvmx_agl_gmx_txx_soft_pause_s cn52xx;
 891 +       struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
 892 +       struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
 893 +       struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
 894 +};
 895 +
 896 +union cvmx_agl_gmx_txx_stat0 {
 897 +       uint64_t u64;
 898 +       struct cvmx_agl_gmx_txx_stat0_s {
 899 +               uint64_t xsdef:32;
 900 +               uint64_t xscol:32;
 901 +       } s;
 902 +       struct cvmx_agl_gmx_txx_stat0_s cn52xx;
 903 +       struct cvmx_agl_gmx_txx_stat0_s cn52xxp1;
 904 +       struct cvmx_agl_gmx_txx_stat0_s cn56xx;
 905 +       struct cvmx_agl_gmx_txx_stat0_s cn56xxp1;
 906 +};
 907 +
 908 +union cvmx_agl_gmx_txx_stat1 {
 909 +       uint64_t u64;
 910 +       struct cvmx_agl_gmx_txx_stat1_s {
 911 +               uint64_t scol:32;
 912 +               uint64_t mcol:32;
 913 +       } s;
 914 +       struct cvmx_agl_gmx_txx_stat1_s cn52xx;
 915 +       struct cvmx_agl_gmx_txx_stat1_s cn52xxp1;
 916 +       struct cvmx_agl_gmx_txx_stat1_s cn56xx;
 917 +       struct cvmx_agl_gmx_txx_stat1_s cn56xxp1;
 918 +};
 919 +
 920 +union cvmx_agl_gmx_txx_stat2 {
 921 +       uint64_t u64;
 922 +       struct cvmx_agl_gmx_txx_stat2_s {
 923 +               uint64_t reserved_48_63:16;
 924 +               uint64_t octs:48;
 925 +       } s;
 926 +       struct cvmx_agl_gmx_txx_stat2_s cn52xx;
 927 +       struct cvmx_agl_gmx_txx_stat2_s cn52xxp1;
 928 +       struct cvmx_agl_gmx_txx_stat2_s cn56xx;
 929 +       struct cvmx_agl_gmx_txx_stat2_s cn56xxp1;
 930 +};
 931 +
 932 +union cvmx_agl_gmx_txx_stat3 {
 933 +       uint64_t u64;
 934 +       struct cvmx_agl_gmx_txx_stat3_s {
 935 +               uint64_t reserved_32_63:32;
 936 +               uint64_t pkts:32;
 937 +       } s;
 938 +       struct cvmx_agl_gmx_txx_stat3_s cn52xx;
 939 +       struct cvmx_agl_gmx_txx_stat3_s cn52xxp1;
 940 +       struct cvmx_agl_gmx_txx_stat3_s cn56xx;
 941 +       struct cvmx_agl_gmx_txx_stat3_s cn56xxp1;
 942 +};
 943 +
 944 +union cvmx_agl_gmx_txx_stat4 {
 945 +       uint64_t u64;
 946 +       struct cvmx_agl_gmx_txx_stat4_s {
 947 +               uint64_t hist1:32;
 948 +               uint64_t hist0:32;
 949 +       } s;
 950 +       struct cvmx_agl_gmx_txx_stat4_s cn52xx;
 951 +       struct cvmx_agl_gmx_txx_stat4_s cn52xxp1;
 952 +       struct cvmx_agl_gmx_txx_stat4_s cn56xx;
 953 +       struct cvmx_agl_gmx_txx_stat4_s cn56xxp1;
 954 +};
 955 +
 956 +union cvmx_agl_gmx_txx_stat5 {
 957 +       uint64_t u64;
 958 +       struct cvmx_agl_gmx_txx_stat5_s {
 959 +               uint64_t hist3:32;
 960 +               uint64_t hist2:32;
 961 +       } s;
 962 +       struct cvmx_agl_gmx_txx_stat5_s cn52xx;
 963 +       struct cvmx_agl_gmx_txx_stat5_s cn52xxp1;
 964 +       struct cvmx_agl_gmx_txx_stat5_s cn56xx;
 965 +       struct cvmx_agl_gmx_txx_stat5_s cn56xxp1;
 966 +};
 967 +
 968 +union cvmx_agl_gmx_txx_stat6 {
 969 +       uint64_t u64;
 970 +       struct cvmx_agl_gmx_txx_stat6_s {
 971 +               uint64_t hist5:32;
 972 +               uint64_t hist4:32;
 973 +       } s;
 974 +       struct cvmx_agl_gmx_txx_stat6_s cn52xx;
 975 +       struct cvmx_agl_gmx_txx_stat6_s cn52xxp1;
 976 +       struct cvmx_agl_gmx_txx_stat6_s cn56xx;
 977 +       struct cvmx_agl_gmx_txx_stat6_s cn56xxp1;
 978 +};
 979 +
 980 +union cvmx_agl_gmx_txx_stat7 {
 981 +       uint64_t u64;
 982 +       struct cvmx_agl_gmx_txx_stat7_s {
 983 +               uint64_t hist7:32;
 984 +               uint64_t hist6:32;
 985 +       } s;
 986 +       struct cvmx_agl_gmx_txx_stat7_s cn52xx;
 987 +       struct cvmx_agl_gmx_txx_stat7_s cn52xxp1;
 988 +       struct cvmx_agl_gmx_txx_stat7_s cn56xx;
 989 +       struct cvmx_agl_gmx_txx_stat7_s cn56xxp1;
 990 +};
 991 +
 992 +union cvmx_agl_gmx_txx_stat8 {
 993 +       uint64_t u64;
 994 +       struct cvmx_agl_gmx_txx_stat8_s {
 995 +               uint64_t mcst:32;
 996 +               uint64_t bcst:32;
 997 +       } s;
 998 +       struct cvmx_agl_gmx_txx_stat8_s cn52xx;
 999 +       struct cvmx_agl_gmx_txx_stat8_s cn52xxp1;
1000 +       struct cvmx_agl_gmx_txx_stat8_s cn56xx;
1001 +       struct cvmx_agl_gmx_txx_stat8_s cn56xxp1;
1002 +};
1003 +
1004 +union cvmx_agl_gmx_txx_stat9 {
1005 +       uint64_t u64;
1006 +       struct cvmx_agl_gmx_txx_stat9_s {
1007 +               uint64_t undflw:32;
1008 +               uint64_t ctl:32;
1009 +       } s;
1010 +       struct cvmx_agl_gmx_txx_stat9_s cn52xx;
1011 +       struct cvmx_agl_gmx_txx_stat9_s cn52xxp1;
1012 +       struct cvmx_agl_gmx_txx_stat9_s cn56xx;
1013 +       struct cvmx_agl_gmx_txx_stat9_s cn56xxp1;
1014 +};
1015 +
1016 +union cvmx_agl_gmx_txx_stats_ctl {
1017 +       uint64_t u64;
1018 +       struct cvmx_agl_gmx_txx_stats_ctl_s {
1019 +               uint64_t reserved_1_63:63;
1020 +               uint64_t rd_clr:1;
1021 +       } s;
1022 +       struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx;
1023 +       struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1;
1024 +       struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx;
1025 +       struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1;
1026 +};
1027 +
1028 +union cvmx_agl_gmx_txx_thresh {
1029 +       uint64_t u64;
1030 +       struct cvmx_agl_gmx_txx_thresh_s {
1031 +               uint64_t reserved_6_63:58;
1032 +               uint64_t cnt:6;
1033 +       } s;
1034 +       struct cvmx_agl_gmx_txx_thresh_s cn52xx;
1035 +       struct cvmx_agl_gmx_txx_thresh_s cn52xxp1;
1036 +       struct cvmx_agl_gmx_txx_thresh_s cn56xx;
1037 +       struct cvmx_agl_gmx_txx_thresh_s cn56xxp1;
1038 +};
1039 +
1040 +union cvmx_agl_gmx_tx_bp {
1041 +       uint64_t u64;
1042 +       struct cvmx_agl_gmx_tx_bp_s {
1043 +               uint64_t reserved_2_63:62;
1044 +               uint64_t bp:2;
1045 +       } s;
1046 +       struct cvmx_agl_gmx_tx_bp_s cn52xx;
1047 +       struct cvmx_agl_gmx_tx_bp_s cn52xxp1;
1048 +       struct cvmx_agl_gmx_tx_bp_cn56xx {
1049 +               uint64_t reserved_1_63:63;
1050 +               uint64_t bp:1;
1051 +       } cn56xx;
1052 +       struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1;
1053 +};
1054 +
1055 +union cvmx_agl_gmx_tx_col_attempt {
1056 +       uint64_t u64;
1057 +       struct cvmx_agl_gmx_tx_col_attempt_s {
1058 +               uint64_t reserved_5_63:59;
1059 +               uint64_t limit:5;
1060 +       } s;
1061 +       struct cvmx_agl_gmx_tx_col_attempt_s cn52xx;
1062 +       struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
1063 +       struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
1064 +       struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
1065 +};
1066 +
1067 +union cvmx_agl_gmx_tx_ifg {
1068 +       uint64_t u64;
1069 +       struct cvmx_agl_gmx_tx_ifg_s {
1070 +               uint64_t reserved_8_63:56;
1071 +               uint64_t ifg2:4;
1072 +               uint64_t ifg1:4;
1073 +       } s;
1074 +       struct cvmx_agl_gmx_tx_ifg_s cn52xx;
1075 +       struct cvmx_agl_gmx_tx_ifg_s cn52xxp1;
1076 +       struct cvmx_agl_gmx_tx_ifg_s cn56xx;
1077 +       struct cvmx_agl_gmx_tx_ifg_s cn56xxp1;
1078 +};
1079 +
1080 +union cvmx_agl_gmx_tx_int_en {
1081 +       uint64_t u64;
1082 +       struct cvmx_agl_gmx_tx_int_en_s {
1083 +               uint64_t reserved_18_63:46;
1084 +               uint64_t late_col:2;
1085 +               uint64_t reserved_14_15:2;
1086 +               uint64_t xsdef:2;
1087 +               uint64_t reserved_10_11:2;
1088 +               uint64_t xscol:2;
1089 +               uint64_t reserved_4_7:4;
1090 +               uint64_t undflw:2;
1091 +               uint64_t reserved_1_1:1;
1092 +               uint64_t pko_nxa:1;
1093 +       } s;
1094 +       struct cvmx_agl_gmx_tx_int_en_s cn52xx;
1095 +       struct cvmx_agl_gmx_tx_int_en_s cn52xxp1;
1096 +       struct cvmx_agl_gmx_tx_int_en_cn56xx {
1097 +               uint64_t reserved_17_63:47;
1098 +               uint64_t late_col:1;
1099 +               uint64_t reserved_13_15:3;
1100 +               uint64_t xsdef:1;
1101 +               uint64_t reserved_9_11:3;
1102 +               uint64_t xscol:1;
1103 +               uint64_t reserved_3_7:5;
1104 +               uint64_t undflw:1;
1105 +               uint64_t reserved_1_1:1;
1106 +               uint64_t pko_nxa:1;
1107 +       } cn56xx;
1108 +       struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
1109 +};
1110 +
1111 +union cvmx_agl_gmx_tx_int_reg {
1112 +       uint64_t u64;
1113 +       struct cvmx_agl_gmx_tx_int_reg_s {
1114 +               uint64_t reserved_18_63:46;
1115 +               uint64_t late_col:2;
1116 +               uint64_t reserved_14_15:2;
1117 +               uint64_t xsdef:2;
1118 +               uint64_t reserved_10_11:2;
1119 +               uint64_t xscol:2;
1120 +               uint64_t reserved_4_7:4;
1121 +               uint64_t undflw:2;
1122 +               uint64_t reserved_1_1:1;
1123 +               uint64_t pko_nxa:1;
1124 +       } s;
1125 +       struct cvmx_agl_gmx_tx_int_reg_s cn52xx;
1126 +       struct cvmx_agl_gmx_tx_int_reg_s cn52xxp1;
1127 +       struct cvmx_agl_gmx_tx_int_reg_cn56xx {
1128 +               uint64_t reserved_17_63:47;
1129 +               uint64_t late_col:1;
1130 +               uint64_t reserved_13_15:3;
1131 +               uint64_t xsdef:1;
1132 +               uint64_t reserved_9_11:3;
1133 +               uint64_t xscol:1;
1134 +               uint64_t reserved_3_7:5;
1135 +               uint64_t undflw:1;
1136 +               uint64_t reserved_1_1:1;
1137 +               uint64_t pko_nxa:1;
1138 +       } cn56xx;
1139 +       struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
1140 +};
1141 +
1142 +union cvmx_agl_gmx_tx_jam {
1143 +       uint64_t u64;
1144 +       struct cvmx_agl_gmx_tx_jam_s {
1145 +               uint64_t reserved_8_63:56;
1146 +               uint64_t jam:8;
1147 +       } s;
1148 +       struct cvmx_agl_gmx_tx_jam_s cn52xx;
1149 +       struct cvmx_agl_gmx_tx_jam_s cn52xxp1;
1150 +       struct cvmx_agl_gmx_tx_jam_s cn56xx;
1151 +       struct cvmx_agl_gmx_tx_jam_s cn56xxp1;
1152 +};
1153 +
1154 +union cvmx_agl_gmx_tx_lfsr {
1155 +       uint64_t u64;
1156 +       struct cvmx_agl_gmx_tx_lfsr_s {
1157 +               uint64_t reserved_16_63:48;
1158 +               uint64_t lfsr:16;
1159 +       } s;
1160 +       struct cvmx_agl_gmx_tx_lfsr_s cn52xx;
1161 +       struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1;
1162 +       struct cvmx_agl_gmx_tx_lfsr_s cn56xx;
1163 +       struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1;
1164 +};
1165 +
1166 +union cvmx_agl_gmx_tx_ovr_bp {
1167 +       uint64_t u64;
1168 +       struct cvmx_agl_gmx_tx_ovr_bp_s {
1169 +               uint64_t reserved_10_63:54;
1170 +               uint64_t en:2;
1171 +               uint64_t reserved_6_7:2;
1172 +               uint64_t bp:2;
1173 +               uint64_t reserved_2_3:2;
1174 +               uint64_t ign_full:2;
1175 +       } s;
1176 +       struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx;
1177 +       struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1;
1178 +       struct cvmx_agl_gmx_tx_ovr_bp_cn56xx {
1179 +               uint64_t reserved_9_63:55;
1180 +               uint64_t en:1;
1181 +               uint64_t reserved_5_7:3;
1182 +               uint64_t bp:1;
1183 +               uint64_t reserved_1_3:3;
1184 +               uint64_t ign_full:1;
1185 +       } cn56xx;
1186 +       struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
1187 +};
1188 +
1189 +union cvmx_agl_gmx_tx_pause_pkt_dmac {
1190 +       uint64_t u64;
1191 +       struct cvmx_agl_gmx_tx_pause_pkt_dmac_s {
1192 +               uint64_t reserved_48_63:16;
1193 +               uint64_t dmac:48;
1194 +       } s;
1195 +       struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx;
1196 +       struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
1197 +       struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
1198 +       struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
1199 +};
1200 +
1201 +union cvmx_agl_gmx_tx_pause_pkt_type {
1202 +       uint64_t u64;
1203 +       struct cvmx_agl_gmx_tx_pause_pkt_type_s {
1204 +               uint64_t reserved_16_63:48;
1205 +               uint64_t type:16;
1206 +       } s;
1207 +       struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx;
1208 +       struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
1209 +       struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
1210 +       struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
1211 +};
1212 +
1213 +#endif
1214 diff --git a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
1215 new file mode 100644
1216 index 0000000..dab6dca
1217 --- /dev/null
1218 +++ b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
1219 @@ -0,0 +1,248 @@
1220 +/***********************license start***************
1221 + * Author: Cavium Networks
1222 + *
1223 + * Contact: support@caviumnetworks.com
1224 + * This file is part of the OCTEON SDK
1225 + *
1226 + * Copyright (c) 2003-2008 Cavium Networks
1227 + *
1228 + * This file is free software; you can redistribute it and/or modify
1229 + * it under the terms of the GNU General Public License, Version 2, as
1230 + * published by the Free Software Foundation.
1231 + *
1232 + * This file is distributed in the hope that it will be useful, but
1233 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
1234 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
1235 + * NONINFRINGEMENT.  See the GNU General Public License for more
1236 + * details.
1237 + *
1238 + * You should have received a copy of the GNU General Public License
1239 + * along with this file; if not, write to the Free Software
1240 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
1241 + * or visit http://www.gnu.org/licenses/.
1242 + *
1243 + * This file may also be available under a different license from Cavium.
1244 + * Contact Cavium Networks for more information
1245 + ***********************license end**************************************/
1246 +
1247 +#ifndef __CVMX_MIXX_DEFS_H__
1248 +#define __CVMX_MIXX_DEFS_H__
1249 +
1250 +#define CVMX_MIXX_BIST(offset) \
1251 +        CVMX_ADD_IO_SEG(0x0001070000100078ull + (((offset) & 1) * 2048))
1252 +#define CVMX_MIXX_CTL(offset) \
1253 +        CVMX_ADD_IO_SEG(0x0001070000100020ull + (((offset) & 1) * 2048))
1254 +#define CVMX_MIXX_INTENA(offset) \
1255 +        CVMX_ADD_IO_SEG(0x0001070000100050ull + (((offset) & 1) * 2048))
1256 +#define CVMX_MIXX_IRCNT(offset) \
1257 +        CVMX_ADD_IO_SEG(0x0001070000100030ull + (((offset) & 1) * 2048))
1258 +#define CVMX_MIXX_IRHWM(offset) \
1259 +        CVMX_ADD_IO_SEG(0x0001070000100028ull + (((offset) & 1) * 2048))
1260 +#define CVMX_MIXX_IRING1(offset) \
1261 +        CVMX_ADD_IO_SEG(0x0001070000100010ull + (((offset) & 1) * 2048))
1262 +#define CVMX_MIXX_IRING2(offset) \
1263 +        CVMX_ADD_IO_SEG(0x0001070000100018ull + (((offset) & 1) * 2048))
1264 +#define CVMX_MIXX_ISR(offset) \
1265 +        CVMX_ADD_IO_SEG(0x0001070000100048ull + (((offset) & 1) * 2048))
1266 +#define CVMX_MIXX_ORCNT(offset) \
1267 +        CVMX_ADD_IO_SEG(0x0001070000100040ull + (((offset) & 1) * 2048))
1268 +#define CVMX_MIXX_ORHWM(offset) \
1269 +        CVMX_ADD_IO_SEG(0x0001070000100038ull + (((offset) & 1) * 2048))
1270 +#define CVMX_MIXX_ORING1(offset) \
1271 +        CVMX_ADD_IO_SEG(0x0001070000100000ull + (((offset) & 1) * 2048))
1272 +#define CVMX_MIXX_ORING2(offset) \
1273 +        CVMX_ADD_IO_SEG(0x0001070000100008ull + (((offset) & 1) * 2048))
1274 +#define CVMX_MIXX_REMCNT(offset) \
1275 +        CVMX_ADD_IO_SEG(0x0001070000100058ull + (((offset) & 1) * 2048))
1276 +
1277 +union cvmx_mixx_bist {
1278 +       uint64_t u64;
1279 +       struct cvmx_mixx_bist_s {
1280 +               uint64_t reserved_4_63:60;
1281 +               uint64_t mrqdat:1;
1282 +               uint64_t ipfdat:1;
1283 +               uint64_t irfdat:1;
1284 +               uint64_t orfdat:1;
1285 +       } s;
1286 +       struct cvmx_mixx_bist_s cn52xx;
1287 +       struct cvmx_mixx_bist_s cn52xxp1;
1288 +       struct cvmx_mixx_bist_s cn56xx;
1289 +       struct cvmx_mixx_bist_s cn56xxp1;
1290 +};
1291 +
1292 +union cvmx_mixx_ctl {
1293 +       uint64_t u64;
1294 +       struct cvmx_mixx_ctl_s {
1295 +               uint64_t reserved_8_63:56;
1296 +               uint64_t crc_strip:1;
1297 +               uint64_t busy:1;
1298 +               uint64_t en:1;
1299 +               uint64_t reset:1;
1300 +               uint64_t lendian:1;
1301 +               uint64_t nbtarb:1;
1302 +               uint64_t mrq_hwm:2;
1303 +       } s;
1304 +       struct cvmx_mixx_ctl_s cn52xx;
1305 +       struct cvmx_mixx_ctl_s cn52xxp1;
1306 +       struct cvmx_mixx_ctl_s cn56xx;
1307 +       struct cvmx_mixx_ctl_s cn56xxp1;
1308 +};
1309 +
1310 +union cvmx_mixx_intena {
1311 +       uint64_t u64;
1312 +       struct cvmx_mixx_intena_s {
1313 +               uint64_t reserved_7_63:57;
1314 +               uint64_t orunena:1;
1315 +               uint64_t irunena:1;
1316 +               uint64_t data_drpena:1;
1317 +               uint64_t ithena:1;
1318 +               uint64_t othena:1;
1319 +               uint64_t ivfena:1;
1320 +               uint64_t ovfena:1;
1321 +       } s;
1322 +       struct cvmx_mixx_intena_s cn52xx;
1323 +       struct cvmx_mixx_intena_s cn52xxp1;
1324 +       struct cvmx_mixx_intena_s cn56xx;
1325 +       struct cvmx_mixx_intena_s cn56xxp1;
1326 +};
1327 +
1328 +union cvmx_mixx_ircnt {
1329 +       uint64_t u64;
1330 +       struct cvmx_mixx_ircnt_s {
1331 +               uint64_t reserved_20_63:44;
1332 +               uint64_t ircnt:20;
1333 +       } s;
1334 +       struct cvmx_mixx_ircnt_s cn52xx;
1335 +       struct cvmx_mixx_ircnt_s cn52xxp1;
1336 +       struct cvmx_mixx_ircnt_s cn56xx;
1337 +       struct cvmx_mixx_ircnt_s cn56xxp1;
1338 +};
1339 +
1340 +union cvmx_mixx_irhwm {
1341 +       uint64_t u64;
1342 +       struct cvmx_mixx_irhwm_s {
1343 +               uint64_t reserved_40_63:24;
1344 +               uint64_t ibplwm:20;
1345 +               uint64_t irhwm:20;
1346 +       } s;
1347 +       struct cvmx_mixx_irhwm_s cn52xx;
1348 +       struct cvmx_mixx_irhwm_s cn52xxp1;
1349 +       struct cvmx_mixx_irhwm_s cn56xx;
1350 +       struct cvmx_mixx_irhwm_s cn56xxp1;
1351 +};
1352 +
1353 +union cvmx_mixx_iring1 {
1354 +       uint64_t u64;
1355 +       struct cvmx_mixx_iring1_s {
1356 +               uint64_t reserved_60_63:4;
1357 +               uint64_t isize:20;
1358 +               uint64_t reserved_36_39:4;
1359 +               uint64_t ibase:33;
1360 +               uint64_t reserved_0_2:3;
1361 +       } s;
1362 +       struct cvmx_mixx_iring1_s cn52xx;
1363 +       struct cvmx_mixx_iring1_s cn52xxp1;
1364 +       struct cvmx_mixx_iring1_s cn56xx;
1365 +       struct cvmx_mixx_iring1_s cn56xxp1;
1366 +};
1367 +
1368 +union cvmx_mixx_iring2 {
1369 +       uint64_t u64;
1370 +       struct cvmx_mixx_iring2_s {
1371 +               uint64_t reserved_52_63:12;
1372 +               uint64_t itlptr:20;
1373 +               uint64_t reserved_20_31:12;
1374 +               uint64_t idbell:20;
1375 +       } s;
1376 +       struct cvmx_mixx_iring2_s cn52xx;
1377 +       struct cvmx_mixx_iring2_s cn52xxp1;
1378 +       struct cvmx_mixx_iring2_s cn56xx;
1379 +       struct cvmx_mixx_iring2_s cn56xxp1;
1380 +};
1381 +
1382 +union cvmx_mixx_isr {
1383 +       uint64_t u64;
1384 +       struct cvmx_mixx_isr_s {
1385 +               uint64_t reserved_7_63:57;
1386 +               uint64_t orun:1;
1387 +               uint64_t irun:1;
1388 +               uint64_t data_drp:1;
1389 +               uint64_t irthresh:1;
1390 +               uint64_t orthresh:1;
1391 +               uint64_t idblovf:1;
1392 +               uint64_t odblovf:1;
1393 +       } s;
1394 +       struct cvmx_mixx_isr_s cn52xx;
1395 +       struct cvmx_mixx_isr_s cn52xxp1;
1396 +       struct cvmx_mixx_isr_s cn56xx;
1397 +       struct cvmx_mixx_isr_s cn56xxp1;
1398 +};
1399 +
1400 +union cvmx_mixx_orcnt {
1401 +       uint64_t u64;
1402 +       struct cvmx_mixx_orcnt_s {
1403 +               uint64_t reserved_20_63:44;
1404 +               uint64_t orcnt:20;
1405 +       } s;
1406 +       struct cvmx_mixx_orcnt_s cn52xx;
1407 +       struct cvmx_mixx_orcnt_s cn52xxp1;
1408 +       struct cvmx_mixx_orcnt_s cn56xx;
1409 +       struct cvmx_mixx_orcnt_s cn56xxp1;
1410 +};
1411 +
1412 +union cvmx_mixx_orhwm {
1413 +       uint64_t u64;
1414 +       struct cvmx_mixx_orhwm_s {
1415 +               uint64_t reserved_20_63:44;
1416 +               uint64_t orhwm:20;
1417 +       } s;
1418 +       struct cvmx_mixx_orhwm_s cn52xx;
1419 +       struct cvmx_mixx_orhwm_s cn52xxp1;
1420 +       struct cvmx_mixx_orhwm_s cn56xx;
1421 +       struct cvmx_mixx_orhwm_s cn56xxp1;
1422 +};
1423 +
1424 +union cvmx_mixx_oring1 {
1425 +       uint64_t u64;
1426 +       struct cvmx_mixx_oring1_s {
1427 +               uint64_t reserved_60_63:4;
1428 +               uint64_t osize:20;
1429 +               uint64_t reserved_36_39:4;
1430 +               uint64_t obase:33;
1431 +               uint64_t reserved_0_2:3;
1432 +       } s;
1433 +       struct cvmx_mixx_oring1_s cn52xx;
1434 +       struct cvmx_mixx_oring1_s cn52xxp1;
1435 +       struct cvmx_mixx_oring1_s cn56xx;
1436 +       struct cvmx_mixx_oring1_s cn56xxp1;
1437 +};
1438 +
1439 +union cvmx_mixx_oring2 {
1440 +       uint64_t u64;
1441 +       struct cvmx_mixx_oring2_s {
1442 +               uint64_t reserved_52_63:12;
1443 +               uint64_t otlptr:20;
1444 +               uint64_t reserved_20_31:12;
1445 +               uint64_t odbell:20;
1446 +       } s;
1447 +       struct cvmx_mixx_oring2_s cn52xx;
1448 +       struct cvmx_mixx_oring2_s cn52xxp1;
1449 +       struct cvmx_mixx_oring2_s cn56xx;
1450 +       struct cvmx_mixx_oring2_s cn56xxp1;
1451 +};
1452 +
1453 +union cvmx_mixx_remcnt {
1454 +       uint64_t u64;
1455 +       struct cvmx_mixx_remcnt_s {
1456 +               uint64_t reserved_52_63:12;
1457 +               uint64_t iremcnt:20;
1458 +               uint64_t reserved_20_31:12;
1459 +               uint64_t oremcnt:20;
1460 +       } s;
1461 +       struct cvmx_mixx_remcnt_s cn52xx;
1462 +       struct cvmx_mixx_remcnt_s cn52xxp1;
1463 +       struct cvmx_mixx_remcnt_s cn56xx;
1464 +       struct cvmx_mixx_remcnt_s cn56xxp1;
1465 +};
1466 +
1467 +#endif
1468 diff --git a/arch/mips/include/asm/octeon/cvmx-smix-defs.h b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
1469 new file mode 100644
1470 index 0000000..9ae45fc
1471 --- /dev/null
1472 +++ b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
1473 @@ -0,0 +1,178 @@
1474 +/***********************license start***************
1475 + * Author: Cavium Networks
1476 + *
1477 + * Contact: support@caviumnetworks.com
1478 + * This file is part of the OCTEON SDK
1479 + *
1480 + * Copyright (c) 2003-2008 Cavium Networks
1481 + *
1482 + * This file is free software; you can redistribute it and/or modify
1483 + * it under the terms of the GNU General Public License, Version 2, as
1484 + * published by the Free Software Foundation.
1485 + *
1486 + * This file is distributed in the hope that it will be useful, but
1487 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
1488 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
1489 + * NONINFRINGEMENT.  See the GNU General Public License for more
1490 + * details.
1491 + *
1492 + * You should have received a copy of the GNU General Public License
1493 + * along with this file; if not, write to the Free Software
1494 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
1495 + * or visit http://www.gnu.org/licenses/.
1496 + *
1497 + * This file may also be available under a different license from Cavium.
1498 + * Contact Cavium Networks for more information
1499 + ***********************license end**************************************/
1500 +
1501 +#ifndef __CVMX_SMIX_DEFS_H__
1502 +#define __CVMX_SMIX_DEFS_H__
1503 +
1504 +#define CVMX_SMIX_CLK(offset) \
1505 +        CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256))
1506 +#define CVMX_SMIX_CMD(offset) \
1507 +        CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256))
1508 +#define CVMX_SMIX_EN(offset) \
1509 +        CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256))
1510 +#define CVMX_SMIX_RD_DAT(offset) \
1511 +        CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256))
1512 +#define CVMX_SMIX_WR_DAT(offset) \
1513 +        CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256))
1514 +
1515 +union cvmx_smix_clk {
1516 +       uint64_t u64;
1517 +       struct cvmx_smix_clk_s {
1518 +               uint64_t reserved_25_63:39;
1519 +               uint64_t mode:1;
1520 +               uint64_t reserved_21_23:3;
1521 +               uint64_t sample_hi:5;
1522 +               uint64_t sample_mode:1;
1523 +               uint64_t reserved_14_14:1;
1524 +               uint64_t clk_idle:1;
1525 +               uint64_t preamble:1;
1526 +               uint64_t sample:4;
1527 +               uint64_t phase:8;
1528 +       } s;
1529 +       struct cvmx_smix_clk_cn30xx {
1530 +               uint64_t reserved_21_63:43;
1531 +               uint64_t sample_hi:5;
1532 +               uint64_t reserved_14_15:2;
1533 +               uint64_t clk_idle:1;
1534 +               uint64_t preamble:1;
1535 +               uint64_t sample:4;
1536 +               uint64_t phase:8;
1537 +       } cn30xx;
1538 +       struct cvmx_smix_clk_cn30xx cn31xx;
1539 +       struct cvmx_smix_clk_cn30xx cn38xx;
1540 +       struct cvmx_smix_clk_cn30xx cn38xxp2;
1541 +       struct cvmx_smix_clk_cn50xx {
1542 +               uint64_t reserved_25_63:39;
1543 +               uint64_t mode:1;
1544 +               uint64_t reserved_21_23:3;
1545 +               uint64_t sample_hi:5;
1546 +               uint64_t reserved_14_15:2;
1547 +               uint64_t clk_idle:1;
1548 +               uint64_t preamble:1;
1549 +               uint64_t sample:4;
1550 +               uint64_t phase:8;
1551 +       } cn50xx;
1552 +       struct cvmx_smix_clk_s cn52xx;
1553 +       struct cvmx_smix_clk_cn50xx cn52xxp1;
1554 +       struct cvmx_smix_clk_s cn56xx;
1555 +       struct cvmx_smix_clk_cn50xx cn56xxp1;
1556 +       struct cvmx_smix_clk_cn30xx cn58xx;
1557 +       struct cvmx_smix_clk_cn30xx cn58xxp1;
1558 +};
1559 +
1560 +union cvmx_smix_cmd {
1561 +       uint64_t u64;
1562 +       struct cvmx_smix_cmd_s {
1563 +               uint64_t reserved_18_63:46;
1564 +               uint64_t phy_op:2;
1565 +               uint64_t reserved_13_15:3;
1566 +               uint64_t phy_adr:5;
1567 +               uint64_t reserved_5_7:3;
1568 +               uint64_t reg_adr:5;
1569 +       } s;
1570 +       struct cvmx_smix_cmd_cn30xx {
1571 +               uint64_t reserved_17_63:47;
1572 +               uint64_t phy_op:1;
1573 +               uint64_t reserved_13_15:3;
1574 +               uint64_t phy_adr:5;
1575 +               uint64_t reserved_5_7:3;
1576 +               uint64_t reg_adr:5;
1577 +       } cn30xx;
1578 +       struct cvmx_smix_cmd_cn30xx cn31xx;
1579 +       struct cvmx_smix_cmd_cn30xx cn38xx;
1580 +       struct cvmx_smix_cmd_cn30xx cn38xxp2;
1581 +       struct cvmx_smix_cmd_s cn50xx;
1582 +       struct cvmx_smix_cmd_s cn52xx;
1583 +       struct cvmx_smix_cmd_s cn52xxp1;
1584 +       struct cvmx_smix_cmd_s cn56xx;
1585 +       struct cvmx_smix_cmd_s cn56xxp1;
1586 +       struct cvmx_smix_cmd_cn30xx cn58xx;
1587 +       struct cvmx_smix_cmd_cn30xx cn58xxp1;
1588 +};
1589 +
1590 +union cvmx_smix_en {
1591 +       uint64_t u64;
1592 +       struct cvmx_smix_en_s {
1593 +               uint64_t reserved_1_63:63;
1594 +               uint64_t en:1;
1595 +       } s;
1596 +       struct cvmx_smix_en_s cn30xx;
1597 +       struct cvmx_smix_en_s cn31xx;
1598 +       struct cvmx_smix_en_s cn38xx;
1599 +       struct cvmx_smix_en_s cn38xxp2;
1600 +       struct cvmx_smix_en_s cn50xx;
1601 +       struct cvmx_smix_en_s cn52xx;
1602 +       struct cvmx_smix_en_s cn52xxp1;
1603 +       struct cvmx_smix_en_s cn56xx;
1604 +       struct cvmx_smix_en_s cn56xxp1;
1605 +       struct cvmx_smix_en_s cn58xx;
1606 +       struct cvmx_smix_en_s cn58xxp1;
1607 +};
1608 +
1609 +union cvmx_smix_rd_dat {
1610 +       uint64_t u64;
1611 +       struct cvmx_smix_rd_dat_s {
1612 +               uint64_t reserved_18_63:46;
1613 +               uint64_t pending:1;
1614 +               uint64_t val:1;
1615 +               uint64_t dat:16;
1616 +       } s;
1617 +       struct cvmx_smix_rd_dat_s cn30xx;
1618 +       struct cvmx_smix_rd_dat_s cn31xx;
1619 +       struct cvmx_smix_rd_dat_s cn38xx;
1620 +       struct cvmx_smix_rd_dat_s cn38xxp2;
1621 +       struct cvmx_smix_rd_dat_s cn50xx;
1622 +       struct cvmx_smix_rd_dat_s cn52xx;
1623 +       struct cvmx_smix_rd_dat_s cn52xxp1;
1624 +       struct cvmx_smix_rd_dat_s cn56xx;
1625 +       struct cvmx_smix_rd_dat_s cn56xxp1;
1626 +       struct cvmx_smix_rd_dat_s cn58xx;
1627 +       struct cvmx_smix_rd_dat_s cn58xxp1;
1628 +};
1629 +
1630 +union cvmx_smix_wr_dat {
1631 +       uint64_t u64;
1632 +       struct cvmx_smix_wr_dat_s {
1633 +               uint64_t reserved_18_63:46;
1634 +               uint64_t pending:1;
1635 +               uint64_t val:1;
1636 +               uint64_t dat:16;
1637 +       } s;
1638 +       struct cvmx_smix_wr_dat_s cn30xx;
1639 +       struct cvmx_smix_wr_dat_s cn31xx;
1640 +       struct cvmx_smix_wr_dat_s cn38xx;
1641 +       struct cvmx_smix_wr_dat_s cn38xxp2;
1642 +       struct cvmx_smix_wr_dat_s cn50xx;
1643 +       struct cvmx_smix_wr_dat_s cn52xx;
1644 +       struct cvmx_smix_wr_dat_s cn52xxp1;
1645 +       struct cvmx_smix_wr_dat_s cn56xx;
1646 +       struct cvmx_smix_wr_dat_s cn56xxp1;
1647 +       struct cvmx_smix_wr_dat_s cn58xx;
1648 +       struct cvmx_smix_wr_dat_s cn58xxp1;
1649 +};
1650 +
1651 +#endif
1652 --
1653 1.5.6.5
1654
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