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[openwrt.git] / target / linux / coldfire / patches / 047-m547x_8x_fec_cleanup.patch
1 From 5bac5f471fb1124c51a5811757c54174f6224e7e Mon Sep 17 00:00:00 2001
2 From: Kurt Mahan <kmahan@freescale.com>
3 Date: Wed, 12 Mar 2008 17:13:29 -0600
4 Subject: [PATCH] Clean up FEC DMA driver.
5
6 LTIBName: m547x-8x-fec-cleanup
7 Signed-off-by: Kurt Mahan <kmahan@freescale.com>
8 ---
9 drivers/net/fec/fec.c | 611 +++++++++++++++++++++---------------------------
10 1 files changed, 267 insertions(+), 344 deletions(-)
11
12 --- a/drivers/net/fec/fec.c
13 +++ b/drivers/net/fec/fec.c
14 @@ -4,7 +4,6 @@
15 *
16 * Code crunched to get it to work on 2.6.24 -- FEC cleanup coming
17 * soon -- Kurt Mahan
18 - *
19 */
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 @@ -44,42 +43,40 @@
23 #undef FEC_2
24 #endif
25
26 -#define VERSION "0.13"
27 +#define VERSION "0.20"
28 MODULE_DESCRIPTION( "DMA Fast Ethernet Controller driver ver " VERSION);
29
30 -// Private structure
31 +/* fec private */
32 struct fec_priv {
33 struct net_device *netdev; /* owning net device */
34 - void* fecpriv_txbuf[FEC_TX_BUF_NUMBER]; //Array of transmission buffers
35 - MCD_bufDescFec *fecpriv_txdesc; // Array of transmission descriptors
36 - volatile unsigned int fecpriv_current_tx; // Inex of the transmission descriptor that is used by DMA
37 - volatile unsigned int fecpriv_next_tx; // Inex of the transmission descriptor that can be used for new data
38 - unsigned int fecpriv_current_rx; // Index of the reception descriptor that is used by DMA
39 - MCD_bufDescFec *fecpriv_rxdesc; // Array of reception descriptors
40 -// unsigned char *fecpriv_rxbuf; // Address of reception buffers
41 - struct sk_buff *askb_rx[FEC_RX_BUF_NUMBER]; // Array of reception skb structure pointers
42 - unsigned int fecpriv_initiator_rx; // Reception DMA initiator
43 - unsigned int fecpriv_initiator_tx; // Transmission DMA initiator
44 - int fecpriv_fec_rx_channel; // DMA reception channel
45 - int fecpriv_fec_tx_channel; // DMA transmission channel
46 - int fecpriv_rx_requestor; // DMA reception requestor
47 - int fecpriv_tx_requestor; // DMA transmission requestor
48 - void *fecpriv_interrupt_fec_rx_handler; // DMA reception handler
49 - void *fecpriv_interrupt_fec_tx_handler; // DMA transmission handler
50 - unsigned char *fecpriv_mac_addr; // Private copy of FEC address
51 - struct net_device_stats fecpriv_stat; // Pointer to the statistical information
52 + void* fecpriv_txbuf[FEC_TX_BUF_NUMBER]; /* tx buffer ptrs */
53 + MCD_bufDescFec *fecpriv_txdesc; /* tx descriptor ptrs */
54 + volatile unsigned int fecpriv_current_tx; /* current tx desc index */
55 + volatile unsigned int fecpriv_next_tx; /* next tx desc index */
56 + unsigned int fecpriv_current_rx; /* current rx desc index */
57 + MCD_bufDescFec *fecpriv_rxdesc; /* rx descriptor ptrs */
58 + struct sk_buff *askb_rx[FEC_RX_BUF_NUMBER]; /* rx SKB ptrs */
59 + unsigned int fecpriv_initiator_rx; /* rx dma initiator */
60 + unsigned int fecpriv_initiator_tx; /* tx dma initiator */
61 + int fecpriv_fec_rx_channel; /* rx dma channel */
62 + int fecpriv_fec_tx_channel; /* tx dma channel */
63 + int fecpriv_rx_requestor; /* rx dma requestor */
64 + int fecpriv_tx_requestor; /* tx dma requestor */
65 + void *fecpriv_interrupt_fec_rx_handler; /* dma rx handler */
66 + void *fecpriv_interrupt_fec_tx_handler; /* dma tx handler */
67 + unsigned char *fecpriv_mac_addr; /* private fec mac addr */
68 + struct net_device_stats fecpriv_stat; /* stats ptr */
69 spinlock_t fecpriv_lock;
70 int fecpriv_rxflag;
71 struct tasklet_struct fecpriv_tasklet_reinit;
72 - int index;
73 + int index; /* fec hw number */
74 };
75
76 struct net_device *fec_dev[FEC_MAX_PORTS];
77
78 -// FEC functions
79 +/* FEC functions */
80 int __init fec_init(void);
81 struct net_device_stats *fec_get_stat(struct net_device *dev);
82 -
83 int fec_open(struct net_device *dev);
84 int fec_close(struct net_device *nd);
85 int fec_tx(struct sk_buff *skb, struct net_device *dev);
86 @@ -93,10 +90,12 @@ void fec_interrupt_fec_tx_handler_fec0(v
87 void fec_interrupt_fec_rx_handler_fec0(void);
88 void fec_interrupt_fec_reinit(unsigned long data);
89
90 -unsigned char fec_mac_addr_fec0[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x50 }; // Default address of FEC0
91 +/* default fec0 address */
92 +unsigned char fec_mac_addr_fec0[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x50 };
93
94 #ifdef FEC_2
95 -unsigned char fec_mac_addr_fec1[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x51 }; // Default address of FEC1
96 +/* default fec1 address */
97 +unsigned char fec_mac_addr_fec1[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x51 };
98 #endif
99
100 extern unsigned char uboot_enet0[];
101 @@ -111,17 +110,18 @@ int __init fec_mac_setup0 (char *s);
102 #ifdef FEC_2
103 void fec_interrupt_fec_tx_handler_fec1(void);
104 void fec_interrupt_fec_rx_handler_fec1(void);
105 +#endif
106
107 #ifndef MODULE
108 int __init fec_mac_setup1 (char *s);
109 #endif
110
111 -#endif
112 int fec_read_mii(unsigned int base_addr, unsigned int pa, unsigned int ra, unsigned int *data);
113 int fec_write_mii(unsigned int base_addr, unsigned int pa, unsigned int ra, unsigned int data);
114
115 module_init(fec_init);
116 /* module_exit(fec_cleanup); */
117 +
118 __setup("mac0=", fec_mac_setup0);
119
120 #ifdef FEC_2
121 @@ -140,7 +140,6 @@ int fec_enet_init(struct net_device *dev
122 fp->index = index;
123 fp->netdev = dev;
124 fec_dev[ index ] = dev;
125 -printk(KERN_INFO "FEI: index=%d\n", index);
126
127 if (index == 0) {
128 /* disable fec0 */
129 @@ -175,8 +174,6 @@ printk(KERN_INFO "FEI: index=%d\n", inde
130 /* rx descriptors */
131 fp->fecpriv_rxdesc = (void*)FEC_RX_DESC_FEC0;
132
133 -printk(KERN_INFO "FEI: txdesc=0x%p rxdesc=0x%p\n", fp->fecpriv_txdesc, fp->fecpriv_rxdesc);
134 -
135 /* mac addr */
136 if (uboot_enet0[0] || uboot_enet0[1] || uboot_enet0[2] ||
137 uboot_enet0[3] || uboot_enet0[4] || uboot_enet0[5]) {
138 @@ -229,8 +226,6 @@ printk(KERN_INFO "FEI: txdesc=0x%p rxde
139 #endif
140 }
141
142 -printk(KERN_INFO "FEI: index=%d base_addr=0x%lx\n", index, dev->base_addr);
143 -
144 /* clear MIB */
145 memset((void *) (dev->base_addr + 0x200), 0, FEC_MIB_LEN);
146
147 @@ -288,8 +283,7 @@ int __init fec_init(void)
148 int err;
149 DECLARE_MAC_BUF(mac);
150
151 - printk(KERN_INFO "FEC ENET (DMA) Version .00\n");
152 -
153 + printk(KERN_INFO "FEC ENET (DMA) Version %s\n", VERSION);
154
155 for (i = 0; i < FEC_MAX_PORTS; i++) {
156 dev = alloc_etherdev(sizeof(struct fec_priv));
157 @@ -333,7 +327,6 @@ void fec_stop(struct net_device *dev)
158 *
159 * RETURNS: If no error occurs, this function returns zero.
160 *************************************************************************/
161 -
162 int fec_open(struct net_device *dev)
163 {
164 struct fec_priv *fp = netdev_priv(dev);
165 @@ -343,13 +336,10 @@ int fec_open(struct net_device *dev)
166 int channel;
167 int error_code = -EBUSY;
168
169 -printk(KERN_INFO "FECOPEN: index=%d\n", fp->index);
170 -
171 - //Receive the DMA channels
172 + /* Receive the DMA channels */
173 channel = dma_set_channel_fec(fp->fecpriv_rx_requestor);
174
175 - if (channel == -1)
176 - {
177 + if (channel == -1) {
178 printk("Dma channel cannot be reserved\n");
179 goto ERRORS;
180 }
181 @@ -360,60 +350,54 @@ printk(KERN_INFO "FECOPEN: index=%d\n",
182
183 channel = dma_set_channel_fec(fp->fecpriv_tx_requestor);
184
185 - if (channel == -1)
186 - {
187 + if (channel == -1) {
188 printk("Dma channel cannot be reserved\n");
189 goto ERRORS;
190 }
191 -printk(KERN_INFO "FECOPEN2\n");
192
193 fp->fecpriv_fec_tx_channel = channel;
194
195 dma_connect(channel, (int) fp->fecpriv_interrupt_fec_tx_handler);
196
197 - // init tasklet for controller reinitialization
198 + /* init tasklet for controller reinitialization */
199 tasklet_init(&fp->fecpriv_tasklet_reinit, fec_interrupt_fec_reinit, (unsigned long) dev);
200 -printk(KERN_INFO "FECOPEN3\n");
201
202 - // Reset FIFOs
203 + /* Reset FIFOs */
204 FEC_FECFRST(base_addr) |= FEC_SW_RST | FEC_RST_CTL;
205 FEC_FECFRST(base_addr) &= ~FEC_SW_RST;
206
207 - // Reset and disable FEC
208 + /* Reset and disable FEC */
209 FEC_ECR(base_addr) = FEC_ECR_RESET;
210
211 - // Wait
212 udelay(10);
213
214 - // Clear all events
215 + /* Clear all events */
216 FEC_EIR(base_addr) = FEC_EIR_CLEAR;
217
218 - // Reset FIFO status
219 + /* Reset FIFO status */
220 FEC_FECTFSR(base_addr) = FEC_FECTFSR_MSK;
221 FEC_FECRFSR(base_addr) = FEC_FECRFSR_MSK;
222
223 -#if 0
224 -/* JKM -- move into HW init */
225 - // Copy the default address to the device structure
226 - memcpy(dev->dev_addr, fp->fecpriv_mac_addr, ETH_ALEN);
227 -#endif
228 + /* Set the default address */
229 + FEC_PALR(base_addr) = (fp->fecpriv_mac_addr[0] << 24) |
230 + (fp->fecpriv_mac_addr[1] << 16) |
231 + (fp->fecpriv_mac_addr[2] << 8) |
232 + fp->fecpriv_mac_addr[3];
233 + FEC_PAUR(base_addr) = (fp->fecpriv_mac_addr[4] << 24) |
234 + (fp->fecpriv_mac_addr[5] << 16) | 0x8808;
235
236 - // Set the default address
237 - FEC_PALR(base_addr) = (fp->fecpriv_mac_addr[0] << 24) | (fp->fecpriv_mac_addr[1] << 16) | (fp->fecpriv_mac_addr[2] << 8) | fp->fecpriv_mac_addr[3];
238 - FEC_PAUR(base_addr) = (fp->fecpriv_mac_addr[4] << 24) | (fp->fecpriv_mac_addr[5] << 16) | 0x8808;
239 -
240 - // Reset the group address descriptor
241 + /* Reset the group address descriptor */
242 FEC_GALR(base_addr) = 0x00000000;
243 FEC_GAUR(base_addr) = 0x00000000;
244
245 - // Reset the individual address descriptor
246 + /* Reset the individual address descriptor */
247 FEC_IALR(base_addr) = 0x00000000;
248 FEC_IAUR(base_addr) = 0x00000000;
249
250 - // Set the receive control register
251 + /* Set the receive control register */
252 FEC_RCR(base_addr) = FEC_RCR_MAX_FRM_SIZE | FEC_RCR_MII;
253
254 - // Set the receive FIFO control register
255 + /* Set the receive FIFO control register */
256 // FEC_FECRFCR(base_addr) = FEC_FECRFCR_FRM | FEC_FECRFCR_GR | FEC_FECRFCR_MSK;
257 FEC_FECRFCR(base_addr) = FEC_FECRFCR_FRM | FEC_FECRFCR_GR
258 | (FEC_FECRFCR_MSK // disable all but ...
259 @@ -422,10 +406,10 @@ printk(KERN_INFO "FECOPEN3\n");
260 // & ~FEC_FECRFCR_UF // enable FIFO underflow
261 );
262
263 - //Set the receive FIFO alarm register
264 + /* Set the receive FIFO alarm register */
265 FEC_FECRFAR(base_addr) = FEC_FECRFAR_ALARM;
266
267 - // Set the transmit FIFO control register
268 + /* Set the transmit FIFO control register */
269 // FEC_FECTFCR(base_addr) = FEC_FECTFCR_FRM | FEC_FECTFCR_GR | FEC_FECTFCR_MSK;
270 FEC_FECTFCR(base_addr) = FEC_FECTFCR_FRM | FEC_FECTFCR_GR
271 | (FEC_FECTFCR_MSK // disable all but ...
272 @@ -434,16 +418,16 @@ printk(KERN_INFO "FECOPEN3\n");
273 // & ~FEC_FECTFCR_UF // enable FIFO underflow
274 & ~FEC_FECTFCR_OF); // enable FIFO overflow
275
276 - //Set the transmit FIFO alarm register
277 + /* Set the transmit FIFO alarm register */
278 FEC_FECTFAR(base_addr) = FEC_FECTFAR_ALARM;
279
280 - // Set the Tx FIFO watermark
281 + /* Set the Tx FIFO watermark */
282 FEC_FECTFWR(base_addr) = FEC_FECTFWR_XWMRK;
283
284 - // Enable the transmitter to append the CRC
285 + /* Enable the transmitter to append the CRC */
286 FEC_CTCWR(base_addr) = FEC_CTCWR_TFCW_CRC;
287
288 - // Enable the ethernet interrupts
289 + /* Enable the ethernet interrupts */
290 // FEC_EIMR(base_addr) = FEC_EIMR_MASK;
291 FEC_EIMR(base_addr) = FEC_EIMR_DISABLE
292 | FEC_EIR_LC
293 @@ -453,9 +437,16 @@ printk(KERN_INFO "FECOPEN3\n");
294 | FEC_EIR_XFERR
295 | FEC_EIR_RFERR
296 ;
297 -printk(KERN_INFO "FECOPEN4\n");
298
299 -#ifdef CONFIG_FEC_548x_AUTO_NEGOTIATION
300 +/*
301 + * JKM --
302 + *
303 + * There's a problem with the PHY initialization code --
304 + * for now assume uboot left it in an initialized state.
305 + */
306 +// printk(KERN_INFO "FECOPEN: starting auto-negotiation\n");
307 +// #ifdef CONFIG_FEC_548x_AUTO_NEGOTIATION
308 +#if 0
309 if ((error_code = init_transceiver(base_addr, &fduplex)) != 0)
310 {
311 printk("Initialization of the transceiver is failed\n");
312 @@ -464,25 +455,24 @@ printk(KERN_INFO "FECOPEN4\n");
313 #else
314 fduplex = 1;
315 #endif
316 -printk(KERN_INFO "FECOPEN5\n");
317 +// printk(KERN_INFO "FECOPEN: done with auto-negotiation\n");
318
319 if (fduplex)
320 - // Enable the full duplex mode
321 + /* Enable the full duplex mode */
322 FEC_TCR(base_addr) = FEC_TCR_FDEN | FEC_TCR_HBC;
323 else
324 - // Disable reception of frames while transmitting
325 + /* Disable reception of frames while transmitting */
326 FEC_RCR(base_addr) |= FEC_RCR_DRT;
327
328 - // Enable MIB
329 + /* Enable MIB */
330 FEC_MIBC(base_addr) = FEC_MIBC_ENABLE;
331
332 - // Enable FEC
333 + /* Enable FEC */
334 FEC_ECR(base_addr) |= FEC_ECR_ETHEREN;
335
336 - // Initialize transmission descriptors and start DMA for the transmission
337 + /* Initialize tx descriptors and start DMA for the transmission */
338 for (i = 0; i < FEC_TX_BUF_NUMBER; i++)
339 fp->fecpriv_txdesc[i].statCtrl = MCD_FEC_INTERRUPT;
340 -printk(KERN_INFO "FECOPEN6\n");
341
342 fp->fecpriv_txdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
343
344 @@ -494,31 +484,27 @@ printk(KERN_INFO "FECOPEN6\n");
345 FEC_TX_DMA_PRI, MCD_FECTX_DMA | MCD_INTERRUPT,
346 MCD_NO_CSUM | MCD_NO_BYTE_SWAP);
347
348 - // Initialize reception descriptors and start DMA for the reception
349 - for (i = 0; i < FEC_RX_BUF_NUMBER; i++)
350 - {
351 + /* Initialize rx descriptors and start DMA for the reception */
352 + for (i = 0; i < FEC_RX_BUF_NUMBER; i++) {
353 fp->askb_rx[i] = alloc_skb(FEC_MAXBUF_SIZE + 16, GFP_DMA);
354 - if (!fp->askb_rx[i])
355 - {
356 - fp->fecpriv_rxdesc[i].dataPointer = 0;
357 - fp->fecpriv_rxdesc[i].statCtrl = 0;
358 - fp->fecpriv_rxdesc[i].length = 0;
359 + if (!fp->askb_rx[i]) {
360 + fp->fecpriv_rxdesc[i].dataPointer = 0;
361 + fp->fecpriv_rxdesc[i].statCtrl = 0;
362 + fp->fecpriv_rxdesc[i].length = 0;
363 }
364 - else
365 - {
366 - skb_reserve(fp->askb_rx[i], 16);
367 + else {
368 + skb_reserve(fp->askb_rx[i], 16);
369 fp->askb_rx[i]->dev = dev;
370 - fp->fecpriv_rxdesc[i].dataPointer = (unsigned int) virt_to_phys(fp->askb_rx[i]->tail);
371 - fp->fecpriv_rxdesc[i].statCtrl = MCD_FEC_BUF_READY | MCD_FEC_INTERRUPT;
372 - fp->fecpriv_rxdesc[i].length = FEC_MAXBUF_SIZE;
373 - }
374 + fp->fecpriv_rxdesc[i].dataPointer = (unsigned int) virt_to_phys(fp->askb_rx[i]->tail);
375 + fp->fecpriv_rxdesc[i].statCtrl = MCD_FEC_BUF_READY | MCD_FEC_INTERRUPT;
376 + fp->fecpriv_rxdesc[i].length = FEC_MAXBUF_SIZE;
377 + }
378 }
379 -printk(KERN_INFO "FECOPEN7\n");
380
381 fp->fecpriv_rxdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
382 fp->fecpriv_current_rx = 0;
383
384 - // flush entire data cache before restarting the DMA
385 + /* flush entire data cache before restarting the DMA */
386 #if 0
387 /* JKM -- currently running with cache turned off */
388 DcacheFlushInvalidate();
389 @@ -531,31 +517,24 @@ printk(KERN_INFO "FECOPEN7\n");
390 MCD_NO_CSUM | MCD_NO_BYTE_SWAP);
391
392 netif_start_queue(dev);
393 -
394 -// MOD_INC_USE_COUNT;
395 -printk(KERN_INFO "FECOPEN: finished\n");
396 -
397 return 0;
398
399 ERRORS:
400
401 - // Remove the channels and return with the error code
402 - if (fp->fecpriv_fec_rx_channel != -1)
403 - {
404 + /* Remove the channels and return with the error code */
405 + if (fp->fecpriv_fec_rx_channel != -1) {
406 dma_disconnect(fp->fecpriv_fec_rx_channel);
407 dma_remove_channel_by_number(fp->fecpriv_fec_rx_channel);
408 fp->fecpriv_fec_rx_channel = -1;
409 }
410
411 - if (fp->fecpriv_fec_tx_channel != -1)
412 - {
413 + if (fp->fecpriv_fec_tx_channel != -1) {
414 dma_disconnect(fp->fecpriv_fec_tx_channel);
415 dma_remove_channel_by_number(fp->fecpriv_fec_tx_channel);
416 fp->fecpriv_fec_tx_channel = -1;
417 }
418
419 return error_code;
420 -
421 }
422
423 /************************************************************************
424 @@ -568,31 +547,26 @@ ERRORS:
425 *************************************************************************/
426 int fec_close(struct net_device *dev)
427 {
428 - //Receive the pointer to the private structure
429 struct fec_priv *fp = netdev_priv(dev);
430 -
431 - // Receive the base address
432 unsigned long base_addr = (unsigned long) dev->base_addr;
433 -
434 unsigned long time;
435 -
436 int i;
437
438 netif_stop_queue(dev);
439
440 - // Perform the graceful stop
441 + /* Perform the graceful stop */
442 FEC_TCR(base_addr) |= FEC_TCR_GTS;
443
444 time = jiffies;
445
446 - // Wait for the graceful stop
447 + /* Wait for the graceful stop */
448 while (!(FEC_EIR(base_addr) & FEC_EIR_GRA) && jiffies - time < FEC_GR_TIMEOUT * HZ)
449 schedule();
450
451 - // Disable FEC
452 + /* Disable FEC */
453 FEC_ECR(base_addr) = FEC_ECR_DISABLE;
454
455 - // Reset the DMA channels
456 + /* Reset the DMA channels */
457 spin_lock_irq(&fp->fecpriv_lock);
458 MCD_killDma(fp->fecpriv_fec_tx_channel);
459 spin_unlock_irq(&fp->fecpriv_lock);
460 @@ -600,12 +574,12 @@ int fec_close(struct net_device *dev)
461 dma_disconnect(fp->fecpriv_fec_tx_channel);
462 fp->fecpriv_fec_tx_channel = -1;
463
464 - for (i = 0; i < FEC_TX_BUF_NUMBER; i++)
465 - if (fp->fecpriv_txbuf[i])
466 - {
467 + for (i = 0; i < FEC_TX_BUF_NUMBER; i++) {
468 + if (fp->fecpriv_txbuf[i]) {
469 kfree(fp->fecpriv_txbuf[i]);
470 fp->fecpriv_txbuf[i] = NULL;
471 }
472 + }
473
474 spin_lock_irq(&fp->fecpriv_lock);
475 MCD_killDma(fp->fecpriv_fec_rx_channel);
476 @@ -615,15 +589,12 @@ int fec_close(struct net_device *dev)
477 dma_disconnect(fp->fecpriv_fec_rx_channel);
478 fp->fecpriv_fec_rx_channel = -1;
479
480 - for (i = 0; i < FEC_RX_BUF_NUMBER; i++)
481 - {
482 - if (fp->askb_rx[i])
483 - {
484 - kfree_skb(fp->askb_rx[i]);
485 - fp->askb_rx[i] = NULL;
486 - }
487 + for (i = 0; i < FEC_RX_BUF_NUMBER; i++) {
488 + if (fp->askb_rx[i]) {
489 + kfree_skb(fp->askb_rx[i]);
490 + fp->askb_rx[i] = NULL;
491 + }
492 }
493 -// MOD_DEC_USE_COUNT;
494
495 return 0;
496 }
497 @@ -635,14 +606,10 @@ int fec_close(struct net_device *dev)
498 *************************************************************************/
499 struct net_device_stats * fec_get_stat(struct net_device *dev)
500 {
501 -
502 - //Receive the pointer to the private structure
503 struct fec_priv *fp = netdev_priv(dev);
504 -
505 - // Receive the base address
506 unsigned long base_addr = dev->base_addr;
507
508 - // Receive the statistical information
509 + /* Receive the statistical information */
510 fp->fecpriv_stat.rx_packets = FECSTAT_RMON_R_PACKETS(base_addr);
511 fp->fecpriv_stat.tx_packets = FECSTAT_RMON_T_PACKETS(base_addr);
512 fp->fecpriv_stat.rx_bytes = FECSTAT_RMON_R_OCTETS(base_addr);
513 @@ -651,7 +618,10 @@ struct net_device_stats * fec_get_stat(s
514 fp->fecpriv_stat.multicast = FECSTAT_RMON_R_MC_PKT(base_addr);
515 fp->fecpriv_stat.collisions = FECSTAT_RMON_T_COL(base_addr);
516
517 - fp->fecpriv_stat.rx_length_errors = FECSTAT_RMON_R_UNDERSIZE(base_addr) + FECSTAT_RMON_R_OVERSIZE(base_addr) + FECSTAT_RMON_R_FRAG(base_addr) + FECSTAT_RMON_R_JAB(base_addr);
518 + fp->fecpriv_stat.rx_length_errors = FECSTAT_RMON_R_UNDERSIZE(base_addr) +
519 + FECSTAT_RMON_R_OVERSIZE(base_addr) +
520 + FECSTAT_RMON_R_FRAG(base_addr) +
521 + FECSTAT_RMON_R_JAB(base_addr);
522 fp->fecpriv_stat.rx_crc_errors = FECSTAT_IEEE_R_CRC(base_addr);
523 fp->fecpriv_stat.rx_frame_errors = FECSTAT_IEEE_R_ALIGN(base_addr);
524 fp->fecpriv_stat.rx_over_errors = FECSTAT_IEEE_R_MACERR(base_addr);
525 @@ -660,9 +630,18 @@ struct net_device_stats * fec_get_stat(s
526 fp->fecpriv_stat.tx_fifo_errors = FECSTAT_IEEE_T_MACERR(base_addr);
527 fp->fecpriv_stat.tx_window_errors = FECSTAT_IEEE_T_LCOL(base_addr);
528
529 - // I hope that one frame doesn't have more than one error
530 - fp->fecpriv_stat.rx_errors = fp->fecpriv_stat.rx_length_errors + fp->fecpriv_stat.rx_crc_errors + fp->fecpriv_stat.rx_frame_errors + fp->fecpriv_stat.rx_over_errors + fp->fecpriv_stat.rx_dropped;
531 - fp->fecpriv_stat.tx_errors = fp->fecpriv_stat.tx_carrier_errors + fp->fecpriv_stat.tx_fifo_errors + fp->fecpriv_stat.tx_window_errors + fp->fecpriv_stat.tx_aborted_errors + fp->fecpriv_stat.tx_heartbeat_errors + fp->fecpriv_stat.tx_dropped;
532 + /* I hope that one frame doesn't have more than one error */
533 + fp->fecpriv_stat.rx_errors = fp->fecpriv_stat.rx_length_errors +
534 + fp->fecpriv_stat.rx_crc_errors +
535 + fp->fecpriv_stat.rx_frame_errors +
536 + fp->fecpriv_stat.rx_over_errors +
537 + fp->fecpriv_stat.rx_dropped;
538 + fp->fecpriv_stat.tx_errors = fp->fecpriv_stat.tx_carrier_errors +
539 + fp->fecpriv_stat.tx_fifo_errors +
540 + fp->fecpriv_stat.tx_window_errors +
541 + fp->fecpriv_stat.tx_aborted_errors +
542 + fp->fecpriv_stat.tx_heartbeat_errors +
543 + fp->fecpriv_stat.tx_dropped;
544
545 return &fp->fecpriv_stat;
546 }
547 @@ -674,59 +653,47 @@ struct net_device_stats * fec_get_stat(s
548 *************************************************************************/
549 void fec_set_multicast_list(struct net_device *dev)
550 {
551 - // Pointer to the address list
552 struct dev_mc_list *dmi;
553 -
554 unsigned int crc, data;
555 int i, j, k;
556 -
557 - // Receive the base address
558 unsigned long base_addr = (unsigned long) dev->base_addr;
559
560 - if (dev->flags & IFF_PROMISC || dev->flags & IFF_ALLMULTI)
561 - {
562 - // Allow all incoming frames
563 + if (dev->flags & IFF_PROMISC || dev->flags & IFF_ALLMULTI) {
564 + /* Allow all incoming frames */
565 FEC_GALR(base_addr) = 0xFFFFFFFF;
566 FEC_GAUR(base_addr) = 0xFFFFFFFF;
567 return;
568 }
569 - // Reset the group address register
570 +
571 + /* Reset the group address register */
572 FEC_GALR(base_addr) = 0x00000000;
573 FEC_GAUR(base_addr) = 0x00000000;
574
575 - // Process all addresses
576 - for (i = 0, dmi = dev->mc_list; i < dev->mc_count; i++, dmi = dmi->next)
577 - {
578 - // Processing must be only for the group addresses
579 + /* Process all addresses */
580 + for (i = 0, dmi = dev->mc_list; i < dev->mc_count; i++, dmi = dmi->next) {
581 + /* Processing must be only for the group addresses */
582 if (!(dmi->dmi_addr[0] & 1))
583 continue;
584
585 - // Calculate crc value for the current address
586 + /* Calculate crc value for the current address */
587 crc = 0xFFFFFFFF;
588 - for (j = 0; j < dmi->dmi_addrlen; j++)
589 - {
590 -
591 - for (k = 0, data = dmi->dmi_addr[j]; k < 8; k++, data >>= 1)
592 - {
593 + for (j = 0; j < dmi->dmi_addrlen; j++) {
594 + for (k = 0, data = dmi->dmi_addr[j]; k < 8; k++, data >>= 1) {
595 if ((crc ^ data) & 1)
596 crc = (crc >> 1) ^ FEC_CRCPOL;
597 else
598 crc >>= 1;
599 -
600 }
601 -
602 }
603
604 - // Add this value
605 + /* Add this value */
606 crc >>= 26;
607 crc &= 0x3F;
608 if (crc > 31)
609 FEC_GAUR(base_addr) |= 0x1 << (crc - 32);
610 else
611 FEC_GALR(base_addr) |= 0x1 << crc;
612 -
613 }
614 -
615 }
616
617 /************************************************************************
618 @@ -736,26 +703,27 @@ void fec_set_multicast_list(struct net_d
619 *************************************************************************/
620 int fec_set_mac_address(struct net_device *dev, void *p)
621 {
622 - //Receive the pointer to the private structure
623 struct fec_priv *fp = netdev_priv(dev);
624 -
625 - // Receive the base address
626 unsigned long base_addr = (unsigned long) dev->base_addr;
627 -
628 struct sockaddr *addr = p;
629
630 if (netif_running(dev))
631 return -EBUSY;
632
633 - // Copy a new address to the device structure
634 + /* Copy a new address to the device structure */
635 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
636
637 - // Copy a new address to the private structure
638 + /* Copy a new address to the private structure */
639 memcpy(fp->fecpriv_mac_addr, addr->sa_data, 6);
640
641 - // Set the address to the registers
642 - FEC_PALR(base_addr) = (fp->fecpriv_mac_addr[0] << 24) | (fp->fecpriv_mac_addr[1] << 16) | (fp->fecpriv_mac_addr[2] << 8) | fp->fecpriv_mac_addr[3];
643 - FEC_PAUR(base_addr) = (fp->fecpriv_mac_addr[4] << 24) | (fp->fecpriv_mac_addr[5] << 16) | 0x8808;
644 + /* Set the address to the registers */
645 + FEC_PALR(base_addr) = (fp->fecpriv_mac_addr[0] << 24) |
646 + (fp->fecpriv_mac_addr[1] << 16) |
647 + (fp->fecpriv_mac_addr[2] << 8) |
648 + fp->fecpriv_mac_addr[3];
649 + FEC_PAUR(base_addr) = (fp->fecpriv_mac_addr[4] << 24) |
650 + (fp->fecpriv_mac_addr[5] << 16) |
651 + 0x8808;
652
653 return 0;
654 }
655 @@ -769,27 +737,24 @@ int fec_set_mac_address(struct net_devic
656 *************************************************************************/
657 int fec_tx(struct sk_buff *skb, struct net_device *dev)
658 {
659 -
660 - //Receive the pointer to the private structure
661 struct fec_priv *fp = netdev_priv(dev);
662 -
663 void *data, *data_aligned;
664 int offset;
665
666 data = kmalloc(skb->len + 15, GFP_DMA | GFP_ATOMIC);
667
668 - if (!data)
669 - {
670 + if (!data) {
671 fp->fecpriv_stat.tx_dropped++;
672 dev_kfree_skb(skb);
673 return 0;
674 }
675
676 - offset = (((unsigned long)virt_to_phys(data) + 15) & 0xFFFFFFF0) - (unsigned long)virt_to_phys(data);
677 + offset = (((unsigned long)virt_to_phys(data) + 15) & 0xFFFFFFF0) -
678 + (unsigned long)virt_to_phys(data);
679 data_aligned = (void*)((unsigned long)data + offset);
680 memcpy(data_aligned, skb->data, skb->len);
681
682 - // flush data cache before initializing the descriptor and starting DMA
683 + /* flush data cache before initializing the descriptor and starting DMA */
684 #if 0
685 /* JKM -- currently running with cache turned off */
686 DcacheFlushInvalidateCacheBlock((void*)virt_to_phys(data_aligned), skb->len);
687 @@ -797,7 +762,7 @@ int fec_tx(struct sk_buff *skb, struct n
688
689 spin_lock_irq(&fp->fecpriv_lock);
690
691 - // Initialize the descriptor
692 + /* Initialize the descriptor */
693 fp->fecpriv_txbuf[fp->fecpriv_next_tx] = data;
694 fp->fecpriv_txdesc[fp->fecpriv_next_tx].dataPointer = (unsigned int) virt_to_phys(data_aligned);
695 fp->fecpriv_txdesc[fp->fecpriv_next_tx].length = skb->len;
696 @@ -809,7 +774,7 @@ int fec_tx(struct sk_buff *skb, struct n
697
698 spin_unlock_irq(&fp->fecpriv_lock);
699
700 - // Tell the DMA to continue the transmission
701 + /* Tell the DMA to continue the transmission */
702 MCD_continDma(fp->fecpriv_fec_tx_channel);
703
704 dev_kfree_skb(skb);
705 @@ -835,14 +800,10 @@ void fec_tx_timeout(struct net_device *d
706
707 spin_lock_irq(&fp->fecpriv_lock);
708 MCD_killDma(fp->fecpriv_fec_tx_channel);
709 - for (i = 0; i < FEC_TX_BUF_NUMBER; i++)
710 - {
711 - if (fp->fecpriv_txbuf[i])
712 - {
713 -
714 + for (i = 0; i < FEC_TX_BUF_NUMBER; i++) {
715 + if (fp->fecpriv_txbuf[i]) {
716 kfree(fp->fecpriv_txbuf[i]);
717 fp->fecpriv_txbuf[i] = NULL;
718 -
719 }
720 fp->fecpriv_txdesc[i].statCtrl = MCD_FEC_INTERRUPT;
721 }
722 @@ -850,14 +811,14 @@ void fec_tx_timeout(struct net_device *d
723
724 fp->fecpriv_current_tx = fp->fecpriv_next_tx = 0;
725
726 - // Reset FIFOs
727 + /* Reset FIFOs */
728 FEC_FECFRST(base_addr) |= FEC_SW_RST;
729 FEC_FECFRST(base_addr) &= ~FEC_SW_RST;
730
731 - // Reset and disable FEC
732 + /* Reset and disable FEC */
733 // FEC_ECR(base_addr) = FEC_ECR_RESET;
734
735 - // Enable FEC
736 + /* Enable FEC */
737 FEC_ECR(base_addr) |= FEC_ECR_ETHEREN;
738
739 MCD_startDma(fp->fecpriv_fec_tx_channel, (char *) fp->fecpriv_txdesc, 0,
740 @@ -883,23 +844,22 @@ int fec_read_mii(unsigned int base_addr,
741 {
742 unsigned long time;
743
744 - // Clear the MII interrupt bit
745 + /* Clear the MII interrupt bit */
746 FEC_EIR(base_addr) = FEC_EIR_MII;
747
748 - // Write to the MII management frame register
749 + /* Write to the MII management frame register */
750 FEC_MMFR(base_addr) = FEC_MMFR_READ | (pa << 23) | (ra << 18);
751
752 time = jiffies;
753
754 - // Wait for the reading
755 - while (!(FEC_EIR(base_addr) & FEC_EIR_MII))
756 - {
757 + /* Wait for the reading */
758 + while (!(FEC_EIR(base_addr) & FEC_EIR_MII)) {
759 if (jiffies - time > FEC_MII_TIMEOUT * HZ)
760 return -ETIME;
761 schedule();
762 }
763
764 - // Clear the MII interrupt bit
765 + /* Clear the MII interrupt bit */
766 FEC_EIR(base_addr) = FEC_EIR_MII;
767
768 *data = FEC_MMFR(base_addr) & 0x0000FFFF;
769 @@ -918,25 +878,22 @@ int fec_write_mii(unsigned int base_addr
770 {
771 unsigned long time;
772
773 - // Clear the MII interrupt bit
774 + /* Clear the MII interrupt bit */
775 FEC_EIR(base_addr) = FEC_EIR_MII;
776
777 - // Write to the MII management frame register
778 + /* Write to the MII management frame register */
779 FEC_MMFR(base_addr) = FEC_MMFR_WRITE | (pa << 23) | (ra << 18) | data;
780
781 time = jiffies;
782
783 - // Wait for the writing
784 -
785 - while (!(FEC_EIR(base_addr) & FEC_EIR_MII))
786 - {
787 + /* Wait for the writing */
788 + while (!(FEC_EIR(base_addr) & FEC_EIR_MII)) {
789 if (jiffies - time > FEC_MII_TIMEOUT * HZ)
790 return -ETIME;
791 -
792 schedule();
793 }
794
795 - // Clear the MII interrupt bit
796 + /* Clear the MII interrupt bit */
797 FEC_EIR(base_addr) = FEC_EIR_MII;
798
799 return 0;
800 @@ -953,27 +910,24 @@ void fec_interrupt_fec_tx_handler(struct
801 {
802 struct fec_priv *fp = netdev_priv(dev);
803
804 - //Release the socket buffer
805 - if(fp->fecpriv_txbuf[fp->fecpriv_current_tx])
806 - {
807 + /* Release the socket buffer */
808 + if(fp->fecpriv_txbuf[fp->fecpriv_current_tx]) {
809 kfree(fp->fecpriv_txbuf[fp->fecpriv_current_tx]);
810 fp->fecpriv_txbuf[fp->fecpriv_current_tx] = NULL;
811 }
812 fp->fecpriv_current_tx = (fp->fecpriv_current_tx + 1) & FEC_TX_INDEX_MASK;
813
814 - if (MCD_dmaStatus(fp->fecpriv_fec_tx_channel) == MCD_DONE)
815 - for (; fp->fecpriv_current_tx != fp->fecpriv_next_tx; fp->fecpriv_current_tx = (fp->fecpriv_current_tx + 1) & FEC_TX_INDEX_MASK)
816 - {
817 - if(fp->fecpriv_txbuf[fp->fecpriv_current_tx])
818 - {
819 + if (MCD_dmaStatus(fp->fecpriv_fec_tx_channel) == MCD_DONE) {
820 + for (; fp->fecpriv_current_tx != fp->fecpriv_next_tx; fp->fecpriv_current_tx = (fp->fecpriv_current_tx + 1) & FEC_TX_INDEX_MASK) {
821 + if(fp->fecpriv_txbuf[fp->fecpriv_current_tx]) {
822 kfree(fp->fecpriv_txbuf[fp->fecpriv_current_tx]);
823 fp->fecpriv_txbuf[fp->fecpriv_current_tx] = NULL;
824 }
825 }
826 + }
827
828 if (netif_queue_stopped(dev))
829 netif_wake_queue(dev);
830 -
831 }
832
833 /************************************************************************
834 @@ -1008,49 +962,41 @@ void fec_interrupt_fec_rx_handler(struct
835 }
836 }
837 */
838 - for (; fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl & MCD_FEC_END_FRAME; fp->fecpriv_current_rx = (fp->fecpriv_current_rx + 1) & FEC_RX_INDEX_MASK)
839 - {
840 + for (; fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl & MCD_FEC_END_FRAME; fp->fecpriv_current_rx = (fp->fecpriv_current_rx + 1) & FEC_RX_INDEX_MASK) {
841 if( (fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length <= FEC_MAXBUF_SIZE) &&
842 - (fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length > 4)) // --tym--
843 - {
844 + (fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length > 4)) { /* --tym-- */
845 skb = fp->askb_rx[fp->fecpriv_current_rx];
846 if (!skb)
847 - {
848 - fp->fecpriv_stat.rx_dropped++;
849 - }
850 - else
851 - {
852 - // flush data cache before initializing the descriptor and starting DMA
853 + fp->fecpriv_stat.rx_dropped++;
854 + else {
855 + /* flush data cache before initializing the descriptor and starting DMA */
856 // DcacheFlushInvalidateCacheBlock((void*)virt_to_phys(fp->askb_rx[fp->fecpriv_current_rx]->tail), fp->askb_rx[fp->fecpriv_current_rx]->len);
857
858 skb_put(skb, fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length - 4);
859 -// skb->dev = dev;
860 skb->protocol = eth_type_trans(skb, dev);
861 netif_rx(skb);
862 - }
863 - fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl &= ~MCD_FEC_END_FRAME;
864 - // allocate new skbuff
865 + }
866 + fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl &= ~MCD_FEC_END_FRAME;
867 + /* allocate new skbuff */
868 fp->askb_rx[fp->fecpriv_current_rx] = alloc_skb(FEC_MAXBUF_SIZE + 16, /*GFP_ATOMIC |*/ GFP_DMA);
869 - if (!fp->askb_rx[fp->fecpriv_current_rx])
870 - {
871 - fp->fecpriv_rxdesc[fp->fecpriv_current_rx].dataPointer = 0;
872 - fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length = 0;
873 - fp->fecpriv_stat.rx_dropped++;
874 - }
875 - else
876 - {
877 - skb_reserve(fp->askb_rx[fp->fecpriv_current_rx], 16);
878 - fp->askb_rx[fp->fecpriv_current_rx]->dev = dev;
879 + if (!fp->askb_rx[fp->fecpriv_current_rx]) {
880 + fp->fecpriv_rxdesc[fp->fecpriv_current_rx].dataPointer = 0;
881 + fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length = 0;
882 + fp->fecpriv_stat.rx_dropped++;
883 + }
884 + else {
885 + skb_reserve(fp->askb_rx[fp->fecpriv_current_rx], 16);
886 + fp->askb_rx[fp->fecpriv_current_rx]->dev = dev;
887
888 - // flush data cache before initializing the descriptor and starting DMA
889 + /* flush data cache before initializing the descriptor and starting DMA */
890 #if 0
891 /* JKM -- currently running with cache turned off */
892 - DcacheFlushInvalidateCacheBlock((void*)virt_to_phys(fp->askb_rx[fp->fecpriv_current_rx]->tail), FEC_MAXBUF_SIZE);
893 + DcacheFlushInvalidateCacheBlock((void*)virt_to_phys(fp->askb_rx[fp->fecpriv_current_rx]->tail), FEC_MAXBUF_SIZE);
894 #endif
895
896 fp->fecpriv_rxdesc[fp->fecpriv_current_rx].dataPointer = (unsigned int) virt_to_phys(fp->askb_rx[fp->fecpriv_current_rx]->tail);
897 fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length = FEC_MAXBUF_SIZE;
898 - fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl |= MCD_FEC_BUF_READY;
899 + fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl |= MCD_FEC_BUF_READY;
900
901 // flush data cache before initializing the descriptor and starting DMA
902 // DcacheFlushInvalidateCacheBlock((void*)virt_to_phys(fp->askb_rx[fp->fecpriv_current_rx]->tail), FEC_MAXBUF_SIZE);
903 @@ -1059,11 +1005,10 @@ void fec_interrupt_fec_rx_handler(struct
904
905 }
906
907 - // Tell the DMA to continue the reception
908 + /* Tell the DMA to continue the reception */
909 MCD_continDma(fp->fecpriv_fec_rx_channel);
910
911 fp->fecpriv_rxflag = 0;
912 -
913 }
914
915 /************************************************************************
916 @@ -1080,76 +1025,70 @@ irqreturn_t fec_interrupt_handler(int ir
917 unsigned long base_addr = (unsigned long) dev->base_addr;
918 unsigned long events;
919
920 - // Read and clear the events
921 + /* Read and clear the events */
922 events = FEC_EIR(base_addr) & FEC_EIMR(base_addr);
923
924 - if (events & FEC_EIR_HBERR)
925 - {
926 + if (events & FEC_EIR_HBERR) {
927 fp->fecpriv_stat.tx_heartbeat_errors++;
928 - FEC_EIR(base_addr) = FEC_EIR_HBERR;
929 + FEC_EIR(base_addr) = FEC_EIR_HBERR;
930 }
931
932 - // receive/transmit FIFO error
933 - if (((events & FEC_EIR_RFERR) != 0) || ((events & FEC_EIR_XFERR) != 0))
934 - {
935 - // kill DMA receive channel
936 - MCD_killDma (fp->fecpriv_fec_rx_channel);
937 - // kill running transmission by DMA
938 - MCD_killDma (fp->fecpriv_fec_tx_channel);
939 -
940 - // Reset FIFOs
941 - FEC_FECFRST(base_addr) |= FEC_SW_RST;
942 - FEC_FECFRST(base_addr) &= ~FEC_SW_RST;
943 -
944 - // reset receive FIFO status register
945 - FEC_FECRFSR(base_addr) = FEC_FECRFSR_FAE
946 - | FEC_FECRFSR_RXW
947 - | FEC_FECRFSR_UF;
948 -
949 - // reset transmit FIFO status register
950 - FEC_FECTFSR(base_addr) = FEC_FECTFSR_FAE
951 - | FEC_FECTFSR_TXW
952 - | FEC_FECTFSR_UF
953 - | FEC_FECTFSR_OF;
954 + /* receive/transmit FIFO error */
955 + if (((events & FEC_EIR_RFERR) != 0) || ((events & FEC_EIR_XFERR) != 0)) {
956 + /* kill DMA receive channel */
957 + MCD_killDma (fp->fecpriv_fec_rx_channel);
958
959 - // reset RFERR and XFERR event
960 - FEC_EIR(base_addr) = FEC_EIR_RFERR | FEC_EIR_XFERR;
961 + /* kill running transmission by DMA */
962 + MCD_killDma (fp->fecpriv_fec_tx_channel);
963
964 - // stop queue
965 - netif_stop_queue(dev);
966 -
967 - // execute reinitialization as tasklet
968 - tasklet_schedule(&fp->fecpriv_tasklet_reinit);
969 + /* Reset FIFOs */
970 + FEC_FECFRST(base_addr) |= FEC_SW_RST;
971 + FEC_FECFRST(base_addr) &= ~FEC_SW_RST;
972
973 - fp->fecpriv_stat.rx_dropped++;
974 + /* reset receive FIFO status register */
975 + FEC_FECRFSR(base_addr) = FEC_FECRFSR_FAE |
976 + FEC_FECRFSR_RXW |
977 + FEC_FECRFSR_UF;
978
979 - }
980 + /* reset transmit FIFO status register */
981 + FEC_FECTFSR(base_addr) = FEC_FECTFSR_FAE |
982 + FEC_FECTFSR_TXW |
983 + FEC_FECTFSR_UF |
984 + FEC_FECTFSR_OF;
985
986 - // transmit FIFO underrun
987 - if ((events & FEC_EIR_XFUN) != 0)
988 - {
989 - // reset XFUN event
990 - FEC_EIR(base_addr) = FEC_EIR_XFUN;
991 - fp->fecpriv_stat.tx_aborted_errors++;
992 - }
993 + /* reset RFERR and XFERR event */
994 + FEC_EIR(base_addr) = FEC_EIR_RFERR | FEC_EIR_XFERR;
995 +
996 + /* stop queue */
997 + netif_stop_queue(dev);
998 +
999 + /* execute reinitialization as tasklet */
1000 + tasklet_schedule(&fp->fecpriv_tasklet_reinit);
1001 +
1002 + fp->fecpriv_stat.rx_dropped++;
1003 + }
1004
1005 - // late collision
1006 - if ((events & FEC_EIR_LC) != 0)
1007 - {
1008 - // reset LC event
1009 - FEC_EIR(base_addr) = FEC_EIR_LC;
1010 + /* transmit FIFO underrun */
1011 + if ((events & FEC_EIR_XFUN) != 0) {
1012 + /* reset XFUN event */
1013 + FEC_EIR(base_addr) = FEC_EIR_XFUN;
1014 fp->fecpriv_stat.tx_aborted_errors++;
1015 - }
1016 + }
1017
1018 - // collision retry limit
1019 - if ((events & FEC_EIR_RL) != 0)
1020 - {
1021 - // reset RL event
1022 - FEC_EIR(base_addr) = FEC_EIR_RL;
1023 + /* late collision */
1024 + if ((events & FEC_EIR_LC) != 0) {
1025 + /* reset LC event */
1026 + FEC_EIR(base_addr) = FEC_EIR_LC;
1027 fp->fecpriv_stat.tx_aborted_errors++;
1028 - }
1029 + }
1030
1031 - return 0;
1032 + /* collision retry limit */
1033 + if ((events & FEC_EIR_RL) != 0) {
1034 + /* reset RL event */
1035 + FEC_EIR(base_addr) = FEC_EIR_RL;
1036 + fp->fecpriv_stat.tx_aborted_errors++;
1037 + }
1038 + return 0;
1039 }
1040
1041 /************************************************************************
1042 @@ -1166,52 +1105,46 @@ void fec_interrupt_fec_reinit(unsigned l
1043 struct fec_priv *fp = netdev_priv(dev);
1044 unsigned long base_addr = (unsigned long) dev->base_addr;
1045
1046 - // Initialize reception descriptors and start DMA for the reception
1047 - for (i = 0; i < FEC_RX_BUF_NUMBER; i++)
1048 - {
1049 - if (!fp->askb_rx[i])
1050 - {
1051 - fp->askb_rx[i] = alloc_skb(FEC_MAXBUF_SIZE + 16, GFP_ATOMIC | GFP_DMA);
1052 - if (!fp->askb_rx[i])
1053 - {
1054 - fp->fecpriv_rxdesc[i].dataPointer = 0;
1055 - fp->fecpriv_rxdesc[i].statCtrl = 0;
1056 - fp->fecpriv_rxdesc[i].length = 0;
1057 - continue;
1058 - }
1059 + /* Initialize reception descriptors and start DMA for the reception */
1060 + for (i = 0; i < FEC_RX_BUF_NUMBER; i++) {
1061 + if (!fp->askb_rx[i]) {
1062 + fp->askb_rx[i] = alloc_skb(FEC_MAXBUF_SIZE + 16, GFP_ATOMIC | GFP_DMA);
1063 + if (!fp->askb_rx[i]) {
1064 + fp->fecpriv_rxdesc[i].dataPointer = 0;
1065 + fp->fecpriv_rxdesc[i].statCtrl = 0;
1066 + fp->fecpriv_rxdesc[i].length = 0;
1067 + continue;
1068 + }
1069 fp->askb_rx[i]->dev = dev;
1070 - skb_reserve(fp->askb_rx[i], 16);
1071 - }
1072 - fp->fecpriv_rxdesc[i].dataPointer = (unsigned int) virt_to_phys(fp->askb_rx[i]->tail);
1073 + skb_reserve(fp->askb_rx[i], 16);
1074 + }
1075 + fp->fecpriv_rxdesc[i].dataPointer = (unsigned int) virt_to_phys(fp->askb_rx[i]->tail);
1076 fp->fecpriv_rxdesc[i].statCtrl = MCD_FEC_BUF_READY | MCD_FEC_INTERRUPT;
1077 - fp->fecpriv_rxdesc[i].length = FEC_MAXBUF_SIZE;
1078 + fp->fecpriv_rxdesc[i].length = FEC_MAXBUF_SIZE;
1079 }
1080
1081 fp->fecpriv_rxdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
1082 fp->fecpriv_current_rx = 0;
1083
1084 - // restart frame transmission
1085 - for (i = 0; i < FEC_TX_BUF_NUMBER; i++)
1086 - {
1087 - if (fp->fecpriv_txbuf[i])
1088 - {
1089 -
1090 + /* restart frame transmission */
1091 + for (i = 0; i < FEC_TX_BUF_NUMBER; i++) {
1092 + if (fp->fecpriv_txbuf[i]) {
1093 kfree(fp->fecpriv_txbuf[i]);
1094 fp->fecpriv_txbuf[i] = NULL;
1095 - fp->fecpriv_stat.tx_dropped++;
1096 + fp->fecpriv_stat.tx_dropped++;
1097 }
1098 fp->fecpriv_txdesc[i].statCtrl = MCD_FEC_INTERRUPT;
1099 }
1100 fp->fecpriv_txdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
1101 fp->fecpriv_current_tx = fp->fecpriv_next_tx = 0;
1102
1103 - // flush entire data cache before restarting the DMA
1104 + /* flush entire data cache before restarting the DMA */
1105 #if 0
1106 /* JKM -- currently running with cache turned off */
1107 DcacheFlushInvalidate();
1108 #endif
1109
1110 - // restart DMA from beginning
1111 + /* restart DMA from beginning */
1112 MCD_startDma(fp->fecpriv_fec_rx_channel,
1113 (char *) fp->fecpriv_rxdesc, 0,
1114 (unsigned char *) &(FEC_FECRFDR(base_addr)), 0,
1115 @@ -1225,11 +1158,10 @@ void fec_interrupt_fec_reinit(unsigned l
1116 FEC_TX_DMA_PRI, MCD_FECTX_DMA | MCD_INTERRUPT,
1117 MCD_NO_CSUM | MCD_NO_BYTE_SWAP);
1118
1119 - // Enable FEC
1120 - FEC_ECR(base_addr) |= FEC_ECR_ETHEREN;
1121 + /* Enable FEC */
1122 + FEC_ECR(base_addr) |= FEC_ECR_ETHEREN;
1123
1124 netif_wake_queue(dev);
1125 -
1126 }
1127
1128 /************************************************************************
1129 @@ -1284,8 +1216,8 @@ void fec_interrupt_fec_rx_handler_fec1(v
1130 }
1131
1132 #endif
1133 -#ifndef MODULE
1134
1135 +#ifndef MODULE
1136 /************************************************************************
1137 * NAME: fec_mac_setup0
1138 *
1139 @@ -1300,7 +1232,6 @@ int __init fec_mac_setup0(char *s)
1140 if(fec_str_to_mac(s, fec_mac_addr_fec0))
1141 printk("The MAC address of FEC0 cannot be set from command line");
1142 return 1;
1143 -
1144 }
1145
1146 #ifdef FEC_2
1147 @@ -1316,11 +1247,9 @@ int __init fec_mac_setup1(char *s)
1148 if(!s || !*s)
1149 return 1;
1150
1151 -
1152 if(fec_str_to_mac(s, fec_mac_addr_fec1))
1153 printk("The MAC address of FEC1 cannot be set from command line");
1154 return 1;
1155 -
1156 }
1157 #endif
1158
1159 @@ -1332,52 +1261,46 @@ int __init fec_mac_setup1(char *s)
1160 *************************************************************************/
1161 int fec_str_to_mac( char *str_mac, unsigned char* addr)
1162 {
1163 - unsigned long val;
1164 + unsigned long val;
1165 char c;
1166 unsigned long octet[6], *octetptr = octet;
1167 int i;
1168 -again:
1169
1170 +again:
1171 val = 0;
1172 - while ((c = *str_mac) != '\0')
1173 - {
1174 - if ((c>='0')&&(c<='9'))
1175 - {
1176 + while ((c = *str_mac) != '\0') {
1177 + if ((c>='0')&&(c<='9')) {
1178 val = (val * 16) + (c - '0');
1179 str_mac++;
1180 continue;
1181 }
1182 - else
1183 - if (((c>='a')&&(c<='f'))||((c>='A')&&(c<='F')))
1184 - {
1185 + else if (((c>='a')&&(c<='f'))||((c>='A')&&(c<='F'))) {
1186 val = (val << 4) + (c + 10 - (((c>='a')&&(c<='f')) ? 'a' : 'A'));
1187 str_mac++;
1188 continue;
1189 }
1190 break;
1191 }
1192 - if (*str_mac == ':')
1193 - {
1194 + if (*str_mac == ':') {
1195 *octetptr++ = val, str_mac++;
1196 if (octetptr >= octet + 6)
1197 return 1;
1198 goto again;
1199 }
1200
1201 - //Check for trailing characters.
1202 + /* Check for trailing characters */
1203 if (*str_mac && !(*str_mac==' '))
1204 return 1;
1205 +
1206 *octetptr++ = val;
1207
1208 - if ((octetptr - octet)==6)
1209 - {
1210 - for(i=0;i<=6;i++)
1211 - addr[i]=octet[i];
1212 + if ((octetptr - octet)==6) {
1213 + for(i=0;i<=6;i++)
1214 + addr[i]=octet[i];
1215 }
1216 - else
1217 + else
1218 return 1;
1219
1220 return 0;
1221 -
1222 }
1223 #endif
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