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[ar71xx] reorganize PCI code
[openwrt.git] / target / linux / brcm63xx / files / drivers / net / bcm63xx_enet.c
1 /*
2 * Driver for BCM963xx builtin Ethernet mac
3 *
4 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/clk.h>
23 #include <linux/etherdevice.h>
24 #include <linux/delay.h>
25 #include <linux/ethtool.h>
26 #include <linux/crc32.h>
27 #include <linux/err.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/platform_device.h>
30 #include <linux/if_vlan.h>
31
32 #include <bcm63xx_dev_enet.h>
33 #include "bcm63xx_enet.h"
34
35 static char bcm_enet_driver_name[] = "bcm63xx_enet";
36 static char bcm_enet_driver_version[] = "1.0";
37
38 static int copybreak __read_mostly = 128;
39 module_param(copybreak, int, 0);
40 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
41
42 /* io memory shared between all devices */
43 static void __iomem *bcm_enet_shared_base;
44
45 /*
46 * io helpers to access mac registers
47 */
48 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
49 {
50 return bcm_readl(priv->base + off);
51 }
52
53 static inline void enet_writel(struct bcm_enet_priv *priv,
54 u32 val, u32 off)
55 {
56 bcm_writel(val, priv->base + off);
57 }
58
59 /*
60 * io helpers to access shared registers
61 */
62 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
63 {
64 return bcm_readl(bcm_enet_shared_base + off);
65 }
66
67 static inline void enet_dma_writel(struct bcm_enet_priv *priv,
68 u32 val, u32 off)
69 {
70 bcm_writel(val, bcm_enet_shared_base + off);
71 }
72
73 /*
74 * write given data into mii register and wait for transfer to end
75 * with timeout (average measured transfer time is 25us)
76 */
77 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
78 {
79 int limit;
80
81 /* make sure mii interrupt status is cleared */
82 enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
83
84 enet_writel(priv, data, ENET_MIIDATA_REG);
85 wmb();
86
87 /* busy wait on mii interrupt bit, with timeout */
88 limit = 1000;
89 do {
90 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
91 break;
92 udelay(1);
93 } while (limit-- >= 0);
94
95 return (limit < 0) ? 1 : 0;
96 }
97
98 /*
99 * MII internal read callback
100 */
101 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
102 int regnum)
103 {
104 u32 tmp, val;
105
106 tmp = regnum << ENET_MIIDATA_REG_SHIFT;
107 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
108 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
109 tmp |= ENET_MIIDATA_OP_READ_MASK;
110
111 if (do_mdio_op(priv, tmp))
112 return -1;
113
114 val = enet_readl(priv, ENET_MIIDATA_REG);
115 val &= 0xffff;
116 return val;
117 }
118
119 /*
120 * MII internal write callback
121 */
122 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
123 int regnum, u16 value)
124 {
125 u32 tmp;
126
127 tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
128 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
129 tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
130 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
131 tmp |= ENET_MIIDATA_OP_WRITE_MASK;
132
133 (void)do_mdio_op(priv, tmp);
134 return 0;
135 }
136
137 /*
138 * MII read callback from phylib
139 */
140 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
141 int regnum)
142 {
143 return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
144 }
145
146 /*
147 * MII write callback from phylib
148 */
149 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
150 int regnum, u16 value)
151 {
152 return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
153 }
154
155 /*
156 * MII read callback from mii core
157 */
158 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
159 int regnum)
160 {
161 return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
162 }
163
164 /*
165 * MII write callback from mii core
166 */
167 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
168 int regnum, int value)
169 {
170 bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
171 }
172
173 /*
174 * refill rx queue
175 */
176 static int bcm_enet_refill_rx(struct net_device *dev)
177 {
178 struct bcm_enet_priv *priv;
179
180 priv = netdev_priv(dev);
181
182 while (priv->rx_desc_count < priv->rx_ring_size) {
183 struct bcm_enet_desc *desc;
184 struct sk_buff *skb;
185 dma_addr_t p;
186 int desc_idx;
187 u32 len_stat;
188
189 desc_idx = priv->rx_dirty_desc;
190 desc = &priv->rx_desc_cpu[desc_idx];
191
192 if (!priv->rx_skb[desc_idx]) {
193 skb = netdev_alloc_skb(dev, priv->rx_skb_size);
194 if (!skb)
195 break;
196 priv->rx_skb[desc_idx] = skb;
197
198 p = dma_map_single(&priv->pdev->dev, skb->data,
199 priv->rx_skb_size,
200 DMA_FROM_DEVICE);
201 desc->address = p;
202 }
203
204 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
205 len_stat |= DMADESC_OWNER_MASK;
206 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
207 len_stat |= DMADESC_WRAP_MASK;
208 priv->rx_dirty_desc = 0;
209 } else {
210 priv->rx_dirty_desc++;
211 }
212 wmb();
213 desc->len_stat = len_stat;
214
215 priv->rx_desc_count++;
216
217 /* tell dma engine we allocated one buffer */
218 enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
219 }
220
221 /* If rx ring is still empty, set a timer to try allocating
222 * again at a later time. */
223 if (priv->rx_desc_count == 0 && netif_running(dev)) {
224 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
225 priv->rx_timeout.expires = jiffies + HZ;
226 add_timer(&priv->rx_timeout);
227 }
228
229 return 0;
230 }
231
232 /*
233 * timer callback to defer refill rx queue in case we're OOM
234 */
235 static void bcm_enet_refill_rx_timer(unsigned long data)
236 {
237 struct net_device *dev;
238 struct bcm_enet_priv *priv;
239
240 dev = (struct net_device *)data;
241 priv = netdev_priv(dev);
242
243 spin_lock(&priv->rx_lock);
244 bcm_enet_refill_rx((struct net_device *)data);
245 spin_unlock(&priv->rx_lock);
246 }
247
248 /*
249 * extract packet from rx queue
250 */
251 static int bcm_enet_receive_queue(struct net_device *dev, int budget)
252 {
253 struct bcm_enet_priv *priv;
254 struct device *kdev;
255 int processed;
256
257 priv = netdev_priv(dev);
258 kdev = &priv->pdev->dev;
259 processed = 0;
260
261 /* don't scan ring further than number of refilled
262 * descriptor */
263 if (budget > priv->rx_desc_count)
264 budget = priv->rx_desc_count;
265
266 do {
267 struct bcm_enet_desc *desc;
268 struct sk_buff *skb;
269 int desc_idx;
270 u32 len_stat;
271 unsigned int len;
272
273 desc_idx = priv->rx_curr_desc;
274 desc = &priv->rx_desc_cpu[desc_idx];
275
276 /* make sure we actually read the descriptor status at
277 * each loop */
278 rmb();
279
280 len_stat = desc->len_stat;
281
282 /* break if dma ownership belongs to hw */
283 if (len_stat & DMADESC_OWNER_MASK)
284 break;
285
286 processed++;
287 priv->rx_curr_desc++;
288 if (priv->rx_curr_desc == priv->rx_ring_size)
289 priv->rx_curr_desc = 0;
290 priv->rx_desc_count--;
291
292 /* if the packet does not have start of packet _and_
293 * end of packet flag set, then just recycle it */
294 if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
295 priv->stats.rx_dropped++;
296 continue;
297 }
298
299 /* recycle packet if it's marked as bad */
300 if (unlikely(len_stat & DMADESC_ERR_MASK)) {
301 priv->stats.rx_errors++;
302
303 if (len_stat & DMADESC_OVSIZE_MASK)
304 priv->stats.rx_length_errors++;
305 if (len_stat & DMADESC_CRC_MASK)
306 priv->stats.rx_crc_errors++;
307 if (len_stat & DMADESC_UNDER_MASK)
308 priv->stats.rx_frame_errors++;
309 if (len_stat & DMADESC_OV_MASK)
310 priv->stats.rx_fifo_errors++;
311 continue;
312 }
313
314 /* valid packet */
315 skb = priv->rx_skb[desc_idx];
316 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
317 /* don't include FCS */
318 len -= 4;
319
320 if (len < copybreak) {
321 struct sk_buff *nskb;
322
323 nskb = netdev_alloc_skb(dev, len + 2);
324 if (!nskb) {
325 /* forget packet, just rearm desc */
326 priv->stats.rx_dropped++;
327 continue;
328 }
329
330 /* since we're copying the data, we can align
331 * them properly */
332 skb_reserve(nskb, NET_IP_ALIGN);
333 dma_sync_single_for_cpu(kdev, desc->address,
334 len, DMA_FROM_DEVICE);
335 memcpy(nskb->data, skb->data, len);
336 dma_sync_single_for_device(kdev, desc->address,
337 len, DMA_FROM_DEVICE);
338 skb = nskb;
339 } else {
340 dma_unmap_single(&priv->pdev->dev, desc->address,
341 priv->rx_skb_size, DMA_FROM_DEVICE);
342 priv->rx_skb[desc_idx] = NULL;
343 }
344
345 skb_put(skb, len);
346 skb->dev = dev;
347 skb->protocol = eth_type_trans(skb, dev);
348 priv->stats.rx_packets++;
349 priv->stats.rx_bytes += len;
350 dev->last_rx = jiffies;
351 netif_receive_skb(skb);
352
353 } while (--budget > 0);
354
355 if (processed || !priv->rx_desc_count) {
356 bcm_enet_refill_rx(dev);
357
358 /* kick rx dma */
359 enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
360 ENETDMA_CHANCFG_REG(priv->rx_chan));
361 }
362
363 return processed;
364 }
365
366
367 /*
368 * try to or force reclaim of transmitted buffers
369 */
370 static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
371 {
372 struct bcm_enet_priv *priv;
373 int released;
374
375 priv = netdev_priv(dev);
376 released = 0;
377
378 while (priv->tx_desc_count < priv->tx_ring_size) {
379 struct bcm_enet_desc *desc;
380 struct sk_buff *skb;
381
382 /* We run in a bh and fight against start_xmit, which
383 * is called with bh disabled */
384 spin_lock(&priv->tx_lock);
385
386 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
387
388 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
389 spin_unlock(&priv->tx_lock);
390 break;
391 }
392
393 /* ensure other field of the descriptor were not read
394 * before we checked ownership */
395 rmb();
396
397 skb = priv->tx_skb[priv->tx_dirty_desc];
398 priv->tx_skb[priv->tx_dirty_desc] = NULL;
399 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
400 DMA_TO_DEVICE);
401
402 priv->tx_dirty_desc++;
403 if (priv->tx_dirty_desc == priv->tx_ring_size)
404 priv->tx_dirty_desc = 0;
405 priv->tx_desc_count++;
406
407 spin_unlock(&priv->tx_lock);
408
409 if (desc->len_stat & DMADESC_UNDER_MASK)
410 priv->stats.tx_errors++;
411
412 dev_kfree_skb(skb);
413 released++;
414 }
415
416 if (netif_queue_stopped(dev) && released)
417 netif_wake_queue(dev);
418
419 return released;
420 }
421
422 /*
423 * poll func, called by network core
424 */
425 static int bcm_enet_poll(struct napi_struct *napi, int budget)
426 {
427 struct bcm_enet_priv *priv;
428 struct net_device *dev;
429 int tx_work_done, rx_work_done;
430
431 priv = container_of(napi, struct bcm_enet_priv, napi);
432 dev = priv->net_dev;
433
434 /* ack interrupts */
435 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
436 ENETDMA_IR_REG(priv->rx_chan));
437 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
438 ENETDMA_IR_REG(priv->tx_chan));
439
440 /* reclaim sent skb */
441 tx_work_done = bcm_enet_tx_reclaim(dev, 0);
442
443 spin_lock(&priv->rx_lock);
444 rx_work_done = bcm_enet_receive_queue(dev, budget);
445 spin_unlock(&priv->rx_lock);
446
447 if (rx_work_done >= budget || tx_work_done > 0) {
448 /* rx/tx queue is not yet empty/clean */
449 return rx_work_done;
450 }
451
452 /* no more packet in rx/tx queue, remove device from poll
453 * queue */
454 netif_rx_complete(dev, napi);
455
456 /* restore rx/tx interrupt */
457 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
458 ENETDMA_IRMASK_REG(priv->rx_chan));
459 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
460 ENETDMA_IRMASK_REG(priv->tx_chan));
461
462 return rx_work_done;
463 }
464
465 /*
466 * mac interrupt handler
467 */
468 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
469 {
470 struct net_device *dev;
471 struct bcm_enet_priv *priv;
472 u32 stat;
473
474 dev = dev_id;
475 priv = netdev_priv(dev);
476
477 stat = enet_readl(priv, ENET_IR_REG);
478 if (!(stat & ENET_IR_MIB))
479 return IRQ_NONE;
480
481 /* clear & mask interrupt */
482 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
483 enet_writel(priv, 0, ENET_IRMASK_REG);
484
485 /* read mib registers in workqueue */
486 schedule_work(&priv->mib_update_task);
487
488 return IRQ_HANDLED;
489 }
490
491 /*
492 * rx/tx dma interrupt handler
493 */
494 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
495 {
496 struct net_device *dev;
497 struct bcm_enet_priv *priv;
498
499 dev = dev_id;
500 priv = netdev_priv(dev);
501
502 /* mask rx/tx interrupts */
503 enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
504 enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
505
506 netif_rx_schedule(dev, &priv->napi);
507
508 return IRQ_HANDLED;
509 }
510
511 /*
512 * tx request callback
513 */
514 static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
515 {
516 struct bcm_enet_priv *priv;
517 struct bcm_enet_desc *desc;
518 u32 len_stat;
519 int ret;
520
521 priv = netdev_priv(dev);
522
523 /* lock against tx reclaim */
524 spin_lock(&priv->tx_lock);
525
526 /* make sure the tx hw queue is not full, should not happen
527 * since we stop queue before it's the case */
528 if (unlikely(!priv->tx_desc_count)) {
529 netif_stop_queue(dev);
530 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
531 "available?\n");
532 ret = NETDEV_TX_BUSY;
533 goto out_unlock;
534 }
535
536 /* point to the next available desc */
537 desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
538 priv->tx_skb[priv->tx_curr_desc] = skb;
539
540 /* fill descriptor */
541 desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
542 DMA_TO_DEVICE);
543
544 len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
545 len_stat |= DMADESC_ESOP_MASK |
546 DMADESC_APPEND_CRC |
547 DMADESC_OWNER_MASK;
548
549 priv->tx_curr_desc++;
550 if (priv->tx_curr_desc == priv->tx_ring_size) {
551 priv->tx_curr_desc = 0;
552 len_stat |= DMADESC_WRAP_MASK;
553 }
554 priv->tx_desc_count--;
555
556 /* dma might be already polling, make sure we update desc
557 * fields in correct order */
558 wmb();
559 desc->len_stat = len_stat;
560 wmb();
561
562 /* kick tx dma */
563 enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
564 ENETDMA_CHANCFG_REG(priv->tx_chan));
565
566 /* stop queue if no more desc available */
567 if (!priv->tx_desc_count)
568 netif_stop_queue(dev);
569
570 priv->stats.tx_bytes += skb->len;
571 priv->stats.tx_packets++;
572 dev->trans_start = jiffies;
573 ret = NETDEV_TX_OK;
574
575 out_unlock:
576 spin_unlock(&priv->tx_lock);
577 return ret;
578 }
579
580 /*
581 * Change the interface's mac address.
582 */
583 static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
584 {
585 struct bcm_enet_priv *priv;
586 struct sockaddr *addr = p;
587 u32 val;
588
589 priv = netdev_priv(dev);
590 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
591
592 /* use perfect match register 0 to store my mac address */
593 val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
594 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
595 enet_writel(priv, val, ENET_PML_REG(0));
596
597 val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
598 val |= ENET_PMH_DATAVALID_MASK;
599 enet_writel(priv, val, ENET_PMH_REG(0));
600
601 return 0;
602 }
603
604 /*
605 * Change rx mode (promiscous/allmulti) and update multicast list
606 */
607 static void bcm_enet_set_multicast_list(struct net_device *dev)
608 {
609 struct bcm_enet_priv *priv;
610 struct dev_mc_list *mc_list;
611 u32 val;
612 int i;
613
614 priv = netdev_priv(dev);
615
616 val = enet_readl(priv, ENET_RXCFG_REG);
617
618 if (dev->flags & IFF_PROMISC)
619 val |= ENET_RXCFG_PROMISC_MASK;
620 else
621 val &= ~ENET_RXCFG_PROMISC_MASK;
622
623 /* only 3 perfect match registers left, first one is used for
624 * own mac address */
625 if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 3)
626 val |= ENET_RXCFG_ALLMCAST_MASK;
627 else
628 val &= ~ENET_RXCFG_ALLMCAST_MASK;
629
630 /* no need to set perfect match registers if we catch all
631 * multicast */
632 if (val & ENET_RXCFG_ALLMCAST_MASK) {
633 enet_writel(priv, val, ENET_RXCFG_REG);
634 return;
635 }
636
637 for (i = 0, mc_list = dev->mc_list;
638 (mc_list != NULL) && (i < dev->mc_count) && (i < 3);
639 i++, mc_list = mc_list->next) {
640 u8 *dmi_addr;
641 u32 tmp;
642
643 /* filter non ethernet address */
644 if (mc_list->dmi_addrlen != 6)
645 continue;
646
647 /* update perfect match registers */
648 dmi_addr = mc_list->dmi_addr;
649 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
650 (dmi_addr[4] << 8) | dmi_addr[5];
651 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
652
653 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
654 tmp |= ENET_PMH_DATAVALID_MASK;
655 enet_writel(priv, tmp, ENET_PMH_REG(i + 1));
656 }
657
658 for (; i < 3; i++) {
659 enet_writel(priv, 0, ENET_PML_REG(i + 1));
660 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
661 }
662
663 enet_writel(priv, val, ENET_RXCFG_REG);
664 }
665
666 /*
667 * set mac duplex parameters
668 */
669 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
670 {
671 u32 val;
672
673 val = enet_readl(priv, ENET_TXCTL_REG);
674 if (fullduplex)
675 val |= ENET_TXCTL_FD_MASK;
676 else
677 val &= ~ENET_TXCTL_FD_MASK;
678 enet_writel(priv, val, ENET_TXCTL_REG);
679 }
680
681 /*
682 * set mac flow control parameters
683 */
684 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
685 {
686 u32 val;
687
688 /* rx flow control (pause frame handling) */
689 val = enet_readl(priv, ENET_RXCFG_REG);
690 if (rx_en)
691 val |= ENET_RXCFG_ENFLOW_MASK;
692 else
693 val &= ~ENET_RXCFG_ENFLOW_MASK;
694 enet_writel(priv, val, ENET_RXCFG_REG);
695
696 /* tx flow control (pause frame generation) */
697 val = enet_dma_readl(priv, ENETDMA_CFG_REG);
698 if (tx_en)
699 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
700 else
701 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
702 enet_dma_writel(priv, val, ENETDMA_CFG_REG);
703 }
704
705 /*
706 * link changed callback (from phylib)
707 */
708 static void bcm_enet_adjust_phy_link(struct net_device *dev)
709 {
710 struct bcm_enet_priv *priv;
711 struct phy_device *phydev;
712 int status_changed;
713
714 priv = netdev_priv(dev);
715 phydev = priv->phydev;
716 status_changed = 0;
717
718 if (priv->old_link != phydev->link) {
719 status_changed = 1;
720 priv->old_link = phydev->link;
721 }
722
723 /* reflect duplex change in mac configuration */
724 if (phydev->link && phydev->duplex != priv->old_duplex) {
725 bcm_enet_set_duplex(priv,
726 (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
727 status_changed = 1;
728 priv->old_duplex = phydev->duplex;
729 }
730
731 /* enable flow control if remote advertise it (trust phylib to
732 * check that duplex is full */
733 if (phydev->link && phydev->pause != priv->old_pause) {
734 int rx_pause_en, tx_pause_en;
735
736 if (phydev->pause) {
737 /* pause was advertised by lpa and us */
738 rx_pause_en = 1;
739 tx_pause_en = 1;
740 } else if (!priv->pause_auto) {
741 /* pause setting overrided by user */
742 rx_pause_en = priv->pause_rx;
743 tx_pause_en = priv->pause_tx;
744 } else {
745 rx_pause_en = 0;
746 tx_pause_en = 0;
747 }
748
749 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
750 status_changed = 1;
751 priv->old_pause = phydev->pause;
752 }
753
754 if (status_changed) {
755 pr_info("%s: link %s", dev->name, phydev->link ?
756 "UP" : "DOWN");
757 if (phydev->link)
758 printk(" - %d/%s - flow control %s", phydev->speed,
759 DUPLEX_FULL == phydev->duplex ? "full" : "half",
760 phydev->pause == 1 ? "rx&tx" : "off");
761
762 printk("\n");
763 }
764 }
765
766 /*
767 * link changed callback (if phylib is not used)
768 */
769 static void bcm_enet_adjust_link(struct net_device *dev)
770 {
771 struct bcm_enet_priv *priv;
772
773 priv = netdev_priv(dev);
774 bcm_enet_set_duplex(priv, priv->force_duplex_full);
775 bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
776
777 pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
778 dev->name,
779 priv->force_speed_100 ? 100 : 10,
780 priv->force_duplex_full ? "full" : "half",
781 priv->pause_rx ? "rx" : "off",
782 priv->pause_tx ? "tx" : "off");
783 }
784
785 /*
786 * open callback, allocate dma rings & buffers and start rx operation
787 */
788 static int bcm_enet_open(struct net_device *dev)
789 {
790 struct bcm_enet_priv *priv;
791 struct sockaddr addr;
792 struct device *kdev;
793 struct phy_device *phydev;
794 int irq_requested, i, ret;
795 unsigned int size;
796 char phy_id[BUS_ID_SIZE];
797 void *p;
798 u32 val;
799
800 priv = netdev_priv(dev);
801 priv->rx_desc_cpu = priv->tx_desc_cpu = NULL;
802 priv->rx_skb = priv->tx_skb = NULL;
803
804 kdev = &priv->pdev->dev;
805
806 if (priv->has_phy) {
807 /* connect to PHY */
808 snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT,
809 priv->mac_id ? "1" : "0", priv->phy_id);
810
811 phydev = phy_connect(dev, phy_id, &bcm_enet_adjust_phy_link, 0,
812 PHY_INTERFACE_MODE_MII);
813
814 if (IS_ERR(phydev)) {
815 dev_err(kdev, "could not attach to PHY\n");
816 return PTR_ERR(phydev);
817 }
818
819 /* mask with MAC supported features */
820 phydev->supported &= (SUPPORTED_10baseT_Half |
821 SUPPORTED_10baseT_Full |
822 SUPPORTED_100baseT_Half |
823 SUPPORTED_100baseT_Full |
824 SUPPORTED_Autoneg |
825 SUPPORTED_Pause |
826 SUPPORTED_MII);
827 phydev->advertising = phydev->supported;
828
829 if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
830 phydev->advertising |= SUPPORTED_Pause;
831 else
832 phydev->advertising &= ~SUPPORTED_Pause;
833
834 dev_info(kdev, "attached PHY at address %d [%s]\n",
835 phydev->addr, phydev->drv->name);
836
837 priv->old_link = 0;
838 priv->old_duplex = -1;
839 priv->old_pause = -1;
840 priv->phydev = phydev;
841 }
842
843 /* mask all interrupts and request them */
844 enet_writel(priv, 0, ENET_IRMASK_REG);
845 enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
846 enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
847
848 irq_requested = 0;
849 ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
850 if (ret)
851 goto out;
852 irq_requested++;
853
854 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
855 IRQF_SAMPLE_RANDOM | IRQF_DISABLED, dev->name, dev);
856 if (ret)
857 goto out;
858 irq_requested++;
859
860 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
861 IRQF_DISABLED, dev->name, dev);
862 if (ret)
863 goto out;
864 irq_requested++;
865
866 /* initialize perfect match registers */
867 for (i = 0; i < 4; i++) {
868 enet_writel(priv, 0, ENET_PML_REG(i));
869 enet_writel(priv, 0, ENET_PMH_REG(i));
870 }
871
872 /* write device mac address */
873 memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
874 bcm_enet_set_mac_address(dev, &addr);
875
876 /* allocate rx dma ring */
877 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
878 p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
879 if (!p) {
880 dev_err(kdev, "cannot allocate rx ring %u\n", size);
881 ret = -ENOMEM;
882 goto out;
883 }
884
885 memset(p, 0, size);
886 priv->rx_desc_alloc_size = size;
887 priv->rx_desc_cpu = p;
888
889 /* allocate tx dma ring */
890 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
891 p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
892 if (!p) {
893 dev_err(kdev, "cannot allocate tx ring\n");
894 ret = -ENOMEM;
895 goto out;
896 }
897
898 memset(p, 0, size);
899 priv->tx_desc_alloc_size = size;
900 priv->tx_desc_cpu = p;
901
902 priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
903 GFP_KERNEL);
904 if (!priv->tx_skb) {
905 dev_err(kdev, "cannot allocate rx skb queue\n");
906 ret = -ENOMEM;
907 goto out;
908 }
909
910 priv->tx_desc_count = priv->tx_ring_size;
911 priv->tx_dirty_desc = 0;
912 priv->tx_curr_desc = 0;
913 spin_lock_init(&priv->tx_lock);
914
915 /* init & fill rx ring with skbs */
916 priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
917 GFP_KERNEL);
918 if (!priv->rx_skb) {
919 dev_err(kdev, "cannot allocate rx skb queue\n");
920 ret = -ENOMEM;
921 goto out;
922 }
923
924 priv->rx_desc_count = 0;
925 priv->rx_dirty_desc = 0;
926 priv->rx_curr_desc = 0;
927
928 /* initialize flow control buffer allocation */
929 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
930 ENETDMA_BUFALLOC_REG(priv->rx_chan));
931
932 if (bcm_enet_refill_rx(dev)) {
933 dev_err(kdev, "cannot allocate rx skb queue\n");
934 ret = -ENOMEM;
935 goto out;
936 }
937
938 /* write rx & tx ring addresses */
939 enet_dma_writel(priv, priv->rx_desc_dma,
940 ENETDMA_RSTART_REG(priv->rx_chan));
941 enet_dma_writel(priv, priv->tx_desc_dma,
942 ENETDMA_RSTART_REG(priv->tx_chan));
943
944 /* clear remaining state ram for rx & tx channel */
945 enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->rx_chan));
946 enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->tx_chan));
947 enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->rx_chan));
948 enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->tx_chan));
949 enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->rx_chan));
950 enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->tx_chan));
951
952 /* set max rx/tx length */
953 enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
954 enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
955
956 /* set dma maximum burst len */
957 enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
958 ENETDMA_MAXBURST_REG(priv->rx_chan));
959 enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
960 ENETDMA_MAXBURST_REG(priv->tx_chan));
961
962 /* set correct transmit fifo watermark */
963 enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
964
965 /* set flow control low/high threshold to 1/3 / 2/3 */
966 val = priv->rx_ring_size / 3;
967 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
968 val = (priv->rx_ring_size * 2) / 3;
969 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
970
971 /* all set, enable mac and interrupts, start dma engine and
972 * kick rx dma channel */
973 wmb();
974 enet_writel(priv, ENET_CTL_ENABLE_MASK, ENET_CTL_REG);
975 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
976 enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
977 ENETDMA_CHANCFG_REG(priv->rx_chan));
978
979 /* watch "mib counters about to overflow" interrupt */
980 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
981 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
982
983 /* watch "packet transferred" interrupt in rx and tx */
984 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
985 ENETDMA_IR_REG(priv->rx_chan));
986 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
987 ENETDMA_IR_REG(priv->tx_chan));
988
989 /* make sure we enable napi before rx interrupt */
990 napi_enable(&priv->napi);
991
992 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
993 ENETDMA_IRMASK_REG(priv->rx_chan));
994 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
995 ENETDMA_IRMASK_REG(priv->tx_chan));
996
997 if (priv->has_phy)
998 phy_start(priv->phydev);
999 else
1000 bcm_enet_adjust_link(dev);
1001
1002 netif_start_queue(dev);
1003 return 0;
1004
1005 out:
1006 phy_disconnect(priv->phydev);
1007 if (irq_requested > 2)
1008 free_irq(priv->irq_tx, dev);
1009 if (irq_requested > 1)
1010 free_irq(priv->irq_rx, dev);
1011 if (irq_requested > 0)
1012 free_irq(dev->irq, dev);
1013 for (i = 0; i < priv->rx_ring_size; i++) {
1014 struct bcm_enet_desc *desc;
1015
1016 if (!priv->rx_skb[i])
1017 continue;
1018
1019 desc = &priv->rx_desc_cpu[i];
1020 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1021 DMA_FROM_DEVICE);
1022 kfree_skb(priv->rx_skb[i]);
1023 }
1024 if (priv->rx_desc_cpu)
1025 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1026 priv->rx_desc_cpu, priv->rx_desc_dma);
1027 if (priv->tx_desc_cpu)
1028 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1029 priv->tx_desc_cpu, priv->tx_desc_dma);
1030 kfree(priv->rx_skb);
1031 kfree(priv->tx_skb);
1032 return ret;
1033 }
1034
1035 /*
1036 * disable mac
1037 */
1038 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1039 {
1040 int limit;
1041 u32 val;
1042
1043 val = enet_readl(priv, ENET_CTL_REG);
1044 val |= ENET_CTL_DISABLE_MASK;
1045 enet_writel(priv, val, ENET_CTL_REG);
1046
1047 limit = 1000;
1048 do {
1049 u32 val;
1050
1051 val = enet_readl(priv, ENET_CTL_REG);
1052 if (!(val & ENET_CTL_DISABLE_MASK))
1053 break;
1054 udelay(1);
1055 } while (limit--);
1056 }
1057
1058 /*
1059 * disable dma in given channel
1060 */
1061 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1062 {
1063 int limit;
1064
1065 enet_dma_writel(priv, 0, ENETDMA_CHANCFG_REG(chan));
1066
1067 limit = 1000;
1068 do {
1069 u32 val;
1070
1071 val = enet_dma_readl(priv, ENETDMA_CHANCFG_REG(chan));
1072 if (!(val & ENETDMA_CHANCFG_EN_MASK))
1073 break;
1074 udelay(1);
1075 } while (limit--);
1076 }
1077
1078 /*
1079 * stop callback
1080 */
1081 static int bcm_enet_stop(struct net_device *dev)
1082 {
1083 struct bcm_enet_priv *priv;
1084 struct device *kdev;
1085 int i;
1086
1087 priv = netdev_priv(dev);
1088 kdev = &priv->pdev->dev;
1089
1090 netif_stop_queue(dev);
1091 napi_disable(&priv->napi);
1092 if (priv->has_phy)
1093 phy_stop(priv->phydev);
1094 del_timer_sync(&priv->rx_timeout);
1095
1096 /* mask all interrupts */
1097 enet_writel(priv, 0, ENET_IRMASK_REG);
1098 enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
1099 enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
1100
1101 /* make sure no mib update is scheduled */
1102 flush_scheduled_work();
1103
1104 /* disable dma & mac */
1105 bcm_enet_disable_dma(priv, priv->tx_chan);
1106 bcm_enet_disable_dma(priv, priv->rx_chan);
1107 bcm_enet_disable_mac(priv);
1108
1109 /* force reclaim of all tx buffers */
1110 bcm_enet_tx_reclaim(dev, 1);
1111
1112 /* free the rx skb ring */
1113 for (i = 0; i < priv->rx_ring_size; i++) {
1114 struct bcm_enet_desc *desc;
1115
1116 if (!priv->rx_skb[i])
1117 continue;
1118
1119 desc = &priv->rx_desc_cpu[i];
1120 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1121 DMA_FROM_DEVICE);
1122 kfree_skb(priv->rx_skb[i]);
1123 }
1124
1125 /* free remaining allocated memory */
1126 kfree(priv->rx_skb);
1127 kfree(priv->tx_skb);
1128 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1129 priv->rx_desc_cpu, priv->rx_desc_dma);
1130 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1131 priv->tx_desc_cpu, priv->tx_desc_dma);
1132 free_irq(priv->irq_tx, dev);
1133 free_irq(priv->irq_rx, dev);
1134 free_irq(dev->irq, dev);
1135
1136 /* release phy */
1137 if (priv->has_phy) {
1138 phy_disconnect(priv->phydev);
1139 priv->phydev = NULL;
1140 }
1141
1142 return 0;
1143 }
1144
1145 /*
1146 * core request to return device rx/tx stats
1147 */
1148 static struct net_device_stats *bcm_enet_get_stats(struct net_device *dev)
1149 {
1150 struct bcm_enet_priv *priv;
1151
1152 priv = netdev_priv(dev);
1153 return &priv->stats;
1154 }
1155
1156 /*
1157 * ethtool callbacks
1158 */
1159 struct bcm_enet_stats {
1160 char stat_string[ETH_GSTRING_LEN];
1161 int sizeof_stat;
1162 int stat_offset;
1163 int mib_reg;
1164 };
1165
1166 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m), \
1167 offsetof(struct bcm_enet_priv, m)
1168
1169 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
1170 { "rx_packets", GEN_STAT(stats.rx_packets), -1 },
1171 { "tx_packets", GEN_STAT(stats.tx_packets), -1 },
1172 { "rx_bytes", GEN_STAT(stats.rx_bytes), -1 },
1173 { "tx_bytes", GEN_STAT(stats.tx_bytes), -1 },
1174 { "rx_errors", GEN_STAT(stats.rx_errors), -1 },
1175 { "tx_errors", GEN_STAT(stats.tx_errors), -1 },
1176 { "rx_dropped", GEN_STAT(stats.rx_dropped), -1 },
1177 { "tx_dropped", GEN_STAT(stats.tx_dropped), -1 },
1178
1179 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1180 { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1181 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1182 { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1183 { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1184 { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1185 { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1186 { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1187 { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1188 { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1189 { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1190 { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1191 { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1192 { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1193 { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1194 { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1195 { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1196 { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1197 { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1198 { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1199 { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1200
1201 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1202 { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1203 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1204 { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1205 { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1206 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1207 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1208 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1209 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1210 { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1211 { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1212 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1213 { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1214 { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1215 { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1216 { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1217 { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1218 { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1219 { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1220 { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1221 { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1222 { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1223
1224 };
1225
1226 #define BCM_ENET_STATS_LEN \
1227 (sizeof(bcm_enet_gstrings_stats) / sizeof(struct bcm_enet_stats))
1228
1229 static const u32 unused_mib_regs[] = {
1230 ETH_MIB_TX_ALL_OCTETS,
1231 ETH_MIB_TX_ALL_PKTS,
1232 ETH_MIB_RX_ALL_OCTETS,
1233 ETH_MIB_RX_ALL_PKTS,
1234 };
1235
1236
1237 static void bcm_enet_get_drvinfo(struct net_device *netdev,
1238 struct ethtool_drvinfo *drvinfo)
1239 {
1240 strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
1241 strncpy(drvinfo->version, bcm_enet_driver_version, 32);
1242 strncpy(drvinfo->fw_version, "N/A", 32);
1243 strncpy(drvinfo->bus_info, "bcm63xx", 32);
1244 drvinfo->n_stats = BCM_ENET_STATS_LEN;
1245 }
1246
1247 static int bcm_enet_get_stats_count(struct net_device *netdev)
1248 {
1249 return BCM_ENET_STATS_LEN;
1250 }
1251
1252 static void bcm_enet_get_strings(struct net_device *netdev,
1253 u32 stringset, u8 *data)
1254 {
1255 int i;
1256
1257 switch (stringset) {
1258 case ETH_SS_STATS:
1259 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1260 memcpy(data + i * ETH_GSTRING_LEN,
1261 bcm_enet_gstrings_stats[i].stat_string,
1262 ETH_GSTRING_LEN);
1263 }
1264 break;
1265 }
1266 }
1267
1268 static void update_mib_counters(struct bcm_enet_priv *priv)
1269 {
1270 int i;
1271
1272 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1273 const struct bcm_enet_stats *s;
1274 u32 val;
1275 char *p;
1276
1277 s = &bcm_enet_gstrings_stats[i];
1278 if (s->mib_reg == -1)
1279 continue;
1280
1281 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1282 p = (char *)priv + s->stat_offset;
1283
1284 if (s->sizeof_stat == sizeof(u64))
1285 *(u64 *)p += val;
1286 else
1287 *(u32 *)p += val;
1288 }
1289
1290 /* also empty unused mib counters to make sure mib counter
1291 * overflow interrupt is cleared */
1292 for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1293 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1294 }
1295
1296 static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1297 {
1298 struct bcm_enet_priv *priv;
1299
1300 priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1301 mutex_lock(&priv->mib_update_lock);
1302 update_mib_counters(priv);
1303 mutex_unlock(&priv->mib_update_lock);
1304
1305 /* reenable mib interrupt */
1306 if (netif_running(priv->net_dev))
1307 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1308 }
1309
1310 static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1311 struct ethtool_stats *stats,
1312 u64 *data)
1313 {
1314 struct bcm_enet_priv *priv;
1315 int i;
1316
1317 priv = netdev_priv(netdev);
1318
1319 mutex_lock(&priv->mib_update_lock);
1320 update_mib_counters(priv);
1321
1322 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1323 const struct bcm_enet_stats *s;
1324 char *p;
1325
1326 s = &bcm_enet_gstrings_stats[i];
1327 p = (char *)priv + s->stat_offset;
1328 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1329 *(u64 *)p : *(u32 *)p;
1330 }
1331 mutex_unlock(&priv->mib_update_lock);
1332 }
1333
1334 static int bcm_enet_get_settings(struct net_device *dev,
1335 struct ethtool_cmd *cmd)
1336 {
1337 struct bcm_enet_priv *priv;
1338
1339 priv = netdev_priv(dev);
1340
1341 cmd->maxrxpkt = 0;
1342 cmd->maxtxpkt = 0;
1343
1344 if (priv->has_phy) {
1345 if (!priv->phydev)
1346 return -ENODEV;
1347 return phy_ethtool_gset(priv->phydev, cmd);
1348 } else {
1349 cmd->autoneg = 0;
1350 cmd->speed = (priv->force_speed_100) ? SPEED_100 : SPEED_10;
1351 cmd->duplex = (priv->force_duplex_full) ?
1352 DUPLEX_FULL : DUPLEX_HALF;
1353 cmd->supported = ADVERTISED_10baseT_Half |
1354 ADVERTISED_10baseT_Full |
1355 ADVERTISED_100baseT_Half |
1356 ADVERTISED_100baseT_Full;
1357 cmd->advertising = 0;
1358 cmd->port = PORT_MII;
1359 cmd->transceiver = XCVR_EXTERNAL;
1360 }
1361 return 0;
1362 }
1363
1364 static int bcm_enet_set_settings(struct net_device *dev,
1365 struct ethtool_cmd *cmd)
1366 {
1367 struct bcm_enet_priv *priv;
1368
1369 priv = netdev_priv(dev);
1370 if (priv->has_phy) {
1371 if (!priv->phydev)
1372 return -ENODEV;
1373 return phy_ethtool_sset(priv->phydev, cmd);
1374 } else {
1375
1376 if (cmd->autoneg ||
1377 (cmd->speed != SPEED_100 && cmd->speed != SPEED_10) ||
1378 cmd->port != PORT_MII)
1379 return -EINVAL;
1380
1381 priv->force_speed_100 = (cmd->speed == SPEED_100) ? 1 : 0;
1382 priv->force_duplex_full = (cmd->duplex == DUPLEX_FULL) ? 1 : 0;
1383
1384 if (netif_running(dev))
1385 bcm_enet_adjust_link(dev);
1386 return 0;
1387 }
1388 }
1389
1390 static void bcm_enet_get_ringparam(struct net_device *dev,
1391 struct ethtool_ringparam *ering)
1392 {
1393 struct bcm_enet_priv *priv;
1394
1395 priv = netdev_priv(dev);
1396
1397 /* rx/tx ring is actually only limited by memory */
1398 ering->rx_max_pending = 8192;
1399 ering->tx_max_pending = 8192;
1400 ering->rx_mini_max_pending = 0;
1401 ering->rx_jumbo_max_pending = 0;
1402 ering->rx_pending = priv->rx_ring_size;
1403 ering->tx_pending = priv->tx_ring_size;
1404 }
1405
1406 static int bcm_enet_set_ringparam(struct net_device *dev,
1407 struct ethtool_ringparam *ering)
1408 {
1409 struct bcm_enet_priv *priv;
1410 int was_running;
1411
1412 priv = netdev_priv(dev);
1413
1414 was_running = 0;
1415 if (netif_running(dev)) {
1416 bcm_enet_stop(dev);
1417 was_running = 1;
1418 }
1419
1420 priv->rx_ring_size = ering->rx_pending;
1421 priv->tx_ring_size = ering->tx_pending;
1422
1423 if (was_running) {
1424 int err;
1425
1426 err = bcm_enet_open(dev);
1427 if (err)
1428 dev_close(dev);
1429 else
1430 bcm_enet_set_multicast_list(dev);
1431 }
1432 return 0;
1433 }
1434
1435 static void bcm_enet_get_pauseparam(struct net_device *dev,
1436 struct ethtool_pauseparam *ecmd)
1437 {
1438 struct bcm_enet_priv *priv;
1439
1440 priv = netdev_priv(dev);
1441 ecmd->autoneg = priv->pause_auto;
1442 ecmd->rx_pause = priv->pause_rx;
1443 ecmd->tx_pause = priv->pause_tx;
1444 }
1445
1446 static int bcm_enet_set_pauseparam(struct net_device *dev,
1447 struct ethtool_pauseparam *ecmd)
1448 {
1449 struct bcm_enet_priv *priv;
1450
1451 priv = netdev_priv(dev);
1452
1453 if (priv->has_phy) {
1454 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1455 /* asymetric pause mode not supported,
1456 * actually possible but integrated PHY has RO
1457 * asym_pause bit */
1458 return -EINVAL;
1459 }
1460 } else {
1461 /* no pause autoneg on direct mii connection */
1462 if (ecmd->autoneg)
1463 return -EINVAL;
1464 }
1465
1466 priv->pause_auto = ecmd->autoneg;
1467 priv->pause_rx = ecmd->rx_pause;
1468 priv->pause_tx = ecmd->tx_pause;
1469
1470 return 0;
1471 }
1472
1473 static struct ethtool_ops bcm_enet_ethtool_ops = {
1474 .get_strings = bcm_enet_get_strings,
1475 .get_stats_count = bcm_enet_get_stats_count,
1476 .get_ethtool_stats = bcm_enet_get_ethtool_stats,
1477 .get_settings = bcm_enet_get_settings,
1478 .set_settings = bcm_enet_set_settings,
1479 .get_drvinfo = bcm_enet_get_drvinfo,
1480 .get_link = ethtool_op_get_link,
1481 .get_ringparam = bcm_enet_get_ringparam,
1482 .set_ringparam = bcm_enet_set_ringparam,
1483 .get_pauseparam = bcm_enet_get_pauseparam,
1484 .set_pauseparam = bcm_enet_set_pauseparam,
1485 };
1486
1487 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1488 {
1489 struct bcm_enet_priv *priv;
1490
1491 priv = netdev_priv(dev);
1492 if (priv->has_phy) {
1493 if (!priv->phydev)
1494 return -ENODEV;
1495 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
1496 } else {
1497 struct mii_if_info mii;
1498
1499 mii.dev = dev;
1500 mii.mdio_read = bcm_enet_mdio_read_mii;
1501 mii.mdio_write = bcm_enet_mdio_write_mii;
1502 mii.phy_id = 0;
1503 mii.phy_id_mask = 0x3f;
1504 mii.reg_num_mask = 0x1f;
1505 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1506 }
1507 }
1508
1509 /*
1510 * calculate actual hardware mtu
1511 */
1512 static int compute_hw_mtu(struct bcm_enet_priv *priv, int mtu)
1513 {
1514 int actual_mtu;
1515
1516 actual_mtu = mtu;
1517
1518 /* add ethernet header + vlan tag size */
1519 actual_mtu += VLAN_ETH_HLEN;
1520
1521 if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU)
1522 return -EINVAL;
1523
1524 /*
1525 * setup maximum size before we get overflow mark in
1526 * descriptor, note that this will not prevent reception of
1527 * big frames, they will be split into multiple buffers
1528 * anyway
1529 */
1530 priv->hw_mtu = actual_mtu;
1531
1532 /*
1533 * align rx buffer size to dma burst len, account FCS since
1534 * it's appended
1535 */
1536 priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
1537 BCMENET_DMA_MAXBURST * 4);
1538 return 0;
1539 }
1540
1541 /*
1542 * adjust mtu, can't be called while device is running
1543 */
1544 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1545 {
1546 int ret;
1547
1548 if (netif_running(dev))
1549 return -EBUSY;
1550
1551 ret = compute_hw_mtu(netdev_priv(dev), new_mtu);
1552 if (ret)
1553 return ret;
1554 dev->mtu = new_mtu;
1555 return 0;
1556 }
1557
1558 /*
1559 * preinit hardware to allow mii operation while device is down
1560 */
1561 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1562 {
1563 u32 val;
1564 int limit;
1565
1566 /* make sure mac is disabled */
1567 bcm_enet_disable_mac(priv);
1568
1569 /* soft reset mac */
1570 val = ENET_CTL_SRESET_MASK;
1571 enet_writel(priv, val, ENET_CTL_REG);
1572 wmb();
1573
1574 limit = 1000;
1575 do {
1576 val = enet_readl(priv, ENET_CTL_REG);
1577 if (!(val & ENET_CTL_SRESET_MASK))
1578 break;
1579 udelay(1);
1580 } while (limit--);
1581
1582 /* select correct mii interface */
1583 val = enet_readl(priv, ENET_CTL_REG);
1584 if (priv->use_external_mii)
1585 val |= ENET_CTL_EPHYSEL_MASK;
1586 else
1587 val &= ~ENET_CTL_EPHYSEL_MASK;
1588 enet_writel(priv, val, ENET_CTL_REG);
1589
1590 /* turn on mdc clock */
1591 enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1592 ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1593
1594 /* set mib counters to self-clear when read */
1595 val = enet_readl(priv, ENET_MIBCTL_REG);
1596 val |= ENET_MIBCTL_RDCLEAR_MASK;
1597 enet_writel(priv, val, ENET_MIBCTL_REG);
1598 }
1599
1600 /*
1601 * allocate netdevice, request register memory and register device.
1602 */
1603 static int __devinit bcm_enet_probe(struct platform_device *pdev)
1604 {
1605 struct bcm_enet_priv *priv;
1606 struct net_device *dev;
1607 struct bcm63xx_enet_platform_data *pd;
1608 struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1609 struct mii_bus *bus;
1610 const char *clk_name;
1611 unsigned int iomem_size;
1612 int i, ret, mdio_registered, mem_requested;
1613
1614 /* stop if shared driver failed, assume driver->probe will be
1615 * called in the same order we register devices (correct ?) */
1616 if (!bcm_enet_shared_base)
1617 return -ENODEV;
1618
1619 mdio_registered = mem_requested = 0;
1620
1621 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1622 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1623 res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1624 res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1625 if (!res_mem || !res_irq || !res_irq_rx || !res_irq_tx)
1626 return -ENODEV;
1627
1628 ret = 0;
1629 dev = alloc_etherdev(sizeof(*priv));
1630 if (!dev)
1631 return -ENOMEM;
1632 priv = netdev_priv(dev);
1633 memset(priv, 0, sizeof(*priv));
1634
1635 ret = compute_hw_mtu(priv, dev->mtu);
1636 if (ret)
1637 goto out;
1638
1639 iomem_size = res_mem->end - res_mem->start + 1;
1640 if (!request_mem_region(res_mem->start, iomem_size, "bcm63xx_enet")) {
1641 ret = -EBUSY;
1642 goto err;
1643 }
1644 mem_requested = 1;
1645
1646 priv->base = ioremap(res_mem->start, iomem_size);
1647 if (priv->base == NULL) {
1648 ret = -ENOMEM;
1649 goto err;
1650 }
1651 dev->irq = priv->irq = res_irq->start;
1652 priv->irq_rx = res_irq_rx->start;
1653 priv->irq_tx = res_irq_tx->start;
1654 priv->mac_id = pdev->id;
1655
1656 /* get rx & tx dma channel id for this mac */
1657 if (priv->mac_id == 0) {
1658 priv->rx_chan = 0;
1659 priv->tx_chan = 1;
1660 clk_name = "enet0";
1661 } else {
1662 priv->rx_chan = 2;
1663 priv->tx_chan = 3;
1664 clk_name = "enet1";
1665 }
1666
1667 priv->mac_clk = clk_get(&pdev->dev, clk_name);
1668 if (IS_ERR(priv->mac_clk)) {
1669 ret = PTR_ERR(priv->mac_clk);
1670 priv->mac_clk = NULL;
1671 goto err;
1672 }
1673 clk_enable(priv->mac_clk);
1674
1675 /* initialize default and fetch platform data */
1676 priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1677 priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1678
1679 pd = pdev->dev.platform_data;
1680 if (pd) {
1681 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1682 priv->has_phy = pd->has_phy;
1683 priv->phy_id = pd->phy_id;
1684 priv->has_phy_interrupt = pd->has_phy_interrupt;
1685 priv->phy_interrupt = pd->phy_interrupt;
1686 priv->use_external_mii = !pd->use_internal_phy;
1687 priv->pause_auto = pd->pause_auto;
1688 priv->pause_rx = pd->pause_rx;
1689 priv->pause_tx = pd->pause_tx;
1690 priv->force_duplex_full = pd->force_duplex_full;
1691 priv->force_speed_100 = pd->force_speed_100;
1692 }
1693
1694 if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
1695 /* using internal PHY, enable clock */
1696 priv->phy_clk = clk_get(&pdev->dev, "ephy");
1697 if (IS_ERR(priv->phy_clk)) {
1698 ret = PTR_ERR(priv->phy_clk);
1699 priv->phy_clk = NULL;
1700 goto err;
1701 }
1702 clk_enable(priv->phy_clk);
1703 }
1704
1705 /* do minimal hardware init to be able to probe mii bus */
1706 bcm_enet_hw_preinit(priv);
1707
1708 /* MII bus registration */
1709 if (priv->has_phy) {
1710 bus = &priv->mii_bus;
1711 bus->name = "bcm63xx_enet MII bus";
1712 bus->dev = &pdev->dev;
1713 bus->priv = priv;
1714 bus->read = bcm_enet_mdio_read_phylib;
1715 bus->write = bcm_enet_mdio_write_phylib;
1716 sprintf(bus->id, "%d", priv->mac_id);
1717
1718 /* only probe bus where we think the PHY is, because
1719 * the mdio read operation return 0 instead of 0xffff
1720 * if a slave is not present on hw */
1721 bus->phy_mask = ~(1 << priv->phy_id);
1722
1723 bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1724 if (!bus->irq) {
1725 ret = -ENOMEM;
1726 goto err;
1727 }
1728
1729 if (priv->has_phy_interrupt)
1730 bus->irq[priv->phy_id] = priv->phy_interrupt;
1731 else
1732 bus->irq[priv->phy_id] = PHY_POLL;
1733
1734 ret = mdiobus_register(bus);
1735 if (ret) {
1736 dev_err(&pdev->dev, "unable to register mdio bus\n");
1737 goto err;
1738 }
1739 mdio_registered = 1;
1740 } else {
1741
1742 /* run platform code to initialize PHY device */
1743 if (pd->mii_config &&
1744 pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1745 bcm_enet_mdio_write_mii)) {
1746 dev_err(&pdev->dev, "unable to configure mdio bus\n");
1747 goto err;
1748 }
1749 }
1750
1751 spin_lock_init(&priv->rx_lock);
1752
1753 /* init rx timeout (used for oom) */
1754 init_timer(&priv->rx_timeout);
1755 priv->rx_timeout.function = bcm_enet_refill_rx_timer;
1756 priv->rx_timeout.data = (unsigned long)dev;
1757
1758 /* init the mib update lock&work */
1759 mutex_init(&priv->mib_update_lock);
1760 INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1761
1762 /* zero mib counters */
1763 for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1764 enet_writel(priv, 0, ENET_MIB_REG(i));
1765
1766 /* register netdevice */
1767 dev->open = bcm_enet_open;
1768 dev->stop = bcm_enet_stop;
1769 dev->hard_start_xmit = bcm_enet_start_xmit;
1770 dev->get_stats = bcm_enet_get_stats;
1771 dev->set_mac_address = bcm_enet_set_mac_address;
1772 dev->set_multicast_list = bcm_enet_set_multicast_list;
1773 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1774 dev->do_ioctl = bcm_enet_ioctl;
1775 #ifdef CONFIG_NET_POLL_CONTROLLER
1776 dev->poll_controller = bcm_enet_netpoll;
1777 #endif
1778 dev->change_mtu = bcm_enet_change_mtu;
1779
1780 SET_ETHTOOL_OPS(dev, &bcm_enet_ethtool_ops);
1781 SET_NETDEV_DEV(dev, &pdev->dev);
1782
1783 ret = register_netdev(dev);
1784 if (ret)
1785 goto err;
1786
1787 platform_set_drvdata(pdev, dev);
1788 priv->pdev = pdev;
1789 priv->net_dev = dev;
1790
1791 return 0;
1792
1793 err:
1794 if (mem_requested)
1795 release_mem_region(res_mem->start, iomem_size);
1796 if (mdio_registered)
1797 mdiobus_unregister(&priv->mii_bus);
1798 kfree(priv->mii_bus.irq);
1799 if (priv->mac_clk) {
1800 clk_disable(priv->mac_clk);
1801 clk_put(priv->mac_clk);
1802 }
1803 if (priv->phy_clk) {
1804 clk_disable(priv->phy_clk);
1805 clk_put(priv->phy_clk);
1806 }
1807 if (priv->base) {
1808 /* turn off mdc clock */
1809 enet_writel(priv, 0, ENET_MIISC_REG);
1810 iounmap(priv->base);
1811 }
1812 out:
1813 free_netdev(dev);
1814 return ret;
1815 }
1816
1817
1818 /*
1819 * exit func, stops hardware and unregisters netdevice
1820 */
1821 static int __devexit bcm_enet_remove(struct platform_device *pdev)
1822 {
1823 struct bcm_enet_priv *priv;
1824 struct net_device *dev;
1825 struct resource *res;
1826
1827 /* stop netdevice */
1828 dev = platform_get_drvdata(pdev);
1829 priv = netdev_priv(dev);
1830 unregister_netdev(dev);
1831
1832 /* turn off mdc clock */
1833 enet_writel(priv, 0, ENET_MIISC_REG);
1834
1835 if (priv->has_phy) {
1836 mdiobus_unregister(&priv->mii_bus);
1837 kfree(priv->mii_bus.irq);
1838 } else {
1839 struct bcm63xx_enet_platform_data *pd;
1840
1841 pd = pdev->dev.platform_data;
1842 if (pd && pd->mii_config)
1843 pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1844 bcm_enet_mdio_write_mii);
1845 }
1846
1847 /* release device resources */
1848 iounmap(priv->base);
1849 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1850 release_mem_region(res->start, res->end - res->start + 1);
1851
1852 /* disable hw block clocks */
1853 if (priv->phy_clk) {
1854 clk_disable(priv->phy_clk);
1855 clk_put(priv->phy_clk);
1856 }
1857 clk_disable(priv->mac_clk);
1858 clk_put(priv->mac_clk);
1859
1860 platform_set_drvdata(pdev, NULL);
1861 free_netdev(dev);
1862 return 0;
1863 }
1864
1865 struct platform_driver bcm63xx_enet_driver = {
1866 .probe = bcm_enet_probe,
1867 .remove = __devexit_p(bcm_enet_remove),
1868 .driver = {
1869 .name = "bcm63xx_enet",
1870 .owner = THIS_MODULE,
1871 },
1872 };
1873
1874 /*
1875 * reserve & remap memory space shared between all macs
1876 */
1877 static int __devinit bcm_enet_shared_probe(struct platform_device *pdev)
1878 {
1879 struct resource *res;
1880 unsigned int iomem_size;
1881
1882 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1883 if (!res)
1884 return -ENODEV;
1885
1886 iomem_size = res->end - res->start + 1;
1887 if (!request_mem_region(res->start, iomem_size, "bcm63xx_enet_dma"))
1888 return -EBUSY;
1889
1890 bcm_enet_shared_base = ioremap(res->start, iomem_size);
1891 if (!bcm_enet_shared_base) {
1892 release_mem_region(res->start, iomem_size);
1893 return -ENOMEM;
1894 }
1895 return 0;
1896 }
1897
1898 static int __devexit bcm_enet_shared_remove(struct platform_device *pdev)
1899 {
1900 struct resource *res;
1901
1902 iounmap(bcm_enet_shared_base);
1903 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1904 release_mem_region(res->start, res->end - res->start + 1);
1905 return 0;
1906 }
1907
1908 /*
1909 * this "shared" driver is needed because both macs share a single
1910 * address space
1911 */
1912 struct platform_driver bcm63xx_enet_shared_driver = {
1913 .probe = bcm_enet_shared_probe,
1914 .remove = __devexit_p(bcm_enet_shared_remove),
1915 .driver = {
1916 .name = "bcm63xx_enet_shared",
1917 .owner = THIS_MODULE,
1918 },
1919 };
1920
1921 /*
1922 * entry point
1923 */
1924 static int __init bcm_enet_init(void)
1925 {
1926 int ret;
1927
1928 ret = platform_driver_register(&bcm63xx_enet_shared_driver);
1929 if (ret)
1930 return ret;
1931
1932 ret = platform_driver_register(&bcm63xx_enet_driver);
1933 if (ret)
1934 platform_driver_unregister(&bcm63xx_enet_shared_driver);
1935
1936 return ret;
1937 }
1938
1939 static void __exit bcm_enet_exit(void)
1940 {
1941 platform_driver_unregister(&bcm63xx_enet_driver);
1942 platform_driver_unregister(&bcm63xx_enet_shared_driver);
1943 }
1944
1945
1946 module_init(bcm_enet_init);
1947 module_exit(bcm_enet_exit);
1948
1949 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
1950 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
1951 MODULE_LICENSE("GPL");
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