1 #ifndef BCM63XX_REGS_H_
2 #define BCM63XX_REGS_H_
4 /*************************************************************************
5 * _REG relative to RSET_PERF
6 *************************************************************************/
8 /* Chip Identifier / Revision register */
9 #define PERF_REV_REG 0x0
10 #define REV_CHIPID_SHIFT 16
11 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
12 #define REV_REVID_SHIFT 0
13 #define REV_REVID_MASK (0xffff << REV_REVID_SHIFT)
15 /* Clock Control register */
16 #define PERF_CKCTL_REG 0x4
18 #define CKCTL_6338_ADSLPHY_EN (1 << 0)
19 #define CKCTL_6338_MPI_EN (1 << 1)
20 #define CKCTL_6338_DRAM_EN (1 << 2)
21 #define CKCTL_6338_ENET_EN (1 << 4)
22 #define CKCTL_6338_USBS_EN (1 << 4)
23 #define CKCTL_6338_SAR_EN (1 << 5)
24 #define CKCTL_6338_SPI_EN (1 << 9)
26 #define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ADSLPHY_EN | \
28 CKCTL_6338_ENET_EN | \
32 #define CKCTL_6345_CPU_EN (1 << 0)
33 #define CKCTL_6345_UART_EN (1 << 3)
34 #define CKCTL_6345_ENET_EN (1 << 7)
35 #define CKCTL_6345_USBH_EN (1 << 8)
37 #define CKCTL_6348_ADSLPHY_EN (1 << 0)
38 #define CKCTL_6348_MPI_EN (1 << 1)
39 #define CKCTL_6348_SDRAM_EN (1 << 2)
40 #define CKCTL_6348_M2M_EN (1 << 3)
41 #define CKCTL_6348_ENET_EN (1 << 4)
42 #define CKCTL_6348_SAR_EN (1 << 5)
43 #define CKCTL_6348_USBS_EN (1 << 6)
44 #define CKCTL_6348_USBH_EN (1 << 8)
45 #define CKCTL_6348_SPI_EN (1 << 9)
47 #define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \
49 CKCTL_6348_ENET_EN | \
51 CKCTL_6348_USBS_EN | \
52 CKCTL_6348_USBH_EN | \
55 #define CKCTL_6358_ENET_EN (1 << 4)
56 #define CKCTL_6358_ADSLPHY_EN (1 << 5)
57 #define CKCTL_6358_PCM_EN (1 << 8)
58 #define CKCTL_6358_SPI_EN (1 << 9)
59 #define CKCTL_6358_USBS_EN (1 << 10)
60 #define CKCTL_6358_SAR_EN (1 << 11)
61 #define CKCTL_6358_EMUSB_EN (1 << 17)
62 #define CKCTL_6358_ENET0_EN (1 << 18)
63 #define CKCTL_6358_ENET1_EN (1 << 19)
64 #define CKCTL_6358_USBSU_EN (1 << 20)
65 #define CKCTL_6358_EPHY_EN (1 << 21)
67 #define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \
68 CKCTL_6358_ADSLPHY_EN | \
71 CKCTL_6358_USBS_EN | \
73 CKCTL_6358_EMUSB_EN | \
74 CKCTL_6358_ENET0_EN | \
75 CKCTL_6358_ENET1_EN | \
76 CKCTL_6358_USBSU_EN | \
79 /* System PLL Control register */
80 #define PERF_SYS_PLL_CTL_REG 0x8
81 #define SYS_PLL_SOFT_RESET 0x1
83 /* Interrupt Mask register */
84 #define PERF_IRQMASK_REG 0xc
85 #define PERF_IRQSTAT_REG 0x10
87 /* Interrupt Status register */
88 #define PERF_IRQSTAT_REG 0x10
90 /* External Interrupt Configuration register */
91 #define PERF_EXTIRQ_CFG_REG 0x14
92 #define EXTIRQ_CFG_SENSE(x) (1 << (x))
93 #define EXTIRQ_CFG_STAT(x) (1 << (x + 5))
94 #define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10))
95 #define EXTIRQ_CFG_MASK(x) (1 << (x + 15))
96 #define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20))
97 #define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25))
99 #define EXTIRQ_CFG_CLEAR_ALL (0xf << 10)
100 #define EXTIRQ_CFG_MASK_ALL (0xf << 15)
102 /* Soft Reset register */
103 #define PERF_SOFTRESET_REG 0x28
105 #define SOFTRESET_6338_SPI_MASK (1 << 0)
106 #define SOFTRESET_6338_ENET_MASK (1 << 2)
107 #define SOFTRESET_6338_USBH_MASK (1 << 3)
108 #define SOFTRESET_6338_USBS_MASK (1 << 4)
109 #define SOFTRESET_6338_ADSL_MASK (1 << 5)
110 #define SOFTRESET_6338_DMAMEM_MASK (1 << 6)
111 #define SOFTRESET_6338_SAR_MASK (1 << 7)
112 #define SOFTRESET_6338_ACLC_MASK (1 << 8)
113 #define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10)
114 #define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \
115 SOFTRESET_6338_ENET_MASK | \
116 SOFTRESET_6338_USBH_MASK | \
117 SOFTRESET_6338_USBS_MASK | \
118 SOFTRESET_6338_ADSL_MASK | \
119 SOFTRESET_6338_DMAMEM_MASK | \
120 SOFTRESET_6338_SAR_MASK | \
121 SOFTRESET_6338_ACLC_MASK | \
122 SOFTRESET_6338_ADSLMIPSPLL_MASK)
124 #define SOFTRESET_6348_SPI_MASK (1 << 0)
125 #define SOFTRESET_6348_ENET_MASK (1 << 2)
126 #define SOFTRESET_6348_USBH_MASK (1 << 3)
127 #define SOFTRESET_6348_USBS_MASK (1 << 4)
128 #define SOFTRESET_6348_ADSL_MASK (1 << 5)
129 #define SOFTRESET_6348_DMAMEM_MASK (1 << 6)
130 #define SOFTRESET_6348_SAR_MASK (1 << 7)
131 #define SOFTRESET_6348_ACLC_MASK (1 << 8)
132 #define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10)
134 #define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \
135 SOFTRESET_6348_ENET_MASK | \
136 SOFTRESET_6348_USBH_MASK | \
137 SOFTRESET_6348_USBS_MASK | \
138 SOFTRESET_6348_ADSL_MASK | \
139 SOFTRESET_6348_DMAMEM_MASK | \
140 SOFTRESET_6348_SAR_MASK | \
141 SOFTRESET_6348_ACLC_MASK | \
142 SOFTRESET_6348_ADSLMIPSPLL_MASK)
144 /* MIPS PLL control register */
145 #define PERF_MIPSPLLCTL_REG 0x34
146 #define MIPSPLLCTL_N1_SHIFT 20
147 #define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT)
148 #define MIPSPLLCTL_N2_SHIFT 15
149 #define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT)
150 #define MIPSPLLCTL_M1REF_SHIFT 12
151 #define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT)
152 #define MIPSPLLCTL_M2REF_SHIFT 9
153 #define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT)
154 #define MIPSPLLCTL_M1CPU_SHIFT 6
155 #define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT)
156 #define MIPSPLLCTL_M1BUS_SHIFT 3
157 #define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT)
158 #define MIPSPLLCTL_M2BUS_SHIFT 0
159 #define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT)
161 /* ADSL PHY PLL Control register */
162 #define PERF_ADSLPLLCTL_REG 0x38
163 #define ADSLPLLCTL_N1_SHIFT 20
164 #define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT)
165 #define ADSLPLLCTL_N2_SHIFT 15
166 #define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT)
167 #define ADSLPLLCTL_M1REF_SHIFT 12
168 #define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT)
169 #define ADSLPLLCTL_M2REF_SHIFT 9
170 #define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT)
171 #define ADSLPLLCTL_M1CPU_SHIFT 6
172 #define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT)
173 #define ADSLPLLCTL_M1BUS_SHIFT 3
174 #define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT)
175 #define ADSLPLLCTL_M2BUS_SHIFT 0
176 #define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT)
178 #define ADSLPLLCTL_VAL(n1,n2,m1ref,m2ref,m1cpu,m1bus,m2bus) \
179 (((n1) << ADSLPLLCTL_N1_SHIFT) | \
180 ((n2) << ADSLPLLCTL_N2_SHIFT) | \
181 ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \
182 ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \
183 ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \
184 ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \
185 ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))
188 /*************************************************************************
189 * _REG relative to RSET_TIMER
190 *************************************************************************/
192 #define BCM63XX_TIMER_COUNT 4
193 #define TIMER_T0_ID 0
194 #define TIMER_T1_ID 1
195 #define TIMER_T2_ID 2
196 #define TIMER_WDT_ID 3
198 /* Timer irqstat register */
199 #define TIMER_IRQSTAT_REG 0
200 #define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x))
201 #define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0)
202 #define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1)
203 #define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2)
204 #define TIMER_IRQSTAT_WDT_CAUSE (1 << 3)
205 #define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8))
206 #define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8)
207 #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9)
208 #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10)
210 /* Timer control register */
211 #define TIMER_CTLx_REG(x) (0x4 + (x * 4))
212 #define TIMER_CTL0_REG 0x4
213 #define TIMER_CTL1_REG 0x8
214 #define TIMER_CTL2_REG 0xC
215 #define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff)
216 #define TIMER_CTL_MONOTONIC_MASK (1 << 30)
217 #define TIMER_CTL_ENABLE_MASK (1 << 31)
220 /*************************************************************************
221 * _REG relative to RSET_WDT
222 *************************************************************************/
224 /* Watchdog default count register */
225 #define WDT_DEFVAL_REG 0x0
227 /* Watchdog control register */
228 #define WDT_CTL_REG 0x4
230 /* Watchdog control register constants */
231 #define WDT_START_1 (0xff00)
232 #define WDT_START_2 (0x00ff)
233 #define WDT_STOP_1 (0xee00)
234 #define WDT_STOP_2 (0x00ee)
236 /* Watchdog reset length register */
237 #define WDT_RSTLEN_REG 0x8
240 /*************************************************************************
241 * _REG relative to RSET_UARTx
242 *************************************************************************/
244 /* UART Control Register */
245 #define UART_CTL_REG 0x0
246 #define UART_CTL_RXTMOUTCNT_SHIFT 0
247 #define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
248 #define UART_CTL_RSTTXDN_SHIFT 5
249 #define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT)
250 #define UART_CTL_RSTRXFIFO_SHIFT 6
251 #define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
252 #define UART_CTL_RSTTXFIFO_SHIFT 7
253 #define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
254 #define UART_CTL_STOPBITS_SHIFT 8
255 #define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
256 #define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
257 #define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT)
258 #define UART_CTL_BITSPERSYM_SHIFT 12
259 #define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
260 #define UART_CTL_XMITBRK_SHIFT 14
261 #define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
262 #define UART_CTL_RSVD_SHIFT 15
263 #define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
264 #define UART_CTL_RXPAREVEN_SHIFT 16
265 #define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
266 #define UART_CTL_RXPAREN_SHIFT 17
267 #define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
268 #define UART_CTL_TXPAREVEN_SHIFT 18
269 #define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
270 #define UART_CTL_TXPAREN_SHIFT 18
271 #define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
272 #define UART_CTL_LOOPBACK_SHIFT 20
273 #define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
274 #define UART_CTL_RXEN_SHIFT 21
275 #define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
276 #define UART_CTL_TXEN_SHIFT 22
277 #define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
278 #define UART_CTL_BRGEN_SHIFT 23
279 #define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
281 /* UART Baudword register */
282 #define UART_BAUD_REG 0x4
284 /* UART Misc Control register */
285 #define UART_MCTL_REG 0x8
286 #define UART_MCTL_DTR_SHIFT 0
287 #define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT)
288 #define UART_MCTL_RTS_SHIFT 1
289 #define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT)
290 #define UART_MCTL_RXFIFOTHRESH_SHIFT 8
291 #define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
292 #define UART_MCTL_TXFIFOTHRESH_SHIFT 12
293 #define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
294 #define UART_MCTL_RXFIFOFILL_SHIFT 16
295 #define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
296 #define UART_MCTL_TXFIFOFILL_SHIFT 24
297 #define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
299 /* UART External Input Configuration register */
300 #define UART_EXTINP_REG 0xc
301 #define UART_EXTINP_RI_SHIFT 0
302 #define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT)
303 #define UART_EXTINP_CTS_SHIFT 1
304 #define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT)
305 #define UART_EXTINP_DCD_SHIFT 2
306 #define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT)
307 #define UART_EXTINP_DSR_SHIFT 3
308 #define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT)
309 #define UART_EXTINP_IRSTAT(x) (1 << (x + 4))
310 #define UART_EXTINP_IRMASK(x) (1 << (x + 8))
311 #define UART_EXTINP_IR_RI 0
312 #define UART_EXTINP_IR_CTS 1
313 #define UART_EXTINP_IR_DCD 2
314 #define UART_EXTINP_IR_DSR 3
315 #define UART_EXTINP_RI_NOSENSE_SHIFT 16
316 #define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT)
317 #define UART_EXTINP_CTS_NOSENSE_SHIFT 17
318 #define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
319 #define UART_EXTINP_DCD_NOSENSE_SHIFT 18
320 #define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
321 #define UART_EXTINP_DSR_NOSENSE_SHIFT 19
322 #define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
324 /* UART Interrupt register */
325 #define UART_IR_REG 0x10
326 #define UART_IR_MASK(x) (1 << (x + 16))
327 #define UART_IR_STAT(x) (1 << (x))
328 #define UART_IR_EXTIP 0
329 #define UART_IR_TXUNDER 1
330 #define UART_IR_TXOVER 2
331 #define UART_IR_TXTRESH 3
332 #define UART_IR_TXRDLATCH 4
333 #define UART_IR_TXEMPTY 5
334 #define UART_IR_RXUNDER 6
335 #define UART_IR_RXOVER 7
336 #define UART_IR_RXTIMEOUT 8
337 #define UART_IR_RXFULL 9
338 #define UART_IR_RXTHRESH 10
339 #define UART_IR_RXNOTEMPTY 11
340 #define UART_IR_RXFRAMEERR 12
341 #define UART_IR_RXPARERR 13
342 #define UART_IR_RXBRK 14
343 #define UART_IR_TXDONE 15
345 /* UART Fifo register */
346 #define UART_FIFO_REG 0x14
347 #define UART_FIFO_VALID_SHIFT 0
348 #define UART_FIFO_VALID_MASK 0xff
349 #define UART_FIFO_FRAMEERR_SHIFT 8
350 #define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
351 #define UART_FIFO_PARERR_SHIFT 9
352 #define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
353 #define UART_FIFO_BRKDET_SHIFT 10
354 #define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
355 #define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
356 UART_FIFO_PARERR_MASK | \
357 UART_FIFO_BRKDET_MASK)
360 /*************************************************************************
361 * _REG relative to RSET_GPIO
362 *************************************************************************/
365 #define GPIO_CTL_HI_REG 0x0
366 #define GPIO_CTL_LO_REG 0x4
367 #define GPIO_DATA_HI_REG 0x8
368 #define GPIO_DATA_LO_REG 0xC
370 /* GPIO mux registers and constants */
371 #define GPIO_MODE_REG 0x18
373 #define GPIO_MODE_6348_G4_DIAG 0x00090000
374 #define GPIO_MODE_6348_G4_UTOPIA 0x00080000
375 #define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000
376 #define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000
377 #define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000
378 #define GPIO_MODE_6348_G3_DIAG 0x00009000
379 #define GPIO_MODE_6348_G3_UTOPIA 0x00008000
380 #define GPIO_MODE_6348_G3_EXT_MII 0x00007000
381 #define GPIO_MODE_6348_G2_DIAG 0x00000900
382 #define GPIO_MODE_6348_G2_PCI 0x00000500
383 #define GPIO_MODE_6348_G1_DIAG 0x00000090
384 #define GPIO_MODE_6348_G1_UTOPIA 0x00000080
385 #define GPIO_MODE_6348_G1_SPI_UART 0x00000060
386 #define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060
387 #define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040
388 #define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020
389 #define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010
390 #define GPIO_MODE_6348_G0_DIAG 0x00000009
391 #define GPIO_MODE_6348_G0_EXT_MII 0x00000007
393 #define GPIO_MODE_6358_EXTRACS (1 << 5)
394 #define GPIO_MODE_6358_UART1 (1 << 6)
395 #define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
396 #define GPIO_MODE_6358_SERIAL_LED (1 << 10)
397 #define GPIO_MODE_6358_UTOPIA (1 << 12)
400 /*************************************************************************
401 * _REG relative to RSET_ENET
402 *************************************************************************/
404 /* Receiver Configuration register */
405 #define ENET_RXCFG_REG 0x0
406 #define ENET_RXCFG_ALLMCAST_SHIFT 1
407 #define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT)
408 #define ENET_RXCFG_PROMISC_SHIFT 3
409 #define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT)
410 #define ENET_RXCFG_LOOPBACK_SHIFT 4
411 #define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT)
412 #define ENET_RXCFG_ENFLOW_SHIFT 5
413 #define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT)
415 /* Receive Maximum Length register */
416 #define ENET_RXMAXLEN_REG 0x4
417 #define ENET_RXMAXLEN_SHIFT 0
418 #define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT)
420 /* Transmit Maximum Length register */
421 #define ENET_TXMAXLEN_REG 0x8
422 #define ENET_TXMAXLEN_SHIFT 0
423 #define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT)
425 /* MII Status/Control register */
426 #define ENET_MIISC_REG 0x10
427 #define ENET_MIISC_MDCFREQDIV_SHIFT 0
428 #define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
429 #define ENET_MIISC_PREAMBLEEN_SHIFT 7
430 #define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT)
432 /* MII Data register */
433 #define ENET_MIIDATA_REG 0x14
434 #define ENET_MIIDATA_DATA_SHIFT 0
435 #define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT)
436 #define ENET_MIIDATA_TA_SHIFT 16
437 #define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT)
438 #define ENET_MIIDATA_REG_SHIFT 18
439 #define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT)
440 #define ENET_MIIDATA_PHYID_SHIFT 23
441 #define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT)
442 #define ENET_MIIDATA_OP_READ_MASK (0x6 << 28)
443 #define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28)
445 /* Ethernet Interrupt Mask register */
446 #define ENET_IRMASK_REG 0x18
448 /* Ethernet Interrupt register */
449 #define ENET_IR_REG 0x1c
450 #define ENET_IR_MII (1 << 0)
451 #define ENET_IR_MIB (1 << 1)
452 #define ENET_IR_FLOWC (1 << 2)
454 /* Ethernet Control register */
455 #define ENET_CTL_REG 0x2c
456 #define ENET_CTL_ENABLE_SHIFT 0
457 #define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT)
458 #define ENET_CTL_DISABLE_SHIFT 1
459 #define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT)
460 #define ENET_CTL_SRESET_SHIFT 2
461 #define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT)
462 #define ENET_CTL_EPHYSEL_SHIFT 3
463 #define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT)
465 /* Transmit Control register */
466 #define ENET_TXCTL_REG 0x30
467 #define ENET_TXCTL_FD_SHIFT 0
468 #define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT)
470 /* Transmit Watermask register */
471 #define ENET_TXWMARK_REG 0x34
472 #define ENET_TXWMARK_WM_SHIFT 0
473 #define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT)
475 /* MIB Control register */
476 #define ENET_MIBCTL_REG 0x38
477 #define ENET_MIBCTL_RDCLEAR_SHIFT 0
478 #define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT)
480 /* Perfect Match Data Low register */
481 #define ENET_PML_REG(x) (0x58 + (x) * 8)
482 #define ENET_PMH_REG(x) (0x5c + (x) * 8)
483 #define ENET_PMH_DATAVALID_SHIFT 16
484 #define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT)
487 #define ENET_MIB_REG(x) (0x200 + (x) * 4)
488 #define ENET_MIB_REG_COUNT 55
491 /*************************************************************************
492 * _REG relative to RSET_ENETDMA
493 *************************************************************************/
495 /* Controller Configuration Register */
496 #define ENETDMA_CFG_REG (0x0)
497 #define ENETDMA_CFG_EN_SHIFT 0
498 #define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT)
499 #define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1))
501 /* Flow Control Descriptor Low Threshold register */
502 #define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6)
504 /* Flow Control Descriptor High Threshold register */
505 #define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6)
507 /* Flow Control Descriptor Buffer Alloca Threshold register */
508 #define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6)
509 #define ENETDMA_BUFALLOC_FORCE_SHIFT 31
510 #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
512 /* Channel Configuration register */
513 #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10)
514 #define ENETDMA_CHANCFG_EN_SHIFT 0
515 #define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
516 #define ENETDMA_CHANCFG_PKTHALT_SHIFT 1
517 #define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
519 /* Interrupt Control/Status register */
520 #define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10)
521 #define ENETDMA_IR_BUFDONE_MASK (1 << 0)
522 #define ENETDMA_IR_PKTDONE_MASK (1 << 1)
523 #define ENETDMA_IR_NOTOWNER_MASK (1 << 2)
525 /* Interrupt Mask register */
526 #define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10)
528 /* Maximum Burst Length */
529 #define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10)
531 /* Ring Start Address register */
532 #define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10)
534 /* State Ram Word 2 */
535 #define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10)
537 /* State Ram Word 3 */
538 #define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10)
540 /* State Ram Word 4 */
541 #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
544 /*************************************************************************
545 * _REG relative to RSET_OHCI_PRIV
546 *************************************************************************/
548 #define OHCI_PRIV_REG 0x0
549 #define OHCI_PRIV_PORT1_HOST_SHIFT 0
550 #define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT)
551 #define OHCI_PRIV_REG_SWAP_SHIFT 3
552 #define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT)
555 /*************************************************************************
556 * _REG relative to RSET_USBH_PRIV
557 *************************************************************************/
559 #define USBH_PRIV_SWAP_REG 0x0
560 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
561 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
562 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
563 #define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
564 #define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1
565 #define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
566 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
567 #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
569 #define USBH_PRIV_TEST_REG 0x24
572 /*************************************************************************
573 * _REG relative to RSET_MPI
574 *************************************************************************/
576 /* well known (hard wired) chip select */
577 #define MPI_CS_PCMCIA_COMMON 4
578 #define MPI_CS_PCMCIA_ATTR 5
579 #define MPI_CS_PCMCIA_IO 6
581 /* Chip select base register */
582 #define MPI_CSBASE_REG(x) (0x0 + (x) * 8)
583 #define MPI_CSBASE_BASE_SHIFT 13
584 #define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT)
585 #define MPI_CSBASE_SIZE_SHIFT 0
586 #define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT)
588 #define MPI_CSBASE_SIZE_8K 0
589 #define MPI_CSBASE_SIZE_16K 1
590 #define MPI_CSBASE_SIZE_32K 2
591 #define MPI_CSBASE_SIZE_64K 3
592 #define MPI_CSBASE_SIZE_128K 4
593 #define MPI_CSBASE_SIZE_256K 5
594 #define MPI_CSBASE_SIZE_512K 6
595 #define MPI_CSBASE_SIZE_1M 7
596 #define MPI_CSBASE_SIZE_2M 8
597 #define MPI_CSBASE_SIZE_4M 9
598 #define MPI_CSBASE_SIZE_8M 10
599 #define MPI_CSBASE_SIZE_16M 11
600 #define MPI_CSBASE_SIZE_32M 12
601 #define MPI_CSBASE_SIZE_64M 13
602 #define MPI_CSBASE_SIZE_128M 14
603 #define MPI_CSBASE_SIZE_256M 15
605 /* Chip select control register */
606 #define MPI_CSCTL_REG(x) (0x4 + (x) * 8)
607 #define MPI_CSCTL_ENABLE_MASK (1 << 0)
608 #define MPI_CSCTL_WAIT_SHIFT 1
609 #define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT)
610 #define MPI_CSCTL_DATA16_MASK (1 << 4)
611 #define MPI_CSCTL_SYNCMODE_MASK (1 << 7)
612 #define MPI_CSCTL_TSIZE_MASK (1 << 8)
613 #define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10)
614 #define MPI_CSCTL_SETUP_SHIFT 16
615 #define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT)
616 #define MPI_CSCTL_HOLD_SHIFT 20
617 #define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT)
620 #define MPI_SP0_RANGE_REG 0x100
621 #define MPI_SP0_REMAP_REG 0x104
622 #define MPI_SP0_REMAP_ENABLE_MASK (1 << 0)
623 #define MPI_SP1_RANGE_REG 0x10C
624 #define MPI_SP1_REMAP_REG 0x110
625 #define MPI_SP1_REMAP_ENABLE_MASK (1 << 0)
627 #define MPI_L2PCFG_REG 0x11C
628 #define MPI_L2PCFG_CFG_TYPE_SHIFT 0
629 #define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
630 #define MPI_L2PCFG_REG_SHIFT 2
631 #define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT)
632 #define MPI_L2PCFG_FUNC_SHIFT 8
633 #define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT)
634 #define MPI_L2PCFG_DEVNUM_SHIFT 11
635 #define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
636 #define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30)
637 #define MPI_L2PCFG_CFG_SEL_MASK (1 << 31)
639 #define MPI_L2PMEMRANGE1_REG 0x120
640 #define MPI_L2PMEMBASE1_REG 0x124
641 #define MPI_L2PMEMREMAP1_REG 0x128
642 #define MPI_L2PMEMRANGE2_REG 0x12C
643 #define MPI_L2PMEMBASE2_REG 0x130
644 #define MPI_L2PMEMREMAP2_REG 0x134
645 #define MPI_L2PIORANGE_REG 0x138
646 #define MPI_L2PIOBASE_REG 0x13C
647 #define MPI_L2PIOREMAP_REG 0x140
648 #define MPI_L2P_BASE_MASK (0xffff8000)
649 #define MPI_L2PREMAP_ENABLED_MASK (1 << 0)
650 #define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2)
652 #define MPI_PCIMODESEL_REG 0x144
653 #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
654 #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
655 #define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2)
656 #define MPI_PCIMODESEL_PREFETCH_SHIFT 4
657 #define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
659 #define MPI_LOCBUSCTL_REG 0x14C
660 #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0)
661 #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1)
663 #define MPI_LOCINT_REG 0x150
664 #define MPI_LOCINT_MASK(x) (1 << (x + 16))
665 #define MPI_LOCINT_STAT(x) (1 << (x))
666 #define MPI_LOCINT_DIR_FAILED 6
667 #define MPI_LOCINT_EXT_PCI_INT 7
668 #define MPI_LOCINT_SERR 8
669 #define MPI_LOCINT_CSERR 9
671 #define MPI_PCICFGCTL_REG 0x178
672 #define MPI_PCICFGCTL_CFGADDR_SHIFT 2
673 #define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
674 #define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7)
676 #define MPI_PCICFGDATA_REG 0x17C
678 /* PCI host bridge custom register */
679 #define BCMPCI_REG_TIMERS 0x40
680 #define REG_TIMER_TRDY_SHIFT 0
681 #define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT)
682 #define REG_TIMER_RETRY_SHIFT 8
683 #define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT)
686 /*************************************************************************
687 * _REG relative to RSET_PCMCIA
688 *************************************************************************/
690 #define PCMCIA_C1_REG 0x0
691 #define PCMCIA_C1_CD1_MASK (1 << 0)
692 #define PCMCIA_C1_CD2_MASK (1 << 1)
693 #define PCMCIA_C1_VS1_MASK (1 << 2)
694 #define PCMCIA_C1_VS2_MASK (1 << 3)
695 #define PCMCIA_C1_VS1OE_MASK (1 << 6)
696 #define PCMCIA_C1_VS2OE_MASK (1 << 7)
697 #define PCMCIA_C1_CBIDSEL_SHIFT (8)
698 #define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
699 #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13)
700 #define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14)
701 #define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15)
702 #define PCMCIA_C1_RESET_MASK (1 << 18)
704 #define PCMCIA_C2_REG 0x8
705 #define PCMCIA_C2_DATA16_MASK (1 << 0)
706 #define PCMCIA_C2_BYTESWAP_MASK (1 << 1)
707 #define PCMCIA_C2_RWCOUNT_SHIFT 2
708 #define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
709 #define PCMCIA_C2_INACTIVE_SHIFT 8
710 #define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT)
711 #define PCMCIA_C2_SETUP_SHIFT 16
712 #define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT)
713 #define PCMCIA_C2_HOLD_SHIFT 24
714 #define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT)
717 /*************************************************************************
718 * _REG relative to RSET_SDRAM
719 *************************************************************************/
721 #define SDRAM_CFG_REG 0x0
722 #define SDRAM_CFG_ROW_SHIFT 4
723 #define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
724 #define SDRAM_CFG_COL_SHIFT 6
725 #define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
726 #define SDRAM_CFG_32B_SHIFT 10
727 #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
728 #define SDRAM_CFG_BANK_SHIFT 13
729 #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
731 #define SDRAM_PRIO_REG 0x2C
732 #define SDRAM_PRIO_MIPS_SHIFT 29
733 #define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
734 #define SDRAM_PRIO_ADSL_SHIFT 30
735 #define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT)
736 #define SDRAM_PRIO_EN_SHIFT 31
737 #define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT)
740 /*************************************************************************
741 * _REG relative to RSET_MEMC
742 *************************************************************************/
744 #define MEMC_CFG_REG 0x4
745 #define MEMC_CFG_32B_SHIFT 1
746 #define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
747 #define MEMC_CFG_COL_SHIFT 3
748 #define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
749 #define MEMC_CFG_ROW_SHIFT 6
750 #define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
753 /*************************************************************************
754 * _REG relative to RSET_DDR
755 *************************************************************************/
757 #define DDR_DMIPSPLLCFG_REG 0x18
758 #define DMIPSPLLCFG_M1_SHIFT 0
759 #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
760 #define DMIPSPLLCFG_N1_SHIFT 23
761 #define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT)
762 #define DMIPSPLLCFG_N2_SHIFT 29
763 #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
765 /*************************************************************************
766 * _REG relative to RSET_SPI
767 *************************************************************************/
769 /* BCM 6338 SPI core */
770 #define SPI_BCM_6338_SPI_CMD 0x00 /* 16-bits register */
771 #define SPI_BCM_6338_SPI_INT_STATUS 0x02
772 #define SPI_BCM_6338_SPI_MASK_INT_ST 0x03
773 #define SPI_BCM_6338_SPI_INT_MASK 0x04
774 #define SPI_BCM_6338_SPI_ST 0x05
775 #define SPI_BCM_6338_SPI_CLK_CFG 0x06
776 #define SPI_BCM_6338_SPI_FILL_BYTE 0x07
777 #define SPI_BCM_6338_SPI_MSG_TAIL 0x09
778 #define SPI_BCM_6338_SPI_RX_TAIL 0x0b
779 #define SPI_BCM_6338_SPI_MSG_CTL 0x40
780 #define SPI_BCM_6338_SPI_MSG_DATA 0x41
781 #define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f
782 #define SPI_BCM_6338_SPI_RX_DATA 0x80
783 #define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
785 /* BCM 6348 SPI core */
786 #define SPI_BCM_6348_SPI_MASK_INT_ST 0x00
787 #define SPI_BCM_6348_SPI_INT_STATUS 0x01
788 #define SPI_BCM_6348_SPI_CMD 0x02 /* 16-bits register */
789 #define SPI_BCM_6348_SPI_FILL_BYTE 0x04
790 #define SPI_BCM_6348_SPI_CLK_CFG 0x05
791 #define SPI_BCM_6348_SPI_ST 0x06
792 #define SPI_BCM_6348_SPI_INT_MASK 0x07
793 #define SPI_BCM_6348_SPI_RX_TAIL 0x08
794 #define SPI_BCM_6348_SPI_MSG_TAIL 0x10
795 #define SPI_BCM_6348_SPI_MSG_DATA 0x40
796 #define SPI_BCM_6348_SPI_MSG_CTL 0x42
797 #define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
798 #define SPI_BCM_6348_SPI_RX_DATA 0x80
799 #define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
801 /* BCM 6358 SPI core */
802 #define SPI_BCM_6358_MSG_CTL 0x00 /* 16-bits register */
804 #define SPI_BCM_6358_SPI_MSG_DATA 0x02
805 #define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
807 #define SPI_BCM_6358_SPI_RX_DATA 0x400
808 #define SPI_BCM_6358_SPI_RX_DATA_SIZE 0x220
810 #define SPI_BCM_6358_SPI_CMD 0x700 /* 16-bits register */
812 #define SPI_BCM_6358_SPI_INT_STATUS 0x702
813 #define SPI_BCM_6358_SPI_MASK_INT_ST 0x703
815 #define SPI_BCM_6358_SPI_INT_MASK 0x704
817 #define SPI_BCM_6358_SPI_STATUS 0x705
819 #define SPI_BCM_6358_SPI_CLK_CFG 0x706
821 #define SPI_BCM_6358_SPI_FILL_BYTE 0x707
822 #define SPI_BCM_6358_SPI_MSG_TAIL 0x709
823 #define SPI_BCM_6358_SPI_RX_TAIL 0x70B
825 /* Shared SPI definitions */
827 /* Message configuration */
828 #define SPI_FD_RW 0x00
829 #define SPI_HD_W 0x01
830 #define SPI_HD_R 0x02
831 #define SPI_BYTE_CNT_SHIFT 0
832 #define SPI_MSG_TYPE_SHIFT 14
835 #define SPI_CMD_NOOP 0x01
836 #define SPI_CMD_SOFT_RESET 0x02
837 #define SPI_CMD_HARD_RESET 0x04
838 #define SPI_CMD_START_IMMEDIATE 0x08
839 #define SPI_CMD_COMMAND_SHIFT 0
840 #define SPI_CMD_COMMAND_MASK 0x000f
841 #define SPI_CMD_DEVICE_ID_SHIFT 4
842 #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
843 #define SPI_CMD_ONE_BYTE_SHIFT 11
844 #define SPI_CMD_ONE_WIRE_SHIFT 12
845 #define SPI_DEV_ID_0 0
846 #define SPI_DEV_ID_1 1
847 #define SPI_DEV_ID_2 2
848 #define SPI_DEV_ID_3 3
851 #define SPI_INTR_CMD_DONE 0x01
852 #define SPI_INTR_RX_OVERFLOW 0x02
853 #define SPI_INTR_TX_UNDERFLOW 0x04
854 #define SPI_INTR_TX_OVERFLOW 0x08
855 #define SPI_INTR_RX_UNDERFLOW 0x10
856 #define SPI_INTR_CLEAR_ALL 0x1f
859 #define SPI_RX_EMPTY 0x02
860 #define SPI_CMD_BUSY 0x04
861 #define SPI_SERIAL_BUSY 0x08
863 /* Clock configuration */
864 #define SPI_CLK_20MHZ 0x00
865 #define SPI_CLK_0_391MHZ 0x01
866 #define SPI_CLK_0_781MHZ 0x02 /* default */
867 #define SPI_CLK_1_563MHZ 0x03
868 #define SPI_CLK_3_125MHZ 0x04
869 #define SPI_CLK_6_250MHZ 0x05
870 #define SPI_CLK_12_50MHZ 0x06
871 #define SPI_CLK_25MHZ 0x07
872 #define SPI_CLK_MASK 0x07
873 #define SPI_SSOFFTIME_MASK 0x38
874 #define SPI_SSOFFTIME_SHIFT 3
875 #define SPI_BYTE_SWAP 0x80
878 #endif /* BCM63XX_REGS_H_ */
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