target/linux/brcm63xx-2.6/files/include/asm-mips/mach-bcm963xx/6348_map_part.h

   1 /*
   2 <:copyright-gpl
   3  Copyright 2002 Broadcom Corp. All Rights Reserved.
   4
   5  This program is free software; you can distribute it and/or modify it
   6  under the terms of the GNU General Public License (Version 2) as
   7  published by the Free Software Foundation.
   8
   9  This program is distributed in the hope it will be useful, but WITHOUT
  10  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  for more details.
  13
  14  You should have received a copy of the GNU General Public License along
  15  with this program; if not, write to the Free Software Foundation, Inc.,
  16  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17 :>
  18 */
  19
  20 #ifndef __BCM6348_MAP_H
  21 #define __BCM6348_MAP_H
  22
  23 #include "bcmtypes.h"
  24
  25 #define PERF_BASE           0xfffe0000
  26 #define TIMR_BASE           0xfffe0200
  27 #define UART_BASE           0xfffe0300
  28 #define GPIO_BASE           0xfffe0400
  29 #define MPI_BASE            0xfffe2000    /* MPI control registers */
  30 #define USB_HOST_BASE       0xfffe1b00    /* USB host registers */
  31 #define USB_HOST_NON_OHCI   0xfffe1c00    /* USB host non-OHCI registers */
  32
  33 typedef struct PerfControl {
  34   uint32        RevID;
  35   uint16        testControl;
  36   uint16        blkEnables;
  37 #define EMAC_CLK_EN     0x0010
  38 #define SAR_CLK_EN      0x0020
  39 #define USBS_CLK_EN     0x0040
  40 #define USBH_CLK_EN     0x0100
  41
  42   uint32        pll_control;
  43 #define SOFT_RESET 0x00000001
  44
  45   uint32        IrqMask;
  46   uint32        IrqStatus;
  47
  48   uint32        ExtIrqCfg;
  49 #define EI_SENSE_SHFT   0
  50 #define EI_STATUS_SHFT  5
  51 #define EI_CLEAR_SHFT   10
  52 #define EI_MASK_SHFT    15
  53 #define EI_INSENS_SHFT  20
  54 #define EI_LEVEL_SHFT   25
  55
  56   uint32        unused[4];      /* (18) */
  57   uint32        BlockSoftReset; /* (28) */
  58 #define BSR_SPI             0x00000001
  59 #define BSR_EMAC            0x00000004
  60 #define BSR_USBH            0x00000008
  61 #define BSR_USBS            0x00000010
  62 #define BSR_ADSL            0x00000020
  63 #define BSR_DMAMEM          0x00000040
  64 #define BSR_SAR             0x00000080
  65 #define BSR_ACLC            0x00000100
  66 #define BSR_ADSL_MIPS_PLL   0x00000400
  67 #define BSR_ALL_BLOCKS      \
  68     (BSR_SPI | BSR_EMAC | BSR_USBH | BSR_USBS | BSR_ADSL | BSR_DMAMEM | \
  69      BSR_SAR | BSR_ACLC | BSR_ADSL_MIPS_PLL)
  70   uint32        unused2[2];     /* (2c) */
  71   uint32        PllStrap;       /* (34) */
  72 #define PLL_N1_SHFT         20
  73 #define PLL_N1_MASK         (7<<PLL_N1_SHFT)
  74 #define PLL_N2_SHFT         15
  75 #define PLL_N2_MASK         (0x1f<<PLL_N2_SHFT)
  76 #define PLL_M1_REF_SHFT     12
  77 #define PLL_M1_REF_MASK     (7<<PLL_M1_REF_SHFT)
  78 #define PLL_M2_REF_SHFT     9
  79 #define PLL_M2_REF_MASK     (7<<PLL_M2_REF_SHFT)
  80 #define PLL_M1_CPU_SHFT     6
  81 #define PLL_M1_CPU_MASK     (7<<PLL_M1_CPU_SHFT)
  82 #define PLL_M1_BUS_SHFT     3
  83 #define PLL_M1_BUS_MASK     (7<<PLL_M1_BUS_SHFT)
  84 #define PLL_M2_BUS_SHFT     0
  85 #define PLL_M2_BUS_MASK     (7<<PLL_M2_BUS_SHFT)
  86 } PerfControl;
  87
  88 #define PERF ((volatile PerfControl * const) PERF_BASE)
  89
  90 typedef struct Timer {
  91   uint16        unused0;
  92   byte          TimerMask;
  93 #define TIMER0EN        0x01
  94 #define TIMER1EN        0x02
  95 #define TIMER2EN        0x04
  96   byte          TimerInts;
  97 #define TIMER0          0x01
  98 #define TIMER1          0x02
  99 #define TIMER2          0x04
 100 #define WATCHDOG        0x08
 101   uint32        TimerCtl0;
 102   uint32        TimerCtl1;
 103   uint32        TimerCtl2;
 104 #define TIMERENABLE     0x80000000
 105 #define RSTCNTCLR       0x40000000
 106   uint32        TimerCnt0;
 107   uint32        TimerCnt1;
 108   uint32        TimerCnt2;
 109   uint32        WatchDogDefCount;
 110
 111   /* Write 0xff00 0x00ff to Start timer
 112    * Write 0xee00 0x00ee to Stop and re-load default count
 113    * Read from this register returns current watch dog count
 114    */
 115   uint32        WatchDogCtl;
 116
 117   /* Number of 40-MHz ticks for WD Reset pulse to last */
 118   uint32        WDResetCount;
 119 } Timer;
 120
 121 #define TIMER ((volatile Timer * const) TIMR_BASE)
 122
 123 typedef struct UartChannel {
 124   byte          unused0;
 125   byte          control;
 126 #define BRGEN           0x80    /* Control register bit defs */
 127 #define TXEN            0x40
 128 #define RXEN            0x20
 129 #define LOOPBK          0x10
 130 #define TXPARITYEN      0x08
 131 #define TXPARITYEVEN    0x04
 132 #define RXPARITYEN      0x02
 133 #define RXPARITYEVEN    0x01
 134
 135   byte          config;
 136 #define XMITBREAK       0x40
 137 #define BITS5SYM        0x00
 138 #define BITS6SYM        0x10
 139 #define BITS7SYM        0x20
 140 #define BITS8SYM        0x30
 141 #define ONESTOP         0x07
 142 #define TWOSTOP         0x0f
 143   /* 4-LSBS represent STOP bits/char
 144    * in 1/8 bit-time intervals.  Zero
 145    * represents 1/8 stop bit interval.
 146    * Fifteen represents 2 stop bits.
 147    */
 148   byte          fifoctl;
 149 #define RSTTXFIFOS      0x80
 150 #define RSTRXFIFOS      0x40
 151   /* 5-bit TimeoutCnt is in low bits of this register.
 152    *  This count represents the number of characters
 153    *  idle times before setting receive Irq when below threshold
 154    */
 155   uint32        baudword;
 156   /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate
 157    */
 158
 159   byte          txf_levl;       /* Read-only fifo depth */
 160   byte          rxf_levl;       /* Read-only fifo depth */
 161   byte          fifocfg;        /* Upper 4-bits are TxThresh, Lower are
 162                                  *      RxThreshold.  Irq can be asserted
 163                                  *      when rx fifo> thresh, txfifo<thresh
 164                                  */
 165   byte          prog_out;       /* Set value of DTR (Bit0), RTS (Bit1)
 166                                  *  if these bits are also enabled to GPIO_o
 167                                  */
 168 #define DTREN   0x01
 169 #define RTSEN   0x02
 170
 171   byte          unused1;
 172   byte          DeltaIPEdgeNoSense;     /* Low 4-bits, set corr bit to 1 to
 173                                          * detect irq on rising AND falling
 174                                          * edges for corresponding GPIO_i
 175                                          * if enabled (edge insensitive)
 176                                          */
 177   byte          DeltaIPConfig_Mask;     /* Upper 4 bits: 1 for posedge sense
 178                                          *      0 for negedge sense if
 179                                          *      not configured for edge
 180                                          *      insensitive (see above)
 181                                          * Lower 4 bits: Mask to enable change
 182                                          *  detection IRQ for corresponding
 183                                          *  GPIO_i
 184                                          */
 185   byte          DeltaIP_SyncIP;         /* Upper 4 bits show which bits
 186                                          *  have changed (may set IRQ).
 187                                          *  read automatically clears bit
 188                                          * Lower 4 bits are actual status
 189                                          */
 190
 191   uint16        intMask;                                /* Same Bit defs for Mask and status */
 192   uint16        intStatus;
 193 #define DELTAIP         0x0001
 194 #define TXUNDERR        0x0002
 195 #define TXOVFERR        0x0004
 196 #define TXFIFOTHOLD     0x0008
 197 #define TXREADLATCH     0x0010
 198 #define TXFIFOEMT       0x0020
 199 #define RXUNDERR        0x0040
 200 #define RXOVFERR        0x0080
 201 #define RXTIMEOUT       0x0100
 202 #define RXFIFOFULL      0x0200
 203 #define RXFIFOTHOLD     0x0400
 204 #define RXFIFONE        0x0800
 205 #define RXFRAMERR       0x1000
 206 #define RXPARERR        0x2000
 207 #define RXBRK           0x4000
 208
 209   uint16        unused2;
 210   uint16        Data;                   /* Write to TX, Read from RX */
 211                                         /* bits 11:8 are BRK,PAR,FRM errors */
 212
 213   uint32                unused3;
 214   uint32                unused4;
 215 } Uart;
 216
 217 #define UART ((volatile Uart * const) UART_BASE)
 218
 219 typedef struct GpioControl {
 220   uint32        GPIODir_high; /* bits 36:32 */
 221   uint32        GPIODir;      /* bits 31:00 */
 222   uint32        GPIOio_high;  /* bits 36:32 */
 223   uint32        GPIOio;       /* bits 31:00 */
 224   uint32        LEDCtrl;
 225 #define         LED3_STROBE             0x08000000
 226 #define         LED2_STROBE             0x04000000
 227 #define         LED1_STROBE             0x02000000
 228 #define         LED0_STROBE             0x01000000
 229 #define         LED_TEST                0x00010000
 230 #define         LED3_DISABLE_LINK_ACT   0x00008000
 231 #define         LED2_DISABLE_LINK_ACT   0x00004000
 232 #define         LED1_DISABLE_LINK_ACT   0x00002000
 233 #define         LED0_DISABLE_LINK_ACT   0x00001000
 234 #define         LED_INTERVAL_SET_MASK   0x00000f00
 235 #define         LED_INTERVAL_SET_320MS  0x00000500
 236 #define         LED_INTERVAL_SET_160MS  0x00000400
 237 #define         LED_INTERVAL_SET_80MS   0x00000300
 238 #define         LED_INTERVAL_SET_40MS   0x00000200
 239 #define         LED_INTERVAL_SET_20MS   0x00000100
 240 #define         LED3_ON                 0x00000080
 241 #define         LED2_ON                 0x00000040
 242 #define         LED1_ON                 0x00000020
 243 #define         LED0_ON                 0x00000010
 244 #define         LED3_ENABLE             0x00000008
 245 #define         LED2_ENABLE             0x00000004
 246 #define         LED1_ENABLE             0x00000002
 247 #define         LED0_ENABLE             0x00000001
 248   uint32        SpiSlaveCfg;
 249 #define         SPI_SLAVE_RESET         0x00010000
 250 #define         SPI_RESTRICT            0x00000400
 251 #define         SPI_DELAY_DISABLE       0x00000200
 252 #define         SPI_PROBE_MUX_SEL_MASK  0x000001e0
 253 #define         SPI_SER_ADDR_CFG_MASK   0x0000000c
 254 #define         SPI_MODE                0x00000001
 255   uint32        GPIOMode;
 256 #define         GROUP4_DIAG             0x00090000
 257 #define         GROUP4_UTOPIA           0x00080000
 258 #define         GROUP4_LEGACY_LED       0x00030000
 259 #define         GROUP4_MII_SNOOP        0x00020000
 260 #define         GROUP4_EXT_EPHY         0x00010000
 261 #define         GROUP3_DIAG             0x00009000
 262 #define         GROUP3_UTOPIA           0x00008000
 263 #define         GROUP3_EXT_MII          0x00007000
 264 #define         GROUP2_DIAG             0x00000900
 265 #define         GROUP2_PCI              0x00000500
 266 #define         GROUP1_DIAG             0x00000090
 267 #define         GROUP1_UTOPIA           0x00000080
 268 #define         GROUP1_SPI_UART         0x00000060
 269 #define         GROUP1_SPI_MASTER       0x00000060
 270 #define         GROUP1_MII_PCCARD       0x00000040
 271 #define         GROUP1_MII_SNOOP        0x00000020
 272 #define         GROUP1_EXT_EPHY         0x00000010
 273 #define         GROUP0_DIAG             0x00000009
 274 #define         GROUP0_EXT_MII          0x00000007
 275
 276 } GpioControl;
 277
 278 #define GPIO ((volatile GpioControl * const) GPIO_BASE)
 279
 280 /* Number to mask conversion macro used for GPIODir and GPIOio */
 281 #define GPIO_NUM_TOTAL_BITS_MASK        0x3f
 282 #define GPIO_NUM_MAX_BITS_MASK          0x1f
 283 #define GPIO_NUM_TO_MASK(X)             ( (((X) & GPIO_NUM_TOTAL_BITS_MASK) < 32) ? (1 << ((X) & GPIO_NUM_MAX_BITS_MASK)) : (0) )
 284
 285 /* Number to mask conversion macro used for GPIODir_high and GPIOio_high */
 286 #define GPIO_NUM_MAX_BITS_MASK_HIGH     0x07
 287 #define GPIO_NUM_TO_MASK_HIGH(X)        ( (((X) & GPIO_NUM_TOTAL_BITS_MASK) >= 32) ? (1 << ((X-32) & GPIO_NUM_MAX_BITS_MASK_HIGH)) : (0) )
 288
 289
 290 /*
 291 ** External Bus Interface
 292 */
 293 typedef struct EbiChipSelect {
 294   uint32        base;                   /* base address in upper 24 bits */
 295 #define EBI_SIZE_8K         0
 296 #define EBI_SIZE_16K        1
 297 #define EBI_SIZE_32K        2
 298 #define EBI_SIZE_64K        3
 299 #define EBI_SIZE_128K       4
 300 #define EBI_SIZE_256K       5
 301 #define EBI_SIZE_512K       6
 302 #define EBI_SIZE_1M         7
 303 #define EBI_SIZE_2M         8
 304 #define EBI_SIZE_4M         9
 305 #define EBI_SIZE_8M         10
 306 #define EBI_SIZE_16M        11
 307 #define EBI_SIZE_32M        12
 308 #define EBI_SIZE_64M        13
 309 #define EBI_SIZE_128M       14
 310 #define EBI_SIZE_256M       15
 311   uint32        config;
 312 #define EBI_ENABLE          0x00000001      /* .. enable this range */
 313 #define EBI_WAIT_STATES     0x0000000e      /* .. mask for wait states */
 314 #define EBI_WTST_SHIFT      1               /* .. for shifting wait states */
 315 #define EBI_WORD_WIDE       0x00000010      /* .. 16-bit peripheral, else 8 */
 316 #define EBI_WREN            0x00000020      /* enable posted writes */
 317 #define EBI_POLARITY        0x00000040      /* .. set to invert something,
 318                                         **    don't know what yet */
 319 #define EBI_TS_TA_MODE      0x00000080      /* .. use TS/TA mode */
 320 #define EBI_TS_SEL          0x00000100      /* .. drive tsize, not bs_b */
 321 #define EBI_FIFO            0x00000200      /* .. use fifo */
 322 #define EBI_RE              0x00000400      /* .. Reverse Endian */
 323 } EbiChipSelect;
 324
 325 typedef struct MpiRegisters {
 326   EbiChipSelect cs[7];                  /* size chip select configuration */
 327 #define EBI_CS0_BASE            0
 328 #define EBI_CS1_BASE            1
 329 #define EBI_CS2_BASE            2
 330 #define EBI_CS3_BASE            3
 331 #define PCMCIA_COMMON_BASE      4
 332 #define PCMCIA_ATTRIBUTE_BASE   5
 333 #define PCMCIA_IO_BASE          6
 334   uint32        unused0[2];             /* reserved */
 335   uint32        ebi_control;            /* ebi control */
 336   uint32        unused1[4];             /* reserved */
 337 #define EBI_ACCESS_TIMEOUT      0x000007FF
 338   uint32        pcmcia_cntl1;           /* pcmcia control 1 */
 339 #define PCCARD_CARD_RESET       0x00040000
 340 #define CARDBUS_ENABLE          0x00008000
 341 #define PCMCIA_ENABLE           0x00004000
 342 #define PCMCIA_GPIO_ENABLE      0x00002000
 343 #define CARDBUS_IDSEL           0x00001F00
 344 #define VS2_OEN                 0x00000080
 345 #define VS1_OEN                 0x00000040
 346 #define VS2_OUT                 0x00000020
 347 #define VS1_OUT                 0x00000010
 348 #define VS2_IN                  0x00000008
 349 #define VS1_IN                  0x00000004
 350 #define CD2_IN                  0x00000002
 351 #define CD1_IN                  0x00000001
 352 #define VS_MASK                 0x0000000C
 353 #define CD_MASK                 0x00000003
 354   uint32        unused2;                /* reserved */
 355   uint32        pcmcia_cntl2;           /* pcmcia control 2 */
 356 #define PCMCIA_BYTESWAP_DIS     0x00000002
 357 #define PCMCIA_HALFWORD_EN      0x00000001
 358 #define RW_ACTIVE_CNT_BIT       2
 359 #define INACTIVE_CNT_BIT        8
 360 #define CE_SETUP_CNT_BIT        16
 361 #define CE_HOLD_CNT_BIT         24
 362   uint32        unused3[40];            /* reserved */
 363
 364   uint32        sp0range;               /* PCI to internal system bus address space */
 365   uint32        sp0remap;
 366   uint32        sp0cfg;
 367   uint32        sp1range;
 368   uint32        sp1remap;
 369   uint32        sp1cfg;
 370
 371   uint32        EndianCfg;
 372
 373   uint32        l2pcfgctl;              /* internal system bus to PCI IO/Cfg control */
 374 #define DIR_CFG_SEL             0x80000000 /* change from PCI I/O access to PCI config access */
 375 #define DIR_CFG_USEREG          0x40000000 /* use this register info for PCI configuration access */
 376 #define DEVICE_NUMBER           0x00007C00 /* device number for the PCI configuration access */
 377 #define FUNC_NUMBER             0x00000300 /* function number for the PCI configuration access */
 378 #define REG_NUMBER              0x000000FC /* register number for the PCI configuration access */
 379 #define CONFIG_TYPE             0x00000003 /* configuration type for the PCI configuration access */
 380
 381   uint32        l2pmrange1;             /* internal system bus to PCI memory space */
 382 #define PCI_SIZE_64K            0xFFFF0000
 383 #define PCI_SIZE_128K           0xFFFE0000
 384 #define PCI_SIZE_256K           0xFFFC0000
 385 #define PCI_SIZE_512K           0xFFF80000
 386 #define PCI_SIZE_1M             0xFFF00000
 387 #define PCI_SIZE_2M             0xFFE00000
 388 #define PCI_SIZE_4M             0xFFC00000
 389 #define PCI_SIZE_8M             0xFF800000
 390 #define PCI_SIZE_16M            0xFF000000
 391 #define PCI_SIZE_32M            0xFE000000
 392   uint32        l2pmbase1;              /* kseg0 or kseg1 address & 0x1FFFFFFF */
 393   uint32        l2pmremap1;
 394 #define CARDBUS_MEM             0x00000004
 395 #define MEM_WINDOW_EN           0x00000001
 396   uint32        l2pmrange2;
 397   uint32        l2pmbase2;
 398   uint32        l2pmremap2;
 399   uint32        l2piorange;             /* internal system bus to PCI I/O space */
 400   uint32        l2piobase;
 401   uint32        l2pioremap;
 402
 403   uint32        pcimodesel;
 404 #define PCI2_INT_BUS_RD_PREFECH 0x000000F0
 405 #define PCI_BAR2_NOSWAP         0x00000002 /* BAR at offset 0x20 */
 406 #define PCI_BAR1_NOSWAP         0x00000001 /* BAR at affset 0x1c */
 407
 408   uint32        pciintstat;             /* PCI interrupt mask/status */
 409 #define MAILBOX1_SENT           0x08
 410 #define MAILBOX0_SENT           0x04
 411 #define MAILBOX1_MSG_RCV        0x02
 412 #define MAILBOX0_MSG_RCV        0x01
 413   uint32        locbuscntrl;            /* internal system bus control */
 414 #define DIR_U2P_NOSWAP          0x00000002
 415 #define EN_PCI_GPIO             0x00000001
 416   uint32        locintstat;             /* internal system bus interrupt mask/status */
 417 #define CSERR                   0x0200
 418 #define SERR                    0x0100
 419 #define EXT_PCI_INT             0x0080
 420 #define DIR_FAILED              0x0040
 421 #define DIR_COMPLETE            0x0020
 422 #define PCI_CFG                 0x0010
 423   uint32        unused5[7];
 424
 425   uint32        mailbox0;
 426   uint32        mailbox1;
 427
 428   uint32        pcicfgcntrl;            /* internal system bus PCI configuration control */
 429 #define PCI_CFG_REG_WRITE_EN    0x00000080
 430 #define PCI_CFG_ADDR            0x0000003C
 431   uint32        pcicfgdata;             /* internal system bus PCI configuration data */
 432
 433   uint32        locch2ctl;              /* PCI to interrnal system bus DMA (downstream) local control */
 434 #define MPI_DMA_HALT            0x00000008  /* idle after finish current memory burst */
 435 #define MPI_DMA_PKT_HALT        0x00000004  /* idle after an EOP flag is detected */
 436 #define MPI_DMA_STALL           0x00000002  /* idle after an EOP flag is detected */
 437 #define MPI_DMA_ENABLE          0x00000001  /* set to enable channel */
 438   uint32        locch2intStat;
 439 #define MPI_DMA_NO_DESC         0x00000004  /* no valid descriptors */
 440 #define MPI_DMA_DONE            0x00000002  /* packet xfer complete */
 441 #define MPI_DMA_BUFF_DONE       0x00000001  /* buffer done */
 442   uint32        locch2intMask;
 443   uint32        unused6;
 444   uint32        locch2descaddr;
 445   uint32        locch2status1;
 446 #define LOCAL_DESC_STATE        0xE0000000
 447 #define PCI_DESC_STATE          0x1C000000
 448 #define BYTE_DONE               0x03FFC000
 449 #define RING_ADDR               0x00003FFF
 450   uint32        locch2status2;
 451 #define BUFPTR_OFFSET           0x1FFF0000
 452 #define PCI_MASTER_STATE        0x000000C0
 453 #define LOC_MASTER_STATE        0x00000038
 454 #define CONTROL_STATE           0x00000007
 455   uint32        unused7;
 456
 457   uint32        locch1Ctl;              /*internal system bus to PCI DMA (upstream) local control */
 458 #define DMA_U2P_LE              0x00000200  /* local bus is little endian */
 459 #define DMA_U2P_NOSWAP          0x00000100  /* lccal bus is little endian but no data swapped */
 460   uint32        locch1intstat;
 461   uint32        locch1intmask;
 462   uint32        unused8;
 463   uint32        locch1descaddr;
 464   uint32        locch1status1;
 465   uint32        locch1status2;
 466   uint32        unused9;
 467
 468   uint32        pcich1ctl;              /* internal system bus to PCI DMA PCI control */
 469   uint32        pcich1intstat;
 470   uint32        pcich1intmask;
 471   uint32        pcich1descaddr;
 472   uint32        pcich1status1;
 473   uint32        pcich1status2;
 474
 475   uint32        pcich2Ctl;              /* PCI to internal system bus DMA PCI control */
 476   uint32        pcich2intstat;
 477   uint32        pcich2intmask;
 478   uint32        pcich2descaddr;
 479   uint32        pcich2status1;
 480   uint32        pcich2status2;
 481
 482   uint32        perm_id;                /* permanent device and vendor id */
 483   uint32        perm_rev;               /* permanent revision id */
 484 } MpiRegisters;
 485
 486 #define MPI ((volatile MpiRegisters * const) MPI_BASE)
 487
 488 /* PCI configuration address space start offset 0x40 */
 489 #define BRCM_PCI_CONFIG_TIMER               0x40
 490 #define BRCM_PCI_CONFIG_TIMER_RETRY_MASK        0x0000FF00
 491 #define BRCM_PCI_CONFIG_TIMER_TRDY_MASK         0x000000FF
 492
 493 /* USB host non-Open HCI register, USB_HOST_NON_OHCI, bit definitions. */
 494 #define NON_OHCI_ENABLE_PORT1   0x00000001 /* Use USB port 1 for host, not dev */
 495 #define NON_OHCI_BYTE_SWAP      0x00000008 /* Swap USB host registers */
 496
 497 #define USBH_NON_OHCI ((volatile unsigned long * const) USB_HOST_NON_OHCI)
 498
 499 #endif
 500