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don't try to create mtd partitions on bcm947xx when the trx header is not found ...
[openwrt.git] / target / linux / brcm-2.6 / patches / 004-b44_bcm47xx_support.patch
1 diff -Nur linux-2.6.17/drivers/net/b44.c linux-2.6.17-owrt/drivers/net/b44.c
2 --- linux-2.6.17/drivers/net/b44.c 2006-06-18 03:49:35.000000000 +0200
3 +++ linux-2.6.17-owrt/drivers/net/b44.c 2006-06-18 16:24:14.000000000 +0200
4 @@ -1,7 +1,9 @@
5 -/* b44.c: Broadcom 4400 device driver.
6 +/* b44.c: Broadcom 4400/47xx device driver.
7 *
8 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
9 - * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
10 + * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
11 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
12 + * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
13 * Copyright (C) 2006 Broadcom Corporation.
14 *
15 * Distribute under GPL.
16 @@ -32,6 +34,28 @@
17 #define DRV_MODULE_VERSION "1.00"
18 #define DRV_MODULE_RELDATE "Apr 7, 2006"
19
20 +#ifdef CONFIG_BCM947XX
21 +extern char *nvram_get(char *name);
22 +static inline void e_aton(char *str, char *dest)
23 +{
24 + int i = 0;
25 +
26 + if (str == NULL) {
27 + memset(dest, 0, 6);
28 + return;
29 + }
30 +
31 + for (;;) {
32 + dest[i++] = (char) simple_strtoul(str, NULL, 16);
33 + str += 2;
34 + if (!*str++ || i == 6)
35 + break;
36 + }
37 +}
38 +
39 +static int b44_4713_instance;
40 +#endif
41 +
42 #define B44_DEF_MSG_ENABLE \
43 (NETIF_MSG_DRV | \
44 NETIF_MSG_PROBE | \
45 @@ -78,8 +102,8 @@
46 static char version[] __devinitdata =
47 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
48
49 -MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
50 -MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
51 +MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
52 +MODULE_DESCRIPTION("Broadcom 4400/47xx 10/100 PCI ethernet driver");
53 MODULE_LICENSE("GPL");
54 MODULE_VERSION(DRV_MODULE_VERSION);
55
56 @@ -94,6 +118,10 @@
57 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
58 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
59 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
60 +#ifdef CONFIG_BCM947XX
61 + { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4713,
62 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
63 +#endif
64 { } /* terminate list with empty entry */
65 };
66
67 @@ -132,17 +160,6 @@
68 dma_desc_sync_size, dir);
69 }
70
71 -static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
72 -{
73 - return readl(bp->regs + reg);
74 -}
75 -
76 -static inline void bw32(const struct b44 *bp,
77 - unsigned long reg, unsigned long val)
78 -{
79 - writel(val, bp->regs + reg);
80 -}
81 -
82 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
83 u32 bit, unsigned long timeout, const int clear)
84 {
85 @@ -269,6 +286,10 @@
86 break;
87 };
88 #endif
89 +#ifdef CONFIG_BCM947XX
90 + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
91 + return b44_4713_instance++;
92 +#endif
93 return 0;
94 }
95
96 @@ -278,6 +299,30 @@
97 == SBTMSLOW_CLOCK);
98 }
99
100 +#ifdef CONFIG_BCM947XX
101 +static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
102 +{
103 + u32 val;
104 +
105 + bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
106 + (index << CAM_CTRL_INDEX_SHIFT)));
107 +
108 + b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
109 +
110 + val = br32(bp, B44_CAM_DATA_LO);
111 +
112 + data[2] = (val >> 24) & 0xFF;
113 + data[3] = (val >> 16) & 0xFF;
114 + data[4] = (val >> 8) & 0xFF;
115 + data[5] = (val >> 0) & 0xFF;
116 +
117 + val = br32(bp, B44_CAM_DATA_HI);
118 +
119 + data[0] = (val >> 8) & 0xFF;
120 + data[1] = (val >> 0) & 0xFF;
121 +}
122 +#endif
123 +
124 static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
125 {
126 u32 val;
127 @@ -314,14 +359,14 @@
128 bw32(bp, B44_IMASK, bp->imask);
129 }
130
131 -static int b44_readphy(struct b44 *bp, int reg, u32 *val)
132 +static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
133 {
134 int err;
135
136 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
137 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
138 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
139 - (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
140 + (phy_addr << MDIO_DATA_PMD_SHIFT) |
141 (reg << MDIO_DATA_RA_SHIFT) |
142 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
143 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
144 @@ -330,18 +375,34 @@
145 return err;
146 }
147
148 -static int b44_writephy(struct b44 *bp, int reg, u32 val)
149 +static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
150 {
151 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
152 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
153 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
154 - (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
155 + (phy_addr << MDIO_DATA_PMD_SHIFT) |
156 (reg << MDIO_DATA_RA_SHIFT) |
157 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
158 (val & MDIO_DATA_DATA)));
159 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
160 }
161
162 +static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
163 +{
164 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
165 + return 0;
166 +
167 + return __b44_readphy(bp, bp->phy_addr, reg, val);
168 +}
169 +
170 +static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
171 +{
172 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
173 + return 0;
174 +
175 + return __b44_writephy(bp, bp->phy_addr, reg, val);
176 +}
177 +
178 /* miilib interface */
179 /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
180 * due to code existing before miilib use was added to this driver.
181 @@ -370,6 +431,8 @@
182 u32 val;
183 int err;
184
185 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
186 + return 0;
187 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
188 if (err)
189 return err;
190 @@ -433,6 +496,22 @@
191 u32 val;
192 int err;
193
194 +#ifdef CONFIG_BCM947XX
195 + /*
196 + * workaround for bad hardware design in Linksys WAP54G v1.0
197 + * see https://dev.openwrt.org/ticket/146
198 + * check and reset bit "isolate"
199 + */
200 + if ((bp->pdev->device == PCI_DEVICE_ID_BCM4713) &&
201 + (atoi(nvram_get("boardnum")) == 2) &&
202 + (__b44_readphy(bp, 0, MII_BMCR, &val) == 0) &&
203 + (val & BMCR_ISOLATE) &&
204 + (__b44_writephy(bp, 0, MII_BMCR, val & ~BMCR_ISOLATE) != 0)) {
205 + printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n");
206 + }
207 +#endif
208 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
209 + return 0;
210 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
211 goto out;
212 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
213 @@ -528,6 +607,19 @@
214 {
215 u32 bmsr, aux;
216
217 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
218 + bp->flags |= B44_FLAG_100_BASE_T;
219 + bp->flags |= B44_FLAG_FULL_DUPLEX;
220 + if (!netif_carrier_ok(bp->dev)) {
221 + u32 val = br32(bp, B44_TX_CTRL);
222 + val |= TX_CTRL_DUPLEX;
223 + bw32(bp, B44_TX_CTRL, val);
224 + netif_carrier_on(bp->dev);
225 + b44_link_report(bp);
226 + }
227 + return;
228 + }
229 +
230 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
231 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
232 (bmsr != 0xffff)) {
233 @@ -1282,9 +1374,10 @@
234 bw32(bp, B44_DMARX_CTRL, 0);
235 bp->rx_prod = bp->rx_cons = 0;
236 } else {
237 - ssb_pci_setup(bp, (bp->core_unit == 0 ?
238 - SBINTVEC_ENET0 :
239 - SBINTVEC_ENET1));
240 + if (bp->pdev->device != PCI_DEVICE_ID_BCM4713)
241 + ssb_pci_setup(bp, (bp->core_unit == 0 ?
242 + SBINTVEC_ENET0 :
243 + SBINTVEC_ENET1));
244 }
245
246 ssb_core_reset(bp);
247 @@ -1292,8 +1385,14 @@
248 b44_clear_stats(bp);
249
250 /* Make PHY accessible. */
251 - bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
252 + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
253 + bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
254 + (((100000000 + (B44_MDC_RATIO / 2)) / B44_MDC_RATIO)
255 + & MDIO_CTRL_MAXF_MASK)));
256 + else
257 + bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
258 (0x0d & MDIO_CTRL_MAXF_MASK)));
259 +
260 br32(bp, B44_MDIO_CTRL);
261
262 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
263 @@ -1837,18 +1936,297 @@
264 .get_perm_addr = ethtool_op_get_perm_addr,
265 };
266
267 +static int b44_ethtool_ioctl (struct net_device *dev, void __user *useraddr)
268 +{
269 + struct b44 *bp = dev->priv;
270 + struct pci_dev *pci_dev = bp->pdev;
271 + u32 ethcmd;
272 +
273 + if (copy_from_user (&ethcmd, useraddr, sizeof (ethcmd)))
274 + return -EFAULT;
275 +
276 + switch (ethcmd) {
277 + case ETHTOOL_GDRVINFO: {
278 + struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
279 + strcpy (info.driver, DRV_MODULE_NAME);
280 + strcpy (info.version, DRV_MODULE_VERSION);
281 + memset(&info.fw_version, 0, sizeof(info.fw_version));
282 + strcpy (info.bus_info, pci_name(pci_dev));
283 + info.eedump_len = 0;
284 + info.regdump_len = 0;
285 + if (copy_to_user (useraddr, &info, sizeof (info)))
286 + return -EFAULT;
287 + return 0;
288 + }
289 +
290 + case ETHTOOL_GSET: {
291 + struct ethtool_cmd cmd = { ETHTOOL_GSET };
292 +
293 + if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
294 + return -EAGAIN;
295 + cmd.supported = (SUPPORTED_Autoneg);
296 + cmd.supported |= (SUPPORTED_100baseT_Half |
297 + SUPPORTED_100baseT_Full |
298 + SUPPORTED_10baseT_Half |
299 + SUPPORTED_10baseT_Full |
300 + SUPPORTED_MII);
301 +
302 + cmd.advertising = 0;
303 + if (bp->flags & B44_FLAG_ADV_10HALF)
304 + cmd.advertising |= ADVERTISE_10HALF;
305 + if (bp->flags & B44_FLAG_ADV_10FULL)
306 + cmd.advertising |= ADVERTISE_10FULL;
307 + if (bp->flags & B44_FLAG_ADV_100HALF)
308 + cmd.advertising |= ADVERTISE_100HALF;
309 + if (bp->flags & B44_FLAG_ADV_100FULL)
310 + cmd.advertising |= ADVERTISE_100FULL;
311 + cmd.advertising |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
312 + cmd.speed = (bp->flags & B44_FLAG_100_BASE_T) ?
313 + SPEED_100 : SPEED_10;
314 + cmd.duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
315 + DUPLEX_FULL : DUPLEX_HALF;
316 + cmd.port = 0;
317 + cmd.phy_address = bp->phy_addr;
318 + cmd.transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
319 + XCVR_INTERNAL : XCVR_EXTERNAL;
320 + cmd.autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
321 + AUTONEG_DISABLE : AUTONEG_ENABLE;
322 + cmd.maxtxpkt = 0;
323 + cmd.maxrxpkt = 0;
324 + if (copy_to_user(useraddr, &cmd, sizeof(cmd)))
325 + return -EFAULT;
326 + return 0;
327 + }
328 + case ETHTOOL_SSET: {
329 + struct ethtool_cmd cmd;
330 +
331 + if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
332 + return -EAGAIN;
333 +
334 + if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
335 + return -EFAULT;
336 +
337 + /* We do not support gigabit. */
338 + if (cmd.autoneg == AUTONEG_ENABLE) {
339 + if (cmd.advertising &
340 + (ADVERTISED_1000baseT_Half |
341 + ADVERTISED_1000baseT_Full))
342 + return -EINVAL;
343 + } else if ((cmd.speed != SPEED_100 &&
344 + cmd.speed != SPEED_10) ||
345 + (cmd.duplex != DUPLEX_HALF &&
346 + cmd.duplex != DUPLEX_FULL)) {
347 + return -EINVAL;
348 + }
349 +
350 + spin_lock_irq(&bp->lock);
351 +
352 + if (cmd.autoneg == AUTONEG_ENABLE) {
353 + bp->flags &= ~B44_FLAG_FORCE_LINK;
354 + bp->flags &= ~(B44_FLAG_ADV_10HALF |
355 + B44_FLAG_ADV_10FULL |
356 + B44_FLAG_ADV_100HALF |
357 + B44_FLAG_ADV_100FULL);
358 + if (cmd.advertising & ADVERTISE_10HALF)
359 + bp->flags |= B44_FLAG_ADV_10HALF;
360 + if (cmd.advertising & ADVERTISE_10FULL)
361 + bp->flags |= B44_FLAG_ADV_10FULL;
362 + if (cmd.advertising & ADVERTISE_100HALF)
363 + bp->flags |= B44_FLAG_ADV_100HALF;
364 + if (cmd.advertising & ADVERTISE_100FULL)
365 + bp->flags |= B44_FLAG_ADV_100FULL;
366 + } else {
367 + bp->flags |= B44_FLAG_FORCE_LINK;
368 + if (cmd.speed == SPEED_100)
369 + bp->flags |= B44_FLAG_100_BASE_T;
370 + if (cmd.duplex == DUPLEX_FULL)
371 + bp->flags |= B44_FLAG_FULL_DUPLEX;
372 + }
373 +
374 + b44_setup_phy(bp);
375 +
376 + spin_unlock_irq(&bp->lock);
377 +
378 + return 0;
379 + }
380 +
381 + case ETHTOOL_GMSGLVL: {
382 + struct ethtool_value edata = { ETHTOOL_GMSGLVL };
383 + edata.data = bp->msg_enable;
384 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
385 + return -EFAULT;
386 + return 0;
387 + }
388 + case ETHTOOL_SMSGLVL: {
389 + struct ethtool_value edata;
390 + if (copy_from_user(&edata, useraddr, sizeof(edata)))
391 + return -EFAULT;
392 + bp->msg_enable = edata.data;
393 + return 0;
394 + }
395 + case ETHTOOL_NWAY_RST: {
396 + u32 bmcr;
397 + int r;
398 +
399 + spin_lock_irq(&bp->lock);
400 + b44_readphy(bp, MII_BMCR, &bmcr);
401 + b44_readphy(bp, MII_BMCR, &bmcr);
402 + r = -EINVAL;
403 + if (bmcr & BMCR_ANENABLE) {
404 + b44_writephy(bp, MII_BMCR,
405 + bmcr | BMCR_ANRESTART);
406 + r = 0;
407 + }
408 + spin_unlock_irq(&bp->lock);
409 +
410 + return r;
411 + }
412 + case ETHTOOL_GLINK: {
413 + struct ethtool_value edata = { ETHTOOL_GLINK };
414 + edata.data = netif_carrier_ok(bp->dev) ? 1 : 0;
415 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
416 + return -EFAULT;
417 + return 0;
418 + }
419 + case ETHTOOL_GRINGPARAM: {
420 + struct ethtool_ringparam ering = { ETHTOOL_GRINGPARAM };
421 +
422 + ering.rx_max_pending = B44_RX_RING_SIZE - 1;
423 + ering.rx_pending = bp->rx_pending;
424 +
425 + /* XXX ethtool lacks a tx_max_pending, oops... */
426 +
427 + if (copy_to_user(useraddr, &ering, sizeof(ering)))
428 + return -EFAULT;
429 + return 0;
430 + }
431 + case ETHTOOL_SRINGPARAM: {
432 + struct ethtool_ringparam ering;
433 +
434 + if (copy_from_user(&ering, useraddr, sizeof(ering)))
435 + return -EFAULT;
436 +
437 + if ((ering.rx_pending > B44_RX_RING_SIZE - 1) ||
438 + (ering.rx_mini_pending != 0) ||
439 + (ering.rx_jumbo_pending != 0) ||
440 + (ering.tx_pending > B44_TX_RING_SIZE - 1))
441 + return -EINVAL;
442 +
443 + spin_lock_irq(&bp->lock);
444 +
445 + bp->rx_pending = ering.rx_pending;
446 + bp->tx_pending = ering.tx_pending;
447 +
448 + b44_halt(bp);
449 + b44_init_rings(bp);
450 + b44_init_hw(bp);
451 + netif_wake_queue(bp->dev);
452 + spin_unlock_irq(&bp->lock);
453 +
454 + b44_enable_ints(bp);
455 +
456 + return 0;
457 + }
458 + case ETHTOOL_GPAUSEPARAM: {
459 + struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM };
460 +
461 + epause.autoneg =
462 + (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
463 + epause.rx_pause =
464 + (bp->flags & B44_FLAG_RX_PAUSE) != 0;
465 + epause.tx_pause =
466 + (bp->flags & B44_FLAG_TX_PAUSE) != 0;
467 + if (copy_to_user(useraddr, &epause, sizeof(epause)))
468 + return -EFAULT;
469 + return 0;
470 + }
471 + case ETHTOOL_SPAUSEPARAM: {
472 + struct ethtool_pauseparam epause;
473 +
474 + if (copy_from_user(&epause, useraddr, sizeof(epause)))
475 + return -EFAULT;
476 +
477 + spin_lock_irq(&bp->lock);
478 + if (epause.autoneg)
479 + bp->flags |= B44_FLAG_PAUSE_AUTO;
480 + else
481 + bp->flags &= ~B44_FLAG_PAUSE_AUTO;
482 + if (epause.rx_pause)
483 + bp->flags |= B44_FLAG_RX_PAUSE;
484 + else
485 + bp->flags &= ~B44_FLAG_RX_PAUSE;
486 + if (epause.tx_pause)
487 + bp->flags |= B44_FLAG_TX_PAUSE;
488 + else
489 + bp->flags &= ~B44_FLAG_TX_PAUSE;
490 + if (bp->flags & B44_FLAG_PAUSE_AUTO) {
491 + b44_halt(bp);
492 + b44_init_rings(bp);
493 + b44_init_hw(bp);
494 + } else {
495 + __b44_set_flow_ctrl(bp, bp->flags);
496 + }
497 + spin_unlock_irq(&bp->lock);
498 +
499 + b44_enable_ints(bp);
500 +
501 + return 0;
502 + }
503 + };
504 +
505 + return -EOPNOTSUPP;
506 +}
507 +
508 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
509 {
510 struct mii_ioctl_data *data = if_mii(ifr);
511 struct b44 *bp = netdev_priv(dev);
512 int err = -EINVAL;
513
514 - if (!netif_running(dev))
515 + if (bp->pdev->device != PCI_DEVICE_ID_BCM4713) {
516 + if (!netif_running(dev))
517 + goto out;
518 +
519 + spin_lock_irq(&bp->lock);
520 + err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
521 + spin_unlock_irq(&bp->lock);
522 goto out;
523 + }
524
525 - spin_lock_irq(&bp->lock);
526 - err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
527 - spin_unlock_irq(&bp->lock);
528 + switch (cmd) {
529 + case SIOCETHTOOL:
530 + return b44_ethtool_ioctl(dev, (void __user*) ifr->ifr_data);
531 +
532 + case SIOCGMIIPHY:
533 + data->phy_id = bp->phy_addr;
534 +
535 + /* fallthru */
536 + case SIOCGMIIREG: {
537 + u32 mii_regval;
538 + spin_lock_irq(&bp->lock);
539 + err = __b44_readphy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
540 + spin_unlock_irq(&bp->lock);
541 +
542 + data->val_out = mii_regval;
543 +
544 + return err;
545 + }
546 +
547 + case SIOCSMIIREG:
548 + if (!capable(CAP_NET_ADMIN))
549 + return -EPERM;
550 +
551 + spin_lock_irq(&bp->lock);
552 + err = __b44_writephy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
553 + spin_unlock_irq(&bp->lock);
554 +
555 + return err;
556 +
557 + default:
558 + break;
559 + };
560 + return -EOPNOTSUPP;
561 +
562 out:
563 return err;
564 }
565 @@ -1868,27 +2246,60 @@
566 static int __devinit b44_get_invariants(struct b44 *bp)
567 {
568 u8 eeprom[128];
569 - int err;
570 + u8 buf[32];
571 + int err = 0;
572 + unsigned long flags;
573 +
574 +#ifdef CONFIG_BCM947XX
575 + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) {
576 + /*
577 + * BCM47xx boards don't have a EEPROM. The MAC is stored in
578 + * a NVRAM area somewhere in the flash memory.
579 + */
580 + sprintf(buf, "et%dmacaddr", b44_4713_instance);
581 + if (nvram_get(buf)) {
582 + e_aton(nvram_get(buf), bp->dev->dev_addr);
583 + } else {
584 + /*
585 + * Getting the MAC out of NVRAM failed. To make it work
586 + * here, we simply rely on the bootloader to write the
587 + * MAC into the CAM.
588 + */
589 + spin_lock_irqsave(&bp->lock, flags);
590 + __b44_cam_read(bp, bp->dev->dev_addr, 0);
591 + spin_unlock_irqrestore(&bp->lock, flags);
592 + }
593
594 - err = b44_read_eeprom(bp, &eeprom[0]);
595 - if (err)
596 - goto out;
597 + /*
598 + * BCM47xx boards don't have a PHY. Usually there is a switch
599 + * chip with multiple PHYs connected to the PHY port.
600 + */
601 + bp->phy_addr = B44_PHY_ADDR_NO_PHY;
602 + bp->dma_offset = 0;
603 + } else
604 +#endif
605 + {
606 + err = b44_read_eeprom(bp, &eeprom[0]);
607 + if (err)
608 + goto out;
609
610 - bp->dev->dev_addr[0] = eeprom[79];
611 - bp->dev->dev_addr[1] = eeprom[78];
612 - bp->dev->dev_addr[2] = eeprom[81];
613 - bp->dev->dev_addr[3] = eeprom[80];
614 - bp->dev->dev_addr[4] = eeprom[83];
615 - bp->dev->dev_addr[5] = eeprom[82];
616 + bp->dev->dev_addr[0] = eeprom[79];
617 + bp->dev->dev_addr[1] = eeprom[78];
618 + bp->dev->dev_addr[2] = eeprom[81];
619 + bp->dev->dev_addr[3] = eeprom[80];
620 + bp->dev->dev_addr[4] = eeprom[83];
621 + bp->dev->dev_addr[5] = eeprom[82];
622
623 - if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
624 - printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
625 - return -EINVAL;
626 - }
627 + if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
628 + printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
629 + return -EINVAL;
630 + }
631
632 - memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
633 + memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
634
635 - bp->phy_addr = eeprom[90] & 0x1f;
636 + bp->phy_addr = eeprom[90] & 0x1f;
637 + bp->dma_offset = SB_PCI_DMA;
638 + }
639
640 /* With this, plus the rx_header prepended to the data by the
641 * hardware, we'll land the ethernet header on a 2-byte boundary.
642 @@ -1898,7 +2309,6 @@
643 bp->imask = IMASK_DEF;
644
645 bp->core_unit = ssb_core_unit(bp);
646 - bp->dma_offset = SB_PCI_DMA;
647
648 /* XXX - really required?
649 bp->flags |= B44_FLAG_BUGGY_TXPTR;
650 @@ -2048,11 +2458,17 @@
651 */
652 b44_chip_reset(bp);
653
654 - printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
655 + printk(KERN_INFO "%s: Broadcom %s 10/100BaseT Ethernet ", dev->name,
656 + (pdev->device == PCI_DEVICE_ID_BCM4713) ? "47xx" : "4400");
657 for (i = 0; i < 6; i++)
658 printk("%2.2x%c", dev->dev_addr[i],
659 i == 5 ? '\n' : ':');
660
661 + /* Initialize phy */
662 + spin_lock_irq(&bp->lock);
663 + b44_chip_reset(bp);
664 + spin_unlock_irq(&bp->lock);
665 +
666 return 0;
667
668 err_out_iounmap:
669 diff -Nur linux-2.6.17/drivers/net/b44.h linux-2.6.17-owrt/drivers/net/b44.h
670 --- linux-2.6.17/drivers/net/b44.h 2006-06-18 03:49:35.000000000 +0200
671 +++ linux-2.6.17-owrt/drivers/net/b44.h 2006-06-18 16:01:10.000000000 +0200
672 @@ -292,6 +292,10 @@
673 #define SSB_PCI_MASK1 0xfc000000
674 #define SSB_PCI_MASK2 0xc0000000
675
676 +#define br32(bp, REG) readl((void *)bp->regs + (REG))
677 +#define bw32(bp, REG,VAL) writel((VAL), (void *)bp->regs + (REG))
678 +#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
679 +
680 /* 4400 PHY registers */
681 #define B44_MII_AUXCTRL 24 /* Auxiliary Control */
682 #define MII_AUXCTRL_DUPLEX 0x0001 /* Full Duplex */
683 @@ -345,6 +349,8 @@
684 };
685
686 #define B44_MCAST_TABLE_SIZE 32
687 +#define B44_PHY_ADDR_NO_PHY 30
688 +#define B44_MDC_RATIO 5000000
689
690 #define B44_STAT_REG_DECLARE \
691 _B44(tx_good_octets) \
692 @@ -420,6 +426,7 @@
693
694 u32 dma_offset;
695 u32 flags;
696 +#define B44_FLAG_INIT_COMPLETE 0x00000001
697 #define B44_FLAG_BUGGY_TXPTR 0x00000002
698 #define B44_FLAG_REORDER_BUG 0x00000004
699 #define B44_FLAG_PAUSE_AUTO 0x00008000
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