make use of the adm6996 switch for atheros devices that support it (autodetected...
[openwrt.git] / target / linux / brcm47xx / patches-2.6.23 / 130-remove_scache.patch
1 Index: linux-2.6.23/arch/mips/Kconfig
2 ===================================================================
3 --- linux-2.6.23.orig/arch/mips/Kconfig 2007-10-13 02:23:41.484492317 +0200
4 +++ linux-2.6.23/arch/mips/Kconfig 2007-10-13 02:47:02.784347843 +0200
5 @@ -192,7 +192,6 @@
6 select I8259
7 select MIPS_BOARDS_GEN
8 select MIPS_BONITO64
9 - select MIPS_CPU_SCACHE
10 select PCI_GT64XXX_PCI0
11 select MIPS_MSC
12 select SWAP_IO_SPACE
13 @@ -1281,13 +1280,6 @@
14 bool
15 select BOARD_SCACHE
16
17 -#
18 -# Support for a MIPS32 / MIPS64 style S-caches
19 -#
20 -config MIPS_CPU_SCACHE
21 - bool
22 - select BOARD_SCACHE
23 -
24 config R5000_CPU_SCACHE
25 bool
26 select BOARD_SCACHE
27 Index: linux-2.6.23/arch/mips/kernel/cpu-probe.c
28 ===================================================================
29 --- linux-2.6.23.orig/arch/mips/kernel/cpu-probe.c 2007-10-13 02:23:11.210767122 +0200
30 +++ linux-2.6.23/arch/mips/kernel/cpu-probe.c 2007-10-13 02:47:02.788348072 +0200
31 @@ -701,6 +701,8 @@
32 break;
33 case PRID_IMP_25KF:
34 c->cputype = CPU_25KF;
35 + /* Probe for L2 cache */
36 + c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
37 break;
38 case PRID_IMP_34K:
39 c->cputype = CPU_34K;
40 Index: linux-2.6.23/arch/mips/mm/c-r4k.c
41 ===================================================================
42 --- linux-2.6.23.orig/arch/mips/mm/c-r4k.c 2007-10-09 22:31:38.000000000 +0200
43 +++ linux-2.6.23/arch/mips/mm/c-r4k.c 2007-10-13 02:47:02.792348301 +0200
44 @@ -1086,7 +1086,6 @@
45
46 extern int r5k_sc_init(void);
47 extern int rm7k_sc_init(void);
48 -extern int mips_sc_init(void);
49
50 static void __init setup_scache(void)
51 {
52 @@ -1140,29 +1139,17 @@
53 #endif
54
55 default:
56 - if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
57 - c->isa_level == MIPS_CPU_ISA_M32R2 ||
58 - c->isa_level == MIPS_CPU_ISA_M64R1 ||
59 - c->isa_level == MIPS_CPU_ISA_M64R2) {
60 -#ifdef CONFIG_MIPS_CPU_SCACHE
61 - if (mips_sc_init ()) {
62 - scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
63 - printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
64 - scache_size >> 10,
65 - way_string[c->scache.ways], c->scache.linesz);
66 - }
67 -#else
68 - if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
69 - panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
70 -#endif
71 - return;
72 - }
73 sc_present = 0;
74 }
75
76 if (!sc_present)
77 return;
78
79 + if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
80 + c->isa_level == MIPS_CPU_ISA_M64R1) &&
81 + !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
82 + panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
83 +
84 /* compute a couple of other cache variables */
85 c->scache.waysize = scache_size / c->scache.ways;
86
87 Index: linux-2.6.23/arch/mips/mm/Makefile
88 ===================================================================
89 --- linux-2.6.23.orig/arch/mips/mm/Makefile 2007-10-09 22:31:38.000000000 +0200
90 +++ linux-2.6.23/arch/mips/mm/Makefile 2007-10-13 02:47:23.393522295 +0200
91 @@ -31,6 +31,5 @@
92 obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
93 obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
94 obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o
95 -obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o
96
97 EXTRA_CFLAGS += -Werror
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