projects / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
some additions to the ar7 system code, added cpmac network driver
[openwrt.git] / target / linux / linux-2.4 / patches / ar7 / 002-net_driver_cpmac.patch
1 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpcommon_cpmac.c linux-2.4.30/drivers/net/avalanche_cpmac/cpcommon_cpmac.c
2 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpcommon_cpmac.c 1970-01-01 02:00:00.000000000 +0200
3 +++ linux-2.4.30/drivers/net/avalanche_cpmac/cpcommon_cpmac.c 2005-04-15 05:10:40.000000000 +0200
4 @@ -0,0 +1,728 @@
5 +#ifndef _INC_CPCOMMON_C
6 +#define _INC_CPCOMMON_C
7 +
8 +#ifdef _CPHAL_CPMAC
9 +#include "cpremap_cpmac.c"
10 +#endif
11 +
12 +#ifdef _CPHAL_AAL5
13 +#include "cpremap_cpaal5.c"
14 +#endif
15 +
16 +#ifdef _CPHAL_CPSAR
17 +#include "cpremap_cpsar.c"
18 +#endif
19 +
20 +#ifdef _CPHAL_AAL2
21 +#include "cpremap_cpaal2.c"
22 +#endif
23 +
24 +/**
25 +@defgroup Common_Config_Params Common Configuration Parameters
26 +
27 +This section documents the configuration parameters that are valid across
28 +all CPHAL devices.
29 +@{
30 +*/
31 +/** This is the debug level. The field is bit defined, such that the user
32 +should set to 1 all the bits corresponding to desired debug outputs. The following
33 +are the meanings for each debug bit:
34 +- bit0 (LSB): CPHAL Function Trace
35 +- b1 : OS Function call trace
36 +- b2 : Critical section entry/exit
37 +- b3 : Memory allocation/destruction
38 +- b4 : Detailed information in Rx path
39 +- b5 : Detailed information in Tx path
40 +- b6 : Extended error information
41 +- b7 : General info
42 +*/
43 +static const char pszDebug[] = "debug";
44 +/** CPU Frequency. */
45 +/*static const char pszCpuFreq[] = "CpuFreq";*/ /*MJH-030403*/
46 +/** Base address for the module. */
47 +static const char pszBase[] = "base";
48 +/** Reset bit for the module. */
49 +static const char pszResetBit[] = "reset_bit";
50 +/** Reset base address for the module. */
51 +static const char pszResetBase[] = "ResetBase";
52 +/** Interrupt line for the module. */
53 +static const char pszIntLine[] = "int_line";
54 +/** VLYNQ offset for the module. Disregard if not using VLYNQ. */
55 +static const char pszOffset[] = "offset";
56 +/** The OS may "Get" this parameter, which is a pointer
57 + to a character string that indicates the version of CPHAL. */
58 +static const char pszVer[] = "Version";
59 +/*@}*/
60 +
61 +/**
62 +@defgroup Common_Control_Params Common Keys for [os]Control()
63 +
64 +This section documents the keys used with the OS @c Control() interface that
65 +are required by CPHAL devices.
66 +
67 +@{
68 +*/
69 +/** Used to wait for an integer number of clock ticks, given as an integer
70 + pointer in the @p Value parameter. No actions are defined. */
71 +static const char pszSleep[] = "Sleep";
72 +/** Requests the OS to flush it's IO buffers. No actions are defined. */
73 +static const char pszSioFlush[] = "SioFlush";
74 +/*@}*/
75 +
76 +static const char pszStateChange[] = "StateChange";
77 +static const char pszStatus[] = "Status";
78 +
79 +static const char pszGET[] = "Get";
80 +static const char pszSET[] = "Set";
81 +static const char pszCLEAR[] = "Clear";
82 +static const char pszNULL[] = "";
83 +static const char pszLocator[] = "Locator";
84 +static const char pszOff[] = "Off";
85 +static const char pszOn[] = "On";
86 +static const char hcMaxFrags[] = "MaxFrags";
87 +
88 +#ifdef _CPHAL_CPMAC
89 +
90 +/* New method for string constants */
91 +const char hcClear[] = "Clear";
92 +const char hcGet[] = "Get";
93 +const char hcSet[] = "Set";
94 +
95 +const char hcTick[] = "Tick";
96 +
97 +static const CONTROL_KEY KeyCommon[] =
98 + {
99 + {"" , enCommonStart},
100 + {pszStatus , enStatus},
101 + {pszOff , enOff},
102 + {pszOn , enOn},
103 + {pszDebug , enDebug},
104 + {hcCpuFrequency , enCpuFreq}, /*MJH~030403*/
105 + {"" , enCommonEnd}
106 + };
107 +#endif
108 +
109 +/**
110 +@defgroup Common_Statistics Statistics
111 +
112 +A broad array of module statistics is available. Statistics values are accessed
113 +through the @c Control() interface of the CPHAL. There are 5 different levels
114 +of statistics, each of which correspond to a unique set of data. Furthermore,
115 +certain statistics data is indexed by using a channel number and Tx queue number.
116 +The following is a brief description of each statistics level, along with the
117 +indexes used for the level:
118 +
119 +- Level 0: Hardware Statistics (index with channel)
120 +- Level 1: CPHAL Software Statistics (channel, queue)
121 +- Level 2: CPHAL Flags (channel, queue)
122 +- Level 3: CPHAL Channel Configuration (channel)
123 +- Level 4: CPHAL General Configuration (no index)
124 +
125 +The caller requests statistics information by providing a Key string to the
126 +@c Control() API in the following format: "Stats;[Level #];[Ch #];[Queue #]".
127 +The only valid Action parameter for statistics usage is "Get".
128 +
129 +Code Examples:
130 +@code
131 +unsigned int *StatsData;
132 +
133 +# Get Level 0 stats for Channel 1
134 +HalFunc->Control(OsDev->HalDev, "Stats;0;1", "Get", &StatsData);
135 +
136 +# Get Level 2 stats for Channel 0, Queue 0
137 +HalFunc->Control(OsDev->HalDev, "Stats;2;0;0", "Get", &StatsData);
138 +
139 +# Get Level 4 stats
140 +HalFunc->Control(OsDev->HalDev, "Stats;4", "Get", &StatsData);
141 +@endcode
142 +
143 +The information returned in the Value parameter of @c Control() is an
144 +array of pointers to strings. The pointers are arranged in pairs.
145 +The first pointer is a pointer to a name string for a particular statistic.
146 +The next pointer is a pointer to a string containing the representation of
147 +the integer statistic value corresponding to the first pointer. This is followed
148 +by another pair of pointers, and so on, until a NULL pointer is encountered. The
149 +following is example code for processing the statistics data. Note that the OS
150 +is responsible for freeing the memory passed back through the Value parameter of
151 +@c Control().
152 +
153 +@code
154 +unsigned int *StatsData;
155 +
156 +# Get Level 0 stats for Channel 1
157 +HalFunc->Control(OsDev->HalDev, "Stats;0;1", "Get", &StatsData);
158 +
159 +# output Statistics data
160 +PrintStats(StatsData);
161 +
162 +# the upper layer is responsible for freeing stats info
163 +free(&StatsPtr);
164 +
165 +...
166 +
167 +void PrintStats(unsigned int *StatsPtr)
168 + {
169 + while(*StatsPtr)
170 + {
171 + printf("%20s:", (char *)*StatsPtr);
172 + StatsPtr++;
173 + printf("%11s\n", (char *)*StatsPtr);
174 + StatsPtr++;
175 + }
176 + MySioFlush();
177 + }
178 +@endcode
179 +
180 +Within each statistics level, there are several statistics defined. The statistics that
181 +are common to every CPPI module are listed below. In addition, each module may define
182 +extra statistics in each level, which will be documented within the module-specific
183 +documentation appendices.
184 +
185 +- Level 0 Statistics
186 + - All level 0 statistics are module-specific.
187 +- Level 1 Statistics (CPHAL Software Statistics)
188 + - DmaLenErrors: Incremented when the port DMA's more data than expected (per channel). (AAL5 Only)
189 + - TxMisQCnt: Incremented when host queues a packet for transmission as the port finishes
190 +transmitting the previous last packet in the queue (per channel and queue).
191 + - RxMisQCnt: Incremented when host queues adds buffers to a queue as the port finished the
192 +reception of the previous last packet in the queue (per channel).
193 + - TxEOQCnt: Number of times the port has reached the end of the transmit queue (per channel and queue).
194 + - RxEOQCnt: Number of times the port has reached the end of the receive queue (per channel).
195 + - RxPacketsServiced: Number of received packets (per channel).
196 + - TxPacketsServiced: Number of transmitted packets (per channel and queue).
197 + - RxMaxServiced: Maximum number of packets that the CPHAL receive interrupt has serviced at a time (per channel).
198 + - TxMaxServiced: Maximum number of packets that the CPHAL transmit interrupt has serviced at a time (per channel and queue).
199 + - RxTotal: Total number of received packets, all channels.
200 + - TxTotal: Total number of transmitted packets, all channels and queues.
201 +- Level 2 Statistics (CPHAL Flags)
202 + - RcbPool: Pointer to receive descriptor pool (per channel).
203 + - RxActQueueCount: Number of buffers currently available for receive (per channel).
204 + - RxActQueueHead: Pointer to first buffer in receive queue (per channel).
205 + - RxActQueueTail: Pointer to last buffer in receive queue (per channel).
206 + - RxActive: 0 if inactive (no buffers available), or 1 if active (buffers available).
207 + - RcbStart: Pointer to block of receive descriptors.
208 + - RxTeardownPending: 1 if Rx teardown is pending but incomplete, 0 otherwise.
209 + - TcbPool: Pointer to transmit descriptor pool (per channel and queue).
210 + - TxActQueueCount: Number of buffers currently queued to be transmitted (per channel and queue).
211 + - TxActQueueHead: Pointer to first buffer in transmit queue (per channel and queue).
212 + - TxActQueueTail: Pointer to last buffer in transmit queue (per channel and queue).
213 + - TxActive: 0 if inactive (no buffers to send), or 1 if active (buffers queued to send).
214 + - TcbStart: Pointer to block of transmit descriptors.
215 + - TxTeardownPending: 1 if Tx teardown is pending but incomplete, 0 otherwise.
216 +- Level 3 Statistics (CPHAL Channel Configuration)
217 + - RxBufSize: Rx buffer size.
218 + - RxBufferOffset: Rx buffer offset.
219 + - RxNumBuffers: Number of Rx buffers.
220 + - RxServiceMax: Maximum number of receive packets to service at a time.
221 + - TxNumBuffers: Number of Tx buffer descriptors.
222 + - TxNumQueues: Number of Tx queues to use.
223 + - TxServiceMax: Maximum number of transmit packets to service at a time.
224 +- Level 4 Statistics (CPHAL General Configuration)
225 + - Base Address: Base address of the module.
226 + - Offset (VLYNQ): VLYNQ relative module offset.
227 + - Interrupt Line: Interrupt number.
228 + - Debug: Debug flag, 1 to enable debug.
229 + - Inst: Instance number.
230 +*/
231 +
232 +/*
233 + Data Type 0 = int display
234 + Data Type 1 = hex display
235 + Data Type 2 = channel structure, int display
236 + Data Type 3 = queue index and int display
237 + Data Type 4 = queue index and hex display
238 +*/
239 +#if (defined(_CPHAL_AAL5) || defined(_CPHAL_CPMAC)) /* +GSG 030307 */
240 +static STATS_TABLE StatsTable0[] =
241 + {
242 +#ifdef _CPHAL_AAL5
243 + /* Name , Data Ptr, Data Type */
244 + {"Crc Errors", 0, 0},
245 + {"Len Errors", 0, 0},
246 + {"Abort Errors", 0, 0},
247 + {"Starv Errors", 0, 0}
248 +#endif
249 +#ifdef _CPHAL_CPMAC
250 + {"Rx Good Frames", 0, 0}
251 +#endif
252 + };
253 +
254 +static STATS_TABLE StatsTable1[] =
255 + {
256 + /* Name , Data Ptr, Data Type */
257 + {"DmaLenErrors", 0, 0},
258 + {"TxMisQCnt", 0, 3},
259 + {"RxMisQCnt", 0, 0},
260 + {"TxEOQCnt", 0, 3},
261 + {"RxEOQCnt", 0, 0},
262 + {"RxPacketsServiced", 0, 0},
263 + {"TxPacketsServiced", 0, 3},
264 + {"RxMaxServiced", 0, 0},
265 + {"TxMaxServiced", 0, 3},
266 + {"RxTotal", 0, 0},
267 + {"TxTotal", 0, 0},
268 + };
269 +
270 +static STATS_TABLE StatsTable2[] =
271 + {
272 + /* Name , Data Ptr, Data Type */
273 + {"RcbPool", 0, 1},
274 + {"RxActQueueCount", 0, 0},
275 + {"RxActQueueHead", 0, 1},
276 + {"RxActQueueTail", 0, 1},
277 + {"RxActive", 0, 0},
278 + {"RcbStart", 0, 1},
279 + {"RxTeardownPending", 0, 0},
280 + {"TcbPool", 0, 4},
281 + {"TxActQueueCount", 0, 3},
282 + {"TxActQueueHead", 0, 4},
283 + {"TxActQueueTail", 0, 4},
284 + {"TxActive", 0, 3},
285 + {"TcbStart", 0, 4},
286 + {"TxTeardownPending", 0, 0}
287 + };
288 +
289 +static STATS_TABLE StatsTable3[] =
290 + {
291 + /* Name , Data Ptr, Data Type */
292 + {"RxBufSize", 0, 2},
293 + {"RxBufferOffset", 0, 2},
294 + {"RxNumBuffers", 0, 2},
295 + {"RxServiceMax", 0, 2},
296 + {"TxNumBuffers", 0, 2},
297 + {"TxNumQueues", 0, 2},
298 + {"TxServiceMax", 0, 2},
299 +#ifdef _CPHAL_AAL5
300 + {"CpcsUU", 0, 2},
301 + {"Gfc", 0, 2},
302 + {"Clp", 0, 2},
303 + {"Pti", 0, 2},
304 + {"DaMask", 0, 2},
305 + {"Priority", 0, 2},
306 + {"PktType", 0, 2},
307 + {"Vci", 0, 2},
308 + {"Vpi", 0, 2},
309 + {"CellRate", 0, 2},
310 + {"QosType", 0, 2},
311 + {"Mbs", 0, 2},
312 + {"Pcr", 0, 2}
313 +#endif
314 + };
315 +
316 +static STATS_TABLE StatsTable4[] =
317 + {
318 + {"Base Address", 0, 1},
319 + {"Offset (VLYNQ)", 0, 0},
320 + {"Interrupt Line", 0, 0},
321 + {"Debug", 0, 0},
322 + {"Instance", 0, 0},
323 +#ifdef _CPHAL_AAL5
324 + {"UniNni", 0, 0}
325 +#endif
326 + };
327 +
328 +static STATS_DB StatsDb[] =
329 + {
330 + {(sizeof(StatsTable0)/sizeof(STATS_TABLE)), StatsTable0},
331 + {(sizeof(StatsTable1)/sizeof(STATS_TABLE)), StatsTable1},
332 + {(sizeof(StatsTable2)/sizeof(STATS_TABLE)), StatsTable2},
333 + {(sizeof(StatsTable3)/sizeof(STATS_TABLE)), StatsTable3},
334 + {(sizeof(StatsTable4)/sizeof(STATS_TABLE)), StatsTable4}
335 + };
336 +#endif /* +GSG 030307 */
337 +
338 +#ifdef _CPHAL_CPMAC /* +RC 3.02 */
339 +static void resetWait(HAL_DEVICE *HalDev)
340 + { /*+RC3.02*/
341 + const int TickReset=64;
342 + osfuncSleep((int*)&TickReset);
343 + } /*+RC3.02*/
344 +#endif /* +RC 3.02 */
345 +
346 +/* I only define the reset base function for the modules
347 + that can perform a reset. The AAL5 and AAL2 modules
348 + do not perform a reset, that is done by the shared module
349 + CPSAR */
350 +#if defined(_CPHAL_CPSAR) || defined(_CPHAL_CPMAC) || defined(_CPHAL_VDMAVT)
351 +/*
352 + * Determines the reset register address to be used for a particular device.
353 + * It will search the current device entry for Locator information. If the
354 + * device is a root device, there will be no Locator information, and the
355 + * function will find and return the root reset register. If a Locator value
356 + * is found, the function will search each VLYNQ device entry in the system
357 + * looking for a matching Locator. Once it finds a VLYNQ device entry with
358 + * a matching Locator, it will extract the "ResetBase" parameter from that
359 + * VLYNQ device entry (thus every VLYNQ entry must have the ResetBase parameter).
360 + *
361 + * @param HalDev CPHAL module instance. (set by xxxInitModule())
362 + * @param ResetBase Pointer to integer address of reset register.
363 + *
364 + * @return 0 OK, Non-zero not OK
365 + */
366 +static int ResetBaseGet(HAL_DEVICE *HalDev, bit32u *ResetBase)
367 + {
368 + char *DeviceInfo = HalDev->DeviceInfo;
369 + char *MyLocator, *NextLocator;
370 + int Inst=1;
371 + bit32u error_code;
372 +
373 +#ifdef __CPHAL_DEBUG
374 + if (DBG(0))
375 + {
376 + dbgPrintf("[cpcommon]ResetBaseGet(HalDev:%08x, ResetBase:%08x)\n", (bit32u)HalDev, ResetBase);
377 + osfuncSioFlush();
378 + }
379 +#endif
380 +
381 + error_code = HalDev->OsFunc->DeviceFindParmValue(DeviceInfo, "Locator", &MyLocator);
382 + if (error_code)
383 + {
384 + /* if no Locator value, device is on the root, so get the "reset" device */
385 + error_code = HalDev->OsFunc->DeviceFindInfo(0, "reset", &DeviceInfo);
386 + if (error_code)
387 + {
388 + return(EC_VAL_DEVICE_NOT_FOUND);
389 + }
390 +
391 + error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, "base", ResetBase);
392 + if (error_code)
393 + {
394 + return(EC_VAL_BASE_ADDR_NOT_FOUND);
395 + }
396 +
397 + *ResetBase = ((bit32u)PhysToVirtNoCache(*ResetBase));
398 +
399 + /* found base address for root device, so we're done */
400 + return (EC_NO_ERRORS);
401 + }
402 + else
403 + {
404 + /* we have a Locator value, so the device is remote */
405 +
406 + /* Find a vlynq device with a matching locator value */
407 + while ((HalDev->OsFunc->DeviceFindInfo(Inst, "vlynq", &DeviceInfo)) == EC_NO_ERRORS)
408 + {
409 + error_code = HalDev->OsFunc->DeviceFindParmValue(DeviceInfo, "Locator", &NextLocator);
410 + if (error_code)
411 + {
412 + /* no Locator value for this VLYNQ, so move on */
413 + continue;
414 + }
415 + if (HalDev->OsFunc->Strcmpi(MyLocator, NextLocator)==0)
416 + {
417 + /* we have found a VLYNQ with a matching Locator, so extract the ResetBase */
418 + error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, "ResetBase", ResetBase);
419 + if (error_code)
420 + {
421 + return(EC_VAL_BASE_ADDR_NOT_FOUND);
422 + }
423 + *ResetBase = ((bit32u)PhysToVirtNoCache(*ResetBase));
424 +
425 + /* found base address for root device, so we're done */
426 + return (EC_NO_ERRORS);
427 + }
428 + Inst++;
429 + } /* while */
430 + } /* else */
431 +
432 + return (EC_NO_ERRORS);
433 + }
434 +#endif
435 +
436 +#ifndef _CPHAL_AAL2 /* + RC 3.02 */
437 +static bit32u ConfigGetCommon(HAL_DEVICE *HalDev)
438 + {
439 + bit32u ParmValue;
440 + bit32 error_code;
441 + char *DeviceInfo = HalDev->DeviceInfo;
442 +
443 +#ifdef __CPHAL_DEBUG
444 + if (DBG(0))
445 + {
446 + dbgPrintf("[cpcommon]ConfigGetCommon(HalDev:%08x)\n", (bit32u)HalDev);
447 + osfuncSioFlush();
448 + }
449 +#endif
450 +
451 + error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszBase, &ParmValue);
452 + if (error_code)
453 + {
454 + return(EC_FUNC_HAL_INIT|EC_VAL_BASE_ADDR_NOT_FOUND);
455 + }
456 + HalDev->dev_base = ((bit32u)PhysToVirtNoCache(ParmValue));
457 +
458 +#ifndef _CPHAL_AAL5
459 +#ifndef _CPHAL_AAL2
460 + error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszResetBit, &ParmValue);
461 + if(error_code)
462 + {
463 + return(EC_FUNC_HAL_INIT|EC_VAL_RESET_BIT_NOT_FOUND);
464 + }
465 + HalDev->ResetBit = ParmValue;
466 +
467 + /* Get reset base address */
468 + error_code = ResetBaseGet(HalDev, &ParmValue);
469 + if (error_code)
470 + return(EC_FUNC_HAL_INIT|EC_VAL_RESET_BASE_NOT_FOUND);
471 + HalDev->ResetBase = ParmValue;
472 +#endif
473 +#endif
474 +
475 +#ifndef _CPHAL_CPSAR
476 + error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszIntLine,&ParmValue);
477 + if (error_code)
478 + {
479 + return(EC_FUNC_HAL_INIT|EC_VAL_INTERRUPT_NOT_FOUND);
480 + }
481 + HalDev->interrupt = ParmValue;
482 +#endif
483 +
484 + /* only look for the offset if there is a Locator field, which indicates that
485 + the module is a VLYNQ module */
486 + error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszLocator,&ParmValue);
487 + if (!error_code)
488 + {
489 + error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszOffset,&ParmValue);
490 + if (error_code)
491 + {
492 + return(EC_FUNC_HAL_INIT|EC_VAL_OFFSET_NOT_FOUND);
493 + }
494 + HalDev->offset = ParmValue;
495 + }
496 + else
497 + HalDev->offset = 0;
498 +
499 + error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszDebug, &ParmValue);
500 + if (!error_code) HalDev->debug = ParmValue;
501 +
502 + return (EC_NO_ERRORS);
503 + }
504 +#endif /* +RC 3.02 */
505 +
506 +#ifdef _CPHAL_CPMAC /* +RC 3.02 */
507 +static void StatsInit(HAL_DEVICE *HalDev) /* +() RC3.02 */
508 + {
509 + /* even though these statistics may be for multiple channels and
510 + queues, i need only configure the pointer to the beginning
511 + of the array, and I can index from there if necessary */
512 +
513 +#ifdef _CPHAL_AAL5
514 + StatsTable0[0].StatPtr = &HalDev->Stats.CrcErrors[0];
515 + StatsTable0[1].StatPtr = &HalDev->Stats.LenErrors[0];
516 + StatsTable0[2].StatPtr = &HalDev->Stats.AbortErrors[0];
517 + StatsTable0[3].StatPtr = &HalDev->Stats.StarvErrors[0];
518 +
519 + StatsTable1[0].StatPtr = &HalDev->Stats.DmaLenErrors[0];
520 + StatsTable1[1].StatPtr = &HalDev->Stats.TxMisQCnt[0][0];
521 + StatsTable1[2].StatPtr = &HalDev->Stats.RxMisQCnt[0];
522 + StatsTable1[3].StatPtr = &HalDev->Stats.TxEOQCnt[0][0];
523 + StatsTable1[4].StatPtr = &HalDev->Stats.RxEOQCnt[0];
524 + StatsTable1[5].StatPtr = &HalDev->Stats.RxPacketsServiced[0];
525 + StatsTable1[6].StatPtr = &HalDev->Stats.TxPacketsServiced[0][0];
526 + StatsTable1[7].StatPtr = &HalDev->Stats.RxMaxServiced;
527 + StatsTable1[8].StatPtr = &HalDev->Stats.TxMaxServiced[0][0];
528 + StatsTable1[9].StatPtr = &HalDev->Stats.RxTotal;
529 + StatsTable1[10].StatPtr = &HalDev->Stats.TxTotal;
530 +#endif
531 +
532 +#if (defined(_CPHAL_AAL5) || defined(_CPHAL_CPMAC))
533 + StatsTable2[0].StatPtr = (bit32u *)&HalDev->RcbPool[0];
534 + StatsTable2[1].StatPtr = &HalDev->RxActQueueCount[0];
535 + StatsTable2[2].StatPtr = (bit32u *)&HalDev->RxActQueueHead[0];
536 + StatsTable2[3].StatPtr = (bit32u *)&HalDev->RxActQueueTail[0];
537 + StatsTable2[4].StatPtr = &HalDev->RxActive[0];
538 + StatsTable2[5].StatPtr = (bit32u *)&HalDev->RcbStart[0];
539 + StatsTable2[6].StatPtr = &HalDev->RxTeardownPending[0];
540 + StatsTable2[7].StatPtr = (bit32u *)&HalDev->TcbPool[0][0];
541 + StatsTable2[8].StatPtr = &HalDev->TxActQueueCount[0][0];
542 + StatsTable2[9].StatPtr = (bit32u *)&HalDev->TxActQueueHead[0][0];
543 + StatsTable2[10].StatPtr = (bit32u *)&HalDev->TxActQueueTail[0][0];
544 + StatsTable2[11].StatPtr = &HalDev->TxActive[0][0];
545 + StatsTable2[12].StatPtr = (bit32u *)&HalDev->TcbStart[0][0];
546 + StatsTable2[13].StatPtr = &HalDev->TxTeardownPending[0];
547 +
548 + StatsTable3[0].StatPtr = &HalDev->ChData[0].RxBufSize;
549 + StatsTable3[1].StatPtr = &HalDev->ChData[0].RxBufferOffset;
550 + StatsTable3[2].StatPtr = &HalDev->ChData[0].RxNumBuffers;
551 + StatsTable3[3].StatPtr = &HalDev->ChData[0].RxServiceMax;
552 + StatsTable3[4].StatPtr = &HalDev->ChData[0].TxNumBuffers;
553 + StatsTable3[5].StatPtr = &HalDev->ChData[0].TxNumQueues;
554 + StatsTable3[6].StatPtr = &HalDev->ChData[0].TxServiceMax;
555 +#ifdef _CPHAL_AAL5
556 + StatsTable3[7].StatPtr = &HalDev->ChData[0].CpcsUU;
557 + StatsTable3[8].StatPtr = &HalDev->ChData[0].Gfc;
558 + StatsTable3[9].StatPtr = &HalDev->ChData[0].Clp;
559 + StatsTable3[10].StatPtr = &HalDev->ChData[0].Pti;
560 + StatsTable3[11].StatPtr = &HalDev->ChData[0].DaMask;
561 + StatsTable3[12].StatPtr = &HalDev->ChData[0].Priority;
562 + StatsTable3[13].StatPtr = &HalDev->ChData[0].PktType;
563 + StatsTable3[14].StatPtr = &HalDev->ChData[0].Vci;
564 + StatsTable3[15].StatPtr = &HalDev->ChData[0].Vpi;
565 + StatsTable3[16].StatPtr = &HalDev->ChData[0].TxVc_CellRate;
566 + StatsTable3[17].StatPtr = &HalDev->ChData[0].TxVc_QosType;
567 + StatsTable3[18].StatPtr = &HalDev->ChData[0].TxVc_Mbs;
568 + StatsTable3[19].StatPtr = &HalDev->ChData[0].TxVc_Pcr;
569 +#endif
570 +#endif
571 +
572 + StatsTable4[0].StatPtr = &HalDev->dev_base;
573 + StatsTable4[1].StatPtr = &HalDev->offset;
574 + StatsTable4[2].StatPtr = &HalDev->interrupt;
575 + StatsTable4[3].StatPtr = &HalDev->debug;
576 + StatsTable4[4].StatPtr = &HalDev->Inst;
577 + }
578 +#endif /* +RC 3.02 */
579 +
580 +#ifndef _CPHAL_CPSAR /* +RC 3.02 */
581 +#ifndef _CPHAL_AAL2 /* +RC 3.02 */
582 +/*
583 + * Returns statistics information.
584 + *
585 + * @param HalDev CPHAL module instance. (set by xxxInitModule())
586 + *
587 + * @return 0
588 + */
589 +static int StatsGet(HAL_DEVICE *HalDev, void **StatPtr, int Index, int Ch, int Queue)
590 + {
591 + int Size;
592 + bit32u *AddrPtr;
593 + char *DataPtr;
594 + STATS_TABLE *StatsTable;
595 + int i, NumberOfStats;
596 +
597 +#ifdef __CPHAL_DEBUG
598 + if (DBG(0))
599 + {
600 + dbgPrintf("[cpcommon]StatsGet(HalDev:%08x, StatPtr:%08x)\n",
601 + (bit32u)HalDev, (bit32u)StatPtr);
602 + osfuncSioFlush();
603 + }
604 +#endif
605 +
606 + StatsTable = StatsDb[Index].StatTable;
607 + NumberOfStats = StatsDb[Index].NumberOfStats;
608 +
609 + Size = sizeof(bit32u)*((NumberOfStats*2)+1);
610 + Size += (NumberOfStats*11);
611 + *StatPtr = (bit32u *)HalDev->OsFunc->Malloc(Size);
612 +
613 + AddrPtr = (bit32u *) *StatPtr;
614 + DataPtr = (char *)AddrPtr;
615 + DataPtr += sizeof(bit32u)*((NumberOfStats*2)+1);
616 +
617 + for (i=0; i<NumberOfStats; i++)
618 + {
619 + *AddrPtr++ = (bit32u)StatsTable[i].StatName;
620 + *AddrPtr++ = (bit32u)DataPtr;
621 + if (&StatsTable[i].StatPtr[Ch] != 0)
622 + {
623 + switch(StatsTable[i].DataType)
624 + {
625 + case 0:
626 + HalDev->OsFunc->Sprintf(DataPtr, "%d", (bit32u *)StatsTable[i].StatPtr[Ch]);
627 + break;
628 + case 1:
629 + HalDev->OsFunc->Sprintf(DataPtr, "0x%x", (bit32u *)StatsTable[i].StatPtr[Ch]);
630 + break;
631 + case 2:
632 + HalDev->OsFunc->Sprintf(DataPtr, "%d", *((bit32u *)StatsTable[i].StatPtr + (Ch * (sizeof(CHANNEL_INFO)/4))));
633 + break;
634 + case 3:
635 + HalDev->OsFunc->Sprintf(DataPtr, "%d", *((bit32u *)StatsTable[i].StatPtr + (Ch*MAX_QUEUE)+Queue));
636 + break;
637 + case 4:
638 + HalDev->OsFunc->Sprintf(DataPtr, "0x%x", *((bit32u *)StatsTable[i].StatPtr + (Ch*MAX_QUEUE)+Queue));
639 + break;
640 + default:
641 + /* invalid data type, due to CPHAL programming error */
642 + break;
643 + }
644 + }
645 + else
646 + {
647 + /* invalid statistics pointer, probably was not initialized */
648 + }
649 + DataPtr += HalDev->OsFunc->Strlen(DataPtr) + 1;
650 + }
651 +
652 + *AddrPtr = (bit32u) 0;
653 +
654 + return (EC_NO_ERRORS);
655 + }
656 +#endif /* +RC 3.02 */
657 +#endif /* +RC 3.02 */
658 +
659 +#ifdef _CPHAL_CPMAC
660 +static void gpioFunctional(int base, int bit)
661 + { /*+RC3.02*/
662 + bit32u GpioEnr = base + 0xC;
663 + /* To make functional, set to zero */
664 + *(volatile bit32u *)(GpioEnr) &= ~(1 << bit); /*+RC3.02*/
665 + } /*+RC3.02*/
666 +
667 +
668 +/*+RC3.02*/
669 +/* Common function, Checks to see if GPIO should be in functional mode */
670 +static void gpioCheck(HAL_DEVICE *HalDev, void *moduleDeviceInfo)
671 + { /*+RC3.02*/
672 + int rc;
673 + void *DeviceInfo;
674 + char *pszMuxBits;
675 + char pszMuxBit[20];
676 + char *pszTmp;
677 + char szMuxBit[20];
678 + char *ptr;
679 + int base;
680 + int reset_bit;
681 + int bit;
682 + OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
683 +
684 + rc = OsFunc->DeviceFindParmValue(moduleDeviceInfo, "gpio_mux",&pszTmp);
685 + if(rc) return;
686 + /* gpio entry found, get GPIO register info and make functional */
687 +
688 + /* temp copy until FinParmValue fixed */
689 + ptr = &szMuxBit[0];
690 + while ((*ptr++ = *pszTmp++));
691 +
692 + pszMuxBits = &szMuxBit[0];
693 +
694 + rc = OsFunc->DeviceFindInfo(0,"gpio",&DeviceInfo);
695 + if(rc) return;
696 +
697 + rc = OsFunc->DeviceFindParmUint(DeviceInfo, "base",&base);
698 + if(rc) return;
699 +
700 + rc = OsFunc->DeviceFindParmUint(DeviceInfo, "reset_bit",&reset_bit);
701 + if(rc) return;
702 +
703 + /* If GPIO still in reset, then exit */
704 + if((VOLATILE32(HalDev->ResetBase) & (1 << reset_bit)) == 0)
705 + return;
706 + /* format for gpio_mux is gpio_mux = <int>;<int>;<int>...*/
707 + while (*pszMuxBits)
708 + {
709 + pszTmp = &pszMuxBit[0];
710 + if(*pszMuxBits == ';') pszMuxBits++;
711 + while ((*pszMuxBits != ';') && (*pszMuxBits != '\0'))
712 + {
713 + osfuncSioFlush();
714 + /*If value not a number, skip */
715 + if((*pszMuxBits < '0') || (*pszMuxBits > '9'))
716 + pszMuxBits++;
717 + else
718 + *pszTmp++ = *pszMuxBits++;
719 + }
720 + *pszTmp = '\0';
721 + bit = OsFunc->Strtoul(pszMuxBit, &pszTmp, 10);
722 + gpioFunctional(base, bit);
723 + resetWait(HalDev); /* not sure if this is needed */
724 + }
725 + } /*+RC3.02*/
726 +#endif /* CPMAC */
727 +
728 +#ifdef _CPHAL_AAL5
729 +const char hcSarFrequency[] = "SarFreq";
730 +#endif
731 +
732 +#endif /* _INC */
733 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpcommon_cpmac.h linux-2.4.30/drivers/net/avalanche_cpmac/cpcommon_cpmac.h
734 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpcommon_cpmac.h 1970-01-01 02:00:00.000000000 +0200
735 +++ linux-2.4.30/drivers/net/avalanche_cpmac/cpcommon_cpmac.h 2005-04-15 05:10:40.000000000 +0200
736 @@ -0,0 +1,79 @@
737 +#ifndef _INC_CPCOMMON_H
738 +#define _INC_CPCOMMON_H
739 +
740 +#define VOLATILE32(addr) (*(volatile bit32u *)(addr))
741 +#ifndef dbgPrintf
742 +#define dbgPrintf HalDev->OsFunc->Printf
743 +#endif
744 +
745 +#define ChannelUpdate(Field) if(HalChn->Field != 0xFFFFFFFF) HalDev->ChData[Ch].Field = HalChn->Field
746 +
747 +#define DBG(level) (HalDev->debug & (1<<(level)))
748 +/*
749 +#define DBG0() DBG(0)
750 +#define DBG1() DBG(1)
751 +#define DBG2() DBG(2)
752 +#define DBG3() DBG(3)
753 +#define DBG4() DBG(4)
754 +#define DBG5() DBG(5)
755 +#define DBG6() DBG(6)
756 +#define DBG7() DBG(7)
757 +*/
758 +
759 +/*
760 + * List of defined actions for use with Control().
761 + */
762 +typedef enum
763 + {
764 + enGET=0, /**< Get the value associated with a key */
765 + enSET, /**< Set the value associates with a key */
766 + enCLEAR, /**<Clear the value */
767 + enNULL /**< No data action, used to initiate a service or send a message */
768 + }ACTION;
769 +
770 +/*
771 + * Enumerated hardware states.
772 + */
773 +typedef enum
774 + {
775 + enConnected=1, enDevFound, enInitialized, enOpened
776 + }DEVICE_STATE;
777 +
778 +typedef enum
779 + {
780 + enCommonStart=0,
781 + /* General */
782 + enOff, enOn, enDebug,
783 + /* Module General */
784 + enCpuFreq,
785 + enStatus,
786 + enCommonEnd
787 + }COMMON_KEY;
788 +
789 +typedef struct
790 + {
791 + const char *strKey;
792 + int enKey;
793 + }CONTROL_KEY;
794 +
795 +typedef struct
796 + {
797 + char *StatName;
798 + unsigned int *StatPtr;
799 + int DataType; /* 0: int, 1: hex int, 2:channel data */
800 + }STATS_TABLE;
801 +
802 +typedef struct
803 + {
804 + int NumberOfStats;
805 + STATS_TABLE *StatTable;
806 + }STATS_DB;
807 +
808 +#define osfuncSioFlush() HalDev->OsFunc->Control(HalDev->OsDev,"SioFlush",pszNULL,0)
809 +#define osfuncSleep(Ticks) HalDev->OsFunc->Control(HalDev->OsDev,pszSleep,pszNULL,Ticks)
810 +#define osfuncStateChange() HalDev->OsFunc->Control(HalDev->OsDev,pszStateChange,pszNULL,0)
811 +
812 +#define CHANNEL_NAMES {"Ch0","Ch1","Ch2","Ch3","Ch4","Ch5","Ch6","Ch7","Ch8","Ch9","Ch10","Ch11","Ch12","Ch13","Ch14","Ch15"}
813 +
814 +#endif
815 +
816 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpmac.c linux-2.4.30/drivers/net/avalanche_cpmac/cpmac.c
817 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpmac.c 1970-01-01 02:00:00.000000000 +0200
818 +++ linux-2.4.30/drivers/net/avalanche_cpmac/cpmac.c 2005-07-08 22:20:26.953335844 +0200
819 @@ -0,0 +1,2507 @@
820 +/******************************************************************************
821 + * FILE PURPOSE: CPMAC Linux Network Device Driver Source
822 + ******************************************************************************
823 + * FILE NAME: cpmac.c
824 + *
825 + * DESCRIPTION: CPMAC Network Device Driver Source
826 + *
827 + * REVISION HISTORY:
828 + *
829 + * Date Description Author
830 + *-----------------------------------------------------------------------------
831 + * 27 Nov 2002 Initial Creation Suraj S Iyer
832 + * 09 Jun 2003 Updates for GA Suraj S Iyer
833 + * 30 Sep 2003 Updates for LED, Reset stats Suraj S Iyer
834 + *
835 + * (C) Copyright 2003, Texas Instruments, Inc
836 + *******************************************************************************/
837 +#include <linux/kernel.h>
838 +#include <linux/module.h>
839 +#include <linux/init.h>
840 +#include <linux/netdevice.h>
841 +#include <linux/etherdevice.h>
842 +#include <linux/delay.h>
843 +#include <linux/spinlock.h>
844 +#include <linux/proc_fs.h>
845 +#include <linux/ioport.h>
846 +#include <asm/io.h>
847 +
848 +#include <linux/skbuff.h>
849 +
850 +#include <asm/mips-boards/prom.h>
851 +#include <linux/string.h>
852 +#include <asm/uaccess.h>
853 +#include <linux/config.h>
854 +
855 +#include <asm/ar7/avalanche_misc.h>
856 +#include <asm/ar7/sangam_clk_cntl.h>
857 +#include <asm/ar7/if_port.h>
858 +extern void build_psp_config(void);
859 +extern void psp_config_cleanup(void);
860 +
861 +#include "cpmacHalLx.h"
862 +#include "cpmac.h"
863 +
864 +static struct net_device *last_cpmac_device = NULL;
865 +static int cpmac_devices_installed = 0;
866 +
867 +void xdump( u_char* cp, int length, char* prefix );
868 +
869 +unsigned int cpmac_cpu_freq = 0;
870 +
871 +char cpmac_version[] = "1.5";
872 +
873 +char l3_align_array[] = {0x02, 0x01, 0x00, 0x03};
874 +#define L3_ALIGN(i) l3_align_array[i]
875 +
876 +char add_for_4byte_align[] = {0x04, 0x03, 0x02, 0x05};
877 +#define ADD_FOR_4BYTE_ALIGN(i) add_for_4byte_align[i]
878 +
879 +
880 +#define TPID 0x8100
881 +#define IS_802_1Q_FRAME(byte_ptr) (*(unsigned short*)byte_ptr == TPID)
882 +#define TPID_START_OFFSET 12
883 +#define TCI_START_OFFSET 14
884 +#define TCI_LENGTH 2
885 +#define TPID_LENGTH 2
886 +#define TPID_END_OFFSET (TPID_START_OFFSET + TPID_LENGTH)
887 +#define TCI_END_OFFSET (TCI_START_OFFSET + TCI_LENGTH)
888 +#define IS_VALID_VLAN_ID(byte_ptr) ((*(unsigned short*)byte_ptr) && 0xfff != 0)
889 +#define MAX_CLASSES 8
890 +#define MAX_USER_PRIORITY 8
891 +#define CONTROL_802_1Q_SIZE (TCI_LENGTH + TPID_LENGTH)
892 +
893 +unsigned char user_priority_to_traffic_class_map[MAX_CLASSES][MAX_USER_PRIORITY] =
894 +{
895 + {0, 0, 0, 1, 1, 1, 1, 2},
896 + {0, 0, 0, 0, 0, 0, 0, 0},
897 + {0, 0, 0, 0, 0, 0, 0, 1},
898 + {0, 0, 0, 1, 1, 2, 2, 3},
899 + {0, 1, 1, 2, 2, 3, 3, 4},
900 + {0, 1, 1, 2, 3, 4, 4, 5},
901 + {0, 1, 2, 3, 4, 5, 5, 6},
902 + {0, 1, 2, 3, 4, 5, 6, 7}
903 +};
904 +
905 +#define GET_802_1P_CHAN(x,y) user_priority_to_traffic_class_map[x][(y & 0xe0)]
906 +
907 +#if defined(CONFIG_MIPS_SEAD2)
908 +unsigned long temp_base_address[2] = {0xa8610000, 0xa8612800};
909 +unsigned long temp_reset_value[2] = { 1<< 17,1<<21};
910 +#define RESET_REG_PRCR (*(volatile unsigned int *)((0xa8611600 + 0x0)))
911 +#define VERSION(base) (*(volatile unsigned int *)(((base)|0xa0000000) + 0x0))
912 +#endif
913 +
914 +MODULE_AUTHOR("Maintainer: Suraj S Iyer <ssiyer@ti.com>");
915 +MODULE_DESCRIPTION("Driver for TI CPMAC");
916 +
917 +static int cfg_link_speed = 0;
918 +MODULE_PARM(cfg_link_speed, "i");
919 +MODULE_PARM_DESC(cfg_link_speed, "Fixed speed of the Link: <100/10>");
920 +
921 +static char *cfg_link_mode = NULL;
922 +MODULE_PARM(cfg_link_mode, "1-3s");
923 +MODULE_PARM_DESC(cfg_link_mode, "Fixed mode of the Link: <fd/hd>");
924 +
925 +int cpmac_debug_mode = 0;
926 +MODULE_PARM(debug_mode, "i");
927 +MODULE_PARM_DESC(debug_mode, "Turn on the debug info: <0/1>. Default is 0 (off)");
928 +
929 +#define dbgPrint if (cpmac_debug_mode) printk
930 +#define errPrint printk
931 +
932 +static int g_cfg_start_link_params = CFG_START_LINK_SPEED;
933 +static int g_init_enable_flag = 0;
934 +static int cfg_start_link_speed;
935 +static int cpmac_max_frame_size;
936 +
937 +static struct net_device *g_dev_array[2];
938 +static struct proc_dir_entry *gp_stats_file = NULL;
939 +
940 +//-----------------------------------------------------------------------------
941 +// Statistics related private functions.
942 +//-----------------------------------------------------------------------------
943 +static int cpmac_p_update_statistics(struct net_device *p_dev, char *buf, int limit, int *len);
944 +static int cpmac_p_read_rfc2665_stats(char *buf, char **start, off_t offset, int count, int *eof, void *data);
945 +static int cpmac_p_read_link(char *buf, char **start, off_t offset, int count, int *eof, void *data);
946 +static int cpmac_p_read_stats(char* buf, char **start, off_t offset, int count, int *eof, void *data);
947 +static int cpmac_p_write_stats (struct file *fp, const char * buf, unsigned long count, void * data);
948 +static int cpmac_p_reset_statistics (struct net_device *p_dev);
949 +static int cpmac_p_get_version(char *buf, char **start, off_t offset, int count, int *eof, void *data);
950 +
951 +static int cpmac_p_detect_manual_cfg(int, char*, int);
952 +static int cpmac_p_process_status_ind(CPMAC_PRIVATE_INFO_T *p_cpmac_priv);
953 +
954 +//-----------------------------------------------------------------------------
955 +// Timer related private functions.
956 +//-----------------------------------------------------------------------------
957 +static int cpmac_p_timer_init(CPMAC_PRIVATE_INFO_T *p_cpmac_priv);
958 +// static int cpmac_timer_cleanup(CPMAC_PRIVATE_INFO_T *p_cpmac_priv);
959 +static void cpmac_p_tick_timer_expiry(unsigned long p_cb_param);
960 +inline static int cpmac_p_start_timer(struct timer_list *p_timer, unsigned int delay_ticks);
961 +static int cpmac_p_stop_timer(struct timer_list *p_timer);
962 +
963 +//------------------------------------------------------------------------------
964 +// Device configuration and setup related private functions.
965 +//------------------------------------------------------------------------------
966 +static int cpmac_p_probe_and_setup_device(CPMAC_PRIVATE_INFO_T *p_cpmac_priv, unsigned long *p_dev_flags);
967 +static int cpmac_p_setup_driver_params(CPMAC_PRIVATE_INFO_T *p_cpmac_priv);
968 +inline static int cpmac_p_rx_buf_setup(CPMAC_RX_CHAN_INFO_T *p_rx_chan);
969 +
970 +//-----------------------------------------------------------------------------
971 +// Net device related private functions.
972 +//-----------------------------------------------------------------------------
973 +static int cpmac_dev_init(struct net_device *p_dev);
974 +static int cpmac_dev_open( struct net_device *dev );
975 +static int cpmac_dev_close(struct net_device *p_dev);
976 +static void cpmac_dev_mcast_set(struct net_device *p_dev);
977 +static int cpmac_dev_set_mac_addr(struct net_device *p_dev,void * addr);
978 +static int cpmac_dev_tx( struct sk_buff *skb, struct net_device *p_dev);
979 +static struct net_device_stats *cpmac_dev_get_net_stats (struct net_device *dev);
980 +
981 +static int cpmac_p_dev_enable( struct net_device *p_dev);
982 +
983 +
984 +
985 +/* Max. Reserved headroom in front of each packet so that the headers can be added to
986 + * a packet. Worst case scenario would be PPPoE + 2684 LLC Encapsulation + Ethernet
987 + * header. */
988 +#define MAX_RESERVED_HEADROOM 20
989 +
990 +/* This is the MAX size of the static buffer for pure data. */
991 +#define MAX_SIZE_STATIC_BUFFER 1600
992 +
993 +typedef struct DRIVER_BUFFER
994 +{
995 + /* Pointer to the allocated data buffer. This is the static data buffer
996 + * allocated for the TI-Cache. 60 bytes out of the below buffer are required
997 + * by the SKB shared info. We always reserve at least MAX_RESERVED_HEADROOM bytes
998 + * so that the packets always have sufficient headroom. */
999 + char ptr_buffer[MAX_SIZE_STATIC_BUFFER + MAX_RESERVED_HEADROOM + 60];
1000 +
1001 + /* List of the driver buffers. */
1002 + struct DRIVER_BUFFER* ptr_next;
1003 +}DRIVER_BUFFER;
1004 +
1005 +typedef struct DRIVER_BUFFER_MCB
1006 +{
1007 + /* List of the driver buffers. */
1008 + DRIVER_BUFFER* ptr_available_driver_buffers;
1009 +
1010 + /* The number of available buffers. */
1011 + int num_available_buffers;
1012 +}DRIVER_BUFFER_MCB;
1013 +
1014 +DRIVER_BUFFER_MCB driver_mcb;
1015 +int hybrid_mode = 0;
1016 +
1017 +static union {
1018 + struct sk_buff_head list;
1019 + char pad[SMP_CACHE_BYTES];
1020 +} skb_head_pool[NR_CPUS];
1021 +
1022 +/**************************************************************************
1023 + * FUNCTION NAME : ti_release_skb
1024 + **************************************************************************
1025 + * DESCRIPTION :
1026 + * This function is called from the ti_alloc_skb when there were no more
1027 + * data buffers available. The allocated SKB had to released back to the
1028 + * data pool. The reason why this function was moved from the fast path
1029 + * below was because '__skb_queue_head' is an inline function which adds
1030 + * a large code chunk on the fast path.
1031 + *
1032 + * NOTES :
1033 + * This function is called with interrupts disabled.
1034 + **************************************************************************/
1035 +static void ti_release_skb (struct sk_buff_head* list, struct sk_buff* skb)
1036 +{
1037 + __skb_queue_head(list, skb);
1038 + return;
1039 +}
1040 +
1041 +/**************************************************************************
1042 + * FUNCTION NAME : ti_alloc_skb
1043 + **************************************************************************
1044 + * DESCRIPTION :
1045 + * The function is called to allocate memory from the static allocated
1046 + * TI-Cached memory pool.
1047 + *
1048 + * RETURNS :
1049 + * Allocated static memory buffer - Success
1050 + * NULL - Error.
1051 + **************************************************************************/
1052 +struct sk_buff *ti_alloc_skb(unsigned int size,int gfp_mask)
1053 +{
1054 + register struct sk_buff* skb;
1055 + unsigned long flags;
1056 + struct sk_buff_head* list;
1057 + DRIVER_BUFFER* ptr_node = NULL;
1058 +
1059 + /* Critical Section Begin: Lock out interrupts. */
1060 + local_irq_save(flags);
1061 +
1062 + /* Get the SKB Pool list associated with the processor and dequeue the head. */
1063 + list = &skb_head_pool[smp_processor_id()].list;
1064 + skb = __skb_dequeue(list);
1065 +
1066 + /* Align the data size. */
1067 + size = SKB_DATA_ALIGN(size);
1068 +
1069 + /* Did we get one. */
1070 + if (skb != NULL)
1071 + {
1072 + /* YES. Now get a data block from the head of statically allocated block. */
1073 + ptr_node = driver_mcb.ptr_available_driver_buffers;
1074 + if (ptr_node != NULL)
1075 + {
1076 + /* YES. Got a data block. Advance the free list pointer to the next available buffer. */
1077 + driver_mcb.ptr_available_driver_buffers = ptr_node->ptr_next;
1078 + ptr_node->ptr_next = NULL;
1079 +
1080 + /* Decrement the number of available data buffers. */
1081 + driver_mcb.num_available_buffers = driver_mcb.num_available_buffers - 1;
1082 + }
1083 + else
1084 + {
1085 + /* NO. Was unable to get a data block. So put the SKB back on the free list.
1086 + * This is slow path. */
1087 +#ifdef DEBUG_SKB
1088 + printk ("DEBUG: No Buffer memory available: Number of free buffer:%d.\n",
1089 + driver_mcb.num_available_buffers);
1090 +#endif
1091 + ti_release_skb (list, skb);
1092 + }
1093 + }
1094 +
1095 + /* Critical Section End: Unlock interrupts. */
1096 + local_irq_restore(flags);
1097 +
1098 + /* Did we get an SKB and data buffer. Proceed only if we were succesful in getting both else drop */
1099 + if (skb != NULL && ptr_node != NULL)
1100 + {
1101 + /* XXX: does not include slab overhead */
1102 + skb->truesize = size + sizeof(struct sk_buff);
1103 +
1104 + /* Load the data pointers. */
1105 + skb->head = ptr_node->ptr_buffer;
1106 + skb->data = ptr_node->ptr_buffer + MAX_RESERVED_HEADROOM;
1107 + skb->tail = ptr_node->ptr_buffer + MAX_RESERVED_HEADROOM;
1108 + skb->end = ptr_node->ptr_buffer + size + MAX_RESERVED_HEADROOM;
1109 +
1110 + /* Set up other state */
1111 + skb->len = 0;
1112 + skb->cloned = 0;
1113 + skb->data_len = 0;
1114 +
1115 + /* Mark the SKB indicating that the SKB is from the TI cache. */
1116 + skb->cb[45] = 1;
1117 +
1118 + atomic_set(&skb->users, 1);
1119 + atomic_set(&(skb_shinfo(skb)->dataref), 1);
1120 + skb_shinfo(skb)->nr_frags = 0;
1121 + skb_shinfo(skb)->frag_list = NULL;
1122 + return skb;
1123 + }
1124 + else
1125 + {
1126 + /* Control comes here only when there is no statically allocated data buffers
1127 + * available. This case is handled using the mode selected
1128 + *
1129 + * 1. Hybrid Mode.
1130 + * In that case lets jump to the old allocation code. This way we
1131 + * can allocate a small number of data buffers upfront and the rest will hit
1132 + * this portion of the code, which is slow path. Note the number of hits here
1133 + * should be kept as low as possible to satisfy performance requirements.
1134 + *
1135 + * 2. Pure Static Mode.
1136 + * Return NULL the user should have tuned the number of static buffers for
1137 + * worst case scenario. So return NULL and let the drivers handle the error. */
1138 + if (hybrid_mode == 1)
1139 + {
1140 + /* Hybrid Mode: Old allocation. */
1141 + return dev_alloc_skb(size);
1142 + }
1143 + else
1144 + {
1145 + /* Pure Static Mode: No buffers available. */
1146 + return NULL;
1147 + }
1148 + }
1149 +}
1150 +
1151 +/**************************************************************************
1152 + * FUNCTION NAME : ti_skb_release_fragment
1153 + **************************************************************************
1154 + * DESCRIPTION :
1155 + * This function is called to release fragmented packets. This is NOT in
1156 + * the fast path and this function requires some work.
1157 + **************************************************************************/
1158 +static void ti_skb_release_fragment(struct sk_buff *skb)
1159 +{
1160 + if (skb_shinfo(skb)->nr_frags)
1161 + {
1162 + /* PANKAJ TODO: This portion has not been tested. */
1163 + int i;
1164 +#ifdef DEBUG_SKB
1165 + printk ("DEBUG: Releasing fragments in TI-Cached code.\n");
1166 +#endif
1167 + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1168 + printk ("DEBUG: Fragmented Page = 0x%p.\n", skb_shinfo(skb)->frags[i].page);
1169 + }
1170 +
1171 + /* Check if there were any fragments present and if so clean all the SKB's.
1172 + * This is required to recursivly clean the SKB's. */
1173 + if (skb_shinfo(skb)->frag_list)
1174 + skb_drop_fraglist(skb);
1175 +
1176 + return;
1177 +}
1178 +
1179 +/**************************************************************************
1180 + * FUNCTION NAME : ti_skb_release_data
1181 + **************************************************************************
1182 + * DESCRIPTION :
1183 + * The function is called to release the SKB back into the TI-Cached static
1184 + * memory pool.
1185 + **************************************************************************/
1186 +static void ti_skb_release_data(struct sk_buff *skb)
1187 +{
1188 + DRIVER_BUFFER* ptr_node;
1189 + unsigned long flags;
1190 +
1191 + /* The SKB data can be cleaned only if the packet has not been cloned and we
1192 + * are the only one holding a reference to the data. */
1193 + if (!skb->cloned || atomic_dec_and_test(&(skb_shinfo(skb)->dataref)))
1194 + {
1195 + /* Are there any fragments associated with the SKB ?*/
1196 + if ((skb_shinfo(skb)->nr_frags != 0) || (skb_shinfo(skb)->frag_list != NULL))
1197 + {
1198 + /* Slow Path: Try and clean up the fragments. */
1199 + ti_skb_release_fragment (skb);
1200 + }
1201 +
1202 + /* Cleanup the SKB data memory. This is fast path. */
1203 + ptr_node = (DRIVER_BUFFER *)skb->head;
1204 +
1205 + /* Critical Section: Lock out interrupts. */
1206 + local_irq_save(flags);
1207 +
1208 + /* Add the data buffer to the list of available buffers. */
1209 + ptr_node->ptr_next = driver_mcb.ptr_available_driver_buffers;
1210 + driver_mcb.ptr_available_driver_buffers = ptr_node;
1211 +
1212 + /* Increment the number of available data buffers. */
1213 + driver_mcb.num_available_buffers = driver_mcb.num_available_buffers + 1;
1214 +
1215 + /* Criticial Section: Unlock interrupts. */
1216 + local_irq_restore(flags);
1217 + }
1218 + return;
1219 +}
1220 +
1221 +
1222 +
1223 +
1224 +static unsigned char str2hexnum(unsigned char c)
1225 +{
1226 + if(c >= '0' && c <= '9')
1227 + return c - '0';
1228 + if(c >= 'a' && c <= 'f')
1229 + return c - 'a' + 10;
1230 + if(c >= 'A' && c <= 'F')
1231 + return c - 'A' + 10;
1232 + return 0;
1233 +}
1234 +
1235 +static void str2eaddr(unsigned char *ea, unsigned char *str)
1236 +{
1237 + int i;
1238 + unsigned char num;
1239 + for(i = 0; i < 6; i++) {
1240 + if((*str == '.') || (*str == ':'))
1241 + str++;
1242 + num = str2hexnum(*str++) << 4;
1243 + num |= (str2hexnum(*str++));
1244 + ea[i] = num;
1245 + }
1246 +}
1247 +
1248 +//-----------------------------------------------------------------------------
1249 +// Statistics related private functions.
1250 +//-----------------------------------------------------------------------------
1251 +static int cpmac_p_update_statistics(struct net_device *p_dev, char *buf, int limit, int *p_len)
1252 +{
1253 + int ret_val = -1;
1254 + unsigned long rx_hal_errors = 0;
1255 + unsigned long rx_hal_discards = 0;
1256 + unsigned long tx_hal_errors = 0;
1257 + unsigned long ifOutDiscards = 0;
1258 + unsigned long ifInDiscards = 0;
1259 + unsigned long ifOutErrors = 0;
1260 + unsigned long ifInErrors = 0;
1261 +
1262 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
1263 + CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
1264 + CPMAC_DEVICE_MIB_T *p_device_mib = p_cpmac_priv->device_mib;
1265 + CPMAC_DRV_STATS_T *p_stats = p_cpmac_priv->stats;
1266 + CPMAC_DEVICE_MIB_T local_mib;
1267 + CPMAC_DEVICE_MIB_T *p_local_mib = &local_mib;
1268 +
1269 + struct net_device_stats *p_net_dev_stats = &p_cpmac_priv->net_dev_stats;
1270 +
1271 + int len = 0;
1272 + int dev_mib_elem_count = 0;
1273 +
1274 + /* do not access the hardware if it is in the reset state. */
1275 + if(!test_bit(0, &p_cpmac_priv->set_to_close))
1276 + {
1277 + if(p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "StatsDump", "Get",
1278 + p_local_mib) != 0)
1279 + {
1280 + errPrint("The stats dump for %s is failing.\n", p_dev->name);
1281 + return(ret_val);
1282 + }
1283 +
1284 + p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "StatsClear", "Set", NULL);
1285 +
1286 + dev_mib_elem_count = sizeof(CPMAC_DEVICE_MIB_T)/sizeof(unsigned long);
1287 +
1288 + /* Update the history of the stats. This takes care of any reset of the
1289 + * device and stats that might have taken place during the life time of
1290 + * the driver.
1291 + */
1292 + while(dev_mib_elem_count--)
1293 + {
1294 + *((unsigned long*) p_device_mib + dev_mib_elem_count) +=
1295 + *((unsigned long*) p_local_mib + dev_mib_elem_count);
1296 + }
1297 + }
1298 +
1299 + /* RFC2665, section 3.2.7, page 9 */
1300 + rx_hal_errors = p_device_mib->ifInFragments +
1301 + p_device_mib->ifInCRCErrors +
1302 + p_device_mib->ifInAlignCodeErrors +
1303 + p_device_mib->ifInJabberFrames;
1304 +
1305 + /* RFC2233 */
1306 + rx_hal_discards = p_device_mib->ifRxDMAOverruns;
1307 +
1308 + /* RFC2665, section 3.2.7, page 9 */
1309 + tx_hal_errors = p_device_mib->ifExcessiveCollisionFrames +
1310 + p_device_mib->ifLateCollisions +
1311 + p_device_mib->ifCarrierSenseErrors +
1312 + p_device_mib->ifOutUnderrun;
1313 +
1314 + /* if not set, the short frames (< 64 bytes) are considered as errors */
1315 + if(!p_cpmac_priv->flags & IFF_PRIV_SHORT_FRAMES)
1316 + rx_hal_errors += p_device_mib->ifInUndersizedFrames;
1317 +
1318 + /* if not set, the long frames ( > 1518) are considered as errors
1319 + * RFC2665, section 3.2.7, page 9. */
1320 + if(!p_cpmac_priv->flags & IFF_PRIV_JUMBO_FRAMES)
1321 + rx_hal_errors += p_device_mib->ifInOversizedFrames;
1322 +
1323 + /* if not in promiscous, then non addr matching frames are discarded */
1324 + /* CPMAC 2.0 Manual Section 2.8.1.14 */
1325 + if(!p_dev->flags & IFF_PROMISC)
1326 + {
1327 + ifInDiscards += p_device_mib->ifInFilteredFrames;
1328 + }
1329 +
1330 + /* total rx discards = hal discards + driver discards. */
1331 + ifInDiscards = rx_hal_discards + p_net_dev_stats->rx_dropped;
1332 + ifInErrors = rx_hal_errors;
1333 +
1334 + ifOutErrors = tx_hal_errors;
1335 + ifOutDiscards = p_net_dev_stats->tx_dropped;
1336 +
1337 + /* Let us update the net device stats struct. To be updated in the later releases.*/
1338 + p_cpmac_priv->net_dev_stats.rx_errors = ifInErrors;
1339 + p_cpmac_priv->net_dev_stats.collisions = p_device_mib->ifCollisionFrames;
1340 +
1341 + if(buf == NULL || limit == 0)
1342 + {
1343 + return(0);
1344 + }
1345 +
1346 + if(len <= limit)
1347 + len+= sprintf(buf + len, "%-35s: %ld\n", "ifSpeed", (long)p_cpmac_priv->link_speed);
1348 + if(len <= limit)
1349 + len+= sprintf(buf + len, "%-35s: %lu\n", "dot3StatsDuplexStatus", (long)p_cpmac_priv->link_mode);
1350 + if(len <= limit)
1351 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifAdminStatus", (long)(p_dev->flags & IFF_UP ? 1:2));
1352 + if(len <= limit)
1353 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifOperStatus", (long)(((p_dev->flags & IFF_UP) && netif_carrier_ok(p_dev)) ? 1:2));
1354 + if(len <= limit)
1355 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifLastChange", p_stats->start_tick);
1356 + if(len <= limit)
1357 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifInDiscards", ifInDiscards);
1358 + if(len <= limit)
1359 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifInErrors", ifInErrors);
1360 + if(len <= limit)
1361 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutDiscards", ifOutDiscards);
1362 + if(len <= limit)
1363 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutErrors", ifOutErrors);
1364 + if(len <= limit)
1365 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifInGoodFrames", p_device_mib->ifInGoodFrames);
1366 + if(len <= limit)
1367 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifInBroadcasts", p_device_mib->ifInBroadcasts);
1368 + if(len <= limit)
1369 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifInMulticasts", p_device_mib->ifInMulticasts);
1370 + if(len <= limit)
1371 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifInPauseFrames", p_device_mib->ifInPauseFrames);
1372 + if(len <= limit)
1373 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifInCRCErrors", p_device_mib->ifInCRCErrors);
1374 + if(len <= limit)
1375 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifInAlignCodeErrors", p_device_mib->ifInAlignCodeErrors);
1376 + if(len <= limit)
1377 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifInOversizedFrames", p_device_mib->ifInOversizedFrames);
1378 + if(len <= limit)
1379 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifInJabberFrames", p_device_mib->ifInJabberFrames);
1380 + if(len <= limit)
1381 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifInUndersizedFrames", p_device_mib->ifInUndersizedFrames);
1382 + if(len <= limit)
1383 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifInFragments", p_device_mib->ifInFragments);
1384 + if(len <= limit)
1385 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifInFilteredFrames", p_device_mib->ifInFilteredFrames);
1386 + if(len <= limit)
1387 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifInQosFilteredFrames", p_device_mib->ifInQosFilteredFrames);
1388 + if(len <= limit)
1389 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifInOctets", p_device_mib->ifInOctets);
1390 + if(len <= limit)
1391 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutGoodFrames", p_device_mib->ifOutGoodFrames);
1392 + if(len <= limit)
1393 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutBroadcasts", p_device_mib->ifOutBroadcasts);
1394 + if(len <= limit)
1395 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutMulticasts", p_device_mib->ifOutMulticasts);
1396 + if(len <= limit)
1397 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutPauseFrames", p_device_mib->ifOutPauseFrames);
1398 + if(len <= limit)
1399 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifDeferredTransmissions", p_device_mib->ifDeferredTransmissions);
1400 + if(len <= limit)
1401 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifCollisionFrames", p_device_mib->ifCollisionFrames);
1402 + if(len <= limit)
1403 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifSingleCollisionFrames", p_device_mib->ifSingleCollisionFrames);
1404 + if(len <= limit)
1405 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifMultipleCollisionFrames", p_device_mib->ifMultipleCollisionFrames);
1406 + if(len <= limit)
1407 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifExcessiveCollisionFrames", p_device_mib->ifExcessiveCollisionFrames);
1408 + if(len <= limit)
1409 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifLateCollisions", p_device_mib->ifLateCollisions);
1410 + if(len <= limit)
1411 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutUnderrun", p_device_mib->ifOutUnderrun);
1412 + if(len <= limit)
1413 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifCarrierSenseErrors", p_device_mib->ifCarrierSenseErrors);
1414 + if(len <= limit)
1415 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutOctets", p_device_mib->ifOutOctets);
1416 + if(len <= limit)
1417 + len+= sprintf(buf + len, "%-35s: %lu\n", "if64OctetFrames", p_device_mib->if64OctetFrames);
1418 + if(len <= limit)
1419 + len+= sprintf(buf + len, "%-35s: %lu\n", "if65To127POctetFrames", p_device_mib->if65To127OctetFrames);
1420 + if(len <= limit)
1421 + len+= sprintf(buf + len, "%-35s: %lu\n", "if128To255OctetFrames", p_device_mib->if128To255OctetFrames);
1422 + if(len <= limit)
1423 + len+= sprintf(buf + len, "%-35s: %lu\n", "if256To511OctetFrames", p_device_mib->if256To511OctetFrames);
1424 + if(len <= limit)
1425 + len+= sprintf(buf + len, "%-35s: %lu\n", "if512To1023OctetFrames", p_device_mib->if512To1023OctetFrames);
1426 + if(len <= limit)
1427 + len+= sprintf(buf + len, "%-35s: %lu\n", "if1024ToUpOctetFrames", p_device_mib->if1024ToUPOctetFrames);
1428 + if(len <= limit)
1429 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifNetOctets", p_device_mib->ifNetOctets);
1430 + if(len <= limit)
1431 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifRxSofOverruns", p_device_mib->ifRxSofOverruns);
1432 + if(len <= limit)
1433 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifRxMofOverruns", p_device_mib->ifRxMofOverruns);
1434 + if(len <= limit)
1435 + len+= sprintf(buf + len, "%-35s: %lu\n", "ifRxDMAOverruns", p_device_mib->ifRxDMAOverruns);
1436 +
1437 + *p_len = len;
1438 +
1439 + return(0);
1440 +}
1441 +
1442 +
1443 +static int cpmac_p_read_rfc2665_stats(char* buf, char **start, off_t offset,
1444 + int count, int *eof, void *data)
1445 +{
1446 + int limit = count - 80;
1447 + int len = 0;
1448 + struct net_device *p_dev = (struct net_device*)data;
1449 +
1450 + cpmac_p_update_statistics(p_dev, buf, limit, &len);
1451 +
1452 + *eof = 1;
1453 +
1454 + return len;
1455 +}
1456 +
1457 +static int cpmac_p_read_link(char *buf, char **start, off_t offset, int count,
1458 + int *eof, void *data)
1459 +{
1460 + int len = 0;
1461 +
1462 + struct net_device *p_dev;
1463 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv;
1464 + struct net_device *cpmac_dev_list[cpmac_devices_installed];
1465 + CPMAC_DRV_HAL_INFO_T *p_drv_hal;
1466 +
1467 + int i;
1468 + int phy; /* what phy are we using? */
1469 +
1470 + len += sprintf(buf+len, "CPMAC devices = %d\n",cpmac_devices_installed);
1471 +
1472 + p_dev = last_cpmac_device;
1473 +
1474 + /* Reverse the the device link list to list eth0,eth1...in correct order */
1475 + for(i=0; i< cpmac_devices_installed; i++)
1476 + {
1477 + cpmac_dev_list[cpmac_devices_installed -(i+1)] = p_dev;
1478 + p_cpmac_priv = p_dev->priv;
1479 + p_dev = p_cpmac_priv->next_device;
1480 + }
1481 +
1482 + for(i=0; i< cpmac_devices_installed; i++)
1483 + {
1484 + p_dev = cpmac_dev_list[i];
1485 + p_cpmac_priv = p_dev->priv;
1486 + p_drv_hal = p_cpmac_priv->drv_hal;
1487 +
1488 + /* This prints them out from high to low because of how the devices are linked */
1489 + if(netif_carrier_ok(p_dev))
1490 + {
1491 + p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "PhyNum", "Get", &phy);
1492 +
1493 +
1494 + len += sprintf(buf+len,"eth%d: Link State: %s Phy:0x%x, Speed = %s, Duplex = %s\n",
1495 + p_cpmac_priv->instance_num, "UP", phy,
1496 + (p_cpmac_priv->link_speed == 100000000) ? "100":"10",
1497 + (p_cpmac_priv->link_mode == 2) ? "Half":"Full");
1498 +
1499 + }
1500 + else
1501 + len += sprintf(buf+len,"eth%d: Link State: DOWN\n",p_cpmac_priv->instance_num);
1502 +
1503 + p_dev = p_cpmac_priv->next_device;
1504 + }
1505 +
1506 + return len;
1507 +
1508 +}
1509 +
1510 +static int cpmac_p_read_stats(char* buf, char **start, off_t offset, int count,
1511 + int *eof, void *data)
1512 +{
1513 + struct net_device *p_dev = last_cpmac_device;
1514 + int len = 0;
1515 + int limit = count - 80;
1516 + int i;
1517 + struct net_device *cpmac_dev_list[cpmac_devices_installed];
1518 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv;
1519 + CPMAC_DEVICE_MIB_T *p_device_mib;
1520 +
1521 + /* Reverse the the device link list to list eth0,eth1...in correct order */
1522 + for(i=0; i< cpmac_devices_installed; i++)
1523 + {
1524 + cpmac_dev_list[cpmac_devices_installed - (i+1)] = p_dev;
1525 + p_cpmac_priv = p_dev->priv;
1526 + p_dev = p_cpmac_priv->next_device;
1527 + }
1528 +
1529 + for(i=0; i< cpmac_devices_installed; i++)
1530 + {
1531 + p_dev = cpmac_dev_list[i];
1532 +
1533 + if(!p_dev)
1534 + goto proc_error;
1535 +
1536 + /* Get Stats */
1537 + cpmac_p_update_statistics(p_dev, NULL, 0, NULL);
1538 +
1539 + p_cpmac_priv = p_dev->priv;
1540 + p_device_mib = p_cpmac_priv->device_mib;
1541 +
1542 + /* Transmit stats */
1543 + if(len<=limit)
1544 + len+= sprintf(buf+len, "\nCpmac %d, Address %lx\n",i+1, p_dev->base_addr);
1545 + if(len<=limit)
1546 + len+= sprintf(buf+len, " Transmit Stats\n");
1547 + if(len<=limit)
1548 + len+= sprintf(buf+len, " Tx Valid Bytes Sent :%lu\n",p_device_mib->ifOutOctets);
1549 + if(len<=limit)
1550 + len+= sprintf(buf+len, " Good Tx Frames (Hardware) :%lu\n",p_device_mib->ifOutGoodFrames);
1551 + if(len<=limit)
1552 + len+= sprintf(buf+len, " Good Tx Frames (Software) :%lu\n",p_cpmac_priv->net_dev_stats.tx_packets);
1553 + if(len<=limit)
1554 + len+= sprintf(buf+len, " Good Tx Broadcast Frames :%lu\n",p_device_mib->ifOutBroadcasts);
1555 + if(len<=limit)
1556 + len+= sprintf(buf+len, " Good Tx Multicast Frames :%lu\n",p_device_mib->ifOutMulticasts);
1557 + if(len<=limit)
1558 + len+= sprintf(buf+len, " Pause Frames Sent :%lu\n",p_device_mib->ifOutPauseFrames);
1559 + if(len<=limit)
1560 + len+= sprintf(buf+len, " Collisions :%lu\n",p_device_mib->ifCollisionFrames);
1561 + if(len<=limit)
1562 + len+= sprintf(buf+len, " Tx Error Frames :%lu\n",p_cpmac_priv->net_dev_stats.tx_errors);
1563 + if(len<=limit)
1564 + len+= sprintf(buf+len, " Carrier Sense Errors :%lu\n",p_device_mib->ifCarrierSenseErrors);
1565 + if(len<=limit)
1566 + len+= sprintf(buf+len, "\n");
1567 +
1568 +
1569 + /* Receive Stats */
1570 + if(len<=limit)
1571 + len+= sprintf(buf+len, "\nCpmac %d, Address %lx\n",i+1,p_dev->base_addr);
1572 + if(len<=limit)
1573 + len+= sprintf(buf+len, " Receive Stats\n");
1574 + if(len<=limit)
1575 + len+= sprintf(buf+len, " Rx Valid Bytes Received :%lu\n",p_device_mib->ifInOctets);
1576 + if(len<=limit)
1577 + len+= sprintf(buf+len, " Good Rx Frames (Hardware) :%lu\n",p_device_mib->ifInGoodFrames);
1578 + if(len<=limit)
1579 + len+= sprintf(buf+len, " Good Rx Frames (Software) :%lu\n",p_cpmac_priv->net_dev_stats.rx_packets);
1580 + if(len<=limit)
1581 + len+= sprintf(buf+len, " Good Rx Broadcast Frames :%lu\n",p_device_mib->ifInBroadcasts);
1582 + if(len<=limit)
1583 + len+= sprintf(buf+len, " Good Rx Multicast Frames :%lu\n",p_device_mib->ifInMulticasts);
1584 + if(len<=limit)
1585 + len+= sprintf(buf+len, " Pause Frames Received :%lu\n",p_device_mib->ifInPauseFrames);
1586 + if(len<=limit)
1587 + len+= sprintf(buf+len, " Rx CRC Errors :%lu\n",p_device_mib->ifInCRCErrors);
1588 + if(len<=limit)
1589 + len+= sprintf(buf+len, " Rx Align/Code Errors :%lu\n",p_device_mib->ifInAlignCodeErrors);
1590 + if(len<=limit)
1591 + len+= sprintf(buf+len, " Rx Jabbers :%lu\n",p_device_mib->ifInOversizedFrames);
1592 + if(len<=limit)
1593 + len+= sprintf(buf+len, " Rx Filtered Frames :%lu\n",p_device_mib->ifInFilteredFrames);
1594 + if(len<=limit)
1595 + len+= sprintf(buf+len, " Rx Fragments :%lu\n",p_device_mib->ifInFragments);
1596 + if(len<=limit)
1597 + len+= sprintf(buf+len, " Rx Undersized Frames :%lu\n",p_device_mib->ifInUndersizedFrames);
1598 + if(len<=limit)
1599 + len+= sprintf(buf+len, " Rx Overruns :%lu\n",p_device_mib->ifRxDMAOverruns);
1600 + }
1601 +
1602 +
1603 + return len;
1604 +
1605 + proc_error:
1606 + *eof=1;
1607 + return len;
1608 +}
1609 +
1610 +static int cpmac_p_write_stats (struct file *fp, const char * buf, unsigned long count, void * data)
1611 +{
1612 + char local_buf[31];
1613 + int ret_val = 0;
1614 +
1615 + if(count > 30)
1616 + {
1617 + printk("Error : Buffer Overflow\n");
1618 + printk("Use \"echo 0 > cpmac_stat\" to reset the statistics\n");
1619 + return -EFAULT;
1620 + }
1621 +
1622 + copy_from_user(local_buf,buf,count);
1623 + local_buf[count-1]='\0'; /* Ignoring last \n char */
1624 + ret_val = count;
1625 +
1626 + if(strcmp("0",local_buf)==0)
1627 + {
1628 + struct net_device *p_dev = last_cpmac_device;
1629 + int i;
1630 + struct net_device *cpmac_dev_list[cpmac_devices_installed];
1631 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv;
1632 +
1633 + /* Valid command */
1634 + printk("Resetting statistics for CPMAC interface.\n");
1635 +
1636 + /* Reverse the the device link list to list eth0,eth1...in correct order */
1637 + for(i=0; i< cpmac_devices_installed; i++)
1638 + {
1639 + cpmac_dev_list[cpmac_devices_installed - (i+1)] = p_dev;
1640 + p_cpmac_priv = p_dev->priv;
1641 + p_dev = p_cpmac_priv->next_device;
1642 + }
1643 +
1644 + for(i=0; i< cpmac_devices_installed; i++)
1645 + {
1646 + p_dev = cpmac_dev_list[i];
1647 + if(!p_dev)
1648 + {
1649 + ret_val = -EFAULT;
1650 + break;
1651 + }
1652 +
1653 + cpmac_p_reset_statistics(p_dev);
1654 + }
1655 + }
1656 + else
1657 + {
1658 + printk("Error: Unknown operation on cpmac statistics\n");
1659 + printk("Use \"echo 0 > cpmac_stats\" to reset the statistics\n");
1660 + return -EFAULT;
1661 + }
1662 +
1663 + return ret_val;
1664 +}
1665 +
1666 +static int cpmac_p_reset_statistics(struct net_device *p_dev)
1667 +{
1668 + int ret_val = 0;
1669 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
1670 + CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
1671 +
1672 + memset(p_cpmac_priv->device_mib, 0, sizeof(CPMAC_DEVICE_MIB_T));
1673 + memset(p_cpmac_priv->stats, 0, sizeof(CPMAC_DRV_STATS_T));
1674 + memset(&p_cpmac_priv->net_dev_stats, 0, sizeof(struct net_device_stats));
1675 +
1676 + p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "StatsClear", "Set", NULL);
1677 +
1678 + return(ret_val);
1679 +}
1680 +
1681 +static int cpmac_p_get_version(char* buf, char **start, off_t offset, int count,int *eof, void *data)
1682 +{
1683 + int len = 0;
1684 + int limit = count - 80;
1685 + char *hal_version = NULL;
1686 + struct net_device *p_dev = last_cpmac_device;
1687 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
1688 + CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
1689 +
1690 + p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "Version", "Get", &hal_version);
1691 +
1692 + len += sprintf(buf+len, "Texas Instruments CPMAC driver version: %s\n", cpmac_version);
1693 +
1694 + if(len <= limit && hal_version)
1695 + len += sprintf(buf+len, "Texas Instruments CPMAC HAL version: %s\n", hal_version);
1696 +
1697 + return len;
1698 +}
1699 +
1700 +static struct net_device_stats *cpmac_dev_get_net_stats (struct net_device *p_dev)
1701 +{
1702 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv = (CPMAC_PRIVATE_INFO_T *) p_dev->priv;
1703 +
1704 + cpmac_p_update_statistics(p_dev, NULL, 0, NULL);
1705 +
1706 + return &p_cpmac_priv->net_dev_stats;
1707 +}
1708 +
1709 +static int cpmac_p_detect_manual_cfg(int link_speed, char* link_mode, int debug)
1710 +{
1711 + char *pSpeed = NULL;
1712 +
1713 + if(debug == 1)
1714 + {
1715 + cpmac_debug_mode = 1;
1716 + dbgPrint("Enabled the debug print.\n");
1717 + }
1718 +
1719 + if(!link_speed && !link_mode)
1720 + {
1721 + dbgPrint("No manual link params, defaulting to auto negotiation.\n");
1722 + return (0);
1723 + }
1724 +
1725 + if(!link_speed || (link_speed != 10 && link_speed != 100))
1726 + {
1727 + dbgPrint("Invalid or No value of link speed specified, defaulting to auto speed.\n");
1728 + pSpeed = "auto";
1729 + }
1730 + else if(link_speed == 10)
1731 + {
1732 + g_cfg_start_link_params &= ~(_CPMDIO_100);
1733 + pSpeed = "10 Mbps";
1734 + }
1735 + else
1736 + {
1737 + g_cfg_start_link_params &= ~(_CPMDIO_10);
1738 + pSpeed = "100 Mbps";
1739 + }
1740 +
1741 + if(!link_mode || (!strcmp(link_mode, "fd") && !strcmp(link_mode, "hd")))
1742 + {
1743 + dbgPrint("Invalid or No value of link mode specified, defaulting to auto mode.\n");
1744 + }
1745 + else if(!strcmp(link_mode, "hd"))
1746 + {
1747 + g_cfg_start_link_params &= ~(_CPMDIO_FD);
1748 + }
1749 + else
1750 + {
1751 + g_cfg_start_link_params &= ~(_CPMDIO_HD);
1752 + }
1753 +
1754 + dbgPrint("Link is manually set to the speed of %s speed and %s mode.\n",
1755 + pSpeed, link_mode ? link_mode : "auto");
1756 +
1757 + return(0);
1758 +}
1759 +
1760 +//------------------------------------------------------------------------------
1761 +// Call back from the HAL.
1762 +//------------------------------------------------------------------------------
1763 +static int cpmac_p_process_status_ind(CPMAC_PRIVATE_INFO_T *p_cpmac_priv)
1764 +{
1765 + struct net_device *p_dev = p_cpmac_priv->owner;
1766 + CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
1767 + int status;
1768 +
1769 + p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "Status", "Get", &status);
1770 +
1771 + /* We do not reflect the real link status if in loopback.
1772 + * After all, we want the packets to reach the hardware so
1773 + * that Send() should work. */
1774 + if(p_dev->flags & IFF_LOOPBACK)
1775 + {
1776 + dbgPrint("Maintaining the link up loopback for %s.\n", p_dev->name);
1777 + netif_carrier_on(p_dev);
1778 +
1779 +#if defined (CONFIG_MIPS_AVALANCHE_LED)
1780 + avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_LINK_ON);
1781 +#endif
1782 +
1783 + return(0);
1784 + }
1785 +
1786 + if(status & CPMAC_STATUS_ADAPTER_CHECK) /* ???? */
1787 + {
1788 + ; /* what to do ? */
1789 + }
1790 + else if(status)
1791 + {
1792 + if(!netif_carrier_ok(p_dev))
1793 + {
1794 + netif_carrier_on(p_cpmac_priv->owner);
1795 +
1796 +#if defined (CONFIG_MIPS_AVALANCHE_LED)
1797 + avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_LINK_ON);
1798 +#endif
1799 + dbgPrint("Found the Link for the CPMAC instance %s.\n", p_dev->name);
1800 + }
1801 +
1802 + if(netif_running(p_dev) & netif_queue_stopped(p_dev))
1803 + {
1804 + netif_wake_queue(p_dev);
1805 + }
1806 +
1807 + p_cpmac_priv->link_speed = status & CPMAC_STATUS_LINK_SPEED ? 100000000:10000000;
1808 + p_cpmac_priv->link_mode = status & CPMAC_STATUS_LINK_DUPLEX? 3:2;
1809 +
1810 + }
1811 + else
1812 + {
1813 + if(netif_carrier_ok(p_dev))
1814 + {
1815 + /* do we need to register synchronization issues with stats here. */
1816 + p_cpmac_priv->link_speed = 100000000;
1817 + p_cpmac_priv->link_mode = 1;
1818 +
1819 + netif_carrier_off(p_dev);
1820 +
1821 +#if defined (CONFIG_MIPS_AVALANCHE_LED)
1822 + avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_LINK_OFF);
1823 +#endif
1824 +
1825 + dbgPrint("Lost the Link for the CPMAC for %s.\n", p_dev->name);
1826 + }
1827 +
1828 + if(!netif_queue_stopped(p_dev))
1829 + {
1830 + netif_stop_queue(p_dev); /* So that kernel does not keep on xmiting pkts. */
1831 + }
1832 + }
1833 +
1834 + return(0);
1835 +}
1836 +
1837 +//-----------------------------------------------------------------------------
1838 +// Timer related private functions.
1839 +//-----------------------------------------------------------------------------
1840 +static int cpmac_p_timer_init(CPMAC_PRIVATE_INFO_T *p_cpmac_priv)
1841 +{
1842 + struct timer_list *p_timer = p_cpmac_priv->timer;
1843 +
1844 + init_timer(p_timer);
1845 +
1846 + p_timer = p_cpmac_priv->timer + TICK_TIMER;
1847 + p_timer->expires = 0;
1848 + p_timer->data = (unsigned long)p_cpmac_priv;
1849 + p_timer->function = cpmac_p_tick_timer_expiry;
1850 +
1851 + return(0);
1852 +}
1853 +
1854 +#if 0
1855 +static int cpmac_timer_cleanup(CPMAC_PRIVATE_INFO_T *p_cpmac_priv)
1856 +{
1857 + struct timer_list *p_timer;
1858 +
1859 + p_timer = p_cpmac_priv->timer + TICK_TIMER;
1860 +
1861 + /* use spin lock to establish synchronization with the dispatch */
1862 + if(p_timer->function) del_timer_sync(p_timer);
1863 + p_timer->function = NULL;
1864 +
1865 + return (0);
1866 +}
1867 +#endif
1868 +
1869 +static int cpmac_p_start_timer(struct timer_list *p_timer, unsigned int delay_ticks)
1870 +{
1871 + p_timer->expires = jiffies + delay_ticks;
1872 +
1873 + if(p_timer->function)
1874 + {
1875 + add_timer(p_timer);
1876 + }
1877 +
1878 + return(0);
1879 +}
1880 +
1881 +static void cpmac_p_tick_timer_expiry(unsigned long p_cb_param)
1882 +{
1883 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv = (CPMAC_PRIVATE_INFO_T*) p_cb_param;
1884 + CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
1885 + struct timer_list *p_timer = p_cpmac_priv->timer + TICK_TIMER;
1886 +
1887 + if(test_bit(0, &p_cpmac_priv->set_to_close))
1888 + {
1889 + return;
1890 + }
1891 +
1892 + p_drv_hal->hal_funcs->Tick(p_drv_hal->hal_dev);
1893 +
1894 + cpmac_p_start_timer(p_timer, p_cpmac_priv->delay_ticks);
1895 +}
1896 +
1897 +static int cpmac_p_stop_timer(struct timer_list *p_timer)
1898 +{
1899 + /* Ideally we need to a set flag indicating not to start the timer again
1900 + before del_timer_sync() is called up. But here we assume that the
1901 + caller has set the p_cpmac_priv->set_to_close (ok for now). */
1902 + del_timer_sync(p_timer);
1903 +
1904 + return(0);
1905 +}
1906 +
1907 +//------------------------------------------------------------------------------
1908 +// Device configuration and setup related private functions.
1909 +//------------------------------------------------------------------------------
1910 +static int cpmac_p_probe_and_setup_device(CPMAC_PRIVATE_INFO_T *p_cpmac_priv,
1911 + unsigned long *p_dev_flags)
1912 +{
1913 + CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
1914 + HAL_FUNCTIONS *p_hal_funcs = p_drv_hal->hal_funcs;
1915 + HAL_DEVICE *p_hal_dev = p_drv_hal->hal_dev;
1916 + CPMAC_ABILITY_INFO_T *p_capability= p_cpmac_priv->ability_info;
1917 + unsigned int val = 0;
1918 + int channel = 0;
1919 +
1920 + p_cpmac_priv->flags = 0;
1921 +
1922 + p_capability->promiscous = CFG_PROMISCOUS;
1923 + p_capability->broadcast = CFG_BROADCAST;
1924 + p_capability->multicast = CFG_MULTICAST;
1925 + p_capability->all_multi = CFG_ALL_MULTI;
1926 + p_capability->jumbo_frames = CFG_JUMBO_FRAMES;
1927 + p_capability->short_frames = CFG_SHORT_FRAMES;
1928 + p_capability->auto_negotiation = CFG_AUTO_NEGOTIATION;
1929 + p_capability->link_speed = cfg_start_link_speed;
1930 + p_capability->loop_back = CFG_LOOP_BACK;
1931 + p_capability->tx_flow_control = CFG_TX_FLOW_CNTL;
1932 + p_capability->rx_flow_control = CFG_RX_FLOW_CNTL;
1933 + p_capability->tx_pacing = CFG_TX_PACING;
1934 + p_capability->rx_pass_crc = CFG_RX_PASS_CRC;
1935 + p_capability->qos_802_1q = CFG_QOS_802_1Q;
1936 + p_capability->tx_num_chan = CFG_TX_NUM_CHAN;
1937 +
1938 + /* Lets probe the device for the configured capabilities (netdev specific).*/
1939 +
1940 + /* Following are set in the set_multi_list, when indicated by the kernel
1941 + * Promiscous and all multi.
1942 + */
1943 +
1944 + if(p_capability->broadcast)
1945 + {
1946 + channel = 0;
1947 + val = 1;
1948 + if((p_hal_funcs->Control(p_hal_dev, pszRX_BROAD_EN, pszSet, &val) == 0) &&
1949 + (p_hal_funcs->Control(p_hal_dev, pszRX_BROAD_CH, pszSet, &channel) == 0))
1950 + *p_dev_flags |= IFF_BROADCAST;
1951 + else
1952 + p_capability->broadcast = 0; /* no broadcast capabilities */
1953 + }
1954 +
1955 + if(p_capability->multicast)
1956 + {
1957 + val = 1;
1958 + channel = 0;
1959 + if((p_hal_funcs->Control(p_hal_dev, pszRX_MULT_EN, pszSet, &val) == 0) &&
1960 + (p_hal_funcs->Control(p_hal_dev, pszRX_MULT_CH, pszSet, &channel) == 0))
1961 + *p_dev_flags |= IFF_MULTICAST;
1962 + else
1963 + {
1964 + p_capability->multicast = 0;
1965 + p_capability->all_multi = 0; /* no multicast, no all-multi. */
1966 + }
1967 + }
1968 +
1969 + if(p_capability->loop_back)
1970 + {
1971 + ; /* We do not put the device in loopback, if required use ioctl */
1972 + }
1973 +
1974 + /* Lets probe the device for the configured capabilities (Non net device specific).*/
1975 +
1976 + if(p_capability->jumbo_frames)
1977 + {
1978 + val = 0;
1979 + if(p_hal_funcs->Control(p_hal_dev, pszRX_NO_CHAIN, pszSet, &val) == 0)
1980 + p_cpmac_priv->flags |= IFF_PRIV_JUMBO_FRAMES;
1981 + else
1982 + p_capability->jumbo_frames = 0;
1983 + }
1984 +
1985 + if(p_capability->short_frames)
1986 + {
1987 + val = 1;
1988 + if(p_hal_funcs->Control(p_hal_dev, pszRX_CSF_EN, pszSet, &val) == 0)
1989 + p_cpmac_priv->flags |= IFF_PRIV_SHORT_FRAMES;
1990 + else
1991 + p_capability->short_frames = 0;
1992 + }
1993 +
1994 + val = g_cfg_start_link_params;
1995 +
1996 + if( avalanche_is_mdix_on_chip() )
1997 + {
1998 + val |= _CPMDIO_AUTOMDIX;
1999 + }
2000 +
2001 + if(p_hal_funcs->Control(p_hal_dev,pszMdioConnect,pszSet, &val) !=0)
2002 + {
2003 + p_capability->link_speed = 0;
2004 + }
2005 + else
2006 + {
2007 + if(g_cfg_start_link_params & (_CPMDIO_100 | _CPMDIO_HD | _CPMDIO_FD | _CPMDIO_10))
2008 + p_cpmac_priv->flags |= IFF_PRIV_AUTOSPEED;
2009 + else if(g_cfg_start_link_params & (_CPMDIO_100 | _CPMDIO_HD))
2010 + p_cpmac_priv->flags |= IFF_PRIV_LINK100_HD;
2011 + else if(g_cfg_start_link_params & (_CPMDIO_100 | _CPMDIO_FD))
2012 + p_cpmac_priv->flags |= IFF_PRIV_LINK100_FD;
2013 + else if(g_cfg_start_link_params & (_CPMDIO_10 | _CPMDIO_HD))
2014 + p_cpmac_priv->flags |= IFF_PRIV_LINK10_HD;
2015 + else if(g_cfg_start_link_params & (_CPMDIO_10 | _CPMDIO_FD))
2016 + p_cpmac_priv->flags |= IFF_PRIV_LINK10_FD;
2017 + else
2018 + ;
2019 + }
2020 +
2021 + if(p_capability->tx_flow_control)
2022 + {
2023 + val = 1;
2024 + if(p_hal_funcs->Control(p_hal_dev,pszTX_FLOW_EN, pszSet, &val) ==0)
2025 + p_cpmac_priv->flags |= IFF_PRIV_TX_FLOW_CNTL;
2026 + else
2027 + p_capability->tx_flow_control = 0;
2028 + }
2029 +
2030 + if(p_capability->rx_flow_control)
2031 + {
2032 + val = 1;
2033 + if(p_hal_funcs->Control(p_hal_dev, pszRX_FLOW_EN, pszSet, &val) ==0)
2034 + p_cpmac_priv->flags |= IFF_PRIV_RX_FLOW_CNTL;
2035 + else
2036 + p_capability->rx_flow_control = 0;
2037 + }
2038 +
2039 + if(p_capability->tx_pacing)
2040 + {
2041 + val = 1;
2042 + if(p_hal_funcs->Control(p_hal_dev, pszTX_PACE, pszSet, &val) ==0)
2043 + p_cpmac_priv->flags |= IFF_PRIV_TX_PACING;
2044 + else
2045 + p_capability->tx_pacing = 0;
2046 + }
2047 +
2048 + if(p_capability->rx_pass_crc)
2049 + {
2050 + val = 1;
2051 + if(p_hal_funcs->Control(p_hal_dev, pszRX_PASS_CRC, pszSet, &val) == 0)
2052 + p_cpmac_priv->flags |= IFF_PRIV_RX_PASS_CRC;
2053 + else
2054 + p_capability->rx_pass_crc = 0;
2055 + }
2056 +
2057 + if(p_capability->qos_802_1q)
2058 + {
2059 + val = 1;
2060 + if(p_hal_funcs->Control(p_hal_dev, pszRX_QOS_EN, pszSet, &val) == 0)
2061 + p_cpmac_priv->flags |= IFF_PRIV_8021Q_EN;
2062 + else
2063 + {
2064 + p_capability->qos_802_1q = 0;
2065 + p_capability->tx_num_chan= 1;
2066 + }
2067 + }
2068 +
2069 + if(p_capability->tx_num_chan > 1)
2070 + {
2071 + int cfg_tx_num_chan = p_capability->tx_num_chan;
2072 + val = 0;
2073 +#ifdef TEST
2074 + if(p_hal_funcs->Control(p_hal_dev, pszTX_NUM_CH, pszGet, &val) == 0)
2075 + cfg_tx_num_chan = cfg_tx_num_chan > val ? val : cfg_tx_num_chan;
2076 + else
2077 + cfg_tx_num_chan = 1;
2078 +#endif
2079 + p_capability->tx_num_chan = cfg_tx_num_chan;
2080 + }
2081 +
2082 + return(0);
2083 +}
2084 +
2085 +static int cpmac_p_setup_driver_params(CPMAC_PRIVATE_INFO_T *p_cpmac_priv)
2086 +{
2087 + int i=0;
2088 + int threshold = CFG_TX_NUM_BUF_SERVICE;
2089 +
2090 + char *tx_threshold_ptr = prom_getenv("threshold");
2091 +
2092 + CPMAC_TX_CHAN_INFO_T *p_tx_chan_info = p_cpmac_priv->tx_chan_info;
2093 + CPMAC_RX_CHAN_INFO_T *p_rx_chan_info = p_cpmac_priv->rx_chan_info;
2094 + CPMAC_ABILITY_INFO_T *p_capability = p_cpmac_priv->ability_info;
2095 +
2096 + /* Timer stuff */
2097 + p_cpmac_priv->timer_count = 1; /* should be < or = the MAX TIMER */
2098 + p_cpmac_priv->timer_created = 0;
2099 + p_cpmac_priv->timer_access_hal = 1;
2100 +
2101 + for(i=0; i < MAX_TIMER; i++)
2102 + p_cpmac_priv->timer[i].function = NULL;
2103 +
2104 + p_cpmac_priv->enable_802_1q = p_capability->qos_802_1q;
2105 +
2106 + /* Tx channel related.*/
2107 + p_tx_chan_info->cfg_chan = p_capability->tx_num_chan;
2108 + p_tx_chan_info->opened_chan = 0;
2109 +
2110 + if(tx_threshold_ptr)
2111 + threshold = simple_strtol(tx_threshold_ptr, (char **)NULL, 10);
2112 +
2113 + if((threshold <= 0) && tx_threshold_ptr) /* If threshold set to 0 then Enable the TX interrupt */
2114 + {
2115 + threshold = CFG_TX_NUM_BUF_SERVICE;
2116 + p_tx_chan_info->tx_int_disable = 0;
2117 +
2118 + }
2119 + else
2120 + {
2121 + p_tx_chan_info->tx_int_disable = CFG_TX_INT_DISABLE;
2122 + }
2123 +
2124 + for(i=0; i < MAX_TX_CHAN; i++)
2125 + {
2126 +
2127 +
2128 +
2129 + p_tx_chan_info->chan[i].state = CHAN_CLOSE;
2130 + p_tx_chan_info->chan[i].num_BD = CFG_TX_NUM_BUF_DESC;
2131 + p_tx_chan_info->chan[i].buffer_size = cpmac_max_frame_size;
2132 + p_tx_chan_info->chan[i].buffer_offset = CFG_TX_BUF_OFFSET;
2133 +
2134 +
2135 +
2136 + p_tx_chan_info->chan[i].service_max = threshold;
2137 + }
2138 +
2139 + if (p_tx_chan_info->tx_int_disable)
2140 + printk("Cpmac driver Disable TX complete interrupt setting threshold to %d.\n",threshold);
2141 + else
2142 + printk("Cpmac driver Enable TX complete interrupt\n");
2143 +
2144 +
2145 + /* Assuming just one rx channel for now */
2146 + p_rx_chan_info->cfg_chan = 1;
2147 + p_rx_chan_info->opened_chan = 0;
2148 + p_rx_chan_info->chan->state = CHAN_CLOSE;
2149 + p_rx_chan_info->chan->num_BD = CFG_RX_NUM_BUF_DESC;
2150 + p_rx_chan_info->chan->buffer_size = cpmac_max_frame_size;
2151 + p_rx_chan_info->chan->buffer_offset = CFG_RX_BUF_OFFSET;
2152 + p_rx_chan_info->chan->service_max = CFG_RX_NUM_BUF_SERVICE;
2153 +
2154 + /* Set as per RFC 2665 */
2155 + p_cpmac_priv->link_speed = 100000000;
2156 + p_cpmac_priv->link_mode = 1;
2157 +
2158 + p_cpmac_priv->loop_back = 0;
2159 +
2160 + return(0);
2161 +}
2162 +
2163 +inline static int cpmac_p_rx_buf_setup(CPMAC_RX_CHAN_INFO_T *p_rx_chan)
2164 +{
2165 + /* Number of ethernet packets & max pkt length */
2166 + p_rx_chan->chan->tot_buf_size = p_rx_chan->chan->buffer_size +
2167 + 2*(CONTROL_802_1Q_SIZE) +
2168 + p_rx_chan->chan->buffer_offset +
2169 + ADD_FOR_4BYTE_ALIGN(p_rx_chan->chan->buffer_offset & 0x3);
2170 +
2171 + p_rx_chan->chan->tot_reserve_bytes = CONTROL_802_1Q_SIZE +
2172 + p_rx_chan->chan->buffer_offset +
2173 + L3_ALIGN(p_rx_chan->chan->buffer_offset & 0x3);
2174 +
2175 + return(0);
2176 +}
2177 +
2178 +//-----------------------------------------------------------------------------
2179 +// Net device related private functions.
2180 +//-----------------------------------------------------------------------------
2181 +
2182 +/***************************************************************
2183 + * cpmac_dev_init
2184 + *
2185 + * Returns:
2186 + * 0 on success, error code otherwise.
2187 + * Parms:
2188 + * dev The structure of the device to be
2189 + * init'ed.
2190 + *
2191 + * This function completes the initialization of the
2192 + * device structure and driver. It reserves the IO
2193 + * addresses and assignes the device's methods.
2194 + *
2195 + *
2196 + **************************************************************/
2197 +
2198 +static int cpmac_dev_init(struct net_device *p_dev)
2199 +{
2200 + int retVal = -1;
2201 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
2202 + int instance_num = p_cpmac_priv->instance_num;
2203 + unsigned long net_flags = 0;
2204 + char *mac_name = NULL;
2205 + char *mac_string = NULL;
2206 +
2207 + CPMAC_TX_CHAN_INFO_T *p_tx_chan_info;
2208 + CPMAC_RX_CHAN_INFO_T *p_rx_chan_info;
2209 + CPMAC_DRV_HAL_INFO_T *p_drv_hal;
2210 + int i;
2211 +
2212 + int mem_size = sizeof(CPMAC_DRV_HAL_INFO_T)
2213 + + sizeof(CPMAC_TX_CHAN_INFO_T)
2214 + + sizeof(CPMAC_RX_CHAN_INFO_T)
2215 + + sizeof(CPMAC_ABILITY_INFO_T)
2216 + + sizeof(CPMAC_DEVICE_MIB_T)
2217 + + sizeof(CPMAC_DRV_STATS_T);
2218 +
2219 +
2220 +#if defined(CONFIG_MIPS_SEAD2)
2221 + int prev_reset_val = RESET_REG_PRCR;
2222 + /* Bring the module out of reset */
2223 + RESET_REG_PRCR |= temp_reset_value[p_cpmac_priv->instance_num];
2224 +
2225 + /* Read the version id of the device to check if the device really exists */
2226 + if( VERSION(temp_base_address[p_cpmac_priv->instance_num]) == 0)
2227 + {
2228 + printk(" CPMAC:Device not found\n");
2229 + RESET_REG_PRCR = prev_reset_val;
2230 + return -ENODEV;
2231 + }
2232 +
2233 + RESET_REG_PRCR = prev_reset_val;
2234 +#endif
2235 +
2236 +
2237 + if((p_drv_hal = kmalloc(mem_size, GFP_KERNEL)) == NULL)
2238 + {
2239 + errPrint("Failed to allocate memory; rewinding.\n");
2240 + return(-1);
2241 + }
2242 +
2243 + memset(p_drv_hal, 0, mem_size);
2244 +
2245 + /* build the cpmac private object */
2246 + p_cpmac_priv->drv_hal = p_drv_hal;
2247 + p_cpmac_priv->tx_chan_info = p_tx_chan_info
2248 + = (CPMAC_TX_CHAN_INFO_T*)((char*)p_drv_hal
2249 + + sizeof(CPMAC_DRV_HAL_INFO_T));
2250 + p_cpmac_priv->rx_chan_info = p_rx_chan_info
2251 + = (CPMAC_RX_CHAN_INFO_T*)((char *)p_tx_chan_info
2252 + + sizeof(CPMAC_TX_CHAN_INFO_T));
2253 + p_cpmac_priv->ability_info = (CPMAC_ABILITY_INFO_T *)((char *)p_rx_chan_info
2254 + + sizeof(CPMAC_RX_CHAN_INFO_T));
2255 + p_cpmac_priv->device_mib = (CPMAC_DEVICE_MIB_T *)((char *)p_cpmac_priv->ability_info
2256 + + sizeof(CPMAC_ABILITY_INFO_T));
2257 + p_cpmac_priv->stats = (CPMAC_DRV_STATS_T *)((char *)p_cpmac_priv->device_mib
2258 + + sizeof(CPMAC_DEVICE_MIB_T));
2259 +
2260 + p_drv_hal->owner = p_cpmac_priv;
2261 +
2262 +
2263 + switch(instance_num)
2264 + {
2265 +
2266 + case 0:
2267 + mac_name="maca";
2268 +
2269 + /* Also setting port information */
2270 + p_dev->if_port = AVALANCHE_CPMAC_LOW_PORT_ID;
2271 +
2272 + break;
2273 +
2274 + case 1:
2275 + mac_name="macb";
2276 +
2277 + /* Also setting port information */
2278 + p_dev->if_port = AVALANCHE_CPMAC_HIGH_PORT_ID;
2279 +
2280 + break;
2281 + }
2282 +
2283 + if(mac_name)
2284 + mac_string=prom_getenv(mac_name);
2285 +
2286 + if(!mac_string)
2287 + {
2288 + mac_string="08.00.28.32.06.02";
2289 + printk("Error getting mac from Boot enviroment for %s\n",p_dev->name);
2290 + printk("Using default mac address: %s\n",mac_string);
2291 + if(mac_name)
2292 + {
2293 + printk("Use Bootloader command:\n");
2294 + printk(" setenv %s xx.xx.xx.xx.xx.xx\n","<env_name>");
2295 + printk("to set mac address\n");
2296 + }
2297 + }
2298 +
2299 + str2eaddr(p_cpmac_priv->mac_addr,mac_string);
2300 +
2301 + for (i=0; i <= ETH_ALEN; i++)
2302 + {
2303 + /* This sets the hardware address */
2304 + p_dev->dev_addr[i] = p_cpmac_priv->mac_addr[i];
2305 + }
2306 +
2307 + p_cpmac_priv->set_to_close = 1;
2308 + p_cpmac_priv->non_data_irq_expected = 0;
2309 +
2310 +#if defined (CONFIG_MIPS_AVALANCHE_LED)
2311 + if((p_cpmac_priv->led_handle = avalanche_led_register("cpmac", instance_num)) == NULL)
2312 + {
2313 + errPrint("Could not allocate handle for CPMAC[%d] LED.\n", instance_num);
2314 + goto cpmac_init_mod_error;
2315 + }
2316 +#endif
2317 +
2318 + if(cpmac_drv_init_module(p_drv_hal, p_dev, instance_num) != 0)
2319 + {
2320 + errPrint("Could not initialize the HAL for %s.\n", p_dev->name);
2321 + goto cpmac_init_mod_error;
2322 + }
2323 +
2324 + /* initialize the CPMAC device */
2325 + if (cpmac_drv_init(p_drv_hal) == -1)
2326 + {
2327 + errPrint("HAL init failed for %s.\n", p_dev->name);
2328 + goto cpmac_init_device_error;
2329 + }
2330 +
2331 + if(cpmac_p_probe_and_setup_device(p_cpmac_priv, &net_flags) == -1)
2332 + {
2333 + errPrint("Failed to configure up %s.\n", p_dev->name);
2334 + goto cpmac_init_device_error;
2335 + }
2336 +
2337 + if(cpmac_p_setup_driver_params(p_cpmac_priv) == -1)
2338 + {
2339 + errPrint("Failed to set driver parameters for %s.\n", p_dev->name);
2340 + goto cpmac_init_device_error;
2341 + }
2342 +
2343 + cpmac_p_rx_buf_setup(p_rx_chan_info);
2344 +
2345 + /* initialize the timers for the net device */
2346 + if(cpmac_p_timer_init(p_cpmac_priv) == -1)
2347 + {
2348 + errPrint("Failed to set timer(s) for %s.\n", p_dev->name);
2349 + goto cpmac_timer_init_error;
2350 + }
2351 +
2352 + p_dev->addr_len = 6;
2353 +
2354 + p_dev->open = &cpmac_dev_open; /* i.e. Start Device */
2355 + p_dev->hard_start_xmit = &cpmac_dev_tx;
2356 + p_dev->stop = &cpmac_dev_close;
2357 + p_dev->get_stats = &cpmac_dev_get_net_stats;
2358 +
2359 + p_dev->set_multicast_list = &cpmac_dev_mcast_set;
2360 + p_dev->set_mac_address = cpmac_dev_set_mac_addr;
2361 + /* Knocking off the default broadcast and multicast flags. Allowing the
2362 + device configuration to control the flags. */
2363 + p_dev->flags &= ~(IFF_BROADCAST | IFF_MULTICAST);
2364 + p_dev->flags |= net_flags;
2365 +
2366 + netif_carrier_off(p_dev);
2367 +
2368 +#if defined (CONFIG_MIPS_AVALANCHE_LED)
2369 + avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_LINK_OFF);
2370 +#endif
2371 +
2372 + /* Tasklet is initialized at the isr registeration time. */
2373 + p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "CpmacBase", "Get", &p_dev->base_addr);
2374 + p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "CpmacSize", "Get", &p_cpmac_priv->dev_size);
2375 +
2376 + request_mem_region(p_dev->base_addr, p_cpmac_priv->dev_size, p_dev->name);
2377 +
2378 + retVal = 0;
2379 +
2380 + if(g_init_enable_flag)
2381 + cpmac_p_dev_enable(p_dev);
2382 +
2383 + return(retVal);
2384 +
2385 +cpmac_timer_init_error:
2386 +cpmac_init_device_error :
2387 + cpmac_drv_cleanup(p_drv_hal);
2388 +
2389 +cpmac_init_mod_error:
2390 + kfree(p_drv_hal);
2391 +
2392 + return (retVal);
2393 +
2394 +} /* cpmac_dev_init */
2395 +
2396 +
2397 +/***************************************************************
2398 + * cpmac_p_dev_enable
2399 + *
2400 + * Returns:
2401 + * 0 on success, error code otherwise.
2402 + * Parms:
2403 + * dev Structure of device to be opened.
2404 + *
2405 + * This routine puts the driver and CPMAC adapter in a
2406 + * state where it is ready to send and receive packets.
2407 + *
2408 + *
2409 + **************************************************************/
2410 +int cpmac_p_dev_enable( struct net_device *p_dev)
2411 +{
2412 + int ret_val = 0;
2413 + int channel = 0;
2414 +
2415 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
2416 + CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
2417 + CPMAC_RX_CHAN_INFO_T *p_rx_chan_info = p_cpmac_priv->rx_chan_info;
2418 + int max_length = p_rx_chan_info->chan->tot_buf_size;
2419 +
2420 + p_cpmac_priv->set_to_close = 0;
2421 +
2422 + if((ret_val = cpmac_drv_start(p_drv_hal, p_cpmac_priv->tx_chan_info,
2423 + p_cpmac_priv->rx_chan_info, CHAN_SETUP))==-1)
2424 + {
2425 + errPrint("%s error: failed to start the device.\n", p_dev->name);
2426 + ret_val = -1;
2427 + }
2428 + else if(p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev,"RX_UNICAST_SET",
2429 + "Set", &channel)!=0)
2430 + {
2431 + errPrint("%s error: device chan 0 could not be enabled.\n", p_dev->name);
2432 + ret_val = -1;
2433 + }
2434 + else if(p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, pszRX_MAXLEN, pszSet, &max_length) != 0)
2435 + {
2436 + errPrint(" CPMAC registers can't be written \n");
2437 + ret_val = -1;
2438 + }
2439 + else if(p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "TxIntDisable", "Set",
2440 + &p_cpmac_priv->tx_chan_info->tx_int_disable) != 0)
2441 + {
2442 + errPrint(" CPMAC registers can't be written \n");
2443 + ret_val = -1;
2444 + }
2445 + else
2446 + {
2447 + ; // Every thing went OK.
2448 + }
2449 +
2450 + return(ret_val);
2451 +} /* cpmac_dev_enable */
2452 +
2453 +
2454 +static int cpmac_dev_open(struct net_device *p_dev)
2455 +{
2456 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
2457 + CPMAC_ISR_INFO_T *p_isr_cb_param = &p_cpmac_priv->cpmac_isr;
2458 +
2459 + if(!g_init_enable_flag)
2460 + cpmac_p_dev_enable(p_dev);
2461 +
2462 + if(request_irq(p_isr_cb_param->intr, cpmac_hal_isr, SA_INTERRUPT,
2463 + "Cpmac Driver", p_isr_cb_param))
2464 + {
2465 + errPrint("Failed to register the irq %d for Cpmac %s.\n",
2466 + p_isr_cb_param->intr, p_dev->name);
2467 + return (-1);
2468 + }
2469 +
2470 + netif_start_queue(p_dev);
2471 +
2472 + MOD_INC_USE_COUNT;
2473 + p_cpmac_priv->stats->start_tick = jiffies;
2474 + dbgPrint("Started the network queue for %s.\n", p_dev->name);
2475 + return(0);
2476 +}
2477 +
2478 +/***************************************************************
2479 + * cpmac_p_dev_disable
2480 + *
2481 + * Returns:
2482 + * An error code.
2483 + * Parms:
2484 + * dev The device structure of the device to
2485 + * close.
2486 + *
2487 + * This function shuts down the adapter.
2488 + *
2489 + **************************************************************/
2490 +int cpmac_p_dev_disable(struct net_device *p_dev)
2491 +{
2492 + int ret_val = 0;
2493 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
2494 + CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
2495 +
2496 + set_bit(0, &p_cpmac_priv->set_to_close);
2497 + set_bit(0, &p_cpmac_priv->non_data_irq_expected);
2498 +
2499 + /* The driver does not re-schedule the tasklet after kill is called. So, this
2500 + should take care of the bug in the kernel. */
2501 + tasklet_kill(&p_cpmac_priv->cpmac_isr.tasklet);
2502 +
2503 + if(cpmac_drv_stop(p_drv_hal, p_cpmac_priv->tx_chan_info,
2504 + p_cpmac_priv->rx_chan_info,
2505 + CHAN_TEARDOWN | FREE_BUFFER | BLOCKING | COMPLETE) == -1)
2506 + {
2507 + ret_val = -1;
2508 + }
2509 + else
2510 + {
2511 + /* hope that the HAL closes down the tick timer.*/
2512 +
2513 + dbgPrint("Device %s Closed.\n", p_dev->name);
2514 + p_cpmac_priv->stats->start_tick = jiffies;
2515 +
2516 + p_cpmac_priv->link_speed = 100000000;
2517 + p_cpmac_priv->link_mode = 1;
2518 + netif_carrier_off(p_dev);
2519 +
2520 +#if defined (CONFIG_MIPS_AVALANCHE_LED)
2521 + avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_LINK_OFF);
2522 +#endif
2523 +
2524 + clear_bit(0, &p_cpmac_priv->non_data_irq_expected);
2525 +
2526 + }
2527 +
2528 + return (ret_val);
2529 +
2530 +} /* cpmac_dev_close */
2531 +
2532 +
2533 +/***************************************************************
2534 + * cpmac_dev_close
2535 + *
2536 + * Returns:
2537 + * An error code.
2538 + * Parms:
2539 + * dev The device structure of the device to
2540 + * close.
2541 + *
2542 + * This function shuts down the adapter.
2543 + *
2544 + **************************************************************/
2545 +static int cpmac_dev_close(struct net_device *p_dev)
2546 +{
2547 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
2548 + CPMAC_ISR_INFO_T *p_isr_cb_param = &p_cpmac_priv->cpmac_isr;
2549 +
2550 + /* inform the upper layers. */
2551 + netif_stop_queue(p_dev);
2552 +
2553 + if(!g_init_enable_flag)
2554 + cpmac_p_dev_disable(p_dev);
2555 + else
2556 + free_irq(p_isr_cb_param->intr, p_isr_cb_param);
2557 +
2558 + MOD_DEC_USE_COUNT;
2559 +
2560 + return(0);
2561 +}
2562 +
2563 +static void cpmac_dev_mcast_set(struct net_device *p_dev)
2564 +{
2565 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
2566 + CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
2567 + CPMAC_ABILITY_INFO_T *p_capability = p_cpmac_priv->ability_info;
2568 + HAL_FUNCTIONS *p_hal_funcs = p_drv_hal->hal_funcs;
2569 + HAL_DEVICE *p_hal_dev = p_drv_hal->hal_dev;
2570 + int val = 1;
2571 + int channel = 0;
2572 +
2573 +#if defined (CONFIG_MIPS_AVALANCHE_LED)
2574 + if(netif_carrier_ok(p_dev))
2575 + avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_LINK_ON);
2576 +#endif
2577 +
2578 + if(p_dev->flags & IFF_PROMISC)
2579 + {
2580 + if(p_capability->promiscous)
2581 + {
2582 + /* multi mode in the HAL, check this */
2583 + val = 0;
2584 + p_hal_funcs->Control(p_hal_dev, pszRX_MULTI_ALL, "Clear", &val);
2585 +
2586 + val = 1;
2587 + /* set the promiscous mode in the HAL */
2588 + p_hal_funcs->Control(p_hal_dev, pszRX_CAF_EN, pszSet, &val);
2589 + p_hal_funcs->Control(p_hal_dev, pszRX_PROM_CH, pszSet, &channel);
2590 +
2591 + dbgPrint("%s set in the Promisc mode.\n", p_dev->name);
2592 + }
2593 + else
2594 + {
2595 + errPrint("%s not configured for Promisc mode.\n", p_dev->name);
2596 + }
2597 + }
2598 + else if(p_dev->flags & IFF_ALLMULTI)
2599 + {
2600 + if(p_capability->all_multi)
2601 + {
2602 + val = 0;
2603 + /* disable the promiscous mode in the HAL */
2604 + p_hal_funcs->Control(p_hal_dev, pszRX_CAF_EN, "Clear", &val);
2605 +
2606 + val = 1;
2607 + /* set the all multi mode in the HAL */
2608 + p_hal_funcs->Control(p_hal_dev, pszRX_MULTI_ALL, pszSet, &val);
2609 + p_hal_funcs->Control(p_hal_dev, pszRX_MULT_CH, pszSet, &channel);
2610 +
2611 + dbgPrint("%s has been set to the ALL_MULTI mode.\n", p_dev->name);
2612 + }
2613 + else
2614 + {
2615 + errPrint("%s not configured for ALL MULTI mode.\n", p_dev->name);
2616 + }
2617 + }
2618 + else if(p_dev->mc_count)
2619 + {
2620 + if(p_capability->multicast)
2621 + {
2622 + struct dev_mc_list *p_dmi = p_dev->mc_list;
2623 + int count;
2624 +
2625 + val = 0;
2626 + /* clear all the previous data, we are going to populate new ones.*/
2627 + p_hal_funcs->Control(p_hal_dev, pszRX_MULTI_ALL, "Clear", &val);
2628 + /* disable the promiscous mode in the HAL */
2629 + p_hal_funcs->Control(p_hal_dev, pszRX_CAF_EN, pszSet, &val);
2630 +
2631 + for(count = 0; count < p_dev->mc_count; count++, p_dmi = p_dmi->next)
2632 + {
2633 + p_hal_funcs->Control(p_hal_dev, "RX_MULTI_SINGLE", "Set", p_dmi->dmi_addr);
2634 + }
2635 +
2636 + dbgPrint("%s configured for %d multicast addresses.\n", p_dev->name, p_dev->mc_count);
2637 + }
2638 + else
2639 + {
2640 + errPrint("%s has not been configuted for multicast handling.\n", p_dev->name);
2641 + }
2642 + }
2643 + else
2644 + {
2645 + val = 0;
2646 + /* clear all the previous data, we are going to populate new ones.*/
2647 + p_hal_funcs->Control(p_hal_dev, pszRX_MULTI_ALL, "Clear", &val);
2648 + /* disable the promiscous mode in the HAL */
2649 + p_hal_funcs->Control(p_hal_dev, pszRX_CAF_EN, pszSet, &val);
2650 + dbgPrint("Dev set to Unicast mode.\n");
2651 + }
2652 +}
2653 +
2654 +static int cpmac_dev_set_mac_addr(struct net_device *p_dev,void * addr)
2655 +{
2656 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
2657 + CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
2658 + HAL_FUNCTIONS *p_hal_funcs = p_drv_hal->hal_funcs;
2659 + HAL_DEVICE *p_hal_dev = p_drv_hal->hal_dev;
2660 + struct sockaddr *sa = addr;
2661 +
2662 + memcpy(p_cpmac_priv->mac_addr,sa->sa_data,p_dev->addr_len);
2663 + memcpy(p_dev->dev_addr,sa->sa_data,p_dev->addr_len);
2664 + p_hal_funcs->Control(p_hal_dev, pszMacAddr, pszSet, p_cpmac_priv->mac_addr);
2665 +
2666 + return 0;
2667 +
2668 +}
2669 +
2670 +/* VLAN is handled by vlan/vconfig support. Here, we just check for the
2671 + * 802.1q configuration of the device and en-queue the packet accordingly.
2672 + * We do not do any 802.1q processing here.
2673 + */
2674 +static int cpmac_dev_tx( struct sk_buff *skb, struct net_device *p_dev)
2675 +{
2676 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
2677 + CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
2678 + int channel = 0;
2679 + int ret_val = 0;
2680 + FRAGLIST send_frag_list[1];
2681 +
2682 +#ifdef CPMAC_8021Q_SUPPORT
2683 + if(skb->len < TCI_END_OFFSET)
2684 + {
2685 + /* Whee, frame shorter than 14 bytes !! We need to copy
2686 + * fragments to understand the frame. Too much work.
2687 + * Hmm, dump it. */
2688 +
2689 + /* Free the buffer */
2690 + goto cpmac_dev_tx_drop_pkt;
2691 + }
2692 +
2693 + /* 802.1p/q stuff */
2694 + if(IS_802_1Q_FRAME(skb->data + TPID_START_OFFSET))
2695 + {
2696 + /* IEEE 802.1q, section 8.8 and section 8.11.9 */
2697 + if(!p_cpmac_priv->enable_802_1q)
2698 + {
2699 + /* free the buffer */
2700 + goto cpmac_dev_tx_drop_pkt;
2701 + }
2702 +
2703 + channel = GET_802_1P_CHAN(p_cpmac_priv->tx_chan_info->opened_chan,
2704 + skb->data[TCI_START_OFFSET]);
2705 +
2706 + }
2707 + /* sending a non 802.1q frame, when configured for 802.1q: dump it.*/
2708 + else if(p_cpmac_priv->enable_802_1q)
2709 + {
2710 + /* free the buffer */
2711 + goto cpmac_dev_tx_drop_pkt;
2712 + }
2713 + else
2714 + {
2715 + ;/* it is the good old non 802.1q */
2716 + }
2717 +#endif
2718 +
2719 + send_frag_list->len = skb->len;
2720 + send_frag_list->data = skb->data;
2721 +
2722 +#ifdef CPMAC_TEST
2723 + xdump(skb->data, skb->len, "send");
2724 +#endif
2725 +
2726 + dma_cache_wback_inv((unsigned long)skb->data, skb->len);
2727 +
2728 + if(p_drv_hal->hal_funcs->Send(p_drv_hal->hal_dev, send_frag_list, 1,
2729 + skb->len, skb, channel) != 0)
2730 + {
2731 + /* code here to stop the queue, when allowing tx timeout, perhaps next release.*/
2732 + p_cpmac_priv->net_dev_stats.tx_errors++;
2733 +#ifndef TI_SLOW_PATH
2734 + /* Free the skb in case of Send return error */
2735 + dev_kfree_skb_any(skb);
2736 + p_cpmac_priv->net_dev_stats.tx_dropped++;
2737 + return 0;
2738 +#endif
2739 + goto cpmac_dev_tx_drop_pkt;
2740 + }
2741 +
2742 +#if defined (CONFIG_MIPS_AVALANCHE_LED)
2743 + avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_TX_ACTIVITY);
2744 +#endif
2745 +
2746 + return(ret_val);
2747 +
2748 +cpmac_dev_tx_drop_pkt:
2749 +
2750 + p_cpmac_priv->net_dev_stats.tx_dropped++;
2751 + ret_val = -1;
2752 + return (ret_val);
2753 +
2754 +} /*cpmac_dev_tx */
2755 +
2756 +
2757 +//------------------------------------------------------------------------------
2758 +// Public functions : Called by outsiders to this file.
2759 +//------------------------------------------------------------------------------
2760 +
2761 +
2762 +void *cpmac_hal_malloc_buffer(unsigned int size, void* mem_base, unsigned int mem_range,
2763 + OS_SETUP *p_os_setup, HAL_RECEIVEINFO *HalReceiveInfo,
2764 + OS_RECEIVEINFO **osReceiveInfo, OS_DEVICE *p_dev)
2765 +{
2766 + CPMAC_RX_CHAN_INFO_T *p_rx_chan_info = (CPMAC_RX_CHAN_INFO_T *)p_os_setup;
2767 + int tot_buf_size = p_rx_chan_info->chan->tot_buf_size;
2768 + int tot_reserve_bytes = p_rx_chan_info->chan->tot_reserve_bytes;
2769 + struct sk_buff *p_skb;
2770 + void *ret_ptr;
2771 +
2772 + /* use TI SKB private pool */
2773 + p_skb = dev_alloc_skb(tot_buf_size);
2774 +
2775 + if(p_skb == NULL)
2776 + {
2777 + errPrint("Failed to allocate skb for %s.\n", ((struct net_device*)p_dev)->name);
2778 + return (NULL);
2779 + }
2780 +
2781 + p_skb->dev = p_dev;
2782 + skb_reserve(p_skb, tot_reserve_bytes);
2783 +
2784 + *osReceiveInfo = p_skb;
2785 +
2786 + ret_ptr = skb_put(p_skb, p_rx_chan_info->chan->buffer_size);
2787 +
2788 + return(ret_ptr);
2789 +}
2790 +
2791 +void cpmac_hal_isr(int irq, void *p_param, struct pt_regs *regs)
2792 +{
2793 + CPMAC_ISR_INFO_T *p_cb_param = (CPMAC_ISR_INFO_T*) p_param;
2794 + CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cb_param->owner;
2795 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_drv_hal->owner;
2796 + int pkts_to_handle = 0;
2797 +
2798 + if(p_cpmac_priv->non_data_irq_expected)
2799 + {
2800 + p_cb_param->hal_isr(p_drv_hal->hal_dev, &pkts_to_handle);
2801 + p_drv_hal->hal_funcs->PacketProcessEnd(p_drv_hal->hal_dev);
2802 + }
2803 + else if(!p_cpmac_priv->set_to_close)
2804 + tasklet_schedule(&((CPMAC_ISR_INFO_T*) p_param)->tasklet);
2805 + else
2806 + ; // back off from doing anything more. We are closing down.
2807 +}
2808 +
2809 +void cpmac_handle_tasklet(unsigned long data)
2810 +{
2811 + CPMAC_ISR_INFO_T *p_cb_param = (CPMAC_ISR_INFO_T*) data;
2812 + CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cb_param->owner;
2813 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_drv_hal->owner;
2814 + int pkts_to_handle;
2815 +
2816 + p_cb_param->hal_isr(p_drv_hal->hal_dev, &pkts_to_handle);
2817 +
2818 + if(test_bit(0, &p_cpmac_priv->non_data_irq_expected) || !pkts_to_handle)
2819 + p_drv_hal->hal_funcs->PacketProcessEnd(p_drv_hal->hal_dev);
2820 + else if(!test_bit(0, &p_cpmac_priv->set_to_close))
2821 + tasklet_schedule(&p_cb_param->tasklet);
2822 + else
2823 + ; // Back off from processing packets we are closing down.
2824 +}
2825 +
2826 +int cpmac_hal_control(OS_DEVICE *p_dev, const char *key,
2827 + const char *action, void *value)
2828 +{
2829 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
2830 + int ret_val = -1;
2831 +
2832 + if(key == NULL)
2833 + {
2834 + dbgPrint("Encountered NULL key.\n");
2835 + return (-1);
2836 + }
2837 +
2838 + if(cpmac_ci_strcmp(key, "Sleep") == 0 && value != NULL)
2839 + {
2840 + unsigned int clocks_per_tick = cpmac_cpu_freq/HZ;
2841 + unsigned int requested_clocks = *(unsigned int*)value;
2842 + unsigned int requested_ticks = (requested_clocks + clocks_per_tick - 1)/clocks_per_tick;
2843 + mdelay(requested_ticks);
2844 + ret_val = 0;
2845 + }
2846 + else if(cpmac_ci_strcmp(key, "StateChange") == 0)
2847 + {
2848 + ret_val = cpmac_p_process_status_ind(p_cpmac_priv);
2849 + }
2850 + else if(cpmac_ci_strcmp(key, "Tick") == 0 && action != NULL)
2851 + {
2852 + if(cpmac_ci_strcmp(action, "Set") == 0 && value != NULL)
2853 + {
2854 + if(*(unsigned int*)value == 0)
2855 + {
2856 + cpmac_p_stop_timer(p_cpmac_priv->timer + TICK_TIMER);
2857 + ret_val = 0;
2858 + }
2859 + else
2860 + {
2861 + unsigned int clocks_per_tick = cpmac_cpu_freq/HZ;
2862 + unsigned int requested_clocks = *(unsigned int*)value;
2863 + unsigned int requested_ticks = (requested_clocks + clocks_per_tick - 1)/clocks_per_tick;
2864 +
2865 + p_cpmac_priv->delay_ticks = requested_ticks; /* save it for re-triggering */
2866 + ret_val = cpmac_p_start_timer(p_cpmac_priv->timer + TICK_TIMER,
2867 + p_cpmac_priv->delay_ticks);
2868 + }
2869 + }
2870 + else if(cpmac_ci_strcmp(action, "Clear") == 0)
2871 + {
2872 + ret_val = cpmac_p_stop_timer(p_cpmac_priv->timer + TICK_TIMER);
2873 + }
2874 + else
2875 + ;
2876 + }
2877 + else if(cpmac_ci_strcmp(key, "MacAddr") == 0 && action != NULL)
2878 + {
2879 + if(cpmac_ci_strcmp(action, "Get") == 0 && value != NULL)
2880 + {
2881 + *(char **)value = p_cpmac_priv->mac_addr;
2882 + ret_val = 0;
2883 + }
2884 + }
2885 + else if(cpmac_ci_strcmp(key, "CpuFreq") == 0)
2886 + {
2887 + if(cpmac_ci_strcmp(action, "Get") == 0 && value != NULL)
2888 + {
2889 + *(unsigned int *)value = cpmac_cpu_freq;
2890 + dbgPrint("Cpu frequency for cpmacs is %u\n",cpmac_cpu_freq);
2891 + ret_val = 0;
2892 + }
2893 + }
2894 + else if(cpmac_ci_strcmp(key, "SioFlush") == 0)
2895 + {
2896 + ret_val = 0;
2897 + dbgPrint("\n");
2898 + }
2899 + else if(cpmac_ci_strcmp(key, "CpmacFrequency") == 0)
2900 + {
2901 + /* For Sangam cpmac clock is off the PBUS */
2902 + /* OS Needs to supply CORRECT frequency */
2903 + if(cpmac_ci_strcmp(action, "Get") == 0 && value != NULL)
2904 + {
2905 + *(unsigned int *)value = avalanche_get_vbus_freq();
2906 + ret_val = 0;
2907 + }
2908 + }
2909 + /* For now, providing back the default values. */
2910 + else if(cpmac_ci_strcmp(key, "MdioClockFrequency") == 0)
2911 + {
2912 + if(cpmac_ci_strcmp(action, "Get") == 0 && value != NULL)
2913 + {
2914 + *(unsigned int *)value = 2200000; /*DEFAULT */
2915 + ret_val = 0;
2916 + }
2917 + }
2918 + /* For now, providing back the default values. */
2919 + else if(cpmac_ci_strcmp(key, "MdioBusFrequency") == 0)
2920 + {
2921 + /* For Sangam MdioBusFreq is off the PBUS */
2922 + if(cpmac_ci_strcmp(action, "Get") == 0 && value != NULL)
2923 + {
2924 + *(unsigned int *)value = avalanche_get_vbus_freq();
2925 + ret_val = 0;
2926 + }
2927 + }
2928 +
2929 +#if 0
2930 +#if defined(CONFIG_AVALANCHE_AUTO_MDIX)
2931 + /* supporting Mdio Mdix switching */
2932 + else if(cpmac_ci_strcmp(key, hcMdioMdixSwitch) == 0)
2933 + {
2934 + /* For Sangam Mdio-switching action should be always "set"*/
2935 + if(cpmac_ci_strcmp(action, hcSet) == 0 && value != NULL )
2936 + {
2937 + unsigned int mdix = *((unsigned int *) value) ;
2938 +
2939 + if(mdix)
2940 + avalanche_set_phy_into_mdix_mode();
2941 +
2942 + else
2943 + avalanche_set_phy_into_mdi_mode();
2944 +
2945 + ret_val = 0;
2946 + }
2947 +
2948 + }
2949 +#endif
2950 +#endif
2951 + else if(cpmac_ci_strcmp(key, hcMdioMdixSwitch) == 0)
2952 + {
2953 + /* For Sangam Mdio-switching action should be always "set"*/
2954 + if(cpmac_ci_strcmp(action, hcSet) == 0 && value != NULL )
2955 + {
2956 + unsigned int mdix = *((unsigned int *) value) ;
2957 +
2958 + avalanche_set_mdix_on_chip(0xa8610000 , mdix ? 1: 0);
2959 +
2960 + ret_val = 0;
2961 + }
2962 +
2963 + }
2964 +
2965 + return(ret_val);
2966 +}
2967 +
2968 +
2969 +int cpmac_hal_receive(OS_DEVICE *p_dev, FRAGLIST *fragList,
2970 + unsigned int fragCount,
2971 + unsigned int packet_size,
2972 + HAL_RECEIVEINFO *hal_receive_info,
2973 + unsigned int mode)
2974 +{
2975 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
2976 + CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
2977 + struct sk_buff *p_skb = fragList[0].OsInfo;
2978 + p_skb->len = fragList[0].len;
2979 +
2980 + /* invalidate the cache. */
2981 + dma_cache_inv((unsigned long)p_skb->data, fragList[0].len);
2982 +#ifdef CPMAC_TEST
2983 + xdump(p_skb->data, p_skb->len, "recv");
2984 +#endif
2985 +#ifdef CPMAC_8021Q_SUPPORT
2986 + /* 802.1q stuff, just does the basic checking here. */
2987 + if(!p_cpmac_priv->enable_802_1q &&
2988 + p_skb->len > TCI_END_OFFSET &&
2989 + IS_802_1Q_FRAME(p_skb->data + TPID_START_OFFSET))
2990 + {
2991 + goto cpmac_hal_recv_frame_mismatch;
2992 + }
2993 +#endif
2994 + if(fragCount > 1)
2995 + {
2996 + int len;
2997 + struct sk_buff *p_temp_skb;
2998 + CPMAC_RX_CHAN_INFO_T *p_rx_chan_info = p_cpmac_priv->rx_chan_info;
2999 + int count;
3000 +
3001 + dbgPrint("Recv: It is multifragment for %s.\n", p_dev->name);
3002 +
3003 + p_skb = dev_alloc_skb(packet_size +
3004 + p_rx_chan_info->chan->tot_reserve_bytes);
3005 + if(p_skb == NULL)
3006 + {
3007 + p_cpmac_priv->net_dev_stats.rx_errors++;
3008 + goto cpmac_hal_recv_alloc_failed;
3009 + }
3010 +
3011 + p_skb->dev = p_dev;
3012 + skb_reserve(p_skb, p_rx_chan_info->chan->tot_reserve_bytes);
3013 +
3014 + for(count = 0; count < fragCount; count++)
3015 + {
3016 + p_temp_skb = fragList[count].OsInfo;
3017 + len = fragList[count].len;
3018 +
3019 + dma_cache_inv((unsigned long)p_temp_skb->data, len);
3020 +
3021 + memcpy(skb_put(p_skb, len), p_temp_skb->data, len);
3022 + dev_kfree_skb_any(p_temp_skb);
3023 + }
3024 + }
3025 +
3026 +
3027 +#if defined(CONFIG_MIPS_AVALANCHE_MARVELL)
3028 + /* Fetch the receiving port information from EGRESS TRAILOR Bytes*/
3029 + p_dev->if_port = (unsigned char)p_skb->data[packet_size -(EGRESS_TRAILOR_LEN-1)] + AVALANCHE_MARVELL_BASE_PORT_ID;
3030 + skb_trim(p_skb, packet_size - EGRESS_TRAILOR_LEN);
3031 +#else
3032 + /* set length & tail */
3033 + skb_trim(p_skb, packet_size);
3034 +#endif
3035 +
3036 +#ifndef TI_SLOW_PATH
3037 + /* TI Optimization: This is NOT required if the ethernet resides below the bridge. But is
3038 + * required only if the ethernet is directly connected to the IP stack. */
3039 + if (p_dev->br_port == NULL)
3040 +#endif
3041 + p_skb->protocol = eth_type_trans(p_skb, p_dev);
3042 +
3043 + netif_rx(p_skb);
3044 +
3045 +#if defined (CONFIG_MIPS_AVALANCHE_LED)
3046 + avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_RX_ACTIVITY);
3047 +#endif
3048 +
3049 + p_cpmac_priv->net_dev_stats.rx_packets++;
3050 + p_cpmac_priv->net_dev_stats.rx_bytes += packet_size;
3051 +
3052 + p_drv_hal->hal_funcs->RxReturn(hal_receive_info,1);
3053 +
3054 + return(0);
3055 +
3056 +cpmac_hal_recv_alloc_failed:
3057 +
3058 +#ifdef CPMAC_8021Q_SUPPORT
3059 +cpmac_hal_recv_frame_mismatch:
3060 +#endif
3061 +
3062 + fragCount--;
3063 +
3064 + do
3065 + {
3066 + dev_kfree_skb_any(fragList[fragCount].OsInfo);
3067 + }
3068 + while(fragCount--);
3069 +
3070 + p_cpmac_priv->net_dev_stats.rx_dropped++;
3071 +
3072 + return(-1);
3073 +} /*cpmac_receive*/
3074 +
3075 +
3076 +void cpmac_hal_tear_down_complete(OS_DEVICE*a, int b, int ch)
3077 +{
3078 + dbgPrint("what to do with this.\n");
3079 +}
3080 +
3081 +
3082 +int cpmac_hal_send_complete(OS_SENDINFO *p_skb)
3083 +{
3084 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_skb->dev->priv;
3085 +
3086 + p_cpmac_priv->net_dev_stats.tx_packets++;
3087 + p_cpmac_priv->net_dev_stats.tx_bytes += p_skb->len;
3088 +
3089 + dev_kfree_skb_any(p_skb);
3090 +
3091 + return(0);
3092 +}
3093 +
3094 +
3095 +int cpmac_reset(CPMAC_PRIVATE_INFO_T *p_cpmac_priv)
3096 +{
3097 + // code here to reset the device/hal. Not now.
3098 +
3099 + netif_wake_queue(p_cpmac_priv->owner);
3100 + return(0);
3101 +}
3102 +
3103 +#ifdef CPMAC_TEST
3104 +
3105 +#define isprint(a) ((a >=' ')&&(a<= '~'))
3106 +void xdump( u_char* cp, int length, char* prefix )
3107 +{
3108 + int col, count;
3109 + u_char prntBuf[120];
3110 + u_char* pBuf = prntBuf;
3111 + count = 0;
3112 + while(count < length){
3113 + pBuf += sprintf( pBuf, "%s", prefix );
3114 + for(col = 0;count + col < length && col < 16; col++){
3115 + if (col != 0 && (col % 4) == 0)
3116 + pBuf += sprintf( pBuf, " " );
3117 + pBuf += sprintf( pBuf, "%02X ", cp[count + col] );
3118 + }
3119 + while(col++ < 16){ /* pad end of buffer with blanks */
3120 + if ((col % 4) == 0)
3121 + sprintf( pBuf, " " );
3122 + pBuf += sprintf( pBuf, " " );
3123 + }
3124 + pBuf += sprintf( pBuf, " " );
3125 + for(col = 0;count + col < length && col < 16; col++){
3126 + if (isprint((int)cp[count + col]))
3127 + pBuf += sprintf( pBuf, "%c", cp[count + col] );
3128 + else
3129 + pBuf += sprintf( pBuf, "." );
3130 + }
3131 + sprintf( pBuf, "\n" );
3132 + // SPrint(prntBuf);
3133 + printk(prntBuf);
3134 + count += col;
3135 + pBuf = prntBuf;
3136 + }
3137 +
3138 +} /* close xdump(... */
3139 +#endif
3140 +
3141 +
3142 +static int __init cpmac_dev_probe(void)
3143 +{
3144 + int retVal = 0;
3145 + int unit;
3146 + int instance_count = CONFIG_MIPS_CPMAC_PORTS;
3147 +
3148 + //cpmac_cpu_freq = avalanche_clkc_get_freq(CLKC_MIPS);
3149 + cpmac_cpu_freq = tnetd73xx_clkc_get_freq(CLKC_MIPS);
3150 +
3151 + build_psp_config();
3152 +
3153 + for(unit = 0; unit < instance_count; unit++)
3154 + {
3155 + struct net_device *p_dev;
3156 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv;
3157 + size_t dev_size;
3158 + int failed;
3159 +
3160 + dev_size = sizeof(struct net_device)
3161 + + sizeof(CPMAC_PRIVATE_INFO_T);
3162 +
3163 +
3164 + if((p_dev = (struct net_device *) kmalloc(dev_size, GFP_KERNEL)) == NULL)
3165 + {
3166 + dbgPrint( "Could not allocate memory for device.\n" );
3167 + retVal = -ENOMEM;
3168 + break;
3169 + }
3170 +
3171 + memset(p_dev, 0, dev_size );
3172 +
3173 + p_dev->priv = p_cpmac_priv
3174 + = (CPMAC_PRIVATE_INFO_T*)(((char *) p_dev) + sizeof(struct net_device));
3175 + p_cpmac_priv->owner = p_dev;
3176 +
3177 + ether_setup(p_dev);
3178 +
3179 + p_cpmac_priv->instance_num = unit;
3180 + p_dev->init = cpmac_dev_init;
3181 +
3182 + g_dev_array[p_cpmac_priv->instance_num] = p_dev;
3183 +
3184 +#if defined CONFIG_MIPS_CPMAC_INIT_BUF_MALLOC
3185 + g_init_enable_flag = 1;
3186 + printk("Cpmac driver is allocating buffer memory at init time.\n");
3187 +#endif
3188 +
3189 + /* This section gives a default value by the number of PHY in order to
3190 + * replace the default MACRO. */
3191 + {
3192 + char *mac_port = prom_getenv("MAC_PORT"); /* Internal: 0, External: 1 */
3193 + if(!mac_port || (0 != strcmp(mac_port, "0"))) {
3194 + printk("Using the MAC with external PHY\n");
3195 + cfg_start_link_speed = _CPMDIO_NOPHY;
3196 + cpmac_max_frame_size = CPMAC_MAX_FRAME_SIZE + 4;
3197 + }
3198 + else {
3199 + printk("Using the MAC with internal PHY\n");
3200 + cfg_start_link_speed = CFG_START_LINK_SPEED;
3201 + cpmac_max_frame_size = CPMAC_MAX_FRAME_SIZE;
3202 + }
3203 + g_cfg_start_link_params = cfg_start_link_speed;
3204 + }
3205 +
3206 + cpmac_p_detect_manual_cfg(cfg_link_speed, cfg_link_mode, cpmac_debug_mode);
3207 +
3208 + failed = register_netdev(p_dev);
3209 + if (failed)
3210 + {
3211 + dbgPrint("Could not register device for inst %d because of reason \
3212 + code %d.\n", unit, failed);
3213 + retVal = -1;
3214 + kfree(p_dev);
3215 + break;
3216 + }
3217 + else
3218 + {
3219 +
3220 + char proc_name[100];
3221 + int proc_category_name_len = 0;
3222 +
3223 + p_cpmac_priv->next_device = last_cpmac_device;
3224 + last_cpmac_device = p_dev;
3225 +
3226 + dbgPrint(" %s irq=%2d io=%04x\n",p_dev->name, (int) p_dev->irq,
3227 + (int) p_dev->base_addr);
3228 +
3229 + strcpy(proc_name, "avalanche/");
3230 + strcat(proc_name, p_dev->name);
3231 + proc_category_name_len = strlen(proc_name);
3232 +
3233 + strcpy(proc_name + proc_category_name_len, "_rfc2665_stats");
3234 + create_proc_read_entry(proc_name,0,NULL,cpmac_p_read_rfc2665_stats, p_dev);
3235 +
3236 + }
3237 + }
3238 +
3239 + if(retVal == 0)
3240 + {
3241 + /* To maintain backward compatibility with NSP. */
3242 + gp_stats_file = create_proc_entry("avalanche/cpmac_stats", 0644, NULL);
3243 + if(gp_stats_file)
3244 + {
3245 + gp_stats_file->read_proc = cpmac_p_read_stats;
3246 + gp_stats_file->write_proc = cpmac_p_write_stats;
3247 + }
3248 + create_proc_read_entry("avalanche/cpmac_link", 0, NULL, cpmac_p_read_link, NULL);
3249 + create_proc_read_entry("avalanche/cpmac_ver", 0, NULL, cpmac_p_get_version, NULL);
3250 +
3251 + }
3252 +
3253 + cpmac_devices_installed = unit;
3254 + dbgPrint("Installed %d cpmac instances.\n", unit);
3255 + return ( (unit >= 0 ) ? 0 : -ENODEV );
3256 +
3257 +} /* init_module */
3258 +
3259 +
3260 +/***************************************************************
3261 + * cleanup_module
3262 + *
3263 + * Returns:
3264 + * Nothing
3265 + * Parms:
3266 + * None
3267 + *
3268 + * Goes through the CpmacDevices list and frees the device
3269 + * structs and memory associated with each device (lists
3270 + * and buffers). It also ureserves the IO port regions
3271 + * associated with this device.
3272 + *
3273 + **************************************************************/
3274 +
3275 +void cpmac_exit(void)
3276 +{
3277 + struct net_device *p_dev;
3278 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv;
3279 +
3280 + while (cpmac_devices_installed)
3281 + {
3282 + char proc_name[100];
3283 + int proc_category_name_len = 0;
3284 +
3285 + p_dev = last_cpmac_device;
3286 + p_cpmac_priv = (CPMAC_PRIVATE_INFO_T *) p_dev->priv;
3287 +
3288 + dbgPrint("Unloading %s irq=%2d io=%04x\n",p_dev->name, (int) p_dev->irq, (int) p_dev->base_addr);
3289 +
3290 + if(g_init_enable_flag)
3291 + cpmac_p_dev_disable(p_dev);
3292 +
3293 + cpmac_drv_cleanup(p_cpmac_priv->drv_hal);
3294 +
3295 +#if defined (CONFIG_MIPS_AVALANCHE_LED)
3296 + avalanche_led_unregister(p_cpmac_priv->led_handle);
3297 +#endif
3298 + strcpy(proc_name, "avalanche/");
3299 + strcat(proc_name, p_dev->name);
3300 + proc_category_name_len = strlen(proc_name);
3301 +
3302 + strcpy(proc_name + proc_category_name_len, "_rfc2665_stats");
3303 + remove_proc_entry(proc_name, NULL);
3304 +
3305 + release_mem_region(p_dev->base_addr, p_cpmac_priv->dev_size);
3306 + unregister_netdev(p_dev);
3307 + last_cpmac_device = p_cpmac_priv->next_device;
3308 +
3309 + kfree(p_cpmac_priv->drv_hal);
3310 + kfree(p_dev);
3311 +
3312 + cpmac_devices_installed--;
3313 + }
3314 +
3315 + if(gp_stats_file)
3316 + remove_proc_entry("avalanche/cpmac_stats", NULL);
3317 +
3318 + remove_proc_entry("avalanche/cpmac_link", NULL);
3319 + remove_proc_entry("avalanche/cpmac_ver", NULL);
3320 +
3321 + psp_config_cleanup();
3322 +}
3323 +
3324 +
3325 +module_init(cpmac_dev_probe);
3326 +module_exit(cpmac_exit);
3327 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpmac.h linux-2.4.30/drivers/net/avalanche_cpmac/cpmac.h
3328 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpmac.h 1970-01-01 02:00:00.000000000 +0200
3329 +++ linux-2.4.30/drivers/net/avalanche_cpmac/cpmac.h 2005-07-08 22:00:13.000000000 +0200
3330 @@ -0,0 +1,379 @@
3331 +/******************************************************************************
3332 + * FILE PURPOSE: CPMAC Linux Network Device Driver Header
3333 + ******************************************************************************
3334 + * FILE NAME: cpmac.h
3335 + *
3336 + * DESCRIPTION: CPMAC Network Device Driver Header
3337 + *
3338 + * REVISION HISTORY:
3339 + * Date Name Details
3340 + *-----------------------------------------------------------------------------
3341 + * 27 Nov 2002 Suraj S Iyer Initial Create.
3342 + * 09 Jun 2003 Suraj S Iyer Preparing for GA.
3343 + *
3344 + * (C) Copyright 2003, Texas Instruments, Inc
3345 + *******************************************************************************/
3346 +
3347 +#ifndef CPMAC_H
3348 +#define CPMAC_H
3349 +
3350 +#include <linux/timer.h>
3351 +#include <linux/netdevice.h>
3352 +#include <asm/semaphore.h>
3353 +#include <linux/ctype.h>
3354 +#include <linux/interrupt.h>
3355 +
3356 +#include "cpmacHalLx.h"
3357 +/*-----------------------------------------------------------------------------
3358 + * Config macros. Use these to config the driver.
3359 + *---------------------------------------------------------------------------*/
3360 +#define CPMAC_MAX_FRAME_SIZE 1518
3361 +
3362 +#if defined(CONFIG_AR7WRD) || defined(CONFIG_AR7WI) || defined(CONFIG_AR7VWI)|| defined(CONFIG_AR7VW)
3363 +#define CFG_RX_NUM_BUF_DESC 64
3364 +#define CFG_RX_NUM_BUF_SERVICE 32
3365 +#else
3366 +#define CFG_RX_NUM_BUF_DESC 16
3367 +#define CFG_RX_NUM_BUF_SERVICE 8
3368 +#endif
3369 +
3370 +#define CFG_RX_BUF_OFFSET 0
3371 +
3372 +#define CFG_TX_NUM_BUF_DESC 128
3373 +#define CFG_TX_NUM_BUF_SERVICE 20
3374 +#define CFG_TX_BUF_OFFSET 0 /* Lets not change this. */
3375 +#define CFG_TX_TIMEOUT 2000 /* ticks*/
3376 +#define CFG_TX_INT_DISABLE 1 /* Disable the Tx Complete interrupt */
3377 +
3378 +#define CFG_JUMBO_FRAMES 1
3379 +#define CFG_SHORT_FRAMES 1
3380 +#define CFG_PROMISCOUS 1
3381 +#define CFG_BROADCAST 1
3382 +#define CFG_MULTICAST 1
3383 +#define CFG_ALL_MULTI (1*(CFG_MULTICAST))
3384 +#define CFG_AUTO_NEGOTIATION 1
3385 +
3386 +#if defined (CONFIG_MIPS_AVALANCHE_MARVELL)
3387 +#define EGRESS_TRAILOR_LEN 4
3388 +#define CFG_START_LINK_SPEED (_CPMDIO_NOPHY)
3389 +#undef CPMAC_MAX_FRAME_SIZE
3390 +#define CPMAC_MAX_FRAME_SIZE (1518 + EGRESS_TRAILOR_LEN)
3391 +#else
3392 +#define CFG_START_LINK_SPEED (_CPMDIO_10 | _CPMDIO_100 | _CPMDIO_HD | _CPMDIO_FD) /* auto nego */
3393 +#endif
3394 +
3395 +#define CFG_LOOP_BACK 1
3396 +#define CFG_TX_FLOW_CNTL 0
3397 +#define CFG_RX_FLOW_CNTL 0
3398 +#define CFG_TX_PACING 0
3399 +#define CFG_RX_PASS_CRC 0
3400 +#define CFG_QOS_802_1Q 0
3401 +#define CFG_TX_NUM_CHAN 1
3402 +
3403 +
3404 +/*-----------------------------------------------------------------------------
3405 + * Private macros.
3406 + *---------------------------------------------------------------------------*/
3407 +#define MAX_TIMER 2
3408 +#define TX_TIMER 0
3409 +#define TICK_TIMER 0
3410 +#define MAX_TX_CHAN 8
3411 +
3412 +#define CPMAC_LINK_OFF 0
3413 +#define CPMAC_LINK_ON 1
3414 +/*#define CPMAC_SPEED_100 2
3415 +#define CPMAC_SPEED_10 3
3416 +#define CPMAC_FULL_DPLX 4
3417 +#define CPMAC_HALF_DPLX 5*/
3418 +#define CPMAC_RX_ACTIVITY 2
3419 +#define CPMAC_TX_ACTIVITY 3
3420 +
3421 +struct cpmac_timer_info;
3422 +
3423 +typedef int (*CPMAC_HAL_ISR_FUNC_T)(HAL_DEVICE*, int*);
3424 +typedef int (*CPMAC_TIMEOUT_CB_T)(struct cpmac_timer_info*);
3425 +
3426 +typedef struct cpmac_ability_info
3427 +{
3428 + int promiscous;
3429 + int broadcast;
3430 + int multicast;
3431 + int all_multi;
3432 + int loop_back;
3433 + int jumbo_frames;
3434 + int short_frames;
3435 + int auto_negotiation;
3436 + int tx_flow_control;
3437 + int rx_flow_control;
3438 + int tx_pacing;
3439 + int link_speed;
3440 + int rx_pass_crc;
3441 + int qos_802_1q;
3442 + int tx_num_chan;
3443 +}
3444 +CPMAC_ABILITY_INFO_T;
3445 +
3446 +#ifdef DEBUG
3447 +typedef struct cpmac_timer_info
3448 +{
3449 + void *owner;
3450 + UINT32 delay_ticks;
3451 + WDOG_ID timer_id;
3452 + UINT32 is_running;
3453 + UINT32 timer_set_at;
3454 + CPMAC_TIMEOUT_CB_T timeout_CB;
3455 +} CPMAC_TIMER_INFO_T;
3456 +
3457 +typedef struct
3458 +{
3459 + void *owner;
3460 + unsigned int num_cl_desc;
3461 + CL_DESC *cl_desc_tbl;
3462 + M_CL_CONFIG *m_cl_blk_config;
3463 + NET_POOL *net_pool;
3464 + CL_POOL_ID clPoolId;
3465 +
3466 +} CPMAC_NET_MEM_INFO_T;
3467 +
3468 +#endif
3469 +
3470 +typedef struct
3471 +{
3472 + void *owner;
3473 + CPMAC_HAL_ISR_FUNC_T hal_isr;
3474 + struct tasklet_struct tasklet;
3475 + int intr;
3476 +
3477 +} CPMAC_ISR_INFO_T;
3478 +
3479 +typedef struct cpmac_chan
3480 +{
3481 + int num_BD;
3482 + int buffer_size;
3483 + int buffer_offset;
3484 + int service_max;
3485 + int state;
3486 + int tot_buf_size;
3487 + int tot_reserve_bytes;
3488 +
3489 +} CPMAC_CHAN_T;
3490 +
3491 +#define CHAN_CLOSE 0
3492 +#define CHAN_OPENED 1
3493 +
3494 +typedef struct
3495 +{
3496 + int cfg_chan;
3497 + int dev_chan;
3498 + int opened_chan;
3499 + CPMAC_CHAN_T chan[1];
3500 + int enable_802_1q;
3501 +
3502 +} CPMAC_RX_CHAN_INFO_T;
3503 +
3504 +typedef struct
3505 +{
3506 + int cfg_chan;
3507 + int dev_chan;
3508 + int opened_chan;
3509 + int tx_int_disable;
3510 + CPMAC_CHAN_T chan[MAX_TX_CHAN];
3511 +
3512 +} CPMAC_TX_CHAN_INFO_T;
3513 +
3514 +
3515 +
3516 +typedef struct
3517 +{
3518 + void *owner;
3519 + HAL_FUNCTIONS *hal_funcs;
3520 + HAL_DEVICE *hal_dev;
3521 + OS_FUNCTIONS *os_funcs;
3522 +// SEM_ID chan_teardown_sem;
3523 + int non_data_irq_expected;
3524 +} CPMAC_DRV_HAL_INFO_T;
3525 +
3526 +
3527 +typedef struct
3528 +{
3529 + unsigned long tx_discards;
3530 + unsigned long rx_discards;
3531 + unsigned long start_tick;
3532 +
3533 +} CPMAC_DRV_STATS_T;
3534 +
3535 +typedef struct
3536 +{
3537 + unsigned long ifInGoodFrames;
3538 + unsigned long ifInBroadcasts;
3539 + unsigned long ifInMulticasts;
3540 + unsigned long ifInPauseFrames;
3541 + unsigned long ifInCRCErrors;
3542 + unsigned long ifInAlignCodeErrors;
3543 + unsigned long ifInOversizedFrames;
3544 + unsigned long ifInJabberFrames;
3545 + unsigned long ifInUndersizedFrames;
3546 + unsigned long ifInFragments;
3547 + unsigned long ifInFilteredFrames;
3548 + unsigned long ifInQosFilteredFrames;
3549 + unsigned long ifInOctets;
3550 + unsigned long ifOutGoodFrames;
3551 + unsigned long ifOutBroadcasts;
3552 + unsigned long ifOutMulticasts;
3553 + unsigned long ifOutPauseFrames;
3554 + unsigned long ifDeferredTransmissions;
3555 + unsigned long ifCollisionFrames;
3556 + unsigned long ifSingleCollisionFrames;
3557 + unsigned long ifMultipleCollisionFrames;
3558 + unsigned long ifExcessiveCollisionFrames;
3559 + unsigned long ifLateCollisions;
3560 + unsigned long ifOutUnderrun;
3561 + unsigned long ifCarrierSenseErrors;
3562 + unsigned long ifOutOctets;
3563 + unsigned long if64OctetFrames;
3564 + unsigned long if65To127OctetFrames;
3565 + unsigned long if128To255OctetFrames;
3566 + unsigned long if256To511OctetFrames;
3567 + unsigned long if512To1023OctetFrames;
3568 + unsigned long if1024ToUPOctetFrames;
3569 + unsigned long ifNetOctets;
3570 + unsigned long ifRxSofOverruns;
3571 + unsigned long ifRxMofOverruns;
3572 + unsigned long ifRxDMAOverruns;
3573 +
3574 +} CPMAC_DEVICE_MIB_T;
3575 +
3576 +
3577 +typedef struct
3578 +{
3579 + void *owner;
3580 + int timer_count;
3581 + int timer_created;
3582 + struct timer_list timer[1];
3583 + CPMAC_DRV_HAL_INFO_T *drv_hal;
3584 + unsigned int num_of_intr;
3585 + CPMAC_ISR_INFO_T cpmac_isr;
3586 + unsigned int link_speed;
3587 + unsigned int link_mode;
3588 + unsigned int enable_802_1q;
3589 + unsigned int timer_access_hal;
3590 + unsigned int loop_back;
3591 + CPMAC_RX_CHAN_INFO_T *rx_chan_info;
3592 + CPMAC_TX_CHAN_INFO_T *tx_chan_info;
3593 + CPMAC_ABILITY_INFO_T *ability_info;
3594 + CPMAC_DEVICE_MIB_T *device_mib;
3595 + CPMAC_DRV_STATS_T *stats;
3596 + unsigned int flags;
3597 + unsigned int delay_ticks;
3598 + char mac_addr[6];
3599 + struct net_device_stats net_dev_stats;
3600 +// rwlock_t rw_lock;
3601 + int set_to_close;
3602 + struct net_device *next_device;
3603 + unsigned int instance_num;
3604 + unsigned int non_data_irq_expected;
3605 + unsigned long dev_size;
3606 + void* led_handle;
3607 +} CPMAC_PRIVATE_INFO_T;
3608 +
3609 +
3610 +/* Private flags */
3611 +
3612 +/* bit 0 to 31, bit 32 is used to indicate set or reset */
3613 +
3614 +#define IFF_PRIV_SHORT_FRAMES 0x00010000
3615 +#define IFF_PRIV_JUMBO_FRAMES 0x00020000
3616 +#define IFF_PRIV_AUTOSPEED 0x00080000
3617 +#define IFF_PRIV_LINK10_HD 0x00100000
3618 +#define IFF_PRIV_LINK10_FD 0x00200000
3619 +#define IFF_PRIV_LINK100_HD 0x00400000
3620 +#define IFF_PRIV_LINK100_FD 0x00800000
3621 +#define IFF_PRIV_8021Q_EN 0x01000000
3622 +#define IFF_PRIV_NUM_TX_CHAN 0x02000000
3623 +#define IFF_PRIV_TX_FLOW_CNTL 0x04000000
3624 +#define IFF_PRIV_RX_FLOW_CNTL 0x08000000
3625 +#define IFF_PRIV_TX_PACING 0x10000000
3626 +#define IFF_PRIV_RX_PASS_CRC 0x20000000
3627 +
3628 +#define PRIVCSFLAGS 0x200
3629 +#define PRIVCGFLAGS 0x201
3630 +
3631 +
3632 +#define BLOCKING 1
3633 +#define CHAN_TEARDOWN 2
3634 +#define CHAN_SETUP 4
3635 +#define COMPLETE 8
3636 +#define FREE_BUFFER 16
3637 +
3638 +
3639 +static const char pszStats0[] = "Stats0";
3640 +static const char pszStats1[] = "Stats1";
3641 +static const char pszStats2[] = "Stats2";
3642 +static const char pszStats3[] = "Stats3";
3643 +static const char pszStats4[] = "Stats4";
3644 +static const char pszStatsDump[] = "StatsDump";
3645 +static const char pszStatsClear[] = "StatsClear";
3646 +static const char pszRX_PASS_CRC[] = "RX_PASS_CRC";
3647 +static const char pszRX_QOS_EN[] = "RX_QOS_EN";
3648 +static const char pszRX_NO_CHAIN[] = "RX_NO_CHAIN";
3649 +static const char pszRX_CMF_EN[] = "RX_CMF_EN";
3650 +static const char pszRX_CSF_EN[] = "RX_CSF_EN";
3651 +static const char pszRX_CEF_EN[] = "RX_CEF_EN";
3652 +static const char pszRX_CAF_EN[] = "RX_CAF_EN";
3653 +static const char pszRX_PROM_CH[] = "RX_PROM_CH";
3654 +static const char pszRX_BROAD_EN[] = "RX_BROAD_EN";
3655 +static const char pszRX_BROAD_CH[] = "RX_BROAD_CH";
3656 +static const char pszRX_MULT_EN[] = "RX_MULT_EN";
3657 +static const char pszRX_MULT_CH[] = "RX_MULT_CH";
3658 +static const char pszTX_PTYPE[] = "TX_PTYPE";
3659 +static const char pszTX_PACE[] = "TX_PACE";
3660 +static const char pszMII_EN[] = "MII_EN";
3661 +static const char pszTX_FLOW_EN[] = "TX_FLOW_EN";
3662 +static const char pszRX_FLOW_EN[] = "RX_FLOW_EN";
3663 +static const char pszRX_MAXLEN[] = "RX_MAXLEN";
3664 +static const char pszRX_FILTERLOWTHRESH[] = "RX_FILTERLOWTHRESH";
3665 +static const char pszRX0_FLOWTHRESH[] = "RX0_FLOWTHRESH";
3666 +static const char pszRX_UNICAST_SET[] = "RX_UNICAST_SET";
3667 +static const char pszRX_UNICAST_CLEAR[] = "RX_UNICAST_CLEAR";
3668 +static const char pszMdioConnect[] = "MdioConnect";
3669 +static const char pszMacAddr[] = "MacAddr";
3670 +static const char pszTick[] = "Tick";
3671 +static const char pszRX_MULTICAST[] = "RX_MULTICAST";
3672 +static const char pszRX_MULTI_ALL[] = "RX_MULTI_ALL";
3673 +static const char pszRX_MULTI_SINGLE[] = "RX_MULTI_SINGLE";
3674 +
3675 +static const char pszSet[] = "Set";
3676 +static const char pszGet[] = "Get";
3677 +static const char pszClear[] = "Clear";
3678 +
3679 +
3680 +void *cpmac_hal_malloc_buffer(unsigned int size, void *MemBase, unsigned int MemRange,
3681 + HAL_DEVICE *HalDev, HAL_RECEIVEINFO *HalReceiveInfo,
3682 + OS_RECEIVEINFO **OsReceiveInfo, OS_DEVICE *OsDev);
3683 +
3684 +void cpmac_hal_tear_down_complete(OS_DEVICE*, int, int);
3685 +int cpmac_hal_control(OS_DEVICE *p_END_obj, const char *key,
3686 + const char *action, void *value);
3687 +int cpmac_hal_receive(OS_DEVICE *p_END_obj, FRAGLIST *fragList,
3688 + unsigned int FragCount, unsigned int pkt_len,
3689 + HAL_RECEIVEINFO *halReceiveInfo,
3690 + unsigned int mode);
3691 +int cpmac_hal_send_complete(OS_SENDINFO*);
3692 +
3693 +void cpmac_hal_isr(int irq, void *p_param, struct pt_regs *p_cb_param);
3694 +void cpmac_handle_tasklet(unsigned long data);
3695 +
3696 +inline static int cpmac_ci_strcmp(const char *s1, const char *s2)
3697 +{
3698 + while(*s1 && *s2)
3699 + {
3700 + if(tolower(*s1) != tolower(*s2))
3701 + break;
3702 + s1++;
3703 + s2++;
3704 + }
3705 +
3706 + return(tolower(*s1) - tolower(*s2));
3707 +}
3708 +
3709 +#endif
3710 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpmacHalLx.c linux-2.4.30/drivers/net/avalanche_cpmac/cpmacHalLx.c
3711 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpmacHalLx.c 1970-01-01 02:00:00.000000000 +0200
3712 +++ linux-2.4.30/drivers/net/avalanche_cpmac/cpmacHalLx.c 2005-04-15 05:10:41.000000000 +0200
3713 @@ -0,0 +1,492 @@
3714 +/******************************************************************************
3715 + * FILE PURPOSE: CPMAC Net Driver HAL support Source
3716 + ******************************************************************************
3717 + * FILE NAME: cpmacHalLx.c
3718 + *
3719 + * DESCRIPTION: CPMAC Network Device Driver Source
3720 + *
3721 + * REVISION HISTORY:
3722 + *
3723 + * Date Description Author
3724 + *-----------------------------------------------------------------------------
3725 + * 27 Nov 2002 Initial Creation Suraj S Iyer
3726 + * 09 Jun 2003 Updates for GA Suraj S Iyer
3727 + * 18 Dec 2003 Updated for 5.7 Suraj S Iyer
3728 + *
3729 + * (C) Copyright 2003, Texas Instruments, Inc
3730 + *******************************************************************************/
3731 +#include <linux/kernel.h>
3732 +#include <linux/module.h>
3733 +#include <linux/init.h>
3734 +#include <linux/netdevice.h>
3735 +#include <linux/etherdevice.h>
3736 +#include <linux/delay.h>
3737 +#include <linux/spinlock.h>
3738 +#include <linux/proc_fs.h>
3739 +#include <asm/io.h>
3740 +#include <linux/string.h>
3741 +
3742 +#include "cpmacHalLx.h"
3743 +#include "cpmac.h"
3744 +
3745 +/* PSP config headers */
3746 +#include "psp_config_parse.h"
3747 +#include "psp_config_mgr.h"
3748 +
3749 +/* Probe Debug Section*/
3750 +
3751 +/* debug */
3752 +extern int cpmac_debug_mode;
3753 +#define dbgPrint if (cpmac_debug_mode) printk
3754 +#define errPrint printk
3755 +
3756 +char CpmacSignature[] = "Cpmac driver";
3757 +static unsigned long irq_flags = 0;
3758 +OS_SETUP *p_os_setup = NULL;
3759 +
3760 +extern int avalanche_request_intr_pacing(int, unsigned int, unsigned int);
3761 +extern int avalanche_free_intr_pacing(unsigned int blk_num);
3762 +
3763 +/*----------------------------------------------------------------------------
3764 + * Parameter extracting functionalities.
3765 + *--------------------------------------------------------------------------*/
3766 +static int os_find_parm_u_int(void *info_ptr, const char *param, unsigned int *val)
3767 +{
3768 + int ret_val = 0;
3769 +
3770 + if((ret_val = psp_config_get_param_uint(info_ptr, param, val)) == -1)
3771 + {
3772 + dbgPrint("Error: could not locate the requested \"%s\" param.\n",param);
3773 + ret_val = -1;
3774 + }
3775 +
3776 + return(ret_val);
3777 +}
3778 +
3779 +static int os_find_parm_val(void *info_ptr, const char *param, void *val)
3780 +{
3781 + int ret_val = 0;
3782 +
3783 + if(psp_config_get_param_string(info_ptr, param, val) == -1)
3784 + {
3785 + dbgPrint("Error: could not locate the requested \"%s\" param.\n",param);
3786 + ret_val = -1;
3787 + }
3788 +
3789 + return(ret_val);
3790 +}
3791 +
3792 +static int os_find_device(int unit, const char *find_name, void *device_info)
3793 +{
3794 + int ret_val = 0;
3795 +
3796 + if(psp_config_get((char *)find_name, unit, device_info) == -1)
3797 + {
3798 + dbgPrint("Error: could not locate the requested \"%s\" param.\n", find_name);
3799 + ret_val = -1;
3800 + }
3801 +
3802 + return(ret_val);
3803 +}
3804 +
3805 +/*---------------------------------------------------------------------------
3806 + * Memory related OS abstraction.
3807 + *--------------------------------------------------------------------------*/
3808 +void os_free(void *mem_ptr)
3809 +{
3810 + kfree(mem_ptr);
3811 +}
3812 +
3813 +void os_free_buffer(OS_RECEIVEINFO *osReceiveInfo, void *mem_ptr)
3814 +{
3815 + dev_kfree_skb_any(osReceiveInfo);
3816 +}
3817 +
3818 +void os_free_dev(void *mem_ptr)
3819 +{
3820 + kfree(mem_ptr);
3821 +}
3822 +
3823 +void os_free_dma_xfer(void *mem_ptr)
3824 +{
3825 + kfree(mem_ptr);
3826 +}
3827 +
3828 +static void *os_malloc(unsigned int size)
3829 +{
3830 + return(kmalloc(size, GFP_KERNEL));
3831 +}
3832 +
3833 +static void *os_malloc_dma_xfer(unsigned int size,
3834 + void *mem_base,
3835 + unsigned int mem_range)
3836 +{
3837 + return(kmalloc(size, GFP_KERNEL));
3838 +}
3839 +
3840 +static void *os_malloc_dev(unsigned int size)
3841 +{
3842 + return(kmalloc(size, GFP_KERNEL));
3843 +}
3844 +
3845 +
3846 +/*----------------------------------------------------------------------------
3847 + * CRITICAL SECTION ENABLING/DISABLING.
3848 + *--------------------------------------------------------------------------*/
3849 +static void os_critical_on(void)
3850 +{
3851 + save_and_cli(irq_flags);
3852 +}
3853 +
3854 +static void os_critical_off(void)
3855 +{
3856 + restore_flags(irq_flags);
3857 +}
3858 +
3859 +/*----------------------------------------------------------------------------
3860 + * Cache related abstraction
3861 + *--------------------------------------------------------------------------*/
3862 +static void os_cache_invalidate(void *mem_ptr, int size)
3863 +{
3864 + dma_cache_inv((unsigned long)mem_ptr, size);
3865 +}
3866 +
3867 +static void os_cache_writeback(void *mem_ptr, int size)
3868 +{
3869 + dma_cache_wback_inv((unsigned long)mem_ptr, size);
3870 +}
3871 +
3872 +/*-----------------------------------------------------------------------------
3873 + * Support functions.
3874 + *---------------------------------------------------------------------------*/
3875 +
3876 +static void hal_drv_unregister_isr(OS_DEVICE *p_dev, int intr)
3877 +{
3878 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
3879 + CPMAC_ISR_INFO_T *p_isr_cb_param = &p_cpmac_priv->cpmac_isr;
3880 + intr = LNXINTNUM(intr);
3881 +
3882 + free_irq(p_isr_cb_param->intr, p_isr_cb_param);
3883 +
3884 + dbgPrint("cpmac_hal_unregister called for the intr %d for unit %x and isr_cb_param %x.\n",
3885 + intr, p_cpmac_priv->instance_num, (unsigned int )&p_cpmac_priv->cpmac_isr);
3886 +}
3887 +
3888 +
3889 +static void hal_drv_register_isr(OS_DEVICE *p_dev,
3890 + CPMAC_HAL_ISR_FUNC_T hal_isr, int intr)
3891 +{
3892 + CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
3893 + CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
3894 + CPMAC_ISR_INFO_T *p_isr_cb_param = &p_cpmac_priv->cpmac_isr;
3895 + intr = LNXINTNUM(intr);
3896 +
3897 + dbgPrint("osRegister called for the intr %d for device %x and p_isr_cb_param %x.\n",
3898 + intr, (bit32u)p_dev, (bit32u)p_isr_cb_param);
3899 +
3900 + p_isr_cb_param->owner = p_drv_hal;
3901 + p_isr_cb_param->hal_isr = hal_isr;
3902 + p_isr_cb_param->intr = intr;
3903 +
3904 + tasklet_init(&p_isr_cb_param->tasklet, cpmac_handle_tasklet, (unsigned long)p_isr_cb_param);
3905 + dbgPrint("Success in registering irq %d for Cpmac unit# %d.\n", intr, p_cpmac_priv->instance_num);
3906 +}
3907 +
3908 +/*---------------------------------------------------------------------------
3909 + * FUNCTIONS called by the CPMAC Net Device.
3910 + *-------------------------------------------------------------------------*/
3911 +static int load_os_funcs(OS_FUNCTIONS *os_func)
3912 +{
3913 + dbgPrint("os_init_module: Start\n");
3914 + if( os_func == 0 )
3915 + {
3916 + return(sizeof(OS_FUNCTIONS));
3917 + }
3918 +
3919 + os_func->Control = cpmac_hal_control;
3920 + os_func->CriticalOn = os_critical_on;
3921 + os_func->CriticalOff = os_critical_off;
3922 + os_func->DataCacheHitInvalidate = os_cache_invalidate;
3923 + os_func->DataCacheHitWriteback = os_cache_writeback;
3924 + os_func->DeviceFindInfo = os_find_device;
3925 + os_func->DeviceFindParmUint = os_find_parm_u_int;
3926 + os_func->DeviceFindParmValue= os_find_parm_val;
3927 + os_func->Free = os_free;
3928 + os_func->FreeRxBuffer = os_free_buffer;
3929 + os_func->FreeDev = os_free_dev;
3930 + os_func->FreeDmaXfer = os_free_dma_xfer;
3931 + os_func->IsrRegister = hal_drv_register_isr;
3932 + os_func->IsrUnRegister = hal_drv_unregister_isr;
3933 + os_func->Malloc = os_malloc;
3934 + os_func->MallocDev = os_malloc_dev;
3935 + os_func->MallocDmaXfer = os_malloc_dma_xfer;
3936 + os_func->MallocRxBuffer = cpmac_hal_malloc_buffer;
3937 + os_func->Memset = memset;
3938 + os_func->Printf = printk;
3939 + os_func->Receive = cpmac_hal_receive;
3940 + os_func->SendComplete = cpmac_hal_send_complete;
3941 + os_func->Strcmpi = cpmac_ci_strcmp;
3942 + os_func->TeardownComplete = cpmac_hal_tear_down_complete;
3943 + os_func->Strstr = strstr;
3944 + os_func->Strtoul = simple_strtol;
3945 + os_func->Sprintf = sprintf;
3946 + os_func->Strlen = strlen;
3947 +
3948 + dbgPrint("os_init_module: Leave\n");
3949 +
3950 + return(0);
3951 +}
3952 +
3953 +
3954 +int cpmac_drv_init(CPMAC_DRV_HAL_INFO_T *p_drv_hal)
3955 +{
3956 + HAL_DEVICE *p_hal_dev = p_drv_hal->hal_dev;
3957 + HAL_FUNCTIONS *p_hal_funcs = p_drv_hal->hal_funcs;
3958 +
3959 + return(p_hal_funcs->Init(p_hal_dev));
3960 +}
3961 +
3962 +int cpmac_drv_cleanup(CPMAC_DRV_HAL_INFO_T *p_drv_hal)
3963 +{
3964 + HAL_DEVICE *p_hal_dev = p_drv_hal->hal_dev;
3965 + HAL_FUNCTIONS *p_hal_funcs = p_drv_hal->hal_funcs;
3966 +
3967 + int ret_val = p_hal_funcs->Shutdown(p_hal_dev);
3968 +
3969 +#if 0
3970 + if(ret_val == 0)
3971 + kfree(p_hal_funcs);
3972 + else
3973 + ret_val = -1;
3974 +#endif
3975 +
3976 + kfree(p_drv_hal->os_funcs);
3977 +
3978 + return (ret_val);
3979 +}
3980 +
3981 +int cpmac_drv_tx_setup(HAL_FUNCTIONS *p_hal_funcs,
3982 + HAL_DEVICE *p_hal_dev,
3983 + CPMAC_TX_CHAN_INFO_T *p_tx_chan_info)
3984 +{
3985 + int ret_val = 0;
3986 + int count = 0;
3987 + CHANNEL_INFO chan_info;
3988 +
3989 + /* Let's setup the TX Channels. */
3990 + for(count=0; count < p_tx_chan_info->cfg_chan; count++)
3991 + {
3992 + chan_info.Channel = count;
3993 + chan_info.Direction = DIRECTION_TX;
3994 + chan_info.TxNumBuffers = p_tx_chan_info->chan[count].num_BD;
3995 + chan_info.TxServiceMax = p_tx_chan_info->chan[count].service_max;
3996 + chan_info.TxNumQueues = 0;
3997 +
3998 + if((ret_val = p_hal_funcs->ChannelSetup(p_hal_dev, &chan_info,
3999 + NULL)) != 0)
4000 + {
4001 + errPrint("Error in opening channel %d for TX.\n", count);
4002 + ret_val = -1;
4003 + break;
4004 + }
4005 +
4006 + p_tx_chan_info->opened_chan++;
4007 + }
4008 +
4009 + return(ret_val);
4010 +}
4011 +
4012 +int cpmac_drv_rx_setup(HAL_FUNCTIONS *p_hal_funcs,
4013 + HAL_DEVICE *p_hal_dev,
4014 + CPMAC_RX_CHAN_INFO_T *p_rx_chan_info)
4015 +{
4016 + int ret_val = 0;
4017 + CHANNEL_INFO chan_info;
4018 +
4019 + chan_info.Channel = 0;
4020 + chan_info.Direction = DIRECTION_RX;
4021 + chan_info.RxBufSize = p_rx_chan_info->chan[0].buffer_size;
4022 + chan_info.RxBufferOffset= p_rx_chan_info->chan[0].buffer_offset;
4023 + chan_info.RxNumBuffers = p_rx_chan_info->chan[0].num_BD;
4024 + chan_info.RxServiceMax = p_rx_chan_info->chan[0].service_max;
4025 +
4026 + if(p_hal_funcs->ChannelSetup(p_hal_dev, &chan_info, p_rx_chan_info) != 0)
4027 + {
4028 + errPrint("Error in opening channel %d for RX.\n", 0);
4029 + ret_val = -1;
4030 + }
4031 +
4032 + return(ret_val);
4033 +}
4034 +
4035 +int cpmac_drv_start(CPMAC_DRV_HAL_INFO_T *p_drv_hal,
4036 + CPMAC_TX_CHAN_INFO_T *p_tx_chan_info,
4037 + CPMAC_RX_CHAN_INFO_T *p_rx_chan_info,
4038 + unsigned int flags)
4039 +{
4040 + int ret_val = 0;
4041 + HAL_FUNCTIONS *p_hal_funcs = p_drv_hal->hal_funcs;
4042 + HAL_DEVICE *p_hal_dev = p_drv_hal->hal_dev;
4043 +
4044 + dbgPrint("It is in cpmac_drv_start for %x.\n", (unsigned int)p_drv_hal);
4045 +
4046 + if(flags & CHAN_SETUP)
4047 + {
4048 + if(cpmac_drv_tx_setup(p_hal_funcs, p_hal_dev,
4049 + p_tx_chan_info)!=0)
4050 + {
4051 + errPrint("Failed to set up tx channel(s).\n");
4052 + ret_val = -1;
4053 + }
4054 + else if(cpmac_drv_rx_setup(p_hal_funcs, p_hal_dev,
4055 + p_rx_chan_info)!=0)
4056 + {
4057 + errPrint("Failed to set up rx channel.\n");
4058 + ret_val = -1;
4059 + }
4060 + else
4061 + {
4062 + ret_val = 0;
4063 + }
4064 + }
4065 +
4066 + /* Error in setting up the Channels, quit. */
4067 + if((ret_val == 0) && (ret_val = p_hal_funcs->Open(p_hal_dev)) != 0)
4068 + {
4069 + errPrint("failed to open the HAL!!!.\n");
4070 + ret_val = -1;
4071 + }
4072 +
4073 + return (ret_val);
4074 +} /* cpmac_drv_start */
4075 +
4076 +
4077 +
4078 +int cpmac_drv_tx_teardown(HAL_FUNCTIONS *p_hal_funcs,
4079 + HAL_DEVICE *p_hal_dev,
4080 + CPMAC_TX_CHAN_INFO_T *p_tx_chan_info,
4081 + unsigned int flags)
4082 +{
4083 + int ret_val = 0;
4084 + int count = 0;
4085 +
4086 + /* Let's setup the TX Channels. */
4087 + for(; p_tx_chan_info->opened_chan > 0;
4088 + p_tx_chan_info->opened_chan--, count++)
4089 + {
4090 + if(p_hal_funcs->ChannelTeardown(p_hal_dev, count, flags) != 0)
4091 + {
4092 + errPrint("Error in tearing down channel %d for TX.\n", count);
4093 + ret_val = -1;
4094 + break;
4095 + }
4096 + }
4097 +
4098 + return(ret_val);
4099 +}
4100 +
4101 +
4102 +int cpmac_drv_rx_teardown(HAL_FUNCTIONS *p_hal_funcs,
4103 + HAL_DEVICE *p_hal_dev,
4104 + unsigned int flags)
4105 +{
4106 + int ret_val = 0;
4107 +
4108 + if(p_hal_funcs->ChannelTeardown(p_hal_dev, 0, flags) != 0)
4109 + {
4110 + errPrint("Error in tearing down channel %d for RX.\n", 0);
4111 + ret_val = -1;
4112 + }
4113 +
4114 + return(ret_val);
4115 +}
4116 +
4117 +int cpmac_drv_stop(CPMAC_DRV_HAL_INFO_T *p_drv_hal,
4118 + CPMAC_TX_CHAN_INFO_T *p_tx_chan_info,
4119 + CPMAC_RX_CHAN_INFO_T *p_rx_chan_info,
4120 + unsigned int flags)
4121 +{
4122 + HAL_DEVICE *p_hal_dev = p_drv_hal->hal_dev;
4123 + HAL_FUNCTIONS *p_hal_funcs = p_drv_hal->hal_funcs;
4124 + int ret_val = 0;
4125 +
4126 + if(flags & CHAN_TEARDOWN)
4127 + {
4128 + unsigned int chan_flags = 0;
4129 +
4130 + if(flags & FREE_BUFFER) chan_flags |= 0x4; /* full tear down */
4131 + if(flags & BLOCKING) chan_flags |= 0x8; /* blocking call */
4132 +
4133 + dbgPrint("The teardown flags are %d.\n", flags);
4134 + dbgPrint("The teardown chan flags are %d.\n", chan_flags);
4135 +
4136 + if(cpmac_drv_tx_teardown(p_hal_funcs, p_hal_dev,
4137 + p_tx_chan_info, chan_flags | 0x1) != 0)
4138 + {
4139 + ret_val = -1;
4140 + errPrint("The tx channel teardown failed.\n");
4141 + }
4142 + else if(cpmac_drv_rx_teardown(p_hal_funcs, p_hal_dev, chan_flags | 0x2) != 0)
4143 + {
4144 + ret_val = -1;
4145 + errPrint("The rx channel teardown failed.\n");
4146 + }
4147 + else
4148 + {
4149 + ;
4150 + }
4151 + }
4152 +
4153 + if(ret_val == 0)
4154 + {
4155 + int close_flags = 1;
4156 +
4157 + if(flags & FREE_BUFFER) close_flags = 2;
4158 +// if(flags & COMPLETE) close_flags = 3;
4159 +
4160 + if(p_hal_funcs->Close(p_hal_dev, close_flags) != 0)
4161 + {
4162 + ret_val = -1;
4163 + }
4164 + }
4165 +
4166 + return(ret_val);
4167 +}
4168 +
4169 +int cpmac_drv_init_module(CPMAC_DRV_HAL_INFO_T *p_drv_hal, OS_DEVICE *p_os_dev, int inst)
4170 +{
4171 + int ret_val = -1;
4172 + int hal_func_size;
4173 +
4174 + dbgPrint("Entering the CpmacInitModule for the inst %d \n", inst);
4175 +
4176 + if((p_drv_hal->os_funcs = kmalloc(sizeof(OS_FUNCTIONS), GFP_KERNEL)) == NULL)
4177 + {
4178 + errPrint("Failed to allocate memory for OS_FUNCTIONS.\n");
4179 + }
4180 + else if(load_os_funcs(p_drv_hal->os_funcs) != 0)
4181 + {
4182 + errPrint("Failed to load OS funcs.\n");
4183 + os_free(p_drv_hal->os_funcs);
4184 + }
4185 + else if(halCpmacInitModule(&p_drv_hal->hal_dev, p_os_dev,
4186 + &p_drv_hal->hal_funcs, p_drv_hal->os_funcs,
4187 + sizeof(*p_drv_hal->os_funcs),
4188 + &hal_func_size, inst) != 0)
4189 + {
4190 + errPrint("halCpmacInitModule failed for inst %d \n", inst);
4191 + os_free(p_drv_hal->os_funcs);
4192 + }
4193 + else if(p_drv_hal->hal_funcs->Probe(p_drv_hal->hal_dev) != 0)
4194 + {
4195 + errPrint("halCpmacProbe failed for inst %d \n", inst);
4196 + os_free(p_drv_hal->os_funcs);
4197 + }
4198 + else
4199 + {
4200 + /* every thing went well. */
4201 + ret_val = 0;
4202 + }
4203 +
4204 + return (ret_val);
4205 +}
4206 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpmacHalLx.h linux-2.4.30/drivers/net/avalanche_cpmac/cpmacHalLx.h
4207 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpmacHalLx.h 1970-01-01 02:00:00.000000000 +0200
4208 +++ linux-2.4.30/drivers/net/avalanche_cpmac/cpmacHalLx.h 2005-07-08 22:00:13.000000000 +0200
4209 @@ -0,0 +1,51 @@
4210 +/******************************************************************************
4211 + * FILE PURPOSE: CPMAC Linux Device Driver HAL support Header
4212 + ******************************************************************************
4213 + * FILE NAME: cpmacHalVx.h
4214 + *
4215 + * DESCRIPTION: CPMAC Linux Device Driver Header
4216 + *
4217 + * REVISION HISTORY:
4218 + *
4219 + * Date Description Author
4220 + *-----------------------------------------------------------------------------
4221 + * 27 Nov 2002 Initial Creation Suraj S Iyer
4222 + * 09 Jun 2003 Updates for GA Suraj S Iyer
4223 + *
4224 + * (C) Copyright 2002, Texas Instruments, Inc
4225 + *******************************************************************************/
4226 +
4227 +#ifndef __CPMAC_HAL_LX_H
4228 +#define __CPMAC_HAL_LX_H
4229 +
4230 +
4231 +typedef struct net_device OS_DEVICE;
4232 +typedef struct sk_buff OS_RECEIVEINFO;
4233 +typedef struct sk_buff OS_SENDINFO;
4234 +
4235 +#ifdef DEBUG
4236 +typedef void HAL_RECEIVEINFO;
4237 +typedef void HAL_DEVICE;
4238 +typedef void OS_SETUP;
4239 +#endif
4240 +
4241 +#define OS_SETUP void
4242 +#define HAL_DEVICE void
4243 +#define HAL_RECEIVEINFO void
4244 +
4245 +#define _CPHAL_CPMAC
4246 +
4247 +#include "cpswhal_cpmac.h"
4248 +#include "cpmac.h"
4249 +
4250 +int cpmac_drv_start(CPMAC_DRV_HAL_INFO_T *, CPMAC_TX_CHAN_INFO_T*,
4251 + CPMAC_RX_CHAN_INFO_T *, unsigned int);
4252 +int cpmac_drv_cleanup(CPMAC_DRV_HAL_INFO_T *);
4253 +int cpmac_drv_init(CPMAC_DRV_HAL_INFO_T*);
4254 +int cpmac_drv_close(CPMAC_DRV_HAL_INFO_T*);
4255 +int cpmac_drv_open(CPMAC_DRV_HAL_INFO_T*);
4256 +int cpmac_drv_init_module(CPMAC_DRV_HAL_INFO_T*, OS_DEVICE*, int);
4257 +int cpmac_drv_stop(CPMAC_DRV_HAL_INFO_T *p_drv_hal,CPMAC_TX_CHAN_INFO_T *p_tx_chan_info,
4258 + CPMAC_RX_CHAN_INFO_T *p_rx_chan_info,unsigned int flags);
4259 +
4260 +#endif
4261 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpmac_reg.h linux-2.4.30/drivers/net/avalanche_cpmac/cpmac_reg.h
4262 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpmac_reg.h 1970-01-01 02:00:00.000000000 +0200
4263 +++ linux-2.4.30/drivers/net/avalanche_cpmac/cpmac_reg.h 2005-07-08 22:08:52.149427385 +0200
4264 @@ -0,0 +1,406 @@
4265 +/****************************************************************************
4266 + TNETD73xx Software Support
4267 + Copyright(c) 2000, Texas Instruments Incorporated. All Rights Reserved.
4268 +
4269 + FILE: cpmac_reg.h Register definitions for the CPMAC module
4270 +
4271 + DESCRIPTION:
4272 + This include file contains register definitions for the
4273 + CPMAC module.
4274 +
4275 + HISTORY:
4276 + 15Nov00 BEGR Original version written
4277 + 30May02 MICK Added bits for Int Vector
4278 + 19Sep02 MICK Added INT_ACK per Channel
4279 + 08Nov02 GDUN Updated to use base
4280 + 12Nov02 MICK Incorporated into CPHAL
4281 +*****************************************************************************/
4282 +#ifndef _INC_CPMAC_REG
4283 +#define _INC_CPMAC_REG
4284 +
4285 +#ifndef MEM_PTR
4286 +#define MEM_PTR volatile bit32u *
4287 +#endif
4288 +
4289 +/***************************************************************************
4290 + *
4291 + * C P M A C M E M O R Y M A P
4292 + *
4293 + **************************************************************************/
4294 +
4295 +#define pCPMAC_TX_IDVER(base) ((MEM_PTR)(base+0x000))
4296 +#define CPMAC_TX_IDVER(base) (*pCPMAC_TX_IDVER(base))
4297 +#define pCPMAC_TX_CONTROL(base) ((MEM_PTR)(base+0x004))
4298 +#define CPMAC_TX_CONTROL(base) (*pCPMAC_TX_CONTROL(base))
4299 +#define pCPMAC_TX_TEARDOWN(base) ((MEM_PTR)(base+0x008))
4300 +#define CPMAC_TX_TEARDOWN(base) (*pCPMAC_TX_TEARDOWN(base))
4301 +#define pCPMAC_RX_IDVER(base) ((MEM_PTR)(base+0x010))
4302 +#define CPMAC_RX_IDVER(base) (*pCPMAC_RX_IDVER(base))
4303 +#define pCPMAC_RX_CONTROL(base) ((MEM_PTR)(base+0x014))
4304 +#define CPMAC_RX_CONTROL(base) (*pCPMAC_RX_CONTROL(base))
4305 +#define pCPMAC_RX_TEARDOWN(base) ((MEM_PTR)(base+0x018))
4306 +#define CPMAC_RX_TEARDOWN(base) (*pCPMAC_RX_TEARDOWN(base))
4307 +#define pCPMAC_RX_MBP_ENABLE(base) ((MEM_PTR)(base+0x100))
4308 +#define CPMAC_RX_MBP_ENABLE(base) (*pCPMAC_RX_MBP_ENABLE(base))
4309 +#define pCPMAC_RX_UNICAST_SET(base) ((MEM_PTR)(base+0x104))
4310 +#define CPMAC_RX_UNICAST_SET(base) (*pCPMAC_RX_UNICAST_SET(base))
4311 +#define pCPMAC_RX_UNICAST_CLEAR(base) ((MEM_PTR)(base+0x108))
4312 +#define CPMAC_RX_UNICAST_CLEAR(base) (*pCPMAC_RX_UNICAST_CLEAR(base))
4313 +#define pCPMAC_RX_MAXLEN(base) ((MEM_PTR)(base+0x10C))
4314 +#define CPMAC_RX_MAXLEN(base) (*pCPMAC_RX_MAXLEN(base))
4315 +#define pCPMAC_RX_BUFFER_OFFSET(base) ((MEM_PTR)(base+0x110))
4316 +#define CPMAC_RX_BUFFER_OFFSET(base) (*pCPMAC_RX_BUFFER_OFFSET(base))
4317 +#define pCPMAC_RX_FILTERLOWTHRESH(base) ((MEM_PTR)(base+0x114))
4318 +#define CPMAC_RX_FILTERLOWTHRESH(base) (*pCPMAC_RX_FILTERLOWTHRESH(base))
4319 +#define pCPMAC_RX0_FLOWTHRESH(base) ((MEM_PTR)(base+0x120))
4320 +#define CPMAC_RX0_FLOWTHRESH(base) (*pCPMAC_RX0_FLOWTHRESH(base))
4321 +#define pCPMAC_RX1_FLOWTHRESH(base) ((MEM_PTR)(base+0x124))
4322 +#define CPMAC_RX1_FLOWTHRESH(base) (*pCPMAC_RX1_FLOWTHRESH(base))
4323 +#define pCPMAC_RX2_FLOWTHRESH(base) ((MEM_PTR)(base+0x128))
4324 +#define CPMAC_RX2_FLOWTHRESH(base) (*pCPMAC_RX2_FLOWTHRESH(base))
4325 +#define pCPMAC_RX3_FLOWTHRESH(base) ((MEM_PTR)(base+0x12C))
4326 +#define CPMAC_RX3_FLOWTHRESH(base) (*pCPMAC_RX3_FLOWTHRESH(base))
4327 +#define pCPMAC_RX4_FLOWTHRESH(base) ((MEM_PTR)(base+0x130))
4328 +#define CPMAC_RX4_FLOWTHRESH(base) (*pCPMAC_RX4_FLOWTHRESH(base))
4329 +#define pCPMAC_RX5_FLOWTHRESH(base) ((MEM_PTR)(base+0x134))
4330 +#define CPMAC_RX5_FLOWTHRESH(base) (*pCPMAC_RX5_FLOWTHRESH(base))
4331 +#define pCPMAC_RX6_FLOWTHRESH(base) ((MEM_PTR)(base+0x138))
4332 +#define CPMAC_RX6_FLOWTHRESH(base) (*pCPMAC_RX6_FLOWTHRESH(base))
4333 +#define pCPMAC_RX7_FLOWTHRESH(base) ((MEM_PTR)(base+0x13C))
4334 +#define CPMAC_RX7_FLOWTHRESH(base) (*pCPMAC_RX7_FLOWTHRESH(base))
4335 +#define pCPMAC_RX0_FREEBUFFER(base) ((MEM_PTR)(base+0x140))
4336 +#define CPMAC_RX0_FREEBUFFER(base) (*pCPMAC_RX0_FREEBUFFER(base))
4337 +#define pCPMAC_RX1_FREEBUFFER(base) ((MEM_PTR)(base+0x144))
4338 +#define CPMAC_RX1_FREEBUFFER(base) (*pCPMAC_RX1_FREEBUFFER(base))
4339 +#define pCPMAC_RX2_FREEBUFFER(base) ((MEM_PTR)(base+0x148))
4340 +#define CPMAC_RX2_FREEBUFFER(base) (*pCPMAC_RX2_FREEBUFFER(base))
4341 +#define pCPMAC_RX3_FREEBUFFER(base) ((MEM_PTR)(base+0x14C))
4342 +#define CPMAC_RX3_FREEBUFFER(base) (*pCPMAC_RX3_FREEBUFFER(base))
4343 +#define pCPMAC_RX4_FREEBUFFER(base) ((MEM_PTR)(base+0x150))
4344 +#define CPMAC_RX4_FREEBUFFER(base) (*pCPMAC_RX4_FREEBUFFER(base))
4345 +#define pCPMAC_RX5_FREEBUFFER(base) ((MEM_PTR)(base+0x154))
4346 +#define CPMAC_RX5_FREEBUFFER(base) (*pCPMAC_RX5_FREEBUFFER(base))
4347 +#define pCPMAC_RX6_FREEBUFFER(base) ((MEM_PTR)(base+0x158))
4348 +#define CPMAC_RX6_FREEBUFFER(base) (*pCPMAC_RX6_FREEBUFFER(base))
4349 +#define pCPMAC_RX7_FREEBUFFER(base) ((MEM_PTR)(base+0x15C))
4350 +#define CPMAC_RX7_FREEBUFFER(base) (*pCPMAC_RX7_FREEBUFFER(base))
4351 +#define pCPMAC_MACCONTROL(base) ((MEM_PTR)(base+0x160))
4352 +#define CPMAC_MACCONTROL(base) (*pCPMAC_MACCONTROL(base))
4353 +#define pCPMAC_MACSTATUS(base) ((MEM_PTR)(base+0x164))
4354 +#define CPMAC_MACSTATUS(base) (*pCPMAC_MACSTATUS(base))
4355 +#define pCPMAC_EMCONTROL(base) ((MEM_PTR)(base+0x168))
4356 +#define CPMAC_EMCONTROL(base) (*pCPMAC_EMCONTROL(base))
4357 +#define pCPMAC_TX_INTSTAT_RAW(base) ((MEM_PTR)(base+0x170))
4358 +#define CPMAC_TX_INTSTAT_RAW(base) (*pCPMAC_TX_INTSTAT_RAW(base))
4359 +#define pCPMAC_TX_INTSTAT_MASKED(base) ((MEM_PTR)(base+0x174))
4360 +#define CPMAC_TX_INTSTAT_MASKED(base) (*pCPMAC_TX_INTSTAT_MASKED(base))
4361 +#define pCPMAC_TX_INTMASK_SET(base) ((MEM_PTR)(base+0x178))
4362 +#define CPMAC_TX_INTMASK_SET(base) (*pCPMAC_TX_INTMASK_SET(base))
4363 +#define pCPMAC_TX_INTMASK_CLEAR(base) ((MEM_PTR)(base+0x17C))
4364 +#define CPMAC_TX_INTMASK_CLEAR(base) (*pCPMAC_TX_INTMASK_CLEAR(base))
4365 +#define pCPMAC_MAC_IN_VECTOR(base) ((MEM_PTR)(base+0x180))
4366 +#define CPMAC_MAC_IN_VECTOR(base) (*pCPMAC_MAC_IN_VECTOR(base))
4367 +#define pCPMAC_MAC_EOI_VECTOR(base) ((MEM_PTR)(base+0x184))
4368 +#define CPMAC_MAC_EOI_VECTOR(base) (*pCPMAC_MAC_EOI_VECTOR(base))
4369 +#define pCPMAC_RX_INTSTAT_RAW(base) ((MEM_PTR)(base+0x190))
4370 +#define CPMAC_RX_INTSTAT_RAW(base) (*pCPMAC_RX_INTSTAT_RAW(base))
4371 +#define pCPMAC_RX_INTSTAT_MASKED(base) ((MEM_PTR)(base+0x194))
4372 +#define CPMAC_RX_INTSTAT_MASKED(base) (*pCPMAC_RX_INTSTAT_MASKED(base))
4373 +#define pCPMAC_RX_INTMASK_SET(base) ((MEM_PTR)(base+0x198))
4374 +#define CPMAC_RX_INTMASK_SET(base) (*pCPMAC_RX_INTMASK_SET(base))
4375 +#define pCPMAC_RX_INTMASK_CLEAR(base) ((MEM_PTR)(base+0x19C))
4376 +#define CPMAC_RX_INTMASK_CLEAR(base) (*pCPMAC_RX_INTMASK_CLEAR(base))
4377 +#define pCPMAC_MAC_INTSTAT_RAW(base) ((MEM_PTR)(base+0x1A0))
4378 +#define CPMAC_MAC_INTSTAT_RAW(base) (*pCPMAC_MAC_INTSTAT_RAW(base))
4379 +#define pCPMAC_MAC_INTSTAT_MASKED(base) ((MEM_PTR)(base+0x1A4))
4380 +#define CPMAC_MAC_INTSTAT_MASKED(base) (*pCPMAC_MAC_INTSTAT_MASKED(base))
4381 +#define pCPMAC_MAC_INTMASK_SET(base) ((MEM_PTR)(base+0x1A8))
4382 +#define CPMAC_MAC_INTMASK_SET(base) (*pCPMAC_MAC_INTMASK_SET(base))
4383 +#define pCPMAC_MAC_INTMASK_CLEAR(base) ((MEM_PTR)(base+0x1AC))
4384 +#define CPMAC_MAC_INTMASK_CLEAR(base) (*pCPMAC_MAC_INTMASK_CLEAR(base))
4385 +#define pCPMAC_MACADDRLO_0(base) ((MEM_PTR)(base+0x1B0))
4386 +#define CPMAC_MACADDRLO_0(base) (*pCPMAC_MACADDRLO_0(base))
4387 +#define pCPMAC_MACADDRLO_1(base) ((MEM_PTR)(base+0x1B4))
4388 +#define CPMAC_MACADDRLO_1(base) (*pCPMAC_MACADDRLO_1(base))
4389 +#define pCPMAC_MACADDRLO_2(base) ((MEM_PTR)(base+0x1B8))
4390 +#define CPMAC_MACADDRLO_2(base) (*pCPMAC_MACADDRLO_2(base))
4391 +#define pCPMAC_MACADDRLO_3(base) ((MEM_PTR)(base+0x1BC))
4392 +#define CPMAC_MACADDRLO_3(base) (*pCPMAC_MACADDRLO_3(base))
4393 +#define pCPMAC_MACADDRLO_4(base) ((MEM_PTR)(base+0x1C0))
4394 +#define CPMAC_MACADDRLO_4(base) (*pCPMAC_MACADDRLO_4(base))
4395 +#define pCPMAC_MACADDRLO_5(base) ((MEM_PTR)(base+0x1C4))
4396 +#define CPMAC_MACADDRLO_5(base) (*pCPMAC_MACADDRLO_5(base))
4397 +#define pCPMAC_MACADDRLO_6(base) ((MEM_PTR)(base+0x1C8))
4398 +#define CPMAC_MACADDRLO_6(base) (*pCPMAC_MACADDRLO_6(base))
4399 +#define pCPMAC_MACADDRLO_7(base) ((MEM_PTR)(base+0x1CC))
4400 +#define CPMAC_MACADDRLO_7(base) (*pCPMAC_MACADDRLO_7(base))
4401 +#define pCPMAC_MACADDRMID(base) ((MEM_PTR)(base+0x1D0))
4402 +#define CPMAC_MACADDRMID(base) (*pCPMAC_MACADDRMID(base))
4403 +#define pCPMAC_MACADDRHI(base) ((MEM_PTR)(base+0x1D4))
4404 +#define CPMAC_MACADDRHI(base) (*pCPMAC_MACADDRHI(base))
4405 +#define pCPMAC_MACHASH1(base) ((MEM_PTR)(base+0x1D8))
4406 +#define CPMAC_MACHASH1(base) (*pCPMAC_MACHASH1(base))
4407 +#define pCPMAC_MACHASH2(base) ((MEM_PTR)(base+0x1DC))
4408 +#define CPMAC_MACHASH2(base) (*pCPMAC_MACHASH2(base))
4409 +#define pCPMAC_BOFFTEST(base) ((MEM_PTR)(base+0x1E0))
4410 +#define CPMAC_BOFFTEST(base) (*pCPMAC_BOFFTEST(base))
4411 +#define pCPMAC_PACTEST(base) ((MEM_PTR)(base+0x1E4))
4412 +#define CPMAC_PACTEST(base) (*pCPMAC_PACTEST(base))
4413 +#define pCPMAC_RXPAUSE(base) ((MEM_PTR)(base+0x1E8))
4414 +#define CPMAC_RXPAUSE(base) (*pCPMAC_RXPAUSE(base))
4415 +#define pCPMAC_TXPAUSE(base) ((MEM_PTR)(base+0x1EC))
4416 +#define CPMAC_TXPAUSE(base) (*pCPMAC_TXPAUSE(base))
4417 +/* STATISTICS */
4418 +#define pCPMAC_RXGOODFRAMES(base) ((MEM_PTR)(base+0x200))
4419 +#define CPMAC_RXGOODFRAMES(base) (*pCPMAC_RXGOODFRAMES(base))
4420 +#define pCPMAC_RXBROADCASTFRAMES(base) ((MEM_PTR)(base+0x204))
4421 +#define CPMAC_RXBROADCASTFRAMES(base) (*pCPMAC_RXBROADCASTFRAMES(base))
4422 +#define pCPMAC_RXMULTICASTFRAMES(base) ((MEM_PTR)(base+0x208))
4423 +#define CPMAC_RXMULTICASTFRAMES(base) (*pCPMAC_RXMULTICASTFRAMES(base))
4424 +#define pCPMAC_RXPAUSEFRAMES(base) ((MEM_PTR)(base+0x20C))
4425 +#define CPMAC_RXPAUSEFRAMES(base) (*pCPMAC_RXPAUSEFRAMES(base))
4426 +#define pCPMAC_RXCRCERRORS(base) ((MEM_PTR)(base+0x210))
4427 +#define CPMAC_RXCRCERRORS(base) (*pCPMAC_RXCRCERRORS(base))
4428 +#define pCPMAC_RXALIGNCODEERRORS(base) ((MEM_PTR)(base+0x214))
4429 +#define CPMAC_RXALIGNCODEERRORS(base) (*pCPMAC_RXALIGNCODEERRORS(base))
4430 +#define pCPMAC_RXOVERSIZEDFRAMES(base) ((MEM_PTR)(base+0x218))
4431 +#define CPMAC_RXOVERSIZEDFRAMES(base) (*pCPMAC_RXOVERSIZEDFRAMES(base))
4432 +#define pCPMAC_RXJABBERFRAMES(base) ((MEM_PTR)(base+0x21C))
4433 +#define CPMAC_RXJABBERFRAMES(base) (*pCPMAC_RXJABBERFRAMES(base))
4434 +#define pCPMAC_RXUNDERSIZEDFRAMES(base) ((MEM_PTR)(base+0x220))
4435 +#define CPMAC_RXUNDERSIZEDFRAMES(base) (*pCPMAC_RXUNDERSIZEDFRAMES(base))
4436 +#define pCPMAC_RXFRAGMENTS(base) ((MEM_PTR)(base+0x224))
4437 +#define CPMAC_RXFRAGMENTS(base) (*pCPMAC_RXFRAGMENTS(base))
4438 +#define pCPMAC_RXFILTEREDFRAMES(base) ((MEM_PTR)(base+0x228))
4439 +#define CPMAC_RXFILTEREDFRAMES(base) (*pCPMAC_RXFILTEREDFRAMES(base))
4440 +#define pCPMAC_RXQOSFILTEREDFRAMES(base) ((MEM_PTR)(base+0x22C))
4441 +#define CPMAC_RXQOSFILTEREDFRAMES(base) (*pCPMAC_RXQOSFILTEREDFRAMES(base))
4442 +#define pCPMAC_RXOCTETS(base) ((MEM_PTR)(base+0x230))
4443 +#define CPMAC_RXOCTETS(base) (*pCPMAC_RXOCTETS(base))
4444 +#define pCPMAC_TXGOODFRAMES(base) ((MEM_PTR)(base+0x234))
4445 +#define CPMAC_TXGOODFRAMES(base) (*pCPMAC_TXGOODFRAMES(base))
4446 +#define pCPMAC_TXBROADCASTFRAMES(base) ((MEM_PTR)(base+0x238))
4447 +#define CPMAC_TXBROADCASTFRAMES(base) (*pCPMAC_TXBROADCASTFRAMES(base))
4448 +#define pCPMAC_TXMULTICASTFRAMES(base) ((MEM_PTR)(base+0x23C))
4449 +#define CPMAC_TXMULTICASTFRAMES(base) (*pCPMAC_TXMULTICASTFRAMES(base))
4450 +#define pCPMAC_TXPAUSEFRAMES(base) ((MEM_PTR)(base+0x240))
4451 +#define CPMAC_TXPAUSEFRAMES(base) (*pCPMAC_TXPAUSEFRAMES(base))
4452 +#define pCPMAC_TXDEFERREDFRAMES(base) ((MEM_PTR)(base+0x244))
4453 +#define CPMAC_TXDEFERREDFRAMES(base) (*pCPMAC_TXDEFERREDFRAMES(base))
4454 +#define pCPMAC_TXCOLLISIONFRAMES(base) ((MEM_PTR)(base+0x248))
4455 +#define CPMAC_TXCOLLISIONFRAMES(base) (*pCPMAC_TXCOLLISIONFRAMES(base))
4456 +#define pCPMAC_TXSINGLECOLLFRAMES(base) ((MEM_PTR)(base+0x24C))
4457 +#define CPMAC_TXSINGLECOLLFRAMES(base) (*pCPMAC_TXSINGLECOLLFRAMES(base))
4458 +#define pCPMAC_TXMULTCOLLFRAMES(base) ((MEM_PTR)(base+0x250))
4459 +#define CPMAC_TXMULTCOLLFRAMES(base) (*pCPMAC_TXMULTCOLLFRAMES(base))
4460 +#define pCPMAC_TXEXCESSIVECOLLISIONS(base) ((MEM_PTR)(base+0x254))
4461 +#define CPMAC_TXEXCESSIVECOLLISIONS(base) (*pCPMAC_TXEXCESSIVECOLLISIONS(base))
4462 +#define pCPMAC_TXLATECOLLISIONS(base) ((MEM_PTR)(base+0x258))
4463 +#define CPMAC_TXLATECOLLISIONS(base) (*pCPMAC_TXLATECOLLISIONS(base))
4464 +#define pCPMAC_TXUNDERRUN(base) ((MEM_PTR)(base+0x25C))
4465 +#define CPMAC_TXUNDERRUN(base) (*pCPMAC_TXUNDERRUN(base))
4466 +#define pCPMAC_TXCARRIERSENSEERRORS(base) ((MEM_PTR)(base+0x260))
4467 +#define CPMAC_TXCARRIERSENSEERRORS(base) (*pCPMAC_TXCARRIERSENSEERRORS(base))
4468 +#define pCPMAC_TXOCTETS(base) ((MEM_PTR)(base+0x264))
4469 +#define CPMAC_TXOCTETS(base) (*pCPMAC_TXOCTETS(base))
4470 +#define pCPMAC_64OCTETFRAMES(base) ((MEM_PTR)(base+0x268))
4471 +#define CPMAC_64OCTETFRAMES(base) (*pCPMAC_64OCTETFRAMES(base))
4472 +#define pCPMAC_65T127OCTETFRAMES(base) ((MEM_PTR)(base+0x26C))
4473 +#define CPMAC_65T127OCTETFRAMES(base) (*pCPMAC_65T127OCTETFRAMES(base))
4474 +#define pCPMAC_128T255OCTETFRAMES(base) ((MEM_PTR)(base+0x270))
4475 +#define CPMAC_128T255OCTETFRAMES(base) (*pCPMAC_128T255OCTETFRAMES(base))
4476 +#define pCPMAC_256T511OCTETFRAMES(base) ((MEM_PTR)(base+0x274))
4477 +#define CPMAC_256T511OCTETFRAMES(base) (*pCPMAC_256T511OCTETFRAMES(base))
4478 +#define pCPMAC_512T1023OCTETFRAMES(base) ((MEM_PTR)(base+0x278))
4479 +#define CPMAC_512T1023OCTETFRAMES(base) (*pCPMAC_512T1023OCTETFRAMES(base))
4480 +#define pCPMAC_1024TUPOCTETFRAMES(base) ((MEM_PTR)(base+0x27C))
4481 +#define CPMAC_1024TUPOCTETFRAMES(base) (*pCPMAC_1024TUPOCTETFRAMES(base))
4482 +#define pCPMAC_NETOCTETS(base) ((MEM_PTR)(base+0x280))
4483 +#define CPMAC_NETOCTETS(base) (*pCPMAC_NETOCTETS(base))
4484 +#define pCPMAC_RXSOFOVERRUNS(base) ((MEM_PTR)(base+0x284))
4485 +#define CPMAC_RXSOFOVERRUNS(base) (*pCPMAC_RXSOFOVERRUNS(base))
4486 +#define pCPMAC_RXMOFOVERRUNS(base) ((MEM_PTR)(base+0x288))
4487 +#define CPMAC_RXMOFOVERRUNS(base) (*pCPMAC_RXMOFOVERRUNS(base))
4488 +#define pCPMAC_RXDMAOVERRUNS(base) ((MEM_PTR)(base+0x28C))
4489 +#define CPMAC_RXDMAOVERRUNS(base) (*pCPMAC_RXDMAOVERRUNS(base))
4490 +
4491 +#define CPMAC_TX_HDP(base,ch) (*(MEM_PTR)(base+0x600+(4*ch)))
4492 +#define pCPMAC_TX0_HDP(base) ((MEM_PTR)(base+0x600))
4493 +#define CPMAC_TX0_HDP(base) (*pCPMAC_TX0_HDP(base))
4494 +#define pCPMAC_TX1_HDP(base) ((MEM_PTR)(base+0x604))
4495 +#define CPMAC_TX1_HDP(base) (*pCPMAC_TX1_HDP(base))
4496 +#define pCPMAC_TX2_HDP(base) ((MEM_PTR)(base+0x608))
4497 +#define CPMAC_TX2_HDP(base) (*pCPMAC_TX2_HDP(base))
4498 +#define pCPMAC_TX3_HDP(base) ((MEM_PTR)(base+0x60C))
4499 +#define CPMAC_TX3_HDP(base) (*pCPMAC_TX3_HDP(base))
4500 +#define pCPMAC_TX4_HDP(base) ((MEM_PTR)(base+0x610))
4501 +#define CPMAC_TX4_HDP(base) (*pCPMAC_TX4_HDP(base))
4502 +#define pCPMAC_TX5_HDP(base) ((MEM_PTR)(base+0x614))
4503 +#define CPMAC_TX5_HDP(base) (*pCPMAC_TX5_HDP(base))
4504 +#define pCPMAC_TX6_HDP(base) ((MEM_PTR)(base+0x618))
4505 +#define CPMAC_TX6_HDP(base) (*pCPMAC_TX6_HDP(base))
4506 +#define pCPMAC_TX7_HDP(base) ((MEM_PTR)(base+0x61C))
4507 +#define CPMAC_TX7_HDP(base) (*pCPMAC_TX7_HDP(base))
4508 +#define CPMAC_RX_HDP(base,ch) (*(MEM_PTR)(base+0x620+(4*ch)))
4509 +#define pCPMAC_RX0_HDP(base) ((MEM_PTR)(base+0x620))
4510 +#define CPMAC_RX0_HDP(base) (*pCPMAC_RX0_HDP(base))
4511 +#define pCPMAC_RX1_HDP(base) ((MEM_PTR)(base+0x624))
4512 +#define CPMAC_RX1_HDP(base) (*pCPMAC_RX1_HDP(base))
4513 +#define pCPMAC_RX2_HDP(base) ((MEM_PTR)(base+0x628))
4514 +#define CPMAC_RX2_HDP(base) (*pCPMAC_RX2_HDP(base))
4515 +#define pCPMAC_RX3_HDP(base) ((MEM_PTR)(base+0x62C))
4516 +#define CPMAC_RX3_HDP(base) (*pCPMAC_RX3_HDP(base))
4517 +#define pCPMAC_RX4_HDP(base) ((MEM_PTR)(base+0x630))
4518 +#define CPMAC_RX4_HDP(base) (*pCPMAC_RX4_HDP(base))
4519 +#define pCPMAC_RX5_HDP(base) ((MEM_PTR)(base+0x634))
4520 +#define CPMAC_RX5_HDP(base) (*pCPMAC_RX5_HDP(base))
4521 +#define pCPMAC_RX6_HDP(base) ((MEM_PTR)(base+0x638))
4522 +#define CPMAC_RX6_HDP(base) (*pCPMAC_RX6_HDP(base))
4523 +#define pCPMAC_RX7_HDP(base) ((MEM_PTR)(base+0x63C))
4524 +#define CPMAC_RX7_HDP(base) (*pCPMAC_RX7_HDP(base))
4525 +
4526 +
4527 +#define CPMAC_TX_INT_ACK(base,ch) (*(MEM_PTR)(base+0x640+(4*ch)))
4528 +
4529 +#define pCPMAC_TX0_INT_ACK(base) ((MEM_PTR)(base+0x640))
4530 +#define CPMAC_TX0_INT_ACK(base) (*pCPMAC_TX0_INT_ACK(base))
4531 +#define pCPMAC_TX1_INT_ACK(base) ((MEM_PTR)(base+0x644))
4532 +#define CPMAC_TX1_INT_ACK(base) (*pCPMAC_TX1_INT_ACK(base))
4533 +#define pCPMAC_TX2_INT_ACK(base) ((MEM_PTR)(base+0x648))
4534 +#define CPMAC_TX2_INT_ACK(base) (*pCPMAC_TX2_INT_ACK(base))
4535 +#define pCPMAC_TX3_INT_ACK(base) ((MEM_PTR)(base+0x64C))
4536 +#define CPMAC_TX3_INT_ACK(base) (*pCPMAC_TX3_INT_ACK(base))
4537 +#define pCPMAC_TX4_INT_ACK(base) ((MEM_PTR)(base+0x650))
4538 +#define CPMAC_TX4_INT_ACK(base) (*pCPMAC_TX4_INT_ACK(base))
4539 +#define pCPMAC_TX5_INT_ACK(base) ((MEM_PTR)(base+0x654))
4540 +#define CPMAC_TX5_INT_ACK(base) (*pCPMAC_TX5_INT_ACK(base))
4541 +#define pCPMAC_TX6_INT_ACK(base) ((MEM_PTR)(base+0x658))
4542 +#define CPMAC_TX6_INT_ACK(base) (*pCPMAC_TX6_INT_ACK(base))
4543 +#define pCPMAC_TX7_INT_ACK(base) ((MEM_PTR)(base+0x65C))
4544 +#define CPMAC_TX7_INT_ACK(base) (*pCPMAC_TX7_INT_ACK(base))
4545 +#define CPMAC_RX_INT_ACK(base,ch) (*(MEM_PTR)(base+0x660+(4*ch)))
4546 +
4547 +#define pCPMAC_RX0_INT_ACK(base) ((MEM_PTR)(base+0x660))
4548 +#define CPMAC_RX0_INT_ACK(base) (*pCPMAC_RX0_INT_ACK(base))
4549 +#define pCPMAC_RX1_INT_ACK(base) ((MEM_PTR)(base+0x664))
4550 +#define CPMAC_RX1_INT_ACK(base) (*pCPMAC_RX1_INT_ACK(base))
4551 +#define pCPMAC_RX2_INT_ACK(base) ((MEM_PTR)(base+0x668))
4552 +#define CPMAC_RX2_INT_ACK(base) (*pCPMAC_RX2_INT_ACK(base))
4553 +#define pCPMAC_RX3_INT_ACK(base) ((MEM_PTR)(base+0x66C))
4554 +#define CPMAC_RX3_INT_ACK(base) (*pCPMAC_RX3_INT_ACK(base))
4555 +#define pCPMAC_RX4_INT_ACK(base) ((MEM_PTR)(base+0x670))
4556 +#define CPMAC_RX4_INT_ACK(base) (*pCPMAC_RX4_INT_ACK(base))
4557 +#define pCPMAC_RX5_INT_ACK(base) ((MEM_PTR)(base+0x674))
4558 +#define CPMAC_RX5_INT_ACK(base) (*pCPMAC_RX5_INT_ACK(base))
4559 +#define pCPMAC_RX6_INT_ACK(base) ((MEM_PTR)(base+0x678))
4560 +#define CPMAC_RX6_INT_ACK(base) (*pCPMAC_RX6_INT_ACK(base))
4561 +#define pCPMAC_RX7_INT_ACK(base) ((MEM_PTR)(base+0x67C))
4562 +#define CPMAC_RX7_INT_ACK(base) (*pCPMAC_RX7_INT_ACK(base))
4563 +
4564 +/****************************************************************************/
4565 +/* */
4566 +/* R E G I S T E R B I T D E F I N I T I O N S */
4567 +/* */
4568 +/****************************************************************************/
4569 +
4570 +/* TX_CONTROL */
4571 +
4572 +#define TX_EN (1 << 0)
4573 +
4574 +/* RX_CONTROL */
4575 +
4576 +#define RX_EN (1 << 0)
4577 +
4578 +/* RX_MBP_ENABLE */
4579 +
4580 +#define RX_PASS_CRC (1 << 30)
4581 +#define RX_QOS_EN (1 << 29)
4582 +#define RX_NO_CHAIN (1 << 28)
4583 +
4584 +#define RX_CMF_EN (1 << 24)
4585 +#define RX_CSF_EN (1 << 23)
4586 +#define RX_CEF_EN (1 << 22)
4587 +#define RX_CAF_EN (1 << 21)
4588 +
4589 +#define RX_PROM_CH(n) (n << 16)
4590 +#define RX_PROM_CH_MASK RX_PROM_CH(7)
4591 +#define RX_PROM_CH_7 RX_PROM_CH(7)
4592 +#define RX_PROM_CH_6 RX_PROM_CH(6)
4593 +#define RX_PROM_CH_5 RX_PROM_CH(5)
4594 +#define RX_PROM_CH_4 RX_PROM_CH(4)
4595 +#define RX_PROM_CH_3 RX_PROM_CH(3)
4596 +#define RX_PROM_CH_2 RX_PROM_CH(2)
4597 +#define RX_PROM_CH_1 RX_PROM_CH(1)
4598 +#define RX_PROM_CH_0 RX_PROM_CH(0)
4599 +
4600 +#define RX_BROAD_EN (1 << 13)
4601 +
4602 +#define RX_BROAD_CH(n) (n << 8)
4603 +#define RX_BROAD_CH_MASK RX_BROAD_CH(7)
4604 +#define RX_BROAD_CH_7 RX_BROAD_CH(7)
4605 +#define RX_BROAD_CH_6 RX_BROAD_CH(6)
4606 +#define RX_BROAD_CH_5 RX_BROAD_CH(5)
4607 +#define RX_BROAD_CH_4 RX_BROAD_CH(4)
4608 +#define RX_BROAD_CH_3 RX_BROAD_CH(3)
4609 +#define RX_BROAD_CH_2 RX_BROAD_CH(2)
4610 +#define RX_BROAD_CH_1 RX_BROAD_CH(1)
4611 +#define RX_BROAD_CH_0 RX_BROAD_CH(0)
4612 +
4613 +#define RX_MULT_EN (1 << 5)
4614 +
4615 +#define RX_MULT_CH(n) (n << 0)
4616 +#define RX_MULT_CH_MASK RX_MULT_CH(7)
4617 +#define RX_MULT_CH_7 RX_MULT_CH(7)
4618 +#define RX_MULT_CH_6 RX_MULT_CH(6)
4619 +#define RX_MULT_CH_5 RX_MULT_CH(5)
4620 +#define RX_MULT_CH_4 RX_MULT_CH(4)
4621 +#define RX_MULT_CH_3 RX_MULT_CH(3)
4622 +#define RX_MULT_CH_2 RX_MULT_CH(2)
4623 +#define RX_MULT_CH_1 RX_MULT_CH(1)
4624 +#define RX_MULT_CH_0 RX_MULT_CH(0)
4625 +
4626 +
4627 +
4628 +/* RX_UNICAST_SET */
4629 +
4630 +#define RX_CH7_EN (1 << 7)
4631 +#define RX_CH6_EN (1 << 6)
4632 +#define RX_CH5_EN (1 << 5)
4633 +#define RX_CH4_EN (1 << 4)
4634 +#define RX_CH3_EN (1 << 3)
4635 +#define RX_CH2_EN (1 << 2)
4636 +#define RX_CH1_EN (1 << 1)
4637 +#define RX_CH0_EN (1 << 0)
4638 +
4639 +
4640 +
4641 +/* MAC control */
4642 +#define TX_PTYPE (1 << 9)
4643 +#define TX_PACE (1 << 6)
4644 +#define MII_EN (1 << 5)
4645 +#define TX_FLOW_EN (1 << 4)
4646 +#define RX_FLOW_EN (1 << 3)
4647 +#define MTEST (1 << 2)
4648 +#define CTRL_LOOPBACK (1 << 1)
4649 +#define FULLDUPLEX (1 << 0)
4650 +
4651 +
4652 +/* IntVec definitions */
4653 +#define MAC_IN_VECTOR_STATUS_INT (1 << 19)
4654 +#define MAC_IN_VECTOR_HOST_INT (1 << 18)
4655 +#define MAC_IN_VECTOR_RX_INT_OR (1 << 17)
4656 +#define MAC_IN_VECTOR_TX_INT_OR (1 << 16)
4657 +#define MAC_IN_VECTOR_RX_INT_VEC (7 << 8)
4658 +#define MAC_IN_VECTOR_TX_INT_VEC (7)
4659 +
4660 +
4661 +/* MacStatus */
4662 +
4663 +#define TX_HOST_ERR_CODE (0xF << 20)
4664 +#define TX_ERR_CH (0x7 << 16)
4665 +#define RX_HOST_ERR_CODE (0xF << 12)
4666 +#define RX_ERR_CH (0x7 << 8)
4667 +#define RX_QOS_ACT (1 << 2)
4668 +#define RX_FLOW_ACT (1 << 1)
4669 +#define TX_FLOW_ACT (1 << 0)
4670 +#endif _INC_CPMAC_REG
4671 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpmdio.c linux-2.4.30/drivers/net/avalanche_cpmac/cpmdio.c
4672 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpmdio.c 1970-01-01 02:00:00.000000000 +0200
4673 +++ linux-2.4.30/drivers/net/avalanche_cpmac/cpmdio.c 2005-04-15 05:10:41.000000000 +0200
4674 @@ -0,0 +1,960 @@
4675 +/***************************************************************************
4676 +** TNETD53xx Software Support
4677 +** Copyright(c) 2002, Texas Instruments Incorporated. All Rights Reserved.
4678 +**
4679 +** FILE: cpmdio.c
4680 +**
4681 +** DESCRIPTION:
4682 +** MDIO Polling State Machine API. Functions will enable mii-Phy
4683 +** negotiation.
4684 +**
4685 +** HISTORY:
4686 +** 01Jan01 Denis, Bill Original
4687 +** 27Mar02 Michael Hanrahan (modified from emacmdio.c)
4688 +** 07May02 Michael Hanrahan replaced clockwait for code delay
4689 +** 10Jul02 Michael Hanrahan more debug, if fallback link is selected
4690 +*****************************************************************************/
4691 +#define __CPHAL_CPMDIO
4692 +
4693 +#include "mdio_reg.h"
4694 +
4695 +#ifdef _CPHAL_CPMAC
4696 +#define mdioPrintf PhyDev->HalDev->OsFunc->Printf
4697 +#else
4698 +#define mdioPrintf printf
4699 +#endif
4700 +
4701 +typedef struct _phy_device
4702 +{
4703 + bit32u miibase;
4704 + bit32u inst;
4705 + bit32u PhyState;
4706 + bit32u MdixMask;
4707 + bit32u PhyMask;
4708 + bit32u MLinkMask;
4709 + bit32u PhyMode;
4710 +#ifdef _CPHAL_CPMAC
4711 + HAL_DEVICE *HalDev;
4712 +#endif
4713 +} _PHY_DEVICE;
4714 +
4715 +static void _mdioDelayEmulate(PHY_DEVICE *PhyDev, int ClockWait);
4716 +static void _mdioWaitForAccessComplete(PHY_DEVICE *PhyDev);
4717 +static void _mdioUserAccess(PHY_DEVICE *PhyDev, bit32u method, bit32u regadr, bit32u phyadr, bit32u data);
4718 +static bit32u _mdioUserAccessRead(PHY_DEVICE *PhyDev, bit32u regadr, bit32u phyadr);
4719 +static void _mdioUserAccessWrite(PHY_DEVICE *PhyDev, bit32u regadr, bit32u phyadr, bit32u data);
4720 +
4721 +static void _mdioDisablePhy(PHY_DEVICE *PhyDev,bit32u PhyNum);
4722 +static void _mdioPhyTimeOut(PHY_DEVICE *PhyDev);
4723 +static void _mdioResetPhy(PHY_DEVICE *PhyDev,bit32u PhyNum);
4724 +
4725 +static void _mdioDumpPhy(PHY_DEVICE *PhyDev, bit32u p);
4726 +static void _mdioDumpState(PHY_DEVICE *PhyDev);
4727 +
4728 +/* Auto Mdix */
4729 +static void _mdioMdixDelay(PHY_DEVICE *PhyDev);
4730 +static int _mdioMdixSupported(PHY_DEVICE *PhyDev);
4731 +
4732 +static void _MdioDefaultState (PHY_DEVICE *PhyDev);
4733 +static void _MdioFindingState (PHY_DEVICE *PhyDev);
4734 +static void _MdioFoundState (PHY_DEVICE *PhyDev);
4735 +static void _MdioInitState (PHY_DEVICE *PhyDev);
4736 +static void _MdioLinkedState (PHY_DEVICE *PhyDev);
4737 +static void _MdioLinkWaitState (PHY_DEVICE *PhyDev);
4738 +static void _MdioLoopbackState (PHY_DEVICE *PhyDev);
4739 +static void _MdioNwayStartState(PHY_DEVICE *PhyDev);
4740 +static void _MdioNwayWaitState (PHY_DEVICE *PhyDev);
4741 +
4742 +
4743 +
4744 +#ifndef TRUE
4745 +#define TRUE (1==1)
4746 +#endif
4747 +
4748 +#ifndef FALSE
4749 +#define FALSE (1==2)
4750 +#endif
4751 +
4752 +#define PHY_NOT_FOUND 0xFFFF /* Used in Phy Detection */
4753 +
4754 +/*PhyState breakout */
4755 +
4756 +#define PHY_DEV_OFFSET (0)
4757 +#define PHY_DEV_SIZE (5) /* 5 Bits used */
4758 +#define PHY_DEV_MASK (0x1f<<PHY_DEV_OFFSET)
4759 +
4760 +#define PHY_STATE_OFFSET (PHY_DEV_SIZE+PHY_DEV_OFFSET)
4761 +#define PHY_STATE_SIZE (5) /* 10 Bits used */
4762 +#define PHY_STATE_MASK (0x1f<<PHY_STATE_OFFSET)
4763 + #define INIT (1<<PHY_STATE_OFFSET)
4764 + #define FINDING (2<<PHY_STATE_OFFSET)
4765 + #define FOUND (3<<PHY_STATE_OFFSET)
4766 + #define NWAY_START (4<<PHY_STATE_OFFSET)
4767 + #define NWAY_WAIT (5<<PHY_STATE_OFFSET)
4768 + #define LINK_WAIT (6<<PHY_STATE_OFFSET)
4769 + #define LINKED (7<<PHY_STATE_OFFSET)
4770 + #define LOOPBACK (8<<PHY_STATE_OFFSET)
4771 +
4772 +#define PHY_SPEED_OFFSET (PHY_STATE_OFFSET+PHY_STATE_SIZE)
4773 +#define PHY_SPEED_SIZE (1) /* 11 Bits used */
4774 +#define PHY_SPEED_MASK (1<<PHY_SPEED_OFFSET)
4775 +
4776 +#define PHY_DUPLEX_OFFSET (PHY_SPEED_OFFSET+PHY_SPEED_SIZE)
4777 +#define PHY_DUPLEX_SIZE (1) /* 12 Bits used */
4778 +#define PHY_DUPLEX_MASK (1<<PHY_DUPLEX_OFFSET)
4779 +
4780 +#define PHY_TIM_OFFSET (PHY_DUPLEX_OFFSET+PHY_DUPLEX_SIZE)
4781 +#define PHY_TIM_SIZE (10) /* 22 Bits used */
4782 +#define PHY_TIM_MASK (0x3ff<<PHY_TIM_OFFSET)
4783 + #define PHY_FIND_TO ( 2<<PHY_TIM_OFFSET)
4784 + #define PHY_RECK_TO (200<<PHY_TIM_OFFSET)
4785 + #define PHY_LINK_TO (500<<PHY_TIM_OFFSET)
4786 + #define PHY_NWST_TO (500<<PHY_TIM_OFFSET)
4787 + #define PHY_NWDN_TO (800<<PHY_TIM_OFFSET)
4788 + #define PHY_MDIX_TO (274<<PHY_TIM_OFFSET) /* 2.74 Seconds <--Spec and empirical */
4789 +
4790 +#define PHY_SMODE_OFFSET (PHY_TIM_OFFSET+PHY_TIM_SIZE)
4791 +#define PHY_SMODE_SIZE (5) /* 27 Bits used */
4792 +#define PHY_SMODE_MASK (0x1f<<PHY_SMODE_OFFSET)
4793 + #define SMODE_AUTO (0x10<<PHY_SMODE_OFFSET)
4794 + #define SMODE_FD100 (0x08<<PHY_SMODE_OFFSET)
4795 + #define SMODE_HD100 (0x04<<PHY_SMODE_OFFSET)
4796 + #define SMODE_FD10 (0x02<<PHY_SMODE_OFFSET)
4797 + #define SMODE_HD10 (0x01<<PHY_SMODE_OFFSET)
4798 + #define SMODE_ALL (0x1f<<PHY_SMODE_OFFSET)
4799 +
4800 +#define PHY_CHNG_OFFSET (PHY_SMODE_OFFSET+PHY_SMODE_SIZE)
4801 +#define PHY_CHNG_SIZE (1) /* 28 Bits used */
4802 +#define PHY_CHNG_MASK (1<<PHY_CHNG_OFFSET)
4803 + #define PHY_CHANGE (1<<PHY_CHNG_OFFSET)
4804 +
4805 +#define PHY_TIMEDOUT_OFFSET (PHY_CHNG_OFFSET+PHY_CHNG_SIZE)
4806 +#define PHY_TIMEDOUT_SIZE (1) /* 29 Bits used */
4807 +#define PHY_TIMEDOUT_MASK (1<<PHY_TIMEDOUT_OFFSET)
4808 + #define PHY_MDIX_SWITCH (1<<PHY_TIMEDOUT_OFFSET)
4809 +
4810 +#define PHY_MDIX_OFFSET (PHY_TIMEDOUT_OFFSET+PHY_TIMEDOUT_SIZE)
4811 +#define PHY_MDIX_SIZE (1) /* 30 Bits used */
4812 +#define PHY_MDIX_MASK (1<<PHY_MDIX_OFFSET)
4813 + #define PHY_MDIX (1<<PHY_MDIX_OFFSET)
4814 +
4815 +static char *lstate[]={"NULL","INIT","FINDING","FOUND","NWAY_START","NWAY_WAIT","LINK_WAIT","LINKED", "LOOPBACK"};
4816 +static int cpMacDebug;
4817 +
4818 +/* Local MDIO Register Macros */
4819 +
4820 +#define myMDIO_ALIVE MDIO_ALIVE (PhyDev->miibase)
4821 +#define myMDIO_CONTROL MDIO_CONTROL (PhyDev->miibase)
4822 +#define myMDIO_LINK MDIO_LINK (PhyDev->miibase)
4823 +#define myMDIO_LINKINT MDIO_LINKINT (PhyDev->miibase)
4824 +#define myMDIO_USERACCESS MDIO_USERACCESS(PhyDev->miibase, PhyDev->inst)
4825 +#define myMDIO_USERPHYSEL MDIO_USERPHYSEL(PhyDev->miibase, PhyDev->inst)
4826 +#define myMDIO_VER MDIO_VER (PhyDev->miibase)
4827 +
4828 +#ifndef VOLATILE32
4829 +#define VOLATILE32(addr) (*((volatile bit32u *)(addr)))
4830 +#endif
4831 +
4832 +/************************************
4833 +***
4834 +*** Delays at least ClockWait cylces
4835 +*** before returning
4836 +***
4837 +**************************************/
4838 +void _mdioDelayEmulate(PHY_DEVICE *PhyDev, int ClockWait)
4839 + {
4840 +#ifdef _CPHAL_CPMAC /*+RC3.02*/
4841 + HAL_DEVICE *HalDev = PhyDev->HalDev; /*+RC3.02*/
4842 + osfuncSleep((int*)&ClockWait); /*+RC3.02*/
4843 +#else /*+RC3.02*/
4844 + volatile bit32u i=0;
4845 + while(ClockWait--)
4846 + {
4847 + i |= myMDIO_LINK; /* MDIO register access to burn cycles */
4848 + }
4849 +#endif
4850 + }
4851 +
4852 +void _mdioWaitForAccessComplete(PHY_DEVICE *PhyDev)
4853 + {
4854 + while((myMDIO_USERACCESS & MDIO_USERACCESS_GO)!=0)
4855 + {
4856 + }
4857 + }
4858 +
4859 +void _mdioUserAccess(PHY_DEVICE *PhyDev, bit32u method, bit32u regadr, bit32u phyadr, bit32u data)
4860 + {
4861 + bit32u control;
4862 +
4863 + control = MDIO_USERACCESS_GO |
4864 + (method) |
4865 + (((regadr) << 21) & MDIO_USERACCESS_REGADR) |
4866 + (((phyadr) << 16) & MDIO_USERACCESS_PHYADR) |
4867 + ((data) & MDIO_USERACCESS_DATA);
4868 +
4869 + myMDIO_USERACCESS = control;
4870 + }
4871 +
4872 +
4873 +
4874 +/************************************
4875 +***
4876 +*** Waits for MDIO_USERACCESS to be ready and reads data
4877 +*** If 'WaitForData' set, waits for read to complete and returns Data,
4878 +*** otherwise returns 0
4879 +*** Note: 'data' is 16 bits but we use 32 bits
4880 +*** to be consistent with rest of the code.
4881 +***
4882 +**************************************/
4883 +bit32u _mdioUserAccessRead(PHY_DEVICE *PhyDev, bit32u regadr, bit32u phyadr)
4884 + {
4885 +
4886 + _mdioWaitForAccessComplete(PhyDev); /* Wait until UserAccess ready */
4887 + _mdioUserAccess(PhyDev, MDIO_USERACCESS_READ, regadr, phyadr, 0);
4888 + _mdioWaitForAccessComplete(PhyDev); /* Wait for Read to complete */
4889 +
4890 + return(myMDIO_USERACCESS & MDIO_USERACCESS_DATA);
4891 + }
4892 +
4893 +
4894 +/************************************
4895 +***
4896 +*** Waits for MDIO_USERACCESS to be ready and writes data
4897 +***
4898 +**************************************/
4899 +void _mdioUserAccessWrite(PHY_DEVICE *PhyDev, bit32u regadr, bit32u phyadr, bit32u data)
4900 + {
4901 + _mdioWaitForAccessComplete(PhyDev); /* Wait until UserAccess ready */
4902 + _mdioUserAccess(PhyDev, MDIO_USERACCESS_WRITE, regadr, phyadr, data);
4903 + }
4904 +
4905 +void _mdioDumpPhyDetailed(PHY_DEVICE *PhyDev)
4906 +{
4907 + bit32u *PhyState = &PhyDev->PhyState;
4908 + bit32u PhyNum;
4909 + int RegData;
4910 +
4911 + PhyNum=(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
4912 +
4913 + RegData = _mdioUserAccessRead(PhyDev, 0, PhyNum);
4914 + mdioPrintf("PhyControl: %04X, Lookback=%s, Speed=%s, Duplex=%s\n",
4915 + RegData,
4916 + RegData&PHY_LOOP?"On":"Off",
4917 + RegData&PHY_100?"100":"10",
4918 + RegData&PHY_FD?"Full":"Half");
4919 + RegData = _mdioUserAccessRead(PhyDev, 1, PhyNum);
4920 + mdioPrintf("PhyStatus: %04X, AutoNeg=%s, Link=%s\n",
4921 + RegData,
4922 + RegData&NWAY_COMPLETE?"Complete":"NotComplete",
4923 + RegData&PHY_LINKED?"Up":"Down");
4924 + RegData = _mdioUserAccessRead(PhyDev, 4, PhyNum);
4925 + mdioPrintf("PhyMyCapability: %04X, 100FD=%s, 100HD=%s, 10FD=%s, 10HD=%s\n",
4926 + RegData,
4927 + RegData&NWAY_FD100?"Yes":"No",
4928 + RegData&NWAY_HD100?"Yes":"No",
4929 + RegData&NWAY_FD10?"Yes":"No",
4930 + RegData&NWAY_HD10?"Yes":"No");
4931 +
4932 + RegData = _mdioUserAccessRead(PhyDev, 5, PhyNum);
4933 + mdioPrintf("PhyPartnerCapability: %04X, 100FD=%s, 100HD=%s, 10FD=%s, 10HD=%s\n",
4934 + RegData,
4935 + RegData&NWAY_FD100?"Yes":"No",
4936 + RegData&NWAY_HD100?"Yes":"No",
4937 + RegData&NWAY_FD10?"Yes":"No",
4938 + RegData&NWAY_HD10?"Yes":"No");
4939 +}
4940 +void _mdioDumpPhy(PHY_DEVICE *PhyDev, bit32u p)
4941 + {
4942 + bit32u j,n,PhyAcks;
4943 + bit32u PhyRegAddr;
4944 + bit32u phy_num;
4945 + bit32u PhyMask = PhyDev->PhyMask;
4946 +
4947 + PhyAcks=myMDIO_ALIVE;
4948 + PhyAcks&=PhyMask; /* Only interested in 'our' Phys */
4949 +
4950 + for(phy_num=0,j=1;phy_num<32;phy_num++,j<<=1)
4951 + {
4952 + if (PhyAcks&j)
4953 + {
4954 + mdioPrintf("%2d%s:",phy_num,(phy_num==p)?">":" ");
4955 + for(PhyRegAddr=0;PhyRegAddr<6;PhyRegAddr++)
4956 + {
4957 + n = _mdioUserAccessRead(PhyDev, PhyRegAddr, phy_num);
4958 + mdioPrintf(" %04x",n&0x0ffff);
4959 + }
4960 + mdioPrintf("\n");
4961 + }
4962 + }
4963 + _mdioDumpPhyDetailed(PhyDev);
4964 + }
4965 +
4966 +void _mdioDumpState(PHY_DEVICE *PhyDev)
4967 + {
4968 + bit32u state = PhyDev->PhyState;
4969 +
4970 + if (!cpMacDebug) return;
4971 +
4972 + mdioPrintf("Phy: %d, ",(state&PHY_DEV_MASK)>>PHY_DEV_OFFSET);
4973 + mdioPrintf("State: %d/%s, ",(state&PHY_STATE_MASK)>>PHY_STATE_OFFSET,lstate[(state&PHY_STATE_MASK)>>PHY_STATE_OFFSET]);
4974 + mdioPrintf("Speed: %d, ",(state&PHY_SPEED_MASK)>>PHY_SPEED_OFFSET);
4975 + mdioPrintf("Dup: %d, ",(state&PHY_DUPLEX_MASK)>>PHY_DUPLEX_OFFSET);
4976 + mdioPrintf("Tim: %d, ",(state&PHY_TIM_MASK)>>PHY_TIM_OFFSET);
4977 + mdioPrintf("SMode: %d, ",(state&PHY_SMODE_MASK)>>PHY_SMODE_OFFSET);
4978 + mdioPrintf("Chng: %d",(state&PHY_CHNG_MASK)>>PHY_CHNG_OFFSET);
4979 + mdioPrintf("\n");
4980 +
4981 + if (((state&PHY_STATE_MASK)!=FINDING)&&((state&PHY_STATE_MASK)!=INIT))
4982 + _mdioDumpPhy(PhyDev, (state&PHY_DEV_MASK)>>PHY_DEV_OFFSET);
4983 + }
4984 +
4985 +
4986 +void _mdioResetPhy(PHY_DEVICE *PhyDev,bit32u PhyNum)
4987 + {
4988 + bit16u PhyControlReg;
4989 +
4990 + _mdioUserAccessWrite(PhyDev, PHY_CONTROL_REG, PhyNum, PHY_RESET);
4991 + if (cpMacDebug)
4992 + mdioPrintf("cpMacMdioPhYReset(%d)\n",PhyNum);
4993 +
4994 + /* Read control register until Phy Reset is complete */
4995 + do
4996 + {
4997 + PhyControlReg = _mdioUserAccessRead(PhyDev, PHY_CONTROL_REG, PhyNum);
4998 + }
4999 + while (PhyControlReg & PHY_RESET); /* Wait for Reset to clear */
5000 + }
5001 +
5002 +void _mdioDisablePhy(PHY_DEVICE *PhyDev,bit32u PhyNum)
5003 + {
5004 + _mdioUserAccessWrite(PhyDev, PHY_CONTROL_REG, PhyNum, PHY_ISOLATE|PHY_PDOWN);
5005 +
5006 + if (cpMacDebug)
5007 + mdioPrintf("cpMacMdioDisablePhy(%d)\n",PhyNum);
5008 +
5009 + }
5010 +
5011 +void _MdioInitState(PHY_DEVICE *PhyDev)
5012 + {
5013 + bit32u *PhyState = &PhyDev->PhyState;
5014 + bit32u CurrentState;
5015 +
5016 + CurrentState=*PhyState;
5017 + CurrentState=(CurrentState&~PHY_TIM_MASK)|(PHY_FIND_TO);
5018 + CurrentState=(CurrentState&~PHY_STATE_MASK)|(FINDING);
5019 + CurrentState=(CurrentState&~PHY_SPEED_MASK);
5020 + CurrentState=(CurrentState&~PHY_DUPLEX_MASK);
5021 + CurrentState|=PHY_CHANGE;
5022 +
5023 + *PhyState=CurrentState;
5024 +
5025 + }
5026 +
5027 +void _MdioFindingState(PHY_DEVICE *PhyDev)
5028 + {
5029 + bit32u *PhyState = &PhyDev->PhyState;
5030 + bit32u PhyMask = PhyDev->PhyMask;
5031 + bit32u PhyNum,i,j,PhyAcks;
5032 +
5033 +
5034 + PhyNum=PHY_NOT_FOUND;
5035 +
5036 + if (*PhyState&PHY_TIM_MASK)
5037 + {
5038 + *PhyState=(*PhyState&~PHY_TIM_MASK)|((*PhyState&PHY_TIM_MASK)-(1<<PHY_TIM_OFFSET));
5039 + }
5040 + else
5041 + {
5042 + PhyAcks=myMDIO_ALIVE;
5043 + PhyAcks&=PhyMask; /* Only interested in 'our' Phys */
5044 +
5045 + for(i=0,j=1;(i<32)&&((j&PhyAcks)==0);i++,j<<=1);
5046 +
5047 + if ((PhyAcks)&&(i<32)) PhyNum=i;
5048 + if (PhyNum!=PHY_NOT_FOUND)
5049 + {
5050 + /* Phy Found! */
5051 + *PhyState=(*PhyState&~PHY_DEV_MASK)|((PhyNum&PHY_DEV_MASK)<<PHY_DEV_OFFSET);
5052 + *PhyState=(*PhyState&~PHY_STATE_MASK)|(FOUND);
5053 + *PhyState|=PHY_CHANGE;
5054 + if (cpMacDebug)
5055 + mdioPrintf("cpMacMdioFindingState: PhyNum: %d\n",PhyNum);
5056 + }
5057 + else
5058 + {
5059 + if (cpMacDebug)
5060 + mdioPrintf("cpMacMdioFindingState: Timed Out looking for a Phy!\n");
5061 + *PhyState|=PHY_RECK_TO; /* This state currently has no support?*/
5062 + }
5063 + }
5064 + }
5065 +
5066 +void _MdioFoundState(PHY_DEVICE *PhyDev)
5067 + {
5068 + bit32u *PhyState = &PhyDev->PhyState;
5069 + bit32u PhyMask = PhyDev->PhyMask;
5070 + bit32u MLinkMask = PhyDev->MLinkMask;
5071 + bit32u PhyNum,PhyStatus,NWAYadvertise,m,phynum,i,j,PhyAcks;
5072 + bit32u PhySel;
5073 +
5074 + if ((*PhyState&PHY_SMODE_MASK)==0) return;
5075 +
5076 + PhyNum=(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
5077 +
5078 + PhyAcks=myMDIO_ALIVE;
5079 + PhyAcks&=PhyMask; /* Only interested in 'our' Phys */
5080 +
5081 + /* Will now isolate all our Phys, except the one we have decided to use */
5082 + for(phynum=0,j=1;phynum<32;phynum++,j<<=1)
5083 + {
5084 + if (PhyAcks&j)
5085 + {
5086 + if (phynum!=PhyNum) /* Do not disabled Found Phy */
5087 + _mdioDisablePhy(PhyDev,phynum);
5088 + }
5089 + }
5090 +
5091 + /* Reset the Phy and proceed with auto-negotiation */
5092 + _mdioResetPhy(PhyDev,PhyNum);
5093 +
5094 + /* Now setup the MDIOUserPhySel register */
5095 +
5096 + PhySel=PhyNum; /* Set the phy address */
5097 +
5098 + /* Set the way Link will be Monitored */
5099 + /* Check the Link Selection Method */
5100 + if ((1 << PhyNum) & MLinkMask)
5101 + PhySel |= MDIO_USERPHYSEL_LINKSEL;
5102 +
5103 + myMDIO_USERPHYSEL = PhySel; /* update PHYSEL */
5104 +
5105 + /* Get the Phy Status */
5106 + PhyStatus = _mdioUserAccessRead(PhyDev, PHY_STATUS_REG, PhyNum);
5107 +
5108 +
5109 +#ifdef _CPHAL_CPMAC
5110 + /* For Phy Internal loopback test, need to wait until Phy
5111 + found, then set Loopback */
5112 + if (PhyDev->HalDev->MdioConnect & _CPMDIO_LOOPBK)
5113 + {
5114 + /* Set Phy in Loopback */
5115 + _mdioUserAccessWrite(PhyDev, PHY_CONTROL_REG, PhyNum, PHY_LOOP|PHY_FD);
5116 + /* Do a read to ensure PHY_LOOP has completed */
5117 + _mdioUserAccessRead(PhyDev, PHY_STATUS_REG, PhyNum);
5118 + *PhyState=(*PhyState&~PHY_STATE_MASK)|(LOOPBACK);
5119 + *PhyState|=PHY_CHANGE;
5120 + return;
5121 + }
5122 +#endif
5123 +
5124 +
5125 + if (cpMacDebug)
5126 + mdioPrintf("Enable Phy to negotiate external connection\n");
5127 +
5128 + NWAYadvertise=NWAY_SEL;
5129 + if (*PhyState&SMODE_FD100) NWAYadvertise|=NWAY_FD100;
5130 + if (*PhyState&SMODE_HD100) NWAYadvertise|=NWAY_HD100;
5131 + if (*PhyState&SMODE_FD10) NWAYadvertise|=NWAY_FD10;
5132 + if (*PhyState&SMODE_HD10) NWAYadvertise|=NWAY_HD10;
5133 +
5134 + *PhyState&=~(PHY_TIM_MASK|PHY_STATE_MASK);
5135 + if ((PhyStatus&NWAY_CAPABLE)&&(*PhyState&SMODE_AUTO)) /*NWAY Phy Detected*/
5136 + {
5137 + /*For NWAY compliant Phys */
5138 +
5139 + _mdioUserAccessWrite(PhyDev, NWAY_ADVERTIZE_REG, PhyNum, NWAYadvertise);
5140 +
5141 + if (cpMacDebug)
5142 + {
5143 + mdioPrintf("NWAY Advertising: ");
5144 + if (NWAYadvertise&NWAY_FD100) mdioPrintf("FullDuplex-100 ");
5145 + if (NWAYadvertise&NWAY_HD100) mdioPrintf("HalfDuplex-100 ");
5146 + if (NWAYadvertise&NWAY_FD10) mdioPrintf("FullDuplex-10 ");
5147 + if (NWAYadvertise&NWAY_HD10) mdioPrintf("HalfDuplex-10 ");
5148 + mdioPrintf("\n");
5149 + }
5150 +
5151 + _mdioUserAccessWrite(PhyDev, PHY_CONTROL_REG, PhyNum, AUTO_NEGOTIATE_EN);
5152 +
5153 + _mdioUserAccessWrite(PhyDev, PHY_CONTROL_REG, PhyNum, AUTO_NEGOTIATE_EN|RENEGOTIATE);
5154 +
5155 + *PhyState|=PHY_CHANGE|PHY_NWST_TO|NWAY_START;
5156 + }
5157 + else
5158 + {
5159 + *PhyState&=~SMODE_AUTO; /*The Phy is not capable of auto negotiation! */
5160 + m=NWAYadvertise;
5161 + for(j=0x8000,i=0;(i<16)&&((j&m)==0);i++,j>>=1);
5162 + m=j;
5163 + j=0;
5164 + if (m&(NWAY_FD100|NWAY_HD100))
5165 + {
5166 + j=PHY_100;
5167 + m&=(NWAY_FD100|NWAY_HD100);
5168 + }
5169 + if (m&(NWAY_FD100|NWAY_FD10))
5170 + j |= PHY_FD;
5171 + if (cpMacDebug)
5172 + mdioPrintf("Requested PHY mode %s Duplex %s Mbps\n",(j&PHY_FD)?"Full":"Half",(j&PHY_100)?"100":"10");
5173 + _mdioUserAccessWrite(PhyDev, PHY_CONTROL_REG, PhyNum, j);
5174 + *PhyState&=~PHY_SPEED_MASK;
5175 + if (j&PHY_100)
5176 + *PhyState|=(1<<PHY_SPEED_OFFSET);
5177 + *PhyState&=~PHY_DUPLEX_MASK;
5178 + if (j&PHY_FD)
5179 + *PhyState|=(1<<PHY_DUPLEX_OFFSET);
5180 + *PhyState|=PHY_CHANGE|PHY_LINK_TO|LINK_WAIT;
5181 + }
5182 + _mdioMdixDelay(PhyDev); /* If AutoMdix add delay */
5183 + }
5184 +
5185 +void _MdioNwayStartState(PHY_DEVICE *PhyDev)
5186 + {
5187 + bit32u *PhyState = &PhyDev->PhyState;
5188 + bit32u PhyNum,PhyMode;
5189 +
5190 + PhyNum=(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
5191 +
5192 + /*Wait for Negotiation to start */
5193 +
5194 + PhyMode=_mdioUserAccessRead(PhyDev, PHY_CONTROL_REG, PhyNum);
5195 +
5196 + if((PhyMode&RENEGOTIATE)==0)
5197 + {
5198 + _mdioUserAccessRead(PhyDev, PHY_STATUS_REG, PhyNum); /*Flush pending latch bits*/
5199 + *PhyState&=~(PHY_STATE_MASK|PHY_TIM_MASK);
5200 + *PhyState|=PHY_CHANGE|NWAY_WAIT|PHY_NWDN_TO;
5201 + _mdioMdixDelay(PhyDev); /* If AutoMdix add delay */
5202 + }
5203 + else
5204 + {
5205 + if (*PhyState&PHY_TIM_MASK)
5206 + *PhyState=(*PhyState&~PHY_TIM_MASK)|((*PhyState&PHY_TIM_MASK)-(1<<PHY_TIM_OFFSET));
5207 + else
5208 + _mdioPhyTimeOut(PhyDev);
5209 + }
5210 + }
5211 +
5212 +void _MdioNwayWaitState(PHY_DEVICE *PhyDev)
5213 + {
5214 + bit32u *PhyState = &PhyDev->PhyState;
5215 + bit32u PhyNum,PhyStatus,NWAYadvertise,NWAYREadvertise,NegMode,i,j;
5216 +
5217 + PhyNum=(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
5218 +
5219 + PhyStatus=_mdioUserAccessRead(PhyDev, PHY_STATUS_REG, PhyNum);
5220 +
5221 + if (PhyStatus&NWAY_COMPLETE)
5222 + {
5223 + *PhyState|=PHY_CHANGE;
5224 + *PhyState&=~PHY_SPEED_MASK;
5225 + *PhyState&=~PHY_DUPLEX_MASK;
5226 +
5227 + NWAYadvertise =_mdioUserAccessRead(PhyDev, NWAY_ADVERTIZE_REG, PhyNum);
5228 + NWAYREadvertise =_mdioUserAccessRead(PhyDev, NWAY_REMADVERTISE_REG, PhyNum);
5229 +
5230 + /* Negotiated mode is we and the remote have in common */
5231 + NegMode = NWAYadvertise & NWAYREadvertise;
5232 +
5233 + if (cpMacDebug)
5234 + {
5235 + mdioPrintf("Phy: %d, ",(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET);
5236 + mdioPrintf("NegMode %04X, NWAYadvertise %04X, NWAYREadvertise %04X\n",
5237 + NegMode, NWAYadvertise, NWAYREadvertise);
5238 + }
5239 +
5240 + /* Limit negotiation to fields below */
5241 + NegMode &= (NWAY_FD100|NWAY_HD100|NWAY_FD10|NWAY_HD10);
5242 +
5243 + if (NegMode==0)
5244 + {
5245 + NegMode=(NWAY_HD100|NWAY_HD10)&NWAYadvertise; /*or 10 ?? who knows, Phy is not MII compliant*/
5246 + if(cpMacDebug)
5247 + {
5248 + mdioPrintf("Mdio:WARNING: Negotiation complete but NO agreement, default is HD\n");
5249 + _mdioDumpPhyDetailed(PhyDev);
5250 + }
5251 + }
5252 + for(j=0x8000,i=0;(i<16)&&((j&NegMode)==0);i++,j>>=1);
5253 +
5254 +
5255 + NegMode=j;
5256 + if (cpMacDebug)
5257 + {
5258 + mdioPrintf("Negotiated connection: ");
5259 + if (NegMode&NWAY_FD100) mdioPrintf("FullDuplex 100 Mbs\n");
5260 + if (NegMode&NWAY_HD100) mdioPrintf("HalfDuplex 100 Mbs\n");
5261 + if (NegMode&NWAY_FD10) mdioPrintf("FullDuplex 10 Mbs\n");
5262 + if (NegMode&NWAY_HD10) mdioPrintf("HalfDuplex 10 Mbs\n");
5263 + }
5264 + if (NegMode!=0)
5265 + {
5266 + if (PhyStatus&PHY_LINKED)
5267 + *PhyState=(*PhyState&~PHY_STATE_MASK)|LINKED;
5268 + else
5269 + *PhyState=(*PhyState&~PHY_STATE_MASK)|LINK_WAIT;
5270 + if (NegMode&(NWAY_FD100|NWAY_HD100))
5271 + *PhyState=(*PhyState&~PHY_SPEED_MASK)|(1<<PHY_SPEED_OFFSET);
5272 + if (NegMode&(NWAY_FD100|NWAY_FD10))
5273 + *PhyState=(*PhyState&~PHY_DUPLEX_MASK)|(1<<PHY_DUPLEX_OFFSET);
5274 + }
5275 + }
5276 + else
5277 + {
5278 + if (*PhyState&PHY_TIM_MASK)
5279 + *PhyState=(*PhyState&~PHY_TIM_MASK)|((*PhyState&PHY_TIM_MASK)-(1<<PHY_TIM_OFFSET));
5280 + else
5281 + _mdioPhyTimeOut(PhyDev);
5282 + }
5283 + }
5284 +
5285 +void _MdioLinkWaitState(PHY_DEVICE *PhyDev)
5286 + {
5287 + bit32u *PhyState = &PhyDev->PhyState;
5288 + bit32u PhyStatus;
5289 + bit32u PhyNum;
5290 +
5291 + PhyNum=(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
5292 +
5293 + PhyStatus=_mdioUserAccessRead(PhyDev, PHY_STATUS_REG, PhyNum);
5294 +
5295 + if (PhyStatus&PHY_LINKED)
5296 + {
5297 + *PhyState=(*PhyState&~PHY_STATE_MASK)|LINKED;
5298 + *PhyState|=PHY_CHANGE;
5299 + }
5300 + else
5301 + {
5302 + if (*PhyState&PHY_TIM_MASK)
5303 + *PhyState=(*PhyState&~PHY_TIM_MASK)|((*PhyState&PHY_TIM_MASK)-(1<<PHY_TIM_OFFSET));
5304 + else
5305 + _mdioPhyTimeOut(PhyDev);
5306 + }
5307 + }
5308 +
5309 +void _mdioPhyTimeOut(PHY_DEVICE *PhyDev)
5310 + {
5311 + bit32u *PhyState;
5312 +
5313 + if(_mdioMdixSupported(PhyDev) == 0)
5314 + return; /* AutoMdix not supported */
5315 +
5316 + PhyState = &PhyDev->PhyState;
5317 +
5318 + /* Indicate MDI/MDIX mode switch is needed */
5319 + *PhyState|=PHY_MDIX_SWITCH;
5320 +
5321 + /* Toggle the MDIX mode indicatir */
5322 + if(*PhyState & PHY_MDIX)
5323 + *PhyState &= ~PHY_MDIX_MASK; /* Current State is MDIX, set to MDI */
5324 + else
5325 + *PhyState |= PHY_MDIX_MASK; /* Current State is MDI, set to MDIX */
5326 +
5327 + /* Reset state machine to FOUND */
5328 + *PhyState=(*PhyState&~PHY_STATE_MASK)|(FOUND);
5329 + }
5330 +
5331 +void _MdioLoopbackState(PHY_DEVICE *PhyDev)
5332 + {
5333 + return;
5334 + }
5335 +
5336 +void _MdioLinkedState(PHY_DEVICE *PhyDev)
5337 + {
5338 + bit32u *PhyState = &PhyDev->PhyState;
5339 + bit32u PhyNum = (*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
5340 +
5341 + if (myMDIO_LINK&(1<<PhyNum)) return; /* if still Linked, exit*/
5342 +
5343 + /* Not Linked */
5344 + *PhyState&=~(PHY_STATE_MASK|PHY_TIM_MASK);
5345 + if (*PhyState&SMODE_AUTO)
5346 + *PhyState|=PHY_CHANGE|NWAY_WAIT|PHY_NWDN_TO;
5347 + else
5348 + *PhyState|=PHY_CHANGE|PHY_LINK_TO|LINK_WAIT;
5349 +
5350 + _mdioMdixDelay(PhyDev); /* If AutoMdix add delay */
5351 + }
5352 +
5353 +void _MdioDefaultState(PHY_DEVICE *PhyDev)
5354 + {
5355 + bit32u *PhyState = &PhyDev->PhyState;
5356 + /*Awaiting a cpMacMdioInit call */
5357 + *PhyState|=PHY_CHANGE;
5358 + }
5359 +
5360 +
5361 +/*User Calls********************************************************* */
5362 +
5363 +void cpMacMdioClose(PHY_DEVICE *PhyDev, int Full)
5364 + {
5365 + }
5366 +
5367 +
5368 +int cpMacMdioInit(PHY_DEVICE *PhyDev, bit32u miibase, bit32u inst, bit32u PhyMask, bit32u MLinkMask, bit32u MdixMask, bit32u ResetReg, bit32u ResetBit, bit32u MdioBusFreq, bit32u MdioClockFreq, int verbose, void *Info)
5369 + {
5370 + bit32u HighestChannel;
5371 + bit32u ControlState;
5372 + bit32u *PhyState = &PhyDev->PhyState;
5373 + bit32u clkdiv; /*MJH+030328*/
5374 +
5375 + cpMacDebug=verbose;
5376 +
5377 + PhyDev->miibase = miibase;
5378 + PhyDev->inst = inst;
5379 + PhyDev->PhyMask = PhyMask;
5380 + PhyDev->MLinkMask = MLinkMask;
5381 + PhyDev->MdixMask = MdixMask;
5382 +#ifdef _CPHAL_CPMAC
5383 + PhyDev->HalDev = (HAL_DEVICE*) Info;
5384 +#endif
5385 +
5386 + *PhyState &= ~PHY_MDIX_MASK; /* Set initial State to MDI */
5387 +
5388 + /* Check that the channel supplied is within range */
5389 + HighestChannel = (myMDIO_CONTROL & MDIO_CONTROL_HIGHEST_USER_CHANNEL) > 8;
5390 + if(inst > HighestChannel)
5391 + return(HighestChannel);
5392 +
5393 + /*Setup MII MDIO access regs */
5394 +
5395 + /* Calculate the correct value for the mclkdiv */
5396 + /* See PITS #14 */
5397 + if (MdioClockFreq) /*MJH+030402*/
5398 + clkdiv = (MdioBusFreq / MdioClockFreq) - 1; /*MJH+030402*/
5399 + else /*MJH+030402*/
5400 + clkdiv = 0xFF; /*MJH+030402*/
5401 +
5402 + ControlState = MDIO_CONTROL_ENABLE;
5403 + ControlState |= (clkdiv & MDIO_CONTROL_CLKDIV); /*MJH+030328*/
5404 +
5405 + /*
5406 + If mii is not out of reset or if the Control Register is not set correctly
5407 + then initalize
5408 + */
5409 + if( !(VOLATILE32(ResetReg) & (1 << ResetBit)) ||
5410 + ((myMDIO_CONTROL & (MDIO_CONTROL_CLKDIV | MDIO_CONTROL_ENABLE)) != ControlState) )/*GSG~030404*/
5411 + {
5412 + /* MII not setup, Setup initial condition */
5413 + VOLATILE32(ResetReg) &= ~(1 << ResetBit);
5414 + _mdioDelayEmulate(PhyDev, 64);
5415 + VOLATILE32(ResetReg) |= (1 << ResetBit); /* take mii out of reset */
5416 + _mdioDelayEmulate(PhyDev, 64);
5417 + myMDIO_CONTROL = ControlState; /* Enable MDIO */
5418 + }
5419 +
5420 + *PhyState=INIT;
5421 +
5422 + if (cpMacDebug)
5423 + mdioPrintf("cpMacMdioInit\n");
5424 + _mdioDumpState(PhyDev);
5425 + return(0);
5426 + }
5427 +
5428 +void cpMacMdioSetPhyMode(PHY_DEVICE *PhyDev,bit32u PhyMode)
5429 + {
5430 + bit32u *PhyState = &PhyDev->PhyState;
5431 + bit32u CurrentState;
5432 +
5433 + PhyDev->PhyMode = PhyMode; /* used for AUTOMIDX, planned to replace PhyState fields */
5434 +
5435 + *PhyState&=~PHY_SMODE_MASK;
5436 +
5437 + if (PhyMode&NWAY_AUTO) *PhyState|=SMODE_AUTO;
5438 + if (PhyMode&NWAY_FD100) *PhyState|=SMODE_FD100;
5439 + if (PhyMode&NWAY_HD100) *PhyState|=SMODE_HD100;
5440 + if (PhyMode&NWAY_FD10) *PhyState|=SMODE_FD10;
5441 + if (PhyMode&NWAY_HD10) *PhyState|=SMODE_HD10;
5442 +
5443 + CurrentState=*PhyState&PHY_STATE_MASK;
5444 + if ((CurrentState==NWAY_START)||
5445 + (CurrentState==NWAY_WAIT) ||
5446 + (CurrentState==LINK_WAIT) ||
5447 + (CurrentState==LINKED) )
5448 + *PhyState=(*PhyState&~PHY_STATE_MASK)|FOUND|PHY_CHANGE;
5449 + if (cpMacDebug)
5450 + mdioPrintf("cpMacMdioSetPhyMode:%08X Auto:%d, FD10:%d, HD10:%d, FD100:%d, HD100:%d\n", PhyMode,
5451 + PhyMode&NWAY_AUTO, PhyMode&NWAY_FD10, PhyMode&NWAY_HD10, PhyMode&NWAY_FD100,
5452 + PhyMode&NWAY_HD100);
5453 + _mdioDumpState(PhyDev);
5454 + }
5455 +
5456 +/* cpMacMdioTic is called every 10 mili seconds to process Phy states */
5457 +
5458 +int cpMacMdioTic(PHY_DEVICE *PhyDev)
5459 + {
5460 + bit32u *PhyState = &PhyDev->PhyState;
5461 + bit32u CurrentState;
5462 +
5463 + /*Act on current state of the Phy */
5464 +
5465 + CurrentState=*PhyState;
5466 + switch(CurrentState&PHY_STATE_MASK)
5467 + {
5468 + case INIT: _MdioInitState(PhyDev); break;
5469 + case FINDING: _MdioFindingState(PhyDev); break;
5470 + case FOUND: _MdioFoundState(PhyDev); break;
5471 + case NWAY_START: _MdioNwayStartState(PhyDev); break;
5472 + case NWAY_WAIT: _MdioNwayWaitState(PhyDev); break;
5473 + case LINK_WAIT: _MdioLinkWaitState(PhyDev); break;
5474 + case LINKED: _MdioLinkedState(PhyDev); break;
5475 + case LOOPBACK: _MdioLoopbackState(PhyDev); break;
5476 + default: _MdioDefaultState(PhyDev); break;
5477 + }
5478 +
5479 + /*Dump state info if a change has been detected */
5480 +
5481 + if ((CurrentState&~PHY_TIM_MASK)!=(*PhyState&~PHY_TIM_MASK))
5482 + _mdioDumpState(PhyDev);
5483 +
5484 + /* Check is MDI/MDIX mode switch is needed */
5485 + if(*PhyState & PHY_MDIX_SWITCH)
5486 + {
5487 + bit32u Mdix;
5488 +
5489 + *PhyState &= ~PHY_MDIX_SWITCH; /* Clear Mdix Flip indicator */
5490 +
5491 + if(*PhyState & PHY_MDIX)
5492 + Mdix = 1;
5493 + else
5494 + Mdix = 0;
5495 + return(_MIIMDIO_MDIXFLIP|Mdix);
5496 + }
5497 +
5498 + /*Return state change to user */
5499 +
5500 + if (*PhyState&PHY_CHNG_MASK)
5501 + {
5502 + *PhyState&=~PHY_CHNG_MASK;
5503 + return(1);
5504 + }
5505 + else
5506 + return(0);
5507 + }
5508 +
5509 +/* cpMacMdioGetDuplex is called to retrieve the Duplex info */
5510 +
5511 +int cpMacMdioGetDuplex(PHY_DEVICE *PhyDev)
5512 + {
5513 + bit32u *PhyState = &PhyDev->PhyState;
5514 + return((*PhyState&PHY_DUPLEX_MASK)?1:0); /* return 0 or a 1 */
5515 + }
5516 +
5517 +/* cpMacMdioGetSpeed is called to retreive the Speed info */
5518 +
5519 +int cpMacMdioGetSpeed(PHY_DEVICE *PhyDev)
5520 + {
5521 + bit32u *PhyState = &PhyDev->PhyState;
5522 + return(*PhyState&PHY_SPEED_MASK);
5523 + }
5524 +
5525 +/* cpMacMdioGetPhyNum is called to retreive the Phy Device Adr info */
5526 +
5527 +int cpMacMdioGetPhyNum(PHY_DEVICE *PhyDev)
5528 + {
5529 + bit32u *PhyState = &PhyDev->PhyState;
5530 + return((*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET);
5531 + }
5532 +
5533 +/* cpMacMdioGetLoopback is called to Determine if the LOOPBACK state has been reached*/
5534 +
5535 +int cpMacMdioGetLoopback(PHY_DEVICE *PhyDev)
5536 + {
5537 + bit32u *PhyState = &PhyDev->PhyState;
5538 + return((*PhyState&PHY_STATE_MASK)==LOOPBACK);
5539 + }
5540 +/* cpMacMdioGetLinked is called to Determine if the LINKED state has been reached*/
5541 +
5542 +int cpMacMdioGetLinked(PHY_DEVICE *PhyDev)
5543 + {
5544 + bit32u *PhyState = &PhyDev->PhyState;
5545 + return((*PhyState&PHY_STATE_MASK)==LINKED);
5546 + }
5547 +
5548 +void cpMacMdioLinkChange(PHY_DEVICE *PhyDev)
5549 + {
5550 + bit32u *PhyState = &PhyDev->PhyState;
5551 + bit32u PhyNum,PhyStatus;
5552 +
5553 + PhyNum=(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
5554 +
5555 + if (cpMacMdioGetLinked(PhyDev))
5556 + {
5557 + PhyStatus=_mdioUserAccessRead(PhyDev, PHY_STATUS_REG, PhyNum);
5558 +
5559 + if ((PhyStatus&PHY_LINKED)==0)
5560 + {
5561 + *PhyState&=~(PHY_TIM_MASK|PHY_STATE_MASK);
5562 + if (*PhyState&SMODE_AUTO)
5563 + {
5564 + _mdioUserAccessWrite(PhyDev, PHY_CONTROL_REG, PhyNum, AUTO_NEGOTIATE_EN|RENEGOTIATE);
5565 + *PhyState|=PHY_CHANGE|PHY_NWST_TO|NWAY_START;
5566 + }
5567 + else
5568 + {
5569 + *PhyState|=PHY_CHANGE|PHY_LINK_TO|LINK_WAIT;
5570 + }
5571 + }
5572 + }
5573 + }
5574 +
5575 +void cpMacMdioGetVer(bit32u miibase, bit32u *ModID, bit32u *RevMaj, bit32u *RevMin)
5576 + {
5577 + bit32u Ver;
5578 +
5579 + Ver = MDIO_VER(miibase);
5580 +
5581 + *ModID = (Ver & MDIO_VER_MODID) >> 16;
5582 + *RevMaj = (Ver & MDIO_VER_REVMAJ) >> 8;
5583 + *RevMin = (Ver & MDIO_VER_REVMIN);
5584 + }
5585 +
5586 +int cpMacMdioGetPhyDevSize(void)
5587 + {
5588 + return(sizeof(PHY_DEVICE));
5589 + }
5590 +
5591 + /* returns 0 if current Phy has AutoMdix support, otherwise 0 */
5592 +int _mdioMdixSupported(PHY_DEVICE *PhyDev)
5593 + {
5594 + bit32u *PhyState = &PhyDev->PhyState;
5595 + bit32u PhyNum;
5596 +
5597 + if((PhyDev->PhyMode & NWAY_AUTOMDIX) == 0)
5598 + return(0); /* AutoMdix not turned on */
5599 +
5600 + PhyNum=(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
5601 + if( ((1<<PhyNum) & PhyDev->MdixMask) == 0)
5602 + return(0); /* Phy does not support AutoMdix*/
5603 +
5604 + return(1);
5605 + }
5606 +
5607 +/* If current Phy has AutoMdix support add Mdix Delay to the Timer State Value */
5608 +void _mdioMdixDelay(PHY_DEVICE *PhyDev)
5609 + {
5610 + int Delay;
5611 + bit32u *PhyState = &PhyDev->PhyState;
5612 +#ifdef _CPHAL_CPMAC
5613 + HAL_DEVICE *HalDev = PhyDev->HalDev;
5614 +#endif
5615 +
5616 + if(_mdioMdixSupported(PhyDev) == 0)
5617 + return; /* AutoMdix not supported */
5618 +/* Currently only supported when used with the CPMAC */
5619 +#ifdef _CPHAL_CPMAC
5620 + /* Get the Delay value in milli-seconds and convert to ten-milli second value */
5621 + Delay = cpmacRandomRange(HalDev, _AUTOMDIX_DELAY_MIN, _AUTOMDIX_DELAY_MAX);
5622 + Delay /= 10;
5623 +
5624 + /* Add AutoMidx Random Switch Delay to AutoMdix Link Delay */
5625 +
5626 + Delay += (PHY_MDIX_TO>>PHY_TIM_OFFSET);
5627 +
5628 + /* Change Timeout value to AutoMdix standard */
5629 + *PhyState &= ~(PHY_TIM_MASK); /* Clear current Time out value */
5630 + *PhyState |= (Delay<<PHY_TIM_OFFSET); /* Set new value */
5631 +#endif
5632 + }
5633 +
5634 +
5635 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpmdio.h linux-2.4.30/drivers/net/avalanche_cpmac/cpmdio.h
5636 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpmdio.h 1970-01-01 02:00:00.000000000 +0200
5637 +++ linux-2.4.30/drivers/net/avalanche_cpmac/cpmdio.h 2005-04-15 05:10:41.000000000 +0200
5638 @@ -0,0 +1,73 @@
5639 +/*****************************************************************************
5640 +** TNETD53xx Software Support
5641 +** Copyright(c) 2002, Texas Instruments Incorporated. All Rights Reserved.
5642 +**
5643 +** FILE: cpmdio.h User Include for MDIO API Access
5644 +**
5645 +** DESCRIPTION:
5646 +** This include file contains definitions for the the MDIO API
5647 +**
5648 +** HISTORY:
5649 +** 27Mar02 Michael Hanrahan Original (modified from emacmdio.h)
5650 +** 04Apr02 Michael Hanrahan Added Interrupt Support
5651 +*****************************************************************************/
5652 +#ifndef _INC_CPMDIO
5653 +#define _INC_CPMDIO
5654 +
5655 +
5656 +#ifndef __CPHAL_CPMDIO
5657 +typedef void PHY_DEVICE;
5658 +#endif
5659 +
5660 +
5661 +/*Version Information */
5662 +
5663 +void cpMacMdioGetVer(bit32u miiBase, bit32u *ModID, bit32u *RevMaj, bit32u *RevMin);
5664 +
5665 +/*Called once at the begining of time */
5666 +
5667 +int cpMacMdioInit(PHY_DEVICE *PhyDev, bit32u miibase, bit32u inst, bit32u PhyMask, bit32u MLinkMask, bit32u MdixMask, bit32u ResetBase, bit32u ResetBit, bit32u MdioBusFreq, bit32u MdioClockFreq, int verbose, void *Info);
5668 +int cpMacMdioGetPhyDevSize(void);
5669 +
5670 +
5671 +/*Called every 10 mili Seconds, returns TRUE if there has been a mode change */
5672 +
5673 +int cpMacMdioTic(PHY_DEVICE *PhyDev);
5674 +
5675 +/*Called to set Phy mode */
5676 +
5677 +void cpMacMdioSetPhyMode(PHY_DEVICE *PhyDev,bit32u PhyMode);
5678 +
5679 +/*Calls to retreive info after a mode change! */
5680 +
5681 +int cpMacMdioGetDuplex(PHY_DEVICE *PhyDev);
5682 +int cpMacMdioGetSpeed(PHY_DEVICE *PhyDev);
5683 +int cpMacMdioGetPhyNum(PHY_DEVICE *PhyDev);
5684 +int cpMacMdioGetLinked(PHY_DEVICE *PhyDev);
5685 +void cpMacMdioLinkChange(PHY_DEVICE *PhyDev);
5686 +
5687 +/* Shot Down */
5688 +
5689 +void cpMacMdioClose(PHY_DEVICE *PhyDev, int Full);
5690 +
5691 +
5692 +/* Phy Mode Values */
5693 +#define NWAY_AUTOMDIX (1<<16)
5694 +#define NWAY_FD100 (1<<8)
5695 +#define NWAY_HD100 (1<<7)
5696 +#define NWAY_FD10 (1<<6)
5697 +#define NWAY_HD10 (1<<5)
5698 +#define NWAY_AUTO (1<<0)
5699 +
5700 +/*
5701 + *
5702 + * Tic() return values
5703 + *
5704 + */
5705 +
5706 +#define _MIIMDIO_MDIXFLIP (1<<28)
5707 +
5708 +#define _AUTOMDIX_DELAY_MIN 80 /* milli-seconds*/
5709 +#define _AUTOMDIX_DELAY_MAX 200 /* milli-seconds*/
5710 +
5711 +#endif /* _INC_CPMDIO */
5712 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/cppi_cpmac.c linux-2.4.30/drivers/net/avalanche_cpmac/cppi_cpmac.c
5713 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/cppi_cpmac.c 1970-01-01 02:00:00.000000000 +0200
5714 +++ linux-2.4.30/drivers/net/avalanche_cpmac/cppi_cpmac.c 2005-04-15 05:10:41.000000000 +0200
5715 @@ -0,0 +1,1345 @@
5716 +/*************************************************************************
5717 + * TNETDxxxx Software Support
5718 + * Copyright (c) 2002,2003 Texas Instruments Incorporated. All Rights Reserved.
5719 + *
5720 + * FILE: cppi.c
5721 + *
5722 + * DESCRIPTION:
5723 + * This file contains shared code for all CPPI modules.
5724 + *
5725 + * HISTORY:
5726 + * 7Aug02 Greg RC1.00 Original Version created.
5727 + * 27Sep02 Mick RC1.01 Merged for use by CPMAC/CPSAR
5728 + * 16Oct02 Mick RC1.02 Performance Tweaks (see cppihist.txt)
5729 + * 12Nov02 Mick RC1.02 Updated to use cpmac_reg.h
5730 + * 09Jan03 Mick RC3.01 Removed modification to RxBuffer ptr
5731 + * 28Mar03 Mick 1.03 RxReturn now returns error if Malloc Fails
5732 + * 10Apr03 Mick 1.03.02 Added Needs Buffer Support
5733 + * 11Jun03 Mick 1.06.02 halSend() errors corrected
5734 + * 23Aug04 Mick 1.07.08 cpmac only - Send: bypass threshold check if TxInts re-enabled
5735 + *
5736 + * @author Greg Guyotte
5737 + * @version 1.00
5738 + * @date 7-Aug-2002
5739 + *****************************************************************************/
5740 +/* each CPPI module must modify this file, the rest of the
5741 + code in cppi.c should be totally shared *//* Each CPPI module MUST properly define all constants shown below */
5742 +
5743 +/* CPPI registers */
5744 +
5745 +/* the following defines are not CPPI specific */
5746 +
5747 +static int TxInt(HAL_DEVICE *HalDev, int Ch, int Queue, int *MoreWork);
5748 +
5749 +static void FreeRx(HAL_DEVICE *HalDev, int Ch)
5750 + {
5751 + HAL_RCB *rcb_ptr; /*+GSG 030303*/
5752 + int rcbSize = (sizeof(HAL_RCB)+0xf)&~0xf; /*+GSG 030303*/
5753 + int Num = HalDev->ChData[Ch].RxNumBuffers, i; /*+GSG 030303*/
5754 +
5755 + /* Free Rx data buffers attached to descriptors, if necessary */
5756 + if (HalDev->RcbStart[Ch] != 0) /*+GSG 030303*/
5757 + { /*+GSG 030303*/
5758 + for(i=0;i<Num;i++) /*+GSG 030303*/
5759 + { /*+GSG 030303*/
5760 + rcb_ptr = (HAL_RCB *)(HalDev->RcbStart[Ch] + (i*rcbSize)); /*+GSG 030303*/
5761 +
5762 + /* free the data buffer */
5763 + if (rcb_ptr->DatPtr != 0)
5764 + {
5765 +
5766 + HalDev->OsFunc->FreeRxBuffer((void *)rcb_ptr->OsInfo, (void *)rcb_ptr->DatPtr);
5767 + rcb_ptr->OsInfo=0; /*MJH+030522*/
5768 + rcb_ptr->DatPtr=0; /*MJH+030522*/
5769 + }
5770 + } /*+GSG 030303*/
5771 + } /*+GSG 030303*/
5772 +
5773 + /* free up all desciptors at once */
5774 + HalDev->OsFunc->FreeDmaXfer(HalDev->RcbStart[Ch]);
5775 +
5776 + /* mark buffers as freed */
5777 + HalDev->RcbStart[Ch] = 0;
5778 + }
5779 +
5780 +static void FreeTx(HAL_DEVICE *HalDev, int Ch, int Queue)
5781 + {
5782 +
5783 +/*+GSG 030303*/
5784 +
5785 + /* free all descriptors at once */
5786 + HalDev->OsFunc->FreeDmaXfer(HalDev->TcbStart[Ch][Queue]);
5787 +
5788 + HalDev->TcbStart[Ch][Queue] = 0;
5789 + }
5790 +
5791 +/* return of 0 means that this code executed, -1 means the interrupt was not
5792 + a teardown interrupt */
5793 +static int RxTeardownInt(HAL_DEVICE *HalDev, int Ch)
5794 + {
5795 + bit32u base = HalDev->dev_base;
5796 +
5797 + /* check to see if the interrupt is a teardown interrupt */
5798 + if (((CPMAC_RX_INT_ACK( base , Ch )) & TEARDOWN_VAL) == TEARDOWN_VAL)
5799 + {
5800 + /* finish channel teardown */
5801 +
5802 + /* Free channel resources on a FULL teardown */
5803 + if (HalDev->RxTeardownPending[Ch] & FULL_TEARDOWN)
5804 + {
5805 + FreeRx(HalDev, Ch);
5806 + }
5807 +
5808 + /* bug fix - clear Rx channel pointers on teardown */
5809 + HalDev->RcbPool[Ch] = 0;
5810 + HalDev->RxActQueueHead[Ch] = 0;
5811 + HalDev->RxActQueueCount[Ch] = 0;
5812 + HalDev->RxActive[Ch] = FALSE;
5813 +
5814 + /* write completion pointer */
5815 + (CPMAC_RX_INT_ACK( base , Ch )) = TEARDOWN_VAL;
5816 +
5817 + /* use direction bit as a teardown pending bit! May be able to
5818 + use only one teardown pending integer in HalDev */
5819 +
5820 + HalDev->RxTeardownPending[Ch] &= ~RX_TEARDOWN;
5821 +
5822 + HalDev->ChIsOpen[Ch][DIRECTION_RX] = 0;
5823 +
5824 + HalDev->ChIsOpen[Ch][DIRECTION_RX] = 0;
5825 + CPMAC_RX_INTMASK_CLEAR(HalDev->dev_base) = (1<<Ch);
5826 + if ((HalDev->RxTeardownPending[Ch] & BLOCKING_TEARDOWN) == 0)
5827 + {
5828 +
5829 + HalDev->OsFunc->TeardownComplete(HalDev->OsDev, Ch, DIRECTION_RX);
5830 + }
5831 + HalDev->RxTeardownPending[Ch] = 0;
5832 +
5833 + return (EC_NO_ERRORS);
5834 + }
5835 + return (-1);
5836 + }
5837 +
5838 +/* return of 0 means that this code executed, -1 means the interrupt was not
5839 + a teardown interrupt. Note: this code is always called with Queue == 0 (hi priority). */
5840 +static int TxTeardownInt(HAL_DEVICE *HalDev, int Ch, int Queue)
5841 + {
5842 + bit32u base = HalDev->dev_base;
5843 + HAL_TCB *Last, *Curr, *First; /*+GSG 030303*/
5844 + int i;
5845 +
5846 + if (((CPMAC_TX_INT_ACK( base , Ch )) & TEARDOWN_VAL) == TEARDOWN_VAL)
5847 + {
5848 + /* perform all actions for both queues (+GSG 040212) */
5849 + for (i=0; i<HalDev->ChData[Ch].TxNumQueues; i++)
5850 + {
5851 + /* return outstanding buffers to OS +RC3.02*/
5852 + Curr = HalDev->TxActQueueHead[Ch][i]; /*+GSG 030303*/
5853 + First = Curr; /*+GSG 030303*/
5854 + while (Curr) /*+GSG 030303*/
5855 + { /*+GSG 030303*/
5856 + /* Pop TCB(s) for packet from the stack */ /*+GSG 030303*/
5857 + Last = Curr->Eop; /*+GSG 030303*/
5858 + HalDev->TxActQueueHead[Ch][i] = Last->Next; /*+GSG 030303*/
5859 + /*+GSG 030303*/
5860 + /* return to OS */ /*+GSG 030303*/
5861 + HalDev->OsFunc->SendComplete(Curr->OsInfo); /*+GSG 030303*/
5862 + /*+GSG 030303*/
5863 + /* Push Tcb(s) back onto the stack */ /*+GSG 030303*/
5864 + Curr = Last->Next; /*+GSG 030303*/
5865 + Last->Next = HalDev->TcbPool[Ch][i]; /*+GSG 030303*/
5866 + HalDev->TcbPool[Ch][i] = First; /*+GSG 030303*/
5867 + /*+GSG 030303*/
5868 + /* set the first(SOP) pointer for the next packet */ /*+GSG 030303*/
5869 + First = Curr; /*+GSG 030303*/
5870 + } /*+GSG 030303*/
5871 + }
5872 +
5873 + /* finish channel teardown */
5874 +
5875 + if (HalDev->TxTeardownPending[Ch] & FULL_TEARDOWN)
5876 + {
5877 + FreeTx(HalDev, Ch, 0);
5878 +
5879 + if (HalDev->ChData[Ch].TxNumQueues == 2)
5880 + FreeTx(HalDev, Ch, 1);
5881 + } /* if FULL teardown */
5882 +
5883 + /* perform all actions for both queues (+GSG 040212) */
5884 + for (i=0; i<HalDev->ChData[Ch].TxNumQueues; i++)
5885 + {
5886 + /* bug fix - clear Tx channel pointers on teardown */
5887 + HalDev->TcbPool[Ch][i] = 0;
5888 + HalDev->TxActQueueHead[Ch][i] = 0;
5889 + HalDev->TxActQueueCount[Ch][i] = 0;
5890 + HalDev->TxActive[Ch][i] = FALSE;
5891 + }
5892 +
5893 + /* write completion pointer, only needed for the high priority queue */
5894 + (CPMAC_TX_INT_ACK( base , Ch )) = TEARDOWN_VAL;
5895 +
5896 + /* no longer pending teardown */
5897 + HalDev->TxTeardownPending[Ch] &= ~TX_TEARDOWN;
5898 +
5899 + HalDev->ChIsOpen[Ch][DIRECTION_TX] = 0;
5900 +
5901 + HalDev->ChIsOpen[Ch][DIRECTION_TX] = 0;
5902 + CPMAC_TX_INTMASK_CLEAR(HalDev->dev_base) = (1<<Ch);
5903 + if ((HalDev->TxTeardownPending[Ch] & BLOCKING_TEARDOWN) == 0)
5904 + {
5905 +
5906 + HalDev->OsFunc->TeardownComplete(HalDev->OsDev, Ch, DIRECTION_TX);
5907 + }
5908 + HalDev->TxTeardownPending[Ch] = 0;
5909 +
5910 + return (EC_NO_ERRORS);
5911 + }
5912 + return (-1);
5913 + }
5914 +
5915 +/* +GSG 030421 */
5916 +static void AddToRxQueue(HAL_DEVICE *HalDev, HAL_RCB *FirstRcb, HAL_RCB *LastRcb, int FragCount, int Ch)
5917 + {
5918 + if (HalDev->RxActQueueHead[Ch]==0)
5919 + {
5920 +
5921 + HalDev->RxActQueueHead[Ch]=FirstRcb;
5922 + HalDev->RxActQueueTail[Ch]=LastRcb;
5923 + if (!HalDev->RxActive[Ch])
5924 + {
5925 + /* write Rx Queue Head Descriptor Pointer */
5926 + ((CPMAC_RX_HDP( HalDev->dev_base , Ch )) ) = VirtToPhys(FirstRcb) - HalDev->offset;
5927 + HalDev->RxActive[Ch]=TRUE;
5928 + }
5929 + }
5930 + else
5931 + {
5932 + register HAL_RCB *OldTailRcb;
5933 + register bit32u rmode;
5934 +
5935 + HalDev->OsFunc->CriticalOn();
5936 + OldTailRcb=HalDev->RxActQueueTail[Ch];
5937 + OldTailRcb->Next=(void *)FirstRcb;
5938 + OldTailRcb=VirtToVirtNoCache(OldTailRcb);
5939 + OldTailRcb->HNext=VirtToPhys(FirstRcb) - HalDev->offset;
5940 + HalDev->RxActQueueTail[Ch]=LastRcb;
5941 + rmode=OldTailRcb->mode;
5942 + if (rmode&CB_EOQ_BIT)
5943 + {
5944 + rmode&=~CB_EOQ_BIT;
5945 + ((CPMAC_RX_HDP( HalDev->dev_base , Ch )) ) = VirtToPhys(FirstRcb) - HalDev->offset;
5946 + OldTailRcb->mode=rmode;
5947 + }
5948 + HalDev->OsFunc->CriticalOff();
5949 + }
5950 + }
5951 +
5952 +/**
5953 + * @ingroup CPHAL_Functions
5954 + * This function is called to indicate to the CPHAL that the upper layer
5955 + * software has finished processing the receive data (given to it by
5956 + * osReceive()). The CPHAL will then return the appropriate receive buffers
5957 + * and buffer descriptors to the available pool.
5958 + *
5959 + * @param HalReceiveInfo Start of receive buffer descriptor chain returned to
5960 + * CPHAL.
5961 + * @param StripFlag Flag indicating whether the upper layer software has
5962 + * retained ownership of the receive data buffers.
5963 + *<BR>
5964 + * 'FALSE' means that the CPHAL can reuse the receive data buffers.
5965 + *<BR>
5966 + * 'TRUE' : indicates the data buffers were retained by the OS
5967 + *<BR>
5968 + * NOTE: If StripFlag is TRUE, it is the responsibility of the upper layer software to free the buffers when they are no longer needed.
5969 + *
5970 + * @return EC_NO_ERRORS (ok). <BR>
5971 + * Possible Error Codes:<BR>
5972 + * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
5973 + * @ref EC_VAL_RCB_NEEDS_BUFFER "EC_VAL_RCB_NEEDS_BUFFER"<BR>
5974 + * @ref EC_VAL_RCB_DROPPED "EC_VAL_RCB_DROPPED"<BR>
5975 + */
5976 +static int halRxReturn(HAL_RECEIVEINFO *HalReceiveInfo,
5977 + int StripFlag)
5978 + {
5979 + int Ch, i;
5980 + HAL_RCB *LastRcb;
5981 + HAL_DEVICE *HalDev;
5982 + int RcbSize;
5983 + int FragCount;
5984 +
5985 + Ch = HalReceiveInfo->mode&0x0ff;
5986 + HalDev = (HAL_DEVICE *)HalReceiveInfo->Off_BLen;
5987 + FragCount = HalReceiveInfo->mode>>8;
5988 +
5989 + if (HalDev->State != enOpened)
5990 + return(EC_CPMAC |EC_FUNC_RXRETURN|EC_VAL_INVALID_STATE);
5991 +
5992 + LastRcb=(HAL_RCB *)HalReceiveInfo->Eop;
5993 + LastRcb->HNext=0;
5994 + LastRcb->Next=0;
5995 + RcbSize = HalDev->ChData[Ch].RxBufSize;
5996 +
5997 + if (FragCount>1)
5998 + {
5999 + LastRcb->Off_BLen=RcbSize;
6000 + LastRcb->mode=CB_OWNERSHIP_BIT;
6001 + }
6002 +
6003 + HalReceiveInfo->Off_BLen=RcbSize;
6004 + HalReceiveInfo->mode=CB_OWNERSHIP_BIT;
6005 +
6006 + /* If OS has kept the buffers for this packet, attempt to alloc new buffers */
6007 + if (StripFlag)
6008 + {
6009 + int rc=0; /*MJH+030417*/
6010 + int GoodCount=0; /*GSG+030421*/
6011 + HAL_RCB *TempRcb;
6012 + char *pBuf;
6013 + HAL_RCB *CurrHeadRcb = HalReceiveInfo, *LastGoodRcb=0; /* +GSG 030421 */
6014 +
6015 + TempRcb = HalReceiveInfo;
6016 + for (i=0; i<FragCount; i++)
6017 + {
6018 + if (TempRcb == 0)
6019 + {
6020 + dbgPrintf("Rx Return error while allocating new buffers\n");
6021 + dbgPrintf("Rcb = %08x, Rcb->Eop = %08x, FragCount = %d:%d\n",
6022 + (bit32u)HalReceiveInfo, (bit32u)HalReceiveInfo->Eop, FragCount,i);
6023 + osfuncSioFlush();
6024 +
6025 + return(EC_CPPI|EC_FUNC_RXRETURN|EC_VAL_CORRUPT_RCB_CHAIN);
6026 + }
6027 +
6028 + pBuf= (char *) HalDev->OsFunc->MallocRxBuffer(RcbSize,0,
6029 + 0xF,HalDev->ChData[Ch].OsSetup,
6030 + (void *)TempRcb,
6031 + (void *)&TempRcb->OsInfo,
6032 + (void *) HalDev->OsDev);
6033 + if (!pBuf)
6034 + {
6035 + /* malloc failed, add this RCB to Needs Buffer List */
6036 + (HAL_RCB *)TempRcb->Eop = TempRcb; /* GSG +030430 */
6037 + TempRcb->mode=1<<8|Ch;
6038 + TempRcb->Off_BLen=(bit32u)HalDev;
6039 +
6040 + if(HalDev->NeedsCount < MAX_NEEDS) /* +MJH 030410 */
6041 + { /* +MJH 030410 */
6042 + HalDev->Needs[HalDev->NeedsCount] = (HAL_RECEIVEINFO *) TempRcb; /* +MJH 030410 */
6043 + HalDev->NeedsCount++; /* +MJH 030410 */
6044 + rc = (EC_CPPI|EC_FUNC_RXRETURN|EC_VAL_RCB_NEEDS_BUFFER); /* ~MJH 030417 */
6045 + } /* +MJH 030410 */
6046 + else /* +MJH 030410 */
6047 + rc = (EC_CPPI|EC_FUNC_RXRETURN|EC_VAL_RCB_DROPPED); /* ~MJH 030417 */
6048 +
6049 + /* requeue any previous RCB's that were ready to go before this one */
6050 + if (GoodCount > 0) /* +GSG 030421 */
6051 + { /* +GSG 030421 */
6052 + LastGoodRcb->HNext=0; /* +GSG 030430 */
6053 + LastGoodRcb->Next=0; /* +GSG 030430 */
6054 + osfuncDataCacheHitWritebackAndInvalidate((void *)LastGoodRcb, 16); /* +GSG 030430 */
6055 +
6056 + AddToRxQueue(HalDev, CurrHeadRcb, LastGoodRcb, GoodCount, Ch); /* +GSG 030421 */
6057 + GoodCount = 0; /* +GSG 030421 */
6058 + } /* +GSG 030421 */
6059 +
6060 + CurrHeadRcb = TempRcb->Next; /* +GSG 030421 */
6061 + }
6062 + else /* +GSG 030421 */
6063 + { /* +GSG 030421 */
6064 + /* malloc succeeded, requeue the RCB to the hardware */
6065 + TempRcb->BufPtr=VirtToPhys(pBuf) - HalDev->offset;
6066 + TempRcb->DatPtr=pBuf;
6067 + /* Emerald fix 10/29 */
6068 + osfuncDataCacheHitWritebackAndInvalidate((void *)TempRcb, 16);
6069 +
6070 + /* i store the last good RCB in case the malloc fails for the
6071 + next fragment. This ensures that I can go ahead and return
6072 + a partial chain of RCB's to the hardware */
6073 + LastGoodRcb = TempRcb; /* +GSG 030421 */
6074 + GoodCount++; /* +GSG 030421 */
6075 + } /* +GSG 030421 */
6076 + TempRcb = TempRcb->Next;
6077 + } /* end of Frag loop */
6078 + /* if there any good RCB's to requeue, do so here */
6079 + if (GoodCount > 0) /* +GSG 030421 */
6080 + {
6081 + AddToRxQueue(HalDev, CurrHeadRcb, LastGoodRcb, GoodCount, Ch); /* +GSG 030421 */
6082 + }
6083 + return(rc); /* ~GSG 030421 */
6084 + }
6085 + else
6086 + {
6087 + /* Not Stripping */
6088 + /* Emerald */
6089 + /* Write Back SOP and last RCB */
6090 + osfuncDataCacheHitWritebackAndInvalidate((void *)HalReceiveInfo, 16);
6091 +
6092 + if (FragCount > 1)
6093 + {
6094 + osfuncDataCacheHitWritebackAndInvalidate((void *)LastRcb, 16);
6095 + }
6096 + /* if not stripping buffers, always add to queue */
6097 + AddToRxQueue(HalDev, HalReceiveInfo, LastRcb, FragCount, Ch); /*MJH~030520*/
6098 + }
6099 +
6100 + return(EC_NO_ERRORS);
6101 + }
6102 +
6103 +/* +MJH 030410
6104 + Trys to liberate an RCB until liberation fails.
6105 + Note: If liberation fails then RxReturn will re-add the RCB to the
6106 + Needs list.
6107 +*/
6108 +static void NeedsCheck(HAL_DEVICE *HalDev)
6109 +{
6110 + HAL_RECEIVEINFO* HalRcb;
6111 + int rc;
6112 + HalDev->OsFunc->CriticalOn();
6113 + while(HalDev->NeedsCount)
6114 + {
6115 + HalDev->NeedsCount--;
6116 + HalRcb = HalDev->Needs[HalDev->NeedsCount];
6117 + rc = halRxReturn(HalRcb, 1);
6118 + /* short circuit if RxReturn starts to fail */
6119 + if (rc != 0)
6120 + break;
6121 + }
6122 + HalDev->OsFunc->CriticalOff();
6123 +}
6124 +
6125 +/*
6126 + * This function allocates transmit buffer descriptors (internal CPHAL function).
6127 + * It creates a high priority transmit queue by default for a single Tx
6128 + * channel. If QoS is enabled for the given CPHAL device, this function
6129 + * will also allocate a low priority transmit queue.
6130 + *
6131 + * @param HalDev CPHAL module instance. (set by cphalInitModule())
6132 + * @param Ch Channel number.
6133 + *
6134 + * @return 0 OK, Non-Zero Not OK
6135 + */
6136 +static int InitTcb(HAL_DEVICE *HalDev, int Ch)
6137 + {
6138 + int i, Num = HalDev->ChData[Ch].TxNumBuffers;
6139 + HAL_TCB *pTcb=0;
6140 + char *AllTcb;
6141 + int tcbSize, Queue;
6142 + int SizeMalloc;
6143 +
6144 + tcbSize = (sizeof(HAL_TCB)+0xf)&~0xf;
6145 + SizeMalloc = (tcbSize*Num)+0xf;
6146 +
6147 + for (Queue=0; Queue < HalDev->ChData[Ch].TxNumQueues; Queue++)
6148 + {
6149 + if (HalDev->TcbStart[Ch][Queue] == 0)
6150 + {
6151 +
6152 + /* malloc all TCBs at once */
6153 + AllTcb = (char *)HalDev->OsFunc->MallocDmaXfer(SizeMalloc,0,0xffffffff);
6154 + if (!AllTcb)
6155 + {
6156 + return(EC_CPPI|EC_FUNC_HAL_INIT|EC_VAL_TCB_MALLOC_FAILED);
6157 + }
6158 +
6159 + HalDev->OsFunc->Memset(AllTcb, 0, SizeMalloc);
6160 +
6161 + /* keep this address for freeing later */
6162 + HalDev->TcbStart[Ch][Queue] = AllTcb;
6163 + }
6164 + else
6165 + {
6166 + /* if the memory has already been allocated, simply reuse it! */
6167 + AllTcb = HalDev->TcbStart[Ch][Queue];
6168 + }
6169 +
6170 + /* align to cache line */
6171 + AllTcb = (char *)(((bit32u)AllTcb + 0xf) &~ 0xf); /*PITS #143 MJH~030522*/
6172 +
6173 + /* default High priority transmit queue */
6174 + HalDev->TcbPool[Ch][Queue]=0;
6175 + for(i=0;i<Num;i++)
6176 + {
6177 + /*pTcb=(HAL_TCB *) OsFunc->MallocDmaXfer(sizeof(HAL_TCB),0,0xffffffff); */
6178 + pTcb= (HAL_TCB *)(AllTcb + (i*tcbSize));
6179 + pTcb->mode=0;
6180 + pTcb->BufPtr=0;
6181 + pTcb->Next=HalDev->TcbPool[Ch][Queue];
6182 + pTcb->Off_BLen=0;
6183 + HalDev->TcbPool[Ch][Queue]=pTcb;
6184 + }
6185 + /*HalDev->TcbEnd = pTcb;*/
6186 + }
6187 +
6188 + return(EC_NO_ERRORS);
6189 + }
6190 +
6191 +/*
6192 + * This function allocates receive buffer descriptors (internal CPHAL function).
6193 + * After allocation, the function 'queues' (gives to the hardware) the newly
6194 + * created receive buffers to enable packet reception.
6195 + *
6196 + * @param HalDev CPHAL module instance. (set by cphalInitModule())
6197 + * @param Ch Channel number.
6198 + *
6199 + * @return 0 OK, Non-Zero Not OK
6200 + */
6201 +static int InitRcb(HAL_DEVICE *HalDev, int Ch)
6202 + {
6203 + int i, Num = HalDev->ChData[Ch].RxNumBuffers;
6204 + int Size = HalDev->ChData[Ch].RxBufSize;
6205 + HAL_RCB *pRcb;
6206 + char *pBuf;
6207 + char *AllRcb;
6208 + int rcbSize;
6209 + int DoMalloc = 0;
6210 + int SizeMalloc;
6211 + int MallocSize;
6212 +
6213 + rcbSize = (sizeof(HAL_RCB)+0xf)&~0xf;
6214 + SizeMalloc = (rcbSize*Num)+0xf;
6215 +
6216 + if (HalDev->RcbStart[Ch] == 0)
6217 + {
6218 + DoMalloc = 1;
6219 +
6220 + /* malloc all RCBs at once */
6221 + AllRcb= (char *)HalDev->OsFunc->MallocDmaXfer(SizeMalloc,0,0xffffffff);
6222 + if (!AllRcb)
6223 + {
6224 + return(EC_CPPI|EC_FUNC_HAL_INIT|EC_VAL_RCB_MALLOC_FAILED);
6225 + }
6226 +
6227 + HalDev->OsFunc->Memset(AllRcb, 0, SizeMalloc);
6228 +
6229 + /* keep this address for freeing later */
6230 + HalDev->RcbStart[Ch] = AllRcb;
6231 + }
6232 + else
6233 + {
6234 + /* if the memory has already been allocated, simply reuse it! */
6235 + AllRcb = HalDev->RcbStart[Ch];
6236 + }
6237 +
6238 + /* align to cache line */
6239 + AllRcb = (char *)(((bit32u)AllRcb + 0xf)&~0xf); /*PITS #143 MJH~030522*/
6240 +
6241 + HalDev->RcbPool[Ch]=0;
6242 + for(i=0;i<Num;i++)
6243 + {
6244 + pRcb = (HAL_RCB *)(AllRcb + (i*rcbSize));
6245 +
6246 + if (DoMalloc == 1)
6247 + {
6248 +
6249 + MallocSize = Size; /*~3.01 */
6250 + pBuf= (char *) HalDev->OsFunc->MallocRxBuffer(MallocSize,0,0xF,HalDev->ChData[Ch].OsSetup, (void *)pRcb, (void *)&pRcb->OsInfo, (void *) HalDev->OsDev);
6251 + if(!pBuf)
6252 + {
6253 + return(EC_CPPI|EC_FUNC_HAL_INIT|EC_VAL_RX_BUFFER_MALLOC_FAILED);
6254 + }
6255 + /* -RC3.01 pBuf = (char *)(((bit32u)pBuf+0xF) & ~0xF); */
6256 + pRcb->BufPtr=VirtToPhys(pBuf) - HalDev->offset;
6257 + pRcb->DatPtr=pBuf;
6258 + }
6259 + pRcb->mode=(1<<8)|Ch; /* One Frag for Ch */
6260 + pRcb->Next=(void *)HalDev->RcbPool[Ch];
6261 + pRcb->Off_BLen=(bit32u)HalDev;
6262 + HalDev->RcbPool[Ch]=pRcb;
6263 + }
6264 +
6265 + /* Give all of the Rx buffers to hardware */
6266 +
6267 + while(HalDev->RcbPool[Ch])
6268 + {
6269 + pRcb=HalDev->RcbPool[Ch];
6270 + HalDev->RcbPool[Ch]=pRcb->Next;
6271 + pRcb->Eop=(void*)pRcb;
6272 + pRcb->mode=(1<<8)|Ch;
6273 + halRxReturn((HAL_RECEIVEINFO *)pRcb, 0);
6274 + }
6275 +
6276 + return(EC_NO_ERRORS);
6277 + }
6278 +
6279 +/**
6280 + * @ingroup CPHAL_Functions
6281 + * This function transmits the data in FragList using available transmit
6282 + * buffer descriptors. More information on the use of the Mode parameter
6283 + * is available in the module-specific appendices. Note: The OS should
6284 + * not call Send() for a channel that has been requested to be torndown.
6285 + *
6286 + * @param HalDev CPHAL module instance. (set by cphalInitModule())
6287 + * @param FragList Fragment List structure.
6288 + * @param FragCount Number of fragments in FragList.
6289 + * @param PacketSize Number of bytes to transmit.
6290 + * @param OsSendInfo OS Send Information structure. <BR>
6291 + * @param Mode 32-bit value with the following bit fields: <BR>
6292 + * 31-16: Mode (used for module specific data). <BR>
6293 + * 15-08: Queue (transmit queue to send on). <BR>
6294 + * 07-00: Channel (channel number to send on).
6295 + *
6296 + * @return EC_NO_ERRORS (ok). <BR>
6297 + * Possible Error Codes:<BR>
6298 + * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
6299 + * @ref EC_VAL_NOT_LINKED "EC_VAL_NOT_LINKED"<BR>
6300 + * @ref EC_VAL_INVALID_CH "EC_VAL_INVALID_CH"<BR>
6301 + * @ref EC_VAL_OUT_OF_TCBS "EC_VAL_OUT_OF_TCBS"<BR>
6302 + * @ref EC_VAL_NO_TCBS "EC_VAL_NO_TCBS"<BR>
6303 + */
6304 +static int halSend(HAL_DEVICE *HalDev,FRAGLIST *FragList,
6305 + int FragCount,int PacketSize, OS_SENDINFO *OsSendInfo,
6306 + bit32u Mode)
6307 + {
6308 + HAL_TCB *tcb_ptr, *head;
6309 + int i;
6310 + int rc = EC_NO_ERRORS;
6311 + int Ch = Mode & 0xFF;
6312 + int Queue = (Mode>>8)&0xFF;
6313 + /*int DoThresholdCheck=1; */ /* Used when TxIntDisable is set and TxInts are re-enabled */
6314 +
6315 + if (HalDev->State != enOpened)
6316 + return(EC_CPPI|EC_FUNC_SEND|EC_VAL_INVALID_STATE);
6317 +
6318 + if (!HalDev->Linked)
6319 + {
6320 + rc = EC_CPPI|EC_FUNC_SEND|EC_VAL_NOT_LINKED;
6321 + return(rc);
6322 + }
6323 +
6324 + if (HalDev->ChIsOpen[Ch][DIRECTION_TX] == 0) /*MJH~030611*/ /*PITS 148*/
6325 + return(EC_CPMAC |EC_FUNC_SEND|EC_VAL_INVALID_CH); /*+GSG 030303*/
6326 +
6327 + HalDev->OsFunc->CriticalOn();
6328 +
6329 + /* Setup Tx mode and size */
6330 + if (PacketSize<60)
6331 + {
6332 + FragList[FragCount-1].len += (60 - PacketSize); /*MJH~030506*//*PITS 132*/
6333 + PacketSize = 60; /*MJH~030506*/
6334 + }
6335 + Mode &= CB_PASSCRC_BIT;
6336 +
6337 + tcb_ptr = head = HalDev->TcbPool[Ch][Queue];
6338 +
6339 + if (tcb_ptr)
6340 + {
6341 +
6342 + Mode|=PacketSize|CB_SOF_BIT|CB_OWNERSHIP_BIT;
6343 +
6344 + for (i=0; i<FragCount; i++)
6345 +
6346 + {
6347 + /* Setup Tx mode and size */
6348 + tcb_ptr->Off_BLen = FragList[i].len;
6349 +
6350 + tcb_ptr->mode = Mode;
6351 + tcb_ptr->BufPtr = VirtToPhys((bit32 *)FragList[i].data) - HalDev->offset;
6352 + tcb_ptr->OsInfo = OsSendInfo;
6353 +
6354 + if (i == (FragCount - 1))
6355 + {
6356 + /* last fragment */
6357 + tcb_ptr->mode |= CB_EOF_BIT;
6358 +
6359 + /* since this is the last fragment, set the TcbPool pointer before
6360 + nulling out the Next pointers */
6361 +
6362 + HalDev->TcbPool[Ch][Queue] = tcb_ptr->Next;
6363 +
6364 + tcb_ptr->Next = 0;
6365 + tcb_ptr->HNext = 0;
6366 +
6367 + /* In the Tx Interrupt handler, we will need to know which TCB is EOP,
6368 + so we can save that information in the SOP */
6369 + head->Eop = tcb_ptr;
6370 +
6371 + /* Emerald fix 10/29 */
6372 + osfuncDataCacheHitWritebackAndInvalidate((void *)tcb_ptr, 16);
6373 +
6374 + }
6375 + else
6376 + {
6377 + Mode=CB_OWNERSHIP_BIT;
6378 + tcb_ptr->HNext = VirtToPhys((bit32 *)tcb_ptr->Next) - HalDev->offset;
6379 +
6380 + /* Emerald fix 10/29 */
6381 + osfuncDataCacheHitWritebackAndInvalidate((void *)tcb_ptr, 16);
6382 +
6383 + tcb_ptr = tcb_ptr->Next; /* what about the end of TCB list?? */
6384 +
6385 + if (tcb_ptr == 0)
6386 + {
6387 + rc = EC_CPPI|EC_FUNC_SEND|EC_VAL_OUT_OF_TCBS;
6388 + goto ExitSend;
6389 + }
6390 + }
6391 + } /* for */
6392 +
6393 + /* put it on the high priority queue */
6394 + if (HalDev->TxActQueueHead[Ch][Queue] == 0)
6395 + {
6396 + HalDev->TxActQueueHead[Ch][Queue]=head;
6397 + HalDev->TxActQueueTail[Ch][Queue]=tcb_ptr;
6398 +/*+GSG 030303*//*+GSG 030303*/
6399 + if (!HalDev->TxActive[Ch][Queue])
6400 + {
6401 +
6402 + bit32u base = HalDev->dev_base;
6403 +
6404 + /* write CPPI TX HDP */
6405 + (CPMAC_TX_HDP( base , Ch )) = VirtToPhys(head) - HalDev->offset;
6406 + HalDev->TxActive[Ch][Queue]=TRUE;
6407 +
6408 + }
6409 + }
6410 + else
6411 + {
6412 + register volatile HAL_TCB *pTailTcb;
6413 + register bit32u tmode;
6414 + register bit32u pCurrentTcb;
6415 +
6416 + HalDev->TxActQueueTail[Ch][Queue]->Next=head;
6417 + /* Emerald fix 10/29 */
6418 +
6419 + pTailTcb=(HAL_TCB *)VirtToVirtNoCache(&HalDev->TxActQueueTail[Ch][Queue]->HNext);
6420 + pCurrentTcb=VirtToPhys(head) - HalDev->offset;
6421 + pTailTcb->HNext=pCurrentTcb;
6422 + HalDev->TxActQueueTail[Ch][Queue]=tcb_ptr;
6423 +/*+GSG 030303*/
6424 + tmode=pTailTcb->mode;
6425 + if (tmode&CB_EOQ_BIT)
6426 + {
6427 + bit32u base = HalDev->dev_base;
6428 +
6429 + tmode&=~CB_EOQ_BIT;
6430 + pTailTcb->mode=tmode;
6431 + ((CPMAC_TX_HDP( base , Ch )) ) = pCurrentTcb;
6432 + }
6433 +
6434 + else
6435 + {
6436 + if(HalDev->TxIntDisable)
6437 + {
6438 + /* Enable Interrupts, to ensure packet goes out on wire */
6439 + CPMAC_TX_INTMASK_SET(HalDev->dev_base) = (1<<Ch);
6440 + halPacketProcessEnd(HalDev); /* Allow Interrupt to be seen at the OS */
6441 + /*DoThresholdCheck = 0; */ /* Disable Threshold Check */
6442 +
6443 + }
6444 + }
6445 +
6446 + }
6447 + rc = EC_NO_ERRORS;
6448 + goto ExitSend;
6449 + } /* if (tcb_ptr) */
6450 + else
6451 + {
6452 + rc = EC_CPPI|EC_FUNC_SEND|EC_VAL_NO_TCBS;
6453 + goto ExitSend;
6454 + }
6455 +ExitSend:
6456 +
6457 +/* 15 June 2004 - NSP Performance Update : If Tx Ints are disabled then process them here */
6458 +/* 29 June 2004 - NSP Performance Update : Moved to end at request of BCIL */
6459 +/* 23 Aug 2004 - NSP Performance Update : If Tx Ints are re-enabled do not do Threshold check */
6460 +
6461 + if(HalDev->TxIntDisable /*&& DoThresholdCheck*/)
6462 + {
6463 + if(--HalDev->TxIntThreshold[Ch] <= 0)
6464 + {
6465 + int MoreWork;
6466 + TxInt(HalDev, Ch, 0, &MoreWork);
6467 + HalDev->TxIntThreshold[Ch] = HalDev->TxIntThresholdMaster[Ch];
6468 + }
6469 + }
6470 + HalDev->OsFunc->CriticalOff();
6471 +
6472 + return(rc);
6473 + }
6474 +
6475 +/*
6476 + * This function processes receive interrupts. It traverses the receive
6477 + * buffer queue, extracting the data and passing it to the upper layer software via
6478 + * osReceive(). It handles all error conditions and fragments without valid data by
6479 + * immediately returning the RCB's to the RCB pool.
6480 + *
6481 + * @param HalDev CPHAL module instance. (set by cphalInitModule())
6482 + * @param Ch Channel Number.
6483 + * @param MoreWork Flag that indicates that there is more work to do when set to 1.
6484 + *
6485 + * @return 0 if OK, non-zero otherwise.
6486 + */
6487 +static int RxInt(HAL_DEVICE *HalDev, int Ch, int *MoreWork)
6488 + {
6489 + HAL_RCB *CurrentRcb, *SopRcb, *EofRcb, *EopRcb;
6490 + bit32u RxBufStatus,PacketsServiced, RxPktLen = 0, RxSopStatus,
6491 + FrmFrags, TotalFrags, FrmLen;
6492 + int base = HalDev->dev_base, Ret;
6493 + OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
6494 + int RxServiceMax = HalDev->ChData[Ch].RxServiceMax;
6495 + int FragIndex; /* +GSG 030508 */
6496 +
6497 + if(HalDev->NeedsCount) /* +MJH 030410 */
6498 + NeedsCheck(HalDev); /* +MJH 030410 */
6499 +
6500 + /* Handle case of teardown interrupt */
6501 + if (HalDev->RxTeardownPending[Ch] != 0)
6502 + {
6503 + Ret = RxTeardownInt(HalDev, Ch);
6504 + if (Ret == 0)
6505 + { /*+GSG 030303*/
6506 + *MoreWork = 0;
6507 + return (EC_NO_ERRORS);
6508 + } /*+GSG 030303*/
6509 + }
6510 +
6511 + /* Examine first RCB on the software active queue */
6512 + CurrentRcb=HalDev->RxActQueueHead[Ch];
6513 + osfuncDataCacheHitInvalidate((void*)CurrentRcb, 16);
6514 + RxBufStatus=CurrentRcb->mode;
6515 + PacketsServiced=0;
6516 +
6517 + /* Process received packets until we find hardware owned descriptors
6518 + or until we hit RxServiceMax */
6519 + while((CurrentRcb)&&((RxBufStatus&CB_OWNERSHIP_BIT)==0)&&
6520 + (PacketsServiced<RxServiceMax)) /* ~GSG 030307 */
6521 + {
6522 +
6523 + PacketsServiced++; /* ~GSG 030307 */
6524 + SopRcb=CurrentRcb;
6525 + RxSopStatus=RxBufStatus;
6526 + RxPktLen = RxSopStatus&CB_SIZE_MASK;
6527 +
6528 + FrmFrags=0;
6529 + TotalFrags=0;
6530 + FragIndex=0;
6531 + FrmLen=0;
6532 + EofRcb=0;
6533 +
6534 +/* +GSG 030508 *//* +GSG 030508 */
6535 +
6536 + /* Loop through all fragments that comprise current packet. Build
6537 + fraglist and exit when the end of the packet is reached, or the
6538 + end of the descriptor list is reached. */
6539 + do
6540 + {
6541 + bit32u DmaLen;
6542 +
6543 +
6544 + DmaLen=CurrentRcb->Off_BLen;
6545 +
6546 + FrmLen+=DmaLen;
6547 + TotalFrags++;
6548 + if (!EofRcb)
6549 + {
6550 + HalDev->fraglist[FragIndex].data=((char *)CurrentRcb->DatPtr); /* ~GSG 030508 */
6551 +
6552 + HalDev->fraglist[FragIndex].len=DmaLen; /* ~GSG 030508 */
6553 +
6554 + /* GSG 12/9 */
6555 + HalDev->fraglist[FragIndex].OsInfo = CurrentRcb->OsInfo; /* ~GSG 030508 */
6556 +
6557 + /* Upper layer must do the data invalidate */
6558 +
6559 + FrmFrags++;
6560 + FragIndex++; /* ~GSG 030508 */
6561 + if (FrmLen>=RxPktLen)
6562 + EofRcb=CurrentRcb;
6563 + }
6564 + EopRcb=CurrentRcb;
6565 + CurrentRcb=EopRcb->Next;
6566 + if (CurrentRcb)
6567 + {
6568 + osfuncDataCacheHitInvalidate((void*)CurrentRcb,16);
6569 + }
6570 + }while(((EopRcb->mode&CB_EOF_BIT)==0)&&(CurrentRcb));
6571 +
6572 + /* Write the completion pointer for interrupt acknowledgement*/
6573 + (CPMAC_RX_INT_ACK( base , Ch )) = VirtToPhys(EopRcb) - HalDev->offset;
6574 +
6575 + EopRcb->Next=0;
6576 +
6577 + if (CurrentRcb == 0)
6578 + {
6579 + /* If we are out of RCB's we must not send this packet
6580 + to the OS. */
6581 + int RcbSize = HalDev->ChData[Ch].RxBufSize;
6582 +
6583 + if (TotalFrags>1)
6584 + {
6585 + EopRcb->Off_BLen=RcbSize;
6586 + EopRcb->mode=CB_OWNERSHIP_BIT;
6587 + osfuncDataCacheHitWritebackAndInvalidate((void *)EopRcb, 16);
6588 + }
6589 +
6590 + SopRcb->Off_BLen=RcbSize;
6591 + SopRcb->mode=CB_OWNERSHIP_BIT;
6592 + osfuncDataCacheHitWritebackAndInvalidate((void *)SopRcb, 16);
6593 +
6594 + ((CPMAC_RX_HDP( base , Ch )) ) = VirtToPhys(SopRcb);
6595 + }
6596 + else
6597 + {
6598 + /* Dequeue packet and send to OS */
6599 + int mode;
6600 +
6601 + /* setup SopRcb for the packet */
6602 + SopRcb->Eop=(void*)EopRcb;
6603 +
6604 + /* dequeue packet */
6605 + HalDev->RxActQueueHead[Ch]=CurrentRcb;
6606 +
6607 + if (EopRcb->mode&CB_EOQ_BIT)
6608 + {
6609 + /* Next pointer is non-null and EOQ bit is set, which
6610 + indicates misqueue packet in CPPI protocol. */
6611 +
6612 + ((CPMAC_RX_HDP( base , Ch )) ) = EopRcb->HNext;
6613 + }
6614 +
6615 + mode = (SopRcb->mode & 0xFFFF0000) | Ch;
6616 +
6617 + SopRcb->mode=(FrmFrags<<8)|Ch;
6618 + SopRcb->Off_BLen=(bit32u)HalDev;
6619 +
6620 + /* send packet up the higher layer driver */
6621 + OsFunc->Receive(HalDev->OsDev,HalDev->fraglist,FragIndex,RxPktLen, /* ~GSG 030508 */
6622 + (HAL_RECEIVEINFO *)SopRcb,mode);
6623 +
6624 + RxBufStatus=CurrentRcb->mode;
6625 + }
6626 + } /* while loop */
6627 +
6628 + if ((CurrentRcb)&&((RxBufStatus&CB_OWNERSHIP_BIT)==0)) /*~GSG 030307*/
6629 + {
6630 + *MoreWork = 1;
6631 + }
6632 + else
6633 + {
6634 + *MoreWork = 0;
6635 + }
6636 +
6637 + return (EC_NO_ERRORS);
6638 +}
6639 +
6640 +/*
6641 + * This function processes transmit interrupts. It traverses the
6642 + * transmit buffer queue, detecting sent data buffers and notifying the upper
6643 + * layer software via osSendComplete(). (for SAR, i originally had this split
6644 + * into two functions, one for each queue, but joined them on 8/8/02)
6645 + *
6646 + * @param HalDev CPHAL module instance. (set by cphalInitModule())
6647 + * @param Queue Queue number to service (always 0 for MAC, Choose 1 for SAR to service low priority queue)
6648 + * @param MoreWork Flag that indicates that there is more work to do when set to 1.
6649 + *
6650 + * @return 0 if OK, non-zero otherwise.
6651 + */
6652 +int TxInt(HAL_DEVICE *HalDev, int Ch, int Queue, int *MoreWork)
6653 + {
6654 + HAL_TCB *CurrentTcb,*LastTcbProcessed,*FirstTcbProcessed;
6655 + int PacketsServiced;
6656 + bit32u TxFrameStatus;
6657 + int base;
6658 + int TxServiceMax = HalDev->ChData[Ch].TxServiceMax;
6659 + OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
6660 +
6661 +/*+GSG 030303*//*+GSG 030303*/
6662 +
6663 + /* load the module base address */
6664 + base = HalDev->dev_base;
6665 +
6666 + /* Handle case of teardown interrupt. This must be checked at
6667 + the top of the function rather than the bottom, because
6668 + the normal data processing can wipe out the completion
6669 + pointer which is used to determine teardown complete. */
6670 + if (HalDev->TxTeardownPending[Ch] != 0)
6671 + {
6672 + int Ret;
6673 +
6674 + Ret = TxTeardownInt(HalDev, Ch, Queue);
6675 + if (Ret == 0)
6676 + { /*+GSG 030303*/
6677 + *MoreWork = 0; /* bug fix 1/6 */ /*+GSG 030303*/
6678 + return (EC_NO_ERRORS);
6679 + } /*+GSG 030303*/
6680 + }
6681 +
6682 + OsFunc->CriticalOn(); /* 240904 */
6683 +
6684 + CurrentTcb = HalDev->TxActQueueHead[Ch][Queue];
6685 + FirstTcbProcessed=CurrentTcb;
6686 +
6687 + if (CurrentTcb==0)
6688 + {
6689 + /* I saw this error a couple of times when multi-channels were added */
6690 + dbgPrintf("[cppi TxInt()]TxH int with no TCB in queue!\n");
6691 + dbgPrintf(" Ch=%d, CurrentTcb = 0x%08x\n", Ch, (bit32u)CurrentTcb);
6692 + dbgPrintf(" HalDev = 0x%08x\n", (bit32u)HalDev);
6693 + osfuncSioFlush();
6694 + OsFunc->CriticalOff();
6695 + return(EC_CPPI|EC_FUNC_TXINT|EC_VAL_NULL_TCB);
6696 + }
6697 +
6698 + osfuncDataCacheHitInvalidate((void *)CurrentTcb, 16);
6699 + TxFrameStatus=CurrentTcb->mode;
6700 + PacketsServiced=0;
6701 +
6702 + /* should the ownership bit check be inside of the loop?? could make it a
6703 + while-do loop and take this check away */
6704 + if ((TxFrameStatus&CB_OWNERSHIP_BIT)==0)
6705 + {
6706 + do
6707 + {
6708 + /* Pop TCB(s) for packet from the stack */
6709 + LastTcbProcessed=CurrentTcb->Eop;
6710 +
6711 + /* new location for acknowledge */
6712 + /* Write the completion pointer */
6713 + (CPMAC_TX_INT_ACK( base , Ch )) = VirtToPhys(LastTcbProcessed) - HalDev->offset;
6714 +
6715 + HalDev->TxActQueueHead[Ch][Queue] = LastTcbProcessed->Next;
6716 +
6717 +/*+GSG 030303*//*+GSG 030303*/
6718 +
6719 + osfuncDataCacheHitInvalidate((void *)LastTcbProcessed, 16);
6720 +
6721 + if (LastTcbProcessed->mode&CB_EOQ_BIT)
6722 + {
6723 + if (LastTcbProcessed->Next)
6724 + {
6725 + /* Misqueued packet */
6726 +
6727 + (CPMAC_TX_HDP( base , Ch )) = LastTcbProcessed->HNext;
6728 +
6729 + }
6730 + else
6731 + {
6732 + /* Tx End of Queue */
6733 +
6734 + HalDev->TxActive[Ch][Queue]=FALSE;
6735 + }
6736 + }
6737 +
6738 + OsFunc->SendComplete(CurrentTcb->OsInfo);
6739 +
6740 + /* Push Tcb(s) back onto the stack */
6741 + CurrentTcb = LastTcbProcessed->Next;
6742 +
6743 + LastTcbProcessed->Next=HalDev->TcbPool[Ch][Queue];
6744 +
6745 + HalDev->TcbPool[Ch][Queue]=FirstTcbProcessed;
6746 +
6747 + PacketsServiced++;
6748 +
6749 + TxFrameStatus=CB_OWNERSHIP_BIT;
6750 + /* set the first(SOP) pointer for the next packet */
6751 + FirstTcbProcessed = CurrentTcb;
6752 + if (CurrentTcb)
6753 + {
6754 + osfuncDataCacheHitInvalidate((void *)CurrentTcb, 16);
6755 + TxFrameStatus=CurrentTcb->mode;
6756 + }
6757 +
6758 + }while(((TxFrameStatus&CB_OWNERSHIP_BIT)==0)
6759 + &&(PacketsServiced<TxServiceMax));
6760 +
6761 + if (((TxFrameStatus&CB_OWNERSHIP_BIT)==0)
6762 + &&(PacketsServiced==TxServiceMax))
6763 + {
6764 + *MoreWork = 1;
6765 + }
6766 + else
6767 + {
6768 + *MoreWork = 0;
6769 + }
6770 + }
6771 + OsFunc->CriticalOff();
6772 +
6773 + return(EC_NO_ERRORS);
6774 + }
6775 +
6776 +/**
6777 + * @ingroup CPHAL_Functions
6778 + * This function performs a teardown for the given channel. The value of the
6779 + * Mode parameter controls the operation of the function, as documented below.
6780 + *
6781 + * Note: If bit 3 of Mode is set, this call is blocking, and will not return
6782 + * until the teardown interrupt has occurred and been processed. While waiting
6783 + * for a blocking teardown to complete, ChannelTeardown() will signal the OS
6784 + * (via Control(.."Sleep"..)) to allow the OS to perform other tasks if
6785 + * necessary. If and only if bit 3 of Mode is clear, the CPHAL will call the
6786 + * OS TeardownComplete() function to indicate that the teardown has completed.
6787 + *
6788 + * @param HalDev CPHAL module instance. (set by xxxInitModule())
6789 + * @param Ch Channel number.
6790 + * @param Mode Bit 0 (LSB): Perform Tx teardown (if set).<BR>
6791 + * Bit 1: Perform Rx teardown (if set). <BR>
6792 + * Bit 2: If set, perform full teardown (free buffers/descriptors).
6793 + * If clear, perform partial teardown (keep buffers). <BR>
6794 + * Bit 3 (MSB): If set, call is blocking.
6795 + * If clear, call is non-blocking.
6796 + *
6797 + * @return EC_NO_ERRORS (ok). <BR>
6798 + * Possible Error Codes:<BR>
6799 + * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
6800 + * @ref EC_VAL_INVALID_CH "EC_VAL_INVALID_CH"<BR>
6801 + * @ref EC_VAL_TX_TEARDOWN_ALREADY_PEND "EC_VAL_TX_TEARDOWN_ALREADY_PEND"<BR>
6802 + * @ref EC_VAL_RX_TEARDOWN_ALREADY_PEND "EC_VAL_RX_TEARDOWN_ALREADY_PEND"<BR>
6803 + * @ref EC_VAL_TX_CH_ALREADY_TORNDOWN "EC_VAL_TX_CH_ALREADY_TORNDOWN"<BR>
6804 + * @ref EC_VAL_RX_CH_ALREADY_TORNDOWN "EC_VAL_RX_CH_ALREADY_TORNDOWN"<BR>
6805 + * @ref EC_VAL_TX_TEARDOWN_TIMEOUT "EC_VAL_TX_TEARDOWN_TIMEOUT"<BR>
6806 + * @ref EC_VAL_RX_TEARDOWN_TIMEOUT "EC_VAL_RX_TEARDOWN_TIMEOUT"<BR>
6807 + * @ref EC_VAL_LUT_NOT_READY "EC_VAL_LUT_NOT_READY"<BR>
6808 + */
6809 +static int halChannelTeardown(HAL_DEVICE *HalDev, int Ch, bit32 Mode)
6810 + {
6811 + int DoTx, DoRx, Sleep=2048, timeout=0; /*MJH~030306*/
6812 + bit32u base = HalDev->dev_base;
6813 +
6814 +/* Set the module, used for error returns */
6815 +
6816 + DoTx = (Mode & TX_TEARDOWN);
6817 + DoRx = (Mode & RX_TEARDOWN);
6818 +
6819 + if (HalDev->State < enInitialized)
6820 + return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_INVALID_STATE);
6821 +
6822 + if ((Ch < 0) || (Ch > (MAX_CHAN-1) ))
6823 + {
6824 + return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_INVALID_CH);
6825 + }
6826 +
6827 + /* set teardown pending bits before performing the teardown, because they
6828 + will be used in the int handler (this is done for AAL5) */
6829 + if (DoTx)
6830 + {
6831 + if (HalDev->TxTeardownPending[Ch] != 0)
6832 + return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_TX_TEARDOWN_ALREADY_PEND);
6833 +
6834 + /* If a full teardown, this also means that the user must
6835 + setup all channels again to use them */
6836 + if (Mode & FULL_TEARDOWN)
6837 + HalDev->ChIsSetup[Ch][DIRECTION_TX] = 0;
6838 +
6839 + if (HalDev->State < enOpened)
6840 + {
6841 + /* if the hardware has never been opened, the channel has never actually
6842 + been setup in the hardware, so I just need to reset the software flag
6843 + and leave */
6844 + HalDev->ChIsSetup[Ch][DIRECTION_TX] = 0;
6845 + return (EC_NO_ERRORS);
6846 + }
6847 + else
6848 + {
6849 + if (HalDev->ChIsOpen[Ch][DIRECTION_TX] == 0)
6850 + {
6851 + return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_TX_CH_ALREADY_TORNDOWN);
6852 + }
6853 +
6854 + /* set teardown flag */
6855 + HalDev->TxTeardownPending[Ch] = Mode;
6856 + }
6857 + }
6858 +
6859 + if (DoRx)
6860 + {
6861 + if (HalDev->RxTeardownPending[Ch] != 0)
6862 + return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_RX_TEARDOWN_ALREADY_PEND);
6863 +
6864 + if (Mode & FULL_TEARDOWN)
6865 + HalDev->ChIsSetup[Ch][DIRECTION_RX] = 0;
6866 +
6867 + if (HalDev->State < enOpened)
6868 + {
6869 + HalDev->ChIsSetup[Ch][DIRECTION_RX] = 0;
6870 + return (EC_NO_ERRORS);
6871 + }
6872 + else
6873 + {
6874 + if (HalDev->ChIsOpen[Ch][DIRECTION_RX] == 0)
6875 + return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_RX_CH_ALREADY_TORNDOWN);
6876 +
6877 + HalDev->RxTeardownPending[Ch] = Mode;
6878 + }
6879 + }
6880 +
6881 + /* Perform Tx Teardown Duties */
6882 + if ((DoTx) && (HalDev->State == enOpened))
6883 + {
6884 + /* Request TX channel teardown */
6885 + (CPMAC_TX_TEARDOWN( base )) = Ch;
6886 +
6887 + /* wait until teardown has completed */
6888 + if (Mode & BLOCKING_TEARDOWN)
6889 + {
6890 + timeout = 0;
6891 + while (HalDev->ChIsOpen[Ch][DIRECTION_TX] == TRUE)
6892 + {
6893 + osfuncSleep(&Sleep);
6894 +
6895 + timeout++;
6896 + if (timeout > 100000)
6897 + {
6898 + return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_TX_TEARDOWN_TIMEOUT);
6899 + }
6900 + }
6901 + }
6902 + } /* if DoTx */
6903 +
6904 + /* Perform Rx Teardown Duties */
6905 + if ((DoRx) && (HalDev->State == enOpened))
6906 + {
6907 +
6908 + /* perform CPMAC specific RX channel teardown */
6909 + CPMAC_RX_TEARDOWN(base) = Ch;
6910 +
6911 + if (Mode & BLOCKING_TEARDOWN)
6912 + {
6913 + timeout = 0;
6914 + while (HalDev->ChIsOpen[Ch][DIRECTION_RX] == TRUE)
6915 + {
6916 + osfuncSleep(&Sleep);
6917 +
6918 + timeout++;
6919 + if (timeout > 100000)
6920 + {
6921 + return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_RX_TEARDOWN_TIMEOUT);
6922 + }
6923 + }
6924 + }
6925 + } /* if DoRx */
6926 +
6927 + return (EC_NO_ERRORS);
6928 + }
6929 +
6930 +/**
6931 + * @ingroup CPHAL_Functions
6932 + * This function closes the CPHAL module. The module will be reset.
6933 + * The Mode parameter should be used to determine the actions taken by
6934 + * Close().
6935 + *
6936 + * @param HalDev CPHAL module instance. (set by xxxInitModule())
6937 + * @param Mode Indicates actions to take on close. The following integer
6938 + * values are valid: <BR>
6939 + * 1: Does not free buffer resources, init parameters remain
6940 + * intact. User can then call Open() without calling Init()
6941 + * to attempt to reset the device and bring it back to the
6942 + * last known state.<BR>
6943 + * 2: Frees the buffer resources, but keeps init parameters. This
6944 + * option is a more aggressive means of attempting a device reset.
6945 + * 3: Frees the buffer resources, and clears all init parameters. <BR>
6946 + * At this point, the caller would have to call to completely
6947 + * reinitialize the device (Init()) before being able to call
6948 + * Open(). Use this mode if you are shutting down the module
6949 + * and do not plan to restart.
6950 + *
6951 + * @return EC_NO_ERRORS (ok).<BR>
6952 + * Possible Error Codes:<BR>
6953 + * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
6954 + * Any error code from halChannelTeardown().<BR>
6955 + */
6956 +static int halClose(HAL_DEVICE *HalDev, bit32 Mode)
6957 + {
6958 + int Ch, Inst, Ret;
6959 + OS_DEVICE *TmpOsDev;
6960 + OS_FUNCTIONS *TmpOsFunc;
6961 + HAL_FUNCTIONS *TmpHalFunc;
6962 + char *TmpDeviceInfo;
6963 +
6964 + int Ticks; /*MJH~030306*/
6965 +
6966 + /* Verify proper device state */
6967 + if (HalDev->State != enOpened)
6968 + return (EC_CPMAC | EC_FUNC_CLOSE|EC_VAL_INVALID_STATE);
6969 +
6970 + /* Teardown all open channels */
6971 + for (Ch = 0; Ch <= (MAX_CHAN-1) ; Ch++)
6972 + {
6973 + if (HalDev->ChIsOpen[Ch][DIRECTION_TX] == TRUE)
6974 + {
6975 + if (Mode == 1)
6976 + {
6977 + Ret = halChannelTeardown(HalDev, Ch, TX_TEARDOWN | PARTIAL_TEARDOWN | BLOCKING_TEARDOWN);
6978 + if (Ret) return (Ret);
6979 + }
6980 + else
6981 + {
6982 + Ret = halChannelTeardown(HalDev, Ch, TX_TEARDOWN | FULL_TEARDOWN | BLOCKING_TEARDOWN);
6983 + if (Ret) return (Ret);
6984 + }
6985 + }
6986 +
6987 + if (HalDev->ChIsOpen[Ch][DIRECTION_RX] == TRUE)
6988 + {
6989 + if (Mode == 1)
6990 + {
6991 + Ret = halChannelTeardown(HalDev, Ch, RX_TEARDOWN | PARTIAL_TEARDOWN | BLOCKING_TEARDOWN);
6992 + if (Ret) return (Ret);
6993 + }
6994 + else
6995 + {
6996 + Ret = halChannelTeardown(HalDev, Ch, RX_TEARDOWN | FULL_TEARDOWN | BLOCKING_TEARDOWN);
6997 + if (Ret) return (Ret);
6998 + }
6999 + }
7000 + }
7001 +
7002 + /* free fraglist in HalDev */
7003 + HalDev->OsFunc->Free(HalDev->fraglist);
7004 + HalDev->fraglist = 0;
7005 +
7006 + /* unregister the interrupt */
7007 + HalDev->OsFunc->IsrUnRegister(HalDev->OsDev, HalDev->interrupt);
7008 +
7009 + Ticks = 0; /* Disable Tick Timer */ /*MJH+030306*/
7010 + HalDev->OsFunc->Control(HalDev->OsDev, hcTick, hcClear, &Ticks); /*MJH+030306*/
7011 +
7012 + /* Free the Phy Information Structure */
7013 + if(HalDev->PhyDev)
7014 + {
7015 + HalDev->OsFunc->Free(HalDev->PhyDev); /*MJH+030513*/
7016 + HalDev->PhyDev = 0; /*MJH+030522*/
7017 + }
7018 +
7019 + /* Perform CPMAC specific closing functions */
7020 + CPMAC_MACCONTROL(HalDev->dev_base) &= ~MII_EN;
7021 + CPMAC_TX_CONTROL(HalDev->dev_base) &= ~TX_EN;
7022 + CPMAC_RX_CONTROL(HalDev->dev_base) &= ~RX_EN;
7023 +
7024 + /* put device back into reset */
7025 + (*(volatile bit32u *)(HalDev->ResetBase)) &=~ (1<<HalDev->ResetBit);
7026 + Ticks = 64; /*MJH~030306*/
7027 + osfuncSleep(&Ticks);
7028 +
7029 + /* If mode is 3, than clear the HalDev and set next state to DevFound*/
7030 + if (Mode == 3)
7031 + {
7032 + /* I need to keep the HalDev parameters that were setup in InitModule */
7033 + TmpOsDev = HalDev->OsDev;
7034 + TmpOsFunc = HalDev->OsFunc;
7035 + TmpDeviceInfo = HalDev->DeviceInfo;
7036 +
7037 + TmpHalFunc = HalDev->HalFuncPtr;
7038 + Inst = HalDev->Inst;
7039 +
7040 + /* Clear HalDev */
7041 +
7042 + HalDev->OsFunc->Memset(HalDev, 0, sizeof(HAL_DEVICE));
7043 +
7044 + /* Restore key parameters */
7045 + HalDev->OsDev = TmpOsDev;
7046 + HalDev->OsFunc = TmpOsFunc;
7047 + HalDev->DeviceInfo = TmpDeviceInfo;
7048 +
7049 + HalDev->HalFuncPtr = TmpHalFunc;
7050 + HalDev->Inst = Inst;
7051 +
7052 + HalDev->State = enDevFound;
7053 + }
7054 + else
7055 + {
7056 + HalDev->State = enInitialized;
7057 + }
7058 +
7059 + return(EC_NO_ERRORS);
7060 + }
7061 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpremap_cpmac.c linux-2.4.30/drivers/net/avalanche_cpmac/cpremap_cpmac.c
7062 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpremap_cpmac.c 1970-01-01 02:00:00.000000000 +0200
7063 +++ linux-2.4.30/drivers/net/avalanche_cpmac/cpremap_cpmac.c 2005-04-15 05:10:41.000000000 +0200
7064 @@ -0,0 +1,28 @@
7065 +#ifndef _INC_CPREMAP_C
7066 +#define _INC_CPREMAP_C
7067 +
7068 +#ifdef __ADAM2
7069 +static inline void osfuncDataCacheHitInvalidate(void *ptr, int Size)
7070 + {
7071 + asm(" cache 17, (%0)" : : "r" (ptr));
7072 + }
7073 +
7074 +static inline void osfuncDataCacheHitWriteback(void *ptr, int Size)
7075 + {
7076 + asm(" cache 25, (%0)" : : "r" (ptr));
7077 + }
7078 +
7079 +static inline void osfuncDataCacheHitWritebackAndInvalidate(void *ptr, int Size)
7080 + {
7081 + asm(" cache 21, (%0)" : : "r" (ptr));
7082 + }
7083 +
7084 +#else
7085 +
7086 +#define osfuncDataCacheHitInvalidate(MemPtr, Size) __asm__(" .set mips3; cache 17, (%0); .set mips0" : : "r" (MemPtr))
7087 +#define osfuncDataCacheHitWritebackAndInvalidate(MemPtr, Size) __asm__(" .set mips3; cache 21, (%0); .set mips0" : : "r" (MemPtr))
7088 +#define osfuncDataCacheHitWriteback(MemPtr, Size) __asm__(" .set mips3; cache 25, (%0); .set mips0" : : "r" (MemPtr))
7089 +
7090 +#endif
7091 +
7092 +#endif
7093 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpswhal_cpmac.h linux-2.4.30/drivers/net/avalanche_cpmac/cpswhal_cpmac.h
7094 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/cpswhal_cpmac.h 1970-01-01 02:00:00.000000000 +0200
7095 +++ linux-2.4.30/drivers/net/avalanche_cpmac/cpswhal_cpmac.h 2005-04-15 05:10:41.000000000 +0200
7096 @@ -0,0 +1,632 @@
7097 +/************************************************************************
7098 + * TNETDxxxx Software Support
7099 + * Copyright (c) 2002 Texas Instruments Incorporated. All Rights Reserved.
7100 + *
7101 + * FILE: cphal.h
7102 + *
7103 + * DESCRIPTION:
7104 + * User include file, contains data definitions shared between the CPHAL
7105 + * and the upper-layer software.
7106 + *
7107 + * HISTORY:
7108 + * Date Modifier Ver Notes
7109 + * 28Feb02 Greg 1.00 Original
7110 + * 06Mar02 Greg 1.01 Documentation enhanced
7111 + * 18Jul02 Greg 1.02 Many updates (OAM additions, general reorg)
7112 + * 22Nov02 Mick RC2 Additions from Denis' input on Control
7113 + *
7114 + * author Greg Guyotte
7115 + * version 1.02
7116 + * date 18-Jul-2002
7117 + *****************************************************************************/
7118 +#ifndef _INC_CPHAL_H
7119 +#define _INC_CPHAL_H
7120 +
7121 +#ifdef _CPHAL_CPMAC
7122 +#include "ec_errors_cpmac.h"
7123 +#endif
7124 +
7125 +#ifdef _CPHAL_AAL5
7126 +#include "ec_errors_cpaal5.h"
7127 +#endif
7128 +
7129 +#ifdef _CPHAL_CPSAR
7130 +#include "ec_errors_cpsar.h"
7131 +#endif
7132 +
7133 +#ifdef _CPHAL_AAL2
7134 +#include "ec_errors_cpaal2.h"
7135 +#endif
7136 +
7137 +#ifndef __ADAM2
7138 +typedef char bit8;
7139 +typedef short bit16;
7140 +typedef int bit32;
7141 +
7142 +typedef unsigned char bit8u;
7143 +typedef unsigned short bit16u;
7144 +typedef unsigned int bit32u;
7145 +
7146 +/*
7147 +typedef char INT8;
7148 +typedef short INT16;
7149 +typedef int INT32;
7150 +typedef unsigned char UINT8;
7151 +typedef unsigned short UINT16;
7152 +typedef unsigned int UINT32;
7153 +*/
7154 +/*typedef unsigned int size_t;*/
7155 +#endif
7156 +
7157 +#ifdef _CPHAL
7158 +
7159 +#ifndef TRUE
7160 +#define TRUE (1==1)
7161 +#endif
7162 +
7163 +#ifndef FALSE
7164 +#define FALSE (1==2)
7165 +#endif
7166 +
7167 +#ifndef NULL
7168 +#define NULL 0
7169 +#endif
7170 +
7171 +#endif
7172 +
7173 +#define VirtToPhys(a) (((int)a)&~0xe0000000)
7174 +#define VirtToVirtNoCache(a) ((void*)((VirtToPhys(a))|0xa0000000))
7175 +#define VirtToVirtCache(a) ((void*)((VirtToPhys(a))|0x80000000))
7176 +#define PhysToVirtNoCache(a) ((void*)(((int)a)|0xa0000000))
7177 +#define PhysToVirtCache(a) ((void*)(((int)a)|0x80000000))
7178 +/*
7179 +#define DataCacheHitInvalidate(a) {__asm__(" cache 17, (%0)" : : "r" (a));}
7180 +#define DataCacheHitWriteback(a) {__asm__(" cache 25, (%0)" : : "r" (a));}
7181 +*/
7182 +
7183 +#define PARTIAL 1 /**< Used in @c Close() and @c ChannelTeardown() */
7184 +#define FULL 2 /**< Used in @c Close() and @c ChannelTeardown() */
7185 +
7186 +/* Channel Teardown Defines */
7187 +#define RX_TEARDOWN 2
7188 +#define TX_TEARDOWN 1
7189 +#define BLOCKING_TEARDOWN 8
7190 +#define FULL_TEARDOWN 4
7191 +#define PARTIAL_TEARDOWN 0
7192 +
7193 +#define MAX_DIR 2
7194 +#define DIRECTION_TX 0
7195 +#define DIRECTION_RX 1
7196 +#define TX_CH 0
7197 +#define RX_CH 1
7198 +#define HAL_ERROR_DEVICE_NOT_FOUND 1
7199 +#define HAL_ERROR_FAILED_MALLOC 2
7200 +#define HAL_ERROR_OSFUNC_SIZE 3
7201 +#define HAL_DEFAULT 0xFFFFFFFF
7202 +#define VALID(val) (val!=HAL_DEFAULT)
7203 +
7204 +/*
7205 +ERROR REPORTING
7206 +
7207 +HAL Module Codes. Each HAL module reporting an error code
7208 +should OR the error code with the respective Module error code
7209 +from the list below.
7210 +*/
7211 +#define EC_AAL5 EC_HAL|EC_DEV_AAL5
7212 +#define EC_AAL2 EC_HAL|EC_DEV_AAL2
7213 +#define EC_CPSAR EC_HAL|EC_DEV_CPSAR
7214 +#define EC_CPMAC EC_HAL|EC_DEV_CPMAC
7215 +#define EC_VDMA EC_HAL|EC_DEV_VDMA
7216 +#define EC_VLYNQ EC_HAL|EC_DEV_VLYNQ
7217 +#define EC_CPPI EC_HAL|EC_DEV_CPPI
7218 +
7219 +/*
7220 +HAL Function Codes. Each HAL module reporting an error code
7221 +should OR the error code with one of the function codes from
7222 +the list below.
7223 +*/
7224 +#define EC_FUNC_HAL_INIT EC_FUNC(1)
7225 +#define EC_FUNC_CHSETUP EC_FUNC(2)
7226 +#define EC_FUNC_CHTEARDOWN EC_FUNC(3)
7227 +#define EC_FUNC_RXRETURN EC_FUNC(4)
7228 +#define EC_FUNC_SEND EC_FUNC(5)
7229 +#define EC_FUNC_RXINT EC_FUNC(6)
7230 +#define EC_FUNC_TXINT EC_FUNC(7)
7231 +#define EC_FUNC_AAL2_VDMA EC_FUNC(8)
7232 +#define EC_FUNC_OPTIONS EC_FUNC(9)
7233 +#define EC_FUNC_PROBE EC_FUNC(10)
7234 +#define EC_FUNC_OPEN EC_FUNC(11)
7235 +#define EC_FUNC_CONTROL EC_FUNC(12)
7236 +#define EC_FUNC_DEVICE_INT EC_FUNC(13)
7237 +#define EC_FUNC_STATUS EC_FUNC(14)
7238 +#define EC_FUNC_TICK EC_FUNC(15)
7239 +#define EC_FUNC_CLOSE EC_FUNC(16)
7240 +#define EC_FUNC_SHUTDOWN EC_FUNC(17)
7241 +#define EC_FUNC_DEVICE_INT_ALT EC_FUNC(18) /* +GSG 030306 */
7242 +
7243 +/*
7244 +HAL Error Codes. The list below defines every type of error
7245 +used in all HAL modules. DO NOT CHANGE THESE VALUES! Add new
7246 +values in integer order to the bottom of the list.
7247 +*/
7248 +#define EC_VAL_PDSP_LOAD_FAIL EC_ERR(0x01)|EC_CRITICAL
7249 +#define EC_VAL_FIRMWARE_TOO_LARGE EC_ERR(0x02)|EC_CRITICAL
7250 +#define EC_VAL_DEVICE_NOT_FOUND EC_ERR(0x03)|EC_CRITICAL
7251 +#define EC_VAL_BASE_ADDR_NOT_FOUND EC_ERR(0x04)|EC_CRITICAL
7252 +#define EC_VAL_RESET_BIT_NOT_FOUND EC_ERR(0x05)|EC_CRITICAL
7253 +#define EC_VAL_CH_INFO_NOT_FOUND EC_ERR(0x06)
7254 +#define EC_VAL_RX_STATE_RAM_NOT_CLEARED EC_ERR(0x07)|EC_CRITICAL
7255 +#define EC_VAL_TX_STATE_RAM_NOT_CLEARED EC_ERR(0x08)|EC_CRITICAL
7256 +#define EC_VAL_MALLOC_DEV_FAILED EC_ERR(0x09)
7257 +#define EC_VAL_OS_VERSION_NOT_SUPPORTED EC_ERR(0x0A)|EC_CRITICAL
7258 +#define EC_VAL_CPSAR_VERSION_NOT_SUPPORTED EC_ERR(0x0B)|EC_CRITICAL
7259 +#define EC_VAL_NULL_CPSAR_DEV EC_ERR(0x0C)|EC_CRITICAL
7260 +
7261 +#define EC_VAL_LUT_NOT_READY EC_ERR(0x0D)
7262 +#define EC_VAL_INVALID_CH EC_ERR(0x0E)
7263 +#define EC_VAL_NULL_CH_STRUCT EC_ERR(0x0F)
7264 +#define EC_VAL_RX_TEARDOWN_ALREADY_PEND EC_ERR(0x10)
7265 +#define EC_VAL_TX_TEARDOWN_ALREADY_PEND EC_ERR(0x11)
7266 +#define EC_VAL_RX_CH_ALREADY_TORNDOWN EC_ERR(0x12)
7267 +#define EC_VAL_TX_CH_ALREADY_TORNDOWN EC_ERR(0x13)
7268 +#define EC_VAL_TX_TEARDOWN_TIMEOUT EC_ERR(0x14)
7269 +#define EC_VAL_RX_TEARDOWN_TIMEOUT EC_ERR(0x15)
7270 +#define EC_VAL_CH_ALREADY_TORNDOWN EC_ERR(0x16)
7271 +#define EC_VAL_VC_SETUP_NOT_READY EC_ERR(0x17)
7272 +#define EC_VAL_VC_TEARDOWN_NOT_READY EC_ERR(0x18)
7273 +#define EC_VAL_INVALID_VC EC_ERR(0x19)
7274 +#define EC_VAL_INVALID_LC EC_ERR(0x20)
7275 +#define EC_VAL_INVALID_VDMA_CH EC_ERR(0x21)
7276 +#define EC_VAL_INVALID_CID EC_ERR(0x22)
7277 +#define EC_VAL_INVALID_UUI EC_ERR(0x23)
7278 +#define EC_VAL_INVALID_UUI_DISCARD EC_ERR(0x24)
7279 +#define EC_VAL_CH_ALREADY_OPEN EC_ERR(0x25)
7280 +
7281 +#define EC_VAL_RCB_MALLOC_FAILED EC_ERR(0x26)
7282 +#define EC_VAL_RX_BUFFER_MALLOC_FAILED EC_ERR(0x27)
7283 +#define EC_VAL_OUT_OF_TCBS EC_ERR(0x28)
7284 +#define EC_VAL_NO_TCBS EC_ERR(0x29)
7285 +#define EC_VAL_NULL_RCB EC_ERR(0x30)|EC_CRITICAL
7286 +#define EC_VAL_SOP_ERROR EC_ERR(0x31)|EC_CRITICAL
7287 +#define EC_VAL_EOP_ERROR EC_ERR(0x32)|EC_CRITICAL
7288 +#define EC_VAL_NULL_TCB EC_ERR(0x33)|EC_CRITICAL
7289 +#define EC_VAL_CORRUPT_RCB_CHAIN EC_ERR(0x34)|EC_CRITICAL
7290 +#define EC_VAL_TCB_MALLOC_FAILED EC_ERR(0x35)
7291 +
7292 +#define EC_VAL_DISABLE_POLLING_FAILED EC_ERR(0x36)
7293 +#define EC_VAL_KEY_NOT_FOUND EC_ERR(0x37)
7294 +#define EC_VAL_MALLOC_FAILED EC_ERR(0x38)
7295 +#define EC_VAL_RESET_BASE_NOT_FOUND EC_ERR(0x39)|EC_CRITICAL
7296 +#define EC_VAL_INVALID_STATE EC_ERR(0x40)
7297 +#define EC_VAL_NO_TXH_WORK_TO_DO EC_ERR(0x41)
7298 +#define EC_VAL_NO_TXL_WORK_TO_DO EC_ERR(0x42)
7299 +#define EC_VAL_NO_RX_WORK_TO_DO EC_ERR(0x43)
7300 +#define EC_VAL_NOT_LINKED EC_ERR(0x44)
7301 +#define EC_VAL_INTERRUPT_NOT_FOUND EC_ERR(0x45)
7302 +#define EC_VAL_OFFSET_NOT_FOUND EC_ERR(0x46)
7303 +#define EC_VAL_MODULE_ALREADY_CLOSED EC_ERR(0x47)
7304 +#define EC_VAL_MODULE_ALREADY_SHUTDOWN EC_ERR(0x48)
7305 +#define EC_VAL_ACTION_NOT_FOUND EC_ERR(0x49)
7306 +#define EC_VAL_RX_CH_ALREADY_SETUP EC_ERR(0x50)
7307 +#define EC_VAL_TX_CH_ALREADY_SETUP EC_ERR(0x51)
7308 +#define EC_VAL_RX_CH_ALREADY_OPEN EC_ERR(0x52)
7309 +#define EC_VAL_TX_CH_ALREADY_OPEN EC_ERR(0x53)
7310 +#define EC_VAL_CH_ALREADY_SETUP EC_ERR(0x54)
7311 +#define EC_VAL_RCB_NEEDS_BUFFER EC_ERR(0x55) /* +GSG 030410 */
7312 +#define EC_VAL_RCB_DROPPED EC_ERR(0x56) /* +GSG 030410 */
7313 +#define EC_VAL_INVALID_VALUE EC_ERR(0x57)
7314 +
7315 +/**
7316 +@defgroup shared_data Shared Data Structures
7317 +
7318 +The data structures documented here are shared by all modules.
7319 +*/
7320 +
7321 +/**
7322 + * @ingroup shared_data
7323 + * This is the fragment list structure. Each fragment list entry contains a
7324 + * length and a data buffer.
7325 + */
7326 +typedef struct
7327 + {
7328 + bit32u len; /**< Length of the fragment in bytes (lower 16 bits are valid). For SOP, upper 16 bits is the buffer offset. */
7329 + void *data; /**< Pointer to fragment data. */
7330 + void *OsInfo; /**< Pointer to OS defined data. */
7331 + }FRAGLIST;
7332 +
7333 +#if defined (_CPHAL_CPMAC)
7334 +#define CB_PASSCRC_BIT (1<<26)
7335 +
7336 +/* CPMAC CPHAL STATUS */
7337 +#define CPMAC_STATUS_LINK (1 << 0)
7338 +#define CPMAC_STATUS_LINK_DUPLEX (1 << 1) /* 0 - HD, 1 - FD */
7339 +#define CPMAC_STATUS_LINK_SPEED (1 << 2) /* 0 - 10, 1 - 100 */
7340 +
7341 +/* ADAPTER CHECK Codes */
7342 +
7343 +#define CPMAC_STATUS_ADAPTER_CHECK (1 << 7)
7344 +#define CPMAC_STATUS_HOST_ERR_DIRECTION (1 << 8)
7345 +#define CPMAC_STATUS_HOST_ERR_CODE (0xF << 9)
7346 +#define CPMAC_STATUS_HOST_ERR_CH (0x7 << 13)
7347 +
7348 +#define _CPMDIO_DISABLE (1 << 0)
7349 +#define _CPMDIO_HD (1 << 1)
7350 +#define _CPMDIO_FD (1 << 2)
7351 +#define _CPMDIO_10 (1 << 3)
7352 +#define _CPMDIO_100 (1 << 4)
7353 +#define _CPMDIO_NEG_OFF (1 << 5)
7354 +#define _CPMDIO_LOOPBK (1 << 16)
7355 +#define _CPMDIO_AUTOMDIX (1 << 17) /* Bit 16 and above not used by MII register */
7356 +#define _CPMDIO_NOPHY (1 << 20)
7357 +#endif
7358 +
7359 +/**
7360 + * @ingroup shared_data
7361 + * Channel specific configuration information. This structure should be
7362 + * populated by upper-layer software prior to calling @c ChannelSetup(). Any
7363 + * configuration item that can be changed on a per channel basis should
7364 + * be represented here. Each module may define this structure with additional
7365 + * module-specific members.
7366 + */
7367 +typedef struct
7368 + {
7369 + int Channel; /**< Channel number. */
7370 + int Direction; /**< DIRECTION_RX(1) or DIRECTION_TX(0). */
7371 + OS_SETUP *OsSetup; /**< OS defined information associated with this channel. */
7372 +
7373 +#if defined(_CPHAL_AAL5) || defined (_CPHAL_CPSAR) || defined (_CPHAL_CPMAC)
7374 + int RxBufSize; /**< Size (in bytes) for each Rx buffer.*/
7375 + int RxBufferOffset; /**< Number of bytes to offset rx data from start of buffer (must be less than buffer size). */
7376 + int RxNumBuffers; /**< The number of Rx buffer descriptors to allocate for Ch. */
7377 + int RxServiceMax; /**< Maximum number of packets to service at one time. */
7378 +
7379 + int TxNumBuffers; /**< The number of Tx buffer descriptors to allocate for Ch. */
7380 + int TxNumQueues; /**< Number of Tx queues for this channel (1-2). Choosing 2 enables a low priority SAR queue. */
7381 + int TxServiceMax; /**< Maximum number of packets to service at one time. */
7382 +#endif
7383 +
7384 +#if defined(_CPHAL_AAL5) || defined(_CPHAL_CPSAR)
7385 + int CpcsUU; /**< The 2-byte CPCS UU and CPI information. */
7386 + int Gfc; /**< Generic Flow Control. */
7387 + int Clp; /**< Cell Loss Priority. */
7388 + int Pti; /**< Payload Type Indication. */
7389 +#endif
7390 +
7391 +#if defined(_CPHAL_AAL2) || defined(_CPHAL_AAL5) || defined(_CPHAL_CPSAR)
7392 + int DaMask; /**< Specifies whether credit issuance is paused when Tx data not available. */
7393 + int Priority; /**< Priority bin this channel will be scheduled within. */
7394 + int PktType; /**< 0=AAL5,1=Null AAL,2=OAM,3=Transparent,4=AAL2. */
7395 + int Vci; /**< Virtual Channel Identifier. */
7396 + int Vpi; /**< Virtual Path Identifier. */
7397 + int FwdUnkVc; /**< Enables forwarding of unknown VCI/VPI cells to host. 1=enable, 0=disable. */
7398 +
7399 + /* Tx VC State */
7400 + int TxVc_CellRate; /**< Tx rate, set as clock ticks between transmissions (SCR for VBR, CBR for CBR). */
7401 + int TxVc_QosType; /**< 0=CBR,1=VBR,2=UBR,3=UBRmcr. */
7402 + int TxVc_Mbs; /**< Min Burst Size in cells.*/
7403 + int TxVc_Pcr; /**< Peak Cell Rate for VBR in clock ticks between transmissions. */
7404 +
7405 + bit32 TxVc_AtmHeader; /**< ATM Header placed on firmware gen'd OAM cells for this Tx Ch (must be big endian with 0 PTI). */
7406 + int TxVc_OamTc; /**< TC Path to transmit OAM cells for TX connection (0,1). */
7407 + int TxVc_VpOffset; /**< Offset to the OAM VP state table. */
7408 + /* Rx VC State */
7409 + int RxVc_OamCh; /**< Ch to terminate rx'd OAM cells to be forwarded to the host. */
7410 + int RxVc_OamToHost; /**< 0=do not pass, 1=pass. */
7411 + bit32 RxVc_AtmHeader; /**< ATM Header placed on firmware gen'd OAM cells for this Rx conn (must be big endian with 0 PTI). */
7412 + int RxVc_OamTc; /**< TC Path to transmit OAM cells for RX connection (0,1). */
7413 + int RxVc_VpOffset; /**< Offset to the OAM VP state table. */
7414 + /* Tx VP State */
7415 + int TxVp_OamTc; /**< TC Path to transmit OAM cells for TX VP connection (0,1). */
7416 + bit32 TxVp_AtmHeader; /**< ATM Header placed on firmware gen'd VP OAM cells for this Tx VP conn (must be big endian with 0 VCI). */
7417 + /* Rx VP State */
7418 + int RxVp_OamCh; /**< Ch to terminate rx'd OAM cells to be forwarded to the host. */
7419 + int RxVp_OamToHost; /**< 0=do not pass, 1=pass. */
7420 + bit32 RxVp_AtmHeader; /**< ATM Header placed on firmware gen'd OAM cells for this Rx VP conn (must be big endian with 0 VCI). */
7421 + int RxVp_OamTc; /**< TC Path to transmit OAM cells for RX VP connection (0,1). */
7422 + int RxVp_OamVcList; /**< Indicates all VC channels associated with this VP channel (one-hot encoded). */
7423 +#endif
7424 +
7425 +
7426 +#ifdef _CPHAL_VDMAVT
7427 + bit32u RemFifoAddr; /* Mirror mode only. */
7428 + bit32u FifoAddr;
7429 + bit32 PollInt;
7430 + bit32 FifoSize;
7431 + int Ready;
7432 +#endif
7433 +
7434 + }CHANNEL_INFO;
7435 +
7436 +/*
7437 + * This structure contains each statistic value gathered by the CPHAL.
7438 + * Applications may access statistics data by using the @c StatsGet() routine.
7439 + */
7440 +/* STATS */
7441 +#if defined(_CPHAL_AAL2) || defined(_CPHAL_AAL5) || defined(_CPHAL_CPSAR)
7442 +typedef struct
7443 + {
7444 + bit32u CrcErrors[16];
7445 + bit32u LenErrors[16];
7446 + bit32u DmaLenErrors[16];
7447 + bit32u AbortErrors[16];
7448 + bit32u StarvErrors[16];
7449 + bit32u TxMisQCnt[16][2];
7450 + bit32u RxMisQCnt[16];
7451 + bit32u RxEOQCnt[16];
7452 + bit32u TxEOQCnt[16][2];
7453 + bit32u RxPacketsServiced[16];
7454 + bit32u TxPacketsServiced[16][2];
7455 + bit32u RxMaxServiced;
7456 + bit32u TxMaxServiced[16][2];
7457 + bit32u RxTotal;
7458 + bit32u TxTotal;
7459 + } STAT_INFO;
7460 +#endif
7461 +
7462 +/*
7463 + * VDMA Channel specific configuration information
7464 + */
7465 +#ifdef _CPHAL_AAL2
7466 +typedef struct
7467 + {
7468 + int Ch; /**< Channel Number */
7469 + int RemoteEndian; /**< Endianness of remote VDMA-VT device */
7470 + int CpsSwap; /**< When 0, octet 0 in CPS pkt located in LS byte of 16-bit word sent to rem VDMA device. When 1, in MS byte. */
7471 + }VdmaChInfo;
7472 +#endif
7473 +
7474 +#ifndef _CPHAL
7475 + typedef void HAL_DEVICE;
7476 + typedef void HAL_PRIVATE;
7477 + typedef void HAL_RCB;
7478 + typedef void HAL_RECEIVEINFO;
7479 +#endif
7480 +
7481 +/**
7482 + * @ingroup shared_data
7483 + * The HAL_FUNCTIONS struct defines the function pointers used by upper layer
7484 + * software. The upper layer software receives these pointers through the
7485 + * call to xxxInitModule().
7486 + */
7487 +typedef struct
7488 + {
7489 + int (*ChannelSetup) (HAL_DEVICE *HalDev, CHANNEL_INFO *Channel, OS_SETUP *OsSetup);
7490 + int (*ChannelTeardown) (HAL_DEVICE *HalDev, int Channel, int Mode);
7491 + int (*Close) (HAL_DEVICE *HalDev, int Mode);
7492 + int (*Control) (HAL_DEVICE *HalDev, const char *Key, const char *Action, void *Value);
7493 + int (*Init) (HAL_DEVICE *HalDev);
7494 + int (*Open) (HAL_DEVICE *HalDev);
7495 + int (*PacketProcessEnd) (HAL_DEVICE *HalDev);
7496 + int (*Probe) (HAL_DEVICE *HalDev);
7497 + int (*RxReturn) (HAL_RECEIVEINFO *HalReceiveInfo, int StripFlag);
7498 + int (*Send) (HAL_DEVICE *HalDev, FRAGLIST *FragList, int FragCount, int PacketSize, OS_SENDINFO *OsSendInfo, bit32u Mode);
7499 + int (*Shutdown) (HAL_DEVICE *HalDev);
7500 + int (*Tick) (HAL_DEVICE *HalDev);
7501 +
7502 +#ifdef _CPHAL_AAL5
7503 + int (*Kick) (HAL_DEVICE *HalDev, int Queue);
7504 + void (*OamFuncConfig) (HAL_DEVICE *HalDev, unsigned int OamConfig);
7505 + void (*OamLoopbackConfig) (HAL_DEVICE *HalDev, unsigned int OamConfig, unsigned int *LLID, unsigned int CorrelationTag);
7506 + volatile bit32u* (*RegAccess)(HAL_DEVICE *HalDev, bit32u RegOffset);
7507 + STAT_INFO* (*StatsGetOld)(HAL_DEVICE *HalDev);
7508 +#endif
7509 + } HAL_FUNCTIONS;
7510 +
7511 +/**
7512 + * @ingroup shared_data
7513 + * The OS_FUNCTIONS struct defines the function pointers for all upper layer
7514 + * functions accessible to the CPHAL. The upper layer software is responsible
7515 + * for providing the correct OS-specific implementations for the following
7516 + * functions. It is populated by calling InitModule() (done by the CPHAL in
7517 + * xxxInitModule().
7518 + */
7519 +typedef struct
7520 + {
7521 + int (*Control)(OS_DEVICE *OsDev, const char *Key, const char *Action, void *Value);
7522 + void (*CriticalOn)(void);
7523 + void (*CriticalOff)(void);
7524 + void (*DataCacheHitInvalidate)(void *MemPtr, int Size);
7525 + void (*DataCacheHitWriteback)(void *MemPtr, int Size);
7526 + int (*DeviceFindInfo)(int Inst, const char *DeviceName, void *DeviceInfo);
7527 + int (*DeviceFindParmUint)(void *DeviceInfo, const char *Parm, bit32u *Value);
7528 + int (*DeviceFindParmValue)(void *DeviceInfo, const char *Parm, void *Value);
7529 + void (*Free)(void *MemPtr);
7530 + void (*FreeRxBuffer)(OS_RECEIVEINFO *OsReceiveInfo, void *MemPtr);
7531 + void (*FreeDev)(void *MemPtr);
7532 + void (*FreeDmaXfer)(void *MemPtr);
7533 + void (*IsrRegister)(OS_DEVICE *OsDev, int (*halISR)(HAL_DEVICE*, int*), int InterruptBit);
7534 + void (*IsrUnRegister)(OS_DEVICE *OsDev, int InterruptBit);
7535 + void* (*Malloc)(bit32u size);
7536 + void* (*MallocDev)(bit32u Size);
7537 + void* (*MallocDmaXfer)(bit32u size, void *MemBase, bit32u MemRange);
7538 + void* (*MallocRxBuffer)(bit32u size, void *MemBase, bit32u MemRange,
7539 + OS_SETUP *OsSetup, HAL_RECEIVEINFO *HalReceiveInfo,
7540 + OS_RECEIVEINFO **OsReceiveInfo, OS_DEVICE *OsDev);
7541 + void* (*Memset)(void *Dest, int C, bit32u N);
7542 + int (*Printf)(const char *Format, ...);
7543 + int (*Receive)(OS_DEVICE *OsDev,FRAGLIST *FragList,bit32u FragCount,
7544 + bit32u PacketSize,HAL_RECEIVEINFO *HalReceiveInfo, bit32u Mode);
7545 + int (*SendComplete)(OS_SENDINFO *OsSendInfo);
7546 + int (*Sprintf)(char *S, const char *Format, ...);
7547 + int (*Strcmpi)(const char *Str1, const char *Str2);
7548 + unsigned int (*Strlen)(const char *S);
7549 + char* (*Strstr)(const char *S1, const char *S2);
7550 + unsigned long (*Strtoul)(const char *Str, char **Endptr, int Base);
7551 + void (*TeardownComplete)(OS_DEVICE *OsDev, int Ch, int Direction);
7552 + } OS_FUNCTIONS;
7553 +
7554 +/************** MODULE SPECIFIC STUFF BELOW **************/
7555 +
7556 +#ifdef _CPHAL_CPMAC
7557 +
7558 +/*
7559 +int halCpmacInitModule(HAL_DEVICE **HalDev, OS_DEVICE *OsDev, HAL_FUNCTIONS *HalFunc, int (*osBridgeInitModule)(OS_FUNCTIONS *), void* (*osMallocDev) (bit32u), int *Size, int inst);
7560 +*/
7561 +
7562 +int halCpmacInitModule(HAL_DEVICE **HalDev,
7563 + OS_DEVICE *OsDev,
7564 + HAL_FUNCTIONS **HalFunc,
7565 + OS_FUNCTIONS *OsFunc,
7566 + int OsFuncSize,
7567 + int *HalFuncSize,
7568 + int Inst);
7569 +#endif
7570 +
7571 +#ifdef _CPHAL_AAL5
7572 +/*
7573 + * @ingroup shared_data
7574 + * The AAL5_FUNCTIONS struct defines the AAL5 function pointers used by upper layer
7575 + * software. The upper layer software receives these pointers through the
7576 + * call to cphalInitModule().
7577 + */
7578 +/*
7579 +typedef struct
7580 + {
7581 + int (*ChannelSetup)(HAL_DEVICE *HalDev, CHANNEL_INFO *HalCh, OS_SETUP *OsSetup);
7582 + int (*ChannelTeardown)(HAL_DEVICE *HalDev, int Ch, int Mode);
7583 + int (*Close)(HAL_DEVICE *HalDev, int Mode);
7584 + int (*Init)(HAL_DEVICE *HalDev);
7585 + int (*ModeChange)(HAL_DEVICE *HalDev, char *DeviceParms);
7586 + int (*Open)(HAL_DEVICE *HalDev);
7587 + int (*InfoGet)(HAL_DEVICE *HalDev, int Key, void *Value);
7588 + int (*Probe)(HAL_DEVICE *HalDev);
7589 + int (*RxReturn)(HAL_RECEIVEINFO *HalReceiveInfo, int StripFlag);
7590 + int (*Send)(HAL_DEVICE *HalDev,FRAGLIST *FragList,int FragCount,
7591 + int PacketSize,OS_SENDINFO *OsSendInfo,int Ch, int Queue,
7592 + bit32u Mode);
7593 + int (*StatsClear)(HAL_DEVICE *HalDev);
7594 + STAT_INFO* (*StatsGet)(HAL_DEVICE *HalDev);
7595 + int (*Status)(HAL_DEVICE *HalDev);
7596 + void (*Tick)(HAL_DEVICE *HalDev);
7597 + int (*Kick)(HAL_DEVICE *HalDev, int Queue);
7598 + volatile bit32u* (*RegAccess)(HAL_DEVICE *HalDev, bit32u RegOffset);
7599 + } AAL5_FUNCTIONS;
7600 +*/
7601 +
7602 +int cpaal5InitModule(HAL_DEVICE **HalDev,
7603 + OS_DEVICE *OsDev,
7604 + HAL_FUNCTIONS **HalFunc,
7605 + OS_FUNCTIONS *OsFunc,
7606 + int OsFuncSize,
7607 + int *HalFuncSize,
7608 + int Inst);
7609 +#endif
7610 +
7611 +#ifdef _CPHAL_AAL2
7612 +/**
7613 + * @ingroup shared_data
7614 + * The AAL2_FUNCTIONS struct defines the AAL2 function pointers used by upper layer
7615 + * software. The upper layer software receives these pointers through the
7616 + * call to cphalInitModule().
7617 + */
7618 +typedef struct
7619 + {
7620 + int (*ChannelSetup)(HAL_DEVICE *HalDev, CHANNEL_INFO *HalCh, OS_SETUP *OsSetup);
7621 + int (*ChannelTeardown)(HAL_DEVICE *HalDev, int Ch, int Mode);
7622 + int (*Close)(HAL_DEVICE *HalDev, int Mode);
7623 + int (*Init)(HAL_DEVICE *HalDev);
7624 + int (*ModeChange)(HAL_DEVICE *HalDev, char *DeviceParms);
7625 + int (*Open)(HAL_DEVICE *HalDev);
7626 + int (*OptionsGet)(HAL_DEVICE *HalDev, char *Key, bit32u *Value);
7627 + int (*Probe)(HAL_DEVICE *HalDev);
7628 +
7629 + int (*StatsClear)(HAL_DEVICE *HalDev);
7630 + STAT_INFO* (*StatsGet)(HAL_DEVICE *HalDev);
7631 + int (*Status)(HAL_DEVICE *HalDev);
7632 + void (*Tick)(HAL_DEVICE *HalDev);
7633 + int (*Aal2UuiMappingSetup)(HAL_DEVICE *HalDev, int VC, int UUI,
7634 + int VdmaCh, int UUIDiscard);
7635 + int (*Aal2RxMappingSetup)(HAL_DEVICE *HalDev, int VC, int CID,
7636 + int LC);
7637 + int (*Aal2TxMappingSetup)(HAL_DEVICE *HalDev, int VC, int LC, int VdmaCh);
7638 + int (*Aal2VdmaChSetup)(HAL_DEVICE *HalDev, bit32u RemVdmaVtAddr,
7639 + VdmaChInfo *VdmaCh);
7640 + volatile bit32u* (*RegAccess)(HAL_DEVICE *HalDev, bit32u RegOffset);
7641 + int (*Aal2ModeChange)(HAL_DEVICE *HalDev, int Vc, int RxCrossMode,
7642 + int RxMultiMode, int TxMultiMode, int SchedMode,
7643 + int TcCh);
7644 + void (*Aal2VdmaEnable)(HAL_DEVICE *HalDev, int Ch);
7645 + int (*Aal2VdmaDisable)(HAL_DEVICE *HalDev, int Ch);
7646 + } AAL2_FUNCTIONS;
7647 +
7648 +int cpaal2InitModule(HAL_DEVICE **HalDev,
7649 + OS_DEVICE *OsDev,
7650 + AAL2_FUNCTIONS **HalFunc,
7651 + OS_FUNCTIONS *OsFunc,
7652 + int OsFuncSize,
7653 + int *HalFuncSize,
7654 + int Inst);
7655 +#endif
7656 +
7657 +#ifdef _CPHAL_VDMAVT
7658 +/**
7659 + * @ingroup shared_data
7660 + * The VDMA_FUNCTIONS struct defines the HAL function pointers used by upper layer
7661 + * software. The upper layer software receives these pointers through the
7662 + * call to InitModule().
7663 + *
7664 + * Note that this list is still under definition.
7665 + */
7666 +typedef struct
7667 + {
7668 + bit32 (*Init)( HAL_DEVICE *VdmaVtDev);
7669 + /* bit32 (*SetupTxFifo)(HAL_DEVICE *VdmaVtDev, bit32u LclRem,
7670 + bit32u Addr, bit32u Size, bit32u PollInt);
7671 + bit32 (*SetupRxFifo)(HAL_DEVICE *VdmaVtDev, bit32u LclRem,
7672 + bit32u Addr, bit32u Size, bit32u PollInt); */
7673 + bit32 (*Tx)(HAL_DEVICE *VdmaVtDev);
7674 + bit32 (*Rx)(HAL_DEVICE *VdmaVtDev);
7675 + bit32 (*SetRemoteChannel)(HAL_DEVICE *VdmaVtDev, bit32u RemAddr,
7676 + bit32u RemDevID);
7677 + bit32 (*ClearRxInt)(HAL_DEVICE *VdmaVtDev);
7678 + bit32 (*ClearTxInt)(HAL_DEVICE *VdmaVtDev);
7679 + bit32 (*Open)(HAL_DEVICE *VdmaVtDev);
7680 + bit32 (*Close)(HAL_DEVICE *VdmaVtDev);
7681 + int (*Control) (HAL_DEVICE *HalDev, const char *Key, const char *Action, void *Value);
7682 + int (*ChannelSetup)(HAL_DEVICE *VdmaVtDev, CHANNEL_INFO *HalCh, OS_SETUP *OsSetup);
7683 + int (*ChannelTeardown)(HAL_DEVICE *VdmaVtDev, int Ch, int Mode);
7684 + int (*Send)(HAL_DEVICE *VdmaVtDev,FRAGLIST *FragList,int FragCount,
7685 + int PacketSize,OS_SENDINFO *OsSendInfo,bit32u Mode);
7686 + } VDMA_FUNCTIONS;
7687 +
7688 +int VdmaInitModule(HAL_DEVICE **VdmaVt,
7689 + OS_DEVICE *OsDev,
7690 + VDMA_FUNCTIONS **VdmaVtFunc,
7691 + OS_FUNCTIONS *OsFunc,
7692 + int OsFuncSize,
7693 + int *HalFuncSize,
7694 + int Inst);
7695 +#endif
7696 +
7697 +/*
7698 +extern int cphalInitModule(MODULE_TYPE ModuleType, HAL_DEVICE **HalDev, OS_DEVICE *OsDev, HAL_FUNCTIONS *HalFunc,
7699 + int (*osInitModule)(OS_FUNCTIONS *), void* (*osMallocDev)(bit32u),
7700 + int *Size, int Inst);
7701 +*/
7702 +
7703 +
7704 +#ifdef _CPHAL_AAL5
7705 +extern const char hcSarFrequency[];
7706 +#endif
7707 +
7708 +#ifdef _CPHAL_CPMAC
7709 +/* following will be common, once 'utl' added */
7710 +extern const char hcClear[];
7711 +extern const char hcGet[];
7712 +extern const char hcSet[];
7713 +extern const char hcTick[];
7714 +
7715 +extern const char hcCpuFrequency[];
7716 +extern const char hcCpmacFrequency[];
7717 +extern const char hcMdioBusFrequency[];
7718 +extern const char hcMdioClockFrequency[];
7719 +extern const char hcCpmacBase[];
7720 +extern const char hcPhyNum[];
7721 +extern const char hcSize[];
7722 +extern const char hcCpmacSize[];
7723 +extern const char hcPhyAccess[];
7724 +extern const char hcMdixMask[];
7725 +extern const char hcMdioMdixSwitch[];
7726 +#endif
7727 +
7728 +#endif /* end of _INC_ */
7729 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/dox_cpmac.h linux-2.4.30/drivers/net/avalanche_cpmac/dox_cpmac.h
7730 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/dox_cpmac.h 1970-01-01 02:00:00.000000000 +0200
7731 +++ linux-2.4.30/drivers/net/avalanche_cpmac/dox_cpmac.h 2005-04-15 05:10:41.000000000 +0200
7732 @@ -0,0 +1,842 @@
7733 +/*****************************************************************************
7734 + * TNETDxxxx Software Support
7735 + * Copyright (c) 2002,2003 Texas Instruments Incorporated. All Rights Reserved.
7736 + *
7737 + * FILE:
7738 + *
7739 + * DESCRIPTION:
7740 + * This file contains documentation for the CPMAC
7741 + *
7742 + * HISTORY:
7743 + * @author Michael Hanrahan/Greg Guyotte
7744 + * @version 1.00
7745 + * @date 03-Dec-2002
7746 + *****************************************************************************/
7747 +#ifndef _DOX_CPMAC_H
7748 +#define _DOX_CPMAC_H
7749 +/**
7750 +@page CPMAC_Implementation_Details Version
7751 +
7752 +@copydoc CPMAC_Version
7753 +*/
7754 +
7755 +/**
7756 +@page cpmac_intro Introduction
7757 +
7758 +The CPMAC implementation will support 8 channels for transmit and 8 channel for
7759 +receive. Each of the 8 transmit channels has 1 queue associated with it. It is
7760 +recommended that only 1 channel is used for @c Receive() per processor.
7761 +*/
7762 +
7763 +/**
7764 +@page cpmac_details API Implementation Details
7765 +@par osReceive
7766 +@p Mode parameter
7767 +- The Upper 16 bits of Mode match Word 3 of the Rx Buffer Descriptor
7768 +
7769 +@par halSend
7770 +@p Mode parameter
7771 +- Bits 0-7 contain the Channel Number
7772 +- Bits 8-25 are reserved
7773 +- Bit 26 - if 0, the CRC will be calculated, if 1 the CRC will be Passed
7774 +- Bits 27-31 : reserved
7775 +@section cpmac_keys Control Keys
7776 +
7777 +@par StateChange
7778 +CPHAL calls the OS when a state change is detected.
7779 +OS should check the CPMAC Status. See the Control Key 'Status' for more details.
7780 +
7781 +@par Status
7782 +OS calls the CPHAL to obtain Status information. The Returned status is as follows
7783 +
7784 +@par MaxFrags
7785 +The OS may "Set" or "Get" this value. This defines the maximum
7786 +number of fragments that can be received by the CPMAC Rx port. The default
7787 +value for CPMAC is 2. This provides enough space to receive a maximum
7788 +length packet (1,518 bytes) with the default buffer size of 1518 and any
7789 +amount of RxBufferOffset. If the buffer size is configured to be smaller,
7790 +the OS *MUST* modify this parameter according to the following formula:
7791 +((System Max packet length)/(RxBufSize)) + 1. (The extra 1 fragment is to
7792 +allow for RxBufferOffset)
7793 +
7794 +@code
7795 +// Following defined in "cpswhal_cpmac.h"
7796 +// CPMAC CPHAL STATUS
7797 +#define CPMAC_STATUS_LINK (1 << 0)
7798 +#define CPMAC_STATUS_LINK_DUPLEX (1 << 1) // 0 - HD, 1 - FD
7799 +#define CPMAC_STATUS_LINK_SPEED (1 << 2) // 0 - 10, 1 - 100
7800 +
7801 +// ADAPTER CHECK Codes
7802 +#define CPMAC_STATUS_ADAPTER_CHECK (1 << 7)
7803 +#define CPMAC_STATUS_HOST_ERR_DIRECTION (1 << 8) // 0 - Tx, 1 - Rx
7804 +#define CPMAC_STATUS_HOST_ERR_CODE (0xF << 9) See CPMAC Guide
7805 +#define CPMAC_STATUS_HOST_ERR_CH (0x7 << 13) See CPMAC Guide
7806 +@endcode
7807 +
7808 +@code
7809 +void osStateChange(OS_DEVICE *OsDev)
7810 + {
7811 + int status;
7812 + OsDev->HalFunc->Control(OsDev->HalDev, "Status", hcGet, &status);
7813 + if(status & CPMAC_STATUS_ADAPTER_CHECK)
7814 + {
7815 + printf("[osStateChange[%d]] HAL notified OS of AdapterCheck (Link Status 0x%08X)\n", OsDev->port, status);
7816 + adaptercheck(OsDev->port);
7817 + }
7818 + else
7819 + {
7820 + printf("[osStateChange[%d]] HAL notified OS of State Change (Link Status %s)\n", OsDev->port, (status & CPMAC_STATUS_LINK) ? "Up" : "Down");
7821 + if(status & CPMAC_STATUS_LINK)
7822 + {
7823 + printf("Speed %s, Duplex %s\n",
7824 + status & CPMAC_STATUS_LINK_SPEED ? "100" : "10",
7825 + status & CPMAC_STATUS_LINK_DUPLEX ? "FD" : "HD");
7826 + }
7827 + }
7828 +@endcode
7829 +
7830 +@par Tick
7831 + The CPHAL calls the OS to set the interval for calling halTick()<BR>
7832 + Note: Predefined value hcTick now recommended for use.
7833 +@code
7834 +*** Example Code ***
7835 +
7836 +*** CPHAL code ***
7837 +int Ticks;
7838 +HalDev->OsFunc->Control(HalDev->OsDev, hcTick, hcSet, &Ticks);
7839 +
7840 +*** OS code ***
7841 + ..
7842 + if(osStrcmpi(pszKey, hcTick) == 0)
7843 + {
7844 + if(osStrcmpi(pszAction, hcSet) == 0)
7845 + {
7846 + // Enable the Tick Interval
7847 + if(*(unsigned int *) ParmValue)
7848 + printf("osTickSet: Interval = %d ticks\n", Interval);
7849 + }
7850 + else
7851 + if(osStrcmpi(pszAction, hcClear) == 0)
7852 + {
7853 + // Request disabling of the Tick Timer, ParmValue is ignored
7854 + }
7855 + }
7856 +@endcode
7857 +
7858 +@par The following information can be obtained by the OS via 'Get'
7859 +
7860 +- StatsDump : OS supplies pointer to an 36 element unsigned int array
7861 +CPHAL will populate the array with the current Statistics values.<BR>
7862 +Note: all hcXXXX values are predefined and should be used by the OS.
7863 +
7864 +- hcPhyNum : Returns the PHY number.
7865 +- hcCpmacBase : Returns the base-address of the CPMAC device
7866 +- hcCpmacSize : Returns size of the CPMAC memory map
7867 +
7868 +
7869 +@par Phy Register Communication
7870 +
7871 +halControl() is used to read and write the Phy Registers via the key hcPhyAccess
7872 +
7873 +Both reading and writing the Phy registers involve setting the Value parameter of halControl()
7874 +<BR>
7875 +Value is a 32-bit value with bits partioned as follows
7876 +<BR>
7877 +
7878 + 0 - 4 Phy Number <BR>
7879 + 5 - 9 Phy Register <BR>
7880 + 10 - 15 reserved <BR>
7881 + 16 - 31 Data (write only)
7882 +<BR>
7883 +
7884 +
7885 +<B>Reading the Phy register</B>
7886 +
7887 +@code
7888 + bit32u Value;
7889 + bit32u RegAddr;
7890 + bit32u PhyNum;
7891 + bit32u PhyRegisterData;
7892 +
7893 + // Read Phy 31, register 20
7894 +
7895 + PhyNum = 31;
7896 + RegAddr = 20;
7897 +
7898 + Value = (RegAddr << 5);
7899 + Value |= (PhyNum & 0x1F);
7900 +
7901 + rc = HalFunc->Control(HalDev, hcPhyAccess, hcGet, (bit32u *) &Value)
7902 + If(rc == 0)
7903 + {
7904 + // Value is overwriten with the value in Register 20 of Phy number 31.
7905 + PhyRegisterData = Value;
7906 + }
7907 +@endcode
7908 +
7909 +<B>Writing the Phy register</B>
7910 +@code
7911 + bit32u Value;
7912 + bit32u RegAddr;
7913 + bit32u PhyNum;
7914 + bit32u PhyRegisterData;
7915 +
7916 + // Reset Phy 23
7917 +
7918 + PhyNum = 23;
7919 + RegAddr = 0;
7920 + PhyRegisterData = 0x8000; // Reset bit set
7921 +
7922 + Value = (RegAddr << 5);
7923 + Value |= (PhyNum & 0x1F);
7924 + Value |= (PhyRegisterData << 16);
7925 +
7926 + rc = HalFunc->Control(HalDev, hcPhyAccess, hcSet, (bit32u *) &Value)
7927 +
7928 + // Check is reset if done
7929 +
7930 + PhyNum = 23;
7931 + RegAddr = 0;
7932 +
7933 + Value = (RegAddr << 5);
7934 + Value |= (PhyNum & 0x1F);
7935 +
7936 + rc = HalFunc->Control(HalDev, hcPhyAccess, hcGet, (bit32u *) &Value)
7937 +
7938 + If(rc == 0)
7939 + {
7940 + // Value is overwriten with the value in Register 0 of Phy number 23.
7941 + PhyRegisterData = Value;
7942 + if((PhyRegisterData & 0x8000) == 0)
7943 + ResetIsComplete;
7944 + }
7945 +
7946 +@endcode
7947 +<B>
7948 +*** Example Showing turning values off/on ***
7949 +<BR>
7950 +</B>
7951 +
7952 +@code
7953 +
7954 +int On=1;
7955 +int Off=0;
7956 + # Turn On loopback
7957 + OsDev->HalFunc->Control(OsDev->HalDev, "CTRL_LOOPBACK", hcSet, (int*) &On);
7958 +
7959 + # Turn off RX Flow
7960 + OsDev->HalFunc->Control(OsDev->HalDev, "RX_FLOW_EN", hcSet, (int*) &Off);
7961 +@endcode
7962 +
7963 +@par CPMAC Configurable Parameters
7964 +
7965 +- RX_PASS_CRC : See MBP_Enable description
7966 +- RX_QOS_EN : See MBP_Enable description
7967 +- RX_NO_CHAIN : See MBP_Enable description
7968 +- RX_CMF_EN : See MBP_Enable description
7969 +- RX_CSF_EN : See MBP_Enable description
7970 +- RX_CEF_EN : See MBP_Enable description
7971 +- RX_CAF_EN : See MBP_Enable description
7972 +- RX_PROM_CH : See MBP_Enable description
7973 +- RX_BROAD_EN : See MBP_Enable description
7974 +- RX_BROAD_CH : See MBP_Enable description
7975 +- RX_MULT_EN : See MBP_Enable description
7976 +- RX_MULT_CH : See MBP_Enable description
7977 +
7978 +- TX_PTYPE : See MacControl description
7979 +- TX_PACE : See MacControl description
7980 +- TX_FLOW_EN : See MacControl description
7981 +- RX_FLOW_EN : See MacControl description
7982 +- CTRL_LOOPBACK : See MacControl description
7983 +
7984 +- RX_MAXLEN : See CPMAC Guide
7985 +- RX_FILTERLOWTHRESH : See CPMAC Guide
7986 +- RX0_FLOWTHRESH : See CPMAC Guide
7987 +- RX_UNICAST_SET : See CPMAC Guide
7988 +- RX_UNICAST_CLEAR : See CPMAC Guide
7989 +
7990 +@par Multicast Support
7991 +- RX_MULTI_ALL : When used with hcSet, sets all the Hash Bits. When used
7992 +with hcClear clears all the Hash Bits.
7993 +- RX_MULTI_SINGLE : When used with hcSet, adds the Hashed Mac Address. When used
7994 +with hcClear deletes the Hashed Mac Address.
7995 +Note: Support will be added to keep track of Single additions and deletions.
7996 +
7997 +@code
7998 +*** Example Code ***
7999 +
8000 +*** OS code ***
8001 + bit8u MacAddress[6];
8002 + MacAddress[0] = 0x80;
8003 + MacAddress[1] = 0x12;
8004 + MacAddress[2] = 0x34;
8005 + MacAddress[3] = 0x56;
8006 + MacAddress[4] = 0x78;
8007 + MacAddress[5] = 0x78;
8008 + OsDev->HalFunc->Control(OsDev->HalDev, "RX_MULTI_SINGLE", hcSet, (bit8u*) &MacAddress);
8009 + OsDev->HalFunc->Control(OsDev->HalDev, "RX_MULTI_SINGLE", hcClear, (bit8u*) &MacAddress);
8010 + OsDev->HalFunc->Control(OsDev->HalDev, "RX_MULTI_ALL", hcSet, NULL);
8011 + OsDev->HalFunc->Control(OsDev->HalDev, "RX_MULTI_ALL", hcClear, NULL);
8012 +@endcode
8013 +@par MdioConnect Fields
8014 +<BR>
8015 +- "MdioConnect" : The OS can set the Phy connection using this key. The default connection is Auto-Negotiation ON, All modes possible.
8016 +
8017 +
8018 +- _CPMDIO_HD <----- Allow Half Duplex, default is 1 (On)
8019 +- _CPMDIO_FD <----- Allow Full Duplex, default is 1 (On)
8020 +- _CPMDIO_10 <----- Allow 10 Mbs, default is 1 (On)
8021 +- _CPMDIO_100 <----- Allow 100 Mbs, default is 1 (On)
8022 +- _CPMDIO_NEG_OFF <----- Turn off Auto Negotiation, default is 0 (Auto Neg is on)
8023 +- _CPMDIO_NOPHY <----- Set for use with Marvel-type switch, default is 0 (Phy present)
8024 +- _CPMDIO_AUTOMDIX <---- Enables Auto Mdix (in conjunction with MdixMask), default is 1 (On)
8025 +
8026 +Note: When _CPMDIO_NOPHY is set, CPMAC will report being linked at 100/FD. Reported PhyNum will be 0xFFFFFFFF
8027 +
8028 +@par Setting CPMAC for use with a Marvel-type Switch
8029 +@code
8030 + bit32u MdioConnect;
8031 +
8032 + MdioConnect = _CPMDIO_NOPHY;
8033 + OsDev->HalFunc->Control(OsDev->HalDev, "MdioConnect", hcSet, (bit32u*) &MdioConnect);
8034 +@endcode
8035 +
8036 +@par OS Support for MDIO
8037 +@p The OS will need to supply the following values which the CPHAL will request via halControl()
8038 +<BR>
8039 +- MdioBusFrequency : The frequency of the BUS that MDIO is on (requested via hcMdioBusFrequency)
8040 +<BR>
8041 +- MdioClockFrequency : The desired Clock Frequency that MDIO qill operate at (requested via hcMdioClockFrequency)
8042 +*/
8043 +
8044 +/**
8045 +@page cpmac_conf DeviceFindxxx() Parameters
8046 +
8047 +These are some of the parameters that the CPMAC will request via the DeviceFindxxx() functions -
8048 +<BR>
8049 +- "Mlink" : bit mask indicating what link status method Phy is using. Default is MDIO state machine (0x0)
8050 +- "PhyMask" : bit mask indicating PhyNums used by this CPMAC (e.g 0x8000000, PhyNum is 31)
8051 +- "MdixMask" : bit mask indicating which Phys support AutoMdix. Default is 0x0 (None)
8052 +<BR>
8053 +@par Example cpmac definition from the options.conf for the Sangam VDB
8054 +<BR>
8055 +- cpmac( id=eth0, base=0xA8610000, size=0x800, reset_bit=17, int_line=19, PhyMask=0x80000000, MLink=0, MdixMask=0 )
8056 +*/
8057 +
8058 +/**
8059 +@page auto_mdix Auto Mdix Support
8060 +
8061 +Auto Mdix selection is controlled by two elements in the CPMAC. First the OS can turn Auto Midx On or Off by the use of the
8062 +MdioConnect field, _CPMDIO_AUTOMDIX. This is defaulted ON. For actual Auto Mdix operation the Phy must also be Auto Mdix capable.
8063 +This is specified by the DeviceFindxxx() field, "MdixMask" (supplied as the variable hcMdixMask).
8064 +If both these fields are set then the CPMDIO state machine will be enabled for Auto Mdix checking.
8065 +If a switch to MDI or MDIX mode is needed, the CPMAC will signal this to the OS via Control() using
8066 +the hcMdioMdixSwitch key.
8067 +
8068 +@par OS example for responding to a Mdix Switch Request
8069 +<BR>
8070 +@code
8071 +if(osStrcmpi(pszKey, hcMdioMdixSwitch) == 0) // See if key is Mdix Switch Request
8072 + {
8073 + if(osStrcmpi(pszAction, hcSet) == 0) // Only respond to Set requests
8074 + {
8075 +
8076 + bit32u Mdix;
8077 +
8078 + Mdix = *(bit32u *) ParmValue; // Extract requested Mode
8079 + // 0 : MDI
8080 + // 1 : MDIX
8081 + if(Mdix)
8082 + osSetPhyIntoMdixMode(); // Device specific logic
8083 + else
8084 + osSetPhyIntoMdiMode(); // Device specific logic
8085 + rc = 0; // Set return code as Successfull
8086 + }
8087 +@endcode
8088 +*/
8089 +
8090 +/**
8091 +@page cpmac_stats CPMAC Specific Statistics
8092 +
8093 +Statistics level '0' contains all CPMAC specific statistics.
8094 +
8095 +
8096 +*/
8097 +
8098 +/**
8099 +@page Example_Driver_Code
8100 +
8101 +@section example_intro Introduction
8102 +This section provides an in-depth code example for driver implementations. The code
8103 +below illustrates the use of the CPMAC HAL, but is equally applicable to any CPHAL
8104 +implementation. Note: the CPHAl constants hcGet, hcSet etc., are currently available for use with teh CPMAC module.
8105 +Other modules should continue to use pszGET, etc. until these are made generally available.
8106 +
8107 +@par Pull Model Example
8108 +
8109 +@code
8110 +
8111 +#define _CPHAL_CPMAC
8112 +
8113 +typedef struct _os_device_s OS_DEVICE;
8114 +typedef struct _os_receive_s OS_RECEIVEINFO;
8115 +typedef struct _os_send_s OS_SENDINFO;
8116 +typedef struct _os_setup_s OS_SETUP;
8117 +
8118 +#include "cpswhal_cpmac.h"
8119 +
8120 +#define dbgPrintf printf
8121 +
8122 +typedef struct _os_device_s
8123 +{
8124 + HAL_DEVICE *HalDev;
8125 + HAL_FUNCTIONS *HalFunc;
8126 + OS_FUNCTIONS *OsFunc;
8127 + OS_SETUP *OsSetup;
8128 + bit32u Interrupt;
8129 + int (*halIsr)(HAL_DEVICE *HalDev, int*);
8130 + int ModulePort;
8131 + int Protocol;
8132 + int LinkStatus; // 0-> down, otherwise up
8133 +}os_device_s;
8134 +
8135 +typedef struct _os_receive_s
8136 +{
8137 + HAL_RECEIVEINFO *HalReceiveInfo;
8138 + char *ReceiveBuffer;
8139 + OS_DEVICE *OsDev;
8140 +}os_receive_s;
8141 +
8142 +typedef struct _os_send_s
8143 +{
8144 + OS_DEVICE *OsDev;
8145 +}os_send_s;
8146 +
8147 +typedef struct _os_setup_s
8148 +{
8149 + OS_DEVICE *OsDev;
8150 +}os_setup_s;
8151 +
8152 +
8153 +
8154 +void FlowForCphal(OS_DEVICE *OsDev)
8155 +{
8156 + CHANNEL_INFO ChannelInfo;
8157 + int nChannels = 200;
8158 + int halFuncSize;
8159 + int rc;
8160 +
8161 + // Populate OsFunc structure
8162 + rc = osInitModule(OsDev);
8163 +
8164 + if(rc)
8165 + {
8166 + sprintf(bufTmp, "%s: return code from osInitModule:'0x%08X'", __FUNCTION__, rc);
8167 + errorout(bufTmp);
8168 + }
8169 +
8170 +
8171 + // OS-Cphal handshake
8172 + rc = halCpmacInitModule(&OsDev->HalDev, OsDev, &OsDev->HalFunc, OsDev->OsFunc,
8173 + sizeof(OS_FUNCTIONS), &halFuncSize, OsDev->ModulePort);
8174 +
8175 + if(rc)
8176 + {
8177 + sprintf(bufTmp, "%s: return code from halCpmacInitModule:'0x%08X'", __FUNCTION__, rc);
8178 + errorout(bufTmp);
8179 + }
8180 +
8181 + // See if hardware module exists
8182 + rc = OsDev->HalFunc->Probe(OsDev->HalDev);
8183 +
8184 + if(rc)
8185 + {
8186 + sprintf(bufTmp, "%s: return code from Probe:'0x%08X'", __FUNCTION__, rc);
8187 + errorout(bufTmp);
8188 + }
8189 +
8190 + // Initialize hardware module
8191 + rc = OsDev->HalFunc->Init(OsDev->HalDev);
8192 +
8193 + if(rc)
8194 + {
8195 + sprintf(bufTmp, "%s: return code from Init:'0x%08X'", __FUNCTION__, rc);
8196 + errorout(bufTmp);
8197 + }
8198 +
8199 + // Setup Channel Information (Tranmsit, channel 0)
8200 + ChannelInfo.Channel = 0;
8201 + ChannelInfo.Direction = DIRECTION_TX;
8202 + ChannelInfo.TxNumBuffers = nChannels;
8203 + ChannelInfo.TxNumQueues = 1;
8204 + ChannelInfo.TxServiceMax = nChannels/3;
8205 +
8206 + rc = OsDev->HalFunc->ChannelSetup(OsDev->HalDev, &ChannelInfo, OsDev->OsSetup);
8207 +
8208 + // Setup Channel Information (Receive, channel 0)
8209 + ChannelInfo.Channel = 0;
8210 + ChannelInfo.Direction = DIRECTION_RX;
8211 + ChannelInfo.RxBufSize = 1518;
8212 + ChannelInfo.RxBufferOffset = 0;
8213 + ChannelInfo.RxNumBuffers = 2*nChannels;
8214 + ChannelInfo.RxServiceMax = nChannels/3;
8215 +
8216 + rc = OsDev->HalFunc->ChannelSetup(OsDev->HalDev, &ChannelInfo, OsDev->OsSetup);
8217 +
8218 + // Open the hardware module
8219 + rc = OsDev->HalFunc->Open(OsDev->HalDev);
8220 +
8221 + // Module now ready to Send/Receive data
8222 +}
8223 +
8224 +
8225 +int osInitModule(OS_FUNCTIONS **pOsFunc)
8226 + {
8227 + OS_FUNCTIONS *OsFunc;
8228 +
8229 + OsFunc = (OS_FUNCTIONS *) malloc(sizeof(OS_FUNCTIONS));
8230 + if (!OsFunc)
8231 + return (-1);
8232 +
8233 + *pOsFunc = OsFunc;
8234 +
8235 + OsFunc->CriticalOff = osCriticalOff;
8236 + OsFunc->CriticalOn = osCriticalOn;
8237 + OsFunc->DataCacheHitInvalidate = osDataCacheHitInvalidate;
8238 + OsFunc->DataCacheHitWriteback = osDataCacheHitWriteback;
8239 + OsFunc->DeviceFindInfo = osDeviceFindInfo;
8240 + OsFunc->DeviceFindParmUint = osDeviceFindParmUint;
8241 + OsFunc->DeviceFindParmValue = osDeviceFindParmValue;
8242 + OsFunc->Free = osFree;
8243 + OsFunc->FreeDev = osFreeDev;
8244 + OsFunc->FreeDmaXfer = osFreeDmaXfer;
8245 + OsFunc->FreeRxBuffer = osFreeRxBuffer;
8246 + OsFunc->IsrRegister = osIsrRegister;
8247 + OsFunc->IsrUnRegister = osIsrUnRegister;
8248 + OsFunc->Malloc = osMalloc;
8249 + OsFunc->MallocDev = osMallocDev;
8250 + OsFunc->MallocDmaXfer = osMallocDmaXfer;
8251 + OsFunc->MallocRxBuffer = osMallocRxBuffer;
8252 +
8253 +
8254 + OsFunc->Memset = memset;
8255 + OsFunc->Printf = printf;
8256 + OsFunc->Sprintf = sprintf;
8257 + OsFunc->Strcmpi = osStrcmpi;
8258 + OsFunc->Strlen = strlen;
8259 + OsFunc->Strstr = strstr;
8260 + OsFunc->Strtoul = strtoul;
8261 +
8262 + OsFunc->Control = osControl;
8263 + OsFunc->Receive = osReceive;
8264 + OsFunc->SendComplete = osSendComplete;
8265 + OsFunc->TeardownComplete = osTearDownComplete;
8266 +
8267 + return(0);
8268 + }
8269 +
8270 +
8271 +int osReceive(OS_DEVICE *OsDev,FRAGLIST *Fraglist,bit32u FragCount,bit32u PacketSize,HAL_RECEIVEINFO *halInfo, bit32u mode)
8272 + {
8273 + OS_RECEIVEINFO *skb = (OS_RECEIVEINFO *)Fraglist[0].OsInfo;
8274 + dcache_i((char *)Fraglist->data, Fraglist->len);
8275 + OsDev->HalFunc->RxReturn(halInfo,0);
8276 + return(0);
8277 + }
8278 +
8279 +int osSendComplete(OS_SENDINFO *skb)
8280 + {
8281 + return(0);
8282 + }
8283 +
8284 +
8285 +static void *osMallocRxBuffer(bit32u Size,void *MemBase, bit32u MemRange,
8286 + OS_SETUP *OsSetup, HAL_RECEIVEINFO *HalReceiveInfo,
8287 + OS_RECEIVEINFO **OsReceiveInfo, OS_DEVICE *OsDev )
8288 + {
8289 + void *HalBuffer;
8290 + OS_RECEIVEINFO *OsPriv;
8291 +
8292 + HalBuffer=malloc(Size);
8293 + if (!HalBuffer)
8294 + {
8295 + return(0);
8296 + }
8297 +
8298 + // Malloc the OS block
8299 + *OsReceiveInfo = malloc(sizeof(OS_RECEIVEINFO));
8300 + if (!*OsReceiveInfo)
8301 + {
8302 + free(HalBuffer);
8303 + return(0);
8304 + }
8305 +
8306 + // Initialize the new buffer descriptor
8307 + OsPriv = *OsReceiveInfo;
8308 + OsPriv->OsDev = OsDev;
8309 + OsPriv->ReceiveBuffer = HalBuffer;
8310 + OsPriv->HalReceiveInfo = HalReceiveInfo;
8311 +
8312 + return(HalBuffer);
8313 + }
8314 +
8315 +
8316 +void SendBuffer(OS_DEVICE *OsDev, char *Buffer, int Size)
8317 +{
8318 + FRAGLIST Fraglist;
8319 + bit32u FragCount;
8320 +
8321 + tcb_pending++;
8322 + Fraglist.len = Size;
8323 + Fraglist.data = (unsigned *) Buffer;
8324 + FragCount = 1;
8325 + mode = 0; // Channel 0
8326 +
8327 + dcache_wb(Fraglist.data, Fraglist.len);
8328 + OsDev->HalFunc->Send(OsDev->HalDev, &Fraglist, FragCount, Size, (OS_SENDINFO *) Buffer, mode);
8329 +}
8330 +
8331 +
8332 +void osStateChange(OS_DEVICE *OsDev)
8333 + {
8334 + int status;
8335 + int LinkStatus;
8336 + OsDev->HalFunc->Control(OsDev->HalDev, "Status", hcGet, &status);
8337 + if(status & CPMAC_STATUS_ADAPTER_CHECK)
8338 + {
8339 + // Adapter Check, take appropiate action
8340 + }
8341 + else
8342 + {
8343 + LinkStatus = status & CPMAC_STATUS_LINK;
8344 + if(LinkStatus != OsDev->LinkStatus)
8345 + {
8346 + dbgPrintf("\n%s:Link %s for inst %d Speed %s, Duplex %s\n",
8347 + __FUNCTION__,
8348 + LinkStatus ? "up" : "down",
8349 + OsDev->ModulePort,
8350 + status & CPMAC_STATUS_LINK_SPEED ? "100" : "10",
8351 + status & CPMAC_STATUS_LINK_DUPLEX ? "FD" : "HD");
8352 + OsDev->LinkStatus = LinkStatus;
8353 + }
8354 + }
8355 + }
8356 +
8357 +
8358 +int osControl(OS_DEVICE *OsDev, const char *pszKey, const char* pszAction, void *ParmValue)
8359 + {
8360 + int rc=-1;
8361 +
8362 + if (osStrcmpi(pszKey, hcCpuFrequency) == 0)
8363 + {
8364 + if(osStrcmpi(pszAction, hcGet) == 0)
8365 + {
8366 + *(bit32u*) ParmValue = cpufreq;
8367 + rc = 0;
8368 + }
8369 + }
8370 + if (osStrcmpi(pszKey, hcMdioBusFrequency) == 0)
8371 + {
8372 + if(osStrcmpi(pszAction, hcGet) == 0)
8373 + {
8374 + *(bit32u *)ParmValue = MdioBusFrequency;
8375 + rc = 0;
8376 + }
8377 + }
8378 +if (osStrcmpi(pszKey, hcMdioClockFrequency) == 0)
8379 + {
8380 + if(osStrcmpi(pszAction, hcGet) == 0)
8381 + {
8382 + *(bit32u *)ParmValue = MdioClockFrequency;
8383 + rc = 0;
8384 + }
8385 + }
8386 +
8387 + if (osStrcmpi(pszKey, hcTick) == 0)
8388 + {
8389 + if(osStrcmpi(pszAction, hcSet) == 0)
8390 + {
8391 + osTickSetInterval(OsDev, *(unsigned int *) ParmValue);
8392 + rc = 0;
8393 + }
8394 + else
8395 + if(osStrcmpi(pszAction, hcClear) == 0)
8396 + {
8397 + osTickDisable(OsDev);
8398 + rc = 0;
8399 + }
8400 + }
8401 +
8402 + if (osStrcmpi(pszKey, "SioFlush") == 0)
8403 + {
8404 + MySioFlush();
8405 + rc = 0;
8406 + }
8407 +
8408 + if (osStrcmpi(pszKey, "StateChange") == 0)
8409 + {
8410 + osStateChange(OsDev);
8411 + rc = 0;
8412 + }
8413 +
8414 + if (osStrcmpi(pszKey, "Sleep") == 0)
8415 + {
8416 + osSleep(*(int *)ParmValue);
8417 + rc = 0;
8418 + }
8419 + return(rc);
8420 + }
8421 +
8422 +@endcode
8423 +
8424 +
8425 +@par Push Model Example (Currently Eswitch ONLY)
8426 +
8427 +@code
8428 +
8429 +typedef struct _os_device_s OS_DEVICE;
8430 +typedef struct _os_receive_s OS_RECEIVEINFO;
8431 +typedef struct _os_send_s OS_SENDINFO;
8432 +typedef struct _os_setup_s OS_SETUP;
8433 +
8434 +#include "cpswhal.h" //Get glogal HAL stuff
8435 +#include "cpswhaleswitch.h" //Get device specific hal stuff
8436 +
8437 +
8438 +typedef struct _os_device_s
8439 +{
8440 + HAL_DEVICE *HalDev;
8441 + HAL_FUNCTIONS *HalFunc;
8442 + OS_FUNCTIONS *OsFunc;
8443 + OS_SETUP *OsSetup;
8444 + bit32u Interrupt;
8445 + int (*halIsr)(HAL_DEVICE *HalDev, int*);
8446 + int ModulePort;
8447 + int Protocol;
8448 + int LinkStatus; // 0-> down, otherwise up
8449 +}os_device_s;
8450 +
8451 +typedef struct _os_receive_s
8452 +{
8453 + HAL_RECEIVEINFO *HalReceiveInfo;
8454 + char *ReceiveBuffer;
8455 + OS_DEVICE *OsDev;
8456 +}os_receive_s;
8457 +
8458 +typedef struct _os_send_s
8459 +{
8460 + OS_DEVICE *OsDev;
8461 +}os_send_s;
8462 +
8463 +typedef struct _os_setup_s
8464 +{
8465 + OS_DEVICE *OsDev;
8466 +}os_setup_s;
8467 +
8468 +
8469 +
8470 +void FlowForCphal(OS_DEVICE *OsDev)
8471 +{
8472 +CHANNEL_INFO ChannelInfo;
8473 + int nChannels = 200;
8474 + int halFuncSize;
8475 + int rc;
8476 +
8477 + // Populate OsFunc structure
8478 + rc = osInitModule(OsDev);
8479 +
8480 + if(rc)
8481 + {
8482 + sprintf(bufTmp, "%s: return code from osInitModule:'0x%08X'", __FUNCTION__, rc);
8483 + errorout(bufTmp);
8484 + }
8485 +
8486 +
8487 + // OS-Cphal handshake
8488 + rc = cpswHalEswitchInitModule(&OsDev->HalDev, OsDev, &OsDev->HalFunc, OsDev->OsFunc,
8489 + sizeof(OS_FUNCTIONS), &halFuncSize, OsDev->ModulePort);
8490 +
8491 + if(rc)
8492 + {
8493 + sprintf(bufTmp, "%s: return code from cpswHalEswitchInitModule:'0x%08X'", __FUNCTION__, rc);
8494 + errorout(bufTmp);
8495 + }
8496 +
8497 +
8498 + ChannelInfo.Channel = 7;
8499 + ChannelInfo.Direction = DIRECTION_RX;
8500 + ChanInfo.Receive = osReceiveSS; // Specify function to receive data for this channel
8501 +
8502 + rc = OsDev->HalFunc->ChannelSetup(OsDev->HalDev, &ChannelInfo, OsDev->OsSetup);
8503 +
8504 + MyConfig.debug=0;
8505 + MyConfig.CpuFrequency = CpuFreq;
8506 + MyConfig.EswitchFrequency = EswitchFreq;
8507 + MyConfig.ResetBase = 0xa8611600;
8508 + MyConfig.MacAddress = MacAddr;
8509 +
8510 + MyConfig.EswitchResetBit= 27;
8511 + MyConfig.Cpmac0ResetBit = 17;
8512 + MyConfig.Cpmac1ResetBit = 21;
8513 + MyConfig.MdioResetBit = 22;
8514 + MyConfig.Phy0ResetBit = 26;
8515 + MyConfig.Phy1ResetBit = 28;
8516 + MyConfig.HdmaResetBit = 13;
8517 + MyConfig.Cpmac0IntBit = 19;
8518 + MyConfig.Cpmac1IntBit = 33;
8519 + MyConfig.EswitchIntBit = 27;
8520 + MyConfig.EswitchBase = 0xa8640000;
8521 + MyConfig.EswitchBufferSize = 64;
8522 + MyConfig.EswitchHostBufCount = 0;
8523 + MyConfig.EswitchDefaultCamSize = 64;
8524 + MyConfig.EswitchOverFlowCount = 200;
8525 + MyConfig.EswitchOverFlowSize = 256;
8526 +
8527 +
8528 +
8529 +
8530 + rc=EswitchConfig(HalDev,HalFunc,&MyConfig);
8531 +
8532 +
8533 + // Open the hardware module
8534 + rc = OsDev->HalFunc->Open(OsDev->HalDev);
8535 +
8536 + // Module now ready to Send/Receive data
8537 +}
8538 +
8539 +
8540 +int EswitchConfig(HAL_DEVICE *HalDev, HAL_FUNCTIONS *HalFunc, ESWITCH_CONFIG *Config)
8541 +{
8542 + bit32u sts;
8543 + sts = 0;
8544 +
8545 + sts |= cpswhalPushBin(hcdebug, Config->debug);
8546 + sts |= cpswhalPushBin(hcCpuFrequency , Config->CpuFrequency );
8547 + sts |= cpswhalPushBin(hcEswitchFrequency , Config->EswitchFrequency );
8548 + sts |= cpswhalPushBin(hcResetBase , Config->ResetBase );
8549 + sts |= cpswhalPushBin(hcMacAddress , Config->MacAddress );
8550 + sts |= cpswhalPushBin(hcEswitchResetBit, Config->EswitchResetBit);
8551 + sts |= cpswhalPushBin(hcCpmac0ResetBit , Config->Cpmac0ResetBit );
8552 + sts |= cpswhalPushBin(hcCpmac1ResetBit , Config->Cpmac1ResetBit );
8553 + sts |= cpswhalPushBin(hcMdioResetBit , Config->MdioResetBit );
8554 + sts |= cpswhalPushBin(hcPhy0ResetBit , Config->Phy0ResetBit );
8555 + sts |= cpswhalPushBin(hcPhy1ResetBit , Config->Phy1ResetBit );
8556 + sts |= cpswhalPushBin(hcHdmaResetBit , Config->HdmaResetBit );
8557 + sts |= cpswhalPushBin(hcCpmac0IntBit , Config->Cpmac0IntBit );
8558 + sts |= cpswhalPushBin(hcCpmac1IntBit , Config->Cpmac1IntBit );
8559 + sts |= cpswhalPushBin(hcEswitchIntBit , Config->EswitchIntBit );
8560 + sts |= cpswhalPushBin(hcEswitchBase , Config->EswitchBase );
8561 + sts |= cpswhalPushBin(hcEswitchBufferSize , Config->EswitchBufferSize );
8562 + sts |= cpswhalPushBin(hcEswitchHostBufCount , Config->EswitchHostBufCount );
8563 + sts |= cpswhalPushBin(hcEswitchDefaultCamSize , Config->EswitchDefaultCamSize );
8564 + sts |= cpswhalPushBin(hcEswitchOverFlowCount , Config->EswitchOverFlowCount );
8565 + sts |= cpswhalPushBin(hcEswitchOverFlowSize , Config->EswitchOverFlowSize );
8566 + return(sts);
8567 +}
8568 +
8569 +
8570 +
8571 +@endcode
8572 +*/
8573 +
8574 +#endif
8575 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/ec_errors_cpmac.h linux-2.4.30/drivers/net/avalanche_cpmac/ec_errors_cpmac.h
8576 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/ec_errors_cpmac.h 1970-01-01 02:00:00.000000000 +0200
8577 +++ linux-2.4.30/drivers/net/avalanche_cpmac/ec_errors_cpmac.h 2005-04-15 05:10:41.000000000 +0200
8578 @@ -0,0 +1,118 @@
8579 +/***************************************************************************
8580 + Copyright(c) 2001, Texas Instruments Incorporated. All Rights Reserved.
8581 +
8582 + FILE: ec_errors.h
8583 +
8584 + DESCRIPTION:
8585 + This file contains definitions and function declarations for
8586 + error code support.
8587 +
8588 + HISTORY:
8589 + 14Dec00 MJH Added masking to EC_CLASS etc macros
8590 + 17Sep02 GSG Added HAL support (new class&devices)
8591 + 03Oct02 GSG Removed C++ style comments
8592 +***************************************************************************/
8593 +#ifndef _INC_EC_ERRORS
8594 +#define _INC_EC_ERRORS
8595 +
8596 +/*
8597 + 31 - CRITICAL
8598 + 30-28 - CLASS (ie. DIAG, KERNEL, FLASH, etc)
8599 + 27-24 - INSTANCE (ie. 1, 2, 3, etc )
8600 + 23-16 - DEVICE (ie. EMAC, IIC, etc)
8601 + 15-08 - FUNCTION (ie. RX, TX, INIT, etc)
8602 + 07-00 - ERROR CODE (ie. NO_BASE, FILE_NOT_FOUND, etc )
8603 +*/
8604 +
8605 +/*---------------------------------------------------------------------------
8606 + Useful defines for accessing fields within error code
8607 +---------------------------------------------------------------------------*/
8608 +#define CRITICAL_SHIFT 31
8609 +#define CLASS_SHIFT 28
8610 +#define INST_SHIFT 24
8611 +#define DEVICE_SHIFT 16
8612 +#define FUNCTION_SHIFT 8
8613 +#define ERROR_CODE_SHIFT 0
8614 +
8615 +#define CRITICAL_MASK 1
8616 +#define CLASS_MASK 0x07
8617 +#define DEVICE_MASK 0xFF
8618 +#define INST_MASK 0x0F
8619 +#define FUNCTION_MASK 0xFF
8620 +#define ERROR_CODE_MASK 0xFF
8621 +
8622 +#define EC_CLASS(val) ((val&CLASS_MASK) << CLASS_SHIFT)
8623 +#define EC_DEVICE(val) ((val&DEVICE_MASK) << DEVICE_SHIFT)
8624 +#define EC_INST(val) ((val&INST_MASK) << INST_SHIFT)
8625 +#define EC_FUNC(val) ((val&FUNCTION_MASK) << FUNCTION_SHIFT)
8626 +#define EC_ERR(val) ((val&ERROR_CODE_MASK) << ERROR_CODE_SHIFT)
8627 +
8628 +/*---------------------------------------------------------------------------
8629 + Operation classes
8630 +---------------------------------------------------------------------------*/
8631 +#define EC_HAL EC_CLASS(0)
8632 +#define EC_DIAG EC_CLASS(8)
8633 +
8634 +/*---------------------------------------------------------------------------
8635 + Device types
8636 +---------------------------------------------------------------------------*/
8637 +#define EC_DEV_EMAC EC_DEVICE(1)
8638 +#define EC_DEV_IIC EC_DEVICE(2)
8639 +#define EC_DEV_RESET EC_DEVICE(3)
8640 +#define EC_DEV_ATMSAR EC_DEVICE(4)
8641 +#define EC_DEV_MEM EC_DEVICE(5)
8642 +#define EC_DEV_DES EC_DEVICE(6)
8643 +#define EC_DEV_DMA EC_DEVICE(7)
8644 +#define EC_DEV_DSP EC_DEVICE(8)
8645 +#define EC_DEV_TMR EC_DEVICE(9)
8646 +#define EC_DEV_WDT EC_DEVICE(10)
8647 +#define EC_DEV_DCL EC_DEVICE(11)
8648 +#define EC_DEV_BBIF EC_DEVICE(12)
8649 +#define EC_DEV_PCI EC_DEVICE(13)
8650 +#define EC_DEV_XBUS EC_DEVICE(14)
8651 +#define EC_DEV_DSLIF EC_DEVICE(15)
8652 +#define EC_DEV_USB EC_DEVICE(16)
8653 +#define EC_DEV_CLKC EC_DEVICE(17)
8654 +#define EC_DEV_RAPTOR EC_DEVICE(18)
8655 +#define EC_DEV_DSPC EC_DEVICE(19)
8656 +#define EC_DEV_INTC EC_DEVICE(20)
8657 +#define EC_DEV_GPIO EC_DEVICE(21)
8658 +#define EC_DEV_BIST EC_DEVICE(22)
8659 +#define EC_DEV_HDLC EC_DEVICE(23)
8660 +#define EC_DEV_UART EC_DEVICE(24)
8661 +#define EC_DEV_VOIC EC_DEVICE(25)
8662 +/* 9.17.02 (new HAL modules) */
8663 +#define EC_DEV_CPSAR EC_DEVICE(0x1A)
8664 +#define EC_DEV_AAL5 EC_DEVICE(0x1B)
8665 +#define EC_DEV_AAL2 EC_DEVICE(0x1C)
8666 +#define EC_DEV_CPMAC EC_DEVICE(0x1D)
8667 +#define EC_DEV_VDMA EC_DEVICE(0x1E)
8668 +#define EC_DEV_VLYNQ EC_DEVICE(0x1F)
8669 +#define EC_DEV_CPPI EC_DEVICE(0x20)
8670 +#define EC_DEV_CPMDIO EC_DEVICE(0x21)
8671 +
8672 +/*---------------------------------------------------------------------------
8673 + Function types
8674 +---------------------------------------------------------------------------*/
8675 +#define EC_FUNC_READ_CONF EC_FUNC(1)
8676 +#define EC_FUNC_INIT EC_FUNC(2)
8677 +
8678 +/*---------------------------------------------------------------------------
8679 + Error codes
8680 +---------------------------------------------------------------------------*/
8681 +#define EC_CRITICAL (1<<CRITICAL_SHIFT)
8682 +#define EC_NO_ERRORS 0
8683 +#define EC_VAL_NO_BASE EC_ERR(1)
8684 +#define EC_VAL_NO_RESET_BIT EC_ERR(2)
8685 +#define EC_VAL_NO_RESET EC_ERR(3)
8686 +#define EC_VAL_BAD_BASE EC_ERR(4)
8687 +#define EC_VAL_MALLOCFAILED EC_ERR(5)
8688 +#define EC_VAL_NO_RESETBASE EC_ERR(6)
8689 +#define EC_DEVICE_NOT_FOUND EC_ERR(7)
8690 +
8691 +/*---------------------------------------------------------------------------
8692 + Function declarations
8693 +---------------------------------------------------------------------------*/
8694 +extern void ec_log_error( unsigned int );
8695 +
8696 +#endif /* _INC_EC_ERRORS */
8697 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/hcpmac.c linux-2.4.30/drivers/net/avalanche_cpmac/hcpmac.c
8698 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/hcpmac.c 1970-01-01 02:00:00.000000000 +0200
8699 +++ linux-2.4.30/drivers/net/avalanche_cpmac/hcpmac.c 2005-07-08 22:08:07.755958806 +0200
8700 @@ -0,0 +1,1878 @@
8701 +/******************************************************************************
8702 + * TNETDxxxx Software Support
8703 + * Copyright (c) 2002-2004 Texas Instruments Incorporated. All Rights Reserved.
8704 + *
8705 + * FILE:
8706 + *
8707 + * DESCRIPTION:
8708 + * This file contains the code for the HAL EMAC Bridge Test
8709 + *
8710 + * HISTORY:
8711 + * xxXxx01 Denis RC1.00 Original Version created.
8712 + * 22Jan02 Denis/Mick RC1.01 Modified for HAL EMAC API
8713 + * 24Jan02 Denis/Mick RC1.02 Speed Improvements
8714 + * 28Jan02 Denis/Mick RC1.16 Made function calls pointers
8715 + * 28Jan02 Mick RC1.18 Split into separate modules
8716 + * 29Jan02 Mick RC1.19 Hal include file cleaned up
8717 + * 15Jul02 Michael Hanrahan RC1.20 Synch'd with Linux Version
8718 + * 23Sep02 Michael Hanrahan RC1.21 Added CPPI.C
8719 + * 16Oct02 Michael Hanrahan RC1.22 Added CAF etc to Options.Conf
8720 + * 09Jan03 Michael Hanrahan RC3.01 Fixed incorrect MDIO check
8721 + * 01Feb03 Michael Hanrahan RC3.02 Updated for GPIO/PBUSFREQ
8722 + * 29Mar03 Michael Hanrahan 1.03 Corrected ChannelConfigGet
8723 + * 29Mar03 Michael Hanrahan 1.03 Removed user setting of TxNumQueues
8724 + * 23Aug04 Michael Hanrahan 1.7.8 Support for Setting Mac Address
8725 + * @author Michael Hanrahan
8726 + * @version 1.02
8727 + * @date 24-Jan-2002
8728 + *****************************************************************************/
8729 +#define _HAL_CPMAC
8730 +#define _CPHAL_CPMAC
8731 +#define _CPHAL
8732 +#define __CPHAL_CPMDIO
8733 +
8734 +#include "dox_cpmac.h" /* Documentation information */
8735 +
8736 +/* OS Data Structure definitions */
8737 +
8738 +typedef void OS_PRIVATE;
8739 +typedef void OS_DEVICE;
8740 +typedef void OS_SENDINFO;
8741 +typedef void OS_RECEIVEINFO;
8742 +typedef void OS_SETUP;
8743 +
8744 +/* HAL Data Structure definitions */
8745 +
8746 +typedef struct _phy_device PHY_DEVICE;
8747 +typedef struct hal_device HAL_DEVICE;
8748 +typedef struct hal_private HAL_PRIVATE;
8749 +typedef struct hal_private HAL_RECEIVEINFO;
8750 +
8751 +#include "cpcommon_cpmac.h"
8752 +#include "cpswhal_cpmac.h"
8753 +#include "cpmdio.h"
8754 +#include "hcpmac.h"
8755 +#include "cpmac_reg.h"
8756 +
8757 +
8758 +#define EC_MODULE
8759 +
8760 +/* MDIO Clock Frequency Default Value */
8761 +
8762 +/* Rcb/Tcb Constants */
8763 +
8764 +#define CB_SOF_BIT (1<<31)
8765 +#define CB_EOF_BIT (1<<30)
8766 +#define CB_SOF_AND_EOF_BIT (CB_SOF_BIT|CB_EOF_BIT)
8767 +#define CB_OWNERSHIP_BIT (1<<29)
8768 +#define CB_EOQ_BIT (1<<28)
8769 +#define CB_SIZE_MASK 0x0000ffff
8770 +#define RCB_ERRORS_MASK 0x03fe0000
8771 +
8772 +static char *channel_names[] = CHANNEL_NAMES; /* GSG 11/22 (may change this implementation) */
8773 +
8774 +#define scFound(Module) if (HalDev->State != enDevFound) return (Module|EC_FUNC_CHSETUP|EC_VAL_INVALID_STATE)
8775 +#define scInit(Module) if (HalDev->State < enInitialized) return (Module|EC_FUNC_CHSETUP|EC_VAL_INVALID_STATE)
8776 +#define scOpen(Module) if (HalDev->State < enOpened) return (Module|EC_FUNC_CHSETUP|EC_VAL_INVALID_STATE)
8777 +
8778 +
8779 +
8780 +/********************************************************************
8781 +**
8782 +** L O C A L F U N C T I O N S
8783 +**
8784 +********************************************************************/
8785 +static int halIsr(HAL_DEVICE *HalDev, int *MorePackets);
8786 +static int cpmacRandom(HAL_DEVICE *HalDev);
8787 +static int cpmacRandomRange(HAL_DEVICE *HalDev, int min, int max);
8788 +static int halPacketProcessEnd(HAL_DEVICE *HalDev);
8789 +
8790 +#include "cpcommon_cpmac.c" /*~RC3.02*/
8791 +#include "cppi_cpmac.c"
8792 +#include "cpmdio.c" /*~RC3.02*/
8793 +
8794 +static int MacAddressSave(HAL_DEVICE *HalDev, unsigned char *MacAddr)
8795 + {
8796 + int i;
8797 + int inst = HalDev->inst;
8798 +
8799 + HalDev->MacAddr = MacAddr;
8800 +
8801 + if(HalDev->debug)
8802 + {
8803 + dbgPrintf("MacAddrSave[%d]: ", inst);
8804 + for (i=0;i<6;i++)
8805 + dbgPrintf("%X", HalDev->MacAddr[i]);
8806 + dbgPrintf("\n");
8807 + osfuncSioFlush();
8808 + }
8809 + return(EC_NO_ERRORS);
8810 + }
8811 +static int MacAddressSet(HAL_DEVICE *HalDev)
8812 + {
8813 + unsigned char *macadr = &HalDev->MacAddr[0];
8814 + int base = HalDev->dev_base;
8815 +
8816 + scOpen(EC_CPMAC);
8817 + CPMAC_MACADDRLO_0(base) = macadr[5];
8818 + CPMAC_MACADDRMID(base) = macadr[4];
8819 + CPMAC_MACADDRHI(base) = (macadr[0])|(macadr[1]<<8)|(macadr[2]<<16)|(macadr[3]<<24);
8820 + if(HalDev->debug)
8821 + {
8822 + dbgPrintf("MacAddrSet: MacAddr(%d) %X %X %X\n", HalDev->inst, CPMAC_MACADDRLO_0(base),
8823 + CPMAC_MACADDRMID(base),
8824 + CPMAC_MACADDRHI(base));
8825 +
8826 + dbgPrintf("Start MAC: %d\n",HalDev->dev_base);
8827 + osfuncSioFlush();
8828 + }
8829 + return(EC_NO_ERRORS);
8830 + }
8831 +
8832 +
8833 +/*
8834 + Updates the MacHash registers
8835 +*/
8836 +static void MacHashSet(HAL_DEVICE *HalDev)
8837 + {
8838 + if(HalDev->State < enOpened)
8839 + return;
8840 +
8841 + CPMAC_MACHASH1(HalDev->dev_base) = HalDev->MacHash1;
8842 + CPMAC_MACHASH2(HalDev->dev_base) = HalDev->MacHash2;
8843 + if (DBG(11))
8844 + dbgPrintf("CPMAC[%X]: MacHash1 0x%08X, MacHash2 0x%08X\n", HalDev->dev_base, CPMAC_MACHASH1(HalDev->dev_base), CPMAC_MACHASH2(HalDev->dev_base));
8845 + }
8846 +
8847 +/*
8848 + Reads the MacControl register and updates
8849 + the changable bits. (See MACCONTROL_MASK)
8850 +*/
8851 +static void RxMBP_EnableSet(HAL_DEVICE *HalDev)
8852 + {
8853 + bit32u RxMbpEnable;
8854 + if(HalDev->State < enOpened)
8855 + return;
8856 + RxMbpEnable = CPMAC_RX_MBP_ENABLE(HalDev->dev_base);
8857 + RxMbpEnable &= ~RX_MBP_ENABLE_MASK; /* Clear out updatable bits */
8858 + RxMbpEnable |= HalDev->RxMbpEnable;
8859 + CPMAC_RX_MBP_ENABLE(HalDev->dev_base) = RxMbpEnable;
8860 + }
8861 +/*
8862 + Reads the MacControl register and updates
8863 + the changable bits. (See MACCONTROL_MASK)
8864 +*/
8865 +static void MacControlSet(HAL_DEVICE *HalDev)
8866 + {
8867 + bit32u MacControl;
8868 + if(HalDev->State < enOpened)
8869 + return;
8870 + MacControl = CPMAC_MACCONTROL(HalDev->dev_base);
8871 + MacControl &= ~MACCONTROL_MASK; /* Clear out updatable bits */
8872 + MacControl |= HalDev->MacControl;
8873 + if(!(MacControl & MII_EN)) /* If Enable is not set just update register */
8874 + CPMAC_MACCONTROL(HalDev->dev_base) = MacControl;
8875 + else
8876 + {
8877 + if(MacControl & CTRL_LOOPBACK) /* Loopback Set */
8878 + {
8879 + /* mii_en is set and loopback is needed,
8880 + clear mii_en, set loopback, then set mii_en
8881 + */
8882 + MacControl &= ~MII_EN; /* Clear MII_EN */
8883 + CPMAC_MACCONTROL(HalDev->dev_base) = MacControl;
8884 + CPMAC_MACCONTROL(HalDev->dev_base) |= MII_EN; /* Set MII_EN */
8885 + HalDev->Linked = 1; /* if in loopback the logically linked */
8886 + }
8887 + else /* If Loopback not set just update */
8888 + {
8889 + CPMAC_MACCONTROL(HalDev->dev_base) = MacControl;
8890 + }
8891 + }
8892 + if(DBG(0))
8893 + dbgPrintf("[halMacControlSet]MacControl:%08X\n", CPMAC_MACCONTROL(HalDev->dev_base));
8894 + }
8895 +static int UnicastSet(HAL_DEVICE *HalDev)
8896 + {
8897 + CPMAC_RX_UNICAST_SET(HalDev->dev_base) = HalDev->RxUnicastSet;
8898 + CPMAC_RX_UNICAST_CLEAR(HalDev->dev_base) = HalDev->RxUnicastClear;
8899 + return(EC_NO_ERRORS);
8900 + }
8901 +
8902 +
8903 +static bit32u HashGet(bit8u *Address)
8904 + {
8905 + bit32u hash;
8906 + bit8u tmpval;
8907 + int i;
8908 +
8909 + hash = 0;
8910 + for( i=0; i<2; i++ )
8911 + {
8912 + tmpval = *Address++;
8913 + hash ^= (tmpval>>2)^(tmpval<<4);
8914 + tmpval = *Address++;
8915 + hash ^= (tmpval>>4)^(tmpval<<2);
8916 + tmpval = *Address++;
8917 + hash ^= (tmpval>>6)^(tmpval);
8918 + }
8919 +
8920 + return( hash & 0x3F );
8921 + }
8922 +
8923 +static void HashAdd(HAL_DEVICE *HalDev, bit8u *MacAddress)
8924 +{
8925 + bit32u HashValue;
8926 + bit32u HashBit;
8927 +
8928 + HashValue = HashGet(MacAddress);
8929 +
8930 + if(HashValue < 32)
8931 + {
8932 + HashBit = (1 << HashValue);
8933 + HalDev->MacHash1 |= HashBit;
8934 + }
8935 + else
8936 + {
8937 + HashBit = (1 << (HashValue-32));
8938 + HalDev->MacHash2 |= HashBit;
8939 + }
8940 +}
8941 +
8942 +static void HashDel(HAL_DEVICE *HalDev, bit8u *MacAddress)
8943 +{
8944 + bit32u HashValue;
8945 + bit32u HashBit;
8946 +
8947 + HashValue = HashGet(MacAddress);
8948 +
8949 + if(HashValue < 32)
8950 + {
8951 + HashBit = (1 << HashValue);
8952 + HalDev->MacHash1 &= ~HashBit;
8953 + }
8954 + else
8955 + {
8956 + HashBit = (1 << (HashValue-32));
8957 + HalDev->MacHash2 &= ~HashBit;
8958 + }
8959 +}
8960 +
8961 +/* Replace with an array based on key, with a ptr to the code to do */
8962 +/* e.g. [enRX_PASS_CRC] = {Set, MBP_UPDATE() } */
8963 +static void DuplexUpdate(HAL_DEVICE *HalDev)
8964 +{
8965 + int base = HalDev->dev_base;
8966 + PHY_DEVICE *PhyDev = HalDev->PhyDev;
8967 +
8968 + if(HalDev->State < enOpened)
8969 + return;
8970 +
8971 + /* No Phy Condition */
8972 + if(HalDev->MdioConnect & _CPMDIO_NOPHY) /*MJH+030805*/
8973 + {
8974 + /* No Phy condition, always linked */
8975 + HalDev->Linked = 1;
8976 + HalDev->EmacSpeed = 1;
8977 + HalDev->EmacDuplex = 1;
8978 + HalDev->PhyNum = 0xFFFFFFFF; /* No Phy Num */
8979 + CPMAC_MACCONTROL(base) |= FULLDUPLEX; /*MJH+030909*/
8980 + osfuncStateChange();
8981 + return;
8982 + }
8983 +
8984 + if(HalDev->MacControl & CTRL_LOOPBACK) /* Loopback Set */
8985 + {
8986 + HalDev->Linked = 1;
8987 + return;
8988 + }
8989 +
8990 + if (HalDev->MdioConnect & _CPMDIO_LOOPBK)
8991 + {
8992 + HalDev->Linked = cpMacMdioGetLoopback(HalDev->PhyDev);
8993 + }
8994 + else
8995 + {
8996 + HalDev->Linked = cpMacMdioGetLinked(HalDev->PhyDev);
8997 + }
8998 + if (HalDev->Linked)
8999 + {
9000 + /* Retreive Duplex and Speed and the Phy Number */
9001 + if(HalDev->MdioConnect & _CPMDIO_LOOPBK)
9002 + HalDev->EmacDuplex = 1;
9003 + else
9004 + HalDev->EmacDuplex = cpMacMdioGetDuplex(PhyDev);
9005 + HalDev->EmacSpeed = cpMacMdioGetSpeed(PhyDev);
9006 + HalDev->PhyNum = cpMacMdioGetPhyNum(PhyDev);
9007 +
9008 + if(HalDev->EmacDuplex)
9009 + CPMAC_MACCONTROL(base) |= FULLDUPLEX;
9010 + else
9011 + CPMAC_MACCONTROL(base) &= ~FULLDUPLEX;
9012 + if(HalDev->debug)
9013 + dbgPrintf("%d: Phy= %d, Speed=%s, Duplex=%s\n",HalDev->inst,HalDev->PhyNum,(HalDev->EmacSpeed)?"100":"10",(HalDev->EmacDuplex)?"Full":"Half");
9014 + }
9015 + if(HalDev->debug)
9016 + dbgPrintf("DuplexUpdate[%d]: MACCONTROL 0x%08X, %s\n", HalDev->inst, CPMAC_MACCONTROL(base),(HalDev->Linked)?"Linked":"Not Linked");
9017 +}
9018 +static void MdioSetPhyMode(HAL_DEVICE *HalDev)
9019 + {
9020 + unsigned int PhyMode;
9021 + /* Verify proper device state */
9022 + if (HalDev->State < enOpened)
9023 + return;
9024 +
9025 + PhyMode = NWAY_AUTO|NWAY_FD100|NWAY_HD100|NWAY_FD10|NWAY_HD10;
9026 + if(DBG(0))
9027 + {
9028 + dbgPrintf("halSetPhyMode1: MdioConnect:%08X ,", HalDev->MdioConnect);
9029 + dbgPrintf("PhyMode:%08X Auto:%d, FD10:%d, HD10:%d, FD100:%d, HD100:%d\n", PhyMode,
9030 + PhyMode&NWAY_AUTO, PhyMode&NWAY_FD10, PhyMode&NWAY_HD10, PhyMode&NWAY_FD100,
9031 + PhyMode&NWAY_HD100);
9032 + }
9033 +
9034 +
9035 + if ( HalDev->MdioConnect & _CPMDIO_NEG_OFF) /* ~RC3.01 */
9036 + PhyMode &= ~(NWAY_AUTO); /* Disable Auto Neg */
9037 + if (!(HalDev->MdioConnect & _CPMDIO_HD))
9038 + PhyMode &= ~(NWAY_HD100|NWAY_HD10); /* Cannot support HD */
9039 + if (!(HalDev->MdioConnect & _CPMDIO_FD))
9040 + PhyMode &= ~(NWAY_FD100|NWAY_FD10); /* Cannot support FD */
9041 + if (!(HalDev->MdioConnect & _CPMDIO_10))
9042 + PhyMode &= ~(NWAY_HD10|NWAY_FD10); /* Cannot support 10 Mbs */
9043 + if (!(HalDev->MdioConnect & _CPMDIO_100))
9044 + PhyMode &= ~(NWAY_HD100|NWAY_FD100); /* Cannot support 100 Mbs */
9045 +
9046 + if(HalDev->MdioConnect & _CPMDIO_AUTOMDIX) PhyMode |= NWAY_AUTOMDIX; /* Set AutoMdix */
9047 +
9048 + if (HalDev->CpmacFrequency <= 50000000)
9049 + PhyMode &= ~(NWAY_FD100|NWAY_HD100); /* Cannot support 100 MBS */
9050 + if(DBG(7))
9051 + dbgPrintf("halNeg: PhyMode[0x%08X] %d\n", HalDev->dev_base, PhyMode);
9052 +
9053 + if(DBG(0))
9054 + {
9055 + dbgPrintf("halSetPhyMode2: MdioConnect:%08X ,", HalDev->MdioConnect);
9056 + dbgPrintf("PhyMode:%08X Auto:%d, FD10:%d, HD10:%d, FD100:%d, HD100:%d\n", PhyMode,
9057 + PhyMode&NWAY_AUTO, PhyMode&NWAY_FD10, PhyMode&NWAY_HD10, PhyMode&NWAY_FD100,
9058 + PhyMode&NWAY_HD100);
9059 + }
9060 +
9061 +
9062 + cpMacMdioSetPhyMode(HalDev->PhyDev,PhyMode);
9063 + DuplexUpdate(HalDev);
9064 + }
9065 +static int StatsClear(HAL_DEVICE *HalDev)
9066 +{
9067 + int i;
9068 + MEM_PTR pStats;
9069 +
9070 + scOpen(EC_CPMAC);
9071 +
9072 + pStats = pCPMAC_RXGOODFRAMES(HalDev->dev_base);
9073 + for (i=0;i<STATS_MAX;i++)
9074 + {
9075 + *(MEM_PTR)(pStats) = 0xFFFFFFFF;
9076 + pStats++;
9077 + }
9078 +
9079 + return(EC_NO_ERRORS);
9080 +}
9081 +static void StatsDump(HAL_DEVICE *HalDev, void *Value)
9082 + {
9083 + MEM_PTR ptrStats;
9084 + MEM_PTR ptrValue;
9085 + int i;
9086 + ptrStats = pCPMAC_RXGOODFRAMES(HalDev->dev_base);
9087 + ptrValue = (bit32u*) Value;
9088 + for (i=0; i<STATS_MAX; i++)
9089 + {
9090 + *ptrValue = *ptrStats;
9091 + if(DBG(4))
9092 + {
9093 + dbgPrintf("halStatsDump: Stat[%d:0x%08X] %d 0x%08X %d\n", i, ptrStats, *ptrStats, ptrValue, *ptrValue);
9094 + osfuncSioFlush();
9095 + }
9096 + ptrStats++;
9097 + ptrValue++;
9098 + }
9099 + }
9100 +static void ConfigApply(HAL_DEVICE *HalDev)
9101 + {
9102 + CPMAC_RX_MAXLEN(HalDev->dev_base) = HalDev->RxMaxLen;
9103 + CPMAC_RX_FILTERLOWTHRESH(HalDev->dev_base) = HalDev->RxFilterLowThresh;
9104 + CPMAC_RX0_FLOWTHRESH(HalDev->dev_base) = HalDev->Rx0FlowThresh;
9105 + UnicastSet(HalDev);
9106 + MacAddressSet(HalDev);
9107 + RxMBP_EnableSet(HalDev);
9108 + MacHashSet(HalDev);
9109 + MacControlSet(HalDev);
9110 + if(DBG(0))
9111 + dbgPrintf("ValuesUpdate[%d]: MBP_ENABLE 0x%08X\n", HalDev->inst, CPMAC_RX_MBP_ENABLE(HalDev->dev_base));
9112 + }
9113 +static int halStatus(HAL_DEVICE *HalDev)
9114 +{
9115 + int status;
9116 +
9117 + if(HalDev->State < enOpened)
9118 + return (EC_CPMAC|EC_FUNC_STATUS|EC_VAL_INVALID_STATE); /*MJH+030805*/
9119 +
9120 + /* No Phy Condition */
9121 + if(HalDev->MdioConnect & _CPMDIO_NOPHY) /*MJH+030805*/
9122 + {
9123 + /* No Phy condition, always linked */
9124 + status = HalDev->Linked;
9125 + status |= CPMAC_STATUS_LINK_DUPLEX;
9126 + status |= CPMAC_STATUS_LINK_SPEED;
9127 + return(status);
9128 + }
9129 +
9130 +
9131 + if (HalDev->HostErr) /* Adapter Check */
9132 + {
9133 + bit32u tmp;
9134 + status = CPMAC_STATUS_ADAPTER_CHECK;
9135 + if(HalDev->MacStatus & RX_HOST_ERR_CODE)
9136 + {
9137 + status |= CPMAC_STATUS_HOST_ERR_DIRECTION;
9138 + tmp = (HalDev->MacStatus & RX_HOST_ERR_CODE) >> 12; /* Code */
9139 + status |= (tmp << 9); /* Code */
9140 + tmp = (HalDev->MacStatus & RX_ERR_CH) >> 8; /* Channel */
9141 + status |= (tmp << 13);
9142 + }
9143 + else
9144 + if(HalDev->MacStatus & TX_HOST_ERR_CODE)
9145 + {
9146 + status |= CPMAC_STATUS_HOST_ERR_DIRECTION;
9147 + tmp = (HalDev->MacStatus & TX_HOST_ERR_CODE) >> 20; /* Code */
9148 + status |= (tmp << 9); /* Code */
9149 + tmp = (HalDev->MacStatus & TX_ERR_CH) >> 16; /* Channel */
9150 + status |= (tmp << 13);
9151 + }
9152 + }
9153 + else
9154 + {
9155 + status = HalDev->Linked;
9156 + if(status)
9157 + {
9158 + status = CPMAC_STATUS_LINK;
9159 + if(cpMacMdioGetDuplex(HalDev->PhyDev))
9160 + status |= CPMAC_STATUS_LINK_DUPLEX;
9161 + if(cpMacMdioGetSpeed(HalDev->PhyDev))
9162 + status |= CPMAC_STATUS_LINK_SPEED;
9163 + }
9164 + }
9165 + if(HalDev->debug)
9166 + dbgPrintf("[halStatus] Link Status is %d for 0x%X\n", status, HalDev->dev_base);
9167 + return(status);
9168 +}
9169 +static int InfoAccess(HAL_DEVICE *HalDev, int Key, int Action, void *ParmValue)
9170 + {
9171 + int rc = 0;
9172 + int Update=0;
9173 +
9174 + switch (Key)
9175 + {
9176 + /********************************************************************/
9177 + /* */
9178 + /* GENERAL */
9179 + /* */
9180 + /********************************************************************/
9181 +
9182 + case enVersion :
9183 + if(Action==enGET)
9184 + {
9185 + *(const char **)ParmValue = pszVersion_CPMAC;
9186 + }
9187 + break;
9188 + case enDebug :
9189 + if(Action==enSET)
9190 + {
9191 + HalDev->debug = *(unsigned int *)ParmValue;
9192 + }
9193 + break;
9194 +
9195 + case enStatus :
9196 + if(Action==enGET)
9197 + {
9198 + int status;
9199 + status = halStatus(HalDev);
9200 + *(int *)ParmValue = status;
9201 + }
9202 + break;
9203 + /********************************************************************/
9204 + /* */
9205 + /* RX_MBP_ENABLE */
9206 + /* */
9207 + /********************************************************************/
9208 +
9209 + case enRX_PASS_CRC :
9210 + if(Action==enSET)
9211 + {
9212 + UPDATE_RX_PASS_CRC(*(unsigned int *)ParmValue);
9213 + Update=1;
9214 + }
9215 + break;
9216 + case enRX_QOS_EN :
9217 + if(Action==enSET)
9218 + {
9219 + UPDATE_RX_QOS_EN(*(unsigned int *)ParmValue);
9220 + Update=1;
9221 + }
9222 + break;
9223 + case enRX_NO_CHAIN :
9224 + if(Action==enSET)
9225 + {
9226 + UPDATE_RX_NO_CHAIN(*(unsigned int *)ParmValue);
9227 + Update=1;
9228 + }
9229 + break;
9230 + case enRX_CMF_EN :
9231 + if(Action==enSET)
9232 + {
9233 + UPDATE_RX_CMF_EN(*(unsigned int *)ParmValue);
9234 + Update=1;
9235 + }
9236 + break;
9237 + case enRX_CSF_EN :
9238 + if(Action==enSET)
9239 + {
9240 + UPDATE_RX_CSF_EN(*(unsigned int *)ParmValue);
9241 + Update=1;
9242 + }
9243 + break;
9244 + case enRX_CEF_EN :
9245 + if(Action==enSET)
9246 + {
9247 + UPDATE_RX_CEF_EN(*(unsigned int *)ParmValue);
9248 + Update=1;
9249 + }
9250 + break;
9251 + case enRX_CAF_EN :
9252 + if(Action==enSET)
9253 + {
9254 + UPDATE_RX_CAF_EN(*(unsigned int *)ParmValue);
9255 + Update=1;
9256 + }
9257 + break;
9258 + case enRX_PROM_CH :
9259 + if(Action==enSET)
9260 + {
9261 + UPDATE_RX_PROM_CH(*(unsigned int *)ParmValue);
9262 + Update=1;
9263 + }
9264 + break;
9265 + case enRX_BROAD_EN :
9266 + if(Action==enSET)
9267 + {
9268 + UPDATE_RX_BROAD_EN(*(unsigned int *)ParmValue);
9269 + Update=1;
9270 + }
9271 + break;
9272 + case enRX_BROAD_CH :
9273 + if(Action==enSET)
9274 + {
9275 + UPDATE_RX_BROAD_CH(*(unsigned int *)ParmValue);
9276 + Update=1;
9277 + }
9278 + break;
9279 + case enRX_MULT_EN :
9280 + if(Action==enSET)
9281 + {
9282 + UPDATE_RX_MULT_EN(*(unsigned int *)ParmValue);
9283 + Update=1;
9284 + }
9285 + break;
9286 + case enRX_MULT_CH :
9287 + if(Action==enSET)
9288 + {
9289 + UPDATE_RX_MULT_CH(*(unsigned int *)ParmValue);
9290 + Update=1;
9291 + }
9292 + break;
9293 +
9294 + /********************************************************************/
9295 + /* */
9296 + /* MAC_CONTROL */
9297 + /* */
9298 + /********************************************************************/
9299 +
9300 + case enTX_PTYPE :
9301 + if(Action==enSET)
9302 + {
9303 + UPDATE_TX_PTYPE(*(unsigned int *)ParmValue);
9304 + Update=1;
9305 + }
9306 + break;
9307 + case enTX_PACE :
9308 + if(Action==enSET)
9309 + {
9310 + UPDATE_TX_PACE(*(unsigned int *)ParmValue);
9311 + Update=1;
9312 + }
9313 + break;
9314 + case enTX_FLOW_EN :
9315 + if(Action==enSET)
9316 + {
9317 + UPDATE_TX_FLOW_EN(*(unsigned int *)ParmValue);
9318 + Update=1;
9319 + }
9320 + break;
9321 + case enRX_FLOW_EN :
9322 + if(Action==enSET)
9323 + {
9324 + UPDATE_RX_FLOW_EN(*(unsigned int *)ParmValue);
9325 + Update=1;
9326 + }
9327 + break;
9328 +
9329 + case enCTRL_LOOPBACK :
9330 + if(Action==enSET)
9331 + {
9332 + UPDATE_CTRL_LOOPBACK(*(unsigned int *)ParmValue);
9333 + Update=1;
9334 + }
9335 + break;
9336 + /********************************************************************/
9337 + /* */
9338 + /* RX_UNICAST_SET */
9339 + /* */
9340 + /********************************************************************/
9341 +
9342 + case enRX_UNICAST_SET :
9343 + if(Action==enSET)
9344 + {
9345 + HalDev->RxUnicastSet |= (1 << *(unsigned int *)ParmValue);
9346 + HalDev->RxUnicastClear &= ~(1 << *(unsigned int *)ParmValue);
9347 + Update=1;
9348 + }
9349 + break;
9350 + case enRX_UNICAST_CLEAR :
9351 + if(Action==enSET)
9352 + {
9353 + HalDev->RxUnicastClear |= (1 << *(unsigned int *)ParmValue);
9354 + HalDev->RxUnicastSet &= ~(1 << *(unsigned int *)ParmValue);
9355 + Update=1;
9356 + }
9357 + break;
9358 +
9359 + case enRX_MAXLEN :
9360 + if(Action==enSET)
9361 + {
9362 + HalDev->RxMaxLen = *(unsigned int *)ParmValue;
9363 + Update=1;
9364 + }
9365 + break;
9366 +
9367 + case enRX_FILTERLOWTHRESH :
9368 + if(Action==enSET)
9369 + {
9370 + HalDev->RxFilterLowThresh = *(unsigned int *)ParmValue;
9371 + Update=1;
9372 + }
9373 + break;
9374 + case enRX0_FLOWTHRESH :
9375 + if(Action==enSET)
9376 + {
9377 + HalDev->Rx0FlowThresh = *(unsigned int *)ParmValue;
9378 + Update=1;
9379 + }
9380 + break;
9381 + /********************************************************************/
9382 + /* */
9383 + /* RX_MULTICAST */
9384 + /* */
9385 + /********************************************************************/
9386 +
9387 + case enRX_MULTICAST :
9388 + break;
9389 + case enRX_MULTI_SINGLE :
9390 + if(DBG(11))
9391 + {
9392 + int tmpi;
9393 + bit8u *MacAddress;
9394 + MacAddress = (bit8u *) ParmValue;
9395 + dbgPrintf("CPMAC[%X]: MacAddress '", HalDev->dev_base);
9396 + for (tmpi=0; tmpi<6; tmpi++)
9397 + dbgPrintf("%02X:", MacAddress[tmpi]);
9398 + dbgPrintf("\n");
9399 + }
9400 + if(Action==enCLEAR)
9401 + {
9402 + HashDel(HalDev, ParmValue);
9403 + Update=1;
9404 + }
9405 + else
9406 + if(Action==enSET)
9407 + {
9408 + HashAdd(HalDev, ParmValue);
9409 + Update=1;
9410 + }
9411 + break;
9412 + case enRX_MULTI_ALL :
9413 + if(Action==enCLEAR)
9414 + {
9415 + HalDev->MacHash1 = 0;
9416 + HalDev->MacHash2 = 0;
9417 + Update=1;
9418 + }
9419 + else
9420 + if(Action==enSET)
9421 + {
9422 + HalDev->MacHash1 = 0xFFFFFFFF;
9423 + HalDev->MacHash2 = 0xFFFFFFFF;
9424 + Update=1;
9425 + }
9426 + break;
9427 +
9428 + /********************************************************************/
9429 + /* */
9430 + /* MDIO */
9431 + /* */
9432 + /********************************************************************/
9433 +
9434 + case enMdioConnect :
9435 + if(Action==enSET)
9436 + {
9437 + HalDev->MdioConnect = *(unsigned int *)ParmValue;
9438 + MdioSetPhyMode(HalDev);
9439 + }
9440 + if(Action==enGET)
9441 + {
9442 + *(unsigned int *)ParmValue = HalDev->MdioConnect;
9443 + }
9444 + break;
9445 +
9446 +
9447 + /********************************************************************/
9448 + /* */
9449 + /* STATISTICS */
9450 + /* */
9451 + /********************************************************************/
9452 + case enStatsClear :
9453 + StatsClear(HalDev);
9454 + break;
9455 + case enStatsDump :
9456 + if(Action==enGET)
9457 + {
9458 + StatsDump(HalDev, ParmValue);
9459 + }
9460 + break;
9461 +
9462 +/* Not implemented
9463 + case enStats1 :
9464 + if(Action==enGET)
9465 + {
9466 + StatsGet(HalDev, ParmValue, 1);
9467 + }
9468 + break;
9469 +
9470 + case enStats2 :
9471 + if(Action==enGET)
9472 + {
9473 + StatsGet(HalDev, ParmValue, 2);
9474 + }
9475 + break;
9476 + case enStats3 :
9477 + if(Action==enGET)
9478 + {
9479 + StatsGet(HalDev, ParmValue, 3);
9480 + }
9481 + break;
9482 + case enStats4 :
9483 + if(Action==enGET)
9484 + {
9485 + StatsGet(HalDev, ParmValue, 4);
9486 + }
9487 + break;
9488 +
9489 +*/
9490 +
9491 + default:
9492 + rc = EC_CPMAC|EC_FUNC_OPTIONS|EC_VAL_KEY_NOT_FOUND;
9493 + break;
9494 + }
9495 +
9496 + /* Verify proper device state */
9497 + if (HalDev->State == enOpened)
9498 + switch (Update)
9499 + {
9500 + case 1 :
9501 + ConfigApply(HalDev);
9502 + break;
9503 + default:
9504 + break;
9505 + }
9506 +
9507 + return (rc);
9508 + }
9509 +static const char pszStats[] = "Stats;";
9510 +
9511 +static int halControl(HAL_DEVICE *HalDev, const char *pszKey, const char *pszAction, void *Value)
9512 + {
9513 + int i;
9514 + int rc=0;
9515 + int Action;
9516 + int ActionFound;
9517 + int KeyFound;
9518 +
9519 +#ifdef __CPHAL_DEBUG
9520 + if (DBG(1))
9521 + {
9522 + dbgPrintf("\nhalControl-HalDev:%08X,Action:%s,Key:%s\n", (bit32u)HalDev, pszAction, pszKey);
9523 + }
9524 +#endif
9525 +
9526 + /* 23Aug04 - BCIL needs to set Mac Address */
9527 + if(HalDev->OsFunc->Strcmpi(pszKey, pszMacAddr) == 0)
9528 + {
9529 + KeyFound=1;
9530 + if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
9531 + {
9532 + unsigned char *MacAddr;
9533 + MacAddr = (unsigned char *) Value;
9534 + MacAddressSave(HalDev, MacAddr);
9535 + MacAddressSet(HalDev);
9536 + return(0);
9537 + }
9538 + else
9539 + {
9540 + return(-1);
9541 + }
9542 + }
9543 +
9544 + if(HalDev->OsFunc->Strcmpi(pszKey, hcLinked) == 0)
9545 + {
9546 + KeyFound=1;
9547 + if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
9548 + {
9549 + HalDev->Linked = *(int *)Value;
9550 + return(0);
9551 + }
9552 + else
9553 + {
9554 + return(-1);
9555 + }
9556 + }
9557 +
9558 + if(HalDev->OsFunc->Strcmpi(pszKey, "TxIntDisable") == 0)
9559 + {
9560 + KeyFound=1;
9561 + if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
9562 + {
9563 + HalDev->TxIntDisable = *(int *)Value;
9564 + if(HalDev->TxIntDisable && (HalDev->State == enOpened))
9565 + {
9566 + /* if Opened and need TxIntDisabled, clear Ints for Channel 0 */
9567 + CPMAC_TX_INTMASK_CLEAR(HalDev->dev_base) = 1;
9568 + }
9569 + return(0);
9570 + }
9571 + else
9572 + {
9573 + return(-1);
9574 + }
9575 + }
9576 +
9577 + if(HalDev->OsFunc->Strcmpi(pszKey, hcPhyAccess) == 0)
9578 + {
9579 + bit32u RegAddr;
9580 + bit32u PhyNum;
9581 + bit32u Data;
9582 + bit32u ValueIn;
9583 +
9584 + ValueIn = *(bit32u*) Value;
9585 +
9586 + KeyFound=1;
9587 + /* Cannot access MII if not opended */
9588 +
9589 + if(HalDev->State < enOpened)
9590 + return(-1);
9591 +
9592 + if(HalDev->OsFunc->Strcmpi(pszAction, hcGet) == 0)
9593 + {
9594 +
9595 + PhyNum = (ValueIn & 0x1F); /* Phynum 0-32 */
9596 + RegAddr = (ValueIn >> 5) & 0xFF; /* RegAddr in upper 11 bits */
9597 +
9598 + *(bit32u*)Value = _mdioUserAccessRead(HalDev->PhyDev, RegAddr, PhyNum);
9599 +
9600 + return(0);
9601 + } /* end of hcGet */
9602 +
9603 +
9604 + if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
9605 + {
9606 + PhyNum = (ValueIn & 0x1F); /* Phynum 0-32 */
9607 + RegAddr = (ValueIn >> 5) & 0xFF; /* RegAddr in upper 11 bits of lower 16 */
9608 +
9609 + Data = ValueIn >> 16; /* Data store in upper 16 bits */
9610 +
9611 + _mdioUserAccessWrite(HalDev->PhyDev, RegAddr, PhyNum, Data);
9612 + return(0);
9613 + }
9614 + } /* End of hcPhyAccess */
9615 +
9616 + if(HalDev->OsFunc->Strcmpi(pszKey, hcPhyNum) == 0)
9617 + {
9618 + KeyFound=1;
9619 + if(!HalDev->Linked)
9620 + return(-1); /* if not linked the no Phy Connected */
9621 + if(HalDev->OsFunc->Strcmpi(pszAction, hcGet) == 0)
9622 + {
9623 + *(int *)Value = HalDev->PhyNum;
9624 + return(0);
9625 + }
9626 + }
9627 +
9628 + if(HalDev->OsFunc->Strcmpi(pszKey, hcCpmacSize) == 0)
9629 + {
9630 + KeyFound=1;
9631 + if(HalDev->OsFunc->Strcmpi(pszAction, hcGet) == 0)
9632 + {
9633 + *(bit32u *)Value = HalDev->CpmacSize;
9634 + return(0);
9635 + }
9636 + }
9637 +
9638 + if(HalDev->OsFunc->Strcmpi(pszKey, hcCpmacBase) == 0)
9639 + {
9640 + KeyFound=1;
9641 + if(HalDev->OsFunc->Strcmpi(pszAction, hcGet) == 0)
9642 + {
9643 + *(int *)Value = HalDev->dev_base;
9644 + return(0);
9645 + }
9646 + }
9647 +
9648 + if(HalDev->OsFunc->Strcmpi(pszKey, hcFullDuplex) == 0)
9649 + {
9650 + KeyFound=1;
9651 + if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
9652 + {
9653 + UPDATE_FULLDUPLEX(*(unsigned int *)Value);
9654 + if(HalDev->State == enOpened)
9655 + ConfigApply(HalDev);
9656 + return(0);
9657 + }
9658 + else
9659 + return(-1);
9660 + }
9661 +
9662 + if(HalDev->OsFunc->Strcmpi(pszKey, pszDebug) == 0)
9663 + {
9664 + KeyFound=1;
9665 + if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
9666 + {
9667 + ActionFound=1;
9668 + HalDev->debug = *(int *)Value;
9669 + }
9670 + }
9671 +
9672 + if(HalDev->OsFunc->Strcmpi(pszKey, hcMaxFrags) == 0)
9673 + {
9674 + KeyFound=1;
9675 + if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
9676 + {
9677 + ActionFound=1;
9678 +
9679 + if ((*(int *)Value) > 0)
9680 + HalDev->MaxFrags = *(int *)Value;
9681 + else
9682 + rc = (EC_AAL5|EC_FUNC_CONTROL|EC_VAL_INVALID_VALUE);
9683 + }
9684 +
9685 + if (HalDev->OsFunc->Strcmpi(pszAction, hcGet) == 0)
9686 + {
9687 + ActionFound=1;
9688 +
9689 + *(int *)Value = HalDev->MaxFrags;
9690 + }
9691 + }
9692 +
9693 + if(HalDev->OsFunc->Strstr(pszKey, pszStats) != 0)
9694 + {
9695 + KeyFound=1;
9696 + if(HalDev->OsFunc->Strcmpi(pszAction, hcGet) == 0)
9697 + {
9698 + int Level;
9699 + int Ch;
9700 + char *TmpKey = (char *)pszKey;
9701 + ActionFound=1;
9702 + TmpKey += HalDev->OsFunc->Strlen(pszStats);
9703 + Level = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
9704 + TmpKey++;
9705 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
9706 + TmpKey++;
9707 + osfuncSioFlush();
9708 +#ifdef __CPHAL_DEBUG
9709 + if (DBG(1))
9710 + {
9711 + dbgPrintf("\nhalControl-HalDev:%08X, Level:%d, Ch:%d\n", (bit32u)HalDev, Level, Ch);
9712 + }
9713 +#endif
9714 + StatsGet(HalDev, (void **)Value, Level, Ch, 0);
9715 + osfuncSioFlush();
9716 + }
9717 + }
9718 +
9719 +
9720 + if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
9721 + Action = enSET;
9722 + else
9723 + if(HalDev->OsFunc->Strcmpi(pszAction, hcClear) == 0)
9724 + Action = enCLEAR;
9725 + else
9726 + if(HalDev->OsFunc->Strcmpi(pszAction, hcGet) == 0)
9727 + Action = enGET;
9728 + else
9729 + Action = enNULL;
9730 +
9731 +
9732 +
9733 + for(i=enCommonStart+1;i<enCommonEnd;i++)
9734 + {
9735 + if(HalDev->OsFunc->Strcmpi(KeyCommon[i].strKey, pszKey)==0)
9736 + {
9737 + rc = InfoAccess(HalDev, KeyCommon[i].enKey, Action, Value);
9738 + }
9739 + }
9740 + for(i=enCpmacStart+1;i<enCpmacEnd;i++)
9741 + {
9742 + if(HalDev->OsFunc->Strcmpi(KeyCpmac[i].strKey, pszKey)==0)
9743 + {
9744 + rc = InfoAccess(HalDev, KeyCpmac[i].enKey, Action, Value);
9745 + }
9746 + }
9747 +/*
9748 + if (KeyFound == 0)
9749 + rc = (EC_MODULE|EC_FUNC_CONTROL|EC_VAL_KEY_NOT_FOUND);
9750 +
9751 + if (ActionFound == 0)
9752 + rc = (EC_MODULE|EC_FUNC_CONTROL|EC_VAL_ACTION_NOT_FOUND);
9753 +*/
9754 +
9755 + return(rc);
9756 + }
9757 +static bit32u ConfigGet(HAL_DEVICE *HalDev)
9758 + {
9759 + OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
9760 + char *DeviceInfo = HalDev->DeviceInfo;
9761 + int i = HalDev->inst;
9762 + bit32u Value;
9763 + int Error;
9764 +
9765 + /* get the configuration parameters common to all modules */
9766 + Error = ConfigGetCommon(HalDev);
9767 + if (Error) return (EC_CPMAC|Error);
9768 +
9769 + if (HalDev->debug)
9770 + {
9771 + dbgPrintf("ConfigGet: haldev:0x%08X inst:%d base:0x%08X reset:%d\n", (bit32u) &HalDev, HalDev->inst, HalDev->dev_base, HalDev->ResetBit);
9772 + osfuncSioFlush();
9773 + }
9774 +
9775 + Error = OsFunc->DeviceFindParmUint(DeviceInfo, pszMdioConnect,&Value); /*MJH+030805*/
9776 + if(!Error) HalDev->MdioConnect = Value;
9777 +
9778 + Error = OsFunc->DeviceFindParmUint(DeviceInfo, "PhyMask",&Value);
9779 + if(!Error) HalDev->PhyMask = Value;
9780 +
9781 + Error = OsFunc->DeviceFindParmUint(DeviceInfo, "MLink",&Value);
9782 + if(!Error) HalDev->MLinkMask = Value;
9783 +
9784 + Error = OsFunc->DeviceFindParmUint(DeviceInfo, hcMdixMask, &Value);
9785 + if(!Error)
9786 + HalDev->MdixMask = Value;
9787 + else
9788 + HalDev->MdixMask = 0;
9789 +
9790 + Error = OsFunc->DeviceFindParmUint(DeviceInfo, hcSize, &Value); /*MJH+030425*/
9791 + if(!Error) HalDev->CpmacSize = Value;
9792 +
9793 + for(i=enCommonStart+1;i<enCommonEnd;i++)
9794 + {
9795 + Error = OsFunc->DeviceFindParmUint(DeviceInfo, KeyCommon[i].strKey, (bit32u*)&Value);
9796 + if(!Error)
9797 + {
9798 + InfoAccess(HalDev, KeyCommon[i].enKey, enSET, (bit32u*)&Value);
9799 + }
9800 + }
9801 + for(i=enCpmacStart+1;i<enCpmacEnd;i++)
9802 + {
9803 + Error = OsFunc->DeviceFindParmUint(DeviceInfo, KeyCpmac[i].strKey, (bit32u*)&Value);
9804 + if(!Error)
9805 + {
9806 + InfoAccess(HalDev, KeyCpmac[i].enKey, enSET, (bit32u*)&Value);
9807 + }
9808 + }
9809 + return (EC_NO_ERRORS);
9810 + }
9811 +
9812 +
9813 +static void ConfigInit(HAL_DEVICE *HalDev)
9814 + {
9815 + if(HalDev->inst == 0)
9816 + {
9817 + HalDev->dev_base = 0xA8610000;
9818 + HalDev->ResetBit = 17;
9819 + HalDev->interrupt = 19;
9820 + HalDev->MLinkMask = 0;
9821 + HalDev->PhyMask = 0xAAAAAAAA;
9822 + }
9823 + else
9824 + {
9825 + HalDev->dev_base = 0xA8612800;
9826 + HalDev->ResetBit = 21;
9827 + HalDev->interrupt = 33; /*~RC3.02*/
9828 + HalDev->MLinkMask = 0;
9829 + HalDev->PhyMask = 0x55555555;
9830 + }
9831 + HalDev->RxMaxLen = 1518;
9832 + HalDev->MaxFrags = 2;
9833 + HalDev->MdioConnect = _CPMDIO_HD|_CPMDIO_FD|_CPMDIO_10|_CPMDIO_100|_CPMDIO_AUTOMDIX;
9834 + HalDev->debug=0xFFFFFFFF;
9835 + HalDev->debug=0;
9836 + }
9837 +/* Shuts down the EMAC device
9838 + *
9839 + *@param HalDev EMAC instance. This was returned by halOpen()
9840 + *@param mode Indicates actions to tak on close.
9841 + <br>
9842 + *PARTIAL - Disable EMAC
9843 + <br>
9844 + *FULL - Disable EMAC and call OS to free all allocated memory
9845 + *
9846 + *@retval
9847 + * 0 OK
9848 + <br>
9849 + * Non-Zero Not OK
9850 + *
9851 + */
9852 +static int halInit( HAL_DEVICE *HalDev)
9853 + {
9854 + int rc;
9855 +
9856 + /* Verify proper device state */
9857 + if (HalDev->State != enDevFound)
9858 + return(EC_CPMAC|EC_FUNC_HAL_INIT|EC_VAL_INVALID_STATE);
9859 +
9860 + /* Configure HAL defaults */
9861 + ConfigInit(HalDev);
9862 +
9863 + /* Retrieve HAL configuration parameters from data store */
9864 + rc = ConfigGet(HalDev);
9865 + if (rc) return (rc);
9866 +
9867 + /* Updated 030403*/
9868 + rc = HalDev->OsFunc->Control(HalDev->OsDev, hcCpuFrequency, hcGet, &HalDev->CpuFrequency); /*MJH+030403*/
9869 + if(rc)
9870 + HalDev->CpuFrequency = 20000000; /*20 Mhz default */ /*MJH+030403*/
9871 +
9872 + rc = HalDev->OsFunc->Control(HalDev->OsDev, hcCpmacFrequency, hcGet, &HalDev->CpmacFrequency); /*MJH+030331*/
9873 + if(rc)
9874 + HalDev->CpmacFrequency = HalDev->CpuFrequency/2; /*MJH~030404*/
9875 +
9876 + rc = HalDev->OsFunc->Control(HalDev->OsDev, hcMdioBusFrequency, hcGet, &HalDev->MdioBusFrequency); /*MJH+030402*/
9877 + if(rc)
9878 + HalDev->MdioBusFrequency = HalDev->CpmacFrequency;
9879 +
9880 + rc = HalDev->OsFunc->Control(HalDev->OsDev, hcMdioClockFrequency, hcGet, &HalDev->MdioClockFrequency); /*MJH+030402*/
9881 + if(rc)
9882 + HalDev->MdioClockFrequency = 2200000; /* 2.2 Mhz PITS #14 */
9883 +
9884 +
9885 + /* update device state */
9886 + HalDev->State = enInitialized;
9887 +
9888 + /* initialize statistics */
9889 + StatsInit(HalDev); /* +RC3.02 */
9890 +
9891 + /* -RC3.02
9892 + StatsTable3[0].StatPtr = &HalDev->ChData[0].RxBufSize;
9893 + StatsTable3[1].StatPtr = &HalDev->ChData[0].RxBufferOffset;
9894 + StatsTable3[2].StatPtr = &HalDev->ChData[0].RxNumBuffers;
9895 + StatsTable3[3].StatPtr = &HalDev->ChData[0].RxServiceMax;
9896 + StatsTable3[4].StatPtr = &HalDev->ChData[0].TxNumBuffers;
9897 + StatsTable3[5].StatPtr = &HalDev->ChData[0].TxNumQueues;
9898 + StatsTable3[6].StatPtr = &HalDev->ChData[0].TxServiceMax;
9899 + */
9900 +
9901 + return(EC_NO_ERRORS);
9902 + }
9903 +static int halProbe(HAL_DEVICE *HalDev)
9904 + {
9905 + int inst = HalDev->inst;
9906 + OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
9907 + int error_code;
9908 +
9909 + if (HalDev->State != enConnected)
9910 + return (EC_CPMAC|EC_FUNC_PROBE|EC_VAL_INVALID_STATE);
9911 +
9912 + if(HalDev->debug) dbgPrintf("halProbe: %d ",inst);
9913 +
9914 + error_code = OsFunc->DeviceFindInfo(inst,"cpmac",&HalDev->DeviceInfo);
9915 +
9916 + if(error_code)
9917 + return (EC_CPMAC|EC_FUNC_PROBE|EC_VAL_DEVICE_NOT_FOUND );
9918 +
9919 + /* Set device state to DevFound */
9920 + HalDev->State = enDevFound;
9921 + return(EC_NO_ERRORS);
9922 + }
9923 +static void ChannelConfigInit(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn)
9924 + {
9925 + int Ch = HalChn->Channel;
9926 + int Direction = HalChn->Direction;
9927 + int nTxBuffers = 256;
9928 +
9929 + if (Direction == DIRECTION_TX)
9930 + {
9931 + HalDev->ChData[Ch].TxNumBuffers = nTxBuffers;
9932 + HalDev->ChData[Ch].TxNumQueues = 1;
9933 + HalDev->ChData[Ch].TxServiceMax = nTxBuffers/3;
9934 + HalDev->TxIntThreshold[Ch] = HalDev->ChData[Ch].TxServiceMax;
9935 + HalDev->TxIntThresholdMaster[Ch] = HalDev->TxIntThreshold[Ch];
9936 + }
9937 +
9938 + if (Direction == DIRECTION_RX)
9939 + {
9940 + HalDev->ChData[Ch].RxNumBuffers = nTxBuffers*2;
9941 + HalDev->ChData[Ch].RxBufferOffset = 0;
9942 + HalDev->ChData[Ch].RxBufSize = 1518;
9943 + HalDev->ChData[Ch].RxServiceMax = nTxBuffers/3; /*Not a typo*/
9944 + }
9945 + }
9946 +static int ChannelConfigApply(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn)
9947 + {
9948 + int Ch = HalChn->Channel;
9949 + int Direction = HalChn->Direction;
9950 +
9951 + if (DBG(11))
9952 + {
9953 + dbgPrintf("halChannelConfigApply[%d:%d] haldev:0x%08X inst:%d base:0x%08X reset:%d\n", Ch, Direction, (bit32u) &HalDev, HalDev->inst, HalDev->dev_base, HalDev->ResetBit);
9954 + osfuncSioFlush();
9955 + }
9956 +
9957 + if (Direction == DIRECTION_TX)
9958 + {
9959 + if (HalDev->ChIsOpen[Ch][Direction] == TRUE)
9960 + {
9961 + return(EC_CPMAC|EC_FUNC_CHSETUP|EC_VAL_TX_CH_ALREADY_OPEN);
9962 + }
9963 +
9964 + /* Initialize Queue Data */
9965 + HalDev->TxActQueueHead[Ch][0] = 0;
9966 + HalDev->TxActQueueCount[Ch][0] = 0;
9967 + HalDev->TxActive[Ch][0] = FALSE;
9968 +
9969 + /* Need to use a macro that takes channel as input */
9970 + CPMAC_TX0_HDP(HalDev->dev_base)=0;
9971 +
9972 + /* Initialize buffer memory for the channel */
9973 + InitTcb(HalDev, Ch);
9974 +
9975 + if(!HalDev->TxIntDisable)
9976 + CPMAC_TX_INTMASK_SET(HalDev->dev_base) = (1<<Ch); /* GSG 11/22 */
9977 + }
9978 + else
9979 + {
9980 + if (HalDev->ChIsOpen[Ch][Direction] == TRUE)
9981 + {
9982 + return(EC_CPMAC|EC_FUNC_CHSETUP|EC_VAL_RX_CH_ALREADY_OPEN);
9983 + }
9984 +
9985 + /* Initialize Queue Data */
9986 + HalDev->RxActQueueHead[Ch] = 0;
9987 + HalDev->RxActQueueCount[Ch] = 0;
9988 +
9989 + HalDev->RxActive[Ch] = FALSE;
9990 +
9991 + /* Need to use a macro that takes channel as input */
9992 + CPMAC_RX0_HDP(HalDev->dev_base)=0;
9993 +
9994 + /* Initialize buffer memory for the channel */
9995 + InitRcb(HalDev, Ch);
9996 +
9997 + CPMAC_RX_INTMASK_SET(HalDev->dev_base) = (1<<Ch); /* GSG 11/22 */
9998 + }
9999 +
10000 + HalDev->ChIsOpen[Ch][Direction] = TRUE; /* channel is open */
10001 +
10002 + return (EC_NO_ERRORS);
10003 + }
10004 +
10005 +/* GSG 11/22
10006 + * Retrieves channel parameters from configuration file. Any parameters
10007 + * which are not found are ignored, and the HAL default value will apply,
10008 + * unless a new value is given through the channel structure in the call
10009 + * to ChannelSetup.
10010 + */
10011 +static int ChannelConfigGet(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn)
10012 + {
10013 + int Ch = HalChn->Channel;
10014 + int Direction = HalChn->Direction;
10015 + OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
10016 + unsigned int rc, Value;
10017 + void *ChInfo;
10018 +
10019 + rc=OsFunc->DeviceFindParmValue(HalDev->DeviceInfo, channel_names[Ch], &ChInfo);
10020 + /* Do not fail if Channel Info not available for RC2 */
10021 + if (rc) return(0);
10022 +/* if (rc) return(EC_CPMAC|EC_FUNC_CHSETUP|EC_VAL_CH_INFO_NOT_FOUND);*/
10023 +
10024 + /* i don't care if a value is not found because they are optional */
10025 + if(Direction == DIRECTION_TX)
10026 + {
10027 + rc=OsFunc->DeviceFindParmUint(ChInfo, "TxNumBuffers", &Value);
10028 + if (!rc) HalDev->ChData[Ch].TxNumBuffers = Value;
10029 +
10030 + /*rc=OsFunc->DeviceFindParmUint(ChInfo, "TxNumQueues", &Value);*/ /*MJH-030329*/
10031 + /*if (!rc) HalDev->ChData[Ch].TxNumQueues = Value;*/ /*MJH-030329*/
10032 +
10033 + rc=OsFunc->DeviceFindParmUint(ChInfo, "TxServiceMax", &Value);
10034 + if (!rc)
10035 + {
10036 + HalDev->ChData[Ch].TxServiceMax = Value;
10037 + HalDev->TxIntThreshold[Ch] = HalDev->ChData[Ch].TxServiceMax;
10038 + HalDev->TxIntThresholdMaster[Ch] = HalDev->TxIntThreshold[Ch];
10039 + }
10040 + }
10041 + if(Direction == DIRECTION_RX)
10042 + {
10043 + rc=OsFunc->DeviceFindParmUint(ChInfo, "RxNumBuffers", &Value);
10044 + if (!rc) HalDev->ChData[Ch].RxNumBuffers = Value;
10045 +
10046 + rc=OsFunc->DeviceFindParmUint(ChInfo, "RxBufferOffset", &Value);
10047 + if (!rc) HalDev->ChData[Ch].RxBufferOffset = Value;
10048 +
10049 + rc=OsFunc->DeviceFindParmUint(ChInfo, "RxBufSize", &Value);
10050 + if (!rc) HalDev->ChData[Ch].RxBufSize = Value;
10051 +
10052 + rc=OsFunc->DeviceFindParmUint(ChInfo, "RxServiceMax", &Value);
10053 + if (!rc) HalDev->ChData[Ch].RxServiceMax = Value;
10054 + }
10055 + return (EC_NO_ERRORS);
10056 + }
10057 +#define ChannelUpdate(Field) if(HalChn->Field != 0xFFFFFFFF) HalDev->ChData[Ch].Field = HalChn->Field
10058 +
10059 +static void ChannelConfigUpdate(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn)
10060 + {
10061 + int Ch = HalChn->Channel;
10062 + int Direction = HalChn->Direction;
10063 +#ifdef __CPHAL_DEBUG
10064 + if (DBG(1))
10065 + {
10066 + dbgPrintf("\nChnUpd-HalDev:%08X,Chn:%d:%d\n", (bit32u)HalDev, Ch, Direction); osfuncSioFlush();
10067 + }
10068 +#endif
10069 + if (Direction == DIRECTION_TX)
10070 + {
10071 + ChannelUpdate(TxNumBuffers);
10072 + /*ChannelUpdate(TxNumQueues);*/ /*MJH~030329*/
10073 + ChannelUpdate(TxServiceMax);
10074 + HalDev->TxIntThreshold[Ch] = HalDev->ChData[Ch].TxServiceMax;
10075 + HalDev->TxIntThresholdMaster[Ch] = HalDev->TxIntThreshold[Ch];
10076 + }
10077 + else
10078 + if (Direction == DIRECTION_RX)
10079 + {
10080 + ChannelUpdate(RxBufferOffset);
10081 + ChannelUpdate(RxBufSize);
10082 + ChannelUpdate(RxNumBuffers);
10083 + ChannelUpdate(RxServiceMax);
10084 +#ifdef __CPHAL_DEBUG
10085 + if (DBG(1))
10086 + {
10087 + dbgPrintf("\nRxNumBuffers %d\n",HalChn->RxNumBuffers); osfuncSioFlush();
10088 + }
10089 +#endif
10090 + }
10091 + }
10092 +static int halChannelSetup(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn, OS_SETUP *OsSetup)
10093 + {
10094 + int Direction;
10095 + int Ch;
10096 + int rc;
10097 +
10098 + /* Verify proper device state */
10099 + if (HalDev->State < enInitialized)
10100 + return (EC_CPMAC|EC_FUNC_CHSETUP|EC_VAL_INVALID_STATE);
10101 +
10102 + /* We require the channel structure to be passed, even if it only contains
10103 + the channel number */
10104 + if (HalChn == NULL)
10105 + {
10106 + return(EC_CPMAC|EC_FUNC_CHSETUP|EC_VAL_NULL_CH_STRUCT);
10107 + }
10108 +
10109 + Ch = HalChn->Channel;
10110 + Direction = HalChn->Direction;
10111 +
10112 + /* This should check on Maximum Channels for RX or TX,
10113 + they might be different Mick 021124 */
10114 + if ((Ch < 0) || (Ch > (MAX_CHAN-1)))
10115 + {
10116 + return(EC_CPMAC|EC_FUNC_CHSETUP|EC_VAL_INVALID_CH);
10117 + }
10118 +
10119 + /* if channel is already open, this call is invalid */
10120 + if (HalDev->ChIsOpen[Ch][Direction] == TRUE)
10121 + {
10122 + return(EC_CPMAC|EC_FUNC_CHSETUP|EC_VAL_CH_ALREADY_OPEN);
10123 + }
10124 +
10125 + /* channel is closed, but might be setup. If so, reopen the hardware channel. */
10126 + if (HalDev->ChIsSetup[Ch][Direction] == FALSE)
10127 + {
10128 + /* Setup channel configuration */
10129 + HalDev->ChData[Ch].Channel = Ch;
10130 +
10131 + /* Store OS_SETUP */
10132 + HalDev->ChData[Ch].OsSetup = OsSetup;
10133 +
10134 + /* Framework :
10135 + Set Default Values
10136 + Update with options.conf
10137 + Apply driver updates
10138 + */
10139 + ChannelConfigInit(HalDev, HalChn);
10140 + ChannelConfigGet(HalDev, HalChn);
10141 + ChannelConfigUpdate(HalDev, HalChn);
10142 +
10143 + /* cppi.c needs to use Rx/TxServiceMax */
10144 + HalDev->BuffersServicedMax = 169; /* TEMP */
10145 +
10146 + HalDev->ChIsSetup[Ch][Direction] = TRUE;
10147 + }
10148 +
10149 + rc = EC_NO_ERRORS;
10150 +
10151 + /* If the hardware has been opened (is out of reset), then configure the channel
10152 + in the hardware. NOTE: ChannelConfigApply calls the CPSAR ChannelSetup()! */
10153 + if (HalDev->State == enOpened)
10154 + {
10155 + rc = ChannelConfigApply(HalDev, HalChn);
10156 + }
10157 +
10158 + return (rc);
10159 + }
10160 +
10161 +
10162 +static int miiInfoGet(HAL_DEVICE *HalDev, bit32u *miiBaseAddress, bit32u *miiResetBit)
10163 + {
10164 + int rc;
10165 + void *DeviceInfo;
10166 + OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
10167 +
10168 + /* Only one instance of cpmdio */
10169 + rc = OsFunc->DeviceFindInfo(0,"cpmdio",&DeviceInfo); /*~RC3.02*/
10170 +
10171 + if(rc)
10172 + return (EC_DEV_CPMDIO|EC_FUNC_OPEN|EC_VAL_DEVICE_NOT_FOUND );
10173 +
10174 + rc = OsFunc->DeviceFindParmUint(DeviceInfo, "base",miiBaseAddress);
10175 + if(rc)
10176 + rc=EC_DEV_CPMDIO|EC_FUNC_OPEN|EC_VAL_NO_BASE;
10177 +
10178 + rc = OsFunc->DeviceFindParmUint(DeviceInfo, "reset_bit",miiResetBit);
10179 + if(rc)
10180 + rc=EC_DEV_CPMDIO|EC_FUNC_OPEN|EC_VAL_NO_BASE;
10181 +
10182 +
10183 + /* See if need to make mdio functional in GPIO */
10184 + gpioCheck(HalDev, DeviceInfo);
10185 +
10186 + if(DBG(0))
10187 + dbgPrintf("miiBase: 0x%08X %u\n", *miiBaseAddress, *miiResetBit);
10188 + return(rc);
10189 + }
10190 +static void ephyCheck(HAL_DEVICE *HalDev)
10191 + { /*+RC3.02*/
10192 + int rc;
10193 + void *DeviceInfo;
10194 + int mii_phy;
10195 + int reset_bit;
10196 + OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
10197 +
10198 + rc = OsFunc->DeviceFindInfo(0,"ephy",&DeviceInfo);
10199 + if(rc) return;
10200 +
10201 + rc = OsFunc->DeviceFindParmUint(DeviceInfo, "mii_phy",&mii_phy);
10202 + if(rc) return;
10203 +
10204 + rc = OsFunc->DeviceFindParmUint(DeviceInfo, "reset_bit",&reset_bit);
10205 + if(rc) return;
10206 +
10207 + if (HalDev->PhyMask & (1 << mii_phy))
10208 + {
10209 + *(volatile bit32u *)(HalDev->ResetBase) |= (1 << reset_bit); /*+RC3.02*/
10210 + resetWait(HalDev);
10211 + }
10212 + } /*+RC3.02*/
10213 +static void AutoNegotiate(HAL_DEVICE *HalDev)
10214 + {
10215 + int size;
10216 + bit32u ModID, RevMaj, RevMin;
10217 + PHY_DEVICE *PhyDev;
10218 + bit32u miiBaseAddress;
10219 + bit32u miiResetBit;
10220 +
10221 + /* Verify proper device state */
10222 + if (HalDev->State < enOpened)
10223 + return;
10224 +
10225 + miiInfoGet(HalDev, &miiBaseAddress, &miiResetBit);
10226 +
10227 + cpMacMdioGetVer(miiBaseAddress, &ModID, &RevMaj, &RevMin);
10228 + if(HalDev->debug)
10229 + dbgPrintf("Mdio Module Id %d, Version %d.%d\n", ModID, RevMaj, RevMin);
10230 +
10231 + size = cpMacMdioGetPhyDevSize();
10232 + PhyDev = (PHY_DEVICE *) HalDev->OsFunc->Malloc( size );
10233 +
10234 + HalDev->PhyDev = PhyDev;
10235 +
10236 + ephyCheck(HalDev);
10237 +
10238 + cpMacMdioInit( PhyDev, miiBaseAddress, HalDev->inst, HalDev->PhyMask, HalDev->MLinkMask, HalDev->MdixMask, HalDev->ResetBase, miiResetBit, HalDev->MdioBusFrequency, HalDev->MdioClockFrequency, HalDev->debug, HalDev); /*MJH~030402*/
10239 + MdioSetPhyMode(HalDev);
10240 +
10241 + return;
10242 + }
10243 +static int halOpen(HAL_DEVICE *HalDev)
10244 + {
10245 + unsigned char *MacAddr;
10246 + int i;
10247 + int j;
10248 + int rc, Ticks;
10249 +
10250 + if (HalDev->debug)
10251 + {
10252 + dbgPrintf("halOpen: haldev:0x%08X inst:%d base:0x%08X reset:%d\n", (bit32u) &HalDev, HalDev->inst, HalDev->dev_base, HalDev->ResetBit);
10253 + osfuncSioFlush();
10254 + }
10255 +
10256 + /* Verify proper device state */
10257 + if (HalDev->State < enInitialized)
10258 + return (EC_CPMAC|EC_FUNC_OPEN|EC_VAL_INVALID_STATE);
10259 +
10260 +
10261 + /* take CPMAC out of reset - GSG 11/20*/
10262 + if ((VOLATILE32(HalDev->ResetBase) & (1 << HalDev->ResetBit)) != 0)
10263 + {
10264 + /* perform normal close duties */
10265 + CPMAC_MACCONTROL(HalDev->dev_base) &= ~MII_EN;
10266 + CPMAC_TX_CONTROL(HalDev->dev_base) &= ~TX_EN;
10267 + CPMAC_RX_CONTROL(HalDev->dev_base) &= ~RX_EN;
10268 +
10269 + /* disable interrupt masks */
10270 + CPMAC_TX_INTMASK_CLEAR(HalDev->dev_base) = 0xFF;
10271 + CPMAC_RX_INTMASK_CLEAR(HalDev->dev_base) = 0xFF;
10272 + }
10273 +
10274 + /* take CPMAC out of reset */
10275 + *(volatile bit32u *)(HalDev->ResetBase) &= ~(1 << HalDev->ResetBit);
10276 + resetWait(HalDev);
10277 + *(volatile bit32u *)(HalDev->ResetBase) |= (1 << HalDev->ResetBit);
10278 + resetWait(HalDev);
10279 +
10280 + /* After Reset clear the Transmit and Receive DMA Head Descriptor Pointers */
10281 +
10282 + CPMAC_TX0_HDP(HalDev->dev_base)=0;
10283 + CPMAC_TX1_HDP(HalDev->dev_base)=0;
10284 + CPMAC_TX2_HDP(HalDev->dev_base)=0;
10285 + CPMAC_TX3_HDP(HalDev->dev_base)=0;
10286 + CPMAC_TX4_HDP(HalDev->dev_base)=0;
10287 + CPMAC_TX5_HDP(HalDev->dev_base)=0;
10288 + CPMAC_TX6_HDP(HalDev->dev_base)=0;
10289 + CPMAC_TX7_HDP(HalDev->dev_base)=0;
10290 +
10291 + /* Rx Init */
10292 +
10293 + CPMAC_RX0_HDP(HalDev->dev_base) = 0;
10294 + CPMAC_RX1_HDP(HalDev->dev_base) = 0;
10295 + CPMAC_RX2_HDP(HalDev->dev_base) = 0;
10296 + CPMAC_RX3_HDP(HalDev->dev_base) = 0;
10297 + CPMAC_RX4_HDP(HalDev->dev_base) = 0;
10298 + CPMAC_RX5_HDP(HalDev->dev_base) = 0;
10299 + CPMAC_RX6_HDP(HalDev->dev_base) = 0;
10300 + CPMAC_RX7_HDP(HalDev->dev_base) = 0;
10301 +
10302 + CPMAC_RX_BUFFER_OFFSET(HalDev->dev_base) = 0;
10303 +
10304 + /* Init Tx and Rx DMA */
10305 +
10306 + CPMAC_TX_CONTROL(HalDev->dev_base) |= TX_EN;
10307 + CPMAC_RX_CONTROL(HalDev->dev_base) |= RX_EN;
10308 +
10309 + CPMAC_MAC_INTMASK_SET(HalDev->dev_base) |=2; /* Enable Adaptercheck Ints */
10310 + HalDev->OsFunc->Control(HalDev->OsDev, pszMacAddr, hcGet, &MacAddr); /* GSG 11/22 */
10311 + MacAddressSave(HalDev, MacAddr);
10312 +
10313 + HalDev->HostErr = 0; /* Clear Adapter Check indicator */
10314 + HalDev->State = enOpened; /* Change device state */
10315 +
10316 + /* Start MDIO Negotiation */
10317 + AutoNegotiate(HalDev);
10318 +
10319 + /* Enable the Os Timer */
10320 + Ticks = HalDev->CpuFrequency / 100; /* 10 milli-secs */ /*MJH~030402*/
10321 + HalDev->OsFunc->Control(HalDev->OsDev, pszTick, hcSet, &Ticks); /* GSG 11/22 */
10322 + HalDev->OsFunc->IsrRegister(HalDev->OsDev, halIsr, HalDev->interrupt);
10323 +
10324 + /* GSG +030523 Malloc space for the Rx fraglist */
10325 + HalDev->fraglist = HalDev->OsFunc->Malloc(HalDev->MaxFrags * sizeof(FRAGLIST));
10326 +
10327 + /* Any pre-open configuration */
10328 +
10329 + /* For any channels that have been pre-initialized, set them up now */
10330 + /* Note : This loop should not use MAX_CHN, it should only
10331 + loop through Channels Setup, memory should not be reserved
10332 + until Channel is Setup
10333 + */
10334 + for(i=0; i<MAX_CHAN; i++) /* i loops through Channels */
10335 + for(j=0; j<2; j++) /* j loops through DIRECTION values, 0 and 1 */
10336 + {
10337 + if(HalDev->ChIsSetup[i][j]==TRUE) /* If the Channel and Direction have been Setup */
10338 + if(HalDev->ChIsOpen[i][j]==FALSE) /* but not opened, then Apply Values now */
10339 + {
10340 + CHANNEL_INFO HalChn;
10341 + HalChn.Channel = i;
10342 + HalChn.Direction = j;
10343 + rc = ChannelConfigApply(HalDev, &HalChn);
10344 + if(rc != EC_NO_ERRORS)
10345 + return(rc);
10346 + }
10347 + } /* End of looping through Channel/Direction */
10348 +
10349 + ConfigApply(HalDev); /* Apply Configuration Values to Device */
10350 + CPMAC_MACCONTROL(HalDev->dev_base) |= MII_EN; /* MAC_EN */
10351 + if(DBG(0))
10352 + dbgPrintf("[halOpen]MacControl:%08X\n", CPMAC_MACCONTROL(HalDev->dev_base));
10353 + return(EC_NO_ERRORS);
10354 + }
10355 +
10356 +#define INT_PENDING (MAC_IN_VECTOR_TX_INT_OR | MAC_IN_VECTOR_RX_INT_OR | MAC_IN_VECTOR_HOST_INT)
10357 +static int halShutdown(HAL_DEVICE *HalDev)
10358 + {
10359 + int Ch, Queue; /*GSG+030514*/
10360 +
10361 + /* Verify proper device state */
10362 + if (HalDev->State == enOpened)
10363 + halClose(HalDev, 3); /* GSG ~030429 */
10364 +
10365 + /* Buffer/descriptor resources may still need to be freed if a Close
10366 + Mode 1 was performed prior to Shutdown - clean up here */ /*GSG+030514*/
10367 + for (Ch=0; Ch<MAX_CHAN; Ch++)
10368 + {
10369 + if (HalDev->RcbStart[Ch] != 0)
10370 + FreeRx(HalDev,Ch);
10371 +
10372 + for(Queue=0; Queue<MAX_QUEUE; Queue++)
10373 + {
10374 + if (HalDev->TcbStart[Ch][Queue] != 0)
10375 + FreeTx(HalDev,Ch,Queue);
10376 + }
10377 + }
10378 +
10379 + /* free the HalFunc */
10380 + HalDev->OsFunc->Free(HalDev->HalFuncPtr);
10381 +
10382 + /* free the HAL device */
10383 + HalDev->OsFunc->Free(HalDev);
10384 +
10385 + return(EC_NO_ERRORS);
10386 + }
10387 +int halIsr(HAL_DEVICE *HalDev, int *MorePackets)
10388 +{
10389 + bit32u IntVec;
10390 + int Serviced;
10391 + int PacketsServiced=0;
10392 + int Channel;
10393 + int TxMorePackets=0;
10394 + int RxMorePackets=0;
10395 +
10396 + /* Verify proper device state - important because a call prior to Open would
10397 + result in a lockup */
10398 + if (HalDev->State != enOpened)
10399 + return(EC_CPMAC|EC_FUNC_DEVICE_INT|EC_VAL_INVALID_STATE);
10400 +
10401 + IntVec = CPMAC_MAC_IN_VECTOR(HalDev->dev_base);
10402 +
10403 +#ifdef __CPHAL_DEBUG
10404 + if (DBG(0))
10405 + {
10406 + dbgPrintf("\nhalIsr: inst %d, IntVec 0x%X\n", HalDev->inst, IntVec); osfuncSioFlush();/* GSG 11/22 */
10407 + }
10408 +#endif
10409 +
10410 + HalDev->IntVec = IntVec;
10411 + if (IntVec & MAC_IN_VECTOR_TX_INT_OR)
10412 + {
10413 + int TxServiceMax=0; /* Compiler complains if not initialized */
10414 +
10415 + Channel = (IntVec & 0x7);
10416 +
10417 + if(HalDev->TxIntDisable)
10418 + {
10419 + CPMAC_TX_INTMASK_CLEAR(HalDev->dev_base) = (1<<Channel); /* Disable Interrupt for Channel */
10420 + TxServiceMax = HalDev->ChData[Channel].TxServiceMax;
10421 + HalDev->ChData[Channel].TxServiceMax = 10000; /* Need to service all packets in the Queue */
10422 + }
10423 +
10424 + PacketsServiced |= TxInt(HalDev, Channel, 0, &TxMorePackets);
10425 +
10426 + if(HalDev->TxIntDisable)
10427 + HalDev->ChData[Channel].TxServiceMax = TxServiceMax;
10428 + }
10429 +
10430 + if (IntVec & MAC_IN_VECTOR_RX_INT_OR)
10431 + {
10432 + Channel = (IntVec >> 8) & 0x7;
10433 + Serviced = RxInt(HalDev, Channel, &RxMorePackets);
10434 + PacketsServiced |= (Serviced<<16);
10435 + }
10436 +
10437 + if (IntVec & MAC_IN_VECTOR_HOST_INT)
10438 + {
10439 + /* Adaptercheck */
10440 + HalDev->HostErr = 1;
10441 + HalDev->MacStatus = CPMAC_MACSTATUS(HalDev->dev_base);
10442 + osfuncStateChange(); /*MJH+030328*/
10443 + if(DBG(0))
10444 + {
10445 + dbgPrintf("Adaptercheck: %08x for base:%X\n",HalDev->MacStatus, (bit32u)HalDev->dev_base);
10446 + osfuncSioFlush();
10447 + }
10448 + }
10449 + *MorePackets = (TxMorePackets | RxMorePackets);
10450 + return (PacketsServiced);
10451 +}
10452 +
10453 +int halPacketProcessEnd(HAL_DEVICE *HalDev)
10454 +{
10455 + int base = HalDev->dev_base;
10456 + CPMAC_MAC_EOI_VECTOR(base) = 0;
10457 + return(0);
10458 +}
10459 +
10460 +
10461 +
10462 +static int PhyCheck(HAL_DEVICE *HalDev)
10463 + {
10464 + return(cpMacMdioTic(HalDev->PhyDev));
10465 + }
10466 +static int halTick(HAL_DEVICE *HalDev)
10467 +{
10468 + int TickChange;
10469 +
10470 + if(HalDev->State < enOpened)
10471 + return (EC_CPMAC|EC_FUNC_TICK|EC_VAL_INVALID_STATE);
10472 +
10473 + /* if NO Phy no need to check Link */
10474 + if(HalDev->MdioConnect & _CPMDIO_NOPHY)
10475 + return(EC_NO_ERRORS); /* No change in Phy State detected */
10476 +
10477 + TickChange = PhyCheck(HalDev);
10478 + /* Phy State Change Detected */
10479 + if(TickChange == 1)
10480 + {
10481 + /* MDIO indicated a change */
10482 + DuplexUpdate(HalDev);
10483 + osfuncStateChange();
10484 + return(EC_NO_ERRORS);
10485 + }
10486 +
10487 + /* if in AutoMdix mode, and Flip request received, inform OS */
10488 + if( (HalDev->MdioConnect & _CPMDIO_AUTOMDIX) &&
10489 + (TickChange & _MIIMDIO_MDIXFLIP))
10490 + {
10491 + bit32u Mdix;
10492 + Mdix = TickChange & 0x1; /* Mdix mode stored in bit 0 */
10493 + HalDev->OsFunc->Control(HalDev->OsDev, hcMdioMdixSwitch, hcSet, &Mdix);
10494 + return(EC_NO_ERRORS);
10495 + }
10496 +
10497 + return(EC_NO_ERRORS);
10498 +}
10499 +
10500 +int halCpmacInitModule(HAL_DEVICE **pHalDev, OS_DEVICE *OsDev, HAL_FUNCTIONS **pHalFunc,
10501 + OS_FUNCTIONS *OsFunc, int OsFuncSize, int *HalFuncSize, int Inst)
10502 + {
10503 + HAL_DEVICE *HalDev;
10504 + HAL_FUNCTIONS *HalFunc;
10505 +
10506 + if (OsFuncSize < sizeof(OS_FUNCTIONS))
10507 + return (EC_CPMAC|EC_FUNC_HAL_INIT|EC_VAL_OS_VERSION_NOT_SUPPORTED);
10508 +
10509 + HalDev = (HAL_DEVICE *) OsFunc->MallocDev(sizeof(HAL_DEVICE));
10510 + if (!HalDev)
10511 + return (EC_CPMAC|EC_FUNC_HAL_INIT|EC_VAL_MALLOC_DEV_FAILED);
10512 +
10513 + /* clear the HalDev area */
10514 + OsFunc->Memset(HalDev, 0, sizeof(HAL_DEVICE));
10515 +
10516 + /* Initialize the size of hal functions */
10517 + *HalFuncSize = sizeof (HAL_FUNCTIONS);
10518 +
10519 + HalFunc = (HAL_FUNCTIONS *) OsFunc->Malloc(sizeof(HAL_FUNCTIONS));
10520 + if (!HalFunc)
10521 + return (EC_CPMAC|EC_FUNC_HAL_INIT|EC_VAL_MALLOC_FAILED);
10522 +
10523 + /* clear the function pointers */
10524 + OsFunc->Memset(HalFunc, 0, sizeof(HAL_FUNCTIONS));
10525 +
10526 + HalDev->OsDev = OsDev;
10527 + HalDev->OsOpen = OsDev;
10528 + HalDev->inst = Inst;
10529 + HalDev->OsFunc = OsFunc;
10530 + HalDev->HalFunc = HalFunc;
10531 + /* Remove the following from cppi, replace with HalFunc */
10532 + HalDev->HalFuncPtr = HalFunc; /* GSG 11/20 changed name to match cppi */
10533 +
10534 + /****************************************************************/
10535 + /* POPULATE HALFUNC */
10536 + /****************************************************************/
10537 + HalFunc->ChannelSetup = halChannelSetup;
10538 + HalFunc->ChannelTeardown = halChannelTeardown; /* GSG 11/20 */
10539 + HalFunc->Close = halClose; /* GSG 11/20 */
10540 + HalFunc->Control = halControl; /* GSG 11/22 */
10541 + HalFunc->Init = halInit;
10542 + HalFunc->Open = halOpen;
10543 + HalFunc->PacketProcessEnd = halPacketProcessEnd;
10544 + HalFunc->Probe = halProbe;
10545 + HalFunc->RxReturn = halRxReturn;
10546 + HalFunc->Send = halSend;
10547 + HalFunc->Shutdown = halShutdown;
10548 + HalFunc->Tick = halTick;
10549 +
10550 + /* HalFunc->Status = halStatus;*/ /* GSG 11/22 */
10551 + /* pass the HalDev and HalFunc back to the caller */
10552 +
10553 + *pHalDev = HalDev;
10554 + *pHalFunc = HalFunc;
10555 +
10556 + HalDev->State = enConnected; /* Initialize the hardware state */
10557 +
10558 + if (HalDev->debug) HalDev->OsFunc->Printf("halCpmacInitModule: Leave\n");
10559 + return(0);
10560 + }
10561 +
10562 +int cpmacRandomRange(HAL_DEVICE *HalDev, int min, int max)
10563 +{
10564 + int iTmp;
10565 + iTmp = cpmacRandom(HalDev);
10566 + iTmp %= ((max-min)+1);
10567 + iTmp += min;
10568 + return(iTmp);
10569 +}
10570 +
10571 +int cpmacRandom(HAL_DEVICE *HalDev)
10572 +{
10573 + int iTmp;
10574 + iTmp = CPMAC_BOFFTEST(HalDev->dev_base);
10575 + iTmp >>= 16; /* get rndnum field */
10576 + iTmp &= (0x3FF); /* field is 10 bits wide */
10577 + return(iTmp);
10578 +}
10579 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/hcpmac.h linux-2.4.30/drivers/net/avalanche_cpmac/hcpmac.h
10580 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/hcpmac.h 1970-01-01 02:00:00.000000000 +0200
10581 +++ linux-2.4.30/drivers/net/avalanche_cpmac/hcpmac.h 2005-04-15 05:10:41.000000000 +0200
10582 @@ -0,0 +1,383 @@
10583 +/** @file***********************************************************************
10584 + * TNETDxxxx Software Support
10585 + * Copyright (c) 2002 Texas Instruments Incorporated. All Rights Reserved.
10586 + *
10587 + * FILE:
10588 + *
10589 + * DESCRIPTION:
10590 + * This file contains definitions for the HAL EMAC API
10591 + *
10592 + * HISTORY:
10593 + * xxXxx01 Denis 1.00 Original Version created.
10594 + * 22Jan02 Denis/Mick 1.01 Modified for HAL EMAC API
10595 + * 24Jan02 Denis/Mick 1.02 Speed Improvements
10596 + * 28Jan02 Denis/Mick 1.16 Made function calls pointers
10597 + * 28Jan02 Mick 1.18 Split into separate modules
10598 + * @author Michael Hanrahan
10599 + * @version 1.02
10600 + * @date 24-Jan-2002
10601 + *****************************************************************************/
10602 +#ifndef _INC_HCPMAC
10603 +#define _INC_HCPMAC
10604 +
10605 +/** \namespace CPMAC_Version
10606 +This documents version 01.07.04 of the CPMAC CPHAL.
10607 +*/
10608 +const char *pszVersion_CPMAC="CPMAC 01.07.08 "__DATE__" "__TIME__;
10609 +
10610 +/* CHECK THESE LOCATIONS */
10611 +#define TEARDOWN_VAL 0xfffffffc
10612 +#define CB_OFFSET_MASK 0xFFFF0000
10613 +
10614 +
10615 +#define MAX_CHAN 8
10616 +#define MAX_QUEUE 1
10617 +
10618 +typedef struct
10619 + {
10620 + bit32 HNext; /*< Hardware's pointer to next buffer descriptor */
10621 + bit32 BufPtr; /*< Pointer to the data buffer */
10622 + bit32 Off_BLen; /*< Contains buffer offset and buffer length */
10623 + bit32 mode; /*< SOP, EOP, Ownership, EOQ, Teardown, Q Starv, Length */
10624 + void *Next;
10625 + void *OsInfo;
10626 + void *Eop;
10627 +#ifdef __CPHAL_DEBUG
10628 + bit32 DbgSop;
10629 + bit32 DbgData;
10630 + bit32 DbgFraglist;
10631 +#endif
10632 + }HAL_TCB;
10633 +
10634 +typedef volatile struct hal_private
10635 + {
10636 + bit32 HNext; /*< Hardware's pointer to next buffer descriptor */
10637 + bit32 BufPtr; /*< Pointer to the data buffer */
10638 + bit32 Off_BLen; /*< Contains buffer offset and buffer length */
10639 + bit32 mode; /*< SOP, EOP, Ownership, EOQ, Teardown Complete bits */
10640 + void *DatPtr;
10641 + void *Next;
10642 + void *OsInfo;
10643 + void *Eop;
10644 + }HAL_RCB;
10645 +
10646 +#define MAX_NEEDS 512 /*MJH+030409*/
10647 +/* HAL */
10648 +
10649 +typedef struct hal_device
10650 + {
10651 + OS_DEVICE *OsDev;
10652 + OS_FUNCTIONS *OsFunc;
10653 + /*OS_SETUP *OsSetup;*/ /* -GSG 030508 */
10654 + int inst;
10655 + bit32u rxbufseq;
10656 +
10657 +
10658 + bit32 dev_base;
10659 + bit32 offset;
10660 +
10661 + bit32u ResetBase; /* GSG 10/20 */
10662 + int ResetBit;
10663 + void *OsOpen;
10664 + bit32u IntVec;
10665 + PHY_DEVICE *PhyDev;
10666 + bit32u EmacDuplex;
10667 + bit32u EmacSpeed;
10668 + bit32u PhyNum;
10669 + bit32u MLinkMask;
10670 + bit32u PhyMask;
10671 + bit32u MdixMask;
10672 +
10673 + bit32u Linked;
10674 + DEVICE_STATE State;
10675 + unsigned char *MacAddr;
10676 + HAL_FUNCTIONS *HalFuncPtr; /* GSG 11/20 changed name to match cppi */
10677 + HAL_FUNCTIONS *HalFunc;
10678 +/* unsigned int CpuFreq;*/ /*MJH-030402*/
10679 + unsigned int MdioConnect;
10680 + unsigned int HostErr;
10681 +
10682 +/************************************************************************/
10683 +/* */
10684 +/* R E G I S T E R S */
10685 +/* */
10686 +/************************************************************************/
10687 +
10688 + bit32u RxMbpEnable;
10689 + bit32u RxUnicastSet;
10690 + bit32u RxUnicastClear;
10691 + bit32u RxMaxLen;
10692 + bit32u RxFilterLowThresh;
10693 + bit32u Rx0FlowThresh;
10694 + bit32u MacControl;
10695 + bit32u MacStatus;
10696 + bit32u MacHash1;
10697 + bit32u MacHash2;
10698 +
10699 +/************************************************************************/
10700 +/* */
10701 +/* O P T I O N S */
10702 +/* */
10703 +/************************************************************************/
10704 +
10705 + char *DeviceInfo;
10706 + bit32u interrupt;
10707 +
10708 +
10709 + bit32u RxPassCrc;
10710 + bit32u RxCaf;
10711 + bit32u RxCef;
10712 + bit32u RxBcast;
10713 + bit32u RxBcastCh;
10714 + HAL_RCB *RcbPool[MAX_CHAN];
10715 + bit32 RxActQueueCount[MAX_CHAN];
10716 + HAL_RCB *RxActQueueHead[MAX_CHAN];
10717 + HAL_RCB *RxActQueueTail[MAX_CHAN];
10718 + bit32 RxActive[MAX_CHAN];
10719 + HAL_TCB *TcbPool[MAX_CHAN][MAX_QUEUE];
10720 + bit32 TxActQueueCount[MAX_CHAN][MAX_QUEUE];
10721 + HAL_TCB *TxActQueueHead[MAX_CHAN][MAX_QUEUE];
10722 + HAL_TCB *TxActQueueTail[MAX_CHAN][MAX_QUEUE];
10723 + bit32 TxActive[MAX_CHAN][MAX_QUEUE];
10724 + bit32 TxTeardownPending[MAX_CHAN];
10725 + bit32 RxTeardownPending[MAX_CHAN];
10726 + bit32 ChIsOpen[MAX_CHAN][2];
10727 + bit32 ChIsSetup[MAX_CHAN][2];
10728 + FRAGLIST *fraglist;
10729 + char *TcbStart[MAX_CHAN][MAX_QUEUE];
10730 + char *RcbStart[MAX_CHAN];
10731 + bit32 RcbSize[MAX_CHAN];
10732 +/* STAT_INFO Stats; */
10733 + bit32 Inst;
10734 + bit32u BuffersServicedMax;
10735 + CHANNEL_INFO ChData[MAX_CHAN];
10736 + bit32u MdioClockFrequency; /*MJH+030402*/
10737 + bit32u MdioBusFrequency; /*MJH+030402*/
10738 + bit32u CpuFrequency; /*MJH+030402*/
10739 + bit32u CpmacFrequency; /*MJH+030403*/
10740 + bit32u CpmacSize; /*MJH+030425*/
10741 + int debug;
10742 + bit32u NeedsCount; /*MJH+030409*/
10743 + HAL_RECEIVEINFO *Needs[MAX_NEEDS]; /*MJH+030409*/
10744 + int MaxFrags;
10745 + int TxIntThreshold[MAX_CHAN]; /* MJH 040621 NSP Performance Update */
10746 + int TxIntThresholdMaster[MAX_CHAN]; /* MJH 040827 NSP Performance Update */
10747 + int TxIntDisable; /* MJH 040621 NSP Performance Update */
10748 + }HALDEVICE;
10749 +
10750 +#define STATS_MAX 36
10751 +
10752 +#define MACCONTROL_MASK (TX_PTYPE|TX_PACE|TX_FLOW_EN|RX_FLOW_EN|CTRL_LOOPBACK)
10753 +#define RX_MBP_ENABLE_MASK \
10754 + (RX_PASS_CRC|RX_QOS_EN|RX_NO_CHAIN| \
10755 + RX_CMF_EN|RX_CSF_EN|RX_CEF_EN|RX_CAF_EN|RX_PROM_CH_MASK| \
10756 + RX_BROAD_EN|RX_BROAD_CH_MASK|RX_MULT_EN|RX_MULT_CH_MASK)
10757 +
10758 +
10759 +#define MBP_UPDATE(Mask, On) \
10760 + if(On) HalDev->RxMbpEnable |= Mask; \
10761 + else HalDev->RxMbpEnable &= ~Mask
10762 +
10763 +#define CONTROL_UPDATE(Mask, On) \
10764 + if(On) HalDev->MacControl |= Mask; \
10765 + else HalDev->MacControl &= ~Mask
10766 +
10767 +
10768 +#define UPDATE_TX_PTYPE(Value) CONTROL_UPDATE(TX_PTYPE,Value)
10769 +#define UPDATE_TX_PACE(Value) CONTROL_UPDATE(TX_PACE,Value)
10770 +#define UPDATE_MII_EN(Value) CONTROL_UPDATE(MII_EN,Value)
10771 +#define UPDATE_TX_FLOW_EN(Value) CONTROL_UPDATE(TX_FLOW_EN,Value)
10772 +#define UPDATE_RX_FLOW_EN(Value) CONTROL_UPDATE(RX_FLOW_EN,Value)
10773 +#define UPDATE_CTRL_LOOPBACK(Value) CONTROL_UPDATE(CTRL_LOOPBACK,Value)
10774 +#define UPDATE_FULLDUPLEX(Value) CONTROL_UPDATE(FULLDUPLEX,(Value))
10775 +
10776 +#define UPDATE_RX_PASS_CRC(Value) MBP_UPDATE(RX_PASS_CRC, Value)
10777 +#define UPDATE_RX_QOS_EN(Value) MBP_UPDATE(RX_QOS_EN, Value)
10778 +#define UPDATE_RX_NO_CHAIN(Value) MBP_UPDATE(RX_NO_CHAIN, Value)
10779 +#define UPDATE_RX_CMF_EN(Value) MBP_UPDATE(RX_CMF_EN, Value)
10780 +#define UPDATE_RX_CSF_EN(Value) MBP_UPDATE(RX_CSF_EN, Value)
10781 +#define UPDATE_RX_CEF_EN(Value) MBP_UPDATE(RX_CEF_EN, Value)
10782 +#define UPDATE_RX_CAF_EN(Value) MBP_UPDATE(RX_CAF_EN, Value)
10783 +#define UPDATE_RX_BROAD_EN(Value) MBP_UPDATE(RX_BROAD_EN, Value)
10784 +#define UPDATE_RX_MULT_EN(Value) MBP_UPDATE(RX_MULT_EN, Value)
10785 +
10786 +#define UPDATE_RX_PROM_CH(Value) \
10787 + HalDev->RxMbpEnable &= ~RX_PROM_CH_MASK; \
10788 + HalDev->RxMbpEnable |= RX_PROM_CH(Value)
10789 +
10790 +#define UPDATE_RX_BROAD_CH(Value) \
10791 + HalDev->RxMbpEnable &= ~RX_BROAD_CH_MASK; \
10792 + HalDev->RxMbpEnable |= RX_BROAD_CH(Value)
10793 +
10794 +#define UPDATE_RX_MULT_CH(Value) \
10795 + HalDev->RxMbpEnable &= ~RX_MULT_CH_MASK; \
10796 + HalDev->RxMbpEnable |= RX_MULT_CH(Value)
10797 +
10798 +
10799 +
10800 +typedef enum
10801 + {
10802 + /* CPMAC */
10803 + enCpmacStart=0,
10804 + enStats0,
10805 + enStats1,
10806 + enStats2,
10807 + enStats3,
10808 + enStats4,
10809 + enStatsDump,
10810 + enStatsClear,
10811 + enRX_PASS_CRC,
10812 + enRX_QOS_EN,
10813 + enRX_NO_CHAIN,
10814 + enRX_CMF_EN,
10815 + enRX_CSF_EN,
10816 + enRX_CEF_EN,
10817 + enRX_CAF_EN,
10818 + enRX_PROM_CH,
10819 + enRX_BROAD_EN,
10820 + enRX_BROAD_CH,
10821 + enRX_MULT_EN,
10822 + enRX_MULT_CH,
10823 +
10824 + enTX_PTYPE,
10825 + enTX_PACE,
10826 + enMII_EN,
10827 + enTX_FLOW_EN,
10828 + enRX_FLOW_EN,
10829 + enCTRL_LOOPBACK,
10830 +
10831 + enRX_MAXLEN,
10832 + enRX_FILTERLOWTHRESH,
10833 + enRX0_FLOWTHRESH,
10834 + enRX_UNICAST_SET,
10835 + enRX_UNICAST_CLEAR,
10836 + enMdioConnect,
10837 + enMAC_ADDR_GET,
10838 + enTick,
10839 + enRX_MULTICAST,
10840 + enRX_MULTI_ALL,
10841 + enRX_MULTI_SINGLE,
10842 + enVersion,
10843 + enCpmacEnd /* Last entry */
10844 + }INFO_KEY_CPMAC;
10845 +
10846 +static const char pszVersion[] = "Version";
10847 +static const char pszStats0[] = "Stats0";
10848 +static const char pszStats1[] = "Stats1";
10849 +static const char pszStats2[] = "Stats2";
10850 +static const char pszStats3[] = "Stats3";
10851 +static const char pszStats4[] = "Stats4";
10852 +static const char pszStatsDump[] = "StatsDump";
10853 +static const char pszStatsClear[] = "StatsClear";
10854 +
10855 +/********************************************************************
10856 +**
10857 +** RX MBP ENABLE
10858 +**
10859 +********************************************************************/
10860 +static const char pszRX_PASS_CRC[] = "RX_PASS_CRC";
10861 +static const char pszRX_QOS_EN[] = "RX_QOS_EN";
10862 +static const char pszRX_NO_CHAIN[] = "RX_NO_CHAIN";
10863 +static const char pszRX_CMF_EN[] = "RX_CMF_EN";
10864 +static const char pszRX_CSF_EN[] = "RX_CSF_EN";
10865 +static const char pszRX_CEF_EN[] = "RX_CEF_EN";
10866 +static const char pszRX_CAF_EN[] = "RX_CAF_EN";
10867 +static const char pszRX_PROM_CH[] = "RX_PROM_CH";
10868 +static const char pszRX_BROAD_EN[] = "RX_BROAD_EN";
10869 +static const char pszRX_BROAD_CH[] = "RX_BROAD_CH";
10870 +static const char pszRX_MULT_EN[] = "RX_MULT_EN";
10871 +static const char pszRX_MULT_CH[] = "RX_MULT_CH";
10872 +
10873 +
10874 +/********************************************************************
10875 +**
10876 +** MAC CONTROL
10877 +**
10878 +********************************************************************/
10879 +static const char pszTX_PTYPE[] = "TX_PTYPE";
10880 +static const char pszTX_PACE[] = "TX_PACE";
10881 +static const char pszMII_EN[] = "MII_EN";
10882 +static const char pszTX_FLOW_EN[] = "TX_FLOW_EN";
10883 +static const char pszRX_FLOW_EN[] = "RX_FLOW_EN";
10884 +static const char pszCTRL_LOOPBACK[] = "CTRL_LOOPBACK";
10885 +
10886 +static const char pszRX_MAXLEN[] = "RX_MAXLEN";
10887 +static const char pszRX_FILTERLOWTHRESH[] = "RX_FILTERLOWTHRESH";
10888 +static const char pszRX0_FLOWTHRESH[] = "RX0_FLOWTHRESH";
10889 +static const char pszRX_UNICAST_SET[] = "RX_UNICAST_SET";
10890 +static const char pszRX_UNICAST_CLEAR[] = "RX_UNICAST_CLEAR";
10891 +static const char pszMdioConnect[] = "MdioConnect";
10892 +static const char pszMacAddr[] = "MacAddr";
10893 +static const char pszTick[] = "Tick";
10894 +
10895 +/********************************************************************
10896 +**
10897 +** MULTICAST
10898 +**
10899 +********************************************************************/
10900 +
10901 +static const char pszRX_MULTICAST[] = "RX_MULTICAST";
10902 +static const char pszRX_MULTI_ALL[] = "RX_MULTI_ALL";
10903 +static const char pszRX_MULTI_SINGLE[] = "RX_MULTI_SINGLE";
10904 +
10905 +/*
10906 +static const char* pszGFHN = "GFHN";
10907 +*/
10908 +
10909 +static const CONTROL_KEY KeyCpmac[] =
10910 + {
10911 + {"" , enCpmacStart},
10912 + {pszStats0 , enStats0},
10913 + {pszStats1 , enStats1},
10914 + {pszStats2 , enStats2},
10915 + {pszStats3 , enStats3},
10916 + {pszStats4 , enStats4},
10917 + {pszStatsClear , enStatsClear},
10918 + {pszStatsDump , enStatsDump},
10919 + {pszRX_PASS_CRC , enRX_PASS_CRC},
10920 + {pszRX_QOS_EN , enRX_QOS_EN},
10921 + {pszRX_NO_CHAIN , enRX_NO_CHAIN},
10922 + {pszRX_CMF_EN , enRX_CMF_EN},
10923 + {pszRX_CSF_EN , enRX_CSF_EN},
10924 + {pszRX_CEF_EN , enRX_CEF_EN},
10925 + {pszRX_CAF_EN , enRX_CAF_EN},
10926 + {pszRX_PROM_CH , enRX_PROM_CH},
10927 + {pszRX_BROAD_EN , enRX_BROAD_EN},
10928 + {pszRX_BROAD_CH , enRX_BROAD_CH},
10929 + {pszRX_MULT_EN , enRX_MULT_EN},
10930 + {pszRX_MULT_CH , enRX_MULT_CH},
10931 +
10932 + {pszTX_PTYPE , enTX_PTYPE},
10933 + {pszTX_PACE , enTX_PACE},
10934 + {pszMII_EN , enMII_EN},
10935 + {pszTX_FLOW_EN , enTX_FLOW_EN},
10936 + {pszRX_FLOW_EN , enRX_FLOW_EN},
10937 + {pszCTRL_LOOPBACK , enCTRL_LOOPBACK},
10938 + {pszRX_MAXLEN , enRX_MAXLEN},
10939 + {pszRX_FILTERLOWTHRESH , enRX_FILTERLOWTHRESH},
10940 + {pszRX0_FLOWTHRESH , enRX0_FLOWTHRESH},
10941 + {pszRX_UNICAST_SET , enRX_UNICAST_SET},
10942 + {pszRX_UNICAST_CLEAR , enRX_UNICAST_CLEAR},
10943 + {pszMdioConnect , enMdioConnect},
10944 + {pszRX_MULTICAST , enRX_MULTICAST},
10945 + {pszRX_MULTI_ALL , enRX_MULTI_ALL},
10946 + {pszRX_MULTI_SINGLE , enRX_MULTI_SINGLE},
10947 + {pszTick , enTick},
10948 + {pszVersion , enVersion},
10949 + {"" , enCpmacEnd}
10950 + };
10951 +
10952 +const char hcCpuFrequency[] = "CpuFreq";
10953 +const char hcCpmacFrequency[] = "CpmacFrequency";
10954 +const char hcMdioBusFrequency[] = "MdioBusFrequency";
10955 +const char hcMdioClockFrequency[] = "MdioClockFrequency";
10956 +const char hcCpmacBase[] = "CpmacBase";
10957 +const char hcPhyNum[] = "PhyNum";
10958 +const char hcSize[] = "size";
10959 +const char hcCpmacSize[] = "CpmacSize";
10960 +const char hcPhyAccess[] = "PhyAccess";
10961 +const char hcLinked[] = "Linked";
10962 +const char hcFullDuplex[] = "FullDuplex";
10963 +const char hcMdixMask[] = "MdixMask";
10964 +const char hcMdioMdixSwitch[] = "MdixSet";
10965 +#endif
10966 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/Makefile linux-2.4.30/drivers/net/avalanche_cpmac/Makefile
10967 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/Makefile 1970-01-01 02:00:00.000000000 +0200
10968 +++ linux-2.4.30/drivers/net/avalanche_cpmac/Makefile 2005-04-15 05:10:40.000000000 +0200
10969 @@ -0,0 +1,26 @@
10970 +# File: drivers/net/avalanche_cpmac/Makefile
10971 +#
10972 +# Makefile for the Linux network (CPMAC) device drivers.
10973 +#
10974 +
10975 +O_TARGET := avalanche_cpmac.o
10976 +
10977 +
10978 +list-multi := avalanche_cpmac.o
10979 +obj-$(CONFIG_MIPS_AVALANCHE_CPMAC) := avalanche_cpmac.o
10980 +
10981 +avalanche_cpmac-objs += cpmac.o cpmacHalLx.o hcpmac.o \
10982 + psp_config_build.o psp_config_mgr.o \
10983 + psp_config_parse.o psp_config_util.o
10984 +
10985 +
10986 +include $(TOPDIR)/Rules.make
10987 +
10988 +
10989 +avalanche_cpmac.o: $(avalanche_cpmac-objs)
10990 + $(LD) -r -o $@ $(avalanche_cpmac-objs)
10991 +
10992 +
10993 +
10994 +clean:
10995 + rm -f core *.o *.a *.s
10996 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/mdio_reg.h linux-2.4.30/drivers/net/avalanche_cpmac/mdio_reg.h
10997 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/mdio_reg.h 1970-01-01 02:00:00.000000000 +0200
10998 +++ linux-2.4.30/drivers/net/avalanche_cpmac/mdio_reg.h 2005-07-08 22:08:44.964969914 +0200
10999 @@ -0,0 +1,121 @@
11000 +/****************************************************************************
11001 +** TNETD53xx Software Support
11002 +** Copyright(c) 2002, Texas Instruments Incorporated. All Rights Reserved.
11003 +**
11004 +** FILE: mdio_reg.h Register definitions for the VBUS MII module
11005 +**
11006 +** DESCRIPTION:
11007 +** This include file contains register definitions for the
11008 +** VBUS MII module.
11009 +**
11010 +** HISTORY:
11011 +** 27Mar02 Michael Hanrahan Original (modified from emacmdio.h)
11012 +** 01Apr02 Michael Hanrahan Modified to include all regs. in spec
11013 +** 03Apr02 Michael Hanrahan Updated to Version 0.6 of spec
11014 +** 05Apr02 Michael Hanrahan Moved Phy Mode values into here
11015 +** 30Apr02 Michael Hanrahan Updated to Version 0.8 of spec
11016 +** 30Apr02 Michael Hanrahan Updated to recommended format
11017 +** 10May02 Michael Hanrahan Updated to Version 0.9 of spec
11018 +*****************************************************************************/
11019 +#ifndef _INC_MDIO_REG
11020 +#define _INC_MDIO_REG
11021 +
11022 +/***************************************************************************
11023 +**
11024 +** M D I O M E M O R Y M A P
11025 +**
11026 +***************************************************************************/
11027 +
11028 +
11029 +#define pMDIO_VER(base) ((volatile bit32u *)(base+0x00))
11030 +#define pMDIO_CONTROL(base) ((volatile bit32u *)(base+0x04))
11031 +#define pMDIO_ALIVE(base) ((volatile bit32u *)(base+0x08))
11032 +#define pMDIO_LINK(base) ((volatile bit32u *)(base+0x0C))
11033 +#define pMDIO_LINKINTRAW(base) ((volatile bit32u *)(base+0x10))
11034 +#define pMDIO_LINKINTMASKED(base) ((volatile bit32u *)(base+0x14))
11035 +#define pMDIO_USERINTRAW(base) ((volatile bit32u *)(base+0x20))
11036 +#define pMDIO_USERINTMASKED(base) ((volatile bit32u *)(base+0x24))
11037 +#define pMDIO_USERINTMASKED_SET(base) ((volatile bit32u *)(base+0x28))
11038 +#define pMDIO_USERINTMASKED_CLR(base) ((volatile bit32u *)(base+0x2C))
11039 +#define pMDIO_USERACCESS(base, channel) ((volatile bit32u *)(base+(0x80+(channel*8))))
11040 +#define pMDIO_USERPHYSEL(base, channel) ((volatile bit32u *)(base+(0x84+(channel*8))))
11041 +
11042 +
11043 +/***************************************************************************
11044 +**
11045 +** M D I O R E G I S T E R A C C E S S M A C R O S
11046 +**
11047 +***************************************************************************/
11048 +
11049 +
11050 +#define MDIO_ALIVE(base) (*(pMDIO_ALIVE(base)))
11051 +#define MDIO_CONTROL(base) (*(pMDIO_CONTROL(base)))
11052 +#define MDIO_CONTROL_IDLE (1 << 31)
11053 +#define MDIO_CONTROL_ENABLE (1 << 30)
11054 +#define MDIO_CONTROL_PREAMBLE (1 << 20)
11055 +#define MDIO_CONTROL_FAULT (1 << 19)
11056 +#define MDIO_CONTROL_FAULT_DETECT_ENABLE (1 << 18)
11057 +#define MDIO_CONTROL_INT_TEST_ENABLE (1 << 17)
11058 +#define MDIO_CONTROL_HIGHEST_USER_CHANNEL (0x1F << 8)
11059 +#define MDIO_CONTROL_CLKDIV (0xFF)
11060 +#define MDIO_LINK(base) (*(pMDIO_LINK(base)))
11061 +#define MDIO_LINKINTRAW(base) (*(pMDIO_LINKINTRAW(base)))
11062 +#define MDIO_LINKINTMASKED(base) (*(pMDIO_LINKINTMASKED(base)))
11063 +#define MDIO_USERINTRAW(base) (*(pMDIO_USERINTRAW(base)))
11064 +#define MDIO_USERINTMASKED(base) (*(pMDIO_USERINTMASKED(base)))
11065 +#define MDIO_USERINTMASKED_CLR(base) (*(pMDIO_USERINTMASKED_CLR(base)))
11066 +#define MDIO_USERINTMASKED_SET(base) (*(pMDIO_USERINTMASKED_SET(base)))
11067 +#define MDIO_USERINTRAW(base) (*(pMDIO_USERINTRAW(base)))
11068 +#define MDIO_USERACCESS(base, channel) (*(pMDIO_USERACCESS(base, channel)))
11069 +#define MDIO_USERACCESS_GO (1 << 31)
11070 +#define MDIO_USERACCESS_WRITE (1 << 30)
11071 +#define MDIO_USERACCESS_READ (0 << 30)
11072 +#define MDIO_USERACCESS_ACK (1 << 29)
11073 +#define MDIO_USERACCESS_REGADR (0x1F << 21)
11074 +#define MDIO_USERACCESS_PHYADR (0x1F << 16)
11075 +#define MDIO_USERACCESS_DATA (0xFFFF)
11076 +#define MDIO_USERPHYSEL(base, channel) (*(pMDIO_USERPHYSEL(base, channel)))
11077 +#define MDIO_USERPHYSEL_LINKSEL (1 << 7)
11078 +#define MDIO_USERPHYSEL_LINKINT_ENABLE (1 << 6)
11079 +#define MDIO_USERPHYSEL_PHYADR_MON (0x1F)
11080 +#define MDIO_VER(base) (*(pMDIO_VER(base)))
11081 +#define MDIO_VER_MODID (0xFFFF << 16)
11082 +#define MDIO_VER_REVMAJ (0xFF << 8)
11083 +#define MDIO_VER_REVMIN (0xFF)
11084 +
11085 +
11086 +
11087 +
11088 +/****************************************************************************/
11089 +/* */
11090 +/* P H Y R E G I S T E R D E F I N I T I O N S */
11091 +/* */
11092 +/****************************************************************************/
11093 +
11094 +
11095 +#define PHY_CONTROL_REG 0
11096 + #define PHY_RESET (1<<15)
11097 + #define PHY_LOOP (1<<14)
11098 + #define PHY_100 (1<<13)
11099 + #define AUTO_NEGOTIATE_EN (1<<12)
11100 + #define PHY_PDOWN (1<<11)
11101 + #define PHY_ISOLATE (1<<10)
11102 + #define RENEGOTIATE (1<<9)
11103 + #define PHY_FD (1<<8)
11104 +
11105 +#define PHY_STATUS_REG 1
11106 + #define NWAY_COMPLETE (1<<5)
11107 + #define NWAY_CAPABLE (1<<3)
11108 + #define PHY_LINKED (1<<2)
11109 +
11110 +#define NWAY_ADVERTIZE_REG 4
11111 +#define NWAY_REMADVERTISE_REG 5
11112 + #define NWAY_FD100 (1<<8)
11113 + #define NWAY_HD100 (1<<7)
11114 + #define NWAY_FD10 (1<<6)
11115 + #define NWAY_HD10 (1<<5)
11116 + #define NWAY_SEL (1<<0)
11117 + #define NWAY_AUTO (1<<0)
11118 +
11119 +
11120 +#endif _INC_MDIO_REG
11121 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/psp_config_build.c linux-2.4.30/drivers/net/avalanche_cpmac/psp_config_build.c
11122 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/psp_config_build.c 1970-01-01 02:00:00.000000000 +0200
11123 +++ linux-2.4.30/drivers/net/avalanche_cpmac/psp_config_build.c 2005-07-08 22:09:17.761928277 +0200
11124 @@ -0,0 +1,336 @@
11125 +/******************************************************************************
11126 + * FILE PURPOSE: PSP Config Manager - Configuration Build Source
11127 + ******************************************************************************
11128 + * FILE NAME: psp_config_build.c
11129 + *
11130 + * DESCRIPTION: Configuration Build API Implementation
11131 + *
11132 + * REVISION HISTORY:
11133 + * 27 Nov 02 - PSP TII
11134 + *
11135 + * (C) Copyright 2002, Texas Instruments, Inc
11136 + *******************************************************************************/
11137 +
11138 +#ifdef INCLUDE_FFS
11139 +#include "ffs.h"
11140 +#endif /* INCLUDE_FFS */
11141 +
11142 +#include "psp_config_mgr.h"
11143 +#include "psp_config_build.h"
11144 +#include "psp_config_util.h"
11145 +
11146 +#define MAX_DEVICE_NAME_LEN 16
11147 +#define MAX_DEVICE_STR_LEN 512
11148 +
11149 +#ifndef NULL
11150 +#define NULL (char *)0
11151 +#endif
11152 +
11153 +#include <asm/ar7/avalanche_misc.h>
11154 +#include <asm/ar7/sangam.h>
11155 +#include <linux/slab.h>
11156 +#include <linux/config.h>
11157 +
11158 +
11159 +#define os_malloc(size) kmalloc(size, GFP_KERNEL)
11160 +
11161 +int psp_run_enumerator(void)
11162 +{
11163 + return(0);
11164 +}
11165 +
11166 +#if defined (CONFIG_AVALANCHE_CPMAC_AUTO)
11167 +
11168 +static int auto_detect_cpmac_phy(void)
11169 +{
11170 +
11171 +#define SELECT_INT_PHY_MAC 0
11172 +#define SELECT_EXT_PHY_MAC 1
11173 +
11174 + volatile unsigned long *reset_cntl = AVALANCHE_RESET_CONTROL_BASE, *mdio_cntl = ((int)AVALANCHE_MDIO_BASE + 0x4);
11175 + unsigned int j= 0, detected_phy_map = 0, auto_select = SELECT_INT_PHY_MAC;
11176 +
11177 + *reset_cntl |= (1 << AVALANCHE_MDIO_RESET_BIT) | (1 << AVALANCHE_LOW_CPMAC_RESET_BIT) | (1 << AVALANCHE_HIGH_CPMAC_RESET_BIT) | (1 << AVALANCHE_LOW_EPHY_RESET_BIT);
11178 + *mdio_cntl = (1 << 30) | (avalanche_get_vbus_freq()/2200000);
11179 +
11180 + for(j=0;j < 300000; j++)
11181 + {
11182 + if(j%100000) continue;
11183 +
11184 + detected_phy_map = *(mdio_cntl + 1);
11185 + if(detected_phy_map)
11186 + {
11187 + detected_phy_map &= ~AVALANCHE_LOW_CPMAC_PHY_MASK;
11188 +
11189 + if(detected_phy_map && !(detected_phy_map & (detected_phy_map - 1)))
11190 + {
11191 + auto_select = SELECT_EXT_PHY_MAC;
11192 + break;
11193 + }
11194 + }
11195 + }
11196 +
11197 + return(auto_select);
11198 +
11199 +}
11200 +
11201 +#endif
11202 +
11203 +
11204 +#ifndef AVALANCHE_LOW_CPMAC_MDIX_MASK
11205 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0
11206 +#endif
11207 +
11208 +void psp_load_default_static_cfg(void)
11209 +{
11210 + char s2[100], s3[100];
11211 + char s4[2000], s6[2000];
11212 + int threshold = 20;
11213 + char *tx_threshold_ptr = prom_getenv("threshold");
11214 +
11215 + if(tx_threshold_ptr)
11216 + threshold = simple_strtol(tx_threshold_ptr, (char **)NULL, 10);
11217 +
11218 + /* Static configuration if options.conf not present */
11219 + sprintf(s3,"cpmdio(id=mii, base=%u, reset_bit=%d)", AVALANCHE_MDIO_BASE, 22);
11220 + sprintf(s2, "reset( id=[ResetRegister], base=%u)", AVALANCHE_RESET_CONTROL_BASE);
11221 +
11222 + sprintf(s4, "cpmac(id=[cpmac], unit=0, base=%u, size=0x800, reset_bit=%d, PhyMask=%u, MdixMask=%u, MLink=0, int_line=%d, memory_offset=0, RX_CAF=1, RX_PASSCRC=0, RX_CEF=1, RX_BCAST=0, RX_BCASTCH=0, Ch0=[TxNumBuffers=256, TxNumQueues=1, TxServiceMax=%d, RxNumBuffers=256, RxBufferOffset=0, RxBufSize=1000, RxServiceMax=128], Ch1=[TxNumBuffers=256, TxNumQueues=1, TxServiceMax=%d, RxNumBuffers=256, RxBufferOffset=0, RxBufSize=1000, RxServiceMax=128], Ch2=[TxNumBuffers=256, TxNumQueues=1, TxServiceMax=%d, RxNumBuffers=256, RxBufferOffset=0, RxBufSize=1000, RxServiceMax=128])", AVALANCHE_LOW_CPMAC_BASE, AVALANCHE_LOW_CPMAC_RESET_BIT, AVALANCHE_LOW_CPMAC_PHY_MASK, AVALANCHE_LOW_CPMAC_MDIX_MASK, AVALANCHE_LOW_CPMAC_INT,threshold,threshold,threshold);
11223 +
11224 + sprintf(s6, "cpmac(id=[cpmac], unit=1, base=%u, size=0x800, reset_bit=%d, PhyMask=%u, MLink=0, int_line=%d, memory_offset=0, RX_CAF=1, RX_PASSCRC=0, RX_CEF=1, RX_BCAST=0, RX_BCASTCH=0, Ch0=[TxNumBuffers=256, TxNumQueues=1, TxServiceMax=%d, RxNumBuffers=256, RxBufferOffset=0, RxBufSize=1000, RxServiceMax=128], Ch1=[TxNumBuffers=256, TxNumQueues=1, TxServiceMax=%d, RxNumBuffers=256, RxBufferOffset=0, RxBufSize=1000, RxServiceMax=128], Ch2=[TxNumBuffers=256, TxNumQueues=1, TxServiceMax=%d, RxNumBuffers=256, RxBufferOffset=0, RxBufSize=1000, RxServiceMax=128])", AVALANCHE_HIGH_CPMAC_BASE, AVALANCHE_HIGH_CPMAC_RESET_BIT, AVALANCHE_HIGH_CPMAC_PHY_MASK, AVALANCHE_HIGH_CPMAC_INT,threshold,threshold,threshold);
11225 +
11226 + psp_config_add("reset", s2, psp_config_strlen(s2), en_compile);
11227 +
11228 +
11229 +#if defined (CONFIG_AVALANCHE_LOW_CPMAC)
11230 +
11231 + psp_config_add("cpmdio", s3, psp_config_strlen(s3), en_compile);
11232 + psp_config_add("cpmac", s4, psp_config_strlen(s4), en_compile);
11233 +
11234 +#endif
11235 +
11236 +
11237 +#if defined (CONFIG_AVALANCHE_HIGH_CPMAC)
11238 +
11239 + psp_config_add("cpmdio", s3, psp_config_strlen(s3), en_compile);
11240 + psp_config_add("cpmac", s6, psp_config_strlen(s6), en_compile);
11241 +
11242 +#endif
11243 +
11244 +#if defined (CONFIG_AVALANCHE_CPMAC_AUTO)
11245 + {
11246 + char *phy_sel_ptr = prom_getenv("mac_phy_sel");
11247 + int phy_sel = SELECT_EXT_PHY_MAC;
11248 + char *mac_port = prom_getenv("MAC_PORT"); /* Internal: 0, External: 1 */
11249 +
11250 + if(phy_sel_ptr && (0 == strcmp(phy_sel_ptr, "int")))
11251 + {
11252 + phy_sel = SELECT_INT_PHY_MAC;
11253 + }
11254 +
11255 + //if(phy_sel == auto_detect_cpmac_phy())
11256 + if(!mac_port || (0 != strcmp(mac_port, "0")))
11257 + {
11258 + printk("Using the MAC with external PHY\n");
11259 + psp_config_add("cpmdio", s3, psp_config_strlen(s3), en_compile);
11260 + psp_config_add("cpmac", s6, psp_config_strlen(s6), en_compile);
11261 + }
11262 + else
11263 + {
11264 + printk("Using the MAC with internal PHY\n");
11265 + psp_config_add("cpmdio", s3, psp_config_strlen(s3), en_compile);
11266 + psp_config_add("cpmac", s4, psp_config_strlen(s4), en_compile);
11267 + }
11268 + }
11269 +
11270 +#endif
11271 +
11272 +}
11273 +
11274 +char* psp_conf_read_file(char *p_file_name)
11275 +{
11276 +#ifdef INCLUDE_FFS
11277 +
11278 + char *p_file_data = NULL;
11279 + unsigned int file_size;
11280 + FFS_FILE *p_file = NULL;
11281 +
11282 + if(p_file_name == NULL)
11283 + {
11284 + return (NULL);
11285 + }
11286 +
11287 + if(!(p_file = ffs_fopen(p_file_name, "r")))
11288 + {
11289 + return(NULL);
11290 + }
11291 +
11292 + file_size = p_file->_AvailableBytes;
11293 +
11294 + p_file_data = os_malloc(file_size + 1);
11295 +
11296 + if(ffs_fread(p_file_data, file_size, 1, p_file) == 0)
11297 + {
11298 + kfree(p_file_data);
11299 + return(NULL);
11300 + }
11301 +
11302 + ffs_fclose(p_file);
11303 +
11304 + p_file_data[file_size] = '\0';
11305 +
11306 + return(p_file_data);
11307 +
11308 +#else /* NO FFS */
11309 + return(NULL);
11310 +#endif /* INCLUDE_FFS */
11311 +}
11312 +
11313 +int psp_conf_get_line(char *p_in_data, char **next_line)
11314 +{
11315 + char *p = p_in_data;
11316 +
11317 + while(*p && *p++ != '\n')
11318 + {
11319 +
11320 + }
11321 +
11322 + *next_line = p;
11323 +
11324 + return(p - 1 - p_in_data);
11325 +}
11326 +
11327 +
11328 +int psp_conf_is_data_line(char *line)
11329 +{
11330 + int ret_val = 1;
11331 +
11332 + if(*line == '\0' || *line == '\n' || *line == '#')
11333 + ret_val = 0;
11334 +
11335 + return(ret_val);
11336 +}
11337 +
11338 +int psp_conf_get_key_size(char *data)
11339 +{
11340 + char *p = data;
11341 +
11342 + while(*p && *p != '\n' && *p != '(' && *p != ' ')
11343 + p++;
11344 +
11345 + return(p - data);
11346 +}
11347 +
11348 +char* psp_conf_eat_white_spaces(char *p)
11349 +{
11350 + while(*p && *p != '\n' && *p == ' ')
11351 + p++;
11352 +
11353 + return (p);
11354 +}
11355 +
11356 +int psp_build_from_opt_conf(void)
11357 +{
11358 + char *data = NULL;
11359 + char *data_hold = NULL;
11360 + char *next_line = NULL;
11361 + int line_size = 0;
11362 +
11363 + if((data = psp_conf_read_file("/etc/options.conf")) == NULL)
11364 + return(-1);
11365 +
11366 + data_hold = data;
11367 +
11368 + while((line_size=psp_conf_get_line(data, &next_line)) != -1)
11369 + {
11370 +
11371 + char *name = NULL;
11372 + int name_size;
11373 +
11374 + data = psp_conf_eat_white_spaces(data);
11375 +
11376 + if(psp_conf_is_data_line(data))
11377 + {
11378 + data[line_size] = '\0';
11379 +
11380 + name_size = psp_conf_get_key_size(data);
11381 +
11382 + if(name_size > 0)
11383 + {
11384 + name = (char *) os_malloc(name_size + 1);
11385 + if(name == NULL) break;
11386 +
11387 + psp_config_memcpy(name, data, name_size);
11388 + name[name_size] = '\0';
11389 +
11390 + psp_config_add(name, data, line_size, en_opt_conf);
11391 +
11392 + kfree(name);
11393 + }
11394 +
11395 + data[line_size] = '\n';
11396 + }
11397 +
11398 + data = next_line;
11399 + }
11400 +
11401 + kfree(data_hold);
11402 + return (0);
11403 +}
11404 +
11405 +
11406 +int psp_write_conf_file(char *p_write_file, char * dev_cfg_string)
11407 +{
11408 +#ifdef INCLUDE_FFS
11409 + int bytes_written=0;
11410 + FFS_FILE *file_ptr=NULL;
11411 +
11412 + /*
11413 + * NOTE: In current implementation of FFS in ADAM2 if the file exists beforehand, it
11414 + * can't be opened for write.
11415 + */
11416 + if(!(file_ptr=ffs_fopen(p_write_file, "w"))) {
11417 + return(-1);
11418 + }
11419 +
11420 + /* Write into the file "output.con" the character string */
11421 + /* write a \n before a writing a line */
11422 + if(!(bytes_written = ffs_fwrite("\n", 1, sizeof(char), file_ptr))) {
11423 + return (-1);
11424 + }
11425 +
11426 + if(!(bytes_written = ffs_fwrite(dev_cfg_string, psp_config_strlen(dev_cfg_string), sizeof(char), file_ptr))) {
11427 + return (-1);
11428 + }
11429 + ffs_fclose(file_ptr);
11430 + return (bytes_written+1);
11431 +#else /* NO FFS */
11432 + return(-1);
11433 +#endif /* INCLUDE_FFS */
11434 +}
11435 +
11436 +void build_psp_config(void)
11437 +{
11438 +
11439 + /* initialize the repository. */
11440 + psp_config_init();
11441 +
11442 +#ifdef INCLUDE_FFS
11443 + ffs_init();
11444 +#endif /* INCLUDE_FFS */
11445 +
11446 + /* read the configuration from the options.conf to override default ones */
11447 + psp_build_from_opt_conf();
11448 +
11449 + /* read the configuration which were not over ridden in options.conf */
11450 + psp_load_default_static_cfg();
11451 +
11452 + /* let the vlynq be enumerated. Enumerator will add cfg info
11453 + of the discovered device instances to the repository.*/
11454 + psp_run_enumerator();
11455 +
11456 + /* dump the repository*/
11457 + dump_device_cfg_pool();
11458 +
11459 +}
11460 +
11461 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/psp_config_build.h linux-2.4.30/drivers/net/avalanche_cpmac/psp_config_build.h
11462 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/psp_config_build.h 1970-01-01 02:00:00.000000000 +0200
11463 +++ linux-2.4.30/drivers/net/avalanche_cpmac/psp_config_build.h 2005-04-15 05:10:41.000000000 +0200
11464 @@ -0,0 +1,138 @@
11465 +/******************************************************************************
11466 + * FILE PURPOSE: PSP Config Manager - Configuration Build Header
11467 + ******************************************************************************
11468 + * FILE NAME: psp_config_build.h
11469 + *
11470 + * DESCRIPTION: Configuration Build API's.
11471 + *
11472 + * REVISION HISTORY:
11473 + * 27 Nov 02 - PSP TII
11474 + *
11475 + * (C) Copyright 2002, Texas Instruments, Inc
11476 + *******************************************************************************/
11477 +
11478 +#ifndef __PSP_CONF_BUILD_H__
11479 +#define __PSP_CONF_BUILD_H__
11480 +
11481 +/*------------------------------------------------------------------------------
11482 + * Name: psp_conf_read_file
11483 + *
11484 + * Parameters:
11485 + * in: p_file_name - the name of the file to read from.
11486 + *
11487 + * Description:
11488 + * Reads the entire file in one shot. This function opens the
11489 + * file, determines the size of the data to be read, allocates
11490 + * the required memory, NULL terminates the data and closes the
11491 + * file.
11492 + *
11493 + * It is responsibily of the callee to free the memory after it is
11494 + * done with that data.
11495 + *
11496 + *
11497 + * Returns:
11498 + * A NULL pointer, if failed to read the data otherwise, a valid
11499 + * pointer referring to the data read from the file.
11500 + *
11501 + * Example:
11502 + *
11503 + * psp_conf_read_file("/etc/options.conf");
11504 + *---------------------------------------------------------------------------*/
11505 + char *psp_conf_read_file(char *p_file_name);
11506 +
11507 + /*----------------------------------------------------------------------------
11508 + * Function : psp_conf_write_file
11509 + *
11510 + * Parameters:
11511 + * in: p_file_name - the file to which data is to be written.
11512 + * in: data - the NULL terminated data string.
11513 + *
11514 + * Description:
11515 + * Write the indicated data into the file. This function opens the file,
11516 + * appends the data to end of the file, closes the file.
11517 + *
11518 + * Returns:
11519 + *
11520 + * The number of bytes on success.
11521 + * 0 on failure.
11522 + *
11523 + * Example:
11524 + *
11525 + * psp_conf_write_file("/etc/outcon.conf", data);
11526 + *--------------------------------------------------------------------------*/
11527 + int psp_conf_write_file(char *p_file_name, char *data);
11528 +
11529 + /*----------------------------------------------------------------------------
11530 + * Function: psp_conf_get_line
11531 + *
11532 + * Parameters:
11533 + * in: data - the data from which the line is to identified.
11534 + * out: next_line - the pointer to start of the next line.
11535 + *
11536 + * Description:
11537 + * Expects the data to be '\n' separated segments and data is NULL
11538 + * terminated. Parses the given data for '\n' or '\0'. Provides a pointer
11539 + * to the start of next line in the next_line.
11540 + *
11541 + * Returns:
11542 + * -1 on error.
11543 + * 0 or more to indicate the number of bytes in the line starting at
11544 + * data.
11545 + *--------------------------------------------------------------------------*/
11546 + int psp_get_conf_line(char *p_in_data, char **next_line);
11547 +
11548 + /*----------------------------------------------------------------------------
11549 + * Function: psp_conf_is_data_line
11550 + *
11551 + * Parameters:
11552 + * in: line - the array of bytes.
11553 + *
11554 + * Description:
11555 + * Tests the first byte in the array for '\0' or '\n' or '#'. Lines
11556 + * starting with these characters are not considered data.
11557 + *
11558 + * Returns:
11559 + * 1 if the line has data.
11560 + * 0 otherwise.
11561 + *
11562 + *--------------------------------------------------------------------------*/
11563 + int psp_conf_is_data_line(char *line);
11564 +
11565 + /*----------------------------------------------------------------------------
11566 + * Function: psp_conf_eat_white_spaces
11567 + *
11568 + * Parameters:
11569 + * in: line - the array of bytes.
11570 + *
11571 + * Description:
11572 + * Eats white spaces at the begining of the line while looking out for
11573 + * '\0' or '\n' or ' '.
11574 + *
11575 + * Returns:
11576 + * Pointer to the begining of the non white space character.
11577 + * NULL if '\0' or '\n' is found.
11578 + *
11579 + *--------------------------------------------------------------------------*/
11580 + char *psp_conf_eat_white_spaces(char *line);
11581 +
11582 + /*---------------------------------------------------------------------------
11583 + * Function: psp_conf_get_key_size
11584 + *
11585 + * Parameters:
11586 + * in: line - the array of bytes.
11587 + *
11588 + * Description:
11589 + * Identifies the size of the 'key' in array formatted as
11590 + * key(id=[key1]....). This function also checks out for '\0' and '\n'.
11591 + *
11592 + * Returns:
11593 + * On success, The number of bytes that forms the key.
11594 + * 0 otherwise.
11595 + *
11596 + *-------------------------------------------------------------------------*/
11597 + int psp_conf_get_key_size(char *line);
11598 +
11599 +
11600 +
11601 +#endif /* __PSP_CONF_BUILD_H__ */
11602 +
11603 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/psp_config_mgr.c linux-2.4.30/drivers/net/avalanche_cpmac/psp_config_mgr.c
11604 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/psp_config_mgr.c 1970-01-01 02:00:00.000000000 +0200
11605 +++ linux-2.4.30/drivers/net/avalanche_cpmac/psp_config_mgr.c 2005-04-15 05:10:41.000000000 +0200
11606 @@ -0,0 +1,464 @@
11607 +/******************************************************************************
11608 + * FILE PURPOSE: PSP Config Manager Source
11609 + ******************************************************************************
11610 + * FILE NAME: psp_config_mgr.c
11611 + *
11612 + * DESCRIPTION:
11613 + *
11614 + * Manages configuration information. The repository is managed on the basis of
11615 + * <key, info> pair. It is possible to have multiple occurrence of the same key.
11616 + * Multiple occurences of the same keys are referred to as 'instances'.
11617 + * 'instances' are assigned in the order of configuration arrival. The first
11618 + * config for a 'key' added to the repository would be treated as instance 0 and
11619 + * next config to arrive for the same key would be treated as instance '1' and
11620 + * so on.
11621 + *
11622 + * Info is retrieved from the repository based on the 'key' and 'instance' value.
11623 + *
11624 + * No assumption is made about the format of the information that is put in the
11625 + * repository. The only requirement is that 'key' should be NULL terminated
11626 + * string.
11627 + *
11628 + * REVISION HISTORY:
11629 + * 27 Nov 02 - PSP TII
11630 + *
11631 + * (C) Copyright 2002, Texas Instruments, Inc
11632 + *******************************************************************************/
11633 +
11634 +//#include <stdio.h>
11635 +//#include <stdlib.h>
11636 +#include "psp_config_mgr.h"
11637 +#include "psp_config_util.h"
11638 +
11639 +#include <linux/slab.h>
11640 +
11641 +/*-----------------------------------------------------------
11642 + Implemented elsewhere
11643 + -----------------------------------------------------------*/
11644 +extern int sys_read_options_conf(void);
11645 +extern int sys_write_options_conf(char *cfg_info);
11646 +extern int sys_load_default_static_cfg(void);
11647 +extern int sys_run_enumerator(void);
11648 +
11649 +#define os_malloc(size) kmalloc(size, GFP_KERNEL)
11650 +
11651 +/*---------------------------------------------------------
11652 + * Data structures.
11653 + *--------------------------------------------------------*/
11654 +struct device_cfg_data;
11655 +
11656 +typedef struct device_instance_cfg_data
11657 +{
11658 + struct device_instance_cfg_data *next;
11659 + char locale[100];
11660 + unsigned int data_size;
11661 + char *data;
11662 +
11663 +} DEV_INSTANCE_CFG_DATA_T;
11664 +
11665 +struct device_cfg_collection;
11666 +
11667 +typedef struct device_cfg_collection
11668 +{
11669 + struct device_cfg_collection *next;
11670 + char *device_name;
11671 + CFG_TYPE_T cfg_type;
11672 + int count;
11673 + DEV_INSTANCE_CFG_DATA_T *dev_inst_list_begin;
11674 + DEV_INSTANCE_CFG_DATA_T *dev_inst_list_end;
11675 +} DEVICE_CFG_T;
11676 +
11677 +
11678 +typedef struct device_cfg_list
11679 +{
11680 + DEVICE_CFG_T *device_cfg_begin;
11681 + int count;
11682 +} DEVICE_CFG_LIST_T;
11683 +
11684 +/*-----------------------------------------------------------------------------
11685 + * Functions used locally with in the file.
11686 + *---------------------------------------------------------------------------*/
11687 +static void p_init_device_cfg_list(void);
11688 +static int p_add_instance_cfg_data(DEVICE_CFG_T *p_dev_cfg,
11689 + DEV_INSTANCE_CFG_DATA_T *p_dev_inst_data);
11690 +static DEVICE_CFG_T* p_create_dev_cfg(char *device_name);
11691 +static DEVICE_CFG_T* p_get_dev_cfg(char *device_name);
11692 +static int p_set_device_cfg_type(DEVICE_CFG_T *p_dev_cfg,
11693 + CFG_TYPE_T cfg_type);
11694 +
11695 +/* PSP Config manager debug */
11696 +#define PSP_CFG_MGR_DEBUG 0
11697 +
11698 +#define dbgPrint if (PSP_CFG_MGR_DEBUG) printk
11699 +
11700 +/*-----------------------------------------------------------------------------
11701 + * The repository.
11702 + *---------------------------------------------------------------------------*/
11703 +static DEVICE_CFG_LIST_T g_device_cfg_list;
11704 +
11705 +/*---------------------------------------------
11706 + * Initialize the device collection pool.
11707 + *--------------------------------------------*/
11708 +void p_init_device_cfg_list(void)
11709 +{
11710 + g_device_cfg_list.count = 0;
11711 + g_device_cfg_list.device_cfg_begin = NULL;
11712 +}
11713 +
11714 +/*----------------------------------------------------------------------
11715 + * Add the device cfg into the device linked list.
11716 + *---------------------------------------------------------------------*/
11717 +int p_add_dev_cfg_to_list(DEVICE_CFG_LIST_T *p_dev_list,
11718 + DEVICE_CFG_T *p_dev_cfg)
11719 +{
11720 + if(p_dev_list->count != 0)
11721 + p_dev_cfg->next = p_dev_list->device_cfg_begin;
11722 +
11723 + p_dev_list->device_cfg_begin = p_dev_cfg;
11724 +
11725 + p_dev_list->count++;
11726 +
11727 + return (0);
11728 +}
11729 +
11730 +/*------------------------------------------------------------------
11731 + * Add the cfg data into the cfg data linked list of the collection.
11732 + *------------------------------------------------------------------*/
11733 +int p_add_instance_cfg_data(DEVICE_CFG_T *p_dev_cfg,
11734 + DEV_INSTANCE_CFG_DATA_T *p_dev_inst_data)
11735 +{
11736 + if(p_dev_cfg->count == 0)
11737 + p_dev_cfg->dev_inst_list_begin = p_dev_inst_data;
11738 + else
11739 + p_dev_cfg->dev_inst_list_end->next = p_dev_inst_data;
11740 +
11741 + p_dev_cfg->dev_inst_list_end = p_dev_inst_data;
11742 +
11743 + p_dev_cfg->count++;
11744 +
11745 + return (0);
11746 +}
11747 +
11748 +/*-----------------------------------------------------------------------------
11749 + * Create the device cfg.
11750 + *---------------------------------------------------------------------------*/
11751 +DEVICE_CFG_T *p_create_dev_cfg(char *device_name)
11752 +{
11753 + DEVICE_CFG_T *p_dev_cfg = NULL;
11754 +
11755 + if((p_dev_cfg = os_malloc(sizeof(DEVICE_CFG_T))) == NULL)
11756 + {
11757 + dbgPrint("Failed to allocate memory for DEVICE_CFG_T.\n");
11758 + }
11759 + else if((p_dev_cfg->device_name = os_malloc(psp_config_strlen(device_name) + 1))==NULL)
11760 + {
11761 + dbgPrint("Failed to allocate memory for device name.\n");
11762 + }
11763 + else
11764 + {
11765 + psp_config_strcpy(p_dev_cfg->device_name, device_name);
11766 + p_dev_cfg->cfg_type = en_raw;
11767 + p_dev_cfg->count = 0;
11768 + p_dev_cfg->dev_inst_list_begin = NULL;
11769 + p_dev_cfg->dev_inst_list_end = NULL;
11770 + p_dev_cfg->next = NULL;
11771 + }
11772 +
11773 + return(p_dev_cfg);
11774 +}
11775 +
11776 +/*------------------------------------------------------------------------------
11777 + * Get the device cfg collection.
11778 + *-----------------------------------------------------------------------------*/
11779 +DEVICE_CFG_T *p_get_dev_cfg(char *device_name)
11780 +{
11781 + int count = 0;
11782 + DEVICE_CFG_T *p_dev_cfg = g_device_cfg_list.device_cfg_begin;
11783 +
11784 + for(count=0; count < g_device_cfg_list.count; count++)
11785 + {
11786 + if(psp_config_strcmp(device_name, p_dev_cfg->device_name) == 0)
11787 + {
11788 + break;
11789 + }
11790 +
11791 + p_dev_cfg = p_dev_cfg->next;
11792 + }
11793 +
11794 + return(p_dev_cfg);
11795 +}
11796 +
11797 +/*-------------------------------------------------------------------------
11798 + * Gets the name for the static cfg type. Utility function. Debug purposes.
11799 + *-------------------------------------------------------------------------*/
11800 +char *p_get_cfg_type_name_for_en(CFG_TYPE_T cfg_type)
11801 +{
11802 + static char raw_str [] = "still raw";
11803 + static char compile_str [] = "configured at compile time";
11804 + static char optconf_str [] = "configured by options.conf";
11805 + static char vlynq_str [] = "configured by VLYNQ";
11806 + static char no_static_str[] = "no static configuration";
11807 +
11808 + if(cfg_type == en_raw)
11809 + return (raw_str);
11810 + else if(cfg_type == en_compile)
11811 + return (compile_str);
11812 + else if(cfg_type == en_opt_conf)
11813 + return (optconf_str);
11814 + else if(cfg_type == en_vlynq)
11815 + return (vlynq_str);
11816 + else
11817 + return (no_static_str);
11818 +
11819 +}
11820 +
11821 +/*-----------------------------------------------------------------------------
11822 + * Sets the static cfg status of the device collection.
11823 + *
11824 + * If the collection is en_virgin then, the collection is assigned to cfg_type.
11825 + * If the cfg_type is en_vlynq then, the old cfg_type is retained.
11826 + * en_compile and en_opt_conf are mutually exclusive. One of these can be
11827 + * accomodated.
11828 + *
11829 + *---------------------------------------------------------------------------*/
11830 +int p_set_device_cfg_type(DEVICE_CFG_T *p_dev_cfg,
11831 + CFG_TYPE_T cfg_type)
11832 +{
11833 + int ret_val = 0;
11834 +
11835 + if(p_dev_cfg->cfg_type == en_raw)
11836 + p_dev_cfg->cfg_type = cfg_type;
11837 + else if((cfg_type == en_vlynq) || (p_dev_cfg->cfg_type == cfg_type))
11838 + ;
11839 + else
11840 + {
11841 + dbgPrint("Device %s has been %s which overrides %s.\n",
11842 + p_dev_cfg->device_name,
11843 + p_get_cfg_type_name_for_en(p_dev_cfg->cfg_type),
11844 + p_get_cfg_type_name_for_en(cfg_type));
11845 + ret_val = -1;
11846 + }
11847 +
11848 + return(ret_val);
11849 +}
11850 +
11851 +/*------------------------------------------------------------------------
11852 + * Add the config str into the repository. The cfg type indicates
11853 + * whether the device has been configured statically, from options.conf or
11854 + * by vlynq enumeration.
11855 + *------------------------------------------------------------------------*/
11856 +int psp_config_add(char *key, void *p_cfg_str, unsigned int cfg_len,
11857 + CFG_TYPE_T cfg_type)
11858 +{
11859 + int ret_val = -1;
11860 + DEVICE_CFG_T *p_dev_cfg = NULL;
11861 + DEV_INSTANCE_CFG_DATA_T *p_dev_inst_data = NULL;
11862 +
11863 + if(p_cfg_str == NULL || key == NULL)
11864 + {
11865 + dbgPrint("Null input pointer(s).\n");
11866 + }
11867 + /* check if there exist a dev_cfg for the given key, if not,
11868 + then create one and add it to the device list. */
11869 + else if(((p_dev_cfg = p_get_dev_cfg(key)) == NULL) &&
11870 + (((p_dev_cfg = p_create_dev_cfg(key)) == NULL) ||
11871 + p_add_dev_cfg_to_list(&g_device_cfg_list, p_dev_cfg) != 0))
11872 + {
11873 + dbgPrint("Failed to allocate mem or add dev cfg for %s.\n", key);
11874 + }
11875 + /* make sure that we can add this cfg type to the repository */
11876 + else if(p_set_device_cfg_type(p_dev_cfg, cfg_type) == -1)
11877 + {
11878 + dbgPrint("Ignoring \"%s\" for device \"%s\".\n",
11879 + p_get_cfg_type_name_for_en(cfg_type),
11880 + p_dev_cfg->device_name);
11881 + }
11882 + else if((p_dev_inst_data = os_malloc(sizeof(DEV_INSTANCE_CFG_DATA_T)))== NULL)
11883 + {
11884 + dbgPrint("Failed to allocate memory for DEV_INSTANCE_CFG_DATA_T.\n");
11885 + }
11886 + else if((p_dev_inst_data->data = os_malloc(cfg_len) + 1) == NULL)
11887 + {
11888 + dbgPrint("Failed to allocate memory for the config data.\n");
11889 + }
11890 + else
11891 + {
11892 + p_dev_inst_data->next = NULL;
11893 +
11894 + if(cfg_type == en_opt_conf || cfg_type == en_compile)
11895 + psp_config_strcpy(p_dev_inst_data->locale, "dev on chip ");
11896 + else if(cfg_type == en_vlynq)
11897 + psp_config_strcpy(p_dev_inst_data->locale, "dev on vlynq");
11898 + else
11899 + psp_config_strcpy(p_dev_inst_data->locale, "dev locale ?");
11900 +
11901 + psp_config_memcpy(p_dev_inst_data->data, p_cfg_str, cfg_len);
11902 + p_dev_inst_data->data_size = cfg_len;
11903 + *(p_dev_inst_data->data + cfg_len) = '\0';
11904 +
11905 + ret_val = p_add_instance_cfg_data(p_dev_cfg, p_dev_inst_data);
11906 + }
11907 +
11908 + return(ret_val);
11909 +}
11910 +
11911 +/*-------------------------------------------------------------
11912 + * Get the total number of device instances in the repository
11913 + *------------------------------------------------------------*/
11914 +int psp_config_get_num_keys(void)
11915 +{
11916 + return(g_device_cfg_list.count);
11917 +}
11918 +
11919 +
11920 +/*--------------------------------------------------------------------
11921 + * Get the device configuration info from the repository.
11922 + *-------------------------------------------------------------------*/
11923 +int psp_config_get(char *key, int instance, char **cfg_data_out)
11924 +{
11925 + int ret_val = -1;
11926 + DEVICE_CFG_T *p_dev_cfg = NULL;
11927 + *cfg_data_out = NULL;
11928 +
11929 + if(key == NULL && cfg_data_out == NULL)
11930 + {
11931 + dbgPrint("Key has a NULL value.\n");
11932 + }
11933 + else if((p_dev_cfg = p_get_dev_cfg(key)) == NULL)
11934 + {
11935 + dbgPrint("cfg information for %s could not be found.\n", key);
11936 + }
11937 + else if(p_dev_cfg->count)
11938 + {
11939 + DEV_INSTANCE_CFG_DATA_T *p_dev_inst_data =
11940 + p_dev_cfg->dev_inst_list_begin;
11941 + int index = 0;
11942 + for(index = 0;
11943 + index != instance && index < p_dev_cfg->count;
11944 + index++)
11945 + {
11946 + p_dev_inst_data = p_dev_inst_data->next;
11947 + }
11948 +
11949 + if(p_dev_inst_data != NULL && p_dev_inst_data->data != NULL)
11950 + {
11951 + *cfg_data_out = p_dev_inst_data->data;
11952 + ret_val = p_dev_inst_data->data_size;
11953 + }
11954 + }
11955 +
11956 + return (ret_val);
11957 +}
11958 +
11959 +/*----------------------------------------------------------------
11960 + * Returns the number of instances found in the repository for the
11961 + * specified key.
11962 + *---------------------------------------------------------------*/
11963 +int psp_config_get_num_instances(char *key)
11964 +{
11965 + int ret_val = 0;
11966 + DEVICE_CFG_T *p_dev_cfg = NULL;
11967 +
11968 + if(key == NULL)
11969 + {
11970 + dbgPrint("Key has a NULL value.\n");
11971 + }
11972 + else if((p_dev_cfg = p_get_dev_cfg(key)) == NULL)
11973 + {
11974 + dbgPrint("cfg information for %s could not be found.\n", key);
11975 + }
11976 + else
11977 + {
11978 + ret_val = p_dev_cfg->count;
11979 + }
11980 +
11981 + return (ret_val);
11982 +}
11983 +
11984 +/*------------------------------------------------------------------
11985 + * Dump the configuration repository.
11986 + * Caution: DO NOT USE THIS FOR ANY NON NBU specified config format.
11987 + *-----------------------------------------------------------------*/
11988 +void psp_config_print(char *key)
11989 +{
11990 + DEVICE_CFG_T *p_dev_cfg = NULL;
11991 +
11992 + if(key == NULL)
11993 + {
11994 + dbgPrint("Key has a NULL value.\n");
11995 + }
11996 + else if((p_dev_cfg = p_get_dev_cfg(key)) == NULL)
11997 + {
11998 + dbgPrint("cfg information for %s could not be found.\n", key);
11999 + }
12000 + else if(p_dev_cfg && p_dev_cfg->count)
12001 + {
12002 + DEV_INSTANCE_CFG_DATA_T *p_dev_inst_data;
12003 +
12004 + p_dev_inst_data = p_dev_cfg->dev_inst_list_begin;
12005 +
12006 + do
12007 + {
12008 + dbgPrint("%s : %s\n", p_dev_inst_data->locale,
12009 + p_dev_inst_data->data);
12010 + p_dev_inst_data = p_dev_inst_data->next;
12011 +
12012 + } while(p_dev_inst_data);
12013 + }
12014 + else
12015 + {
12016 + dbgPrint("Nothing was found for %s.\n", key);
12017 + }
12018 +}
12019 +
12020 +void dump_device_cfg_pool(void)
12021 +{
12022 + DEVICE_CFG_T *p_dev_cfg = g_device_cfg_list.device_cfg_begin;
12023 +
12024 + if(p_dev_cfg != NULL && g_device_cfg_list.count)
12025 + {
12026 + int index=0;
12027 +
12028 + for(index=0; index < g_device_cfg_list.count; index++)
12029 + {
12030 + psp_config_print(p_dev_cfg->device_name);
12031 + p_dev_cfg = p_dev_cfg->next;
12032 + }
12033 + }
12034 + else
12035 + {
12036 + dbgPrint("repository is empty.\n");
12037 + }
12038 +}
12039 +
12040 +void psp_config_init(void)
12041 +{
12042 + p_init_device_cfg_list();
12043 +}
12044 +
12045 +void psp_config_cleanup()
12046 +{
12047 + int dev_count = 0;
12048 + int inst_count = 0;
12049 + DEVICE_CFG_T *p = g_device_cfg_list.device_cfg_begin;
12050 + DEV_INSTANCE_CFG_DATA_T *q = NULL;
12051 +
12052 + for(dev_count = 0; dev_count < g_device_cfg_list.count; dev_count++)
12053 + {
12054 + DEVICE_CFG_T *p_temp = NULL;
12055 + if(p) q = p->dev_inst_list_begin;
12056 +
12057 + for(inst_count = 0; inst_count < p->count && q != NULL; inst_count++)
12058 + {
12059 + DEV_INSTANCE_CFG_DATA_T *q_temp = q;
12060 + q_temp = q->next;
12061 + kfree(q->data);
12062 + kfree(q);
12063 + q = q_temp;
12064 + }
12065 +
12066 + p_temp = p->next;
12067 + kfree(p);
12068 + p = p_temp;
12069 + }
12070 +}
12071 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/psp_config_mgr.h linux-2.4.30/drivers/net/avalanche_cpmac/psp_config_mgr.h
12072 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/psp_config_mgr.h 1970-01-01 02:00:00.000000000 +0200
12073 +++ linux-2.4.30/drivers/net/avalanche_cpmac/psp_config_mgr.h 2005-04-15 05:10:41.000000000 +0200
12074 @@ -0,0 +1,110 @@
12075 +/******************************************************************************
12076 + * FILE PURPOSE: PSP Config Manager Header
12077 + ******************************************************************************
12078 + * FILE NAME: psp_config_mgr.h
12079 + *
12080 + * DESCRIPTION: Storing and retrieving the configuration based on key
12081 + * A set of APIs to be used by one and sundry (including drivers and enumerator) to build
12082 + * and read cfg information of the devices for an avalanche SOC.
12083 + *
12084 + * This set of APIs isolates the configuration management from the world and provides simple
12085 + * access convinience.
12086 + *
12087 + * Device in this set refers to the peripherals that can be found on the SOC or on VLYNQ.
12088 + * The configuration is stored in the form of string and drivers can use these APIs to get
12089 + * a particular parameter value.
12090 + *
12091 + * The memory allocation for the pass back parameters is done by the caller.
12092 + *
12093 + * 0 is returned for SUCCESS or TRUE.
12094 + * -1 is returned for FAILURE or FALSE.
12095 + *
12096 + * REVISION HISTORY:
12097 + * 27 Nov 02 - PSP TII
12098 + *
12099 + * (C) Copyright 2002, Texas Instruments, Inc
12100 + *******************************************************************************/
12101 +
12102 +#ifndef __PSP_CONFIG_MGR_H__
12103 +#define __PSP_CONFIG_MGR_H__
12104 +
12105 +typedef enum cfg_type
12106 +{
12107 + en_raw = 0,
12108 + en_compile,
12109 + en_opt_conf,
12110 + en_vlynq
12111 +} CFG_TYPE_T;
12112 +
12113 +/* Build psp configuration */
12114 +void build_psp_config(void);
12115 +
12116 +/********************************************************
12117 + * Access Operations.
12118 + ********************************************************/
12119 +
12120 +/*-------------------------------------------------------------------------
12121 + initializes the configuration repository.
12122 + -------------------------------------------------------------------------*/
12123 +void psp_config_init(void);
12124 +
12125 +/*--------------------------------------------------------------------------
12126 + Adds the configuration information into the repository. 'key' is required
12127 + to be NULL terminated string. 'cfg_ptr' points to the configuration data.
12128 + 'cfg_len' is the length of the data pointed to by 'cfg_ptr' in bytes.
12129 + 'cfg_type' indicates the type of config information.
12130 +
12131 + psp_config_mgr copies the 'cfg_len' bytes of data pointed to by 'cfg_ptr'
12132 + into its internal repository.
12133 +
12134 + Returns: 0 on success, -1 on failure.
12135 + -------------------------------------------------------------------------*/
12136 +int psp_config_add(char *key, void *cfg_ptr,
12137 + unsigned int cfg_len, CFG_TYPE_T cfg_type);
12138 +
12139 +
12140 +/* --------------------------------------------------------------------------
12141 + Passes back, in "*cfg_out_val" a pointer to the config data in the repository
12142 + for the specified 'key' and 'instance'. It returns the size of the config
12143 + info
12144 +
12145 + psp_config_mgr passes back a pointer in '*cfg_out_val' which refers to
12146 + some location in its internal repository. It is strongly recommended that
12147 + if the user intends to modify the contents of the config info for reasons
12148 + whatsoever, then, user should allocate memory of size returned by this
12149 + routine and copy the contents from '*cfg_out_val'.
12150 +
12151 + Any, modification carried out on the repository would lead to un-expected
12152 + results.
12153 +
12154 + Returns: 0 or more for the size of config info, -1 on error.
12155 + --------------------------------------------------------------------------*/
12156 +int psp_config_get(char *key, int instance, char **cfg_out_val);
12157 +
12158 +
12159 +/*--------------------------------------------------------------------------
12160 + Get the number of keys that have been added in the repository so far.
12161 +
12162 + Returns: 0 or more for the num of keys, -1 on error.
12163 + -------------------------------------------------------------------------*/
12164 +int psp_config_get_num_keys(void);
12165 +
12166 +
12167 +/*--------------------------------------------------------------------------
12168 + Get the number of instances that are present in the repository for the
12169 + given 'key'.
12170 +
12171 + Returns: 0 or more for the num of instances, -1 on error.
12172 + -------------------------------------------------------------------------*/
12173 +int psp_config_get_num_instances(char *key);
12174 +
12175 +
12176 +/*--------------------------------------------------------------------------
12177 + Prints the config data for all instances associated with the specified
12178 + 'key'.
12179 + -------------------------------------------------------------------------*/
12180 +void psp_config_print(char *key);
12181 +
12182 +void dump_device_cfg_pool(void);
12183 +
12184 +#endif /* __PSP_CONFIG_MGR_H__ */
12185 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/psp_config_parse.c linux-2.4.30/drivers/net/avalanche_cpmac/psp_config_parse.c
12186 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/psp_config_parse.c 1970-01-01 02:00:00.000000000 +0200
12187 +++ linux-2.4.30/drivers/net/avalanche_cpmac/psp_config_parse.c 2005-07-08 22:11:19.180858923 +0200
12188 @@ -0,0 +1,363 @@
12189 +/******************************************************************************
12190 + * FILE PURPOSE: PSP Config Manager - Parse API Source
12191 + ******************************************************************************
12192 + * FILE NAME: psp_config_parse.c
12193 + *
12194 + * DESCRIPTION: These APIs should be used only for scanvenging parameters which
12195 + * are stored in the following format.
12196 + *
12197 + * str[] = "module(id=[module], k1=v1, k2=[k3=v3, k4=v4], k5=v5)"
12198 + *
12199 + * REVISION HISTORY:
12200 + * 27 Nov 02 - PSP TII
12201 + *
12202 + * (C) Copyright 2002, Texas Instruments, Inc
12203 + *******************************************************************************/
12204 +
12205 +//#include <stdio.h>
12206 +//#include <ctype.h>
12207 +#include <asm/ar7/hal/haltypes.h>
12208 +
12209 +/*--------------------------------------------------
12210 + * MACROS.
12211 + *-------------------------------------------------*/
12212 +#define my_isdigit(c) (c >= '0' && c <= '9')
12213 +#define my_isoct(c) (c >= '0' && c <= '7')
12214 +#define my_xtod(c) ((c) <= '9' ? (c) - '0' : (c) - 'a' + 10)
12215 +#define my_ifupper(c) (c >= 'A' && c <= 'F')
12216 +#define XTOD(c) ((c) - 'A' + 10)
12217 +#define my_ishex(c) ((c >= 'a' && c <='f') || (c >= 'A' && c<='F') || my_isdigit(c) )
12218 +
12219 +/*---------------------------------------------------
12220 + * Local Functions.
12221 + *--------------------------------------------------*/
12222 +static int p_get_substr_from_str(char *p_in_str, char begin_delimiter,
12223 + char end_delimiter, int pair_flag,
12224 + char **p_out_str);
12225 +static int p_get_u_int_from_str(char *p_in_str, char begin_delimiter,
12226 + char end_delimiter, unsigned long *out_val);
12227 +
12228 +/*---------------------------------------------------
12229 + * Return pointer to first instance of the char.
12230 + *--------------------------------------------------*/
12231 +static char* psp_config_strchr(char *str, char chr)
12232 +{
12233 + while(*str)
12234 + {
12235 + if(*str == chr)
12236 + break;
12237 + str++;
12238 + }
12239 +
12240 + return((*str) ? str : NULL);
12241 +}
12242 +
12243 +/*------------------------------------------------------------------------
12244 + * Convert the string upto delimiter to unsigned long.
12245 + *-----------------------------------------------------------------------*/
12246 +unsigned long my_atoul(char *p, char end_delimiter, unsigned long *out_val)
12247 +{
12248 + unsigned long n;
12249 + int c;
12250 +
12251 + /* check the for null input */
12252 + if (!p)
12253 + return -1;
12254 +
12255 + c = *p;
12256 +
12257 + /* pass through the leading spaces */
12258 + if (!my_isdigit(c))
12259 + {
12260 + while ( c == ' ')
12261 + c = *++p;
12262 +
12263 + }
12264 +
12265 + if (c == '0')
12266 + {
12267 + if(*(p + 1) == 'x' || *(p+1) == 'X' )
12268 + {
12269 + /* string is in hex format */
12270 +
12271 + p += 2;
12272 + c = *p;
12273 +
12274 + if(my_ishex(c))
12275 + {
12276 + if(my_ifupper(c))
12277 + n = XTOD(c);
12278 + else
12279 + n = my_xtod(c);
12280 + }
12281 + else
12282 + return -1; /* invalid hex string format */
12283 +
12284 + while ((c = *++p) && my_ishex(c))
12285 + {
12286 + n *= 16;
12287 + if(my_ifupper(c))
12288 + n += XTOD(c);
12289 + else
12290 + n += my_xtod(c);
12291 + }
12292 + }
12293 + else
12294 + {
12295 + /* string is in octal format */
12296 +
12297 + if( my_isoct(c) )
12298 + n = c - '0';
12299 + else
12300 + return -1; /* invalid octal string format */
12301 +
12302 + while ((c = *++p) && my_isoct(c))
12303 + {
12304 + n *= 8;
12305 + n += c - '0';
12306 + }
12307 + }
12308 +
12309 + }
12310 + else
12311 + {
12312 + /* string is in decimal format */
12313 +
12314 + if( my_isdigit(c) )
12315 + n = c - '0';
12316 + else
12317 + return -1; /* invalid decimal string format */
12318 +
12319 + while ((c = *++p) && my_isdigit(c))
12320 + {
12321 + n *= 10;
12322 + n += c - '0';
12323 + }
12324 + }
12325 +
12326 + /* move through the trailing spaces */
12327 + while(*p == ' ')
12328 + p++;
12329 +
12330 + if(*p == end_delimiter)
12331 + {
12332 + *out_val = n;
12333 + return 0;
12334 + }
12335 +
12336 + else
12337 + return -1; /* invalid string format */
12338 +}
12339 +
12340 +/*---------------------------------------------------------------------------------
12341 + * Gets the substring de-limited by the 'begin_delimiter' and 'end_delimiter'.
12342 + * and returns the size of the substring.
12343 + *
12344 + * Parses the NULL terminated p_in_str for a character array delimited by
12345 + * begin_delimiter and end_delimiter, passes back the pointer to the character
12346 + * array in ' *p_out_str '. The passed pointer ' *p_out_str ' should point to
12347 + * the location next (byte) to the begin_delimiter. The function routine returns
12348 + * the number of characters excluding the begin_delimiter and end_delimiter,
12349 + * found in the array delimited by the said delimiters.
12350 + *
12351 + * If the pair_flag is set to 1, then, number of begin_delimiter and end_delimiter
12352 + * found in the parsing should match (equal) and this routine passes back the
12353 + * pointer to the character array, starting at a location next (byte) to the
12354 + * first begin_delimiter, inclusive of all intermediate matching delimiter
12355 + * characters found between outer delimiters. If the pair flag is set and if
12356 + * begin_delimiter and end_delimiter happens to be same, then error (-1) is
12357 + * returned.
12358 + *
12359 + * Return: 0 or more to indicate the size of the substring, -1 on error.
12360 + *-------------------------------------------------------------------------------*/
12361 +int p_get_substr_from_str(char *p_in_str, char begin_delimiter,
12362 + char end_delimiter, int pair_flag,
12363 + char **p_out_str)
12364 +{
12365 + int cnt,pos;
12366 +
12367 + if(pair_flag && begin_delimiter == end_delimiter)
12368 + return -1;
12369 +
12370 + if((p_in_str = psp_config_strchr(p_in_str, begin_delimiter)) == 0)
12371 + return -1; /* no start delimiter found */
12372 +
12373 + p_in_str++;
12374 + *p_out_str = p_in_str;
12375 +
12376 + for(pos = 0,cnt =1; cnt && p_in_str[pos] ; pos++)
12377 + {
12378 + if(p_in_str[pos] == end_delimiter)
12379 + {
12380 + if(pair_flag == 0)
12381 + return pos;
12382 +
12383 + cnt--;
12384 + }
12385 + else if(p_in_str[pos] == begin_delimiter)
12386 + cnt++;
12387 + else
12388 + ; /* We do nothing */
12389 +
12390 + }
12391 +
12392 + if( cnt == 0)
12393 + return pos - 1;
12394 + else
12395 + return -1; /* no corresponding end delimiter found */
12396 +}
12397 +
12398 +/*--------------------------------------------------------------------------
12399 + * Parses the NULL terminated p_in_str for unsigned long value delimited by
12400 + * begin_delimiter and end_delimiter, passes back the found in ' *out_val '.
12401 + * The function routine returns 0 on success and returns -1 on failure.
12402 + * The first instance of the de-limiter should be accounted for the parsing.
12403 + *
12404 + * The base for unsigned value would 10, octal and hex. The value passed back
12405 + * would be of the base 10. Spaces at the begining of the byte array are valid
12406 + * and should be ingnored in the calculation of the value. Space character in
12407 + * the middle of the byte array or any character other than the valid ones
12408 + * (based on base type) should return error. The octal value begins with '0',
12409 + * the hex value begins with "0x" or "0X", the base value can begin with
12410 + * '1' to '9'.
12411 + *
12412 + * Returns: 0 on success, -1 on failure.
12413 + *-------------------------------------------------------------------------*/
12414 +int p_get_u_int_from_str(char *p_in_str, char begin_delimiter,
12415 + char end_delimiter, unsigned long *out_val)
12416 +{
12417 + char *start;
12418 + unsigned long num;
12419 +
12420 + num = p_get_substr_from_str(p_in_str, begin_delimiter, end_delimiter,
12421 + 0, &start);
12422 +
12423 + if(num == (unsigned long)-1)
12424 + return -1;
12425 +
12426 + return my_atoul(start,end_delimiter,out_val);
12427 +}
12428 +
12429 +/*--------------------------------------------------------------------------
12430 + * Finds the first occurrence of the substring p_find_str in the string
12431 + * p_in_str.
12432 + *-------------------------------------------------------------------------*/
12433 +char *my_strstr(char *p_in_str, const char *p_find_str)
12434 +{
12435 + char *p = (char *)p_find_str;
12436 + char *ret = NULL;
12437 +
12438 + while(*p_in_str)
12439 + {
12440 + if(!(*p))
12441 + return (ret);
12442 + else if(*p_in_str == *p)
12443 + {
12444 + if(!ret) ret = p_in_str;
12445 + p++;
12446 + p_in_str++;
12447 + }
12448 + else if(ret)
12449 + {
12450 + p = (char *)p_find_str;
12451 + p_in_str = ret + 1;
12452 + ret = NULL;
12453 + }
12454 + else
12455 + p_in_str++;
12456 + }
12457 +
12458 + if(*p_in_str != *p) ret = NULL;
12459 +
12460 + return (ret);
12461 +
12462 +}
12463 +
12464 +/*------------------------------------------------------------------------------
12465 + * Gets the value of the config param in the unsigned int format. The value is
12466 + * stored in the following format in the string.
12467 + * str[] = "module(id=[module], k1=v1, k2=[k3=v3, k4=v4], k5=v5)"
12468 + *-----------------------------------------------------------------------------*/
12469 +int psp_config_get_param_uint(char *p_in_str, const char *param, unsigned int *out_val)
12470 +{
12471 + int ret_val = -1;
12472 + char *p_strstr;
12473 +
12474 + if(!p_in_str || !param || !out_val)
12475 + {
12476 + ;
12477 + }
12478 + else if((p_strstr = my_strstr(p_in_str, param)) == NULL)
12479 + {
12480 + ;
12481 + }
12482 + else if(p_get_u_int_from_str(p_strstr, '=', ',', (unsigned long *)out_val) == 0)
12483 + {
12484 + ret_val = 0;
12485 + }
12486 + else if(p_get_u_int_from_str(p_strstr, '=', ']', (unsigned long*)out_val) == 0)
12487 + {
12488 + ret_val = 0;
12489 + }
12490 + else if(p_get_u_int_from_str(p_strstr, '=', ')', (unsigned long*)out_val) == 0)
12491 + {
12492 + ret_val = 0;
12493 + }
12494 + else
12495 + {
12496 + /* we failed */
12497 + }
12498 +
12499 + return (ret_val);
12500 +}
12501 +
12502 +/*------------------------------------------------------------------------------
12503 + * Gets the value of the config param in the Non NULL terminated format. The value
12504 + * is stored in the following format in the string.
12505 + * str[] = "module(id=[module], k1=v1, k2=[k3=v3, k4=v4], k5=v5)"
12506 + *-----------------------------------------------------------------------------*/
12507 +int psp_config_get_param_string(char *p_in_str, const char *param, char **out_val)
12508 +{
12509 + int ret_val = -1;
12510 + char *p_strstr;
12511 +
12512 + if(!p_in_str || !param || !(out_val))
12513 + ;
12514 + else if((p_strstr = my_strstr(p_in_str, param)) == NULL)
12515 + {
12516 + ;
12517 + }
12518 + else if((ret_val = p_get_substr_from_str(p_strstr, '[', ']', 1, out_val)) == -1)
12519 + {
12520 + ;
12521 + }
12522 + else
12523 + {
12524 + ; /* we got the value */
12525 + }
12526 +
12527 + return (ret_val);
12528 +}
12529 +
12530 +#ifdef PSP_CONFIG_MGR_DEBUG_TEST
12531 +main()
12532 +{
12533 + unsigned long num =999;
12534 + int ret = 0;
12535 + char *val1 = NULL;
12536 + char val[30];
12537 + char str1[] = "cpmac(id=[cpmac], k0=[a1=[a2=[test], a3=2], k1=100, k2=[k3=300, k4=200], k7=722)";
12538 +
12539 + psp_config_get_param_uint(str1, "k7", &num);
12540 + printf("%u.\n", num);
12541 + ret = psp_config_get_param_string(str1, "a1", &val1);
12542 + if(ret >= 0) { printf("%d.\n", ret); strncpy(val, val1, ret); val[ret] = '\0';}
12543 +
12544 + printf("val = \"%s\", and size = %d \n", val, ret);
12545 +
12546 + if(val[ret]) ; else printf("jeee.\n");
12547 +}
12548 +#endif /* PSP_CONFIG_MGR_DEBUG_TEST */
12549 +
12550 +
12551 +
12552 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/psp_config_parse.h linux-2.4.30/drivers/net/avalanche_cpmac/psp_config_parse.h
12553 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/psp_config_parse.h 1970-01-01 02:00:00.000000000 +0200
12554 +++ linux-2.4.30/drivers/net/avalanche_cpmac/psp_config_parse.h 2005-07-08 22:07:07.685855972 +0200
12555 @@ -0,0 +1,32 @@
12556 +/******************************************************************************
12557 + * FILE PURPOSE: PSP Config Manager - Parse API Header
12558 + ******************************************************************************
12559 + * FILE NAME: psp_config_parse.h
12560 + *
12561 + * DESCRIPTION: Parsing for params from string available in the NBU format.
12562 + * These APIs should be used only for scanvenging parameters which
12563 + * are stored in the following format.
12564 + *
12565 + * str[] = "module(id=[module], k1=v1, k2=[k3=v3, k4=v4], k5=v5)"
12566 + *
12567 + * REVISION HISTORY:
12568 + * 27 Nov 02 - PSP TII
12569 + *
12570 + * (C) Copyright 2002, Texas Instruments, Inc
12571 + *******************************************************************************/
12572 +
12573 +#ifndef __PSP_CONFIG_PARSER_H__
12574 +#define __PSP_CONFIG_PARSER_H__
12575 +
12576 +/*------------------------------------------------------------------
12577 + * These APIs should be used only for scanvenging parameters which
12578 + * are stored in the following format.
12579 + *
12580 + * str[] = "module(id=[module], k1=v1, k2=[k3=v3, k4=v4], k5=v5)"
12581 + *-----------------------------------------------------------------*/
12582 +int psp_config_get_param_uint(char *p_in_str, const char *param,
12583 + unsigned int *out_val);
12584 +int psp_config_get_param_string(char *p_in_str, const char *param,
12585 + char **out_val);
12586 +
12587 +#endif /* __PSP_CONFIG_PARSER_H__ */
12588 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/psp_config_util.c linux-2.4.30/drivers/net/avalanche_cpmac/psp_config_util.c
12589 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/psp_config_util.c 1970-01-01 02:00:00.000000000 +0200
12590 +++ linux-2.4.30/drivers/net/avalanche_cpmac/psp_config_util.c 2005-07-08 22:11:56.567831651 +0200
12591 @@ -0,0 +1,106 @@
12592 +/******************************************************************************
12593 + * FILE PURPOSE: PSP Config Manager - Utilities API Source
12594 + ******************************************************************************
12595 + * FILE NAME: psp_config_util.c
12596 + *
12597 + * DESCRIPTION: These APIs provide the standard "C" string interfaces.
12598 + * Provided here to reduce dependencies on the standard libraries
12599 + * and for cases where psp_config would required to run before
12600 + * the whole system is loaded or outside the scope of the OS.
12601 + *
12602 + * REVISION HISTORY:
12603 + * 27 Nov 02 - PSP TII
12604 + *
12605 + * (C) Copyright 2002, Texas Instruments, Inc
12606 + *******************************************************************************/
12607 +
12608 +//#include <stdio.h>
12609 +#include "psp_config_util.h"
12610 +#include <asm/ar7/hal/haltypes.h>
12611 +
12612 +/*---------------------------------------------
12613 + * strlen.
12614 + *-------------------------------------------*/
12615 +int psp_config_strlen(char *p)
12616 +{
12617 + char *p_orig = p;
12618 + while(*p)
12619 + p++;
12620 + return(p - p_orig);
12621 +}
12622 +
12623 +/*--------------------------------------------
12624 + * strcmp.
12625 + *-------------------------------------------*/
12626 +int psp_config_strcmp(char *s1, char *s2)
12627 +{
12628 + while(*s1 && *s2)
12629 + {
12630 + if(*s1 != *s2)
12631 + break;
12632 + s1++;
12633 + s2++;
12634 + }
12635 +
12636 + return(*s1 - *s2);
12637 +}
12638 +
12639 +/*--------------------------------------------
12640 + * strcpy.
12641 + *------------------------------------------*/
12642 +char* psp_config_strcpy(char *dest, char *src)
12643 +{
12644 + char *dest_orig = dest;
12645 +
12646 + while(*src)
12647 + {
12648 + *dest++ = *src++;
12649 + }
12650 +
12651 + *dest = '\0';
12652 +
12653 + return(dest_orig);
12654 +}
12655 +
12656 +/*----------------------------------------------
12657 + * psp_config_memcpy.
12658 + *--------------------------------------------*/
12659 +void* psp_config_memcpy(void* dest, void* src, unsigned int n)
12660 +{
12661 + void *dest_orig = dest;
12662 +
12663 + while(n)
12664 + {
12665 + *(char *)dest++ = *(char *)src++;
12666 + n--;
12667 + }
12668 +
12669 + return (dest_orig);
12670 +}
12671 +
12672 +/*---------------------------------------------------
12673 + * Return pointer to first instance of the char.
12674 + *--------------------------------------------------*/
12675 +char* psp_config_strchr(char *str, char chr)
12676 +{
12677 + while(*str)
12678 + {
12679 + if(*str == chr)
12680 + break;
12681 + str++;
12682 + }
12683 +
12684 + return((*str) ? str : NULL);
12685 +}
12686 +
12687 +#ifdef PSP_CONFIG_MGR_DEBUG_TEST
12688 +
12689 +int main( )
12690 +{
12691 + char s[] = "hello ";
12692 + printf("%d.\n", psp_config_strlen("hello\n"));
12693 + printf("%d.\n", psp_config_strcmp("hells", "hellq"));
12694 + printf("%s %s.\n", psp_config_strcpy(s + 6, "test1"), s);
12695 +}
12696 +
12697 +#endif /* PSP_CONFIG_MGR_DEBUG_TEST */
12698 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/psp_config_util.h linux-2.4.30/drivers/net/avalanche_cpmac/psp_config_util.h
12699 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/psp_config_util.h 1970-01-01 02:00:00.000000000 +0200
12700 +++ linux-2.4.30/drivers/net/avalanche_cpmac/psp_config_util.h 2005-04-15 05:10:41.000000000 +0200
12701 @@ -0,0 +1,26 @@
12702 +/******************************************************************************
12703 + * FILE PURPOSE: PSP Config Manager - Utilities API Header
12704 + ******************************************************************************
12705 + * FILE NAME: psp_config_util.h
12706 + *
12707 + * DESCRIPTION: These APIs provide the standard "C" string interfaces.
12708 + * Provided here to reduce dependencies on the standard libraries
12709 + * and for cases where psp_config would required to run before
12710 + * the whole system is loaded or outside the scope of the OS.
12711 + *
12712 + * REVISION HISTORY:
12713 + * 27 Nov 02 - PSP TII
12714 + *
12715 + * (C) Copyright 2002, Texas Instruments, Inc
12716 + *******************************************************************************/
12717 +
12718 +#ifndef __PSP_CONFIG_UTIL_H__
12719 +#define __PSP_CONFIG_UTIL_H__
12720 +
12721 +extern int psp_config_strlen(char*);
12722 +extern int psp_config_strcmp(char*, char*);
12723 +extern char* psp_config_strcpy(char*, char*);
12724 +extern void* psp_config_memcpy(void*, void*, unsigned int n);
12725 +extern char* psp_config_strchr(char*, char);
12726 +
12727 +#endif /* __PSP_CONFIG_UTIL_H__ */
12728 diff -ruN linux-2.4.30.orig/drivers/net/avalanche_cpmac/readme.txt linux-2.4.30/drivers/net/avalanche_cpmac/readme.txt
12729 --- linux-2.4.30.orig/drivers/net/avalanche_cpmac/readme.txt 1970-01-01 02:00:00.000000000 +0200
12730 +++ linux-2.4.30/drivers/net/avalanche_cpmac/readme.txt 2005-04-15 05:10:41.000000000 +0200
12731 @@ -0,0 +1,545 @@
12732 +23 August 2004 CPMAC 1.7.8 (NSP Performance Team Release)
12733 +
12734 +CC Labels: REL_20040823_HALdallas_cpmac_01.07.08
12735 +
12736 +New features: Key "MacAddr" can now be used to set the Mac Address after Open.
12737 +
12738 + unsigned char MacAddr[6];
12739 +
12740 + // Set Mac Address to "00.B0.D0.10.80.C1"
12741 + MacAddr[0] = 0x00;
12742 + MacAddr[1] = 0xB0;
12743 + MacAddr[2] = 0xD0;
12744 + MacAddr[3] = 0x10;
12745 + MacAddr[4] = 0x80;
12746 + MacAddr[5] = 0xC1;
12747 +
12748 + HalFunc->Control(HalDev, "MacAddr", hcSet, &MacAddr);
12749 +
12750 +Bug fixes: in Send(), Threshold is not checked if Tx Ints are re-enabled.
12751 +
12752 +Modules affected: hcpmac.c, hcpmac.h, cppi_cpmac.c
12753 +
12754 +22 June 2004 CPMAC 1.7.6 (NSP Performance Team Release)
12755 +
12756 +CC Labels: REL_20040622_HALdallas_cpmac_01.07.06
12757 +
12758 +New features: Key "TxIntDisable" used to disable Tx Interrupts. If it is set, then Tx Interrupts will be processed on Send() controlled by Tx ServiceMax Setting.
12759 +
12760 + int On = 1;
12761 + HalFunc->Control(HalDev, "TxIntDisable", "Set", &On);
12762 +
12763 +Bug fixes: NTR
12764 +
12765 +10 June 2004 CPMAC 1.7.5 (external release)
12766 +
12767 +CC Labels: REL_20040610_HALdallas_cpmac_01.07.05
12768 +
12769 +New features: NTR
12770 +
12771 +Bug fixes: Fixed an issue with calculation for the multicast hash.
12772 +
12773 +27 May 2004 CPSAR 1.7.4, CPMAC 1.7.4 (external release)
12774 +
12775 +CC Labels: REL_20040527_HALdallas_cpsar_01.07.04
12776 + REL_20040527_HALdallas_cpmac_01.07.04
12777 +
12778 +New features: NTR
12779 +
12780 +Bug fixes: A flaw was fixed in the critical sectioning of the CPPI file, affecting both
12781 + the MAC and the SAR releases. This flaw was detected on Titan PSP 4.7 BFT2.
12782 +
12783 +05 May 2004 CPSAR 1.7.3, CPMAC 1.7.3 (external release)
12784 +
12785 +CC Labels: REL_20040505_HALdallas_cpsar_01.07.03
12786 + REL_20040505_HALdallas_cpmac_01.07.03
12787 +
12788 +New features: NTR
12789 +
12790 +Bug fixes: 1) Firmware has been updated to fix a problem with Host OAM mode operation.
12791 + 2) Cache macros have been fixed.
12792 +
12793 +Notes: This release contains all performance enhancements currently available for CPHAL 1.x.
12794 +
12795 +19 April 2004 CPSAR 1.7.2, CPMAC 1.7.2 (external release)
12796 +
12797 +CC Labels: REL_20040419_HALdallas_cpsar_01.07.02
12798 + REL_20040419_HALdallas_cpmac_01.07.02
12799 +
12800 +New features: NTR
12801 +
12802 +Bug fixes: Fixes merge problem in 1.7.1.
12803 +
12804 +Notes: This is a branch release which contains only a subset of the performance improvements.
12805 + The remaining performance improvements are stiill being qualified at this time.
12806 +
12807 +1 April 2004 CPSAR 1.7.1, CPMAC 1.7.1 (external release)
12808 +
12809 +NOTICE: DO NOT USE 1.7.1. It has a known problem (see 1.7.2 notes)
12810 +
12811 +CC Labels: REL_20040401_HALdallas_cpsar_01.07.01
12812 + REL_20040401_HALdallas_cpmac_01.07.01
12813 +
12814 +New features: Performance improvement in CPPI layer, affecting both CPSAR and CPMAC.
12815 +
12816 +Bug fixes: NTR
12817 +
12818 +17 Februrary 2004 CPSAR 1.7.0 (external release)
12819 +
12820 +CC Labels: REL_20040217_HALdallas_cpsar_01.07.00
12821 +
12822 +New features: Added support for "TxFlush" feature. This allows the upper
12823 + layer to flush all or part of a given Tx queue for a given
12824 + channel. This is to be used during call setup for a voice
12825 + connection.
12826 +
12827 +30 January 2004 CPMAC 1.7.0 (external release)
12828 +
12829 +CC Labels: REL_20040130_HALdallas_cpmac_01.07.00
12830 +
12831 +Bug fixes: CPMDIO - When in manual negotiate mode and linked, dropping link would move into NWAY state rather than manual state.
12832 + CPMDIO - Extraneous debug message corrected
12833 +New features: CPMDIO - Support for AutoMdix usage added.
12834 +
12835 +25 September 2003 CPSAR 1.6.6 (external release)
12836 +
12837 +CC Labels: REL_20030925_HALdallas_cpsar_01.06.06
12838 +
12839 +Bug fixes: PDSP firmware has been updated to fix the OAM padding problem. It previously
12840 + wrote pad bytes into a reserved field of the OAM cell. There is a small
12841 + change to the CPSAR configuration code which corresponds to the PDSP spec
12842 + change.
12843 +
12844 +New features: NTR
12845 +
12846 +09 September 2003 CPMAC 1.6.6 (external release)
12847 +
12848 +CC Labels: REL_20030909_HALdallas_cpmac_01.06.06
12849 +
12850 +Bug fixes: CPMAC : When _CPMDIO_NOPHY is set, Cpmac COntrol is set to Full Duplex
12851 + Bridge loopback test does not show a problem using 1.6.5 if packet rate is
12852 + below 50,000 pbs. Now testing with a 100% send from Ixia.
12853 +
12854 +New features: NTR
12855 +
12856 +05 August 2003 CPHAL 1.6.5 (external release)
12857 +
12858 +CC Labels: REL_20030805_HALdallas_cpmac_01.06.05
12859 +
12860 +Bug fixes: NTR
12861 +
12862 +New features: CPMAC : Added support for CPMAC modules that do not have a Phy connected.
12863 + The CPMAC is informed of this by the MdioConnect option
12864 + _CPMDIO_NOPHY. This is the only driver change needed to
12865 + receive and transmit packets through the Marvel switch.
12866 + Note In this mode Link status will reported linked at 100/FD to
12867 + PhyNum 0xFFFFFFFF.
12868 +
12869 + ALL: Cleaned up some Vlynq support logic.
12870 +
12871 +16 July 2003 CPSAR 1.6.3 (external release), no CPMAC release
12872 +
12873 +CC Labels: REL_20030716_HALdallas_cpsar_01.06.03
12874 +
12875 +Bug fixes: 1) Changed default value of CPCS_UU from 0x5aa5 to 0. The old default value caused
12876 + problems with Cisco routers.
12877 +
12878 +New features: NTR
12879 +
12880 +Known issues not addressed in this release: NTR.
12881 +
12882 +01 July 2003 CPHAL 1.6.2 (external release)
12883 +
12884 +CC Labels: REL_20030701_HALdallas_cpmac_01.06.02
12885 + REL_20030701_HALdallas_cpsar_01.06.02
12886 +
12887 +Bug fixes: 1) A previous firmware upgrade caused firmware OAM loopback cells to only work on every other
12888 + command. This has been fixed in the new firmware version (0.47).
12889 + 2) Problem with PTI values changing on transparent mode packets has been resolved.
12890 + 3) Previously, successful firmware OAM loopback cells waited 5 seconds before notifying the
12891 + OS of success, rather that notifying immediately. This has been resolved in firmware.
12892 + 4) PITS #148 (MAC and SAR), #149 (MAC) have been fixed.
12893 +
12894 +New features: 1) AAL5 HAL now capable of receiving unknown VCI/VPI cells on a single transparent channel.
12895 + See updated HAL document (AAL5 appendix) for implementation details.
12896 + 2) AAL5 HAL now allows OS to modify the OAM loopback timeout window. Previously, failed
12897 + OAM loopback attempts timed out after a nominal 5 seconds (based on the SAR frequency
12898 + provided by the OS). Now, the default is 5 seconds, but the OS may change the
12899 + value via halControl() to any integer number of milliseconds. See updated HAL document
12900 + (AAL5 appendix) for implementation details.
12901 + 3) MAC (cpmdio): added loopback to Istate. Used for debug.
12902 +
12903 +Known issues not addressed in this release: NTR.
12904 +
12905 +09 June 2003 CPSAR 1.6.1 (external release), CPMAC 1.6.1 (internal release - no functional change)
12906 +
12907 +Note: This is the same set of fixes being applied to 1.6.0 that were applied to 1.5.3. The only difference
12908 + between 1.6.1 and 1.5.4 is that 1.6.1 has the TurboDSL fix.
12909 +
12910 +CC Labels: REL_20030609_HALdallas_cpmac_01.06.01
12911 + REL_20030609_HALdallas_cpsar_01.06.01
12912 +
12913 +Bug fixes: 1) Bug in OamLoopbackConfig fixed.
12914 + 2) New firmware version (.43) to fix Westell issue of dropped downstream packets in
12915 + presence of OAM traffic when operating at or near line rate.
12916 +
12917 +New features: NTR.
12918 +
12919 +09 June 2003 CPSAR 1.5.4 (external release), CPMAC 1.5.4 (internal release - no functional change)
12920 +
12921 +Note: This is a branch release from 1.5.3. This does not contain anything from 1.6.0. The CPMAC is
12922 +only being labeled to keep the release flow consistent.
12923 +
12924 +CC Labels: REL_20030609_HALdallas_cpmac_01.05.04
12925 + REL_20030609_HALdallas_cpsar_01.05.04
12926 +
12927 +Bug fixes: 1) Bug in OamLoopbackConfig fixed.
12928 + 2) New firmware version (.43) to fix Westell issue of dropped downstream packets in
12929 + presence of OAM traffic when operating at or near line rate.
12930 +
12931 +New features: NTR.
12932 +
12933 +30 May 2003 CPSAR 1.6.0 (external release), CPMAC 1.6.0 (internal release - no functional change)
12934 +
12935 +CC Labels: REL_20030530_HALdallas_cpmac_01.06.00
12936 + REL_20030530_HALdallas_cpsar_01.06.00
12937 +
12938 +Bug fixes: 1) TurboDSL issue has been fixed with a software workaround in TxInt. This workaround
12939 + has been verified under Adam2 ONLY at this point. Testing remains to be done on
12940 + Linux and VxWorks.
12941 +
12942 +New features: NTR.
12943 +
12944 +Known issues not addressed in this release: NTR.
12945 +
12946 +30 May 2003 CPSAR 1.5.3 (external release), CPMAC 1.5.3 (internal release - no functional change)
12947 +
12948 +CC Labels: REL_20030530_HALdallas_cpmac_01.05.03
12949 + REL_20030530_HALdallas_cpsar_01.05.03
12950 +
12951 +Bug fixes: NTR.
12952 +
12953 +New features: 1) AAL5 Send() has been modified to accept an ATM Header either in the first
12954 + fragment by itself, or in the first fragment directly in front of payload data.
12955 + The API() does not change.
12956 + 2) Documentation updates throughout, reflected in latest version of CPHAL user's
12957 + guide.
12958 + 3) AAL5 MaxFrags default value is now 46. This is based upon the default AAL5
12959 + RxBufSize of 1518 (MaxFrags = (65568/1518) + 2). IF THE OS CHOOSES A SMALLER
12960 + RxBufSize, IT MUST INCREASE THE VALUE OF MaxFrags ACCORDINGLY. This is done
12961 + via halControl(), prior to Open().
12962 +
12963 +Known issues not addressed in this release:
12964 + 1) The Linux SAR driver is seeing an issue in which it cannot
12965 + reliably send traffic simultaneously on both the high and
12966 + low priority queues of a single AAL5 channel. (TurboDSL)
12967 +
12968 +23 May 2003 CPHAL 1.5.2 (external release)
12969 +
12970 +CC Labels: REL_20030523_HALdallas_cpmac_01.05.02
12971 + REL_20030523_HALdallas_cpsar_01.05.02
12972 +
12973 +Bug fixes: 1) PITS #138: CPMAC flooding issue resolved.
12974 + 2) PITS #142: OS may now set "MaxFrags" via Control(). This controls the
12975 + maximum number of fragments expected by the CPHAL. The default value is 2 for
12976 + CPMAC and 1028 for AAL5. If the OS chooses a RxBufSize that will cause more
12977 + fragments than the defaults, the OS must set "MaxFrags" to a correct value
12978 + ((maximum packet length / RxBufSize) + 2).
12979 + 3) PITS #143: Fixed.
12980 + 4) Firmware OAM bug fixed. (new firmware release in this version)
12981 +
12982 +New features: NTR.
12983 +
12984 +Known issues not addressed in this release:
12985 + 1) The Linux SAR driver is seeing an issue in which it cannot
12986 + reliably send traffic simultaneously on both the high and
12987 + low priority queues of a single AAL5 channel. (TurboDSL)
12988 +
12989 +14 May 2003 CPHAL 1.5.1 (external release)
12990 +
12991 +CC Labels: REL_20030514_HALdallas_cpmac_01.05.01
12992 + REL_20030514_HALdallas_cpsar_01.05.01
12993 +
12994 +Bug fixes: 1) PITS 132 - (CPMAC) Frames < 60 bytes and split into
12995 + multi-fragments.
12996 + 2) BCIL MR PSP00000353 - (CPMAC) PhyDev not free'd on halClose()
12997 + 3) PITS 113 - OsSetup bug in ChannelSetup fixed.
12998 + 4) Fixed AAL5 to check return values of InitTcb/InitRcb.
12999 + 5) Fixed Shutdown to properly free resources in the case of a Close
13000 + mode 1 followed by Shutdown. Previously, buffer and descriptor
13001 + resources were left unfreed in this case.
13002 +
13003 +New features: 1) AAL5 Send() modified to be capable of accepting ATM header as first four
13004 + bytes of first fragment. This allows the OS to "override" the
13005 + default ATM header which is constructed from preconfigured channel
13006 + parameters.
13007 + 2) AAL5 Receive() modified to be capable of passing the received ATM header (4 bytes, no HEC)
13008 + in the first fragment (by itself). It also passes up the OS an indication
13009 + of what the received packet type was. For Host OAM and transparent mode
13010 + packets, the ATM header is passed in this manner, and for other types of packets
13011 + (AAL5, NULL AAL) no ATM header is passed currently.
13012 +
13013 +Known issues not addressed in this release:
13014 + 1) The Linux SAR driver is seeing an issue in which it cannot
13015 + reliably send traffic simultaneously on both the high and
13016 + low priority queues of a single AAL5 channel.
13017 +
13018 +30 April 2003 CPHAL 1.5.0 (external release)
13019 +
13020 +CC Labels: REL_20030430_HALdallas_cpmac_01.05.00
13021 + REL_20030430_HALdallas_cpsar_01.05.00
13022 +
13023 +Bug fixes: 1) Fixed AAL5 bug that rendered the low priority queue
13024 + unusable.
13025 + 2) Fixed a bug in AAL5's Oam Rate calculations.
13026 + 3) Fixed use of "DeviceCPID" key in AAL5's halControl().
13027 + 4) Fixed RxReturn logic in HAL. The HAL now can handle
13028 + failing MallocRxBuffer calls when multiple fragments
13029 + are being used.
13030 +
13031 +New features: 1) AAL5 Stats now available on a per queue basis.
13032 + 2) AAL5 adds two new keys to halControl() for "Set" actions:
13033 + RxVc_OamCh and RxVp_OamCh.
13034 + 3) Shutdown() has been modified for both AAL5 and CPMAC to
13035 + call Close() if the module is still in the Open state.
13036 + 4) CPMAC adds the following access keys to halControl():
13037 + hcPhyAccess,hcPhyNum,hcCpmacBase,hcSize,and hcCpmacSize.
13038 + 5) CPHAL no longer requests an extra 15 bytes on data buffer
13039 + mallocs.
13040 +
13041 +Known issues not addressed in this release:
13042 + 1) The Linux SAR driver is seeing an issue in which it cannot
13043 + reliably send traffic simultaneously on both the high and
13044 + low priority queues of a single AAL5 channel.
13045 +
13046 +21 April 2003 CPHAL 1.4.1 (external release)
13047 +
13048 +CC Labels: REL_20030421_HALdallas_cpmac_01.04.01
13049 + REL_20030421_HALdallas_cpsar_01.04.01
13050 +
13051 +Bug fixes: 1) Fixed OAM logic in SAR portion of CPHAL.
13052 +
13053 +New features: 1) OAM loopback counters exposed through halControl.
13054 + 2) Host OAM Send() can now use a single channel to send
13055 + OAM cells on unlimited number of VP's/VC's.
13056 + 3) CPHAL now requests "SarFreq" through osControl.
13057 + 4) CPHAL now calculates all OAM function rates based on
13058 + "SarFreq"; function OamRateConfig removed for API.
13059 + 5) New OAM function OamLoopbackConfig, used for configuring
13060 + loopback functions in firmware OAM mode.
13061 +
13062 +Known issues not addressed in this release: Bug fix 1) in release 1.4
13063 + (see below) does not work properly for multiple fragments.
13064 +
13065 +10 April 2003 CPHAL 1.4 (external release)
13066 +
13067 +CC Labels: REL_20030410_HALdallas_cpmac_01.04.00
13068 + REL_20030410_HALdallas_cpsar_01.04.00
13069 +
13070 +This release is for SAR and MAC.
13071 +
13072 + Bug fixes: 1) Implemented logic in HAL to re-request buffer mallocs
13073 + in the case of MallocRxBuffer failing. The HAL now maintains
13074 + a NeedsBuffer queue of all RCB's that are without buffers.
13075 + On interrupts, or on Send(), the HAL checks to see if any
13076 + RCB's are on the queue, and if so, calls MallocRxBuffer
13077 + to attempt to get a new buffer and return the RCB to
13078 + circulation.
13079 + 2) SAR now properly returns all error codes from halOpen and
13080 + halChannelSetup.
13081 +
13082 + New features: NTR
13083 +
13084 + Known issues not addressed in this release: NTR
13085 +
13086 +08 April 2003 CPHAL 1.3.1 (internal release - SAR only)
13087 +
13088 + CC Labels: REL_20030408_HALdallas_cpsar_01.03.01
13089 +
13090 + This is a SAR only release. The current CPMAC release is still 1.3.
13091 +
13092 + Bug fixes: 1) PDSP State RAM / Scratchpad RAM is now completely cleared after reset.
13093 + This resolves a stability issue.
13094 +
13095 + New features: 1) OamMode is now a parameter in halControl(). Both "Set" and "Get"
13096 + actions are available. The value may be "0" (Host OAM), or "1"
13097 + (Firmware OAM).
13098 +
13099 + Known issues not addressed in this release:
13100 + 1) Appropriate action for HAL in the case of MallocRxBuffer failing. We
13101 + are investigating whether the HAL should implement a needs buffer
13102 + queue.
13103 +
13104 +04 April 2003 CPHAL 1.3 (external release)
13105 +
13106 + CC Labels: REL_20030404_HALdallas_cpmac_01.03.00
13107 + REL_20030404_HALdallas_cpsar_01.03.00
13108 + REL_20030404_HALdallas_cpaal5_01.03.00
13109 + REL_20030404_HALdallas_cpaal2_01.03.00
13110 +
13111 + This release requires no changes for the ethernet end driver. The changes necessary
13112 + for the sar driver (firmware file name changes) have already been implemented.
13113 +
13114 + Bug fixes: 1) RxReturn now returns an error if MallocRxBuffer fails. On RxReturn error, the driver should
13115 + call RxReturn again at a later time (when the malloc may succeed) in order for the CPHAL
13116 + to maintain a full complement of Rx buffers. We recommend holding off making this driver
13117 + change until we verify that this condition occurs.
13118 +
13119 + New features: 1) Removed benign compiler warnings.
13120 + 2) PITS 122: http://www.nbu.sc.ti.com/cgi-bin/pits/redisplay_archive?product=cphal_dev&report=122
13121 + 3) Cpsar label (above) now is applied to everything
13122 + beneath /cpsar.
13123 + 4) PITS 14: http://www.nbu.sc.ti.com/cgi-bin/pits/redisplay_archive?product=cphal_dev&report=14
13124 + Transferred to MR PSP 00000089.
13125 + 5) PITS 120: http://www.nbu.sc.ti.com/cgi-bin/pits/redisplay_archive?product=cphal_dev&report=120
13126 +
13127 + Known issues not addressed in this release:
13128 + 1) PITS 102 (as relating to OamMode configuration):
13129 + http://www.nbu.sc.ti.com/cgi-bin/pits/redisplay_archive?product=cphal_dev&report=102
13130 + Future release will make OamMode configurable
13131 + through halControl(), not on per channel basis.
13132 +
13133 +20 March 2003 CPHAL 1.2.1 (internal release)
13134 +
13135 + CC Labels: REL_20030320_HALdallas_cpmac_01.02.01
13136 + REL_20030320_HALdallas_cpsar_01.02.01
13137 + REL_20030320_HALdallas_cpaal5_01.02.01
13138 + REL_20030320_HALdallas_cpaal2_01.02.01
13139 +
13140 + Bug fixes: 1. Fixed modification of buffer pointer following
13141 + MallocRxBuffer in cppi.c.
13142 + 2. Removed extra firmware files from /cpsar.
13143 +
13144 + New features: NTR.
13145 +
13146 + Known issues not addressed in this release: NTR.
13147 +
13148 +07 March 2003 CPHAL 1.2 (external release)
13149 +
13150 + CPMAC/CPSAR feature complete release. SAR added
13151 + several features including full OAM support and various
13152 + other features and bug fixes to address PITS 99-106, and
13153 + 114. CPMAC cleaned up details raised by India PSP
13154 + team.
13155 +
13156 +29 January 2003 CPHAL RC 3.01a (external release)
13157 +
13158 + Corrects non-static functions to be static in cppi.c.
13159 +
13160 +09 Janurary 2003 CPHAL RC 3.01 (external release)
13161 +
13162 + PITS 88: Fixed MDIO re-connection problem (hcpmac.c)
13163 + PITS 90: Corrected Rx Buffer Pointer modification (cppi.c)
13164 +
13165 + Corrected error in cpremap.c
13166 +
13167 +20 December 2002 CPHAL RC 3 (external release)
13168 +
13169 + Statistics support via halControl(). See Appendix A of guide.
13170 + Fixed errors in ChannelTeardown/ChannelSetup CPHAL logic.
13171 + Added multicast support as requested.
13172 + Several new OS string functions added to OS_FUNCTIONS.
13173 + "DebugLevel" configuration parameter changed to "Debug".
13174 + "Stats0" changed to "StatsDump" for CPMAC.
13175 +
13176 +13 December 2002 CPHAL RC 2.03 (internal release)
13177 +
13178 + Performance improvements.
13179 + More debug statements implemented (esp AAL5).
13180 + Updated makefile with "make debug" option.
13181 + Hbridge performance: [debug library] 15774 tps (53% line rate)
13182 + [non-debug library] 13700 tps (46%)
13183 +
13184 +10 December 2002 CPHAL Release Candidate 2.02 (internal release)
13185 +
13186 + Much of the configuration code internal to CPMAC and AAL5 has been made common.
13187 + [os]Receive API had been modified to remove OsReceiveInfo. This information is now
13188 + available as third member of the FRAGLIST structure, on a per buffer basis.
13189 + Successfully tested multi-fragment support on CPMAC, using 32 byte buffers.
13190 + Code is now Emerald compliant - all buffer descriptors now aligned to cache-line
13191 + boundaries.
13192 +
13193 +2 December 2002 CPHAL Release Candidate 2.01
13194 +
13195 + Updates to comments in hcpmac.c, cpmdio.c, hcpmac.h
13196 + Nested comment in hcpmac.c in RC2 can cause compile errors.
13197 +
13198 +25 November 2002 CPHAL Release Candidate 2
13199 +
13200 +Project Items not completed for RC2
13201 +#6 Ship as Library - Once under CC. Moved to RC3
13202 +#8 Under Clearcase - Moved to RC3
13203 +#25 Emerald compliant - Moved to RC3
13204 +#26 Statistics support - Moved to RC3 (some support in RC2)
13205 +#36 Debug scheme implemented - Moved to RC3 (some support in RC2)
13206 +
13207 +8 November 2002 CPHAL Release Candidate 1
13208 +
13209 +Notes:
13210 +
13211 +Project Items not completed for RC1
13212 +
13213 +#8 Under Clearcase - Clearcase server failure this week. Moved to RC2
13214 +#6 Ship as Library - Once under CC. Moved to RC2
13215 +#13 Verify Datatypes. Moved to RC2
13216 +#14 Review APIs. Moved to RC2
13217 +
13218 +APIs under review for RC2
13219 +
13220 +halIsr()
13221 +hslRxReturn()
13222 +halSend()
13223 +osSendComplete()
13224 +osReceive()
13225 +
13226 +
13227 +CPMAC Build Instructions
13228 +
13229 +Compile the file 'hcpmac.c'.
13230 +
13231 +
13232 +AAL5 Build Instructions
13233 +
13234 +The AAL5 build is composed of the source files aal5sar.c and cpsar.c.
13235 +Refer to the provided makefile for an example of compiling these files
13236 +into a library.
13237 +
13238 +Example CPHAL Code
13239 +
13240 +CPMAC:
13241 +
13242 +Example CPMAC code is provided in the file hbridge.c.
13243 +This program is provided simply as an example of using the CPHAL API.
13244 +It is not intended to be compiled and executed in your environment.
13245 +
13246 +AAL5:
13247 +
13248 +Example AAL5 code is provided in the file loopback.c. This program
13249 +is provided simply as an example of using the CPHAL API. It is not
13250 +intended to be compiled and executed in your environment.
13251 +
13252 +
13253 +Performance Baseline
13254 +
13255 +
13256 +Cpmac
13257 +
13258 +RC1: hbridge.bin, running with IXIA cpahl_1.cfg.
13259 + This sends 64-byte packets from each Ixia port, with mac destination the other Ixia port.
13260 + MIPS core 4Kc.
13261 +
13262 +RC2: hbridge.bin, running with IXIA cpahl_1.cfg.
13263 + This sends 64-byte packets from each Ixia port, with mac destination the other Ixia port.
13264 + MIPS core 4Ke.
13265 + CPHAL now includes Emerald support, but this has been disabled by using 'cache -wt' to emulate 4Kc.
13266 +
13267 +RC3: hbridge.bin, running with IXIA cpahl_1.cfg.
13268 + This sends 64-byte packets from each Ixia port, with mac destination the other Ixia port.
13269 + MIPS core 4Ke.
13270 + Running as Emerald processor.
13271 +
13272 +Release Total Receive Rate Throughput Setting
13273 +
13274 +RC1 11300 38%
13275 +RC2 9524 32%
13276 +RC3 15190 51%
13277 diff -ruN linux-2.4.30.orig/drivers/net/Config.in linux-2.4.30/drivers/net/Config.in
13278 --- linux-2.4.30.orig/drivers/net/Config.in 2005-07-07 20:49:04.000000000 +0200
13279 +++ linux-2.4.30/drivers/net/Config.in 2005-07-08 21:52:27.000000000 +0200
13280 @@ -25,6 +25,24 @@
13281 comment 'Ethernet (10 or 100Mbit)'
13282 bool 'Ethernet (10 or 100Mbit)' CONFIG_NET_ETHERNET
13283 if [ "$CONFIG_NET_ETHERNET" = "y" ]; then
13284 + if [ "$CONFIG_MIPS_TITAN" = "y" -o "$CONFIG_AR7" = "y" ]; then
13285 + tristate ' Texas Instruments Avalanche CPMAC support' CONFIG_MIPS_AVALANCHE_CPMAC
13286 + fi
13287 + if [ "$CONFIG_MIPS_AVALANCHE_CPMAC" != "n" ]; then
13288 + if [ "$CONFIG_AR7WRD" = "y" -o "$CONFIG_AR7VWI" = "y" -o "$CONFIG_AR7VW" = "y" ]; then
13289 + define_bool CONFIG_MIPS_CPMAC_INIT_BUF_MALLOC y
13290 + define_int CONFIG_MIPS_CPMAC_PORTS 1
13291 + if [ "$CONFIG_MIPS_AVALANCHE_MARVELL" = "y" ]; then
13292 + define_bool CONFIG_AVALANCHE_LOW_CPMAC n
13293 + define_bool CONFIG_AVALANCHE_HIGH_CPMAC y
13294 + else
13295 + define_bool CONFIG_AVALANCHE_CPMAC_AUTO y
13296 + define_bool CONFIG_AVALANCHE_LOW_CPMAC n
13297 + define_bool CONFIG_AVALANCHE_HIGH_CPMAC n
13298 + fi
13299 + fi
13300 + fi
13301 +
13302 if [ "$CONFIG_ARM" = "y" ]; then
13303 dep_bool ' ARM EBSA110 AM79C961A support' CONFIG_ARM_AM79C961A $CONFIG_ARCH_EBSA110
13304 tristate ' Cirrus Logic CS8900A support' CONFIG_ARM_CIRRUS
13305 diff -ruN linux-2.4.30.orig/drivers/net/Makefile linux-2.4.30/drivers/net/Makefile
13306 --- linux-2.4.30.orig/drivers/net/Makefile 2005-07-07 20:49:03.000000000 +0200
13307 +++ linux-2.4.30/drivers/net/Makefile 2005-07-08 21:52:57.000000000 +0200
13308 @@ -56,6 +56,16 @@
13309 subdir-$(CONFIG_BONDING) += bonding
13310
13311 #
13312 +# Texas Instruments AVALANCHE CPMAC driver
13313 +#
13314 +
13315 +subdir-$(CONFIG_MIPS_AVALANCHE_CPMAC) += avalanche_cpmac
13316 +#obj-$(CONFIG_MIPS_AVALANCHE_CPMAC) += avalanche_cpmac/avalanche_cpmac.o
13317 +ifeq ($(CONFIG_MIPS_AVALANCHE_CPMAC),y)
13318 + obj-y += avalanche_cpmac/avalanche_cpmac.o
13319 +endif
13320 +
13321 +#
13322 # link order important here
13323 #
13324 obj-$(CONFIG_PLIP) += plip.o
Personal OpenWRT clone
This page took 0.870001 seconds and 5 git commands to generate.