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[s3c24xx] glamo-mmc: Limit clock rate.
[openwrt.git] / target / linux / s3c24xx / files-2.6.30 / drivers / mfd / glamo / glamo-core.c
1 /* Smedia Glamo 336x/337x driver
2 *
3 * (C) 2007 by Openmoko, Inc.
4 * Author: Harald Welte <laforge@openmoko.org>
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/string.h>
27 #include <linux/mm.h>
28 #include <linux/delay.h>
29 #include <linux/fb.h>
30 #include <linux/init.h>
31 #include <linux/irq.h>
32 #include <linux/interrupt.h>
33 #include <linux/workqueue.h>
34 #include <linux/platform_device.h>
35 #include <linux/kernel_stat.h>
36 #include <linux/spinlock.h>
37 #include <linux/mfd/core.h>
38 #include <linux/mfd/glamo.h>
39 #include <linux/spi/glamo.h>
40 #include <linux/glamo-gpio.h>
41 #include <linux/glamofb.h>
42 #include <linux/io.h>
43
44 #include <asm/div64.h>
45
46 #include <linux/pm.h>
47
48 #include "glamo-regs.h"
49 #include "glamo-core.h"
50
51 #define GLAMO_MEM_REFRESH_COUNT 0x100
52
53 /*
54 * Glamo internal settings
55 *
56 * We run the memory interface from the faster PLLB on 2.6.28 kernels and
57 * above. Couple of GTA02 users report trouble with memory bus when they
58 * upgraded from 2.6.24. So this parameter allows reversion to 2.6.24
59 * scheme if their Glamo chip needs it.
60 *
61 * you can override the faster default on kernel commandline using
62 *
63 * glamo3362.slow_memory=1
64 *
65 * for example
66 */
67
68 static int slow_memory = 0;
69 module_param(slow_memory, int, 0644);
70
71 struct reg_range {
72 int start;
73 int count;
74 char *name;
75 char dump;
76 };
77
78 struct reg_range reg_range[] = {
79 { 0x0000, 0x76, "General", 1 },
80 { 0x0200, 0x18, "Host Bus", 1 },
81 { 0x0300, 0x38, "Memory", 1 },
82 /* { 0x0400, 0x100, "Sensor", 0 }, */
83 /* { 0x0500, 0x300, "ISP", 0 }, */
84 /* { 0x0800, 0x400, "JPEG", 0 }, */
85 /* { 0x0c00, 0xcc, "MPEG", 0 }, */
86 { 0x1100, 0xb2, "LCD 1", 1 },
87 { 0x1200, 0x64, "LCD 2", 1 },
88 { 0x1400, 0x42, "MMC", 1 },
89 /* { 0x1500, 0x080, "MPU 0", 0 },
90 { 0x1580, 0x080, "MPU 1", 0 },
91 { 0x1600, 0x080, "Cmd Queue", 0 },
92 { 0x1680, 0x080, "RISC CPU", 0 },
93 { 0x1700, 0x400, "2D Unit", 0 },
94 { 0x1b00, 0x900, "3D Unit", 0 }, */
95 };
96
97 static inline void __reg_write(struct glamo_core *glamo,
98 u_int16_t reg, u_int16_t val)
99 {
100 writew(val, glamo->base + reg);
101 }
102
103 static inline u_int16_t __reg_read(struct glamo_core *glamo,
104 u_int16_t reg)
105 {
106 return readw(glamo->base + reg);
107 }
108
109 static void __reg_set_bit_mask(struct glamo_core *glamo,
110 u_int16_t reg, u_int16_t mask,
111 u_int16_t val)
112 {
113 u_int16_t tmp;
114
115 val &= mask;
116
117 tmp = __reg_read(glamo, reg);
118 tmp &= ~mask;
119 tmp |= val;
120 __reg_write(glamo, reg, tmp);
121 }
122
123 static void reg_set_bit_mask(struct glamo_core *glamo,
124 u_int16_t reg, u_int16_t mask,
125 u_int16_t val)
126 {
127 spin_lock(&glamo->lock);
128 __reg_set_bit_mask(glamo, reg, mask, val);
129 spin_unlock(&glamo->lock);
130 }
131
132 static inline void __reg_set_bit(struct glamo_core *glamo,
133 u_int16_t reg, u_int16_t bit)
134 {
135 __reg_set_bit_mask(glamo, reg, bit, 0xffff);
136 }
137
138 static inline void __reg_clear_bit(struct glamo_core *glamo,
139 u_int16_t reg, u_int16_t bit)
140 {
141 __reg_set_bit_mask(glamo, reg, bit, 0);
142 }
143
144 /***********************************************************************
145 * resources of sibling devices
146 ***********************************************************************/
147
148 static struct resource glamo_fb_resources[] = {
149 {
150 .name = "glamo-fb-regs",
151 .start = GLAMO_REGOFS_LCD,
152 .end = GLAMO_REGOFS_MMC - 1,
153 .flags = IORESOURCE_MEM,
154 }, {
155 .name = "glamo-fb-mem",
156 .start = GLAMO_OFFSET_FB,
157 .end = GLAMO_OFFSET_FB + GLAMO_FB_SIZE - 1,
158 .flags = IORESOURCE_MEM,
159 },
160 };
161
162 static struct resource glamo_mmc_resources[] = {
163 {
164 .start = GLAMO_REGOFS_MMC,
165 .end = GLAMO_REGOFS_MPROC0 - 1,
166 .flags = IORESOURCE_MEM
167 }, {
168 .start = IRQ_GLAMO_MMC,
169 .end = IRQ_GLAMO_MMC,
170 .flags = IORESOURCE_IRQ,
171 }, { /* our data buffer for MMC transfers */
172 .start = GLAMO_OFFSET_FB + GLAMO_FB_SIZE,
173 .end = GLAMO_OFFSET_FB + GLAMO_FB_SIZE +
174 GLAMO_MMC_BUFFER_SIZE - 1,
175 .flags = IORESOURCE_MEM
176 },
177 };
178
179 enum glamo_cells {
180 GLAMO_CELL_FB,
181 GLAMO_CELL_MMC,
182 GLAMO_CELL_SPI_GPIO
183 };
184
185 static struct mfd_cell glamo_cells[] = {
186 [GLAMO_CELL_FB] = {
187 .name = "glamo-fb",
188 .num_resources = ARRAY_SIZE(glamo_fb_resources),
189 .resources = glamo_fb_resources,
190 },
191 [GLAMO_CELL_MMC] = {
192 .name = "glamo-mci",
193 .num_resources = ARRAY_SIZE(glamo_mmc_resources),
194 .resources = glamo_mmc_resources,
195 },
196 [GLAMO_CELL_SPI_GPIO] = {
197 .name = "glamo-spi-gpio",
198 },
199 };
200
201
202 /***********************************************************************
203 * IRQ demultiplexer
204 ***********************************************************************/
205 #define irq2glamo(x) (x - IRQ_GLAMO(0))
206
207 static void glamo_ack_irq(unsigned int irq)
208 {
209 struct glamo_core *glamo = (struct glamo_core*)get_irq_chip_data(irq);
210 /* clear interrupt source */
211 __reg_write(glamo, GLAMO_REG_IRQ_CLEAR,
212 1 << irq2glamo(irq));
213 }
214
215 static void glamo_mask_irq(unsigned int irq)
216 {
217 struct glamo_core *glamo = (struct glamo_core*)get_irq_chip_data(irq);
218 u_int16_t tmp;
219
220 /* clear bit in enable register */
221 tmp = __reg_read(glamo, GLAMO_REG_IRQ_ENABLE);
222 tmp &= ~(1 << irq2glamo(irq));
223 __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, tmp);
224 }
225
226 static void glamo_unmask_irq(unsigned int irq)
227 {
228 struct glamo_core *glamo = (struct glamo_core*)get_irq_chip_data(irq);
229 u_int16_t tmp;
230
231 /* set bit in enable register */
232 tmp = __reg_read(glamo, GLAMO_REG_IRQ_ENABLE);
233 tmp |= (1 << irq2glamo(irq));
234 __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, tmp);
235 }
236
237 static struct irq_chip glamo_irq_chip = {
238 .name = "glamo",
239 .ack = glamo_ack_irq,
240 .mask = glamo_mask_irq,
241 .unmask = glamo_unmask_irq,
242 };
243
244 static void glamo_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
245 {
246 struct glamo_core *glamo = get_irq_desc_chip_data(desc);
247 desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
248
249 if (unlikely(desc->status & IRQ_INPROGRESS)) {
250 desc->status |= (IRQ_PENDING | IRQ_MASKED);
251 desc->chip->mask(irq);
252 desc->chip->ack(irq);
253 return;
254 }
255 kstat_incr_irqs_this_cpu(irq, desc);
256
257 desc->chip->ack(irq);
258 desc->status |= IRQ_INPROGRESS;
259
260 do {
261 u_int16_t irqstatus;
262 int i;
263
264 if (unlikely((desc->status &
265 (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) ==
266 (IRQ_PENDING | IRQ_MASKED))) {
267 /* dealing with pending IRQ, unmasking */
268 desc->chip->unmask(irq);
269 desc->status &= ~IRQ_MASKED;
270 }
271
272 desc->status &= ~IRQ_PENDING;
273
274 /* read IRQ status register */
275 irqstatus = __reg_read(glamo, GLAMO_REG_IRQ_STATUS);
276 for (i = 0; i < 9; i++)
277 if (irqstatus & (1 << i))
278 desc_handle_irq(IRQ_GLAMO(i),
279 irq_desc+IRQ_GLAMO(i));
280
281 } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
282
283 desc->status &= ~IRQ_INPROGRESS;
284 }
285
286
287 static ssize_t regs_write(struct device *dev, struct device_attribute *attr,
288 const char *buf, size_t count)
289 {
290 unsigned long reg = simple_strtoul(buf, NULL, 10);
291 struct glamo_core *glamo = dev_get_drvdata(dev);
292
293 while (*buf && (*buf != ' '))
294 buf++;
295 if (*buf != ' ')
296 return -EINVAL;
297 while (*buf && (*buf == ' '))
298 buf++;
299 if (!*buf)
300 return -EINVAL;
301
302 printk(KERN_INFO"reg 0x%02lX <-- 0x%04lX\n",
303 reg, simple_strtoul(buf, NULL, 10));
304
305 __reg_write(glamo, reg, simple_strtoul(buf, NULL, 10));
306
307 return count;
308 }
309
310 static ssize_t regs_read(struct device *dev, struct device_attribute *attr,
311 char *buf)
312 {
313 struct glamo_core *glamo = dev_get_drvdata(dev);
314 int n, n1 = 0, r;
315 char * end = buf;
316
317 spin_lock(&glamo->lock);
318
319 for (r = 0; r < ARRAY_SIZE(reg_range); r++) {
320 if (!reg_range[r].dump)
321 continue;
322 n1 = 0;
323 end += sprintf(end, "\n%s\n", reg_range[r].name);
324 for (n = reg_range[r].start;
325 n < reg_range[r].start + reg_range[r].count; n += 2) {
326 if (((n1++) & 7) == 0)
327 end += sprintf(end, "\n%04X: ", n);
328 end += sprintf(end, "%04x ", __reg_read(glamo, n));
329 }
330 end += sprintf(end, "\n");
331 if (!attr) {
332 printk("%s", buf);
333 end = buf;
334 }
335 }
336 spin_unlock(&glamo->lock);
337
338 return end - buf;
339 }
340
341 static DEVICE_ATTR(regs, 0644, regs_read, regs_write);
342 static struct attribute *glamo_sysfs_entries[] = {
343 &dev_attr_regs.attr,
344 NULL
345 };
346 static struct attribute_group glamo_attr_group = {
347 .name = NULL,
348 .attrs = glamo_sysfs_entries,
349 };
350
351
352
353 /***********************************************************************
354 * 'engine' support
355 ***********************************************************************/
356
357 int __glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
358 {
359 switch (engine) {
360 case GLAMO_ENGINE_LCD:
361 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
362 GLAMO_HOSTBUS2_MMIO_EN_LCD,
363 GLAMO_HOSTBUS2_MMIO_EN_LCD);
364 __reg_write(glamo, GLAMO_REG_CLOCK_LCD,
365 GLAMO_CLOCK_LCD_EN_M5CLK |
366 GLAMO_CLOCK_LCD_EN_DHCLK |
367 GLAMO_CLOCK_LCD_EN_DMCLK |
368 GLAMO_CLOCK_LCD_EN_DCLK |
369 GLAMO_CLOCK_LCD_DG_M5CLK |
370 GLAMO_CLOCK_LCD_DG_DMCLK);
371 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
372 GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
373 GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
374 GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0xffff);
375 break;
376 case GLAMO_ENGINE_MMC:
377 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
378 GLAMO_HOSTBUS2_MMIO_EN_MMC,
379 GLAMO_HOSTBUS2_MMIO_EN_MMC);
380 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
381 GLAMO_CLOCK_MMC_EN_M9CLK |
382 GLAMO_CLOCK_MMC_EN_TCLK |
383 GLAMO_CLOCK_MMC_DG_M9CLK |
384 GLAMO_CLOCK_MMC_DG_TCLK, 0xffff);
385 /* enable the TCLK divider clk input */
386 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
387 GLAMO_CLOCK_GEN51_EN_DIV_TCLK,
388 GLAMO_CLOCK_GEN51_EN_DIV_TCLK);
389 break;
390 case GLAMO_ENGINE_2D:
391 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
392 GLAMO_CLOCK_2D_EN_M7CLK |
393 GLAMO_CLOCK_2D_EN_GCLK |
394 GLAMO_CLOCK_2D_DG_M7CLK |
395 GLAMO_CLOCK_2D_DG_GCLK, 0xffff);
396 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
397 GLAMO_HOSTBUS2_MMIO_EN_2D,
398 GLAMO_HOSTBUS2_MMIO_EN_2D);
399 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
400 GLAMO_CLOCK_GEN51_EN_DIV_GCLK,
401 0xffff);
402 break;
403 case GLAMO_ENGINE_CMDQ:
404 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
405 GLAMO_CLOCK_2D_EN_M6CLK, 0xffff);
406 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
407 GLAMO_HOSTBUS2_MMIO_EN_CQ,
408 GLAMO_HOSTBUS2_MMIO_EN_CQ);
409 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
410 GLAMO_CLOCK_GEN51_EN_DIV_MCLK,
411 0xffff);
412 break;
413 /* FIXME: Implementation */
414 default:
415 return -EINVAL;
416 }
417
418 glamo->engine_enabled_bitfield |= 1 << engine;
419
420 return 0;
421 }
422
423 int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
424 {
425 int ret;
426
427 spin_lock(&glamo->lock);
428
429 ret = __glamo_engine_enable(glamo, engine);
430
431 spin_unlock(&glamo->lock);
432
433 return ret;
434 }
435 EXPORT_SYMBOL_GPL(glamo_engine_enable);
436
437 int __glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
438 {
439 switch (engine) {
440 case GLAMO_ENGINE_LCD:
441 /* remove pixel clock to LCM */
442 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
443 GLAMO_CLOCK_LCD_EN_DCLK, 0);
444 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
445 GLAMO_CLOCK_LCD_EN_DHCLK |
446 GLAMO_CLOCK_LCD_EN_DMCLK, 0);
447 /* kill memory clock */
448 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
449 GLAMO_CLOCK_LCD_EN_M5CLK, 0);
450 /* stop dividing the clocks */
451 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
452 GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
453 GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
454 GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0);
455 break;
456
457 case GLAMO_ENGINE_MMC:
458 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
459 GLAMO_CLOCK_MMC_EN_M9CLK |
460 GLAMO_CLOCK_MMC_EN_TCLK |
461 GLAMO_CLOCK_MMC_DG_M9CLK |
462 GLAMO_CLOCK_MMC_DG_TCLK, 0);
463 /* disable the TCLK divider clk input */
464 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
465 GLAMO_CLOCK_GEN51_EN_DIV_TCLK, 0);
466 break;
467 case GLAMO_ENGINE_CMDQ:
468 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
469 GLAMO_CLOCK_2D_EN_M6CLK,
470 0);
471 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
472 GLAMO_HOSTBUS2_MMIO_EN_CQ,
473 GLAMO_HOSTBUS2_MMIO_EN_CQ);
474 /* __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
475 GLAMO_CLOCK_GEN51_EN_DIV_MCLK,
476 0);*/
477 break;
478 case GLAMO_ENGINE_2D:
479 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
480 GLAMO_CLOCK_2D_EN_M7CLK |
481 GLAMO_CLOCK_2D_EN_GCLK |
482 GLAMO_CLOCK_2D_DG_M7CLK |
483 GLAMO_CLOCK_2D_DG_GCLK,
484 0);
485 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
486 GLAMO_HOSTBUS2_MMIO_EN_2D,
487 GLAMO_HOSTBUS2_MMIO_EN_2D);
488 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
489 GLAMO_CLOCK_GEN51_EN_DIV_GCLK,
490 0);
491 break;
492 default:
493 return -EINVAL;
494 }
495
496 glamo->engine_enabled_bitfield &= ~(1 << engine);
497
498 return 0;
499 }
500 int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
501 {
502 int ret;
503
504 spin_lock(&glamo->lock);
505
506 ret = __glamo_engine_disable(glamo, engine);
507
508 spin_unlock(&glamo->lock);
509
510 return ret;
511 }
512 EXPORT_SYMBOL_GPL(glamo_engine_disable);
513
514 static const u_int16_t engine_clock_regs[__NUM_GLAMO_ENGINES] = {
515 [GLAMO_ENGINE_LCD] = GLAMO_REG_CLOCK_LCD,
516 [GLAMO_ENGINE_MMC] = GLAMO_REG_CLOCK_MMC,
517 [GLAMO_ENGINE_ISP] = GLAMO_REG_CLOCK_ISP,
518 [GLAMO_ENGINE_JPEG] = GLAMO_REG_CLOCK_JPEG,
519 [GLAMO_ENGINE_3D] = GLAMO_REG_CLOCK_3D,
520 [GLAMO_ENGINE_2D] = GLAMO_REG_CLOCK_2D,
521 [GLAMO_ENGINE_MPEG_ENC] = GLAMO_REG_CLOCK_MPEG,
522 [GLAMO_ENGINE_MPEG_DEC] = GLAMO_REG_CLOCK_MPEG,
523 };
524
525 void glamo_engine_clkreg_set(struct glamo_core *glamo,
526 enum glamo_engine engine,
527 u_int16_t mask, u_int16_t val)
528 {
529 reg_set_bit_mask(glamo, engine_clock_regs[engine], mask, val);
530 }
531 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_set);
532
533 u_int16_t glamo_engine_clkreg_get(struct glamo_core *glamo,
534 enum glamo_engine engine)
535 {
536 u_int16_t val;
537
538 spin_lock(&glamo->lock);
539 val = __reg_read(glamo, engine_clock_regs[engine]);
540 spin_unlock(&glamo->lock);
541
542 return val;
543 }
544 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_get);
545
546 static const struct glamo_script engine_div_regs[__NUM_GLAMO_ENGINES] = {
547 [GLAMO_ENGINE_LCD] = {GLAMO_REG_CLOCK_GEN5_1, GLAMO_CLOCK_GEN51_EN_DIV_DCLK},
548 [GLAMO_ENGINE_MMC] = {GLAMO_REG_CLOCK_GEN5_1, GLAMO_CLOCK_GEN51_EN_DIV_TCLK},
549 [GLAMO_ENGINE_2D] = {GLAMO_REG_CLOCK_GEN5_1, GLAMO_CLOCK_GEN51_EN_DIV_GCLK},
550 };
551
552 void glamo_engine_div_enable(struct glamo_core *glamo, enum glamo_engine engine)
553 {
554 uint16_t reg = engine_div_regs[engine].reg;
555 uint16_t bit = engine_div_regs[engine].val;
556 uint16_t val;
557
558 spin_lock(&glamo->lock);
559 val = __reg_read(glamo, reg);
560 __reg_write(glamo, reg, val | bit);
561 spin_unlock(&glamo->lock);
562 mdelay(5);
563 }
564 EXPORT_SYMBOL_GPL(glamo_engine_div_enable);
565
566 void glamo_engine_div_disable(struct glamo_core *glamo, enum glamo_engine engine)
567 {
568 uint16_t reg = engine_div_regs[engine].reg;
569 uint16_t bit = engine_div_regs[engine].val;
570 uint16_t val;
571
572 spin_lock(&glamo->lock);
573 val = __reg_read(glamo, reg);
574 __reg_write(glamo, reg, val & ~bit);
575 spin_unlock(&glamo->lock);
576 }
577 EXPORT_SYMBOL_GPL(glamo_engine_div_disable);
578
579 static const struct glamo_script reset_regs[] = {
580 [GLAMO_ENGINE_LCD] = {
581 GLAMO_REG_CLOCK_LCD, GLAMO_CLOCK_LCD_RESET
582 },
583 #if 0
584 [GLAMO_ENGINE_HOST] = {
585 GLAMO_REG_CLOCK_HOST, GLAMO_CLOCK_HOST_RESET
586 },
587 [GLAMO_ENGINE_MEM] = {
588 GLAMO_REG_CLOCK_MEM, GLAMO_CLOCK_MEM_RESET
589 },
590 #endif
591 [GLAMO_ENGINE_MMC] = {
592 GLAMO_REG_CLOCK_MMC, GLAMO_CLOCK_MMC_RESET
593 },
594 [GLAMO_ENGINE_CMDQ] = {
595 GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_CQ_RESET
596 },
597 [GLAMO_ENGINE_2D] = {
598 GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_RESET
599 },
600 [GLAMO_ENGINE_JPEG] = {
601 GLAMO_REG_CLOCK_JPEG, GLAMO_CLOCK_JPEG_RESET
602 },
603 };
604
605 void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine)
606 {
607 uint16_t reg = reset_regs[engine].reg;
608 uint16_t val = reset_regs[engine].val;
609
610 if (engine >= ARRAY_SIZE(reset_regs)) {
611 dev_warn(&glamo->pdev->dev, "unknown engine %u ", engine);
612 return;
613 }
614
615
616 spin_lock(&glamo->lock);
617 __reg_set_bit(glamo, reg, val);
618 __reg_clear_bit(glamo, reg, val);
619 spin_unlock(&glamo->lock);
620 }
621 EXPORT_SYMBOL_GPL(glamo_engine_reset);
622
623 void glamo_lcm_reset(struct platform_device *pdev, int level)
624 {
625 struct glamo_core *glamo = dev_get_drvdata(&pdev->dev);
626 if (!glamo)
627 return;
628
629 glamo_gpio_setpin(glamo, GLAMO_GPIO4, level);
630 glamo_gpio_cfgpin(glamo, GLAMO_GPIO4_OUTPUT);
631 }
632 EXPORT_SYMBOL_GPL(glamo_lcm_reset);
633
634 int glamo_pll_rate(struct glamo_core *glamo,
635 enum glamo_pll pll)
636 {
637 u_int16_t reg;
638 unsigned int osci = glamo->pdata->osci_clock_rate;
639
640 switch (pll) {
641 case GLAMO_PLL1:
642 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN1);
643 break;
644 case GLAMO_PLL2:
645 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN3);
646 break;
647 default:
648 return -EINVAL;
649 }
650 return osci*reg;
651 }
652 EXPORT_SYMBOL_GPL(glamo_pll_rate);
653
654 int glamo_engine_reclock(struct glamo_core *glamo,
655 enum glamo_engine engine,
656 int hz)
657 {
658 int pll;
659 u_int16_t reg, mask, div;
660
661 if (!hz)
662 return -EINVAL;
663
664 switch (engine) {
665 case GLAMO_ENGINE_LCD:
666 pll = GLAMO_PLL1;
667 reg = GLAMO_REG_CLOCK_GEN7;
668 mask = 0xff;
669 break;
670 case GLAMO_ENGINE_MMC:
671 pll = GLAMO_PLL1;
672 reg = GLAMO_REG_CLOCK_GEN8;
673 mask = 0xff;
674 break;
675 default:
676 dev_warn(&glamo->pdev->dev,
677 "reclock of engine 0x%x not supported\n", engine);
678 return -EINVAL;
679 break;
680 }
681
682 pll = glamo_pll_rate(glamo, pll);
683
684 div = pll / hz;
685
686 if (div != 0 && pll / div <= hz)
687 --div;
688
689 if (div > mask)
690 div = mask;
691
692 dev_dbg(&glamo->pdev->dev,
693 "PLL %d, kHZ %d, div %d\n", pll, hz / 1000, div);
694
695 reg_set_bit_mask(glamo, reg, mask, div);
696 mdelay(5); /* wait some time to stabilize */
697
698 return pll / (div + 1);
699 }
700 EXPORT_SYMBOL_GPL(glamo_engine_reclock);
701
702 /***********************************************************************
703 * script support
704 ***********************************************************************/
705
706 int glamo_run_script(struct glamo_core *glamo, const struct glamo_script *script,
707 int len, int may_sleep)
708 {
709 int i;
710
711 for (i = 0; i < len; i++) {
712 struct glamo_script *line = &script[i];
713
714 switch (line->reg) {
715 case 0xffff:
716 return 0;
717 case 0xfffe:
718 if (may_sleep)
719 msleep(line->val);
720 else
721 mdelay(line->val * 4);
722 break;
723 case 0xfffd:
724 /* spin until PLLs lock */
725 while ((__reg_read(glamo, GLAMO_REG_PLL_GEN5) & 3) != 3)
726 ;
727 break;
728
729 /*
730 * couple of people reported artefacts with 2.6.28 changes, this
731 * allows reversion to 2.6.24 settings
732 */
733
734 case 0x200:
735 switch (slow_memory) {
736 /* choice 1 is the most conservative */
737 case 1: /* 3 waits on Async BB R & W, Use PLL 1 for mem bus */
738 __reg_write(glamo, script[i].reg, 0xef0);
739 break;
740 case 2: /* 2 waits on Async BB R & W, Use PLL 1 for mem bus */
741 __reg_write(glamo, script[i].reg, 0xea0);
742 break;
743 case 3: /* 1 waits on Async BB R & W, Use PLL 1 for mem bus */
744 __reg_write(glamo, script[i].reg, 0xe50);
745 break;
746 case 4: /* 0 waits on Async BB R & W, Use PLL 1 for mem bus */
747 __reg_write(glamo, script[i].reg, 0xe00);
748 break;
749
750 /* using PLL2 for memory bus increases CPU bandwidth significantly */
751 case 5: /* 3 waits on Async BB R & W, Use PLL 2 for mem bus */
752 __reg_write(glamo, script[i].reg, 0xef3);
753 break;
754 case 6: /* 2 waits on Async BB R & W, Use PLL 2 for mem bus */
755 __reg_write(glamo, script[i].reg, 0xea3);
756 break;
757 case 7: /* 1 waits on Async BB R & W, Use PLL 2 for mem bus */
758 __reg_write(glamo, script[i].reg, 0xe53);
759 break;
760 /* default of 0 or >7 is fastest */
761 default: /* 0 waits on Async BB R & W, Use PLL 2 for mem bus */
762 __reg_write(glamo, script[i].reg, 0xe03);
763 break;
764 }
765 break;
766
767 default:
768 __reg_write(glamo, script[i].reg, script[i].val);
769 break;
770 }
771 }
772
773 return 0;
774 }
775 EXPORT_SYMBOL(glamo_run_script);
776
777 static const struct glamo_script glamo_init_script[] = {
778 { GLAMO_REG_CLOCK_HOST, 0x1000 },
779 { 0xfffe, 2 },
780 { GLAMO_REG_CLOCK_MEMORY, 0x1000 },
781 { GLAMO_REG_CLOCK_MEMORY, 0x2000 },
782 { GLAMO_REG_CLOCK_LCD, 0x1000 },
783 { GLAMO_REG_CLOCK_MMC, 0x1000 },
784 { GLAMO_REG_CLOCK_ISP, 0x1000 },
785 { GLAMO_REG_CLOCK_ISP, 0x3000 },
786 { GLAMO_REG_CLOCK_JPEG, 0x1000 },
787 { GLAMO_REG_CLOCK_3D, 0x1000 },
788 { GLAMO_REG_CLOCK_3D, 0x3000 },
789 { GLAMO_REG_CLOCK_2D, 0x1000 },
790 { GLAMO_REG_CLOCK_2D, 0x3000 },
791 { GLAMO_REG_CLOCK_RISC1, 0x1000 },
792 { GLAMO_REG_CLOCK_MPEG, 0x3000 },
793 { GLAMO_REG_CLOCK_MPEG, 0x3000 },
794 { GLAMO_REG_CLOCK_MPROC, 0x1000 /*0x100f*/ },
795 { 0xfffe, 2 },
796 { GLAMO_REG_CLOCK_HOST, 0x0000 },
797 { GLAMO_REG_CLOCK_MEMORY, 0x0000 },
798 { GLAMO_REG_CLOCK_LCD, 0x0000 },
799 { GLAMO_REG_CLOCK_MMC, 0x0000 },
800 #if 0
801 /* unused engines must be left in reset to stop MMC block read "blackouts" */
802 { GLAMO_REG_CLOCK_ISP, 0x0000 },
803 { GLAMO_REG_CLOCK_ISP, 0x0000 },
804 { GLAMO_REG_CLOCK_JPEG, 0x0000 },
805 { GLAMO_REG_CLOCK_3D, 0x0000 },
806 { GLAMO_REG_CLOCK_3D, 0x0000 },
807 { GLAMO_REG_CLOCK_2D, 0x0000 },
808 { GLAMO_REG_CLOCK_2D, 0x0000 },
809 { GLAMO_REG_CLOCK_RISC1, 0x0000 },
810 { GLAMO_REG_CLOCK_MPEG, 0x0000 },
811 { GLAMO_REG_CLOCK_MPEG, 0x0000 },
812 #endif
813 { GLAMO_REG_PLL_GEN1, 0x05db }, /* 48MHz */
814 { GLAMO_REG_PLL_GEN3, 0x0aba }, /* 90MHz */
815 { 0xfffd, 0 },
816 /*
817 * b9 of this register MUST be zero to get any interrupts on INT#
818 * the other set bits enable all the engine interrupt sources
819 */
820 { GLAMO_REG_IRQ_ENABLE, 0x01ff },
821 { GLAMO_REG_CLOCK_GEN6, 0x2000 },
822 { GLAMO_REG_CLOCK_GEN7, 0x0101 },
823 { GLAMO_REG_CLOCK_GEN8, 0x0100 },
824 { GLAMO_REG_CLOCK_HOST, 0x000d },
825 /*
826 * b7..b4 = 0 = no wait states on read or write
827 * b0 = 1 select PLL2 for Host interface, b1 = enable it
828 */
829 { 0x200, 0x0e03 /* this is replaced by script parser */ },
830 { 0x202, 0x07ff },
831 { 0x212, 0x0000 },
832 { 0x214, 0x4000 },
833 { 0x216, 0xf00e },
834
835 /* S-Media recommended "set tiling mode to 512 mode for memory access
836 * more efficiency when 640x480" */
837 { GLAMO_REG_MEM_TYPE, 0x0c74 }, /* 8MB, 16 word pg wr+rd */
838 { GLAMO_REG_MEM_GEN, 0xafaf }, /* 63 grants min + max */
839
840 { GLAMO_REGOFS_HOSTBUS + 2, 0xffff }, /* enable on MMIO*/
841
842 { GLAMO_REG_MEM_TIMING1, 0x0108 },
843 { GLAMO_REG_MEM_TIMING2, 0x0010 }, /* Taa = 3 MCLK */
844 { GLAMO_REG_MEM_TIMING3, 0x0000 },
845 { GLAMO_REG_MEM_TIMING4, 0x0000 }, /* CE1# delay fall/rise */
846 { GLAMO_REG_MEM_TIMING5, 0x0000 }, /* UB# LB# */
847 { GLAMO_REG_MEM_TIMING6, 0x0000 }, /* OE# */
848 { GLAMO_REG_MEM_TIMING7, 0x0000 }, /* WE# */
849 { GLAMO_REG_MEM_TIMING8, 0x1002 }, /* MCLK delay, was 0x1000 */
850 { GLAMO_REG_MEM_TIMING9, 0x6006 },
851 { GLAMO_REG_MEM_TIMING10, 0x00ff },
852 { GLAMO_REG_MEM_TIMING11, 0x0001 },
853 { GLAMO_REG_MEM_POWER1, 0x0020 },
854 { GLAMO_REG_MEM_POWER2, 0x0000 },
855 { GLAMO_REG_MEM_DRAM1, 0x0000 },
856 { 0xfffe, 1 },
857 { GLAMO_REG_MEM_DRAM1, 0xc100 },
858 { 0xfffe, 1 },
859 { GLAMO_REG_MEM_DRAM1, 0xe100 },
860 { GLAMO_REG_MEM_DRAM2, 0x01d6 },
861 { GLAMO_REG_CLOCK_MEMORY, 0x000b },
862 { GLAMO_REG_GPIO_GEN1, 0x000f },
863 { GLAMO_REG_GPIO_GEN2, 0x111e },
864 { GLAMO_REG_GPIO_GEN3, 0xccc3 },
865 { GLAMO_REG_GPIO_GEN4, 0x111e },
866 { GLAMO_REG_GPIO_GEN5, 0x000f },
867 };
868 #if 0
869 static struct glamo_script glamo_resume_script[] = {
870
871 { GLAMO_REG_PLL_GEN1, 0x05db }, /* 48MHz */
872 { GLAMO_REG_PLL_GEN3, 0x0aba }, /* 90MHz */
873 { GLAMO_REG_DFT_GEN6, 1 },
874 { 0xfffe, 100 },
875 { 0xfffd, 0 },
876 { 0x200, 0x0e03 },
877
878 /*
879 * b9 of this register MUST be zero to get any interrupts on INT#
880 * the other set bits enable all the engine interrupt sources
881 */
882 { GLAMO_REG_IRQ_ENABLE, 0x01ff },
883 { GLAMO_REG_CLOCK_HOST, 0x0018 },
884 { GLAMO_REG_CLOCK_GEN5_1, 0x18b1 },
885
886 { GLAMO_REG_MEM_DRAM1, 0x0000 },
887 { 0xfffe, 1 },
888 { GLAMO_REG_MEM_DRAM1, 0xc100 },
889 { 0xfffe, 1 },
890 { GLAMO_REG_MEM_DRAM1, 0xe100 },
891 { GLAMO_REG_MEM_DRAM2, 0x01d6 },
892 { GLAMO_REG_CLOCK_MEMORY, 0x000b },
893 };
894 #endif
895
896 enum glamo_power {
897 GLAMO_POWER_ON,
898 GLAMO_POWER_SUSPEND,
899 };
900
901 static void glamo_power(struct glamo_core *glamo,
902 enum glamo_power new_state)
903 {
904 int n;
905 unsigned long flags;
906
907 spin_lock_irqsave(&glamo->lock, flags);
908
909 dev_info(&glamo->pdev->dev, "***** glamo_power -> %d\n", new_state);
910
911 /*
912 Power management
913 static const REG_VALUE_MASK_TYPE reg_powerOn[] =
914 {
915 { REG_GEN_DFT6, REG_BIT_ALL, REG_DATA(1u << 0) },
916 { REG_GEN_PLL3, 0u, REG_DATA(1u << 13) },
917 { REG_GEN_MEM_CLK, REG_BIT_ALL, REG_BIT_EN_MOCACLK },
918 { REG_MEM_DRAM2, 0u, REG_BIT_EN_DEEP_POWER_DOWN },
919 { REG_MEM_DRAM1, 0u, REG_BIT_SELF_REFRESH }
920 };
921
922 static const REG_VALUE_MASK_TYPE reg_powerStandby[] =
923 {
924 { REG_MEM_DRAM1, REG_BIT_ALL, REG_BIT_SELF_REFRESH },
925 { REG_GEN_MEM_CLK, 0u, REG_BIT_EN_MOCACLK },
926 { REG_GEN_PLL3, REG_BIT_ALL, REG_DATA(1u << 13) },
927 { REG_GEN_DFT5, REG_BIT_ALL, REG_DATA(1u << 0) }
928 };
929
930 static const REG_VALUE_MASK_TYPE reg_powerSuspend[] =
931 {
932 { REG_MEM_DRAM2, REG_BIT_ALL, REG_BIT_EN_DEEP_POWER_DOWN },
933 { REG_GEN_MEM_CLK, 0u, REG_BIT_EN_MOCACLK },
934 { REG_GEN_PLL3, REG_BIT_ALL, REG_DATA(1u << 13) },
935 { REG_GEN_DFT5, REG_BIT_ALL, REG_DATA(1u << 0) }
936 };
937 */
938
939 switch (new_state) {
940 case GLAMO_POWER_ON:
941
942 /*
943 * glamo state on resume is nondeterministic in some
944 * fundamental way, it has also been observed that the
945 * Glamo reset pin can get asserted by, eg, touching it with
946 * a scope probe. So the only answer is to roll with it and
947 * force an external reset on the Glamo during resume.
948 */
949
950 (glamo->pdata->glamo_external_reset)(0);
951 udelay(10);
952 (glamo->pdata->glamo_external_reset)(1);
953 mdelay(5);
954
955 glamo_run_script(glamo, glamo_init_script,
956 ARRAY_SIZE(glamo_init_script), 0);
957
958 break;
959
960 case GLAMO_POWER_SUSPEND:
961
962 /* nuke interrupts */
963 __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, 0x200);
964
965 /* stash a copy of which engines were running */
966 glamo->engine_enabled_bitfield_suspend =
967 glamo->engine_enabled_bitfield;
968
969 /* take down each engine before we kill mem and pll */
970 for (n = 0; n < __NUM_GLAMO_ENGINES; n++)
971 if (glamo->engine_enabled_bitfield & (1 << n))
972 __glamo_engine_disable(glamo, n);
973
974 /* enable self-refresh */
975
976 __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
977 GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
978 GLAMO_MEM_DRAM1_EN_GATE_CKE |
979 GLAMO_MEM_DRAM1_SELF_REFRESH |
980 GLAMO_MEM_REFRESH_COUNT);
981 __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
982 GLAMO_MEM_DRAM1_EN_MODEREG_SET |
983 GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
984 GLAMO_MEM_DRAM1_EN_GATE_CKE |
985 GLAMO_MEM_DRAM1_SELF_REFRESH |
986 GLAMO_MEM_REFRESH_COUNT);
987
988 /* force RAM into deep powerdown */
989
990 __reg_write(glamo, GLAMO_REG_MEM_DRAM2,
991 GLAMO_MEM_DRAM2_DEEP_PWRDOWN |
992 (7 << 6) | /* tRC */
993 (1 << 4) | /* tRP */
994 (1 << 2) | /* tRCD */
995 2); /* CAS latency */
996
997 /* disable clocks to memory */
998 __reg_write(glamo, GLAMO_REG_CLOCK_MEMORY, 0);
999
1000 /* all dividers from OSCI */
1001 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1, 0x400, 0x400);
1002
1003 /* PLL2 into bypass */
1004 __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 12, 1 << 12);
1005
1006 __reg_write(glamo, 0x200, 0x0e00);
1007
1008
1009 /* kill PLLS 1 then 2 */
1010 __reg_write(glamo, GLAMO_REG_DFT_GEN5, 0x0001);
1011 __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 13, 1 << 13);
1012
1013 break;
1014 }
1015
1016 spin_unlock_irqrestore(&glamo->lock, flags);
1017 }
1018
1019 #if 0
1020 #define MEMDETECT_RETRY 6
1021 static unsigned int detect_memsize(struct glamo_core *glamo)
1022 {
1023 int i;
1024
1025 /*static const u_int16_t pattern[] = {
1026 0x1111, 0x8a8a, 0x2222, 0x7a7a,
1027 0x3333, 0x6a6a, 0x4444, 0x5a5a,
1028 0x5555, 0x4a4a, 0x6666, 0x3a3a,
1029 0x7777, 0x2a2a, 0x8888, 0x1a1a
1030 }; */
1031
1032 for (i = 0; i < MEMDETECT_RETRY; i++) {
1033 switch (glamo->type) {
1034 case 3600:
1035 __reg_write(glamo, GLAMO_REG_MEM_TYPE, 0x0072);
1036 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
1037 break;
1038 case 3650:
1039 switch (glamo->revision) {
1040 case GLAMO_CORE_REV_A0:
1041 if (i & 1)
1042 __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1043 0x097a);
1044 else
1045 __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1046 0x0173);
1047
1048 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
1049 msleep(1);
1050 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
1051 break;
1052 default:
1053 if (i & 1)
1054 __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1055 0x0972);
1056 else
1057 __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1058 0x0872);
1059
1060 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
1061 msleep(1);
1062 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xe100);
1063 break;
1064 }
1065 break;
1066 case 3700:
1067 /* FIXME */
1068 default:
1069 break;
1070 }
1071
1072 #if 0
1073 /* FIXME: finish implementation */
1074 for (j = 0; j < 8; j++) {
1075 __
1076 #endif
1077 }
1078
1079 return 0;
1080 }
1081 #endif
1082
1083 /* Find out if we can support this version of the Glamo chip */
1084 static int glamo_supported(struct glamo_core *glamo)
1085 {
1086 u_int16_t dev_id, rev_id; /*, memsize; */
1087
1088 dev_id = __reg_read(glamo, GLAMO_REG_DEVICE_ID);
1089 rev_id = __reg_read(glamo, GLAMO_REG_REVISION_ID);
1090
1091 switch (dev_id) {
1092 case 0x3650:
1093 switch (rev_id) {
1094 case GLAMO_CORE_REV_A2:
1095 break;
1096 case GLAMO_CORE_REV_A0:
1097 case GLAMO_CORE_REV_A1:
1098 case GLAMO_CORE_REV_A3:
1099 dev_warn(&glamo->pdev->dev, "untested core revision "
1100 "%04x, your mileage may vary\n", rev_id);
1101 break;
1102 default:
1103 dev_warn(&glamo->pdev->dev, "unknown glamo revision "
1104 "%04x, your mileage may vary\n", rev_id);
1105 /* maybe should abort ? */
1106 }
1107 break;
1108 case 0x3600:
1109 case 0x3700:
1110 default:
1111 dev_err(&glamo->pdev->dev, "unsupported Glamo device %04x\n",
1112 dev_id);
1113 return 0;
1114 }
1115
1116 dev_dbg(&glamo->pdev->dev, "Detected Glamo core %04x Revision %04x "
1117 "(%uHz CPU / %uHz Memory)\n", dev_id, rev_id,
1118 glamo_pll_rate(glamo, GLAMO_PLL1),
1119 glamo_pll_rate(glamo, GLAMO_PLL2));
1120
1121 return 1;
1122 }
1123
1124 static int __init glamo_probe(struct platform_device *pdev)
1125 {
1126 int rc = 0, irq;
1127 struct glamo_core *glamo;
1128
1129 glamo = kmalloc(GFP_KERNEL, sizeof(*glamo));
1130 if (!glamo)
1131 return -ENOMEM;
1132
1133 spin_lock_init(&glamo->lock);
1134 glamo->pdev = pdev;
1135 glamo->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1136 glamo->irq = platform_get_irq(pdev, 0);
1137 glamo->pdata = pdev->dev.platform_data;
1138 if (!glamo->mem || !glamo->pdata) {
1139 dev_err(&pdev->dev, "platform device with no MEM/PDATA ?\n");
1140 rc = -ENOENT;
1141 goto bail_free;
1142 }
1143
1144 /* register a number of sibling devices whoise IOMEM resources
1145 * are siblings of pdev's IOMEM resource */
1146
1147 /* only remap the generic, hostbus and memory controller registers */
1148 glamo->base = ioremap(glamo->mem->start, 0x4000 /*GLAMO_REGOFS_VIDCAP*/);
1149 if (!glamo->base) {
1150 dev_err(&pdev->dev, "failed to ioremap() memory region\n");
1151 goto bail_free;
1152 }
1153
1154 platform_set_drvdata(pdev, glamo);
1155
1156 (glamo->pdata->glamo_external_reset)(0);
1157 udelay(10);
1158 (glamo->pdata->glamo_external_reset)(1);
1159 mdelay(10);
1160
1161 /*
1162 * finally set the mfd interrupts up
1163 * can't do them earlier or sibling probes blow up
1164 */
1165
1166 for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1167 set_irq_chip_and_handler(irq, &glamo_irq_chip, handle_level_irq);
1168 set_irq_flags(irq, IRQF_VALID);
1169 set_irq_chip_data(irq, glamo);
1170 }
1171
1172 if (glamo->pdata->glamo_irq_is_wired &&
1173 !glamo->pdata->glamo_irq_is_wired()) {
1174 set_irq_chained_handler(glamo->irq, glamo_irq_demux_handler);
1175 set_irq_type(glamo->irq, IRQ_TYPE_EDGE_FALLING);
1176 set_irq_chip_data(glamo->irq, glamo);
1177 dev_info(&pdev->dev, "Glamo interrupt registered\n");
1178 glamo->irq_works = 1;
1179 } else {
1180 dev_err(&pdev->dev, "Glamo interrupt not used\n");
1181 glamo->irq_works = 0;
1182 }
1183
1184 /* confirm it isn't insane version */
1185 if (!glamo_supported(glamo)) {
1186 dev_err(&pdev->dev, "This Glamo is not supported\n");
1187 goto bail_irq;
1188 }
1189
1190 /* sysfs */
1191 rc = sysfs_create_group(&pdev->dev.kobj, &glamo_attr_group);
1192 if (rc < 0) {
1193 dev_err(&pdev->dev, "cannot create sysfs group\n");
1194 goto bail_irq;
1195 }
1196
1197 /* init the chip with canned register set */
1198
1199 dev_dbg(&glamo->pdev->dev, "running init script\n");
1200 glamo_run_script(glamo, glamo_init_script,
1201 ARRAY_SIZE(glamo_init_script), 1);
1202
1203 dev_info(&glamo->pdev->dev, "Glamo core PLL1: %uHz, PLL2: %uHz\n",
1204 glamo_pll_rate(glamo, GLAMO_PLL1),
1205 glamo_pll_rate(glamo, GLAMO_PLL2));
1206
1207 /* register siblings */
1208 glamo->pdata->mmc_data->core = glamo;
1209 glamo_cells[GLAMO_CELL_MMC].platform_data = glamo->pdata->mmc_data;
1210 glamo_cells[GLAMO_CELL_MMC].data_size =
1211 sizeof(struct glamo_mmc_platform_data);
1212
1213 glamo->pdata->fb_data->core = glamo;
1214 glamo_cells[GLAMO_CELL_FB].platform_data = glamo->pdata->fb_data;
1215 glamo_cells[GLAMO_CELL_FB].data_size = sizeof(struct glamo_fb_platform_data);
1216
1217 glamo->pdata->spigpio_data->core = glamo;
1218 glamo_cells[GLAMO_CELL_SPI_GPIO].platform_data =
1219 glamo->pdata->spigpio_data;
1220 glamo_cells[GLAMO_CELL_SPI_GPIO].data_size =
1221 sizeof(struct glamo_spigpio_platform_data);
1222
1223 mfd_add_devices(&pdev->dev, pdev->id, glamo_cells,
1224 ARRAY_SIZE(glamo_cells),
1225 glamo->mem, 0);
1226
1227 /* only request the generic, hostbus and memory controller MMIO */
1228 glamo->mem = request_mem_region(glamo->mem->start,
1229 GLAMO_REGOFS_VIDCAP, "glamo-core");
1230 if (!glamo->mem) {
1231 dev_err(&pdev->dev, "failed to request memory region\n");
1232 goto bail_irq;
1233 }
1234
1235 return 0;
1236
1237 bail_irq:
1238 disable_irq(glamo->irq);
1239 set_irq_chained_handler(glamo->irq, NULL);
1240 set_irq_chip_data(glamo->irq, NULL);
1241
1242 for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1243 set_irq_flags(irq, 0);
1244 set_irq_chip(irq, NULL);
1245 set_irq_chip_data(irq, NULL);
1246 }
1247
1248 iounmap(glamo->base);
1249 bail_free:
1250 platform_set_drvdata(pdev, NULL);
1251 kfree(glamo);
1252
1253 return rc;
1254 }
1255
1256 static int glamo_remove(struct platform_device *pdev)
1257 {
1258 struct glamo_core *glamo = platform_get_drvdata(pdev);
1259 int irq;
1260
1261 disable_irq(glamo->irq);
1262 set_irq_chained_handler(glamo->irq, NULL);
1263 set_irq_chip_data(glamo->irq, NULL);
1264
1265 for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1266 set_irq_flags(irq, 0);
1267 set_irq_chip(irq, NULL);
1268 set_irq_chip_data(irq, NULL);
1269 }
1270
1271 platform_set_drvdata(pdev, NULL);
1272 mfd_remove_devices(&pdev->dev);
1273 iounmap(glamo->base);
1274 release_mem_region(glamo->mem->start, GLAMO_REGOFS_VIDCAP);
1275 kfree(glamo);
1276
1277 return 0;
1278 }
1279
1280 #ifdef CONFIG_PM
1281
1282 static int glamo_suspend(struct device *dev)
1283 {
1284 struct glamo_core *glamo = dev_get_drvdata(dev);
1285 glamo->suspending = 1;
1286 glamo_power(glamo, GLAMO_POWER_SUSPEND);
1287
1288 return 0;
1289 }
1290
1291 static int glamo_resume(struct device *dev)
1292 {
1293 struct glamo_core *glamo = dev_get_drvdata(dev);
1294 glamo_power(glamo, GLAMO_POWER_ON);
1295 glamo->suspending = 0;
1296
1297 return 0;
1298 }
1299
1300 static struct dev_pm_ops glamo_pm_ops = {
1301 .suspend = glamo_suspend,
1302 .resume = glamo_resume,
1303 };
1304
1305 #define GLAMO_PM_OPS (&glamo_pm_ops)
1306
1307 #else
1308 #define GLAMO_PM_OPS NULL
1309 #endif
1310
1311 static struct platform_driver glamo_driver = {
1312 .probe = glamo_probe,
1313 .remove = glamo_remove,
1314 .driver = {
1315 .name = "glamo3362",
1316 .owner = THIS_MODULE,
1317 .pm = GLAMO_PM_OPS,
1318 },
1319 };
1320
1321 static int __devinit glamo_init(void)
1322 {
1323 return platform_driver_register(&glamo_driver);
1324 }
1325
1326 static void __exit glamo_cleanup(void)
1327 {
1328 platform_driver_unregister(&glamo_driver);
1329 }
1330
1331 module_init(glamo_init);
1332 module_exit(glamo_cleanup);
1333
1334 MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
1335 MODULE_DESCRIPTION("Smedia Glamo 336x/337x core/resource driver");
1336 MODULE_LICENSE("GPL");
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