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63 *******************************************************************************/
67 #ifndef __INCmvCommonh
68 #define __INCmvCommonh
74 /* 16bit nibble swap. For example 0x1234 -> 0x2143 */
75 #define MV_NIBBLE_SWAP_16BIT(X) (((X&0xf) << 4) | \
80 /* 32bit nibble swap. For example 0x12345678 -> 0x21436587 */
81 #define MV_NIBBLE_SWAP_32BIT(X) (((X&0xf) << 4) | \
85 ((X&0xf0000) << 4) | \
86 ((X&0xf00000) >> 4) | \
87 ((X&0xf000000) << 4) | \
88 ((X&0xf0000000) >> 4))
90 /* 16bit byte swap. For example 0x1122 -> 0x2211 */
91 #define MV_BYTE_SWAP_16BIT(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8))
93 /* 32bit byte swap. For example 0x11223344 -> 0x44332211 */
94 #define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \
96 (((X)&0xff0000)>>8) | \
97 (((X)&0xff000000)>>24))
99 /* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211 */
100 #define MV_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xffULL)<<56) | \
101 (((X)&0xff00ULL)<<40) | \
102 (((X)&0xff0000ULL)<<24) | \
103 (((X)&0xff000000ULL)<<8) | \
104 (((X)&0xff00000000ULL)>>8) | \
105 (((X)&0xff0000000000ULL)>>24) | \
106 (((X)&0xff000000000000ULL)>>40) | \
107 (((X)&0xff00000000000000ULL)>>56)))
109 /* Endianess macros. */
110 #if defined(MV_CPU_LE)
111 #define MV_16BIT_LE(X) (X)
112 #define MV_32BIT_LE(X) (X)
113 #define MV_64BIT_LE(X) (X)
114 #define MV_16BIT_BE(X) MV_BYTE_SWAP_16BIT(X)
115 #define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X)
116 #define MV_64BIT_BE(X) MV_BYTE_SWAP_64BIT(X)
117 #elif defined(MV_CPU_BE)
118 #define MV_16BIT_LE(X) MV_BYTE_SWAP_16BIT(X)
119 #define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X)
120 #define MV_64BIT_LE(X) MV_BYTE_SWAP_64BIT(X)
121 #define MV_16BIT_BE(X) (X)
122 #define MV_32BIT_BE(X) (X)
123 #define MV_64BIT_BE(X) (X)
125 #error "CPU endianess isn't defined!\n"
129 /* Bit field definitions */
130 #define NO_BIT 0x00000000
131 #define BIT0 0x00000001
132 #define BIT1 0x00000002
133 #define BIT2 0x00000004
134 #define BIT3 0x00000008
135 #define BIT4 0x00000010
136 #define BIT5 0x00000020
137 #define BIT6 0x00000040
138 #define BIT7 0x00000080
139 #define BIT8 0x00000100
140 #define BIT9 0x00000200
141 #define BIT10 0x00000400
142 #define BIT11 0x00000800
143 #define BIT12 0x00001000
144 #define BIT13 0x00002000
145 #define BIT14 0x00004000
146 #define BIT15 0x00008000
147 #define BIT16 0x00010000
148 #define BIT17 0x00020000
149 #define BIT18 0x00040000
150 #define BIT19 0x00080000
151 #define BIT20 0x00100000
152 #define BIT21 0x00200000
153 #define BIT22 0x00400000
154 #define BIT23 0x00800000
155 #define BIT24 0x01000000
156 #define BIT25 0x02000000
157 #define BIT26 0x04000000
158 #define BIT27 0x08000000
159 #define BIT28 0x10000000
160 #define BIT29 0x20000000
161 #define BIT30 0x40000000
162 #define BIT31 0x80000000
165 #define _1K 0x00000400
166 #define _2K 0x00000800
167 #define _4K 0x00001000
168 #define _8K 0x00002000
169 #define _16K 0x00004000
170 #define _32K 0x00008000
171 #define _64K 0x00010000
172 #define _128K 0x00020000
173 #define _256K 0x00040000
174 #define _512K 0x00080000
176 #define _1M 0x00100000
177 #define _2M 0x00200000
178 #define _4M 0x00400000
179 #define _8M 0x00800000
180 #define _16M 0x01000000
181 #define _32M 0x02000000
182 #define _64M 0x04000000
183 #define _128M 0x08000000
184 #define _256M 0x10000000
185 #define _512M 0x20000000
187 #define _1G 0x40000000
188 #define _2G 0x80000000
190 /* Tclock and Sys clock define */
191 #define _100MHz 100000000
192 #define _125MHz 125000000
193 #define _133MHz 133333334
194 #define _150MHz 150000000
195 #define _160MHz 160000000
196 #define _166MHz 166666667
197 #define _175MHz 175000000
198 #define _178MHz 178000000
199 #define _183MHz 183333334
200 #define _187MHz 187000000
201 #define _192MHz 192000000
202 #define _194MHz 194000000
203 #define _200MHz 200000000
204 #define _233MHz 233333334
205 #define _250MHz 250000000
206 #define _266MHz 266666667
207 #define _300MHz 300000000
209 /* For better address window table readability */
212 #define N_A -1 /* Not applicable */
214 /* Cache configuration options for memory (DRAM, SRAM, ... ) */
216 /* Memory uncached, HW or SW cache coherency is not needed */
217 #define MV_UNCACHED 0
218 /* Memory cached, HW cache coherency supported in WriteThrough mode */
219 #define MV_CACHE_COHER_HW_WT 1
220 /* Memory cached, HW cache coherency supported in WriteBack mode */
221 #define MV_CACHE_COHER_HW_WB 2
222 /* Memory cached, No HW cache coherency, Cache coherency must be in SW */
223 #define MV_CACHE_COHER_SW 3
226 /* Macro for testing aligment. Positive if number is NOT aligned */
227 #define MV_IS_NOT_ALIGN(number, align) ((number) & ((align) - 1))
229 /* Macro for alignment up. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0340 */
230 #define MV_ALIGN_UP(number, align) \
231 (((number) & ((align) - 1)) ? (((number) + (align)) & ~((align)-1)) : (number))
233 /* Macro for alignment down. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0320 */
234 #define MV_ALIGN_DOWN(number, align) ((number) & ~((align)-1))
236 /* This macro returns absolute value */
237 #define MV_ABS(number) (((int)(number) < 0) ? -(int)(number) : (int)(number))
240 /* Bit fields manipulation macros */
242 /* An integer word which its 'x' bit is set */
243 #define MV_BIT_MASK(bitNum) (1 << (bitNum) )
245 /* Checks wheter bit 'x' in integer word is set */
246 #define MV_BIT_CHECK(word, bitNum) ( (word) & MV_BIT_MASK(bitNum) )
248 /* Clear (reset) bit 'x' in integer word (RMW - Read-Modify-Write) */
249 #define MV_BIT_CLEAR(word, bitNum) ( (word) &= ~(MV_BIT_MASK(bitNum)) )
251 /* Set bit 'x' in integer word (RMW) */
252 #define MV_BIT_SET(word, bitNum) ( (word) |= MV_BIT_MASK(bitNum) )
254 /* Invert bit 'x' in integer word (RMW) */
255 #define MV_BIT_INV(word, bitNum) ( (word) ^= MV_BIT_MASK(bitNum) )
257 /* Get the min between 'a' or 'b' */
258 #define MV_MIN(a,b) (((a) < (b)) ? (a) : (b))
260 /* Get the max between 'a' or 'b' */
261 #define MV_MAX(a,b) (((a) < (b)) ? (b) : (a))
264 #define mvOsDivide(num, div) \
266 int i=0, rem=(num); \
268 while(rem >= (div)) \
277 #define mvOsReminder(num, div) \
281 while(rem >= (div)) \
286 #define MV_IP_QUAD(ipAddr) ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), \
287 ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF)
289 #define MV_IS_POWER_OF_2(num) ((num != 0) && ((num & (num - 1)) == 0))
291 #ifndef MV_ASMLANGUAGE
292 /* mvCommon API list */
294 MV_VOID
mvHexToBin(const char* pHexStr
, MV_U8
* pBin
, int size
);
295 void mvAsciiToHex(const char* asciiStr
, char* hexStr
);
296 void mvBinToHex(const MV_U8
* bin
, char* hexStr
, int size
);
297 void mvBinToAscii(const MV_U8
* bin
, char* asciiStr
, int size
);
299 MV_STATUS
mvMacStrToHex(const char* macStr
, MV_U8
* macHex
);
300 MV_STATUS
mvMacHexToStr(MV_U8
* macHex
, char* macStr
);
301 void mvSizePrint(MV_U32
);
303 MV_U32
mvLog2(MV_U32 num
);
305 #endif /* MV_ASMLANGUAGE */
308 #endif /* __INCmvCommonh */
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