1 From fa0f89c9cf9ceecc3feac1d96914c8e91f98d90f Mon Sep 17 00:00:00 2001
2 From: Kurt Mahan <kmahan@freescale.com>
3 Date: Wed, 31 Oct 2007 16:43:01 -0600
4 Subject: [PATCH] Add MCF5445x Specific Header Files.
6 LTIBName: m5445x-headers
7 Signed-off-by: Kurt Mahan <kmahan@freescale.com>
9 include/asm-m68k/mcf5445x_ccm.h | 161 ++++
10 include/asm-m68k/mcf5445x_dspi.h | 402 ++++++++++
11 include/asm-m68k/mcf5445x_dtim.h | 87 +++
12 include/asm-m68k/mcf5445x_edma.h | 1458 ++++++++++++++++++++++++++++++++++++
13 include/asm-m68k/mcf5445x_eport.h | 117 +++
14 include/asm-m68k/mcf5445x_fbcs.h | 182 +++++
15 include/asm-m68k/mcf5445x_gpio.h | 1257 +++++++++++++++++++++++++++++++
16 include/asm-m68k/mcf5445x_i2c.h | 39 +
17 include/asm-m68k/mcf5445x_intc.h | 724 ++++++++++++++++++
18 include/asm-m68k/mcf5445x_pci.h | 238 ++++++
19 include/asm-m68k/mcf5445x_pciarb.h | 40 +
20 include/asm-m68k/mcf5445x_sdramc.h | 115 +++
21 include/asm-m68k/mcf5445x_ssi.h | 187 +++++
22 include/asm-m68k/mcf5445x_usb.h | 49 ++
23 14 files changed, 5056 insertions(+), 0 deletions(-)
24 create mode 100644 include/asm-m68k/mcf5445x_ccm.h
25 create mode 100644 include/asm-m68k/mcf5445x_dspi.h
26 create mode 100644 include/asm-m68k/mcf5445x_dtim.h
27 create mode 100644 include/asm-m68k/mcf5445x_edma.h
28 create mode 100644 include/asm-m68k/mcf5445x_eport.h
29 create mode 100644 include/asm-m68k/mcf5445x_fbcs.h
30 create mode 100644 include/asm-m68k/mcf5445x_gpio.h
31 create mode 100644 include/asm-m68k/mcf5445x_i2c.h
32 create mode 100644 include/asm-m68k/mcf5445x_intc.h
33 create mode 100644 include/asm-m68k/mcf5445x_pci.h
34 create mode 100644 include/asm-m68k/mcf5445x_pciarb.h
35 create mode 100644 include/asm-m68k/mcf5445x_sdramc.h
36 create mode 100644 include/asm-m68k/mcf5445x_ssi.h
37 create mode 100644 include/asm-m68k/mcf5445x_usb.h
40 +++ b/include/asm-m68k/mcf5445x_ccm.h
43 + * Matt Waddel Matt.Waddel@freescale.com
45 + * Copyright Freescale Semiconductor, Inc. 2007
47 + * This program is free software; you can redistribute it and/or modify it
48 + * under the terms of the GNU General Public License as published by the
49 + * Free Software Foundation; either version 2 of the License, or (at your
50 + * option) any later version.
53 +#ifndef __MCF5445X_CCM_H__
54 +#define __MCF5445X_CCM_H__
56 +/*********************************************************************
58 +* Chip Configuration Module (CCM)
60 +*********************************************************************/
62 +/* Register read/write macros */
63 +#define MCF_CCM_CCR MCF_REG16(0xFC0A0004) /* Chip Configuration Register (Read-only) (256 or 360 TEPBGA) */
64 +#define MCF_CCM_RCON MCF_REG16(0xFC0A0008) /* Reset Configuration (Read-only) (256 or 360 TEPBGA) */
65 +#define MCF_CCM_CIR MCF_REG16(0xFC0A000A) /* Chip Identification Register (Read-only) */
66 +#define MCF_CCM_MISCCR MCF_REG16(0xFC0A0010) /* Miscellaneous Control Register */
67 +#define MCF_CCM_CDR MCF_REG16(0xFC0A0012) /* Clock Divider Register */
68 +#define MCF_CCM_UOCSR MCF_REG16(0xFC0A0014) /* USB On-the-Go Controller Status Register */
69 +#define MCF_CCM_SBFSR MCF_REG16(0xFC0A0018) /* Serial Boot Facility Status Register (Read Only) */
70 +#define MCF_CCM_SBFCR MCF_REG16(0xFC0A0020) /* Serial Boot Facility Control Register */
72 +/* Bit definitions and macros for CCR_360 */
73 +#define MCF_CCM_CCR_360_PLLMULT2(x) (((x) & 0x0003)) /* 2-Bit PLL clock mode */
74 +#define MCF_CCM_CCR_360_PCISLEW (0x0004) /* PCI pad slew rate mode */
75 +#define MCF_CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */
76 +#define MCF_CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */
77 +#define MCF_CCM_CCR_360_FBCONFIG(x) (((x) & 0x0007) << 5) /* Flexbus/PCI port size configuration */
78 +#define MCF_CCM_CCR_360_PLLMULT3(x) (((x) & 0x0007)) /* 3-Bit PLL Clock Mode */
79 +#define MCF_CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */
80 +#define MCF_CCM_CCR_360_FBCONFIG_MASK (0x00E0)
81 +#define MCF_CCM_CCR_360_PLLMULT2_MASK (0x0003)
82 +#define MCF_CCM_CCR_360_PLLMULT3_MASK (0x0007)
83 +#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000)
84 +#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020)
85 +#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040)
86 +#define MCF_CCM_CCR_360_FBCONFIG_M_P_16 (0x0060)
87 +#define MCF_CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080)
88 +#define MCF_CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0)
89 +#define MCF_CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0)
90 +#define MCF_CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0)
91 +#define MCF_CCM_CCR_360_PLLMULT2_12X (0x0000)
92 +#define MCF_CCM_CCR_360_PLLMULT2_6X (0x0001)
93 +#define MCF_CCM_CCR_360_PLLMULT2_16X (0x0002)
94 +#define MCF_CCM_CCR_360_PLLMULT2_8X (0x0003)
95 +#define MCF_CCM_CCR_360_PLLMULT3_20X (0x0000)
96 +#define MCF_CCM_CCR_360_PLLMULT3_10X (0x0001)
97 +#define MCF_CCM_CCR_360_PLLMULT3_24X (0x0002)
98 +#define MCF_CCM_CCR_360_PLLMULT3_18X (0x0003)
99 +#define MCF_CCM_CCR_360_PLLMULT3_12X (0x0004)
100 +#define MCF_CCM_CCR_360_PLLMULT3_6X (0x0005)
101 +#define MCF_CCM_CCR_360_PLLMULT3_16X (0x0006)
102 +#define MCF_CCM_CCR_360_PLLMULT3_8X (0x0007)
104 +/* Bit definitions and macros for CCR_256 */
105 +#define MCF_CCM_CCR_256_PLLMULT3(x) (((x) & 0x0007)) /* 3-Bit PLL clock mode */
106 +#define MCF_CCM_CCR_256_OSCMODE (0x0008) /* Oscillator clock mode */
107 +#define MCF_CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */
108 +#define MCF_CCM_CCR_256_FBCONFIG(x) (((x) & 0x0007) << 5) /* Flexbus/PCI port size configuration */
109 +#define MCF_CCM_CCR_256_FBCONFIG_MASK (0x00E0)
110 +#define MCF_CCM_CCR_256_FBCONFIG_NM_32 (0x0000)
111 +#define MCF_CCM_CCR_256_FBCONFIG_NM_8 (0x0020)
112 +#define MCF_CCM_CCR_256_FBCONFIG_NM_16 (0x0040)
113 +#define MCF_CCM_CCR_256_FBCONFIG_M_32 (0x0080)
114 +#define MCF_CCM_CCR_256_FBCONFIG_M_8 (0x00A0)
115 +#define MCF_CCM_CCR_256_FBCONFIG_M_16 (0x00C0)
116 +#define MCF_CCM_CCR_256_PLLMULT3_MASK (0x0007)
117 +#define MCF_CCM_CCR_256_PLLMULT3_20X (0x0000)
118 +#define MCF_CCM_CCR_256_PLLMULT3_10X (0x0001)
119 +#define MCF_CCM_CCR_256_PLLMULT3_24X (0x0002)
120 +#define MCF_CCM_CCR_256_PLLMULT3_18X (0x0003)
121 +#define MCF_CCM_CCR_256_PLLMULT3_12X (0x0004)
122 +#define MCF_CCM_CCR_256_PLLMULT3_6X (0x0005)
123 +#define MCF_CCM_CCR_256_PLLMULT3_16X (0x0006)
124 +#define MCF_CCM_CCR_256_PLLMULT3_8X (0x0007)
126 +/* Bit definitions and macros for RCON_360 */
127 +#define MCF_CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */
128 +#define MCF_CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */
129 +#define MCF_CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */
130 +#define MCF_CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */
131 +#define MCF_CCM_RCON_360_FBCONFIG(x) (((x) & 0x0007) << 5) /* Flexbus/PCI port size configuration */
133 +/* Bit definitions and macros for RCON_256 */
134 +#define MCF_CCM_RCON_256_PLLMULT(x) (((x) & 0x0007)) /* PLL clock mode */
135 +#define MCF_CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */
136 +#define MCF_CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */
137 +#define MCF_CCM_RCON_256_FBCONFIG(x) (((x) & 0x0007) << 5) /* Flexbus/PCI port size configuration */
139 +/* Bit definitions and macros for CIR */
140 +#define MCF_CCM_CIR_PRN(x) (((x) & 0x003F)) /* Part revision number */
141 +#define MCF_CCM_CIR_PIN(x) (((x) & 0x03FF) << 6) /* Part identification number */
142 +#define MCF_CCM_CIR_PIN_MASK (0xFFC0)
143 +#define MCF_CCM_CIR_PRN_MASK (0x003F)
144 +#define MCF_CCM_CIR_PIN_MCF54450 (0x4F << 6)
145 +#define MCF_CCM_CIR_PIN_MCF54451 (0x4D << 6)
146 +#define MCF_CCM_CIR_PIN_MCF54452 (0x4B << 6)
147 +#define MCF_CCM_CIR_PIN_MCF54453 (0x49 << 6)
148 +#define MCF_CCM_CIR_PIN_MCF54454 (0x4A << 6)
149 +#define MCF_CCM_CIR_PIN_MCF54455 (0x48 << 6)
151 +/* Bit definitions and macros for MISCCR */
152 +#define MCF_CCM_MISCCR_USBSRC (0x0001) /* USB clock source */
153 +#define MCF_CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense polarity */
154 +#define MCF_CCM_MISCCR_USBPUE (0x0004) /* USB transceiver pull-up enable */
155 +#define MCF_CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */
156 +#define MCF_CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */
157 +#define MCF_CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */
158 +#define MCF_CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */
159 +#define MCF_CCM_MISCCR_BMT(x) (((x) & 0x0007) << 8) /* Bus monitor timing field */
160 +#define MCF_CCM_MISCCR_BME (0x0800) /* Bus monitor external enable bit */
161 +#define MCF_CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */
162 +#define MCF_CCM_MISCCR_BMT_65536 (0)
163 +#define MCF_CCM_MISCCR_BMT_32768 (1)
164 +#define MCF_CCM_MISCCR_BMT_16384 (2)
165 +#define MCF_CCM_MISCCR_BMT_8192 (3)
166 +#define MCF_CCM_MISCCR_BMT_4096 (4)
167 +#define MCF_CCM_MISCCR_BMT_2048 (5)
168 +#define MCF_CCM_MISCCR_BMT_1024 (6)
169 +#define MCF_CCM_MISCCR_BMT_512 (7)
170 +#define MCF_CCM_MISCCR_SSIPUS_UP (1)
171 +#define MCF_CCM_MISCCR_SSIPUS_DOWN (0)
172 +#define MCF_CCM_MISCCR_TIMDMA_TIM (1)
173 +#define MCF_CCM_MISCCR_TIMDMA_SSI (0)
174 +#define MCF_CCM_MISCCR_SSISRC_CLKIN (0)
175 +#define MCF_CCM_MISCCR_SSISRC_PLL (1)
176 +#define MCF_CCM_MISCCR_USBOC_ACTHI (0)
177 +#define MCF_CCM_MISCCR_USBOV_ACTLO (1)
178 +#define MCF_CCM_MISCCR_USBSRC_CLKIN (0)
179 +#define MCF_CCM_MISCCR_USBSRC_PLL (1)
181 +/* Bit definitions and macros for CDR */
182 +#define MCF_CCM_CDR_SSIDIV(x) (((x) & 0x00FF)) /* SSI oversampling clock divider */
183 +#define MCF_CCM_CDR_LPDIV(x) (((x) & 0x000F) << 8) /* Low power clock divider */
185 +/* Bit definitions and macros for UOCSR */
186 +#define MCF_CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down enable */
187 +#define MCF_CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt enable */
188 +#define MCF_CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */
189 +#define MCF_CCM_UOCSR_PWRFLT (0x0008) /* VBUS power fault */
190 +#define MCF_CCM_UOCSR_SEND (0x0010) /* Session end */
191 +#define MCF_CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */
192 +#define MCF_CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */
193 +#define MCF_CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */
194 +#define MCF_CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (read-only) */
195 +#define MCF_CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor enabled (read-only) */
196 +#define MCF_CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (read-only) */
197 +#define MCF_CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (read-only) */
198 +#define MCF_CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (read-only) */
200 +/********************************************************************/
202 +#endif /* __MCF5445X_CCM_H__ */
204 +++ b/include/asm-m68k/mcf5445x_dspi.h
207 + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
209 + * Copyright Freescale Semiconductor, Inc. 2007
211 + * This program is free software; you can redistribute it and/or modify it
212 + * under the terms of the GNU General Public License as published by the
213 + * Free Software Foundation; either version 2 of the License, or (at your
214 + * option) any later version.
217 +#ifndef __MCF5445X_DSPI_H__
218 +#define __MCF5445X_DSPI_H__
220 +/*********************************************************************
222 +* DMA Serial Peripheral Interface (DSPI)
224 +*********************************************************************/
226 +/* Register read/write macros */
227 +#define MCF_DSPI_DMCR MCF_REG32(0xFC05C000) /* DSPI Module Configuration Register */
228 +#define MCF_DSPI_DTCR MCF_REG32(0xFC05C008) /* DSPI Transfer Count Register */
229 +#define MCF_DSPI_DCTAR0 MCF_REG32(0xFC05C00C) /* DSPI Clock and Transfer Attributes Register */
230 +#define MCF_DSPI_DCTAR1 MCF_REG32(0xFC05C010) /* DSPI Clock and Transfer Attributes Register */
231 +#define MCF_DSPI_DCTAR2 MCF_REG32(0xFC05C014) /* DSPI Clock and Transfer Attributes Register */
232 +#define MCF_DSPI_DCTAR3 MCF_REG32(0xFC05C018) /* DSPI Clock and Transfer Attributes Register */
233 +#define MCF_DSPI_DCTAR4 MCF_REG32(0xFC05C01C) /* DSPI Clock and Transfer Attributes Register */
234 +#define MCF_DSPI_DCTAR5 MCF_REG32(0xFC05C020) /* DSPI Clock and Transfer Attributes Register */
235 +#define MCF_DSPI_DCTAR6 MCF_REG32(0xFC05C024) /* DSPI Clock and Transfer Attributes Register */
236 +#define MCF_DSPI_DCTAR7 MCF_REG32(0xFC05C028) /* DSPI Clock and Transfer Attributes Register */
237 +#define MCF_DSPI_DSR MCF_REG32(0xFC05C02C) /* DSPI Status Register */
238 +#define MCF_DSPI_DRSER MCF_REG32(0xFC05C030) /* DSPI DMA/Interrupt Request Select and Enable Register */
239 +#define MCF_DSPI_DTFR MCF_REG32(0xFC05C034) /* DSPI Transmit FIFO Register */
240 +#define MCF_DSPI_DRFR MCF_REG32(0xFC05C038) /* DSPI Receive FIFO Register */
241 +#define MCF_DSPI_DTFDR0 MCF_REG32(0xFC05C03C) /* DSPI Transmit FIFO Debugging Registers */
242 +#define MCF_DSPI_DTFDR1 MCF_REG32(0xFC05C040) /* DSPI Transmit FIFO Debugging Registers */
243 +#define MCF_DSPI_DTFDR2 MCF_REG32(0xFC05C044) /* DSPI Transmit FIFO Debugging Registers */
244 +#define MCF_DSPI_DTFDR3 MCF_REG32(0xFC05C048) /* DSPI Transmit FIFO Debugging Registers */
245 +#define MCF_DSPI_DRFDR0 MCF_REG32(0xFC05C07C) /* DSPI Receive FIFO Debugging Registers */
246 +#define MCF_DSPI_DRFDR1 MCF_REG32(0xFC05C080) /* DSPI Receive FIFO Debugging Registers */
247 +#define MCF_DSPI_DRFDR2 MCF_REG32(0xFC05C084) /* DSPI Receive FIFO Debugging Registers */
248 +#define MCF_DSPI_DRFDR3 MCF_REG32(0xFC05C088) /* DSPI Receive FIFO Debugging Registers */
250 +/* Parameterized register read/write macros for multiple registers */
251 +#define MCF_DSPI_DCTAR(x) MCF_REG32(0xFC05C00C+((x)*0x004)) /* DSPI Clock and Transfer Attributes Register */
252 +#define MCF_DSPI_DTFDR(x) MCF_REG32(0xFC05C03C+((x)*0x004)) /* DSPI Transmit FIFO Debugging Registers */
253 +#define MCF_DSPI_DRFDR(x) MCF_REG32(0xFC05C07C+((x)*0x004)) /* DSPI Receive FIFO Debugging Registers */
255 +/* Bit definitions and macros for DMCR */
256 +#define MCF_DSPI_DMCR_HALT (0x00000001) /* Halt -- stops and starts DSPI transfers */
257 +#define MCF_DSPI_DMCR_SMPLPT(x) (((x)&0x00000003)<<8) /* Sample point selection */
258 +#define MCF_DSPI_DMCR_CLRRXF (0x00000400) /* Clear receive FIFO */
259 +#define MCF_DSPI_DMCR_CLRTXF (0x00000800) /* Clear transmit FIFO */
260 +#define MCF_DSPI_DMCR_DISRXF (0x00001000) /* Disable receive FIFO */
261 +#define MCF_DSPI_DMCR_DISTXF (0x00002000) /* Disable transmit FIFO */
262 +#define MCF_DSPI_DMCR_MDIS (0x00004000) /* Module Disable */
263 +#define MCF_DSPI_DMCR_PCSIS0 (0x00010000) /* Peripheral chip-select 0 inactive state */
264 +#define MCF_DSPI_DMCR_PCSIS1 (0x00020000) /* Peripheral chip-select 1 inactive state */
265 +#define MCF_DSPI_DMCR_PCSIS2 (0x00040000) /* Peripheral chip-select 2 inactive state */
266 +#define MCF_DSPI_DMCR_PCSIS3 (0x00080000) /* Peripheral chip-select 3 inactive state */
267 +#define MCF_DSPI_DMCR_PCSIS4 (0x00100000) /* Peripheral chip-select 4 inactive state */
268 +#define MCF_DSPI_DMCR_PCSIS5 (0x00200000) /* Peripheral chip-select 5 inactive state */
269 +#define MCF_DSPI_DMCR_PCSIS6 (0x00400000) /* Peripheral chip-select 6 inactive state */
270 +#define MCF_DSPI_DMCR_PCSIS7 (0x00800000) /* Peripheral chip-select 7 inactive state */
271 +#define MCF_DSPI_DMCR_ROOE (0x01000000) /* Receive FIFO overflow overwrite enable */
272 +#define MCF_DSPI_DMCR_PCSSE (0x02000000) /* Peripheral chip select strobe enable */
273 +#define MCF_DSPI_DMCR_MTFE (0x04000000) /* Modified timing format enable */
274 +#define MCF_DSPI_DMCR_FRZ (0x08000000) /* Freeze */
275 +#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) /* DSPI configuration */
276 +#define MCF_DSPI_DMCR_CONT_SCKE (0x40000000) /* Continuous SCK enable */
277 +#define MCF_DSPI_DMCR_MSTR (0x80000000) /* Master/Slave mode select */
278 +#define MCF_DSPI_DMCR_DCONF_SPI (0x00000000)
279 +#define MCF_DSPI_DMCR_PCSIS7_LOW (0x00000000)
280 +#define MCF_DSPI_DMCR_PCSIS7_HIGH (0x00800000)
281 +#define MCF_DSPI_DMCR_PCSIS6_LOW (0x00000000)
282 +#define MCF_DSPI_DMCR_PCSIS6_HIGH (0x00400000)
283 +#define MCF_DSPI_DMCR_PCSIS5_LOW (0x00000000)
284 +#define MCF_DSPI_DMCR_PCSIS5_HIGH (0x00200000)
285 +#define MCF_DSPI_DMCR_PCSIS4_LOW (0x00000000)
286 +#define MCF_DSPI_DMCR_PCSIS4_HIGH (0x00100000)
287 +#define MCF_DSPI_DMCR_PCSIS3_LOW (0x00000000)
288 +#define MCF_DSPI_DMCR_PCSIS3_HIGH (0x00080000)
289 +#define MCF_DSPI_DMCR_PCSIS2_LOW (0x00000000)
290 +#define MCF_DSPI_DMCR_PCSIS2_HIGH (0x00040000)
291 +#define MCF_DSPI_DMCR_PCSIS1_LOW (0x00000000)
292 +#define MCF_DSPI_DMCR_PCSIS1_HIGH (0x00020000)
293 +#define MCF_DSPI_DMCR_PCSIS0_LOW (0x00000000)
294 +#define MCF_DSPI_DMCR_PCSIS0_HIGH (0x00010000)
296 +/* Bit definitions and macros for DTCR */
297 +#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) /* SPI transfer count */
299 +/* Bit definitions and macros for DCTAR group */
300 +#define MCF_DSPI_DCTAR_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
301 +#define MCF_DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
302 +#define MCF_DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
303 +#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
304 +#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
305 +#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
306 +#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
307 +#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
308 +#define MCF_DSPI_DCTAR_LSBFE (0x01000000) /* LSB first enable */
309 +#define MCF_DSPI_DCTAR_CPHA (0x02000000) /* Clock phase */
310 +#define MCF_DSPI_DCTAR_CPOL (0x04000000) /* Clock polarity */
311 +#define MCF_DSPI_DCTAR_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
312 +#define MCF_DSPI_DCTAR_DBR (0x80000000) /* Double baud rate */
313 +#define MCF_DSPI_DCTAR_CPOL_LOW (0x00000000)
314 +#define MCF_DSPI_DCTAR_CPOL_HIGH (0x04000000)
315 +#define MCF_DSPI_DCTAR_CPHA_LATCH_RISING (0x00000000)
316 +#define MCF_DSPI_DCTAR_CPHA_LATCH_FALLING (0x02000000)
317 +#define MCF_DSPI_DCTAR_PCSSCK_1CLK (0x00000000)
318 +#define MCF_DSPI_DCTAR_PCSSCK_3CLK (0x00400000)
319 +#define MCF_DSPI_DCTAR_PCSSCK_5CLK (0x00800000)
320 +#define MCF_DSPI_DCTAR_PCSSCK_7CLK (0x00C00000)
321 +#define MCF_DSPI_DCTAR_PASC_1CLK (0x00000000)
322 +#define MCF_DSPI_DCTAR_PASC_3CLK (0x00100000)
323 +#define MCF_DSPI_DCTAR_PASC_5CLK (0x00200000)
324 +#define MCF_DSPI_DCTAR_PASC_7CLK (0x00300000)
325 +#define MCF_DSPI_DCTAR_PDT_1CLK (0x00000000)
326 +#define MCF_DSPI_DCTAR_PDT_3CLK (0x00040000)
327 +#define MCF_DSPI_DCTAR_PDT_5CLK (0x00080000)
328 +#define MCF_DSPI_DCTAR_PDT_7CLK (0x000C0000)
329 +#define MCF_DSPI_DCTAR_PBR_2CLK (0x00000000)
330 +#define MCF_DSPI_DCTAR_PBR_3CLK (0x00010000)
331 +#define MCF_DSPI_DCTAR_PBR_5CLK (0x00020000)
332 +#define MCF_DSPI_DCTAR_PBR_7CLK (0x00030000)
334 +/* Bit definitions and macros for DCTAR0 */
335 +#define MCF_DSPI_DCTAR0_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
336 +#define MCF_DSPI_DCTAR0_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
337 +#define MCF_DSPI_DCTAR0_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
338 +#define MCF_DSPI_DCTAR0_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
339 +#define MCF_DSPI_DCTAR0_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
340 +#define MCF_DSPI_DCTAR0_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
341 +#define MCF_DSPI_DCTAR0_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
342 +#define MCF_DSPI_DCTAR0_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
343 +#define MCF_DSPI_DCTAR0_LSBFE (0x01000000) /* LSB first enable */
344 +#define MCF_DSPI_DCTAR0_CPHA (0x02000000) /* Clock phase */
345 +#define MCF_DSPI_DCTAR0_CPOL (0x04000000) /* Clock polarity */
346 +#define MCF_DSPI_DCTAR0_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
347 +#define MCF_DSPI_DCTAR0_DBR (0x80000000) /* Double baud rate */
348 +#define MCF_DSPI_DCTAR0_CPOL_LOW (0x00000000)
349 +#define MCF_DSPI_DCTAR0_CPOL_HIGH (0x04000000)
350 +#define MCF_DSPI_DCTAR0_CPHA_LATCH_RISING (0x00000000)
351 +#define MCF_DSPI_DCTAR0_CPHA_LATCH_FALLING (0x02000000)
352 +#define MCF_DSPI_DCTAR0_PCSSCK_1CLK (0x00000000)
353 +#define MCF_DSPI_DCTAR0_PCSSCK_3CLK (0x00400000)
354 +#define MCF_DSPI_DCTAR0_PCSSCK_5CLK (0x00800000)
355 +#define MCF_DSPI_DCTAR0_PCSSCK_7CLK (0x00C00000)
356 +#define MCF_DSPI_DCTAR0_PASC_1CLK (0x00000000)
357 +#define MCF_DSPI_DCTAR0_PASC_3CLK (0x00100000)
358 +#define MCF_DSPI_DCTAR0_PASC_5CLK (0x00200000)
359 +#define MCF_DSPI_DCTAR0_PASC_7CLK (0x00300000)
360 +#define MCF_DSPI_DCTAR0_PDT_1CLK (0x00000000)
361 +#define MCF_DSPI_DCTAR0_PDT_3CLK (0x00040000)
362 +#define MCF_DSPI_DCTAR0_PDT_5CLK (0x00080000)
363 +#define MCF_DSPI_DCTAR0_PDT_7CLK (0x000C0000)
364 +#define MCF_DSPI_DCTAR0_PBR_2CLK (0x00000000)
365 +#define MCF_DSPI_DCTAR0_PBR_3CLK (0x00010000)
366 +#define MCF_DSPI_DCTAR0_PBR_5CLK (0x00020000)
367 +#define MCF_DSPI_DCTAR0_PBR_7CLK (0x00030000)
369 +/* Bit definitions and macros for DCTAR1 */
370 +#define MCF_DSPI_DCTAR1_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
371 +#define MCF_DSPI_DCTAR1_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
372 +#define MCF_DSPI_DCTAR1_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
373 +#define MCF_DSPI_DCTAR1_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
374 +#define MCF_DSPI_DCTAR1_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
375 +#define MCF_DSPI_DCTAR1_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
376 +#define MCF_DSPI_DCTAR1_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
377 +#define MCF_DSPI_DCTAR1_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
378 +#define MCF_DSPI_DCTAR1_LSBFE (0x01000000) /* LSB first enable */
379 +#define MCF_DSPI_DCTAR1_CPHA (0x02000000) /* Clock phase */
380 +#define MCF_DSPI_DCTAR1_CPOL (0x04000000) /* Clock polarity */
381 +#define MCF_DSPI_DCTAR1_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
382 +#define MCF_DSPI_DCTAR1_DBR (0x80000000) /* Double baud rate */
384 +/* Bit definitions and macros for DCTAR2 */
385 +#define MCF_DSPI_DCTAR2_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
386 +#define MCF_DSPI_DCTAR2_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
387 +#define MCF_DSPI_DCTAR2_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
388 +#define MCF_DSPI_DCTAR2_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
389 +#define MCF_DSPI_DCTAR2_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
390 +#define MCF_DSPI_DCTAR2_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
391 +#define MCF_DSPI_DCTAR2_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
392 +#define MCF_DSPI_DCTAR2_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
393 +#define MCF_DSPI_DCTAR2_LSBFE (0x01000000) /* LSB first enable */
394 +#define MCF_DSPI_DCTAR2_CPHA (0x02000000) /* Clock phase */
395 +#define MCF_DSPI_DCTAR2_CPOL (0x04000000) /* Clock polarity */
396 +#define MCF_DSPI_DCTAR2_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
397 +#define MCF_DSPI_DCTAR2_DBR (0x80000000) /* Double baud rate */
399 +/* Bit definitions and macros for DCTAR3 */
400 +#define MCF_DSPI_DCTAR3_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
401 +#define MCF_DSPI_DCTAR3_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
402 +#define MCF_DSPI_DCTAR3_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
403 +#define MCF_DSPI_DCTAR3_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
404 +#define MCF_DSPI_DCTAR3_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
405 +#define MCF_DSPI_DCTAR3_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
406 +#define MCF_DSPI_DCTAR3_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
407 +#define MCF_DSPI_DCTAR3_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
408 +#define MCF_DSPI_DCTAR3_LSBFE (0x01000000) /* LSB first enable */
409 +#define MCF_DSPI_DCTAR3_CPHA (0x02000000) /* Clock phase */
410 +#define MCF_DSPI_DCTAR3_CPOL (0x04000000) /* Clock polarity */
411 +#define MCF_DSPI_DCTAR3_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
412 +#define MCF_DSPI_DCTAR3_DBR (0x80000000) /* Double baud rate */
414 +/* Bit definitions and macros for DCTAR4 */
415 +#define MCF_DSPI_DCTAR4_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
416 +#define MCF_DSPI_DCTAR4_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
417 +#define MCF_DSPI_DCTAR4_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
418 +#define MCF_DSPI_DCTAR4_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
419 +#define MCF_DSPI_DCTAR4_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
420 +#define MCF_DSPI_DCTAR4_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
421 +#define MCF_DSPI_DCTAR4_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
422 +#define MCF_DSPI_DCTAR4_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
423 +#define MCF_DSPI_DCTAR4_LSBFE (0x01000000) /* LSB first enable */
424 +#define MCF_DSPI_DCTAR4_CPHA (0x02000000) /* Clock phase */
425 +#define MCF_DSPI_DCTAR4_CPOL (0x04000000) /* Clock polarity */
426 +#define MCF_DSPI_DCTAR4_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
427 +#define MCF_DSPI_DCTAR4_DBR (0x80000000) /* Double baud rate */
429 +/* Bit definitions and macros for DCTAR5 */
430 +#define MCF_DSPI_DCTAR5_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
431 +#define MCF_DSPI_DCTAR5_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
432 +#define MCF_DSPI_DCTAR5_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
433 +#define MCF_DSPI_DCTAR5_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
434 +#define MCF_DSPI_DCTAR5_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
435 +#define MCF_DSPI_DCTAR5_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
436 +#define MCF_DSPI_DCTAR5_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
437 +#define MCF_DSPI_DCTAR5_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
438 +#define MCF_DSPI_DCTAR5_LSBFE (0x01000000) /* LSB first enable */
439 +#define MCF_DSPI_DCTAR5_CPHA (0x02000000) /* Clock phase */
440 +#define MCF_DSPI_DCTAR5_CPOL (0x04000000) /* Clock polarity */
441 +#define MCF_DSPI_DCTAR5_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
442 +#define MCF_DSPI_DCTAR5_DBR (0x80000000) /* Double baud rate */
444 +/* Bit definitions and macros for DCTAR6 */
445 +#define MCF_DSPI_DCTAR6_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
446 +#define MCF_DSPI_DCTAR6_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
447 +#define MCF_DSPI_DCTAR6_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
448 +#define MCF_DSPI_DCTAR6_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
449 +#define MCF_DSPI_DCTAR6_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
450 +#define MCF_DSPI_DCTAR6_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
451 +#define MCF_DSPI_DCTAR6_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
452 +#define MCF_DSPI_DCTAR6_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
453 +#define MCF_DSPI_DCTAR6_LSBFE (0x01000000) /* LSB first enable */
454 +#define MCF_DSPI_DCTAR6_CPHA (0x02000000) /* Clock phase */
455 +#define MCF_DSPI_DCTAR6_CPOL (0x04000000) /* Clock polarity */
456 +#define MCF_DSPI_DCTAR6_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
457 +#define MCF_DSPI_DCTAR6_DBR (0x80000000) /* Double baud rate */
459 +/* Bit definitions and macros for DCTAR7 */
460 +#define MCF_DSPI_DCTAR7_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
461 +#define MCF_DSPI_DCTAR7_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
462 +#define MCF_DSPI_DCTAR7_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
463 +#define MCF_DSPI_DCTAR7_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
464 +#define MCF_DSPI_DCTAR7_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
465 +#define MCF_DSPI_DCTAR7_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
466 +#define MCF_DSPI_DCTAR7_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
467 +#define MCF_DSPI_DCTAR7_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
468 +#define MCF_DSPI_DCTAR7_LSBFE (0x01000000) /* LSB first enable */
469 +#define MCF_DSPI_DCTAR7_CPHA (0x02000000) /* Clock phase */
470 +#define MCF_DSPI_DCTAR7_CPOL (0x04000000) /* Clock polarity */
471 +#define MCF_DSPI_DCTAR7_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
472 +#define MCF_DSPI_DCTAR7_DBR (0x80000000) /* Double baud rate */
474 +/* Bit definitions and macros for DSR */
475 +#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)) /* Receive next pointer */
476 +#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) /* Receive FIFO counter */
477 +#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) /* Transmit next pointer */
478 +#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) /* Transmit FIFO counter */
479 +#define MCF_DSPI_DSR_RFDF (0x00020000) /* Receive FIFO drain flag */
480 +#define MCF_DSPI_DSR_RFOF (0x00080000) /* Receive FIFO overflow flag */
481 +#define MCF_DSPI_DSR_TFFF (0x02000000) /* Transmit FIFO fill flag */
482 +#define MCF_DSPI_DSR_TFUF (0x08000000) /* Transmit FIFO underflow flag */
483 +#define MCF_DSPI_DSR_EOQF (0x10000000) /* End of queue flag */
484 +#define MCF_DSPI_DSR_TXRXS (0x40000000) /* Tx and Rx status (enabled | disabled) */
485 +#define MCF_DSPI_DSR_TCF (0x80000000) /* Transfer complete flag */
487 +/* Bit definitions and macros for DRSER */
488 +#define MCF_DSPI_DRSER_RFDFS (0x00010000) /* Receive FIFO drain DMA or interrupt select */
489 +#define MCF_DSPI_DRSER_RFDFE (0x00020000) /* Receive FIFO drain request enable */
490 +#define MCF_DSPI_DRSER_RFOFE (0x00080000) /* Receive FIFO overflow request enable */
491 +#define MCF_DSPI_DRSER_TFFFS (0x01000000) /* Transmit FIFO fill DMA or interrupt select */
492 +#define MCF_DSPI_DRSER_TFFFE (0x02000000) /* Transmit FIFO fill request enable */
493 +#define MCF_DSPI_DRSER_TFUFE (0x08000000) /* Transmit FIFO underflow request enable */
494 +#define MCF_DSPI_DRSER_EOQFE (0x10000000) /* DSPI finished request enable */
495 +#define MCF_DSPI_DRSER_TCFE (0x80000000) /* Transmission complete request enable */
497 +/* Bit definitions and macros for DTFR */
498 +#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */
499 +#define MCF_DSPI_DTFR_PCS0 (0x00010000) /* Peripheral chip select 0 */
500 +#define MCF_DSPI_DTFR_PCS1 (0x00020000) /* Peripheral chip select 1 */
501 +#define MCF_DSPI_DTFR_PCS2 (0x00040000) /* Peripheral chip select 2 */
502 +#define MCF_DSPI_DTFR_PCS3 (0x00080000) /* Peripheral chip select 3 */
503 +#define MCF_DSPI_DTFR_PCS4 (0x00100000) /* Peripheral chip select 4 */
504 +#define MCF_DSPI_DTFR_PCS5 (0x00200000) /* Peripheral chip select 5 */
505 +#define MCF_DSPI_DTFR_PCS6 (0x00400000) /* Peripheral chip select 6 */
506 +#define MCF_DSPI_DTFR_PCS7 (0x00800000) /* Peripheral chip select 7 */
507 +#define MCF_DSPI_DTFR_CTCNT (0x04000000) /* Clear SPI transfer counter */
508 +#define MCF_DSPI_DTFR_EOQ (0x08000000) /* End of queue */
509 +#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */
510 +#define MCF_DSPI_DTFR_CONT (0x80000000) /* Continuous peripheral chip-select enable */
512 +/* Bit definitions and macros for DRFR */
513 +#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */
515 +/* Bit definitions and macros for DTFDR group */
516 +#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */
517 +#define MCF_DSPI_DTFDR_PCS0 (0x00010000) /* Peripheral chip select 0 */
518 +#define MCF_DSPI_DTFDR_PCS1 (0x00020000) /* Peripheral chip select 1 */
519 +#define MCF_DSPI_DTFDR_PCS2 (0x00040000) /* Peripheral chip select 2 */
520 +#define MCF_DSPI_DTFDR_PCS3 (0x00080000) /* Peripheral chip select 3 */
521 +#define MCF_DSPI_DTFDR_PCS4 (0x00100000) /* Peripheral chip select 4 */
522 +#define MCF_DSPI_DTFDR_PCS5 (0x00200000) /* Peripheral chip select 5 */
523 +#define MCF_DSPI_DTFDR_PCS6 (0x00400000) /* Peripheral chip select 6 */
524 +#define MCF_DSPI_DTFDR_PCS7 (0x00800000) /* Peripheral chip select 7 */
525 +#define MCF_DSPI_DTFDR_CTCNT (0x04000000) /* Clear SPI transfer counter */
526 +#define MCF_DSPI_DTFDR_EOQ (0x08000000) /* End of queue */
527 +#define MCF_DSPI_DTFDR_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */
528 +#define MCF_DSPI_DTFDR_CONT (0x80000000) /* Continuous peripheral chip-select enable */
530 +/* Bit definitions and macros for DTFDR0 */
531 +#define MCF_DSPI_DTFDR0_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */
532 +#define MCF_DSPI_DTFDR0_PCS0 (0x00010000) /* Peripheral chip select 0 */
533 +#define MCF_DSPI_DTFDR0_PCS1 (0x00020000) /* Peripheral chip select 1 */
534 +#define MCF_DSPI_DTFDR0_PCS2 (0x00040000) /* Peripheral chip select 2 */
535 +#define MCF_DSPI_DTFDR0_PCS3 (0x00080000) /* Peripheral chip select 3 */
536 +#define MCF_DSPI_DTFDR0_PCS4 (0x00100000) /* Peripheral chip select 4 */
537 +#define MCF_DSPI_DTFDR0_PCS5 (0x00200000) /* Peripheral chip select 5 */
538 +#define MCF_DSPI_DTFDR0_PCS6 (0x00400000) /* Peripheral chip select 6 */
539 +#define MCF_DSPI_DTFDR0_PCS7 (0x00800000) /* Peripheral chip select 7 */
540 +#define MCF_DSPI_DTFDR0_CTCNT (0x04000000) /* Clear SPI transfer counter */
541 +#define MCF_DSPI_DTFDR0_EOQ (0x08000000) /* End of queue */
542 +#define MCF_DSPI_DTFDR0_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */
543 +#define MCF_DSPI_DTFDR0_CONT (0x80000000) /* Continuous peripheral chip-select enable */
545 +/* Bit definitions and macros for DTFDR1 */
546 +#define MCF_DSPI_DTFDR1_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */
547 +#define MCF_DSPI_DTFDR1_PCS0 (0x00010000) /* Peripheral chip select 0 */
548 +#define MCF_DSPI_DTFDR1_PCS1 (0x00020000) /* Peripheral chip select 1 */
549 +#define MCF_DSPI_DTFDR1_PCS2 (0x00040000) /* Peripheral chip select 2 */
550 +#define MCF_DSPI_DTFDR1_PCS3 (0x00080000) /* Peripheral chip select 3 */
551 +#define MCF_DSPI_DTFDR1_PCS4 (0x00100000) /* Peripheral chip select 4 */
552 +#define MCF_DSPI_DTFDR1_PCS5 (0x00200000) /* Peripheral chip select 5 */
553 +#define MCF_DSPI_DTFDR1_PCS6 (0x00400000) /* Peripheral chip select 6 */
554 +#define MCF_DSPI_DTFDR1_PCS7 (0x00800000) /* Peripheral chip select 7 */
555 +#define MCF_DSPI_DTFDR1_CTCNT (0x04000000) /* Clear SPI transfer counter */
556 +#define MCF_DSPI_DTFDR1_EOQ (0x08000000) /* End of queue */
557 +#define MCF_DSPI_DTFDR1_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */
558 +#define MCF_DSPI_DTFDR1_CONT (0x80000000) /* Continuous peripheral chip-select enable */
560 +/* Bit definitions and macros for DTFDR2 */
561 +#define MCF_DSPI_DTFDR2_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */
562 +#define MCF_DSPI_DTFDR2_PCS0 (0x00010000) /* Peripheral chip select 0 */
563 +#define MCF_DSPI_DTFDR2_PCS1 (0x00020000) /* Peripheral chip select 1 */
564 +#define MCF_DSPI_DTFDR2_PCS2 (0x00040000) /* Peripheral chip select 2 */
565 +#define MCF_DSPI_DTFDR2_PCS3 (0x00080000) /* Peripheral chip select 3 */
566 +#define MCF_DSPI_DTFDR2_PCS4 (0x00100000) /* Peripheral chip select 4 */
567 +#define MCF_DSPI_DTFDR2_PCS5 (0x00200000) /* Peripheral chip select 5 */
568 +#define MCF_DSPI_DTFDR2_PCS6 (0x00400000) /* Peripheral chip select 6 */
569 +#define MCF_DSPI_DTFDR2_PCS7 (0x00800000) /* Peripheral chip select 7 */
570 +#define MCF_DSPI_DTFDR2_CTCNT (0x04000000) /* Clear SPI transfer counter */
571 +#define MCF_DSPI_DTFDR2_EOQ (0x08000000) /* End of queue */
572 +#define MCF_DSPI_DTFDR2_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */
573 +#define MCF_DSPI_DTFDR2_CONT (0x80000000) /* Continuous peripheral chip-select enable */
575 +/* Bit definitions and macros for DTFDR3 */
576 +#define MCF_DSPI_DTFDR3_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */
577 +#define MCF_DSPI_DTFDR3_PCS0 (0x00010000) /* Peripheral chip select 0 */
578 +#define MCF_DSPI_DTFDR3_PCS1 (0x00020000) /* Peripheral chip select 1 */
579 +#define MCF_DSPI_DTFDR3_PCS2 (0x00040000) /* Peripheral chip select 2 */
580 +#define MCF_DSPI_DTFDR3_PCS3 (0x00080000) /* Peripheral chip select 3 */
581 +#define MCF_DSPI_DTFDR3_PCS4 (0x00100000) /* Peripheral chip select 4 */
582 +#define MCF_DSPI_DTFDR3_PCS5 (0x00200000) /* Peripheral chip select 5 */
583 +#define MCF_DSPI_DTFDR3_PCS6 (0x00400000) /* Peripheral chip select 6 */
584 +#define MCF_DSPI_DTFDR3_PCS7 (0x00800000) /* Peripheral chip select 7 */
585 +#define MCF_DSPI_DTFDR3_CTCNT (0x04000000) /* Clear SPI transfer counter */
586 +#define MCF_DSPI_DTFDR3_EOQ (0x08000000) /* End of queue */
587 +#define MCF_DSPI_DTFDR3_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */
588 +#define MCF_DSPI_DTFDR3_CONT (0x80000000) /* Continuous peripheral chip-select enable */
590 +/* Bit definitions and macros for DRFDR group */
591 +#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */
593 +/* Bit definitions and macros for DRFDR0 */
594 +#define MCF_DSPI_DRFDR0_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */
596 +/* Bit definitions and macros for DRFDR1 */
597 +#define MCF_DSPI_DRFDR1_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */
599 +/* Bit definitions and macros for DRFDR2 */
600 +#define MCF_DSPI_DRFDR2_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */
602 +/* Bit definitions and macros for DRFDR3 */
603 +#define MCF_DSPI_DRFDR3_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */
605 +/********************************************************************/
607 +#endif /* __MCF5445X_DSPI_H__ */
609 +++ b/include/asm-m68k/mcf5445x_dtim.h
612 + * Matt Waddel Matt.Waddel@freescale.com
614 + * Copyright Freescale Semiconductor, Inc. 2007
616 + * This program is free software; you can redistribute it and/or modify it
617 + * under the terms of the GNU General Public License as published by the
618 + * Free Software Foundation; either version 2 of the License, or (at your
619 + * option) any later version.
622 +#ifndef __MCF5445X_DTIM_H__
623 +#define __MCF5445X_DTIM_H__
625 +/*********************************************************************
629 +*********************************************************************/
630 +/* Register read/write macros */
631 +#define MCF_DTIM0_DTMR 0xFC070000 /* DMA Timer Mode Register */
632 +#define MCF_DTIM0_DTXMR 0xFC070002 /* DMA Timer Extended Mode Register */
633 +#define MCF_DTIM0_DTER 0xFC070003 /* DMA Timer Event Register */
634 +#define MCF_DTIM0_DTRR 0xFC070004 /* DMA Timer Reference Register */
635 +#define MCF_DTIM0_DTCR 0xFC070008 /* DMA Timer Capture Register */
636 +#define MCF_DTIM0_DTCN 0xFC07000C /* DMA Timer Counter Register */
637 +#define MCF_DTIM1_DTMR 0xFC074000 /* DMA Timer Mode Register */
638 +#define MCF_DTIM1_DTXMR 0xFC074002 /* DMA Timer Extended Mode Register */
639 +#define MCF_DTIM1_DTER 0xFC074003 /* DMA Timer Event Register */
640 +#define MCF_DTIM1_DTRR 0xFC074004 /* DMA Timer Reference Register */
641 +#define MCF_DTIM1_DTCR 0xFC074008 /* DMA Timer Capture Register */
642 +#define MCF_DTIM1_DTCN 0xFC07400C /* DMA Timer Counter Register */
643 +#define MCF_DTIM2_DTMR 0xFC078000 /* DMA Timer Mode Register */
644 +#define MCF_DTIM2_DTXMR 0xFC078002 /* DMA Timer Extended Mode Register */
645 +#define MCF_DTIM2_DTER 0xFC078003 /* DMA Timer Event Register */
646 +#define MCF_DTIM2_DTRR 0xFC078004 /* DMA Timer Reference Register */
647 +#define MCF_DTIM2_DTCR 0xFC078008 /* DMA Timer Capture Register */
648 +#define MCF_DTIM2_DTCN 0xFC07800C /* DMA Timer Counter Register */
649 +#define MCF_DTIM3_DTMR 0xFC07C000 /* DMA Timer Mode Register */
650 +#define MCF_DTIM3_DTXMR 0xFC07C002 /* DMA Timer Extended Mode Register */
651 +#define MCF_DTIM3_DTER 0xFC07C003 /* DMA Timer Event Register */
652 +#define MCF_DTIM3_DTRR 0xFC07C004 /* DMA Timer Reference Register */
653 +#define MCF_DTIM3_DTCR 0xFC07C008 /* DMA Timer Capture Register */
654 +#define MCF_DTIM3_DTCN 0xFC07C00C /* DMA Timer Counter Register */
656 +/* Parameterized register read/write macros for multiple modules */
657 +#define MCF_DTIM_DTMR(x) 0xFC070000+((x)*0x4000) /* DMA Timer Mode Register */
658 +#define MCF_DTIM_DTXMR(x) 0xFC070002+((x)*0x4000) /* DMA Timer Extended Mode Register */
659 +#define MCF_DTIM_DTER(x) 0xFC070003+((x)*0x4000) /* DMA Timer Event Register */
660 +#define MCF_DTIM_DTRR(x) 0xFC070004+((x)*0x4000) /* DMA Timer Reference Register */
661 +#define MCF_DTIM_DTCR(x) 0xFC070008+((x)*0x4000) /* DMA Timer Capture Register */
662 +#define MCF_DTIM_DTCN(x) 0xFC07000C+((x)*0x4000) /* DMA Timer Counter Register */
664 +/* Bit definitions and macros for DTMR */
665 +#define MCF_DTIM_DTMR_RST (0x0001) /* Reset */
666 +#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */
667 +#define MCF_DTIM_DTMR_FRR (0x0008) /* Free run/restart */
668 +#define MCF_DTIM_DTMR_ORRI (0x0010) /* Output reference request/interrupt enable */
669 +#define MCF_DTIM_DTMR_OM (0x0020) /* Output Mode */
670 +#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */
671 +#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */
672 +#define MCF_DTIM_DTMR_RST_EN (0x0001)
673 +#define MCF_DTIM_DTMR_RST_RST (0x0000)
674 +#define MCF_DTIM_DTMR_CE_ANY (0x00C0)
675 +#define MCF_DTIM_DTMR_CE_FALL (0x0080)
676 +#define MCF_DTIM_DTMR_CE_RISE (0x0040)
677 +#define MCF_DTIM_DTMR_CE_NONE (0x0000)
678 +#define MCF_DTIM_DTMR_CLK_DTIN (0x0006)
679 +#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004)
680 +#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002)
681 +#define MCF_DTIM_DTMR_CLK_STOP (0x0000)
683 +/* Bit definitions and macros for DTXMR */
684 +#define MCF_DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */
685 +#define MCF_DTIM_DTXMR_DMAEN (0x80) /* DMA request */
687 +/* Bit definitions and macros for DTER */
688 +#define MCF_DTIM_DTER_CAP (0x01) /* Capture event */
689 +#define MCF_DTIM_DTER_REF (0x02) /* Output reference event */
691 +/* Interrupts used for system timers */
692 +#define MCFSIM_ICR_TIMER1 (0xFC048040+32)
693 +#define MCFSIM_ICR_TIMER2 (0xFC048040+33)
695 +/********************************************************************/
697 +#endif /* __MCF5445X_DTIM_H__ */
699 +++ b/include/asm-m68k/mcf5445x_edma.h
702 + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
704 + * Copyright Freescale Semiconductor, Inc. 2007
706 + * This program is free software; you can redistribute it and/or modify it
707 + * under the terms of the GNU General Public License as published by the
708 + * Free Software Foundation; either version 2 of the License, or (at your
709 + * option) any later version.
711 +#ifndef __MCF5445X_EDMA_H__
712 +#define __MCF5445X_EDMA_H__
714 +/*********************************************************************
716 +* Enhanced DMA (EDMA)
718 +*********************************************************************/
720 +/* Register read/write macros */
721 +#define MCF_EDMA_CR MCF_REG32(0xFC044000)
722 +#define MCF_EDMA_ES MCF_REG32(0xFC044004)
723 +#define MCF_EDMA_ERQ MCF_REG16(0xFC04400E)
724 +#define MCF_EDMA_EEI MCF_REG16(0xFC044016)
725 +#define MCF_EDMA_SERQ MCF_REG08(0xFC044018)
726 +#define MCF_EDMA_CERQ MCF_REG08(0xFC044019)
727 +#define MCF_EDMA_SEEI MCF_REG08(0xFC04401A)
728 +#define MCF_EDMA_CEEI MCF_REG08(0xFC04401B)
729 +#define MCF_EDMA_CINT MCF_REG08(0xFC04401C)
730 +#define MCF_EDMA_CERR MCF_REG08(0xFC04401D)
731 +#define MCF_EDMA_SSRT MCF_REG08(0xFC04401E)
732 +#define MCF_EDMA_CDNE MCF_REG08(0xFC04401F)
733 +#define MCF_EDMA_INTR MCF_REG16(0xFC044026)
734 +#define MCF_EDMA_ERR MCF_REG16(0xFC04402E)
735 +#define MCF_EDMA_DCHPRI0 MCF_REG08(0xFC044100)
736 +#define MCF_EDMA_DCHPRI1 MCF_REG08(0xFC044101)
737 +#define MCF_EDMA_DCHPRI2 MCF_REG08(0xFC044102)
738 +#define MCF_EDMA_DCHPRI3 MCF_REG08(0xFC044103)
739 +#define MCF_EDMA_DCHPRI4 MCF_REG08(0xFC044104)
740 +#define MCF_EDMA_DCHPRI5 MCF_REG08(0xFC044105)
741 +#define MCF_EDMA_DCHPRI6 MCF_REG08(0xFC044106)
742 +#define MCF_EDMA_DCHPRI7 MCF_REG08(0xFC044107)
743 +#define MCF_EDMA_DCHPRI8 MCF_REG08(0xFC044108)
744 +#define MCF_EDMA_DCHPRI9 MCF_REG08(0xFC044109)
745 +#define MCF_EDMA_DCHPRI10 MCF_REG08(0xFC04410A)
746 +#define MCF_EDMA_DCHPRI11 MCF_REG08(0xFC04410B)
747 +#define MCF_EDMA_DCHPRI12 MCF_REG08(0xFC04410C)
748 +#define MCF_EDMA_DCHPRI13 MCF_REG08(0xFC04410D)
749 +#define MCF_EDMA_DCHPRI14 MCF_REG08(0xFC04410E)
750 +#define MCF_EDMA_DCHPRI15 MCF_REG08(0xFC04410F)
751 +#define MCF_EDMA_TCD0_SADDR MCF_REG32(0xFC045000)
752 +#define MCF_EDMA_TCD0_ATTR MCF_REG16(0xFC045004)
753 +#define MCF_EDMA_TCD0_SOFF MCF_REG16(0xFC045006)
754 +#define MCF_EDMA_TCD0_NBYTES MCF_REG32(0xFC045008)
755 +#define MCF_EDMA_TCD0_SLAST MCF_REG32(0xFC04500C)
756 +#define MCF_EDMA_TCD0_DADDR MCF_REG32(0xFC045010)
757 +#define MCF_EDMA_TCD0_CITER_ELINK MCF_REG16(0xFC045014)
758 +#define MCF_EDMA_TCD0_CITER MCF_REG16(0xFC045014)
759 +#define MCF_EDMA_TCD0_DOFF MCF_REG16(0xFC045016)
760 +#define MCF_EDMA_TCD0_DLAST_SGA MCF_REG32(0xFC045018)
761 +#define MCF_EDMA_TCD0_BITER_ELINK MCF_REG16(0xFC04501C)
762 +#define MCF_EDMA_TCD0_BITER MCF_REG16(0xFC04501C)
763 +#define MCF_EDMA_TCD0_CSR MCF_REG16(0xFC04501E)
764 +#define MCF_EDMA_TCD1_SADDR MCF_REG32(0xFC045020)
765 +#define MCF_EDMA_TCD1_ATTR MCF_REG16(0xFC045024)
766 +#define MCF_EDMA_TCD1_SOFF MCF_REG16(0xFC045026)
767 +#define MCF_EDMA_TCD1_NBYTES MCF_REG32(0xFC045028)
768 +#define MCF_EDMA_TCD1_SLAST MCF_REG32(0xFC04502C)
769 +#define MCF_EDMA_TCD1_DADDR MCF_REG32(0xFC045030)
770 +#define MCF_EDMA_TCD1_CITER_ELINK MCF_REG16(0xFC045034)
771 +#define MCF_EDMA_TCD1_CITER MCF_REG16(0xFC045034)
772 +#define MCF_EDMA_TCD1_DOFF MCF_REG16(0xFC045036)
773 +#define MCF_EDMA_TCD1_DLAST_SGA MCF_REG32(0xFC045038)
774 +#define MCF_EDMA_TCD1_BITER MCF_REG16(0xFC04503C)
775 +#define MCF_EDMA_TCD1_BITER_ELINK MCF_REG16(0xFC04503C)
776 +#define MCF_EDMA_TCD1_CSR MCF_REG16(0xFC04503E)
777 +#define MCF_EDMA_TCD2_SADDR MCF_REG32(0xFC045040)
778 +#define MCF_EDMA_TCD2_ATTR MCF_REG16(0xFC045044)
779 +#define MCF_EDMA_TCD2_SOFF MCF_REG16(0xFC045046)
780 +#define MCF_EDMA_TCD2_NBYTES MCF_REG32(0xFC045048)
781 +#define MCF_EDMA_TCD2_SLAST MCF_REG32(0xFC04504C)
782 +#define MCF_EDMA_TCD2_DADDR MCF_REG32(0xFC045050)
783 +#define MCF_EDMA_TCD2_CITER MCF_REG16(0xFC045054)
784 +#define MCF_EDMA_TCD2_CITER_ELINK MCF_REG16(0xFC045054)
785 +#define MCF_EDMA_TCD2_DOFF MCF_REG16(0xFC045056)
786 +#define MCF_EDMA_TCD2_DLAST_SGA MCF_REG32(0xFC045058)
787 +#define MCF_EDMA_TCD2_BITER_ELINK MCF_REG16(0xFC04505C)
788 +#define MCF_EDMA_TCD2_BITER MCF_REG16(0xFC04505C)
789 +#define MCF_EDMA_TCD2_CSR MCF_REG16(0xFC04505E)
790 +#define MCF_EDMA_TCD3_SADDR MCF_REG32(0xFC045060)
791 +#define MCF_EDMA_TCD3_ATTR MCF_REG16(0xFC045064)
792 +#define MCF_EDMA_TCD3_SOFF MCF_REG16(0xFC045066)
793 +#define MCF_EDMA_TCD3_NBYTES MCF_REG32(0xFC045068)
794 +#define MCF_EDMA_TCD3_SLAST MCF_REG32(0xFC04506C)
795 +#define MCF_EDMA_TCD3_DADDR MCF_REG32(0xFC045070)
796 +#define MCF_EDMA_TCD3_CITER MCF_REG16(0xFC045074)
797 +#define MCF_EDMA_TCD3_CITER_ELINK MCF_REG16(0xFC045074)
798 +#define MCF_EDMA_TCD3_DOFF MCF_REG16(0xFC045076)
799 +#define MCF_EDMA_TCD3_DLAST_SGA MCF_REG32(0xFC045078)
800 +#define MCF_EDMA_TCD3_BITER_ELINK MCF_REG16(0xFC04507C)
801 +#define MCF_EDMA_TCD3_BITER MCF_REG16(0xFC04507C)
802 +#define MCF_EDMA_TCD3_CSR MCF_REG16(0xFC04507E)
803 +#define MCF_EDMA_TCD4_SADDR MCF_REG32(0xFC045080)
804 +#define MCF_EDMA_TCD4_ATTR MCF_REG16(0xFC045084)
805 +#define MCF_EDMA_TCD4_SOFF MCF_REG16(0xFC045086)
806 +#define MCF_EDMA_TCD4_NBYTES MCF_REG32(0xFC045088)
807 +#define MCF_EDMA_TCD4_SLAST MCF_REG32(0xFC04508C)
808 +#define MCF_EDMA_TCD4_DADDR MCF_REG32(0xFC045090)
809 +#define MCF_EDMA_TCD4_CITER MCF_REG16(0xFC045094)
810 +#define MCF_EDMA_TCD4_CITER_ELINK MCF_REG16(0xFC045094)
811 +#define MCF_EDMA_TCD4_DOFF MCF_REG16(0xFC045096)
812 +#define MCF_EDMA_TCD4_DLAST_SGA MCF_REG32(0xFC045098)
813 +#define MCF_EDMA_TCD4_BITER MCF_REG16(0xFC04509C)
814 +#define MCF_EDMA_TCD4_BITER_ELINK MCF_REG16(0xFC04509C)
815 +#define MCF_EDMA_TCD4_CSR MCF_REG16(0xFC04509E)
816 +#define MCF_EDMA_TCD5_SADDR MCF_REG32(0xFC0450A0)
817 +#define MCF_EDMA_TCD5_ATTR MCF_REG16(0xFC0450A4)
818 +#define MCF_EDMA_TCD5_SOFF MCF_REG16(0xFC0450A6)
819 +#define MCF_EDMA_TCD5_NBYTES MCF_REG32(0xFC0450A8)
820 +#define MCF_EDMA_TCD5_SLAST MCF_REG32(0xFC0450AC)
821 +#define MCF_EDMA_TCD5_DADDR MCF_REG32(0xFC0450B0)
822 +#define MCF_EDMA_TCD5_CITER MCF_REG16(0xFC0450B4)
823 +#define MCF_EDMA_TCD5_CITER_ELINK MCF_REG16(0xFC0450B4)
824 +#define MCF_EDMA_TCD5_DOFF MCF_REG16(0xFC0450B6)
825 +#define MCF_EDMA_TCD5_DLAST_SGA MCF_REG32(0xFC0450B8)
826 +#define MCF_EDMA_TCD5_BITER_ELINK MCF_REG16(0xFC0450BC)
827 +#define MCF_EDMA_TCD5_BITER MCF_REG16(0xFC0450BC)
828 +#define MCF_EDMA_TCD5_CSR MCF_REG16(0xFC0450BE)
829 +#define MCF_EDMA_TCD6_SADDR MCF_REG32(0xFC0450C0)
830 +#define MCF_EDMA_TCD6_ATTR MCF_REG16(0xFC0450C4)
831 +#define MCF_EDMA_TCD6_SOFF MCF_REG16(0xFC0450C6)
832 +#define MCF_EDMA_TCD6_NBYTES MCF_REG32(0xFC0450C8)
833 +#define MCF_EDMA_TCD6_SLAST MCF_REG32(0xFC0450CC)
834 +#define MCF_EDMA_TCD6_DADDR MCF_REG32(0xFC0450D0)
835 +#define MCF_EDMA_TCD6_CITER MCF_REG16(0xFC0450D4)
836 +#define MCF_EDMA_TCD6_CITER_ELINK MCF_REG16(0xFC0450D4)
837 +#define MCF_EDMA_TCD6_DOFF MCF_REG16(0xFC0450D6)
838 +#define MCF_EDMA_TCD6_DLAST_SGA MCF_REG32(0xFC0450D8)
839 +#define MCF_EDMA_TCD6_BITER_ELINK MCF_REG16(0xFC0450DC)
840 +#define MCF_EDMA_TCD6_BITER MCF_REG16(0xFC0450DC)
841 +#define MCF_EDMA_TCD6_CSR MCF_REG16(0xFC0450DE)
842 +#define MCF_EDMA_TCD7_SADDR MCF_REG32(0xFC0450E0)
843 +#define MCF_EDMA_TCD7_ATTR MCF_REG16(0xFC0450E4)
844 +#define MCF_EDMA_TCD7_SOFF MCF_REG16(0xFC0450E6)
845 +#define MCF_EDMA_TCD7_NBYTES MCF_REG32(0xFC0450E8)
846 +#define MCF_EDMA_TCD7_SLAST MCF_REG32(0xFC0450EC)
847 +#define MCF_EDMA_TCD7_DADDR MCF_REG32(0xFC0450F0)
848 +#define MCF_EDMA_TCD7_CITER MCF_REG16(0xFC0450F4)
849 +#define MCF_EDMA_TCD7_CITER_ELINK MCF_REG16(0xFC0450F4)
850 +#define MCF_EDMA_TCD7_DOFF MCF_REG16(0xFC0450F6)
851 +#define MCF_EDMA_TCD7_DLAST_SGA MCF_REG32(0xFC0450F8)
852 +#define MCF_EDMA_TCD7_BITER_ELINK MCF_REG16(0xFC0450FC)
853 +#define MCF_EDMA_TCD7_BITER MCF_REG16(0xFC0450FC)
854 +#define MCF_EDMA_TCD7_CSR MCF_REG16(0xFC0450FE)
855 +#define MCF_EDMA_TCD8_SADDR MCF_REG32(0xFC045100)
856 +#define MCF_EDMA_TCD8_ATTR MCF_REG16(0xFC045104)
857 +#define MCF_EDMA_TCD8_SOFF MCF_REG16(0xFC045106)
858 +#define MCF_EDMA_TCD8_NBYTES MCF_REG32(0xFC045108)
859 +#define MCF_EDMA_TCD8_SLAST MCF_REG32(0xFC04510C)
860 +#define MCF_EDMA_TCD8_DADDR MCF_REG32(0xFC045110)
861 +#define MCF_EDMA_TCD8_CITER MCF_REG16(0xFC045114)
862 +#define MCF_EDMA_TCD8_CITER_ELINK MCF_REG16(0xFC045114)
863 +#define MCF_EDMA_TCD8_DOFF MCF_REG16(0xFC045116)
864 +#define MCF_EDMA_TCD8_DLAST_SGA MCF_REG32(0xFC045118)
865 +#define MCF_EDMA_TCD8_BITER_ELINK MCF_REG16(0xFC04511C)
866 +#define MCF_EDMA_TCD8_BITER MCF_REG16(0xFC04511C)
867 +#define MCF_EDMA_TCD8_CSR MCF_REG16(0xFC04511E)
868 +#define MCF_EDMA_TCD9_SADDR MCF_REG32(0xFC045120)
869 +#define MCF_EDMA_TCD9_ATTR MCF_REG16(0xFC045124)
870 +#define MCF_EDMA_TCD9_SOFF MCF_REG16(0xFC045126)
871 +#define MCF_EDMA_TCD9_NBYTES MCF_REG32(0xFC045128)
872 +#define MCF_EDMA_TCD9_SLAST MCF_REG32(0xFC04512C)
873 +#define MCF_EDMA_TCD9_DADDR MCF_REG32(0xFC045130)
874 +#define MCF_EDMA_TCD9_CITER_ELINK MCF_REG16(0xFC045134)
875 +#define MCF_EDMA_TCD9_CITER MCF_REG16(0xFC045134)
876 +#define MCF_EDMA_TCD9_DOFF MCF_REG16(0xFC045136)
877 +#define MCF_EDMA_TCD9_DLAST_SGA MCF_REG32(0xFC045138)
878 +#define MCF_EDMA_TCD9_BITER_ELINK MCF_REG16(0xFC04513C)
879 +#define MCF_EDMA_TCD9_BITER MCF_REG16(0xFC04513C)
880 +#define MCF_EDMA_TCD9_CSR MCF_REG16(0xFC04513E)
881 +#define MCF_EDMA_TCD10_SADDR MCF_REG32(0xFC045140)
882 +#define MCF_EDMA_TCD10_ATTR MCF_REG16(0xFC045144)
883 +#define MCF_EDMA_TCD10_SOFF MCF_REG16(0xFC045146)
884 +#define MCF_EDMA_TCD10_NBYTES MCF_REG32(0xFC045148)
885 +#define MCF_EDMA_TCD10_SLAST MCF_REG32(0xFC04514C)
886 +#define MCF_EDMA_TCD10_DADDR MCF_REG32(0xFC045150)
887 +#define MCF_EDMA_TCD10_CITER_ELINK MCF_REG16(0xFC045154)
888 +#define MCF_EDMA_TCD10_CITER MCF_REG16(0xFC045154)
889 +#define MCF_EDMA_TCD10_DOFF MCF_REG16(0xFC045156)
890 +#define MCF_EDMA_TCD10_DLAST_SGA MCF_REG32(0xFC045158)
891 +#define MCF_EDMA_TCD10_BITER MCF_REG16(0xFC04515C)
892 +#define MCF_EDMA_TCD10_BITER_ELINK MCF_REG16(0xFC04515C)
893 +#define MCF_EDMA_TCD10_CSR MCF_REG16(0xFC04515E)
894 +#define MCF_EDMA_TCD11_SADDR MCF_REG32(0xFC045160)
895 +#define MCF_EDMA_TCD11_ATTR MCF_REG16(0xFC045164)
896 +#define MCF_EDMA_TCD11_SOFF MCF_REG16(0xFC045166)
897 +#define MCF_EDMA_TCD11_NBYTES MCF_REG32(0xFC045168)
898 +#define MCF_EDMA_TCD11_SLAST MCF_REG32(0xFC04516C)
899 +#define MCF_EDMA_TCD11_DADDR MCF_REG32(0xFC045170)
900 +#define MCF_EDMA_TCD11_CITER MCF_REG16(0xFC045174)
901 +#define MCF_EDMA_TCD11_CITER_ELINK MCF_REG16(0xFC045174)
902 +#define MCF_EDMA_TCD11_DOFF MCF_REG16(0xFC045176)
903 +#define MCF_EDMA_TCD11_DLAST_SGA MCF_REG32(0xFC045178)
904 +#define MCF_EDMA_TCD11_BITER MCF_REG16(0xFC04517C)
905 +#define MCF_EDMA_TCD11_BITER_ELINK MCF_REG16(0xFC04517C)
906 +#define MCF_EDMA_TCD11_CSR MCF_REG16(0xFC04517E)
907 +#define MCF_EDMA_TCD12_SADDR MCF_REG32(0xFC045180)
908 +#define MCF_EDMA_TCD12_ATTR MCF_REG16(0xFC045184)
909 +#define MCF_EDMA_TCD12_SOFF MCF_REG16(0xFC045186)
910 +#define MCF_EDMA_TCD12_NBYTES MCF_REG32(0xFC045188)
911 +#define MCF_EDMA_TCD12_SLAST MCF_REG32(0xFC04518C)
912 +#define MCF_EDMA_TCD12_DADDR MCF_REG32(0xFC045190)
913 +#define MCF_EDMA_TCD12_CITER MCF_REG16(0xFC045194)
914 +#define MCF_EDMA_TCD12_CITER_ELINK MCF_REG16(0xFC045194)
915 +#define MCF_EDMA_TCD12_DOFF MCF_REG16(0xFC045196)
916 +#define MCF_EDMA_TCD12_DLAST_SGA MCF_REG32(0xFC045198)
917 +#define MCF_EDMA_TCD12_BITER MCF_REG16(0xFC04519C)
918 +#define MCF_EDMA_TCD12_BITER_ELINK MCF_REG16(0xFC04519C)
919 +#define MCF_EDMA_TCD12_CSR MCF_REG16(0xFC04519E)
920 +#define MCF_EDMA_TCD13_SADDR MCF_REG32(0xFC0451A0)
921 +#define MCF_EDMA_TCD13_ATTR MCF_REG16(0xFC0451A4)
922 +#define MCF_EDMA_TCD13_SOFF MCF_REG16(0xFC0451A6)
923 +#define MCF_EDMA_TCD13_NBYTES MCF_REG32(0xFC0451A8)
924 +#define MCF_EDMA_TCD13_SLAST MCF_REG32(0xFC0451AC)
925 +#define MCF_EDMA_TCD13_DADDR MCF_REG32(0xFC0451B0)
926 +#define MCF_EDMA_TCD13_CITER_ELINK MCF_REG16(0xFC0451B4)
927 +#define MCF_EDMA_TCD13_CITER MCF_REG16(0xFC0451B4)
928 +#define MCF_EDMA_TCD13_DOFF MCF_REG16(0xFC0451B6)
929 +#define MCF_EDMA_TCD13_DLAST_SGA MCF_REG32(0xFC0451B8)
930 +#define MCF_EDMA_TCD13_BITER_ELINK MCF_REG16(0xFC0451BC)
931 +#define MCF_EDMA_TCD13_BITER MCF_REG16(0xFC0451BC)
932 +#define MCF_EDMA_TCD13_CSR MCF_REG16(0xFC0451BE)
933 +#define MCF_EDMA_TCD14_SADDR MCF_REG32(0xFC0451C0)
934 +#define MCF_EDMA_TCD14_ATTR MCF_REG16(0xFC0451C4)
935 +#define MCF_EDMA_TCD14_SOFF MCF_REG16(0xFC0451C6)
936 +#define MCF_EDMA_TCD14_NBYTES MCF_REG32(0xFC0451C8)
937 +#define MCF_EDMA_TCD14_SLAST MCF_REG32(0xFC0451CC)
938 +#define MCF_EDMA_TCD14_DADDR MCF_REG32(0xFC0451D0)
939 +#define MCF_EDMA_TCD14_CITER MCF_REG16(0xFC0451D4)
940 +#define MCF_EDMA_TCD14_CITER_ELINK MCF_REG16(0xFC0451D4)
941 +#define MCF_EDMA_TCD14_DOFF MCF_REG16(0xFC0451D6)
942 +#define MCF_EDMA_TCD14_DLAST_SGA MCF_REG32(0xFC0451D8)
943 +#define MCF_EDMA_TCD14_BITER_ELINK MCF_REG16(0xFC0451DC)
944 +#define MCF_EDMA_TCD14_BITER MCF_REG16(0xFC0451DC)
945 +#define MCF_EDMA_TCD14_CSR MCF_REG16(0xFC0451DE)
946 +#define MCF_EDMA_TCD15_SADDR MCF_REG32(0xFC0451E0)
947 +#define MCF_EDMA_TCD15_ATTR MCF_REG16(0xFC0451E4)
948 +#define MCF_EDMA_TCD15_SOFF MCF_REG16(0xFC0451E6)
949 +#define MCF_EDMA_TCD15_NBYTES MCF_REG32(0xFC0451E8)
950 +#define MCF_EDMA_TCD15_SLAST MCF_REG32(0xFC0451EC)
951 +#define MCF_EDMA_TCD15_DADDR MCF_REG32(0xFC0451F0)
952 +#define MCF_EDMA_TCD15_CITER_ELINK MCF_REG16(0xFC0451F4)
953 +#define MCF_EDMA_TCD15_CITER MCF_REG16(0xFC0451F4)
954 +#define MCF_EDMA_TCD15_DOFF MCF_REG16(0xFC0451F6)
955 +#define MCF_EDMA_TCD15_DLAST_SGA MCF_REG32(0xFC0451F8)
956 +#define MCF_EDMA_TCD15_BITER MCF_REG16(0xFC0451FC)
957 +#define MCF_EDMA_TCD15_BITER_ELINK MCF_REG16(0xFC0451FC)
958 +#define MCF_EDMA_TCD15_CSR MCF_REG16(0xFC0451FE)
960 +/* Parameterized register read/write macros for multiple registers */
961 +#define MCF_EDMA_DCHPRI(x) MCF_REG08(0xFC044100+((x)*0x001))
962 +#define MCF_EDMA_TCD_SADDR(x) MCF_REG32(0xFC045000+((x)*0x020))
963 +#define MCF_EDMA_TCD_ATTR(x) MCF_REG16(0xFC045004+((x)*0x020))
964 +#define MCF_EDMA_TCD_SOFF(x) MCF_REG16(0xFC045006+((x)*0x020))
965 +#define MCF_EDMA_TCD_NBYTES(x) MCF_REG32(0xFC045008+((x)*0x020))
966 +#define MCF_EDMA_TCD_SLAST(x) MCF_REG32(0xFC04500C+((x)*0x020))
967 +#define MCF_EDMA_TCD_DADDR(x) MCF_REG32(0xFC045010+((x)*0x020))
968 +#define MCF_EDMA_TCD_CITER_ELINK(x) MCF_REG16(0xFC045014+((x)*0x020))
969 +#define MCF_EDMA_TCD_CITER(x) MCF_REG16(0xFC045014+((x)*0x020))
970 +#define MCF_EDMA_TCD_DOFF(x) MCF_REG16(0xFC045016+((x)*0x020))
971 +#define MCF_EDMA_TCD_DLAST_SGA(x) MCF_REG32(0xFC045018+((x)*0x020))
972 +#define MCF_EDMA_TCD_BITER_ELINK(x) MCF_REG16(0xFC04501C+((x)*0x020))
973 +#define MCF_EDMA_TCD_BITER(x) MCF_REG16(0xFC04501C+((x)*0x020))
974 +#define MCF_EDMA_TCD_CSR(x) MCF_REG16(0xFC04501e +((x)*0x020))
976 +/* Bit definitions and macros for CR */
977 +#define MCF_EDMA_CR_EDBG (0x00000002)
978 +#define MCF_EDMA_CR_ERCA (0x00000004)
980 +/* Bit definitions and macros for ES */
981 +#define MCF_EDMA_ES_DBE (0x00000001)
982 +#define MCF_EDMA_ES_SBE (0x00000002)
983 +#define MCF_EDMA_ES_SGE (0x00000004)
984 +#define MCF_EDMA_ES_NCE (0x00000008)
985 +#define MCF_EDMA_ES_DOE (0x00000010)
986 +#define MCF_EDMA_ES_DAE (0x00000020)
987 +#define MCF_EDMA_ES_SOE (0x00000040)
988 +#define MCF_EDMA_ES_SAE (0x00000080)
989 +#define MCF_EDMA_ES_ERRCHN(x) (((x)&0x0000000F)<<8)
990 +#define MCF_EDMA_ES_CPE (0x00004000)
991 +#define MCF_EDMA_ES_VLD (0x80000000)
993 +/* Bit definitions and macros for ERQ */
994 +#define MCF_EDMA_ERQ_ERQ0 (0x0001)
995 +#define MCF_EDMA_ERQ_ERQ1 (0x0002)
996 +#define MCF_EDMA_ERQ_ERQ2 (0x0004)
997 +#define MCF_EDMA_ERQ_ERQ3 (0x0008)
998 +#define MCF_EDMA_ERQ_ERQ4 (0x0010)
999 +#define MCF_EDMA_ERQ_ERQ5 (0x0020)
1000 +#define MCF_EDMA_ERQ_ERQ6 (0x0040)
1001 +#define MCF_EDMA_ERQ_ERQ7 (0x0080)
1002 +#define MCF_EDMA_ERQ_ERQ8 (0x0100)
1003 +#define MCF_EDMA_ERQ_ERQ9 (0x0200)
1004 +#define MCF_EDMA_ERQ_ERQ10 (0x0400)
1005 +#define MCF_EDMA_ERQ_ERQ11 (0x0800)
1006 +#define MCF_EDMA_ERQ_ERQ12 (0x1000)
1007 +#define MCF_EDMA_ERQ_ERQ13 (0x2000)
1008 +#define MCF_EDMA_ERQ_ERQ14 (0x4000)
1009 +#define MCF_EDMA_ERQ_ERQ15 (0x8000)
1011 +/* Bit definitions and macros for EEI */
1012 +#define MCF_EDMA_EEI_EEI0 (0x0001)
1013 +#define MCF_EDMA_EEI_EEI1 (0x0002)
1014 +#define MCF_EDMA_EEI_EEI2 (0x0004)
1015 +#define MCF_EDMA_EEI_EEI3 (0x0008)
1016 +#define MCF_EDMA_EEI_EEI4 (0x0010)
1017 +#define MCF_EDMA_EEI_EEI5 (0x0020)
1018 +#define MCF_EDMA_EEI_EEI6 (0x0040)
1019 +#define MCF_EDMA_EEI_EEI7 (0x0080)
1020 +#define MCF_EDMA_EEI_EEI8 (0x0100)
1021 +#define MCF_EDMA_EEI_EEI9 (0x0200)
1022 +#define MCF_EDMA_EEI_EEI10 (0x0400)
1023 +#define MCF_EDMA_EEI_EEI11 (0x0800)
1024 +#define MCF_EDMA_EEI_EEI12 (0x1000)
1025 +#define MCF_EDMA_EEI_EEI13 (0x2000)
1026 +#define MCF_EDMA_EEI_EEI14 (0x4000)
1027 +#define MCF_EDMA_EEI_EEI15 (0x8000)
1029 +/* Bit definitions and macros for SERQ */
1030 +#define MCF_EDMA_SERQ_SERQ(x) (((x)&0x0F))
1031 +#define MCF_EDMA_SERQ_SAER (0x40)
1033 +/* Bit definitions and macros for CERQ */
1034 +#define MCF_EDMA_CERQ_CERQ(x) (((x)&0x0F))
1035 +#define MCF_EDMA_CERQ_CAER (0x40)
1037 +/* Bit definitions and macros for SEEI */
1038 +#define MCF_EDMA_SEEI_SEEI(x) (((x)&0x0F))
1039 +#define MCF_EDMA_SEEI_SAEE (0x40)
1041 +/* Bit definitions and macros for CEEI */
1042 +#define MCF_EDMA_CEEI_CEEI(x) (((x)&0x0F))
1043 +#define MCF_EDMA_CEEI_CAEE (0x40)
1045 +/* Bit definitions and macros for CINT */
1046 +#define MCF_EDMA_CINT_CINT(x) (((x)&0x0F))
1047 +#define MCF_EDMA_CINT_CAIR (0x40)
1049 +/* Bit definitions and macros for CERR */
1050 +#define MCF_EDMA_CERR_CERR(x) (((x)&0x0F))
1051 +#define MCF_EDMA_CERR_CAER (0x40)
1053 +/* Bit definitions and macros for SSRT */
1054 +#define MCF_EDMA_SSRT_SSRT(x) (((x)&0x0F))
1055 +#define MCF_EDMA_SSRT_SAST (0x40)
1057 +/* Bit definitions and macros for CDNE */
1058 +#define MCF_EDMA_CDNE_CDNE(x) (((x)&0x0F))
1059 +#define MCF_EDMA_CDNE_CADN (0x40)
1061 +/* Bit definitions and macros for INTR */
1062 +#define MCF_EDMA_INTR_INT0 (0x0001)
1063 +#define MCF_EDMA_INTR_INT1 (0x0002)
1064 +#define MCF_EDMA_INTR_INT2 (0x0004)
1065 +#define MCF_EDMA_INTR_INT3 (0x0008)
1066 +#define MCF_EDMA_INTR_INT4 (0x0010)
1067 +#define MCF_EDMA_INTR_INT5 (0x0020)
1068 +#define MCF_EDMA_INTR_INT6 (0x0040)
1069 +#define MCF_EDMA_INTR_INT7 (0x0080)
1070 +#define MCF_EDMA_INTR_INT8 (0x0100)
1071 +#define MCF_EDMA_INTR_INT9 (0x0200)
1072 +#define MCF_EDMA_INTR_INT10 (0x0400)
1073 +#define MCF_EDMA_INTR_INT11 (0x0800)
1074 +#define MCF_EDMA_INTR_INT12 (0x1000)
1075 +#define MCF_EDMA_INTR_INT13 (0x2000)
1076 +#define MCF_EDMA_INTR_INT14 (0x4000)
1077 +#define MCF_EDMA_INTR_INT15 (0x8000)
1079 +/* Bit definitions and macros for ERR */
1080 +#define MCF_EDMA_ERR_ERR0 (0x0001)
1081 +#define MCF_EDMA_ERR_ERR1 (0x0002)
1082 +#define MCF_EDMA_ERR_ERR2 (0x0004)
1083 +#define MCF_EDMA_ERR_ERR3 (0x0008)
1084 +#define MCF_EDMA_ERR_ERR4 (0x0010)
1085 +#define MCF_EDMA_ERR_ERR5 (0x0020)
1086 +#define MCF_EDMA_ERR_ERR6 (0x0040)
1087 +#define MCF_EDMA_ERR_ERR7 (0x0080)
1088 +#define MCF_EDMA_ERR_ERR8 (0x0100)
1089 +#define MCF_EDMA_ERR_ERR9 (0x0200)
1090 +#define MCF_EDMA_ERR_ERR10 (0x0400)
1091 +#define MCF_EDMA_ERR_ERR11 (0x0800)
1092 +#define MCF_EDMA_ERR_ERR12 (0x1000)
1093 +#define MCF_EDMA_ERR_ERR13 (0x2000)
1094 +#define MCF_EDMA_ERR_ERR14 (0x4000)
1095 +#define MCF_EDMA_ERR_ERR15 (0x8000)
1097 +/* Bit definitions and macros for DCHPRI group */
1098 +#define MCF_EDMA_DCHPRI_CHPRI(x) (((x)&0x0F))
1099 +#define MCF_EDMA_DCHPRI_ECP (0x80)
1101 +/* Bit definitions and macros for DCHPRI0 */
1102 +#define MCF_EDMA_DCHPRI0_CHPRI(x) (((x)&0x0F))
1103 +#define MCF_EDMA_DCHPRI0_ECP (0x80)
1105 +/* Bit definitions and macros for DCHPRI1 */
1106 +#define MCF_EDMA_DCHPRI1_CHPRI(x) (((x)&0x0F))
1107 +#define MCF_EDMA_DCHPRI1_ECP (0x80)
1109 +/* Bit definitions and macros for DCHPRI2 */
1110 +#define MCF_EDMA_DCHPRI2_CHPRI(x) (((x)&0x0F))
1111 +#define MCF_EDMA_DCHPRI2_ECP (0x80)
1113 +/* Bit definitions and macros for DCHPRI3 */
1114 +#define MCF_EDMA_DCHPRI3_CHPRI(x) (((x)&0x0F))
1115 +#define MCF_EDMA_DCHPRI3_ECP (0x80)
1117 +/* Bit definitions and macros for DCHPRI4 */
1118 +#define MCF_EDMA_DCHPRI4_CHPRI(x) (((x)&0x0F))
1119 +#define MCF_EDMA_DCHPRI4_ECP (0x80)
1121 +/* Bit definitions and macros for DCHPRI5 */
1122 +#define MCF_EDMA_DCHPRI5_CHPRI(x) (((x)&0x0F))
1123 +#define MCF_EDMA_DCHPRI5_ECP (0x80)
1125 +/* Bit definitions and macros for DCHPRI6 */
1126 +#define MCF_EDMA_DCHPRI6_CHPRI(x) (((x)&0x0F))
1127 +#define MCF_EDMA_DCHPRI6_ECP (0x80)
1129 +/* Bit definitions and macros for DCHPRI7 */
1130 +#define MCF_EDMA_DCHPRI7_CHPRI(x) (((x)&0x0F))
1131 +#define MCF_EDMA_DCHPRI7_ECP (0x80)
1133 +/* Bit definitions and macros for DCHPRI8 */
1134 +#define MCF_EDMA_DCHPRI8_CHPRI(x) (((x)&0x0F))
1135 +#define MCF_EDMA_DCHPRI8_ECP (0x80)
1137 +/* Bit definitions and macros for DCHPRI9 */
1138 +#define MCF_EDMA_DCHPRI9_CHPRI(x) (((x)&0x0F))
1139 +#define MCF_EDMA_DCHPRI9_ECP (0x80)
1141 +/* Bit definitions and macros for DCHPRI10 */
1142 +#define MCF_EDMA_DCHPRI10_CHPRI(x) (((x)&0x0F))
1143 +#define MCF_EDMA_DCHPRI10_ECP (0x80)
1145 +/* Bit definitions and macros for DCHPRI11 */
1146 +#define MCF_EDMA_DCHPRI11_CHPRI(x) (((x)&0x0F))
1147 +#define MCF_EDMA_DCHPRI11_ECP (0x80)
1149 +/* Bit definitions and macros for DCHPRI12 */
1150 +#define MCF_EDMA_DCHPRI12_CHPRI(x) (((x)&0x0F))
1151 +#define MCF_EDMA_DCHPRI12_ECP (0x80)
1153 +/* Bit definitions and macros for DCHPRI13 */
1154 +#define MCF_EDMA_DCHPRI13_CHPRI(x) (((x)&0x0F))
1155 +#define MCF_EDMA_DCHPRI13_ECP (0x80)
1157 +/* Bit definitions and macros for DCHPRI14 */
1158 +#define MCF_EDMA_DCHPRI14_CHPRI(x) (((x)&0x0F))
1159 +#define MCF_EDMA_DCHPRI14_ECP (0x80)
1161 +/* Bit definitions and macros for DCHPRI15 */
1162 +#define MCF_EDMA_DCHPRI15_CHPRI(x) (((x)&0x0F))
1163 +#define MCF_EDMA_DCHPRI15_ECP (0x80)
1165 +/* Bit definitions and macros for TCD_SADDR group */
1166 +#define MCF_EDMA_TCD_SADDR_SADDR(x) (x)
1168 +/* Bit definitions and macros for TCD0_SADDR */
1169 +#define MCF_EDMA_TCD0_SADDR_SADDR(x) (x)
1171 +/* Bit definitions and macros for TCD_ATTR group */
1172 +#define MCF_EDMA_TCD_ATTR_DSIZE(x) (((x)&0x0007))
1173 +#define MCF_EDMA_TCD_ATTR_DMOD(x) (((x)&0x001F)<<3)
1174 +#define MCF_EDMA_TCD_ATTR_SSIZE(x) (((x)&0x0007)<<8)
1175 +#define MCF_EDMA_TCD_ATTR_SMOD(x) (((x)&0x001F)<<11)
1176 +#define MCF_EDMA_TCD_ATTR_SSIZE_8BIT (0x0000)
1177 +#define MCF_EDMA_TCD_ATTR_SSIZE_16BIT (0x0100)
1178 +#define MCF_EDMA_TCD_ATTR_SSIZE_32BIT (0x0200)
1179 +#define MCF_EDMA_TCD_ATTR_SSIZE_16BYTE (0x0400)
1180 +#define MCF_EDMA_TCD_ATTR_DSIZE_8BIT (0x0000)
1181 +#define MCF_EDMA_TCD_ATTR_DSIZE_16BIT (0x0001)
1182 +#define MCF_EDMA_TCD_ATTR_DSIZE_32BIT (0x0002)
1183 +#define MCF_EDMA_TCD_ATTR_DSIZE_16BYTE (0x0004)
1185 +/* Bit definitions and macros for TCD0_ATTR */
1186 +#define MCF_EDMA_TCD0_ATTR_DSIZE(x) (((x)&0x0007))
1187 +#define MCF_EDMA_TCD0_ATTR_DMOD(x) (((x)&0x001F)<<3)
1188 +#define MCF_EDMA_TCD0_ATTR_SSIZE(x) (((x)&0x0007)<<8)
1189 +#define MCF_EDMA_TCD0_ATTR_SMOD(x) (((x)&0x001F)<<11)
1190 +#define MCF_EDMA_TCD0_ATTR_SSIZE_8BIT (0x0000)
1191 +#define MCF_EDMA_TCD0_ATTR_SSIZE_16BIT (0x0100)
1192 +#define MCF_EDMA_TCD0_ATTR_SSIZE_32BIT (0x0200)
1193 +#define MCF_EDMA_TCD0_ATTR_SSIZE_16BYTE (0x0400)
1194 +#define MCF_EDMA_TCD0_ATTR_DSIZE_8BIT (0x0000)
1195 +#define MCF_EDMA_TCD0_ATTR_DSIZE_16BIT (0x0001)
1196 +#define MCF_EDMA_TCD0_ATTR_DSIZE_32BIT (0x0002)
1197 +#define MCF_EDMA_TCD0_ATTR_DSIZE_16BYTE (0x0004)
1199 +/* Bit definitions and macros for TCD_SOFF group */
1200 +#define MCF_EDMA_TCD_SOFF_SOFF(x) (x)
1202 +/* Bit definitions and macros for TCD0_SOFF */
1203 +#define MCF_EDMA_TCD0_SOFF_SOFF(x) (x)
1205 +/* Bit definitions and macros for TCD_NBYTES group */
1206 +#define MCF_EDMA_TCD_NBYTES_NBYTES(x) (x)
1208 +/* Bit definitions and macros for TCD0_NBYTES */
1209 +#define MCF_EDMA_TCD0_NBYTES_NBYTES(x) (x)
1211 +/* Bit definitions and macros for TCD_SLAST group */
1212 +#define MCF_EDMA_TCD_SLAST_SLAST(x) (x)
1214 +/* Bit definitions and macros for TCD0_SLAST */
1215 +#define MCF_EDMA_TCD0_SLAST_SLAST(x) (x)
1217 +/* Bit definitions and macros for TCD_DADDR group */
1218 +#define MCF_EDMA_TCD_DADDR_DADDR(x) (x)
1220 +/* Bit definitions and macros for TCD0_DADDR */
1221 +#define MCF_EDMA_TCD0_DADDR_DADDR(x) (x)
1223 +/* Bit definitions and macros for TCD_CITER_ELINK group */
1224 +#define MCF_EDMA_TCD_CITER_ELINK_CITER(x) (((x)&0x01FF))
1225 +#define MCF_EDMA_TCD_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1226 +#define MCF_EDMA_TCD_CITER_ELINK_E_LINK (0x8000)
1228 +/* Bit definitions and macros for TCD0_CITER_ELINK */
1229 +#define MCF_EDMA_TCD0_CITER_ELINK_CITER(x) (((x)&0x01FF))
1230 +#define MCF_EDMA_TCD0_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1231 +#define MCF_EDMA_TCD0_CITER_ELINK_E_LINK (0x8000)
1233 +/* Bit definitions and macros for TCD_CITER group */
1234 +#define MCF_EDMA_TCD_CITER_CITER(x) (((x)&0x7FFF))
1235 +#define MCF_EDMA_TCD_CITER_E_LINK (0x8000)
1237 +/* Bit definitions and macros for TCD0_CITER */
1238 +#define MCF_EDMA_TCD0_CITER_CITER(x) (((x)&0x7FFF))
1239 +#define MCF_EDMA_TCD0_CITER_E_LINK (0x8000)
1241 +/* Bit definitions and macros for TCD_DOFF group */
1242 +#define MCF_EDMA_TCD_DOFF_DOFF(x) (x)
1244 +/* Bit definitions and macros for TCD0_DOFF */
1245 +#define MCF_EDMA_TCD0_DOFF_DOFF(x) (x)
1247 +/* Bit definitions and macros for TCD_DLAST_SGA group */
1248 +#define MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(x) (x)
1250 +/* Bit definitions and macros for TCD0_DLAST_SGA */
1251 +#define MCF_EDMA_TCD0_DLAST_SGA_DLAST_SGA(x) (x)
1253 +/* Bit definitions and macros for TCD_BITER_ELINK group */
1254 +#define MCF_EDMA_TCD_BITER_ELINK_BITER(x) (((x)&0x01FF))
1255 +#define MCF_EDMA_TCD_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1256 +#define MCF_EDMA_TCD_BITER_ELINK_E_LINK (0x8000)
1258 +/* Bit definitions and macros for TCD0_BITER_ELINK */
1259 +#define MCF_EDMA_TCD0_BITER_ELINK_BITER(x) (((x)&0x01FF))
1260 +#define MCF_EDMA_TCD0_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1261 +#define MCF_EDMA_TCD0_BITER_ELINK_E_LINK (0x8000)
1263 +/* Bit definitions and macros for TCD_BITER group */
1264 +#define MCF_EDMA_TCD_BITER_BITER(x) (((x)&0x7FFF))
1265 +#define MCF_EDMA_TCD_BITER_E_LINK (0x8000)
1267 +/* Bit definitions and macros for TCD0_BITER */
1268 +#define MCF_EDMA_TCD0_BITER_BITER(x) (((x)&0x7FFF))
1269 +#define MCF_EDMA_TCD0_BITER_E_LINK (0x8000)
1271 +/* Bit definitions and macros for TCD_CSR group */
1272 +#define MCF_EDMA_TCD_CSR_START (0x0001)
1273 +#define MCF_EDMA_TCD_CSR_INT_MAJOR (0x0002)
1274 +#define MCF_EDMA_TCD_CSR_INT_HALF (0x0004)
1275 +#define MCF_EDMA_TCD_CSR_D_REQ (0x0008)
1276 +#define MCF_EDMA_TCD_CSR_E_SG (0x0010)
1277 +#define MCF_EDMA_TCD_CSR_E_LINK (0x0020)
1278 +#define MCF_EDMA_TCD_CSR_ACTIVE (0x0040)
1279 +#define MCF_EDMA_TCD_CSR_DONE (0x0080)
1280 +#define MCF_EDMA_TCD_CSR_LINKCH(x) (((x)&0x003F)<<8)
1281 +#define MCF_EDMA_TCD_CSR_BWC(x) (((x)&0x0003)<<14)
1282 +#define MCF_EDMA_TCD_CSR_BWC_NO_STALL (0x0000)
1283 +#define MCF_EDMA_TCD_CSR_BWC_4CYC_STALL (0x8000)
1284 +#define MCF_EDMA_TCD_CSR_BWC_8CYC_STALL (0xC000)
1286 +/* Bit definitions and macros for TCD0_CSR */
1287 +#define MCF_EDMA_TCD0_CSR_START (0x0001)
1288 +#define MCF_EDMA_TCD0_CSR_INT_MAJOR (0x0002)
1289 +#define MCF_EDMA_TCD0_CSR_INT_HALF (0x0004)
1290 +#define MCF_EDMA_TCD0_CSR_D_REQ (0x0008)
1291 +#define MCF_EDMA_TCD0_CSR_E_SG (0x0010)
1292 +#define MCF_EDMA_TCD0_CSR_E_LINK (0x0020)
1293 +#define MCF_EDMA_TCD0_CSR_ACTIVE (0x0040)
1294 +#define MCF_EDMA_TCD0_CSR_DONE (0x0080)
1295 +#define MCF_EDMA_TCD0_CSR_LINKCH(x) (((x)&0x003F)<<8)
1296 +#define MCF_EDMA_TCD0_CSR_BWC(x) (((x)&0x0003)<<14)
1297 +#define MCF_EDMA_TCD0_CSR_BWC_NO_STALL (0x0000)
1298 +#define MCF_EDMA_TCD0_CSR_BWC_4CYC_STALL (0x8000)
1299 +#define MCF_EDMA_TCD0_CSR_BWC_8CYC_STALL (0xC000)
1301 +/* Bit definitions and macros for TCD1_SADDR */
1302 +#define MCF_EDMA_TCD1_SADDR_SADDR(x) (x)
1304 +/* Bit definitions and macros for TCD1_ATTR */
1305 +#define MCF_EDMA_TCD1_ATTR_DSIZE(x) (((x)&0x0007))
1306 +#define MCF_EDMA_TCD1_ATTR_DMOD(x) (((x)&0x001F)<<3)
1307 +#define MCF_EDMA_TCD1_ATTR_SSIZE(x) (((x)&0x0007)<<8)
1308 +#define MCF_EDMA_TCD1_ATTR_SMOD(x) (((x)&0x001F)<<11)
1310 +/* Bit definitions and macros for TCD1_SOFF */
1311 +#define MCF_EDMA_TCD1_SOFF_SOFF(x) (x)
1313 +/* Bit definitions and macros for TCD1_NBYTES */
1314 +#define MCF_EDMA_TCD1_NBYTES_NBYTES(x) (x)
1316 +/* Bit definitions and macros for TCD1_SLAST */
1317 +#define MCF_EDMA_TCD1_SLAST_SLAST(x) (x)
1319 +/* Bit definitions and macros for TCD1_DADDR */
1320 +#define MCF_EDMA_TCD1_DADDR_DADDR(x) (x)
1322 +/* Bit definitions and macros for TCD1_CITER_ELINK */
1323 +#define MCF_EDMA_TCD1_CITER_ELINK_CITER(x) (((x)&0x01FF))
1324 +#define MCF_EDMA_TCD1_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1325 +#define MCF_EDMA_TCD1_CITER_ELINK_E_LINK (0x8000)
1327 +/* Bit definitions and macros for TCD1_CITER */
1328 +#define MCF_EDMA_TCD1_CITER_CITER(x) (((x)&0x7FFF))
1329 +#define MCF_EDMA_TCD1_CITER_E_LINK (0x8000)
1331 +/* Bit definitions and macros for TCD1_DOFF */
1332 +#define MCF_EDMA_TCD1_DOFF_DOFF(x) (x)
1334 +/* Bit definitions and macros for TCD1_DLAST_SGA */
1335 +#define MCF_EDMA_TCD1_DLAST_SGA_DLAST_SGA(x) (x)
1337 +/* Bit definitions and macros for TCD1_BITER */
1338 +#define MCF_EDMA_TCD1_BITER_BITER(x) (((x)&0x7FFF))
1339 +#define MCF_EDMA_TCD1_BITER_E_LINK (0x8000)
1341 +/* Bit definitions and macros for TCD1_BITER_ELINK */
1342 +#define MCF_EDMA_TCD1_BITER_ELINK_BITER(x) (((x)&0x01FF))
1343 +#define MCF_EDMA_TCD1_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1344 +#define MCF_EDMA_TCD1_BITER_ELINK_E_LINK (0x8000)
1346 +/* Bit definitions and macros for TCD1_CSR */
1347 +#define MCF_EDMA_TCD1_CSR_START (0x0001)
1348 +#define MCF_EDMA_TCD1_CSR_INT_MAJOR (0x0002)
1349 +#define MCF_EDMA_TCD1_CSR_INT_HALF (0x0004)
1350 +#define MCF_EDMA_TCD1_CSR_D_REQ (0x0008)
1351 +#define MCF_EDMA_TCD1_CSR_E_SG (0x0010)
1352 +#define MCF_EDMA_TCD1_CSR_E_LINK (0x0020)
1353 +#define MCF_EDMA_TCD1_CSR_ACTIVE (0x0040)
1354 +#define MCF_EDMA_TCD1_CSR_DONE (0x0080)
1355 +#define MCF_EDMA_TCD1_CSR_LINKCH(x) (((x)&0x003F)<<8)
1356 +#define MCF_EDMA_TCD1_CSR_BWC(x) (((x)&0x0003)<<14)
1358 +/* Bit definitions and macros for TCD2_SADDR */
1359 +#define MCF_EDMA_TCD2_SADDR_SADDR(x) (x)
1361 +/* Bit definitions and macros for TCD2_ATTR */
1362 +#define MCF_EDMA_TCD2_ATTR_DSIZE(x) (((x)&0x0007))
1363 +#define MCF_EDMA_TCD2_ATTR_DMOD(x) (((x)&0x001F)<<3)
1364 +#define MCF_EDMA_TCD2_ATTR_SSIZE(x) (((x)&0x0007)<<8)
1365 +#define MCF_EDMA_TCD2_ATTR_SMOD(x) (((x)&0x001F)<<11)
1367 +/* Bit definitions and macros for TCD2_SOFF */
1368 +#define MCF_EDMA_TCD2_SOFF_SOFF(x) (x)
1370 +/* Bit definitions and macros for TCD2_NBYTES */
1371 +#define MCF_EDMA_TCD2_NBYTES_NBYTES(x) (x)
1373 +/* Bit definitions and macros for TCD2_SLAST */
1374 +#define MCF_EDMA_TCD2_SLAST_SLAST(x) (x)
1376 +/* Bit definitions and macros for TCD2_DADDR */
1377 +#define MCF_EDMA_TCD2_DADDR_DADDR(x) (x)
1379 +/* Bit definitions and macros for TCD2_CITER */
1380 +#define MCF_EDMA_TCD2_CITER_CITER(x) (((x)&0x7FFF))
1381 +#define MCF_EDMA_TCD2_CITER_E_LINK (0x8000)
1383 +/* Bit definitions and macros for TCD2_CITER_ELINK */
1384 +#define MCF_EDMA_TCD2_CITER_ELINK_CITER(x) (((x)&0x01FF))
1385 +#define MCF_EDMA_TCD2_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1386 +#define MCF_EDMA_TCD2_CITER_ELINK_E_LINK (0x8000)
1388 +/* Bit definitions and macros for TCD2_DOFF */
1389 +#define MCF_EDMA_TCD2_DOFF_DOFF(x) (x)
1391 +/* Bit definitions and macros for TCD2_DLAST_SGA */
1392 +#define MCF_EDMA_TCD2_DLAST_SGA_DLAST_SGA(x) (x)
1394 +/* Bit definitions and macros for TCD2_BITER_ELINK */
1395 +#define MCF_EDMA_TCD2_BITER_ELINK_BITER(x) (((x)&0x01FF))
1396 +#define MCF_EDMA_TCD2_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1397 +#define MCF_EDMA_TCD2_BITER_ELINK_E_LINK (0x8000)
1399 +/* Bit definitions and macros for TCD2_BITER */
1400 +#define MCF_EDMA_TCD2_BITER_BITER(x) (((x)&0x7FFF))
1401 +#define MCF_EDMA_TCD2_BITER_E_LINK (0x8000)
1403 +/* Bit definitions and macros for TCD2_CSR */
1404 +#define MCF_EDMA_TCD2_CSR_START (0x0001)
1405 +#define MCF_EDMA_TCD2_CSR_INT_MAJOR (0x0002)
1406 +#define MCF_EDMA_TCD2_CSR_INT_HALF (0x0004)
1407 +#define MCF_EDMA_TCD2_CSR_D_REQ (0x0008)
1408 +#define MCF_EDMA_TCD2_CSR_E_SG (0x0010)
1409 +#define MCF_EDMA_TCD2_CSR_E_LINK (0x0020)
1410 +#define MCF_EDMA_TCD2_CSR_ACTIVE (0x0040)
1411 +#define MCF_EDMA_TCD2_CSR_DONE (0x0080)
1412 +#define MCF_EDMA_TCD2_CSR_LINKCH(x) (((x)&0x003F)<<8)
1413 +#define MCF_EDMA_TCD2_CSR_BWC(x) (((x)&0x0003)<<14)
1415 +/* Bit definitions and macros for TCD3_SADDR */
1416 +#define MCF_EDMA_TCD3_SADDR_SADDR(x) (x)
1418 +/* Bit definitions and macros for TCD3_ATTR */
1419 +#define MCF_EDMA_TCD3_ATTR_DSIZE(x) (((x)&0x0007))
1420 +#define MCF_EDMA_TCD3_ATTR_DMOD(x) (((x)&0x001F)<<3)
1421 +#define MCF_EDMA_TCD3_ATTR_SSIZE(x) (((x)&0x0007)<<8)
1422 +#define MCF_EDMA_TCD3_ATTR_SMOD(x) (((x)&0x001F)<<11)
1424 +/* Bit definitions and macros for TCD3_SOFF */
1425 +#define MCF_EDMA_TCD3_SOFF_SOFF(x) (x)
1427 +/* Bit definitions and macros for TCD3_NBYTES */
1428 +#define MCF_EDMA_TCD3_NBYTES_NBYTES(x) (x)
1430 +/* Bit definitions and macros for TCD3_SLAST */
1431 +#define MCF_EDMA_TCD3_SLAST_SLAST(x) (x)
1433 +/* Bit definitions and macros for TCD3_DADDR */
1434 +#define MCF_EDMA_TCD3_DADDR_DADDR(x) (x)
1436 +/* Bit definitions and macros for TCD3_CITER */
1437 +#define MCF_EDMA_TCD3_CITER_CITER(x) (((x)&0x7FFF))
1438 +#define MCF_EDMA_TCD3_CITER_E_LINK (0x8000)
1440 +/* Bit definitions and macros for TCD3_CITER_ELINK */
1441 +#define MCF_EDMA_TCD3_CITER_ELINK_CITER(x) (((x)&0x01FF))
1442 +#define MCF_EDMA_TCD3_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1443 +#define MCF_EDMA_TCD3_CITER_ELINK_E_LINK (0x8000)
1445 +/* Bit definitions and macros for TCD3_DOFF */
1446 +#define MCF_EDMA_TCD3_DOFF_DOFF(x) (x)
1448 +/* Bit definitions and macros for TCD3_DLAST_SGA */
1449 +#define MCF_EDMA_TCD3_DLAST_SGA_DLAST_SGA(x) (x)
1451 +/* Bit definitions and macros for TCD3_BITER_ELINK */
1452 +#define MCF_EDMA_TCD3_BITER_ELINK_BITER(x) (((x)&0x01FF))
1453 +#define MCF_EDMA_TCD3_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1454 +#define MCF_EDMA_TCD3_BITER_ELINK_E_LINK (0x8000)
1456 +/* Bit definitions and macros for TCD3_BITER */
1457 +#define MCF_EDMA_TCD3_BITER_BITER(x) (((x)&0x7FFF))
1458 +#define MCF_EDMA_TCD3_BITER_E_LINK (0x8000)
1460 +/* Bit definitions and macros for TCD3_CSR */
1461 +#define MCF_EDMA_TCD3_CSR_START (0x0001)
1462 +#define MCF_EDMA_TCD3_CSR_INT_MAJOR (0x0002)
1463 +#define MCF_EDMA_TCD3_CSR_INT_HALF (0x0004)
1464 +#define MCF_EDMA_TCD3_CSR_D_REQ (0x0008)
1465 +#define MCF_EDMA_TCD3_CSR_E_SG (0x0010)
1466 +#define MCF_EDMA_TCD3_CSR_E_LINK (0x0020)
1467 +#define MCF_EDMA_TCD3_CSR_ACTIVE (0x0040)
1468 +#define MCF_EDMA_TCD3_CSR_DONE (0x0080)
1469 +#define MCF_EDMA_TCD3_CSR_LINKCH(x) (((x)&0x003F)<<8)
1470 +#define MCF_EDMA_TCD3_CSR_BWC(x) (((x)&0x0003)<<14)
1472 +/* Bit definitions and macros for TCD4_SADDR */
1473 +#define MCF_EDMA_TCD4_SADDR_SADDR(x) (x)
1475 +/* Bit definitions and macros for TCD4_ATTR */
1476 +#define MCF_EDMA_TCD4_ATTR_DSIZE(x) (((x)&0x0007))
1477 +#define MCF_EDMA_TCD4_ATTR_DMOD(x) (((x)&0x001F)<<3)
1478 +#define MCF_EDMA_TCD4_ATTR_SSIZE(x) (((x)&0x0007)<<8)
1479 +#define MCF_EDMA_TCD4_ATTR_SMOD(x) (((x)&0x001F)<<11)
1481 +/* Bit definitions and macros for TCD4_SOFF */
1482 +#define MCF_EDMA_TCD4_SOFF_SOFF(x) (x)
1484 +/* Bit definitions and macros for TCD4_NBYTES */
1485 +#define MCF_EDMA_TCD4_NBYTES_NBYTES(x) (x)
1487 +/* Bit definitions and macros for TCD4_SLAST */
1488 +#define MCF_EDMA_TCD4_SLAST_SLAST(x) (x)
1490 +/* Bit definitions and macros for TCD4_DADDR */
1491 +#define MCF_EDMA_TCD4_DADDR_DADDR(x) (x)
1493 +/* Bit definitions and macros for TCD4_CITER */
1494 +#define MCF_EDMA_TCD4_CITER_CITER(x) (((x)&0x7FFF))
1495 +#define MCF_EDMA_TCD4_CITER_E_LINK (0x8000)
1497 +/* Bit definitions and macros for TCD4_CITER_ELINK */
1498 +#define MCF_EDMA_TCD4_CITER_ELINK_CITER(x) (((x)&0x01FF))
1499 +#define MCF_EDMA_TCD4_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1500 +#define MCF_EDMA_TCD4_CITER_ELINK_E_LINK (0x8000)
1502 +/* Bit definitions and macros for TCD4_DOFF */
1503 +#define MCF_EDMA_TCD4_DOFF_DOFF(x) (x)
1505 +/* Bit definitions and macros for TCD4_DLAST_SGA */
1506 +#define MCF_EDMA_TCD4_DLAST_SGA_DLAST_SGA(x) (x)
1508 +/* Bit definitions and macros for TCD4_BITER */
1509 +#define MCF_EDMA_TCD4_BITER_BITER(x) (((x)&0x7FFF))
1510 +#define MCF_EDMA_TCD4_BITER_E_LINK (0x8000)
1512 +/* Bit definitions and macros for TCD4_BITER_ELINK */
1513 +#define MCF_EDMA_TCD4_BITER_ELINK_BITER(x) (((x)&0x01FF))
1514 +#define MCF_EDMA_TCD4_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1515 +#define MCF_EDMA_TCD4_BITER_ELINK_E_LINK (0x8000)
1517 +/* Bit definitions and macros for TCD4_CSR */
1518 +#define MCF_EDMA_TCD4_CSR_START (0x0001)
1519 +#define MCF_EDMA_TCD4_CSR_INT_MAJOR (0x0002)
1520 +#define MCF_EDMA_TCD4_CSR_INT_HALF (0x0004)
1521 +#define MCF_EDMA_TCD4_CSR_D_REQ (0x0008)
1522 +#define MCF_EDMA_TCD4_CSR_E_SG (0x0010)
1523 +#define MCF_EDMA_TCD4_CSR_E_LINK (0x0020)
1524 +#define MCF_EDMA_TCD4_CSR_ACTIVE (0x0040)
1525 +#define MCF_EDMA_TCD4_CSR_DONE (0x0080)
1526 +#define MCF_EDMA_TCD4_CSR_LINKCH(x) (((x)&0x003F)<<8)
1527 +#define MCF_EDMA_TCD4_CSR_BWC(x) (((x)&0x0003)<<14)
1529 +/* Bit definitions and macros for TCD5_SADDR */
1530 +#define MCF_EDMA_TCD5_SADDR_SADDR(x) (x)
1532 +/* Bit definitions and macros for TCD5_ATTR */
1533 +#define MCF_EDMA_TCD5_ATTR_DSIZE(x) (((x)&0x0007))
1534 +#define MCF_EDMA_TCD5_ATTR_DMOD(x) (((x)&0x001F)<<3)
1535 +#define MCF_EDMA_TCD5_ATTR_SSIZE(x) (((x)&0x0007)<<8)
1536 +#define MCF_EDMA_TCD5_ATTR_SMOD(x) (((x)&0x001F)<<11)
1538 +/* Bit definitions and macros for TCD5_SOFF */
1539 +#define MCF_EDMA_TCD5_SOFF_SOFF(x) (x)
1541 +/* Bit definitions and macros for TCD5_NBYTES */
1542 +#define MCF_EDMA_TCD5_NBYTES_NBYTES(x) (x)
1544 +/* Bit definitions and macros for TCD5_SLAST */
1545 +#define MCF_EDMA_TCD5_SLAST_SLAST(x) (x)
1547 +/* Bit definitions and macros for TCD5_DADDR */
1548 +#define MCF_EDMA_TCD5_DADDR_DADDR(x) (x)
1550 +/* Bit definitions and macros for TCD5_CITER */
1551 +#define MCF_EDMA_TCD5_CITER_CITER(x) (((x)&0x7FFF))
1552 +#define MCF_EDMA_TCD5_CITER_E_LINK (0x8000)
1554 +/* Bit definitions and macros for TCD5_CITER_ELINK */
1555 +#define MCF_EDMA_TCD5_CITER_ELINK_CITER(x) (((x)&0x01FF))
1556 +#define MCF_EDMA_TCD5_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1557 +#define MCF_EDMA_TCD5_CITER_ELINK_E_LINK (0x8000)
1559 +/* Bit definitions and macros for TCD5_DOFF */
1560 +#define MCF_EDMA_TCD5_DOFF_DOFF(x) (x)
1562 +/* Bit definitions and macros for TCD5_DLAST_SGA */
1563 +#define MCF_EDMA_TCD5_DLAST_SGA_DLAST_SGA(x) (x)
1565 +/* Bit definitions and macros for TCD5_BITER_ELINK */
1566 +#define MCF_EDMA_TCD5_BITER_ELINK_BITER(x) (((x)&0x01FF))
1567 +#define MCF_EDMA_TCD5_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1568 +#define MCF_EDMA_TCD5_BITER_ELINK_E_LINK (0x8000)
1570 +/* Bit definitions and macros for TCD5_BITER */
1571 +#define MCF_EDMA_TCD5_BITER_BITER(x) (((x)&0x7FFF))
1572 +#define MCF_EDMA_TCD5_BITER_E_LINK (0x8000)
1574 +/* Bit definitions and macros for TCD5_CSR */
1575 +#define MCF_EDMA_TCD5_CSR_START (0x0001)
1576 +#define MCF_EDMA_TCD5_CSR_INT_MAJOR (0x0002)
1577 +#define MCF_EDMA_TCD5_CSR_INT_HALF (0x0004)
1578 +#define MCF_EDMA_TCD5_CSR_D_REQ (0x0008)
1579 +#define MCF_EDMA_TCD5_CSR_E_SG (0x0010)
1580 +#define MCF_EDMA_TCD5_CSR_E_LINK (0x0020)
1581 +#define MCF_EDMA_TCD5_CSR_ACTIVE (0x0040)
1582 +#define MCF_EDMA_TCD5_CSR_DONE (0x0080)
1583 +#define MCF_EDMA_TCD5_CSR_LINKCH(x) (((x)&0x003F)<<8)
1584 +#define MCF_EDMA_TCD5_CSR_BWC(x) (((x)&0x0003)<<14)
1586 +/* Bit definitions and macros for TCD6_SADDR */
1587 +#define MCF_EDMA_TCD6_SADDR_SADDR(x) (x)
1589 +/* Bit definitions and macros for TCD6_ATTR */
1590 +#define MCF_EDMA_TCD6_ATTR_DSIZE(x) (((x)&0x0007))
1591 +#define MCF_EDMA_TCD6_ATTR_DMOD(x) (((x)&0x001F)<<3)
1592 +#define MCF_EDMA_TCD6_ATTR_SSIZE(x) (((x)&0x0007)<<8)
1593 +#define MCF_EDMA_TCD6_ATTR_SMOD(x) (((x)&0x001F)<<11)
1595 +/* Bit definitions and macros for TCD6_SOFF */
1596 +#define MCF_EDMA_TCD6_SOFF_SOFF(x) (x)
1598 +/* Bit definitions and macros for TCD6_NBYTES */
1599 +#define MCF_EDMA_TCD6_NBYTES_NBYTES(x) (x)
1601 +/* Bit definitions and macros for TCD6_SLAST */
1602 +#define MCF_EDMA_TCD6_SLAST_SLAST(x) (x)
1604 +/* Bit definitions and macros for TCD6_DADDR */
1605 +#define MCF_EDMA_TCD6_DADDR_DADDR(x) (x)
1607 +/* Bit definitions and macros for TCD6_CITER */
1608 +#define MCF_EDMA_TCD6_CITER_CITER(x) (((x)&0x7FFF))
1609 +#define MCF_EDMA_TCD6_CITER_E_LINK (0x8000)
1611 +/* Bit definitions and macros for TCD6_CITER_ELINK */
1612 +#define MCF_EDMA_TCD6_CITER_ELINK_CITER(x) (((x)&0x01FF))
1613 +#define MCF_EDMA_TCD6_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1614 +#define MCF_EDMA_TCD6_CITER_ELINK_E_LINK (0x8000)
1616 +/* Bit definitions and macros for TCD6_DOFF */
1617 +#define MCF_EDMA_TCD6_DOFF_DOFF(x) (x)
1619 +/* Bit definitions and macros for TCD6_DLAST_SGA */
1620 +#define MCF_EDMA_TCD6_DLAST_SGA_DLAST_SGA(x) (x)
1622 +/* Bit definitions and macros for TCD6_BITER_ELINK */
1623 +#define MCF_EDMA_TCD6_BITER_ELINK_BITER(x) (((x)&0x01FF))
1624 +#define MCF_EDMA_TCD6_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1625 +#define MCF_EDMA_TCD6_BITER_ELINK_E_LINK (0x8000)
1627 +/* Bit definitions and macros for TCD6_BITER */
1628 +#define MCF_EDMA_TCD6_BITER_BITER(x) (((x)&0x7FFF))
1629 +#define MCF_EDMA_TCD6_BITER_E_LINK (0x8000)
1631 +/* Bit definitions and macros for TCD6_CSR */
1632 +#define MCF_EDMA_TCD6_CSR_START (0x0001)
1633 +#define MCF_EDMA_TCD6_CSR_INT_MAJOR (0x0002)
1634 +#define MCF_EDMA_TCD6_CSR_INT_HALF (0x0004)
1635 +#define MCF_EDMA_TCD6_CSR_D_REQ (0x0008)
1636 +#define MCF_EDMA_TCD6_CSR_E_SG (0x0010)
1637 +#define MCF_EDMA_TCD6_CSR_E_LINK (0x0020)
1638 +#define MCF_EDMA_TCD6_CSR_ACTIVE (0x0040)
1639 +#define MCF_EDMA_TCD6_CSR_DONE (0x0080)
1640 +#define MCF_EDMA_TCD6_CSR_LINKCH(x) (((x)&0x003F)<<8)
1641 +#define MCF_EDMA_TCD6_CSR_BWC(x) (((x)&0x0003)<<14)
1643 +/* Bit definitions and macros for TCD7_SADDR */
1644 +#define MCF_EDMA_TCD7_SADDR_SADDR(x) (x)
1646 +/* Bit definitions and macros for TCD7_ATTR */
1647 +#define MCF_EDMA_TCD7_ATTR_DSIZE(x) (((x)&0x0007))
1648 +#define MCF_EDMA_TCD7_ATTR_DMOD(x) (((x)&0x001F)<<3)
1649 +#define MCF_EDMA_TCD7_ATTR_SSIZE(x) (((x)&0x0007)<<8)
1650 +#define MCF_EDMA_TCD7_ATTR_SMOD(x) (((x)&0x001F)<<11)
1652 +/* Bit definitions and macros for TCD7_SOFF */
1653 +#define MCF_EDMA_TCD7_SOFF_SOFF(x) (x)
1655 +/* Bit definitions and macros for TCD7_NBYTES */
1656 +#define MCF_EDMA_TCD7_NBYTES_NBYTES(x) (x)
1658 +/* Bit definitions and macros for TCD7_SLAST */
1659 +#define MCF_EDMA_TCD7_SLAST_SLAST(x) (x)
1661 +/* Bit definitions and macros for TCD7_DADDR */
1662 +#define MCF_EDMA_TCD7_DADDR_DADDR(x) (x)
1664 +/* Bit definitions and macros for TCD7_CITER */
1665 +#define MCF_EDMA_TCD7_CITER_CITER(x) (((x)&0x7FFF))
1666 +#define MCF_EDMA_TCD7_CITER_E_LINK (0x8000)
1668 +/* Bit definitions and macros for TCD7_CITER_ELINK */
1669 +#define MCF_EDMA_TCD7_CITER_ELINK_CITER(x) (((x)&0x01FF))
1670 +#define MCF_EDMA_TCD7_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1671 +#define MCF_EDMA_TCD7_CITER_ELINK_E_LINK (0x8000)
1673 +/* Bit definitions and macros for TCD7_DOFF */
1674 +#define MCF_EDMA_TCD7_DOFF_DOFF(x) (x)
1676 +/* Bit definitions and macros for TCD7_DLAST_SGA */
1677 +#define MCF_EDMA_TCD7_DLAST_SGA_DLAST_SGA(x) (x)
1679 +/* Bit definitions and macros for TCD7_BITER_ELINK */
1680 +#define MCF_EDMA_TCD7_BITER_ELINK_BITER(x) (((x)&0x01FF))
1681 +#define MCF_EDMA_TCD7_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1682 +#define MCF_EDMA_TCD7_BITER_ELINK_E_LINK (0x8000)
1684 +/* Bit definitions and macros for TCD7_BITER */
1685 +#define MCF_EDMA_TCD7_BITER_BITER(x) (((x)&0x7FFF))
1686 +#define MCF_EDMA_TCD7_BITER_E_LINK (0x8000)
1688 +/* Bit definitions and macros for TCD7_CSR */
1689 +#define MCF_EDMA_TCD7_CSR_START (0x0001)
1690 +#define MCF_EDMA_TCD7_CSR_INT_MAJOR (0x0002)
1691 +#define MCF_EDMA_TCD7_CSR_INT_HALF (0x0004)
1692 +#define MCF_EDMA_TCD7_CSR_D_REQ (0x0008)
1693 +#define MCF_EDMA_TCD7_CSR_E_SG (0x0010)
1694 +#define MCF_EDMA_TCD7_CSR_E_LINK (0x0020)
1695 +#define MCF_EDMA_TCD7_CSR_ACTIVE (0x0040)
1696 +#define MCF_EDMA_TCD7_CSR_DONE (0x0080)
1697 +#define MCF_EDMA_TCD7_CSR_LINKCH(x) (((x)&0x003F)<<8)
1698 +#define MCF_EDMA_TCD7_CSR_BWC(x) (((x)&0x0003)<<14)
1700 +/* Bit definitions and macros for TCD8_SADDR */
1701 +#define MCF_EDMA_TCD8_SADDR_SADDR(x) (x)
1703 +/* Bit definitions and macros for TCD8_ATTR */
1704 +#define MCF_EDMA_TCD8_ATTR_DSIZE(x) (((x)&0x0007))
1705 +#define MCF_EDMA_TCD8_ATTR_DMOD(x) (((x)&0x001F)<<3)
1706 +#define MCF_EDMA_TCD8_ATTR_SSIZE(x) (((x)&0x0007)<<8)
1707 +#define MCF_EDMA_TCD8_ATTR_SMOD(x) (((x)&0x001F)<<11)
1709 +/* Bit definitions and macros for TCD8_SOFF */
1710 +#define MCF_EDMA_TCD8_SOFF_SOFF(x) (x)
1712 +/* Bit definitions and macros for TCD8_NBYTES */
1713 +#define MCF_EDMA_TCD8_NBYTES_NBYTES(x) (x)
1715 +/* Bit definitions and macros for TCD8_SLAST */
1716 +#define MCF_EDMA_TCD8_SLAST_SLAST(x) (x)
1718 +/* Bit definitions and macros for TCD8_DADDR */
1719 +#define MCF_EDMA_TCD8_DADDR_DADDR(x) (x)
1721 +/* Bit definitions and macros for TCD8_CITER */
1722 +#define MCF_EDMA_TCD8_CITER_CITER(x) (((x)&0x7FFF))
1723 +#define MCF_EDMA_TCD8_CITER_E_LINK (0x8000)
1725 +/* Bit definitions and macros for TCD8_CITER_ELINK */
1726 +#define MCF_EDMA_TCD8_CITER_ELINK_CITER(x) (((x)&0x01FF))
1727 +#define MCF_EDMA_TCD8_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1728 +#define MCF_EDMA_TCD8_CITER_ELINK_E_LINK (0x8000)
1730 +/* Bit definitions and macros for TCD8_DOFF */
1731 +#define MCF_EDMA_TCD8_DOFF_DOFF(x) (x)
1733 +/* Bit definitions and macros for TCD8_DLAST_SGA */
1734 +#define MCF_EDMA_TCD8_DLAST_SGA_DLAST_SGA(x) (x)
1736 +/* Bit definitions and macros for TCD8_BITER_ELINK */
1737 +#define MCF_EDMA_TCD8_BITER_ELINK_BITER(x) (((x)&0x01FF))
1738 +#define MCF_EDMA_TCD8_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1739 +#define MCF_EDMA_TCD8_BITER_ELINK_E_LINK (0x8000)
1741 +/* Bit definitions and macros for TCD8_BITER */
1742 +#define MCF_EDMA_TCD8_BITER_BITER(x) (((x)&0x7FFF))
1743 +#define MCF_EDMA_TCD8_BITER_E_LINK (0x8000)
1745 +/* Bit definitions and macros for TCD8_CSR */
1746 +#define MCF_EDMA_TCD8_CSR_START (0x0001)
1747 +#define MCF_EDMA_TCD8_CSR_INT_MAJOR (0x0002)
1748 +#define MCF_EDMA_TCD8_CSR_INT_HALF (0x0004)
1749 +#define MCF_EDMA_TCD8_CSR_D_REQ (0x0008)
1750 +#define MCF_EDMA_TCD8_CSR_E_SG (0x0010)
1751 +#define MCF_EDMA_TCD8_CSR_E_LINK (0x0020)
1752 +#define MCF_EDMA_TCD8_CSR_ACTIVE (0x0040)
1753 +#define MCF_EDMA_TCD8_CSR_DONE (0x0080)
1754 +#define MCF_EDMA_TCD8_CSR_LINKCH(x) (((x)&0x003F)<<8)
1755 +#define MCF_EDMA_TCD8_CSR_BWC(x) (((x)&0x0003)<<14)
1757 +/* Bit definitions and macros for TCD9_SADDR */
1758 +#define MCF_EDMA_TCD9_SADDR_SADDR(x) (x)
1760 +/* Bit definitions and macros for TCD9_ATTR */
1761 +#define MCF_EDMA_TCD9_ATTR_DSIZE(x) (((x)&0x0007))
1762 +#define MCF_EDMA_TCD9_ATTR_DMOD(x) (((x)&0x001F)<<3)
1763 +#define MCF_EDMA_TCD9_ATTR_SSIZE(x) (((x)&0x0007)<<8)
1764 +#define MCF_EDMA_TCD9_ATTR_SMOD(x) (((x)&0x001F)<<11)
1766 +/* Bit definitions and macros for TCD9_SOFF */
1767 +#define MCF_EDMA_TCD9_SOFF_SOFF(x) (x)
1769 +/* Bit definitions and macros for TCD9_NBYTES */
1770 +#define MCF_EDMA_TCD9_NBYTES_NBYTES(x) (x)
1772 +/* Bit definitions and macros for TCD9_SLAST */
1773 +#define MCF_EDMA_TCD9_SLAST_SLAST(x) (x)
1775 +/* Bit definitions and macros for TCD9_DADDR */
1776 +#define MCF_EDMA_TCD9_DADDR_DADDR(x) (x)
1778 +/* Bit definitions and macros for TCD9_CITER_ELINK */
1779 +#define MCF_EDMA_TCD9_CITER_ELINK_CITER(x) (((x)&0x01FF))
1780 +#define MCF_EDMA_TCD9_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1781 +#define MCF_EDMA_TCD9_CITER_ELINK_E_LINK (0x8000)
1783 +/* Bit definitions and macros for TCD9_CITER */
1784 +#define MCF_EDMA_TCD9_CITER_CITER(x) (((x)&0x7FFF))
1785 +#define MCF_EDMA_TCD9_CITER_E_LINK (0x8000)
1787 +/* Bit definitions and macros for TCD9_DOFF */
1788 +#define MCF_EDMA_TCD9_DOFF_DOFF(x) (x)
1790 +/* Bit definitions and macros for TCD9_DLAST_SGA */
1791 +#define MCF_EDMA_TCD9_DLAST_SGA_DLAST_SGA(x) (x)
1793 +/* Bit definitions and macros for TCD9_BITER_ELINK */
1794 +#define MCF_EDMA_TCD9_BITER_ELINK_BITER(x) (((x)&0x01FF))
1795 +#define MCF_EDMA_TCD9_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1796 +#define MCF_EDMA_TCD9_BITER_ELINK_E_LINK (0x8000)
1798 +/* Bit definitions and macros for TCD9_BITER */
1799 +#define MCF_EDMA_TCD9_BITER_BITER(x) (((x)&0x7FFF))
1800 +#define MCF_EDMA_TCD9_BITER_E_LINK (0x8000)
1802 +/* Bit definitions and macros for TCD9_CSR */
1803 +#define MCF_EDMA_TCD9_CSR_START (0x0001)
1804 +#define MCF_EDMA_TCD9_CSR_INT_MAJOR (0x0002)
1805 +#define MCF_EDMA_TCD9_CSR_INT_HALF (0x0004)
1806 +#define MCF_EDMA_TCD9_CSR_D_REQ (0x0008)
1807 +#define MCF_EDMA_TCD9_CSR_E_SG (0x0010)
1808 +#define MCF_EDMA_TCD9_CSR_E_LINK (0x0020)
1809 +#define MCF_EDMA_TCD9_CSR_ACTIVE (0x0040)
1810 +#define MCF_EDMA_TCD9_CSR_DONE (0x0080)
1811 +#define MCF_EDMA_TCD9_CSR_LINKCH(x) (((x)&0x003F)<<8)
1812 +#define MCF_EDMA_TCD9_CSR_BWC(x) (((x)&0x0003)<<14)
1814 +/* Bit definitions and macros for TCD10_SADDR */
1815 +#define MCF_EDMA_TCD10_SADDR_SADDR(x) (x)
1817 +/* Bit definitions and macros for TCD10_ATTR */
1818 +#define MCF_EDMA_TCD10_ATTR_DSIZE(x) (((x)&0x0007))
1819 +#define MCF_EDMA_TCD10_ATTR_DMOD(x) (((x)&0x001F)<<3)
1820 +#define MCF_EDMA_TCD10_ATTR_SSIZE(x) (((x)&0x0007)<<8)
1821 +#define MCF_EDMA_TCD10_ATTR_SMOD(x) (((x)&0x001F)<<11)
1823 +/* Bit definitions and macros for TCD10_SOFF */
1824 +#define MCF_EDMA_TCD10_SOFF_SOFF(x) (x)
1826 +/* Bit definitions and macros for TCD10_NBYTES */
1827 +#define MCF_EDMA_TCD10_NBYTES_NBYTES(x) (x)
1829 +/* Bit definitions and macros for TCD10_SLAST */
1830 +#define MCF_EDMA_TCD10_SLAST_SLAST(x) (x)
1832 +/* Bit definitions and macros for TCD10_DADDR */
1833 +#define MCF_EDMA_TCD10_DADDR_DADDR(x) (x)
1835 +/* Bit definitions and macros for TCD10_CITER_ELINK */
1836 +#define MCF_EDMA_TCD10_CITER_ELINK_CITER(x) (((x)&0x01FF))
1837 +#define MCF_EDMA_TCD10_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1838 +#define MCF_EDMA_TCD10_CITER_ELINK_E_LINK (0x8000)
1840 +/* Bit definitions and macros for TCD10_CITER */
1841 +#define MCF_EDMA_TCD10_CITER_CITER(x) (((x)&0x7FFF))
1842 +#define MCF_EDMA_TCD10_CITER_E_LINK (0x8000)
1844 +/* Bit definitions and macros for TCD10_DOFF */
1845 +#define MCF_EDMA_TCD10_DOFF_DOFF(x) (x)
1847 +/* Bit definitions and macros for TCD10_DLAST_SGA */
1848 +#define MCF_EDMA_TCD10_DLAST_SGA_DLAST_SGA(x) (x)
1850 +/* Bit definitions and macros for TCD10_BITER */
1851 +#define MCF_EDMA_TCD10_BITER_BITER(x) (((x)&0x7FFF))
1852 +#define MCF_EDMA_TCD10_BITER_E_LINK (0x8000)
1854 +/* Bit definitions and macros for TCD10_BITER_ELINK */
1855 +#define MCF_EDMA_TCD10_BITER_ELINK_BITER(x) (((x)&0x01FF))
1856 +#define MCF_EDMA_TCD10_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1857 +#define MCF_EDMA_TCD10_BITER_ELINK_E_LINK (0x8000)
1859 +/* Bit definitions and macros for TCD10_CSR */
1860 +#define MCF_EDMA_TCD10_CSR_START (0x0001)
1861 +#define MCF_EDMA_TCD10_CSR_INT_MAJOR (0x0002)
1862 +#define MCF_EDMA_TCD10_CSR_INT_HALF (0x0004)
1863 +#define MCF_EDMA_TCD10_CSR_D_REQ (0x0008)
1864 +#define MCF_EDMA_TCD10_CSR_E_SG (0x0010)
1865 +#define MCF_EDMA_TCD10_CSR_E_LINK (0x0020)
1866 +#define MCF_EDMA_TCD10_CSR_ACTIVE (0x0040)
1867 +#define MCF_EDMA_TCD10_CSR_DONE (0x0080)
1868 +#define MCF_EDMA_TCD10_CSR_LINKCH(x) (((x)&0x003F)<<8)
1869 +#define MCF_EDMA_TCD10_CSR_BWC(x) (((x)&0x0003)<<14)
1871 +/* Bit definitions and macros for TCD11_SADDR */
1872 +#define MCF_EDMA_TCD11_SADDR_SADDR(x) (x)
1874 +/* Bit definitions and macros for TCD11_ATTR */
1875 +#define MCF_EDMA_TCD11_ATTR_DSIZE(x) (((x)&0x0007))
1876 +#define MCF_EDMA_TCD11_ATTR_DMOD(x) (((x)&0x001F)<<3)
1877 +#define MCF_EDMA_TCD11_ATTR_SSIZE(x) (((x)&0x0007)<<8)
1878 +#define MCF_EDMA_TCD11_ATTR_SMOD(x) (((x)&0x001F)<<11)
1880 +/* Bit definitions and macros for TCD11_SOFF */
1881 +#define MCF_EDMA_TCD11_SOFF_SOFF(x) (x)
1883 +/* Bit definitions and macros for TCD11_NBYTES */
1884 +#define MCF_EDMA_TCD11_NBYTES_NBYTES(x) (x)
1886 +/* Bit definitions and macros for TCD11_SLAST */
1887 +#define MCF_EDMA_TCD11_SLAST_SLAST(x) (x)
1889 +/* Bit definitions and macros for TCD11_DADDR */
1890 +#define MCF_EDMA_TCD11_DADDR_DADDR(x) (x)
1892 +/* Bit definitions and macros for TCD11_CITER */
1893 +#define MCF_EDMA_TCD11_CITER_CITER(x) (((x)&0x7FFF))
1894 +#define MCF_EDMA_TCD11_CITER_E_LINK (0x8000)
1896 +/* Bit definitions and macros for TCD11_CITER_ELINK */
1897 +#define MCF_EDMA_TCD11_CITER_ELINK_CITER(x) (((x)&0x01FF))
1898 +#define MCF_EDMA_TCD11_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1899 +#define MCF_EDMA_TCD11_CITER_ELINK_E_LINK (0x8000)
1901 +/* Bit definitions and macros for TCD11_DOFF */
1902 +#define MCF_EDMA_TCD11_DOFF_DOFF(x) (x)
1904 +/* Bit definitions and macros for TCD11_DLAST_SGA */
1905 +#define MCF_EDMA_TCD11_DLAST_SGA_DLAST_SGA(x) (x)
1907 +/* Bit definitions and macros for TCD11_BITER */
1908 +#define MCF_EDMA_TCD11_BITER_BITER(x) (((x)&0x7FFF))
1909 +#define MCF_EDMA_TCD11_BITER_E_LINK (0x8000)
1911 +/* Bit definitions and macros for TCD11_BITER_ELINK */
1912 +#define MCF_EDMA_TCD11_BITER_ELINK_BITER(x) (((x)&0x01FF))
1913 +#define MCF_EDMA_TCD11_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1914 +#define MCF_EDMA_TCD11_BITER_ELINK_E_LINK (0x8000)
1916 +/* Bit definitions and macros for TCD11_CSR */
1917 +#define MCF_EDMA_TCD11_CSR_START (0x0001)
1918 +#define MCF_EDMA_TCD11_CSR_INT_MAJOR (0x0002)
1919 +#define MCF_EDMA_TCD11_CSR_INT_HALF (0x0004)
1920 +#define MCF_EDMA_TCD11_CSR_D_REQ (0x0008)
1921 +#define MCF_EDMA_TCD11_CSR_E_SG (0x0010)
1922 +#define MCF_EDMA_TCD11_CSR_E_LINK (0x0020)
1923 +#define MCF_EDMA_TCD11_CSR_ACTIVE (0x0040)
1924 +#define MCF_EDMA_TCD11_CSR_DONE (0x0080)
1925 +#define MCF_EDMA_TCD11_CSR_LINKCH(x) (((x)&0x003F)<<8)
1926 +#define MCF_EDMA_TCD11_CSR_BWC(x) (((x)&0x0003)<<14)
1928 +/* Bit definitions and macros for TCD12_SADDR */
1929 +#define MCF_EDMA_TCD12_SADDR_SADDR(x) (x)
1931 +/* Bit definitions and macros for TCD12_ATTR */
1932 +#define MCF_EDMA_TCD12_ATTR_DSIZE(x) (((x)&0x0007))
1933 +#define MCF_EDMA_TCD12_ATTR_DMOD(x) (((x)&0x001F)<<3)
1934 +#define MCF_EDMA_TCD12_ATTR_SSIZE(x) (((x)&0x0007)<<8)
1935 +#define MCF_EDMA_TCD12_ATTR_SMOD(x) (((x)&0x001F)<<11)
1937 +/* Bit definitions and macros for TCD12_SOFF */
1938 +#define MCF_EDMA_TCD12_SOFF_SOFF(x) (x)
1940 +/* Bit definitions and macros for TCD12_NBYTES */
1941 +#define MCF_EDMA_TCD12_NBYTES_NBYTES(x) (x)
1943 +/* Bit definitions and macros for TCD12_SLAST */
1944 +#define MCF_EDMA_TCD12_SLAST_SLAST(x) (x)
1946 +/* Bit definitions and macros for TCD12_DADDR */
1947 +#define MCF_EDMA_TCD12_DADDR_DADDR(x) (x)
1949 +/* Bit definitions and macros for TCD12_CITER */
1950 +#define MCF_EDMA_TCD12_CITER_CITER(x) (((x)&0x7FFF))
1951 +#define MCF_EDMA_TCD12_CITER_E_LINK (0x8000)
1953 +/* Bit definitions and macros for TCD12_CITER_ELINK */
1954 +#define MCF_EDMA_TCD12_CITER_ELINK_CITER(x) (((x)&0x01FF))
1955 +#define MCF_EDMA_TCD12_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1956 +#define MCF_EDMA_TCD12_CITER_ELINK_E_LINK (0x8000)
1958 +/* Bit definitions and macros for TCD12_DOFF */
1959 +#define MCF_EDMA_TCD12_DOFF_DOFF(x) (x)
1961 +/* Bit definitions and macros for TCD12_DLAST_SGA */
1962 +#define MCF_EDMA_TCD12_DLAST_SGA_DLAST_SGA(x) (x)
1964 +/* Bit definitions and macros for TCD12_BITER */
1965 +#define MCF_EDMA_TCD12_BITER_BITER(x) (((x)&0x7FFF))
1966 +#define MCF_EDMA_TCD12_BITER_E_LINK (0x8000)
1968 +/* Bit definitions and macros for TCD12_BITER_ELINK */
1969 +#define MCF_EDMA_TCD12_BITER_ELINK_BITER(x) (((x)&0x01FF))
1970 +#define MCF_EDMA_TCD12_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
1971 +#define MCF_EDMA_TCD12_BITER_ELINK_E_LINK (0x8000)
1973 +/* Bit definitions and macros for TCD12_CSR */
1974 +#define MCF_EDMA_TCD12_CSR_START (0x0001)
1975 +#define MCF_EDMA_TCD12_CSR_INT_MAJOR (0x0002)
1976 +#define MCF_EDMA_TCD12_CSR_INT_HALF (0x0004)
1977 +#define MCF_EDMA_TCD12_CSR_D_REQ (0x0008)
1978 +#define MCF_EDMA_TCD12_CSR_E_SG (0x0010)
1979 +#define MCF_EDMA_TCD12_CSR_E_LINK (0x0020)
1980 +#define MCF_EDMA_TCD12_CSR_ACTIVE (0x0040)
1981 +#define MCF_EDMA_TCD12_CSR_DONE (0x0080)
1982 +#define MCF_EDMA_TCD12_CSR_LINKCH(x) (((x)&0x003F)<<8)
1983 +#define MCF_EDMA_TCD12_CSR_BWC(x) (((x)&0x0003)<<14)
1985 +/* Bit definitions and macros for TCD13_SADDR */
1986 +#define MCF_EDMA_TCD13_SADDR_SADDR(x) (x)
1988 +/* Bit definitions and macros for TCD13_ATTR */
1989 +#define MCF_EDMA_TCD13_ATTR_DSIZE(x) (((x)&0x0007))
1990 +#define MCF_EDMA_TCD13_ATTR_DMOD(x) (((x)&0x001F)<<3)
1991 +#define MCF_EDMA_TCD13_ATTR_SSIZE(x) (((x)&0x0007)<<8)
1992 +#define MCF_EDMA_TCD13_ATTR_SMOD(x) (((x)&0x001F)<<11)
1994 +/* Bit definitions and macros for TCD13_SOFF */
1995 +#define MCF_EDMA_TCD13_SOFF_SOFF(x) (x)
1997 +/* Bit definitions and macros for TCD13_NBYTES */
1998 +#define MCF_EDMA_TCD13_NBYTES_NBYTES(x) (x)
2000 +/* Bit definitions and macros for TCD13_SLAST */
2001 +#define MCF_EDMA_TCD13_SLAST_SLAST(x) (x)
2003 +/* Bit definitions and macros for TCD13_DADDR */
2004 +#define MCF_EDMA_TCD13_DADDR_DADDR(x) (x)
2006 +/* Bit definitions and macros for TCD13_CITER_ELINK */
2007 +#define MCF_EDMA_TCD13_CITER_ELINK_CITER(x) (((x)&0x01FF))
2008 +#define MCF_EDMA_TCD13_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
2009 +#define MCF_EDMA_TCD13_CITER_ELINK_E_LINK (0x8000)
2011 +/* Bit definitions and macros for TCD13_CITER */
2012 +#define MCF_EDMA_TCD13_CITER_CITER(x) (((x)&0x7FFF))
2013 +#define MCF_EDMA_TCD13_CITER_E_LINK (0x8000)
2015 +/* Bit definitions and macros for TCD13_DOFF */
2016 +#define MCF_EDMA_TCD13_DOFF_DOFF(x) (x)
2018 +/* Bit definitions and macros for TCD13_DLAST_SGA */
2019 +#define MCF_EDMA_TCD13_DLAST_SGA_DLAST_SGA(x) (x)
2021 +/* Bit definitions and macros for TCD13_BITER_ELINK */
2022 +#define MCF_EDMA_TCD13_BITER_ELINK_BITER(x) (((x)&0x01FF))
2023 +#define MCF_EDMA_TCD13_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
2024 +#define MCF_EDMA_TCD13_BITER_ELINK_E_LINK (0x8000)
2026 +/* Bit definitions and macros for TCD13_BITER */
2027 +#define MCF_EDMA_TCD13_BITER_BITER(x) (((x)&0x7FFF))
2028 +#define MCF_EDMA_TCD13_BITER_E_LINK (0x8000)
2030 +/* Bit definitions and macros for TCD13_CSR */
2031 +#define MCF_EDMA_TCD13_CSR_START (0x0001)
2032 +#define MCF_EDMA_TCD13_CSR_INT_MAJOR (0x0002)
2033 +#define MCF_EDMA_TCD13_CSR_INT_HALF (0x0004)
2034 +#define MCF_EDMA_TCD13_CSR_D_REQ (0x0008)
2035 +#define MCF_EDMA_TCD13_CSR_E_SG (0x0010)
2036 +#define MCF_EDMA_TCD13_CSR_E_LINK (0x0020)
2037 +#define MCF_EDMA_TCD13_CSR_ACTIVE (0x0040)
2038 +#define MCF_EDMA_TCD13_CSR_DONE (0x0080)
2039 +#define MCF_EDMA_TCD13_CSR_LINKCH(x) (((x)&0x003F)<<8)
2040 +#define MCF_EDMA_TCD13_CSR_BWC(x) (((x)&0x0003)<<14)
2042 +/* Bit definitions and macros for TCD14_SADDR */
2043 +#define MCF_EDMA_TCD14_SADDR_SADDR(x) (x)
2045 +/* Bit definitions and macros for TCD14_ATTR */
2046 +#define MCF_EDMA_TCD14_ATTR_DSIZE(x) (((x)&0x0007))
2047 +#define MCF_EDMA_TCD14_ATTR_DMOD(x) (((x)&0x001F)<<3)
2048 +#define MCF_EDMA_TCD14_ATTR_SSIZE(x) (((x)&0x0007)<<8)
2049 +#define MCF_EDMA_TCD14_ATTR_SMOD(x) (((x)&0x001F)<<11)
2051 +/* Bit definitions and macros for TCD14_SOFF */
2052 +#define MCF_EDMA_TCD14_SOFF_SOFF(x) (x)
2054 +/* Bit definitions and macros for TCD14_NBYTES */
2055 +#define MCF_EDMA_TCD14_NBYTES_NBYTES(x) (x)
2057 +/* Bit definitions and macros for TCD14_SLAST */
2058 +#define MCF_EDMA_TCD14_SLAST_SLAST(x) (x)
2060 +/* Bit definitions and macros for TCD14_DADDR */
2061 +#define MCF_EDMA_TCD14_DADDR_DADDR(x) (x)
2063 +/* Bit definitions and macros for TCD14_CITER */
2064 +#define MCF_EDMA_TCD14_CITER_CITER(x) (((x)&0x7FFF))
2065 +#define MCF_EDMA_TCD14_CITER_E_LINK (0x8000)
2067 +/* Bit definitions and macros for TCD14_CITER_ELINK */
2068 +#define MCF_EDMA_TCD14_CITER_ELINK_CITER(x) (((x)&0x01FF))
2069 +#define MCF_EDMA_TCD14_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
2070 +#define MCF_EDMA_TCD14_CITER_ELINK_E_LINK (0x8000)
2072 +/* Bit definitions and macros for TCD14_DOFF */
2073 +#define MCF_EDMA_TCD14_DOFF_DOFF(x) (x)
2075 +/* Bit definitions and macros for TCD14_DLAST_SGA */
2076 +#define MCF_EDMA_TCD14_DLAST_SGA_DLAST_SGA(x) (x)
2078 +/* Bit definitions and macros for TCD14_BITER_ELINK */
2079 +#define MCF_EDMA_TCD14_BITER_ELINK_BITER(x) (((x)&0x01FF))
2080 +#define MCF_EDMA_TCD14_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
2081 +#define MCF_EDMA_TCD14_BITER_ELINK_E_LINK (0x8000)
2083 +/* Bit definitions and macros for TCD14_BITER */
2084 +#define MCF_EDMA_TCD14_BITER_BITER(x) (((x)&0x7FFF))
2085 +#define MCF_EDMA_TCD14_BITER_E_LINK (0x8000)
2087 +/* Bit definitions and macros for TCD14_CSR */
2088 +#define MCF_EDMA_TCD14_CSR_START (0x0001)
2089 +#define MCF_EDMA_TCD14_CSR_INT_MAJOR (0x0002)
2090 +#define MCF_EDMA_TCD14_CSR_INT_HALF (0x0004)
2091 +#define MCF_EDMA_TCD14_CSR_D_REQ (0x0008)
2092 +#define MCF_EDMA_TCD14_CSR_E_SG (0x0010)
2093 +#define MCF_EDMA_TCD14_CSR_E_LINK (0x0020)
2094 +#define MCF_EDMA_TCD14_CSR_ACTIVE (0x0040)
2095 +#define MCF_EDMA_TCD14_CSR_DONE (0x0080)
2096 +#define MCF_EDMA_TCD14_CSR_LINKCH(x) (((x)&0x003F)<<8)
2097 +#define MCF_EDMA_TCD14_CSR_BWC(x) (((x)&0x0003)<<14)
2099 +/* Bit definitions and macros for TCD15_SADDR */
2100 +#define MCF_EDMA_TCD15_SADDR_SADDR(x) (x)
2102 +/* Bit definitions and macros for TCD15_ATTR */
2103 +#define MCF_EDMA_TCD15_ATTR_DSIZE(x) (((x)&0x0007))
2104 +#define MCF_EDMA_TCD15_ATTR_DMOD(x) (((x)&0x001F)<<3)
2105 +#define MCF_EDMA_TCD15_ATTR_SSIZE(x) (((x)&0x0007)<<8)
2106 +#define MCF_EDMA_TCD15_ATTR_SMOD(x) (((x)&0x001F)<<11)
2108 +/* Bit definitions and macros for TCD15_SOFF */
2109 +#define MCF_EDMA_TCD15_SOFF_SOFF(x) (x)
2111 +/* Bit definitions and macros for TCD15_NBYTES */
2112 +#define MCF_EDMA_TCD15_NBYTES_NBYTES(x) (x)
2114 +/* Bit definitions and macros for TCD15_SLAST */
2115 +#define MCF_EDMA_TCD15_SLAST_SLAST(x) (x)
2117 +/* Bit definitions and macros for TCD15_DADDR */
2118 +#define MCF_EDMA_TCD15_DADDR_DADDR(x) (x)
2120 +/* Bit definitions and macros for TCD15_CITER_ELINK */
2121 +#define MCF_EDMA_TCD15_CITER_ELINK_CITER(x) (((x)&0x01FF))
2122 +#define MCF_EDMA_TCD15_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
2123 +#define MCF_EDMA_TCD15_CITER_ELINK_E_LINK (0x8000)
2125 +/* Bit definitions and macros for TCD15_CITER */
2126 +#define MCF_EDMA_TCD15_CITER_CITER(x) (((x)&0x7FFF))
2127 +#define MCF_EDMA_TCD15_CITER_E_LINK (0x8000)
2129 +/* Bit definitions and macros for TCD15_DOFF */
2130 +#define MCF_EDMA_TCD15_DOFF_DOFF(x) (x)
2132 +/* Bit definitions and macros for TCD15_DLAST_SGA */
2133 +#define MCF_EDMA_TCD15_DLAST_SGA_DLAST_SGA(x) (x)
2135 +/* Bit definitions and macros for TCD15_BITER */
2136 +#define MCF_EDMA_TCD15_BITER_BITER(x) (((x)&0x7FFF))
2137 +#define MCF_EDMA_TCD15_BITER_E_LINK (0x8000)
2139 +/* Bit definitions and macros for TCD15_BITER_ELINK */
2140 +#define MCF_EDMA_TCD15_BITER_ELINK_BITER(x) (((x)&0x01FF))
2141 +#define MCF_EDMA_TCD15_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
2142 +#define MCF_EDMA_TCD15_BITER_ELINK_E_LINK (0x8000)
2144 +/* Bit definitions and macros for TCD15_CSR */
2145 +#define MCF_EDMA_TCD15_CSR_START (0x0001)
2146 +#define MCF_EDMA_TCD15_CSR_INT_MAJOR (0x0002)
2147 +#define MCF_EDMA_TCD15_CSR_INT_HALF (0x0004)
2148 +#define MCF_EDMA_TCD15_CSR_D_REQ (0x0008)
2149 +#define MCF_EDMA_TCD15_CSR_E_SG (0x0010)
2150 +#define MCF_EDMA_TCD15_CSR_E_LINK (0x0020)
2151 +#define MCF_EDMA_TCD15_CSR_ACTIVE (0x0040)
2152 +#define MCF_EDMA_TCD15_CSR_DONE (0x0080)
2153 +#define MCF_EDMA_TCD15_CSR_LINKCH(x) (((x)&0x003F)<<8)
2154 +#define MCF_EDMA_TCD15_CSR_BWC(x) (((x)&0x0003)<<14)
2156 +/********************************************************************/
2158 +#endif /* __MCF5445X_EDMA_H__ */
2160 +++ b/include/asm-m68k/mcf5445x_eport.h
2163 + * Kurt Mahan kmahan@freescale.com
2165 + * Copyright Freescale Semiconductor, Inc. 2007
2167 + * This program is free software; you can redistribute it and/or modify it
2168 + * under the terms of the GNU General Public License as published by the
2169 + * Free Software Foundation; either version 2 of the License, or (at your
2170 + * option) any later version.
2173 +#ifndef __MCF5445X_EPORT_H__
2174 +#define __MCF5445X_EPORT_H__
2176 +/*********************************************************************
2178 +* Edge Port Module (EPORT)
2180 +*********************************************************************/
2182 +/* Register read/write macros */
2183 +#define MCF_EPORT_EPPAR MCF_REG16(0xFC094000)
2184 +#define MCF_EPORT_EPDDR MCF_REG08(0xFC094002)
2185 +#define MCF_EPORT_EPIER MCF_REG08(0xFC094003)
2186 +#define MCF_EPORT_EPDR MCF_REG08(0xFC094004)
2187 +#define MCF_EPORT_EPPDR MCF_REG08(0xFC094005)
2188 +#define MCF_EPORT_EPFR MCF_REG08(0xFC094006)
2190 +/* Bit definitions and macros for EPPAR */
2191 +#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
2192 +#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
2193 +#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
2194 +#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
2195 +#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
2196 +#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
2197 +#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
2198 +#define MCF_EPORT_EPPAR_LEVEL (0)
2199 +#define MCF_EPORT_EPPAR_RISING (1)
2200 +#define MCF_EPORT_EPPAR_FALLING (2)
2201 +#define MCF_EPORT_EPPAR_BOTH (3)
2202 +#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000)
2203 +#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
2204 +#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
2205 +#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
2206 +#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000)
2207 +#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
2208 +#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
2209 +#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
2210 +#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000)
2211 +#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400)
2212 +#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800)
2213 +#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00)
2214 +#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000)
2215 +#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100)
2216 +#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200)
2217 +#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300)
2218 +#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000)
2219 +#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040)
2220 +#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080)
2221 +#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0)
2222 +#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000)
2223 +#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010)
2224 +#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020)
2225 +#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030)
2226 +#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000)
2227 +#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004)
2228 +#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008)
2229 +#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C)
2231 +/* Bit definitions and macros for EPDDR */
2232 +#define MCF_EPORT_EPDDR_EPDD1 (0x02)
2233 +#define MCF_EPORT_EPDDR_EPDD2 (0x04)
2234 +#define MCF_EPORT_EPDDR_EPDD3 (0x08)
2235 +#define MCF_EPORT_EPDDR_EPDD4 (0x10)
2236 +#define MCF_EPORT_EPDDR_EPDD5 (0x20)
2237 +#define MCF_EPORT_EPDDR_EPDD6 (0x40)
2238 +#define MCF_EPORT_EPDDR_EPDD7 (0x80)
2240 +/* Bit definitions and macros for EPIER */
2241 +#define MCF_EPORT_EPIER_EPIE1 (0x02)
2242 +#define MCF_EPORT_EPIER_EPIE2 (0x04)
2243 +#define MCF_EPORT_EPIER_EPIE3 (0x08)
2244 +#define MCF_EPORT_EPIER_EPIE4 (0x10)
2245 +#define MCF_EPORT_EPIER_EPIE5 (0x20)
2246 +#define MCF_EPORT_EPIER_EPIE6 (0x40)
2247 +#define MCF_EPORT_EPIER_EPIE7 (0x80)
2249 +/* Bit definitions and macros for EPDR */
2250 +#define MCF_EPORT_EPDR_EPD1 (0x02)
2251 +#define MCF_EPORT_EPDR_EPD2 (0x04)
2252 +#define MCF_EPORT_EPDR_EPD3 (0x08)
2253 +#define MCF_EPORT_EPDR_EPD4 (0x10)
2254 +#define MCF_EPORT_EPDR_EPD5 (0x20)
2255 +#define MCF_EPORT_EPDR_EPD6 (0x40)
2256 +#define MCF_EPORT_EPDR_EPD7 (0x80)
2258 +/* Bit definitions and macros for EPPDR */
2259 +#define MCF_EPORT_EPPDR_EPPD1 (0x02)
2260 +#define MCF_EPORT_EPPDR_EPPD2 (0x04)
2261 +#define MCF_EPORT_EPPDR_EPPD3 (0x08)
2262 +#define MCF_EPORT_EPPDR_EPPD4 (0x10)
2263 +#define MCF_EPORT_EPPDR_EPPD5 (0x20)
2264 +#define MCF_EPORT_EPPDR_EPPD6 (0x40)
2265 +#define MCF_EPORT_EPPDR_EPPD7 (0x80)
2267 +/* Bit definitions and macros for EPFR */
2268 +#define MCF_EPORT_EPFR_EPF1 (0x02)
2269 +#define MCF_EPORT_EPFR_EPF2 (0x04)
2270 +#define MCF_EPORT_EPFR_EPF3 (0x08)
2271 +#define MCF_EPORT_EPFR_EPF4 (0x10)
2272 +#define MCF_EPORT_EPFR_EPF5 (0x20)
2273 +#define MCF_EPORT_EPFR_EPF6 (0x40)
2274 +#define MCF_EPORT_EPFR_EPF7 (0x80)
2276 +/********************************************************************/
2278 +#endif /* __MCF5445X_EPORT_H__ */
2280 +++ b/include/asm-m68k/mcf5445x_fbcs.h
2283 + * Matt Waddel Matt.Waddel@freescale.com
2285 + * Copyright Freescale Semiconductor, Inc. 2007
2287 + * This program is free software; you can redistribute it and/or modify it
2288 + * under the terms of the GNU General Public License as published by the
2289 + * Free Software Foundation; either version 2 of the License, or (at your
2290 + * option) any later version.
2293 +#ifndef __MCF5445X_FBCS_H__
2294 +#define __MCF5445X_FBCS_H__
2296 +/*********************************************************************
2298 +* FlexBus Chip Selects (FBCS)
2300 +*********************************************************************/
2302 +/* Register read/write macros */
2303 +#define MCF_FBCS_CSAR0 MCF_REG32(0xFC008000) /* Chip-select Addr Register */
2304 +#define MCF_FBCS_CSMR0 MCF_REG32(0xFC008004) /* Chip-select Mask Register */
2305 +#define MCF_FBCS_CSCR0 MCF_REG32(0xFC008008) /* Chip-select Cntl Register */
2306 +#define MCF_FBCS_CSAR1 MCF_REG32(0xFC00800C) /* Chip-select Addr Register */
2307 +#define MCF_FBCS_CSMR1 MCF_REG32(0xFC008010) /* Chip-select Mask Register */
2308 +#define MCF_FBCS_CSCR1 MCF_REG32(0xFC008014) /* Chip-select Cntl Register */
2309 +#define MCF_FBCS_CSAR2 MCF_REG32(0xFC008018) /* Chip-select Addr Register */
2310 +#define MCF_FBCS_CSMR2 MCF_REG32(0xFC00801C) /* Chip-select Mask Register */
2311 +#define MCF_FBCS_CSCR2 MCF_REG32(0xFC008020) /* Chip-select Cntl Register */
2312 +#define MCF_FBCS_CSAR3 MCF_REG32(0xFC008024) /* Chip-select Addr Register */
2313 +#define MCF_FBCS_CSMR3 MCF_REG32(0xFC008028) /* Chip-select Mask Register */
2314 +#define MCF_FBCS_CSCR3 MCF_REG32(0xFC00802C) /* Chip-select Cntl Register */
2316 +/* Parameterized register read/write macros for multiple registers */
2317 +#define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C)) /* Chip-select Addr Register */
2318 +#define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C)) /* Chip-select Mask Register */
2319 +#define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C)) /* Chip-select Cntl Register */
2321 +/* Bit definitions and macros for CSAR group */
2322 +#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
2324 +/* Bit definitions and macros for CSAR0 */
2325 +#define MCF_FBCS_CSAR0_BA(x) ((x)&0xFFFF0000)
2327 +/* Bit definitions and macros for CSMR group */
2328 +#define MCF_FBCS_CSMR_V (0x00000001) /* Valid bit */
2329 +#define MCF_FBCS_CSMR_WP (0x00000100) /* Write protect */
2330 +#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base addr mask */
2331 +#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
2332 +#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
2333 +#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
2334 +#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
2335 +#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
2336 +#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000)
2337 +#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000)
2338 +#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000)
2339 +#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000)
2340 +#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000)
2341 +#define MCF_FBCS_CSMR_BAM_8M (0x007F0000)
2342 +#define MCF_FBCS_CSMR_BAM_4M (0x003F0000)
2343 +#define MCF_FBCS_CSMR_BAM_2M (0x001F0000)
2344 +#define MCF_FBCS_CSMR_BAM_1M (0x000F0000)
2345 +#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000)
2346 +#define MCF_FBCS_CSMR_BAM_512K (0x00070000)
2347 +#define MCF_FBCS_CSMR_BAM_256K (0x00030000)
2348 +#define MCF_FBCS_CSMR_BAM_128K (0x00010000)
2349 +#define MCF_FBCS_CSMR_BAM_64K (0x00000000)
2351 +/* Bit definitions and macros for CSMR0 */
2352 +#define MCF_FBCS_CSMR0_V (0x00000001) /* Valid bit */
2353 +#define MCF_FBCS_CSMR0_WP (0x00000100) /* Write protect */
2354 +#define MCF_FBCS_CSMR0_BAM(x) (((x)&0x0000FFFF)<<16) /* Base addr mask */
2355 +#define MCF_FBCS_CSMR0_BAM_4G (0xFFFF0000)
2356 +#define MCF_FBCS_CSMR0_BAM_2G (0x7FFF0000)
2357 +#define MCF_FBCS_CSMR0_BAM_1G (0x3FFF0000)
2358 +#define MCF_FBCS_CSMR0_BAM_1024M (0x3FFF0000)
2359 +#define MCF_FBCS_CSMR0_BAM_512M (0x1FFF0000)
2360 +#define MCF_FBCS_CSMR0_BAM_256M (0x0FFF0000)
2361 +#define MCF_FBCS_CSMR0_BAM_128M (0x07FF0000)
2362 +#define MCF_FBCS_CSMR0_BAM_64M (0x03FF0000)
2363 +#define MCF_FBCS_CSMR0_BAM_32M (0x01FF0000)
2364 +#define MCF_FBCS_CSMR0_BAM_16M (0x00FF0000)
2365 +#define MCF_FBCS_CSMR0_BAM_8M (0x007F0000)
2366 +#define MCF_FBCS_CSMR0_BAM_4M (0x003F0000)
2367 +#define MCF_FBCS_CSMR0_BAM_2M (0x001F0000)
2368 +#define MCF_FBCS_CSMR0_BAM_1M (0x000F0000)
2369 +#define MCF_FBCS_CSMR0_BAM_1024K (0x000F0000)
2370 +#define MCF_FBCS_CSMR0_BAM_512K (0x00070000)
2371 +#define MCF_FBCS_CSMR0_BAM_256K (0x00030000)
2372 +#define MCF_FBCS_CSMR0_BAM_128K (0x00010000)
2373 +#define MCF_FBCS_CSMR0_BAM_64K (0x00000000)
2375 +/* Bit definitions and macros for CSCR group */
2376 +#define MCF_FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */
2377 +#define MCF_FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */
2378 +#define MCF_FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */
2379 +#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */
2380 +#define MCF_FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */
2381 +#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
2382 +#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
2383 +#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
2384 +#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
2385 +#define MCF_FBCS_CSCR_SWSEN (0x00800000) /* Secondary wait state enable */
2386 +#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
2387 +#define MCF_FBCS_CSCR_PS_8 (0x00000040)
2388 +#define MCF_FBCS_CSCR_PS_16 (0x00000080)
2389 +#define MCF_FBCS_CSCR_PS_32 (0x00000000)
2391 +/* Bit definitions and macros for CSCR0 */
2392 +#define MCF_FBCS_CSCR0_BSTW (0x00000008) /* Burst-write enable */
2393 +#define MCF_FBCS_CSCR0_BSTR (0x00000010) /* Burst-read enable */
2394 +#define MCF_FBCS_CSCR0_BEM (0x00000020) /* Byte-enable mode */
2395 +#define MCF_FBCS_CSCR0_PS(x) (((x)&0x00000003)<<6) /* Port size */
2396 +#define MCF_FBCS_CSCR0_AA (0x00000100) /* Auto-acknowledge */
2397 +#define MCF_FBCS_CSCR0_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
2398 +#define MCF_FBCS_CSCR0_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
2399 +#define MCF_FBCS_CSCR0_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
2400 +#define MCF_FBCS_CSCR0_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
2401 +#define MCF_FBCS_CSCR0_SWSEN (0x00800000) /* Secondary wait state enable */
2402 +#define MCF_FBCS_CSCR0_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
2403 +#define MCF_FBCS_CSCR0_PS_8 (0x00000040)
2404 +#define MCF_FBCS_CSCR0_PS_16 (0x00000080)
2405 +#define MCF_FBCS_CSCR0_PS_32 (0x00000000)
2407 +/* Bit definitions and macros for CSMR1 */
2408 +#define MCF_FBCS_CSMR1_V (0x00000001) /* Valid bit */
2409 +#define MCF_FBCS_CSMR1_WP (0x00000100) /* Write protect */
2410 +#define MCF_FBCS_CSMR1_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
2412 +/* Bit definitions and macros for CSCR1 */
2413 +#define MCF_FBCS_CSCR1_BSTW (0x00000008) /* Burst-write enable */
2414 +#define MCF_FBCS_CSCR1_BSTR (0x00000010) /* Burst-read enable */
2415 +#define MCF_FBCS_CSCR1_BEM (0x00000020) /* Byte-enable mode */
2416 +#define MCF_FBCS_CSCR1_PS(x) (((x)&0x00000003)<<6) /* Port size */
2417 +#define MCF_FBCS_CSCR1_AA (0x00000100) /* Auto-acknowledge */
2418 +#define MCF_FBCS_CSCR1_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
2419 +#define MCF_FBCS_CSCR1_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
2420 +#define MCF_FBCS_CSCR1_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
2421 +#define MCF_FBCS_CSCR1_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
2422 +#define MCF_FBCS_CSCR1_SWSEN (0x00800000) /* Secondary wait state enable */
2423 +#define MCF_FBCS_CSCR1_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
2425 +/* Bit definitions and macros for CSMR2 */
2426 +#define MCF_FBCS_CSMR2_V (0x00000001) /* Valid bit */
2427 +#define MCF_FBCS_CSMR2_WP (0x00000100) /* Write protect */
2428 +#define MCF_FBCS_CSMR2_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
2430 +/* Bit definitions and macros for CSCR2 */
2431 +#define MCF_FBCS_CSCR2_BSTW (0x00000008) /* Burst-write enable */
2432 +#define MCF_FBCS_CSCR2_BSTR (0x00000010) /* Burst-read enable */
2433 +#define MCF_FBCS_CSCR2_BEM (0x00000020) /* Byte-enable mode */
2434 +#define MCF_FBCS_CSCR2_PS(x) (((x)&0x00000003)<<6) /* Port size */
2435 +#define MCF_FBCS_CSCR2_AA (0x00000100) /* Auto-acknowledge */
2436 +#define MCF_FBCS_CSCR2_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
2437 +#define MCF_FBCS_CSCR2_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
2438 +#define MCF_FBCS_CSCR2_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
2439 +#define MCF_FBCS_CSCR2_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
2440 +#define MCF_FBCS_CSCR2_SWSEN (0x00800000) /* Secondary wait state enable */
2441 +#define MCF_FBCS_CSCR2_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
2443 +/* Bit definitions and macros for CSMR3 */
2444 +#define MCF_FBCS_CSMR3_V (0x00000001) /* Valid bit */
2445 +#define MCF_FBCS_CSMR3_WP (0x00000100) /* Write protect */
2446 +#define MCF_FBCS_CSMR3_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
2448 +/* Bit definitions and macros for CSCR3 */
2449 +#define MCF_FBCS_CSCR3_BSTW (0x00000008) /* Burst-write enable */
2450 +#define MCF_FBCS_CSCR3_BSTR (0x00000010) /* Burst-read enable */
2451 +#define MCF_FBCS_CSCR3_BEM (0x00000020) /* Byte-enable mode */
2452 +#define MCF_FBCS_CSCR3_PS(x) (((x)&0x00000003)<<6) /* Port size */
2453 +#define MCF_FBCS_CSCR3_AA (0x00000100) /* Auto-acknowledge */
2454 +#define MCF_FBCS_CSCR3_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
2455 +#define MCF_FBCS_CSCR3_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
2456 +#define MCF_FBCS_CSCR3_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
2457 +#define MCF_FBCS_CSCR3_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
2458 +#define MCF_FBCS_CSCR3_SWSEN (0x00800000) /* Secondary wait state enable */
2459 +#define MCF_FBCS_CSCR3_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
2461 +/********************************************************************/
2463 +#endif /* __MCF5445X_FBCS_H__ */
2465 +++ b/include/asm-m68k/mcf5445x_gpio.h
2468 + * Matt Waddel Matt.Waddel@freescale.com
2470 + * Copyright Freescale Semiconductor, Inc. 2007
2472 + * This program is free software; you can redistribute it and/or modify it
2473 + * under the terms of the GNU General Public License as published by the
2474 + * Free Software Foundation; either version 2 of the License, or (at your
2475 + * option) any later version.
2478 +#ifndef __MCF5445X_GPIO_H__
2479 +#define __MCF5445X_GPIO_H__
2481 +/*********************************************************************
2483 +* General Purpose I/O Module (GPIO)
2485 +*********************************************************************/
2487 +/* Register read/write macros */
2488 +#define MCF_GPIO_PODR_FEC0H MCF_REG08(0xFC0A4000) /* FEC0 High Port Output Data Register */
2489 +#define MCF_GPIO_PODR_FEC0L MCF_REG08(0xFC0A4001) /* FEC0 Low Port Output Data Register */
2490 +#define MCF_GPIO_PODR_SSI MCF_REG08(0xFC0A4002) /* SSI Port Output Data Register */
2491 +#define MCF_GPIO_PODR_FBCTL MCF_REG08(0xFC0A4003) /* Flexbus Control Port Output Data Register */
2492 +#define MCF_GPIO_PODR_BE MCF_REG08(0xFC0A4004) /* Flexbus Byte Enable Port Output Data Register */
2493 +#define MCF_GPIO_PODR_CS MCF_REG08(0xFC0A4005) /* Flexbus Chip-Select Port Output Data Register */
2494 +#define MCF_GPIO_PODR_DMA MCF_REG08(0xFC0A4006) /* DMA Port Output Data Register */
2495 +#define MCF_GPIO_PODR_FECI2C MCF_REG08(0xFC0A4007) /* FEC1 / I2C Port Output Data Register */
2496 +#define MCF_GPIO_PODR_UART MCF_REG08(0xFC0A4009) /* UART Port Output Data Register */
2497 +#define MCF_GPIO_PODR_DSPI MCF_REG08(0xFC0A400A) /* DSPI Port Output Data Register */
2498 +#define MCF_GPIO_PODR_TIMER MCF_REG08(0xFC0A400B) /* Timer Port Output Data Register */
2499 +#define MCF_GPIO_PODR_PCI MCF_REG08(0xFC0A400C) /* PCI Port Output Data Register */
2500 +#define MCF_GPIO_PODR_USB MCF_REG08(0xFC0A400D) /* USB Port Output Data Register */
2501 +#define MCF_GPIO_PODR_ATAH MCF_REG08(0xFC0A400E) /* ATA High Port Output Data Register */
2502 +#define MCF_GPIO_PODR_ATAL MCF_REG08(0xFC0A400F) /* ATA Low Port Output Data Register */
2503 +#define MCF_GPIO_PODR_FEC1H MCF_REG08(0xFC0A4010) /* FEC1 High Port Output Data Register */
2504 +#define MCF_GPIO_PODR_FEC1L MCF_REG08(0xFC0A4011) /* FEC1 Low Port Output Data Register */
2505 +#define MCF_GPIO_PODR_FBADH MCF_REG08(0xFC0A4014) /* Flexbus AD High Port Output Data Register */
2506 +#define MCF_GPIO_PODR_FBADMH MCF_REG08(0xFC0A4015) /* Flexbus AD Med-High Port Output Data Register */
2507 +#define MCF_GPIO_PODR_FBADML MCF_REG08(0xFC0A4016) /* Flexbus AD Med-Low Port Output Data Register */
2508 +#define MCF_GPIO_PODR_FBADL MCF_REG08(0xFC0A4017) /* Flexbus AD Low Port Output Data Register */
2509 +#define MCF_GPIO_PDDR_FEC0H MCF_REG08(0xFC0A4018) /* FEC0 High Port Data Direction Register */
2510 +#define MCF_GPIO_PDDR_FEC0L MCF_REG08(0xFC0A4019) /* FEC0 Low Port Data Direction Register */
2511 +#define MCF_GPIO_PDDR_SSI MCF_REG08(0xFC0A401A) /* SSI Port Data Direction Register */
2512 +#define MCF_GPIO_PDDR_FBCTL MCF_REG08(0xFC0A401B) /* Flexbus Control Port Data Direction Register */
2513 +#define MCF_GPIO_PDDR_BE MCF_REG08(0xFC0A401C) /* Flexbus Byte Enable Port Data Direction Register */
2514 +#define MCF_GPIO_PDDR_CS MCF_REG08(0xFC0A401D) /* Flexbus Chip-Select Port Data Direction Register */
2515 +#define MCF_GPIO_PDDR_DMA MCF_REG08(0xFC0A401E) /* DMA Port Data Direction Register */
2516 +#define MCF_GPIO_PDDR_FECI2C MCF_REG08(0xFC0A401F) /* FEC1 / I2C Port Data Direction Register */
2517 +#define MCF_GPIO_PDDR_UART MCF_REG08(0xFC0A4021) /* UART Port Data Direction Register */
2518 +#define MCF_GPIO_PDDR_DSPI MCF_REG08(0xFC0A4022) /* DSPI Port Data Direction Register */
2519 +#define MCF_GPIO_PDDR_TIMER MCF_REG08(0xFC0A4023) /* Timer Port Data Direction Register */
2520 +#define MCF_GPIO_PDDR_PCI MCF_REG08(0xFC0A4024) /* PCI Port Data Direction Register */
2521 +#define MCF_GPIO_PDDR_USB MCF_REG08(0xFC0A4025) /* USB Port Data Direction Register */
2522 +#define MCF_GPIO_PDDR_ATAH MCF_REG08(0xFC0A4026) /* ATA High Port Data Direction Register */
2523 +#define MCF_GPIO_PDDR_ATAL MCF_REG08(0xFC0A4027) /* ATA Low Port Data Direction Register */
2524 +#define MCF_GPIO_PDDR_FEC1H MCF_REG08(0xFC0A4028) /* FEC1 High Port Data Direction Register */
2525 +#define MCF_GPIO_PDDR_FEC1L MCF_REG08(0xFC0A4029) /* FEC1 Low Port Data Direction Register */
2526 +#define MCF_GPIO_PDDR_FBADH MCF_REG08(0xFC0A402C) /* Flexbus AD High Port Data Direction Register */
2527 +#define MCF_GPIO_PDDR_FBADMH MCF_REG08(0xFC0A402D) /* Flexbus AD Med-High Port Data Direction Register */
2528 +#define MCF_GPIO_PDDR_FBADML MCF_REG08(0xFC0A402E) /* Flexbus AD Med-Low Port Data Direction Register */
2529 +#define MCF_GPIO_PDDR_FBADL MCF_REG08(0xFC0A402F) /* Flexbus AD Low Port Data Direction Register */
2530 +#define MCF_GPIO_PPDSDR_FEC0H MCF_REG08(0xFC0A4030) /* FEC0 High Port Pin Data/Set Data Register */
2531 +#define MCF_GPIO_PPDSDR_FEC0L MCF_REG08(0xFC0A4031) /* FEC0 Low Port Clear Output Data Register */
2532 +#define MCF_GPIO_PPDSDR_SSI MCF_REG08(0xFC0A4032) /* SSI Port Pin Data/Set Data Register */
2533 +#define MCF_GPIO_PPDSDR_FBCTL MCF_REG08(0xFC0A4033) /* Flexbus Control Port Pin Data/Set Data Register */
2534 +#define MCF_GPIO_PPDSDR_BE MCF_REG08(0xFC0A4034) /* Flexbus Byte Enable Port Pin Data/Set Data Register */
2535 +#define MCF_GPIO_PPDSDR_CS MCF_REG08(0xFC0A4035) /* Flexbus Chip-Select Port Pin Data/Set Data Register */
2536 +#define MCF_GPIO_PPDSDR_DMA MCF_REG08(0xFC0A4036) /* DMA Port Pin Data/Set Data Register */
2537 +#define MCF_GPIO_PPDSDR_FECI2C MCF_REG08(0xFC0A4037) /* FEC1 / I2C Port Pin Data/Set Data Register */
2538 +#define MCF_GPIO_PPDSDR_UART MCF_REG08(0xFC0A4039) /* UART Port Pin Data/Set Data Register */
2539 +#define MCF_GPIO_PPDSDR_DSPI MCF_REG08(0xFC0A403A) /* DSPI Port Pin Data/Set Data Register */
2540 +#define MCF_GPIO_PPDSDR_TIMER MCF_REG08(0xFC0A403B) /* FTimer Port Pin Data/Set Data Register */
2541 +#define MCF_GPIO_PPDSDR_PCI MCF_REG08(0xFC0A403C) /* PCI Port Pin Data/Set Data Register */
2542 +#define MCF_GPIO_PPDSDR_USB MCF_REG08(0xFC0A403D) /* USB Port Pin Data/Set Data Register */
2543 +#define MCF_GPIO_PPDSDR_ATAH MCF_REG08(0xFC0A403E) /* ATA High Port Pin Data/Set Data Register */
2544 +#define MCF_GPIO_PPDSDR_ATAL MCF_REG08(0xFC0A403F) /* ATA Low Port Pin Data/Set Data Register */
2545 +#define MCF_GPIO_PPDSDR_FEC1H MCF_REG08(0xFC0A4040) /* FEC1 High Port Pin Data/Set Data Register */
2546 +#define MCF_GPIO_PPDSDR_FEC1L MCF_REG08(0xFC0A4041) /* FEC1 Low Port Pin Data/Set Data Register */
2547 +#define MCF_GPIO_PPDSDR_FBADH MCF_REG08(0xFC0A4044) /* Flexbus AD High Port Pin Data/Set Data Register */
2548 +#define MCF_GPIO_PPDSDR_FBADMH MCF_REG08(0xFC0A4045) /* Flexbus AD Med-High Port Pin Data/Set Data Register */
2549 +#define MCF_GPIO_PPDSDR_FBADML MCF_REG08(0xFC0A4046) /* Flexbus AD Med-Low Port Pin Data/Set Data Register */
2550 +#define MCF_GPIO_PPDSDR_FBADL MCF_REG08(0xFC0A4047) /* Flexbus AD Low Port Pin Data/Set Data Register */
2551 +#define MCF_GPIO_PCLRR_FEC0H MCF_REG08(0xFC0A4048) /* FEC0 High Port Clear Output Data Register */
2552 +#define MCF_GPIO_PCLRR_FEC0L MCF_REG08(0xFC0A4049) /* FEC0 Low Port Pin Data/Set Data Register */
2553 +#define MCF_GPIO_PCLRR_SSI MCF_REG08(0xFC0A404A) /* SSI Port Clear Output Data Register */
2554 +#define MCF_GPIO_PCLRR_FBCTL MCF_REG08(0xFC0A404B) /* Flexbus Control Port Clear Output Data Register */
2555 +#define MCF_GPIO_PCLRR_BE MCF_REG08(0xFC0A404C) /* Flexbus Byte Enable Port Clear Output Data Register */
2556 +#define MCF_GPIO_PCLRR_CS MCF_REG08(0xFC0A404D) /* Flexbus Chip-Select Port Clear Output Data Register */
2557 +#define MCF_GPIO_PCLRR_DMA MCF_REG08(0xFC0A404E) /* DMA Port Clear Output Data Register */
2558 +#define MCF_GPIO_PCLRR_FECI2C MCF_REG08(0xFC0A404F) /* FEC1 / I2C Port Clear Output Data Register */
2559 +#define MCF_GPIO_PCLRR_UART MCF_REG08(0xFC0A4051) /* UART Port Clear Output Data Register */
2560 +#define MCF_GPIO_PCLRR_DSPI MCF_REG08(0xFC0A4052) /* DSPI Port Clear Output Data Register */
2561 +#define MCF_GPIO_PCLRR_TIMER MCF_REG08(0xFC0A4053) /* Timer Port Clear Output Data Register */
2562 +#define MCF_GPIO_PCLRR_PCI MCF_REG08(0xFC0A4054) /* PCI Port Clear Output Data Register */
2563 +#define MCF_GPIO_PCLRR_USB MCF_REG08(0xFC0A4055) /* USB Port Clear Output Data Register */
2564 +#define MCF_GPIO_PCLRR_ATAH MCF_REG08(0xFC0A4056) /* ATA High Port Clear Output Data Register */
2565 +#define MCF_GPIO_PCLRR_ATAL MCF_REG08(0xFC0A4057) /* ATA Low Port Clear Output Data Register */
2566 +#define MCF_GPIO_PCLRR_FEC1H MCF_REG08(0xFC0A4058) /* FEC1 High Port Clear Output Data Register */
2567 +#define MCF_GPIO_PCLRR_FEC1L MCF_REG08(0xFC0A4059) /* FEC1 Low Port Clear Output Data Register */
2568 +#define MCF_GPIO_PCLRR_FBADH MCF_REG08(0xFC0A405C) /* Flexbus AD High Port Clear Output Data Register */
2569 +#define MCF_GPIO_PCLRR_FBADMH MCF_REG08(0xFC0A405D) /* Flexbus AD Med-High Port Clear Output Data Register */
2570 +#define MCF_GPIO_PCLRR_FBADML MCF_REG08(0xFC0A405E) /* Flexbus AD Med-Low Port Clear Output Data Register */
2571 +#define MCF_GPIO_PCLRR_FBADL MCF_REG08(0xFC0A405F) /* Flexbus AD Low Port Clear Output Data Register */
2572 +#define MCF_GPIO_PAR_FEC MCF_REG08(0xFC0A4060) /* FEC Pin Assignment Register */
2573 +#define MCF_GPIO_PAR_DMA MCF_REG08(0xFC0A4061) /* DMA Pin Assignment Register */
2574 +#define MCF_GPIO_PAR_FBCTL MCF_REG08(0xFC0A4062) /* Flexbus Control Pin Assignment Register */
2575 +#define MCF_GPIO_PAR_DSPI MCF_REG08(0xFC0A4063) /* DSPI Pin Assignment Register */
2576 +#define MCF_GPIO_PAR_BE MCF_REG08(0xFC0A4064) /* Flexbus Byte-Enable Pin Assignment Register */
2577 +#define MCF_GPIO_PAR_CS MCF_REG08(0xFC0A4065) /* Flexbus Chip-Select Pin Assignment Register */
2578 +#define MCF_GPIO_PAR_TIMER MCF_REG08(0xFC0A4066) /* Time Pin Assignment Register */
2579 +#define MCF_GPIO_PAR_USB MCF_REG08(0xFC0A4067) /* USB Pin Assignment Register */
2580 +#define MCF_GPIO_PAR_UART MCF_REG08(0xFC0A4069) /* UART Pin Assignment Register */
2581 +#define MCF_GPIO_PAR_FECI2C MCF_REG16(0xFC0A406A) /* FEC / I2C Pin Assignment Register */
2582 +#define MCF_GPIO_PAR_SSI MCF_REG16(0xFC0A406C) /* SSI Pin Assignment Register */
2583 +#define MCF_GPIO_PAR_ATA MCF_REG16(0xFC0A406E) /* ATA Pin Assignment Register */
2584 +#define MCF_GPIO_PAR_IRQ MCF_REG08(0xFC0A4070) /* IRQ Pin Assignment Register */
2585 +#define MCF_GPIO_PAR_PCI MCF_REG16(0xFC0A4072) /* PCI Pin Assignment Register */
2586 +#define MCF_GPIO_MSCR_SDRAM MCF_REG08(0xFC0A4074) /* SDRAM Mode Select Control Register */
2587 +#define MCF_GPIO_MSCR_PCI MCF_REG08(0xFC0A4075) /* PCI Mode Select Control Register */
2588 +#define MCF_GPIO_DSCR_I2C MCF_REG08(0xFC0A4078) /* I2C Drive Strength Control Register */
2589 +#define MCF_GPIO_DSCR_FLEXBUS MCF_REG08(0xFC0A4079) /* FLEXBUS Drive Strength Control Register */
2590 +#define MCF_GPIO_DSCR_FEC MCF_REG08(0xFC0A407A) /* FEC Drive Strength Control Register */
2591 +#define MCF_GPIO_DSCR_UART MCF_REG08(0xFC0A407B) /* UART Drive Strength Control Register */
2592 +#define MCF_GPIO_DSCR_DSPI MCF_REG08(0xFC0A407C) /* DSPI Drive Strength Control Register */
2593 +#define MCF_GPIO_DSCR_TIMER MCF_REG08(0xFC0A407D) /* TIMER Drive Strength Control Register */
2594 +#define MCF_GPIO_DSCR_SSI MCF_REG08(0xFC0A407E) /* SSI Drive Strength Control Register */
2595 +#define MCF_GPIO_DSCR_DMA MCF_REG08(0xFC0A407F) /* DMA Drive Strength Control Register */
2596 +#define MCF_GPIO_DSCR_DEBUG MCF_REG08(0xFC0A4080) /* DEBUG Drive Strength Control Register */
2597 +#define MCF_GPIO_DSCR_RESET MCF_REG08(0xFC0A4081) /* RESET Drive Strength Control Register */
2598 +#define MCF_GPIO_DSCR_IRQ MCF_REG08(0xFC0A4082) /* IRQ Drive Strength Control Register */
2599 +#define MCF_GPIO_DSCR_USB MCF_REG08(0xFC0A4083) /* USB Drive Strength Control Register */
2600 +#define MCF_GPIO_DSCR_ATA MCF_REG08(0xFC0A4084) /* ATA Drive Strength Control Register */
2602 +/* Bit definitions and macros for PODR_FEC0H */
2603 +#define MCF_GPIO_PODR_FEC0H_PODR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */
2604 +#define MCF_GPIO_PODR_FEC0H_PODR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */
2605 +#define MCF_GPIO_PODR_FEC0H_PODR2 (0x04) /* FEC0_RXDV/FEC0_RMII_CRS_DV */
2606 +#define MCF_GPIO_PODR_FEC0H_PODR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */
2607 +#define MCF_GPIO_PODR_FEC0H_PODR4 (0x10) /* FEC0_COL / ULPI_DATA7 */
2608 +#define MCF_GPIO_PODR_FEC0H_PODR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */
2609 +#define MCF_GPIO_PODR_FEC0H_PODR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */
2610 +#define MCF_GPIO_PODR_FEC0H_PODR7 (0x80) /* FEC0_TXCLK / FEC0_RMII_REF_CLK */
2612 +/* Bit definitions and macros for PODR_FEC0L */
2613 +#define MCF_GPIO_PODR_FEC0L_PODR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */
2614 +#define MCF_GPIO_PODR_FEC0L_PODR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */
2615 +#define MCF_GPIO_PODR_FEC0L_PODR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */
2616 +#define MCF_GPIO_PODR_FEC0L_PODR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */
2617 +#define MCF_GPIO_PODR_FEC0L_PODR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */
2618 +#define MCF_GPIO_PODR_FEC0L_PODR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */
2619 +#define MCF_GPIO_PODR_FEC0L_PODR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */
2620 +#define MCF_GPIO_PODR_FEC0L_PODR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */
2622 +/* Bit definitions and macros for PODR_SSI */
2623 +#define MCF_GPIO_PODR_SSI_PODR0 (0x01) /* SSI_TXD / U1TXD */
2624 +#define MCF_GPIO_PODR_SSI_PODR1 (0x02) /* SSI_RXD / U1RXD */
2625 +#define MCF_GPIO_PODR_SSI_PODR2 (0x04) /* SSI_FS / U1RTS */
2626 +#define MCF_GPIO_PODR_SSI_PODR3 (0x08) /* SSI_BCLK / U1CTS */
2627 +#define MCF_GPIO_PODR_SSI_PODR4 (0x10) /* SSI_MCLK */
2629 +/* Bit definitions and macros for PODR_FBCTL */
2630 +#define MCF_GPIO_PODR_FBCTL_PODR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */
2631 +#define MCF_GPIO_PODR_FBCTL_PODR1 (0x02) /* FB_RW */
2632 +#define MCF_GPIO_PODR_FBCTL_PODR2 (0x04) /* FB_TA */
2633 +#define MCF_GPIO_PODR_FBCTL_PODR3 (0x08) /* FB_OE */
2635 +/* Bit definitions and macros for PODR_BE */
2636 +#define MCF_GPIO_PODR_BE_PODR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */
2637 +#define MCF_GPIO_PODR_BE_PODR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */
2638 +#define MCF_GPIO_PODR_BE_PODR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */
2639 +#define MCF_GPIO_PODR_BE_PODR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */
2641 +/* Bit definitions and macros for PODR_CS */
2642 +#define MCF_GPIO_PODR_CS_PODR1 (0x02) /* FB_CS1 */
2643 +#define MCF_GPIO_PODR_CS_PODR2 (0x04) /* FB_CS2 */
2644 +#define MCF_GPIO_PODR_CS_PODR3 (0x08) /* FB_CS3 */
2646 +/* Bit definitions and macros for PODR_DMA */
2647 +#define MCF_GPIO_PODR_DMA_PODR0 (0x01) /* DREQ0 */
2648 +#define MCF_GPIO_PODR_DMA_PODR1 (0x02) /* DACK0 / DSPI_PCS3 */
2649 +#define MCF_GPIO_PODR_DMA_PODR2 (0x04) /* DREQ1 / USB_CLKIN */
2650 +#define MCF_GPIO_PODR_DMA_PODR3 (0x08) /* DACK1 / ULPI_DIR */
2652 +/* Bit definitions and macros for PODR_FECI2C */
2653 +#define MCF_GPIO_PODR_FECI2C_PODR0 (0x01) /* I2C_SDA / U2RXD */
2654 +#define MCF_GPIO_PODR_FECI2C_PODR1 (0x02) /* I2C_SCL / U2TXD */
2655 +#define MCF_GPIO_PODR_FECI2C_PODR2 (0x04) /* FEC0_MDIO */
2656 +#define MCF_GPIO_PODR_FECI2C_PODR3 (0x08) /* FEC0_MDC */
2657 +#define MCF_GPIO_PODR_FECI2C_PODR4 (0x10) /* FEC1_MDIO / ATA_DIOW */
2658 +#define MCF_GPIO_PODR_FECI2C_PODR5 (0x20) /* FEC1_MDC / ATA_DIOR */
2660 +/* Bit definitions and macros for PODR_UART */
2661 +#define MCF_GPIO_PODR_UART_PODR0 (0x01) /* U1TXD */
2662 +#define MCF_GPIO_PODR_UART_PODR1 (0x02) /* U1RXD */
2663 +#define MCF_GPIO_PODR_UART_PODR2 (0x04) /* U1RTS */
2664 +#define MCF_GPIO_PODR_UART_PODR3 (0x08) /* U0CTS */
2665 +#define MCF_GPIO_PODR_UART_PODR4 (0x10) /* U1TXD */
2666 +#define MCF_GPIO_PODR_UART_PODR5 (0x20) /* U1RXD */
2667 +#define MCF_GPIO_PODR_UART_PODR6 (0x40) /* U1RTS */
2668 +#define MCF_GPIO_PODR_UART_PODR7 (0x80) /* U1CTS */
2670 +/* Bit definitions and macros for PODR_DSPI */
2671 +#define MCF_GPIO_PODR_DSPI_PODR0 (0x01) /* DSPI_SOUT / SBF_DO */
2672 +#define MCF_GPIO_PODR_DSPI_PODR1 (0x02) /* DSPI_SIN / SBF_DI */
2673 +#define MCF_GPIO_PODR_DSPI_PODR2 (0x04) /* DSPI_SCK / SBF_CK */
2674 +#define MCF_GPIO_PODR_DSPI_PODR3 (0x08) /* DSPI_PCS0/SS */
2675 +#define MCF_GPIO_PODR_DSPI_PODR4 (0x10) /* DSPI_PCS1 / SBF_CS */
2676 +#define MCF_GPIO_PODR_DSPI_PODR5 (0x20) /* DSPI_PCS2 */
2677 +#define MCF_GPIO_PODR_DSPI_PODR6 (0x40) /* DSPI_PCS5/SS */
2679 +/* Bit definitions and macros for PODR_TIMER */
2680 +#define MCF_GPIO_PODR_TIMER_PODR0 (0x01) /* T0IN / T0OUT / U2RTS */
2681 +#define MCF_GPIO_PODR_TIMER_PODR1 (0x02) /* T1IN / T1OUT / U2CTS */
2682 +#define MCF_GPIO_PODR_TIMER_PODR2 (0x04) /* T2IN / T2OUT / U2TXD */
2683 +#define MCF_GPIO_PODR_TIMER_PODR3 (0x08) /* T3IN / T3OUT / U2RXD */
2685 +/* Bit definitions and macros for PODR_PCI */
2686 +#define MCF_GPIO_PODR_PCI_PODR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */
2687 +#define MCF_GPIO_PODR_PCI_PODR1 (0x02) /* PCI_REQ1 */
2688 +#define MCF_GPIO_PODR_PCI_PODR2 (0x04) /* PCI_REQ2 */
2689 +#define MCF_GPIO_PODR_PCI_PODR3 (0x08) /* PCI_REQ3 / ATA_INTR */
2690 +#define MCF_GPIO_PODR_PCI_PODR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */
2691 +#define MCF_GPIO_PODR_PCI_PODR5 (0x20) /* PCI_GNT1 / */
2692 +#define MCF_GPIO_PODR_PCI_PODR6 (0x40) /* PCI_GNT2 / */
2693 +#define MCF_GPIO_PODR_PCI_PODR7 (0x80) /* PCI_GNT3 / ATA_DMACK */
2695 +/* Bit definitions and macros for PODR_USB */
2696 +#define MCF_GPIO_PODR_USB_PODR0 (0x01) /* USB_VBUS_OC / ULPI_STP */
2697 +#define MCF_GPIO_PODR_USB_PODR1 (0x02) /* USB_VBUS_EN / USB_PULLUP / ULPI_NXT */
2699 +/* Bit definitions and macros for PODR_ATAH */
2700 +#define MCF_GPIO_PODR_ATAH_PODR0 (0x01) /* ATA_DA0 */
2701 +#define MCF_GPIO_PODR_ATAH_PODR1 (0x02) /* ATA_DA1 */
2702 +#define MCF_GPIO_PODR_ATAH_PODR2 (0x04) /* ATA_DA2 */
2703 +#define MCF_GPIO_PODR_ATAH_PODR3 (0x08) /* ATA_CS0 */
2704 +#define MCF_GPIO_PODR_ATAH_PODR4 (0x10) /* ATA_CS1 */
2705 +#define MCF_GPIO_PODR_ATAH_PODR5 (0x20) /* ATA_BUFFER_EN */
2707 +/* Bit definitions and macros for PODR_ATAL */
2708 +#define MCF_GPIO_PODR_ATAL_PODR0 (0x01) /* ATA_IORDY */
2709 +#define MCF_GPIO_PODR_ATAL_PODR1 (0x02) /* ATA_DMARQ */
2710 +#define MCF_GPIO_PODR_ATAL_PODR2 (0x04) /* ATA_RESET */
2712 +/* Bit definitions and macros for PODR_FEC1H */
2713 +#define MCF_GPIO_PODR_FEC1H_PODR0 (0x01) /* FEC1_CRS / ATA_DATA6 */
2714 +#define MCF_GPIO_PODR_FEC1H_PODR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */
2715 +#define MCF_GPIO_PODR_FEC1H_PODR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */
2716 +#define MCF_GPIO_PODR_FEC1H_PODR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */
2717 +#define MCF_GPIO_PODR_FEC1H_PODR4 (0x10) /* FEC1_COL / ATA_DATA7 */
2718 +#define MCF_GPIO_PODR_FEC1H_PODR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */
2719 +#define MCF_GPIO_PODR_FEC1H_PODR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */
2720 +#define MCF_GPIO_PODR_FEC1H_PODR7 (0x80) /* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */
2722 +/* Bit definitions and macros for PODR_FEC1L */
2723 +#define MCF_GPIO_PODR_FEC1L_PODR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER / ATA_DATA12 */
2724 +#define MCF_GPIO_PODR_FEC1L_PODR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 / ATA_DATA14 */
2725 +#define MCF_GPIO_PODR_FEC1L_PODR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */
2726 +#define MCF_GPIO_PODR_FEC1L_PODR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */
2727 +#define MCF_GPIO_PODR_FEC1L_PODR4 (0x10) /* FEC1_TXER / ATA_DATA0 */
2728 +#define MCF_GPIO_PODR_FEC1L_PODR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 / ATA_DATA10 */
2729 +#define MCF_GPIO_PODR_FEC1L_PODR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */
2730 +#define MCF_GPIO_PODR_FEC1L_PODR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */
2732 +/* Bit definitions and macros for PODR_FBADH */
2733 +#define MCF_GPIO_PODR_FBADH_PODR0 (0x01) /* FB_AD24 */
2734 +#define MCF_GPIO_PODR_FBADH_PODR1 (0x02) /* FB_AD25 */
2735 +#define MCF_GPIO_PODR_FBADH_PODR2 (0x04) /* FB_AD26 */
2736 +#define MCF_GPIO_PODR_FBADH_PODR3 (0x08) /* FB_AD27 */
2737 +#define MCF_GPIO_PODR_FBADH_PODR4 (0x10) /* FB_AD28 */
2738 +#define MCF_GPIO_PODR_FBADH_PODR5 (0x20) /* FB_AD29 */
2739 +#define MCF_GPIO_PODR_FBADH_PODR6 (0x40) /* FB_AD30 */
2740 +#define MCF_GPIO_PODR_FBADH_PODR7 (0x80) /* FB_AD31 */
2742 +/* Bit definitions and macros for PODR_FBADMH */
2743 +#define MCF_GPIO_PODR_FBADMH_PODR0 (0x01) /* FB_AD16 */
2744 +#define MCF_GPIO_PODR_FBADMH_PODR1 (0x02) /* FB_AD17 */
2745 +#define MCF_GPIO_PODR_FBADMH_PODR2 (0x04) /* FB_AD18 */
2746 +#define MCF_GPIO_PODR_FBADMH_PODR3 (0x08) /* FB_AD19 */
2747 +#define MCF_GPIO_PODR_FBADMH_PODR4 (0x10) /* FB_AD20 */
2748 +#define MCF_GPIO_PODR_FBADMH_PODR5 (0x20) /* FB_AD21 */
2749 +#define MCF_GPIO_PODR_FBADMH_PODR6 (0x40) /* FB_AD22 */
2750 +#define MCF_GPIO_PODR_FBADMH_PODR7 (0x80) /* FB_AD23 */
2752 +/* Bit definitions and macros for PODR_FBADML */
2753 +#define MCF_GPIO_PODR_FBADML_PODR0 (0x01) /* FB_AD8 */
2754 +#define MCF_GPIO_PODR_FBADML_PODR1 (0x02) /* FB_AD9 */
2755 +#define MCF_GPIO_PODR_FBADML_PODR2 (0x04) /* FB_AD10 */
2756 +#define MCF_GPIO_PODR_FBADML_PODR3 (0x08) /* FB_AD11 */
2757 +#define MCF_GPIO_PODR_FBADML_PODR4 (0x10) /* FB_AD12 */
2758 +#define MCF_GPIO_PODR_FBADML_PODR5 (0x20) /* FB_AD13 */
2759 +#define MCF_GPIO_PODR_FBADML_PODR6 (0x40) /* FB_AD14 */
2760 +#define MCF_GPIO_PODR_FBADML_PODR7 (0x80) /* FB_AD15 */
2762 +/* Bit definitions and macros for PODR_FBADL */
2763 +#define MCF_GPIO_PODR_FBADL_PODR0 (0x01) /* FB_AD0 */
2764 +#define MCF_GPIO_PODR_FBADL_PODR1 (0x02) /* FB_AD1 */
2765 +#define MCF_GPIO_PODR_FBADL_PODR2 (0x04) /* FB_AD2 */
2766 +#define MCF_GPIO_PODR_FBADL_PODR3 (0x08) /* FB_AD3 */
2767 +#define MCF_GPIO_PODR_FBADL_PODR4 (0x10) /* FB_AD4 */
2768 +#define MCF_GPIO_PODR_FBADL_PODR5 (0x20) /* FB_AD5 */
2769 +#define MCF_GPIO_PODR_FBADL_PODR6 (0x40) /* FB_AD6 */
2770 +#define MCF_GPIO_PODR_FBADL_PODR7 (0x80) /* FB_AD7 */
2772 +/* Bit definitions and macros for PDDR_FEC0H */
2773 +#define MCF_GPIO_PDDR_FEC0H_PDDR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */
2774 +#define MCF_GPIO_PDDR_FEC0H_PDDR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */
2775 +#define MCF_GPIO_PDDR_FEC0H_PDDR2 (0x04) /* FEC0_RXDV/FEC0_RMII_CRS_DV */
2776 +#define MCF_GPIO_PDDR_FEC0H_PDDR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */
2777 +#define MCF_GPIO_PDDR_FEC0H_PDDR4 (0x10) /* FEC0_COL / ULPI_DATA7 */
2778 +#define MCF_GPIO_PDDR_FEC0H_PDDR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */
2779 +#define MCF_GPIO_PDDR_FEC0H_PDDR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */
2780 +#define MCF_GPIO_PDDR_FEC0H_PDDR7 (0x80) /* FEC0_TXCLK / FEC0_RMII_REF_CLK */
2782 +/* Bit definitions and macros for PDDR_FEC0L */
2783 +#define MCF_GPIO_PDDR_FEC0L_PDDR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */
2784 +#define MCF_GPIO_PDDR_FEC0L_PDDR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */
2785 +#define MCF_GPIO_PDDR_FEC0L_PDDR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */
2786 +#define MCF_GPIO_PDDR_FEC0L_PDDR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */
2787 +#define MCF_GPIO_PDDR_FEC0L_PDDR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */
2788 +#define MCF_GPIO_PDDR_FEC0L_PDDR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */
2789 +#define MCF_GPIO_PDDR_FEC0L_PDDR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */
2790 +#define MCF_GPIO_PDDR_FEC0L_PDDR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */
2792 +/* Bit definitions and macros for PDDR_SSI */
2793 +#define MCF_GPIO_PDDR_SSI_PDDR0 (0x01) /* SSI_TXD / U1TXD */
2794 +#define MCF_GPIO_PDDR_SSI_PDDR1 (0x02) /* SSI_RXD / U1RXD */
2795 +#define MCF_GPIO_PDDR_SSI_PDDR2 (0x04) /* SSI_FS / U1RTS */
2796 +#define MCF_GPIO_PDDR_SSI_PDDR3 (0x08) /* SSI_BCLK / U1CTS */
2797 +#define MCF_GPIO_PDDR_SSI_PDDR4 (0x10) /* SSI_MCLK */
2799 +/* Bit definitions and macros for PDDR_FBCTL */
2800 +#define MCF_GPIO_PDDR_FBCTL_PDDR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */
2801 +#define MCF_GPIO_PDDR_FBCTL_PDDR1 (0x02) /* FB_RW */
2802 +#define MCF_GPIO_PDDR_FBCTL_PDDR2 (0x04) /* FB_TA */
2803 +#define MCF_GPIO_PDDR_FBCTL_PDDR3 (0x08) /* FB_OE */
2805 +/* Bit definitions and macros for PDDR_BE */
2806 +#define MCF_GPIO_PDDR_BE_PDDR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */
2807 +#define MCF_GPIO_PDDR_BE_PDDR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */
2808 +#define MCF_GPIO_PDDR_BE_PDDR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */
2809 +#define MCF_GPIO_PDDR_BE_PDDR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */
2811 +/* Bit definitions and macros for PDDR_CS */
2812 +#define MCF_GPIO_PDDR_CS_PDDR1 (0x02) /* FB_CS1 */
2813 +#define MCF_GPIO_PDDR_CS_PDDR2 (0x04) /* FB_CS2 */
2814 +#define MCF_GPIO_PDDR_CS_PDDR3 (0x08) /* FB_CS3 */
2816 +/* Bit definitions and macros for PDDR_DMA */
2817 +#define MCF_GPIO_PDDR_DMA_PDDR0 (0x01) /* DREQ0 */
2818 +#define MCF_GPIO_PDDR_DMA_PDDR1 (0x02) /* DACK0 / DSPI_PCS3 */
2819 +#define MCF_GPIO_PDDR_DMA_PDDR2 (0x04) /* DREQ1 / USB_CLKIN */
2820 +#define MCF_GPIO_PDDR_DMA_PDDR3 (0x08) /* DACK1 / ULPI_DIR */
2822 +/* Bit definitions and macros for PDDR_FECI2C */
2823 +#define MCF_GPIO_PDDR_FECI2C_PDDR0 (0x01) /* I2C_SDA / U2RXD */
2824 +#define MCF_GPIO_PDDR_FECI2C_PDDR1 (0x02) /* I2C_SCL / U2TXD */
2825 +#define MCF_GPIO_PDDR_FECI2C_PDDR2 (0x04) /* FEC0_MDIO */
2826 +#define MCF_GPIO_PDDR_FECI2C_PDDR3 (0x08) /* FEC0_MDC */
2827 +#define MCF_GPIO_PDDR_FECI2C_PDDR4 (0x10) /* FEC1_MDIO / ATA_DIOW */
2828 +#define MCF_GPIO_PDDR_FECI2C_PDDR5 (0x20) /* FEC1_MDC / ATA_DIOR */
2830 +/* Bit definitions and macros for PDDR_UART */
2831 +#define MCF_GPIO_PDDR_UART_PDDR0 (0x01) /* U1TXD */
2832 +#define MCF_GPIO_PDDR_UART_PDDR1 (0x02) /* U1RXD */
2833 +#define MCF_GPIO_PDDR_UART_PDDR2 (0x04) /* U1RTS */
2834 +#define MCF_GPIO_PDDR_UART_PDDR3 (0x08) /* U0CTS */
2835 +#define MCF_GPIO_PDDR_UART_PDDR4 (0x10) /* U1TXD */
2836 +#define MCF_GPIO_PDDR_UART_PDDR5 (0x20) /* U1RXD */
2837 +#define MCF_GPIO_PDDR_UART_PDDR6 (0x40) /* U1RTS */
2838 +#define MCF_GPIO_PDDR_UART_PDDR7 (0x80) /* U1CTS */
2840 +/* Bit definitions and macros for PDDR_DSPI */
2841 +#define MCF_GPIO_PDDR_DSPI_PDDR0 (0x01) /* DSPI_SOUT / SBF_DO */
2842 +#define MCF_GPIO_PDDR_DSPI_PDDR1 (0x02) /* DSPI_SIN / SBF_DI */
2843 +#define MCF_GPIO_PDDR_DSPI_PDDR2 (0x04) /* DSPI_SCK / SBF_CK */
2844 +#define MCF_GPIO_PDDR_DSPI_PDDR3 (0x08) /* DSPI_PCS0/SS */
2845 +#define MCF_GPIO_PDDR_DSPI_PDDR4 (0x10) /* DSPI_PCS1 / SBF_CS */
2846 +#define MCF_GPIO_PDDR_DSPI_PDDR5 (0x20) /* DSPI_PCS2 */
2847 +#define MCF_GPIO_PDDR_DSPI_PDDR6 (0x40) /* DSPI_PCS5/SS */
2849 +/* Bit definitions and macros for PDDR_TIMER */
2850 +#define MCF_GPIO_PDDR_TIMER_PDDR0 (0x01) /* T0IN / T0OUT / U2RTS */
2851 +#define MCF_GPIO_PDDR_TIMER_PDDR1 (0x02) /* T1IN / T1OUT / U2CTS */
2852 +#define MCF_GPIO_PDDR_TIMER_PDDR2 (0x04) /* T2IN / T2OUT / U2TXD */
2853 +#define MCF_GPIO_PDDR_TIMER_PDDR3 (0x08) /* T3IN / T3OUT / U2RXD */
2855 +/* Bit definitions and macros for PDDR_PCI */
2856 +#define MCF_GPIO_PDDR_PCI_PDDR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */
2857 +#define MCF_GPIO_PDDR_PCI_PDDR1 (0x02) /* PCI_REQ1 */
2858 +#define MCF_GPIO_PDDR_PCI_PDDR2 (0x04) /* PCI_REQ2 */
2859 +#define MCF_GPIO_PDDR_PCI_PDDR3 (0x08) /* PCI_REQ3 / ATA_INTR */
2860 +#define MCF_GPIO_PDDR_PCI_PDDR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */
2861 +#define MCF_GPIO_PDDR_PCI_PDDR5 (0x20) /* PCI_GNT1 / */
2862 +#define MCF_GPIO_PDDR_PCI_PDDR6 (0x40) /* PCI_GNT2 / */
2863 +#define MCF_GPIO_PDDR_PCI_PDDR7 (0x80) /* PCI_GNT3 / ATA_DMACK */
2865 +/* Bit definitions and macros for PDDR_USB */
2866 +#define MCF_GPIO_PDDR_USB_PDDR0 (0x01) /* USB_VBUS_OC / ULPI_STP */
2867 +#define MCF_GPIO_PDDR_USB_PDDR1 (0x02) /* USB_VBUS_EN / USB_PULLUP / ULPI_NXT */
2869 +/* Bit definitions and macros for PDDR_ATAH */
2870 +#define MCF_GPIO_PDDR_ATAH_PDDR0 (0x01) /* ATA_DA0 */
2871 +#define MCF_GPIO_PDDR_ATAH_PDDR1 (0x02) /* ATA_DA1 */
2872 +#define MCF_GPIO_PDDR_ATAH_PDDR2 (0x04) /* ATA_DA2 */
2873 +#define MCF_GPIO_PDDR_ATAH_PDDR3 (0x08) /* ATA_CS0 */
2874 +#define MCF_GPIO_PDDR_ATAH_PDDR4 (0x10) /* ATA_CS1 */
2875 +#define MCF_GPIO_PDDR_ATAH_PDDR5 (0x20) /* ATA_BUFFER_EN */
2877 +/* Bit definitions and macros for PDDR_ATAL */
2878 +#define MCF_GPIO_PDDR_ATAL_PDDR0 (0x01) /* ATA_IORDY */
2879 +#define MCF_GPIO_PDDR_ATAL_PDDR1 (0x02) /* ATA_DMARQ */
2880 +#define MCF_GPIO_PDDR_ATAL_PDDR2 (0x04) /* ATA_RESET */
2882 +/* Bit definitions and macros for PDDR_FEC1H */
2883 +#define MCF_GPIO_PDDR_FEC1H_PDDR0 (0x01) /* FEC1_CRS / ATA_DATA6 */
2884 +#define MCF_GPIO_PDDR_FEC1H_PDDR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */
2885 +#define MCF_GPIO_PDDR_FEC1H_PDDR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */
2886 +#define MCF_GPIO_PDDR_FEC1H_PDDR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */
2887 +#define MCF_GPIO_PDDR_FEC1H_PDDR4 (0x10) /* FEC1_COL / ATA_DATA7 */
2888 +#define MCF_GPIO_PDDR_FEC1H_PDDR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */
2889 +#define MCF_GPIO_PDDR_FEC1H_PDDR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */
2890 +#define MCF_GPIO_PDDR_FEC1H_PDDR7 (0x80) /* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */
2892 +/* Bit definitions and macros for PDDR_FEC1L */
2893 +#define MCF_GPIO_PDDR_FEC1L_PDDR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER / ATA_DATA12 */
2894 +#define MCF_GPIO_PDDR_FEC1L_PDDR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 / ATA_DATA14 */
2895 +#define MCF_GPIO_PDDR_FEC1L_PDDR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */
2896 +#define MCF_GPIO_PDDR_FEC1L_PDDR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */
2897 +#define MCF_GPIO_PDDR_FEC1L_PDDR4 (0x10) /* FEC1_TXER / ATA_DATA0 */
2898 +#define MCF_GPIO_PDDR_FEC1L_PDDR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 / ATA_DATA10 */
2899 +#define MCF_GPIO_PDDR_FEC1L_PDDR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */
2900 +#define MCF_GPIO_PDDR_FEC1L_PDDR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */
2902 +/* Bit definitions and macros for PDDR_FBADH */
2903 +#define MCF_GPIO_PDDR_FBADH_PDDR0 (0x01) /* FB_AD24 */
2904 +#define MCF_GPIO_PDDR_FBADH_PDDR1 (0x02) /* FB_AD25 */
2905 +#define MCF_GPIO_PDDR_FBADH_PDDR2 (0x04) /* FB_AD26 */
2906 +#define MCF_GPIO_PDDR_FBADH_PDDR3 (0x08) /* FB_AD27 */
2907 +#define MCF_GPIO_PDDR_FBADH_PDDR4 (0x10) /* FB_AD28 */
2908 +#define MCF_GPIO_PDDR_FBADH_PDDR5 (0x20) /* FB_AD29 */
2909 +#define MCF_GPIO_PDDR_FBADH_PDDR6 (0x40) /* FB_AD30 */
2910 +#define MCF_GPIO_PDDR_FBADH_PDDR7 (0x80) /* FB_AD31 */
2912 +/* Bit definitions and macros for PDDR_FBADMH */
2913 +#define MCF_GPIO_PDDR_FBADMH_PDDR0 (0x01) /* FB_AD16 */
2914 +#define MCF_GPIO_PDDR_FBADMH_PDDR1 (0x02) /* FB_AD17 */
2915 +#define MCF_GPIO_PDDR_FBADMH_PDDR2 (0x04) /* FB_AD18 */
2916 +#define MCF_GPIO_PDDR_FBADMH_PDDR3 (0x08) /* FB_AD19 */
2917 +#define MCF_GPIO_PDDR_FBADMH_PDDR4 (0x10) /* FB_AD20 */
2918 +#define MCF_GPIO_PDDR_FBADMH_PDDR5 (0x20) /* FB_AD21 */
2919 +#define MCF_GPIO_PDDR_FBADMH_PDDR6 (0x40) /* FB_AD22 */
2920 +#define MCF_GPIO_PDDR_FBADMH_PDDR7 (0x80) /* FB_AD23 */
2922 +/* Bit definitions and macros for PDDR_FBADML */
2923 +#define MCF_GPIO_PDDR_FBADML_PDDR0 (0x01) /* FB_AD8 */
2924 +#define MCF_GPIO_PDDR_FBADML_PDDR1 (0x02) /* FB_AD9 */
2925 +#define MCF_GPIO_PDDR_FBADML_PDDR2 (0x04) /* FB_AD10 */
2926 +#define MCF_GPIO_PDDR_FBADML_PDDR3 (0x08) /* FB_AD11 */
2927 +#define MCF_GPIO_PDDR_FBADML_PDDR4 (0x10) /* FB_AD12 */
2928 +#define MCF_GPIO_PDDR_FBADML_PDDR5 (0x20) /* FB_AD13 */
2929 +#define MCF_GPIO_PDDR_FBADML_PDDR6 (0x40) /* FB_AD14 */
2930 +#define MCF_GPIO_PDDR_FBADML_PDDR7 (0x80) /* FB_AD15 */
2932 +/* Bit definitions and macros for PDDR_FBADL */
2933 +#define MCF_GPIO_PDDR_FBADL_PDDR0 (0x01) /* FB_AD0 */
2934 +#define MCF_GPIO_PDDR_FBADL_PDDR1 (0x02) /* FB_AD1 */
2935 +#define MCF_GPIO_PDDR_FBADL_PDDR2 (0x04) /* FB_AD2 */
2936 +#define MCF_GPIO_PDDR_FBADL_PDDR3 (0x08) /* FB_AD3 */
2937 +#define MCF_GPIO_PDDR_FBADL_PDDR4 (0x10) /* FB_AD4 */
2938 +#define MCF_GPIO_PDDR_FBADL_PDDR5 (0x20) /* FB_AD5 */
2939 +#define MCF_GPIO_PDDR_FBADL_PDDR6 (0x40) /* FB_AD6 */
2940 +#define MCF_GPIO_PDDR_FBADL_PDDR7 (0x80) /* FB_AD7 */
2942 +/* Bit definitions and macros for PPDSDR_FEC0H */
2943 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */
2944 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */
2945 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR2 (0x04) /* FEC0_RXDV / FEC0_RMII_CRS_DV */
2946 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */
2947 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR4 (0x10) /* FEC0_COL / ULPI_DATA7 */
2948 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */
2949 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */
2950 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR7 (0x80) /* FEC0_TXCLK / FEC0_RMII_REF_CLK */
2952 +/* Bit definitions and macros for PPDSDR_FEC0L */
2953 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */
2954 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */
2955 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */
2956 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */
2957 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */
2958 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */
2959 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */
2960 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */
2962 +/* Bit definitions and macros for PPDSDR_SSI */
2963 +#define MCF_GPIO_PPDSDR_SSI_PPDR0 (0x01) /* SSI_TXD / U1TXD */
2964 +#define MCF_GPIO_PPDSDR_SSI_PPDR1 (0x02) /* SSI_RXD / U1RXD */
2965 +#define MCF_GPIO_PPDSDR_SSI_PPDR2 (0x04) /* SSI_FS / U1RTS */
2966 +#define MCF_GPIO_PPDSDR_SSI_PPDR3 (0x08) /* SSI_BCLK / U1CTS */
2967 +#define MCF_GPIO_PPDSDR_SSI_PPDR4 (0x10) /* SSI_MCLK */
2969 +/* Bit definitions and macros for PPDSDR_FBCTL */
2970 +#define MCF_GPIO_PPDSDR_FBCTL_PPDR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */
2971 +#define MCF_GPIO_PPDSDR_FBCTL_PPDR1 (0x02) /* FB_RW */
2972 +#define MCF_GPIO_PPDSDR_FBCTL_PPDR2 (0x04) /* FB_TA */
2973 +#define MCF_GPIO_PPDSDR_FBCTL_PPDR3 (0x08) /* FB_OE */
2975 +/* Bit definitions and macros for PPDSDR_BE */
2976 +#define MCF_GPIO_PPDSDR_BE_PPDR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */
2977 +#define MCF_GPIO_PPDSDR_BE_PPDR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */
2978 +#define MCF_GPIO_PPDSDR_BE_PPDR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */
2979 +#define MCF_GPIO_PPDSDR_BE_PPDR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */
2981 +/* Bit definitions and macros for PPDSDR_CS */
2982 +#define MCF_GPIO_PPDSDR_CS_PPDR1 (0x02) /* FB_CS1 */
2983 +#define MCF_GPIO_PPDSDR_CS_PPDR2 (0x04) /* FB_CS2 */
2984 +#define MCF_GPIO_PPDSDR_CS_PPDR3 (0x08) /* FB_CS3 */
2986 +/* Bit definitions and macros for PPDSDR_DMA */
2987 +#define MCF_GPIO_PPDSDR_DMA_PPDR0 (0x01) /* DREQ0 */
2988 +#define MCF_GPIO_PPDSDR_DMA_PPDR1 (0x02) /* DACK0 / DSPI_PCS3 */
2989 +#define MCF_GPIO_PPDSDR_DMA_PPDR2 (0x04) /* DREQ1 / USB_CLKIN */
2990 +#define MCF_GPIO_PPDSDR_DMA_PPDR3 (0x08) /* DACK1 / ULPI_DIR */
2992 +/* Bit definitions and macros for PPDSDR_FECI2C */
2993 +#define MCF_GPIO_PPDSDR_FECI2C_PPDR0 (0x01) /* I2C_SDA / U2RXD */
2994 +#define MCF_GPIO_PPDSDR_FECI2C_PPDR1 (0x02) /* I2C_SCL / U2TXD */
2995 +#define MCF_GPIO_PPDSDR_FECI2C_PPDR2 (0x04) /* FEC0_MDIO */
2996 +#define MCF_GPIO_PPDSDR_FECI2C_PPDR3 (0x08) /* FEC0_MDC */
2997 +#define MCF_GPIO_PPDSDR_FECI2C_PPDR4 (0x10) /* FEC1_MDIO / ATA_DIOW */
2998 +#define MCF_GPIO_PPDSDR_FECI2C_PPDR5 (0x20) /* FEC1_MDC / ATA_DIOR */
3000 +/* Bit definitions and macros for PPDSDR_UART */
3001 +#define MCF_GPIO_PPDSDR_UART_PPDR0 (0x01) /* U1TXD */
3002 +#define MCF_GPIO_PPDSDR_UART_PPDR1 (0x02) /* U1RXD */
3003 +#define MCF_GPIO_PPDSDR_UART_PPDR2 (0x04) /* U1RTS */
3004 +#define MCF_GPIO_PPDSDR_UART_PPDR3 (0x08) /* U0CTS */
3005 +#define MCF_GPIO_PPDSDR_UART_PPDR4 (0x10) /* U1TXD */
3006 +#define MCF_GPIO_PPDSDR_UART_PPDR5 (0x20) /* U1RXD */
3007 +#define MCF_GPIO_PPDSDR_UART_PPDR6 (0x40) /* U1RTS */
3008 +#define MCF_GPIO_PPDSDR_UART_PPDR7 (0x80) /* U1CTS */
3010 +/* Bit definitions and macros for PPDSDR_DSPI */
3011 +#define MCF_GPIO_PPDSDR_DSPI_PPDR0 (0x01) /* DSPI_SOUT / SBF_DO */
3012 +#define MCF_GPIO_PPDSDR_DSPI_PPDR1 (0x02) /* DSPI_SIN / SBF_DI */
3013 +#define MCF_GPIO_PPDSDR_DSPI_PPDR2 (0x04) /* DSPI_SCK / SBF_CK */
3014 +#define MCF_GPIO_PPDSDR_DSPI_PPDR3 (0x08) /* DSPI_PCS0/SS */
3015 +#define MCF_GPIO_PPDSDR_DSPI_PPDR4 (0x10) /* DSPI_PCS1 / SBF_CS */
3016 +#define MCF_GPIO_PPDSDR_DSPI_PPDR5 (0x20) /* DSPI_PCS2 */
3017 +#define MCF_GPIO_PPDSDR_DSPI_PPDR6 (0x40) /* DSPI_PCS5/SS */
3019 +/* Bit definitions and macros for PPDSDR_TIMER */
3020 +#define MCF_GPIO_PPDSDR_TIMER_PPDR0 (0x01) /* T0IN / T0OUT / U2RTS */
3021 +#define MCF_GPIO_PPDSDR_TIMER_PPDR1 (0x02) /* T1IN / T1OUT / U2CTS */
3022 +#define MCF_GPIO_PPDSDR_TIMER_PPDR2 (0x04) /* T2IN / T2OUT / U2TXD */
3023 +#define MCF_GPIO_PPDSDR_TIMER_PPDR3 (0x08) /* T3IN / T3OUT / U2RXD */
3025 +/* Bit definitions and macros for PPDSDR_PCI */
3026 +#define MCF_GPIO_PPDSDR_PCI_PPDR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */
3027 +#define MCF_GPIO_PPDSDR_PCI_PPDR1 (0x02) /* PCI_REQ1 */
3028 +#define MCF_GPIO_PPDSDR_PCI_PPDR2 (0x04) /* PCI_REQ2 */
3029 +#define MCF_GPIO_PPDSDR_PCI_PPDR3 (0x08) /* PCI_REQ3 / ATA_INTR */
3030 +#define MCF_GPIO_PPDSDR_PCI_PPDR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */
3031 +#define MCF_GPIO_PPDSDR_PCI_PPDR5 (0x20) /* PCI_GNT1 / */
3032 +#define MCF_GPIO_PPDSDR_PCI_PPDR6 (0x40) /* PCI_GNT2 / */
3033 +#define MCF_GPIO_PPDSDR_PCI_PPDR7 (0x80) /* PCI_GNT3 / ATA_DMACK */
3035 +/* Bit definitions and macros for PPDSDR_USB */
3036 +#define MCF_GPIO_PPDSDR_USB_PPDR0 (0x01) /* USB_VBUS_OC / ULPI_STP */
3037 +#define MCF_GPIO_PPDSDR_USB_PPDR1 (0x02) /* USB_VBUS_EN / USB_PULLUP / ULPI_NXT */
3039 +/* Bit definitions and macros for PPDSDR_ATAH */
3040 +#define MCF_GPIO_PPDSDR_ATAH_PPDR0 (0x01) /* ATA_DA0 */
3041 +#define MCF_GPIO_PPDSDR_ATAH_PPDR1 (0x02) /* ATA_DA1 */
3042 +#define MCF_GPIO_PPDSDR_ATAH_PPDR2 (0x04) /* ATA_DA2 */
3043 +#define MCF_GPIO_PPDSDR_ATAH_PPDR3 (0x08) /* ATA_CS0 */
3044 +#define MCF_GPIO_PPDSDR_ATAH_PPDR4 (0x10) /* ATA_CS1 */
3045 +#define MCF_GPIO_PPDSDR_ATAH_PPDR5 (0x20) /* ATA_BUFFER_EN */
3047 +/* Bit definitions and macros for PPDSDR_ATAL */
3048 +#define MCF_GPIO_PPDSDR_ATAL_PPDR0 (0x01) /* ATA_IORDY */
3049 +#define MCF_GPIO_PPDSDR_ATAL_PPDR1 (0x02) /* ATA_DMARQ */
3050 +#define MCF_GPIO_PPDSDR_ATAL_PPDR2 (0x04) /* ATA_RESET */
3052 +/* Bit definitions and macros for PPDSDR_FEC1H */
3053 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR0 (0x01) /* FEC1_CRS / ATA_DATA6 */
3054 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */
3055 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */
3056 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */
3057 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR4 (0x10) /* FEC1_COL / ATA_DATA7 */
3058 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */
3059 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */
3060 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR7 (0x80) /* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */
3062 +/* Bit definitions and macros for PPDSDR_FEC1L */
3063 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER / ATA_DATA12 */
3064 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 / ATA_DATA14 */
3065 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */
3066 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */
3067 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR4 (0x10) /* FEC1_TXER / ATA_DATA0 */
3068 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 / ATA_DATA10 */
3069 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */
3070 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */
3072 +/* Bit definitions and macros for PPDSDR_FBADH */
3073 +#define MCF_GPIO_PPDSDR_FBADH_PPDR0 (0x01) /* FB_AD24 */
3074 +#define MCF_GPIO_PPDSDR_FBADH_PPDR1 (0x02) /* FB_AD25 */
3075 +#define MCF_GPIO_PPDSDR_FBADH_PPDR2 (0x04) /* FB_AD26 */
3076 +#define MCF_GPIO_PPDSDR_FBADH_PPDR3 (0x08) /* FB_AD27 */
3077 +#define MCF_GPIO_PPDSDR_FBADH_PPDR4 (0x10) /* FB_AD28 */
3078 +#define MCF_GPIO_PPDSDR_FBADH_PPDR5 (0x20) /* FB_AD29 */
3079 +#define MCF_GPIO_PPDSDR_FBADH_PPDR6 (0x40) /* FB_AD30 */
3080 +#define MCF_GPIO_PPDSDR_FBADH_PPDR7 (0x80) /* FB_AD31 */
3082 +/* Bit definitions and macros for PPDSDR_FBADMH */
3083 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR0 (0x01) /* FB_AD16 */
3084 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR1 (0x02) /* FB_AD17 */
3085 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR2 (0x04) /* FB_AD18 */
3086 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR3 (0x08) /* FB_AD19 */
3087 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR4 (0x10) /* FB_AD20 */
3088 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR5 (0x20) /* FB_AD21 */
3089 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR6 (0x40) /* FB_AD22 */
3090 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR7 (0x80) /* FB_AD23 */
3092 +/* Bit definitions and macros for PPDSDR_FBADML */
3093 +#define MCF_GPIO_PPDSDR_FBADML_PPDR0 (0x01) /* FB_AD8 */
3094 +#define MCF_GPIO_PPDSDR_FBADML_PPDR1 (0x02) /* FB_AD9 */
3095 +#define MCF_GPIO_PPDSDR_FBADML_PPDR2 (0x04) /* FB_AD10 */
3096 +#define MCF_GPIO_PPDSDR_FBADML_PPDR3 (0x08) /* FB_AD11 */
3097 +#define MCF_GPIO_PPDSDR_FBADML_PPDR4 (0x10) /* FB_AD12 */
3098 +#define MCF_GPIO_PPDSDR_FBADML_PPDR5 (0x20) /* FB_AD13 */
3099 +#define MCF_GPIO_PPDSDR_FBADML_PPDR6 (0x40) /* FB_AD14 */
3100 +#define MCF_GPIO_PPDSDR_FBADML_PPDR7 (0x80) /* FB_AD15 */
3102 +/* Bit definitions and macros for PPDSDR_FBADL */
3103 +#define MCF_GPIO_PPDSDR_FBADL_PPDR0 (0x01) /* FB_AD0 */
3104 +#define MCF_GPIO_PPDSDR_FBADL_PPDR1 (0x02) /* FB_AD1 */
3105 +#define MCF_GPIO_PPDSDR_FBADL_PPDR2 (0x04) /* FB_AD2 */
3106 +#define MCF_GPIO_PPDSDR_FBADL_PPDR3 (0x08) /* FB_AD3 */
3107 +#define MCF_GPIO_PPDSDR_FBADL_PPDR4 (0x10) /* FB_AD4 */
3108 +#define MCF_GPIO_PPDSDR_FBADL_PPDR5 (0x20) /* FB_AD5 */
3109 +#define MCF_GPIO_PPDSDR_FBADL_PPDR6 (0x40) /* FB_AD6 */
3110 +#define MCF_GPIO_PPDSDR_FBADL_PPDR7 (0x80) /* FB_AD7 */
3112 +/* Bit definitions and macros for PCLRR_FEC0H */
3113 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */
3114 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */
3115 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR2 (0x04) /* FEC0_RXDV/FEC0_RMII_CRS_DV */
3116 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */
3117 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR4 (0x10) /* FEC0_COL / ULPI_DATA7 */
3118 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */
3119 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */
3120 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR7 (0x80) /* FEC0_TXCLK / FEC0_RMII_REF_CLK */
3122 +/* Bit definitions and macros for PCLRR_FEC0L */
3123 +#define MCF_GPIO_PCLRR_FEC0L_PPDR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */
3124 +#define MCF_GPIO_PCLRR_FEC0L_PPDR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */
3125 +#define MCF_GPIO_PCLRR_FEC0L_PPDR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */
3126 +#define MCF_GPIO_PCLRR_FEC0L_PPDR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */
3127 +#define MCF_GPIO_PCLRR_FEC0L_PPDR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */
3128 +#define MCF_GPIO_PCLRR_FEC0L_PPDR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */
3129 +#define MCF_GPIO_PCLRR_FEC0L_PPDR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */
3130 +#define MCF_GPIO_PCLRR_FEC0L_PPDR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */
3132 +/* Bit definitions and macros for PCLRR_SSI */
3133 +#define MCF_GPIO_PCLRR_SSI_PCLRR0 (0x01) /* SSI_TXD / U1TXD */
3134 +#define MCF_GPIO_PCLRR_SSI_PCLRR1 (0x02) /* SSI_RXD / U1RXD */
3135 +#define MCF_GPIO_PCLRR_SSI_PCLRR2 (0x04) /* SSI_FS / U1RTS */
3136 +#define MCF_GPIO_PCLRR_SSI_PCLRR3 (0x08) /* SSI_BCLK / U1CTS */
3137 +#define MCF_GPIO_PCLRR_SSI_PCLRR4 (0x10) /* SSI_MCLK */
3139 +/* Bit definitions and macros for PCLRR_FBCTL */
3140 +#define MCF_GPIO_PCLRR_FBCTL_PCLRR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */
3141 +#define MCF_GPIO_PCLRR_FBCTL_PCLRR1 (0x02) /* FB_RW */
3142 +#define MCF_GPIO_PCLRR_FBCTL_PCLRR2 (0x04) /* FB_TA */
3143 +#define MCF_GPIO_PCLRR_FBCTL_PCLRR3 (0x08) /* FB_OE */
3145 +/* Bit definitions and macros for PCLRR_BE */
3146 +#define MCF_GPIO_PCLRR_BE_PCLRR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */
3147 +#define MCF_GPIO_PCLRR_BE_PCLRR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */
3148 +#define MCF_GPIO_PCLRR_BE_PCLRR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */
3149 +#define MCF_GPIO_PCLRR_BE_PCLRR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */
3151 +/* Bit definitions and macros for PCLRR_CS */
3152 +#define MCF_GPIO_PCLRR_CS_PCLRR1 (0x02) /* FB_CS1 */
3153 +#define MCF_GPIO_PCLRR_CS_PCLRR2 (0x04) /* FB_CS2 */
3154 +#define MCF_GPIO_PCLRR_CS_PCLRR3 (0x08) /* FB_CS3 */
3156 +/* Bit definitions and macros for PCLRR_DMA */
3157 +#define MCF_GPIO_PCLRR_DMA_PCLRR0 (0x01) /* DREQ0 */
3158 +#define MCF_GPIO_PCLRR_DMA_PCLRR1 (0x02) /* DACK0 / DSPI_PCS3 */
3159 +#define MCF_GPIO_PCLRR_DMA_PCLRR2 (0x04) /* DREQ1 / USB_CLKIN */
3160 +#define MCF_GPIO_PCLRR_DMA_PCLRR3 (0x08) /* DACK1 / ULPI_DIR */
3162 +/* Bit definitions and macros for PCLRR_FECI2C */
3163 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR0 (0x01) /* I2C_SDA / U2RXD */
3164 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR1 (0x02) /* I2C_SCL / U2TXD */
3165 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR2 (0x04) /* FEC0_MDIO */
3166 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR3 (0x08) /* FEC0_MDC */
3167 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR4 (0x10) /* FEC1_MDIO / ATA_DIOW */
3168 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR5 (0x20) /* FEC1_MDC / ATA_DIOR */
3170 +/* Bit definitions and macros for PCLRR_UART */
3171 +#define MCF_GPIO_PCLRR_UART_PCLRR0 (0x01) /* U1TXD */
3172 +#define MCF_GPIO_PCLRR_UART_PCLRR1 (0x02) /* U1RXD */
3173 +#define MCF_GPIO_PCLRR_UART_PCLRR2 (0x04) /* U1RTS */
3174 +#define MCF_GPIO_PCLRR_UART_PCLRR3 (0x08) /* U0CTS */
3175 +#define MCF_GPIO_PCLRR_UART_PCLRR4 (0x10) /* U1TXD */
3176 +#define MCF_GPIO_PCLRR_UART_PCLRR5 (0x20) /* U1RXD */
3177 +#define MCF_GPIO_PCLRR_UART_PCLRR6 (0x40) /* U1RTS */
3178 +#define MCF_GPIO_PCLRR_UART_PCLRR7 (0x80) /* U1CTS */
3180 +/* Bit definitions and macros for PCLRR_DSPI */
3181 +#define MCF_GPIO_PCLRR_DSPI_PCLRR0 (0x01) /* DSPI_SOUT / SBF_DO */
3182 +#define MCF_GPIO_PCLRR_DSPI_PCLRR1 (0x02) /* DSPI_SIN / SBF_DI */
3183 +#define MCF_GPIO_PCLRR_DSPI_PCLRR2 (0x04) /* DSPI_SCK / SBF_CK */
3184 +#define MCF_GPIO_PCLRR_DSPI_PCLRR3 (0x08) /* DSPI_PCS0/SS */
3185 +#define MCF_GPIO_PCLRR_DSPI_PCLRR4 (0x10) /* DSPI_PCS1 / SBF_CS */
3186 +#define MCF_GPIO_PCLRR_DSPI_PCLRR5 (0x20) /* DSPI_PCS2 */
3187 +#define MCF_GPIO_PCLRR_DSPI_PCLRR6 (0x40) /* DSPI_PCS5/SS */
3189 +/* Bit definitions and macros for PCLRR_TIMER */
3190 +#define MCF_GPIO_PCLRR_TIMER_PCLRR0 (0x01) /* T0IN / T0OUT / U2RTS */
3191 +#define MCF_GPIO_PCLRR_TIMER_PCLRR1 (0x02) /* T1IN / T1OUT / U2CTS */
3192 +#define MCF_GPIO_PCLRR_TIMER_PCLRR2 (0x04) /* T2IN / T2OUT / U2TXD */
3193 +#define MCF_GPIO_PCLRR_TIMER_PCLRR3 (0x08) /* T3IN / T3OUT / U2RXD */
3195 +/* Bit definitions and macros for PCLRR_PCI */
3196 +#define MCF_GPIO_PCLRR_PCI_PCLRR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */
3197 +#define MCF_GPIO_PCLRR_PCI_PCLRR1 (0x02) /* PCI_REQ1 */
3198 +#define MCF_GPIO_PCLRR_PCI_PCLRR2 (0x04) /* PCI_REQ2 */
3199 +#define MCF_GPIO_PCLRR_PCI_PCLRR3 (0x08) /* PCI_REQ3 / ATA_INTR */
3200 +#define MCF_GPIO_PCLRR_PCI_PCLRR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */
3201 +#define MCF_GPIO_PCLRR_PCI_PCLRR5 (0x20) /* PCI_GNT1 / */
3202 +#define MCF_GPIO_PCLRR_PCI_PCLRR6 (0x40) /* PCI_GNT2 / */
3203 +#define MCF_GPIO_PCLRR_PCI_PCLRR7 (0x80) /* PCI_GNT3 / ATA_DMACK */
3205 +/* Bit definitions and macros for PCLRR_USB */
3206 +#define MCF_GPIO_PCLRR_USB_PCLRR0 (0x01) /* USB_VBUS_OC / ULPI_STP */
3207 +#define MCF_GPIO_PCLRR_USB_PCLRR1 (0x02) /* USB_VBUS_EN / USB_PULLUP / ULPI_NXT */
3209 +/* Bit definitions and macros for PCLRR_ATAH */
3210 +#define MCF_GPIO_PCLRR_ATAH_PCLRR0 (0x01) /* ATA_DA0 */
3211 +#define MCF_GPIO_PCLRR_ATAH_PCLRR1 (0x02) /* ATA_DA1 */
3212 +#define MCF_GPIO_PCLRR_ATAH_PCLRR2 (0x04) /* ATA_DA2 */
3213 +#define MCF_GPIO_PCLRR_ATAH_PCLRR3 (0x08) /* ATA_CS0 */
3214 +#define MCF_GPIO_PCLRR_ATAH_PCLRR4 (0x10) /* ATA_CS1 */
3215 +#define MCF_GPIO_PCLRR_ATAH_PCLRR5 (0x20) /* ATA_BUFFER_EN */
3217 +/* Bit definitions and macros for PCLRR_ATAL */
3218 +#define MCF_GPIO_PCLRR_ATAL_PCLRR0 (0x01) /* ATA_IORDY */
3219 +#define MCF_GPIO_PCLRR_ATAL_PCLRR1 (0x02) /* ATA_DMARQ */
3220 +#define MCF_GPIO_PCLRR_ATAL_PCLRR2 (0x04) /* ATA_RESET */
3222 +/* Bit definitions and macros for PCLRR_FEC1H */
3223 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR0 (0x01) /* FEC1_CRS / ATA_DATA6 */
3224 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */
3225 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */
3226 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */
3227 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR4 (0x10) /* FEC1_COL / ATA_DATA7 */
3228 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */
3229 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */
3230 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR7 (0x80) /* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */
3232 +/* Bit definitions and macros for PCLRR_FEC1L */
3233 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER / ATA_DATA12 */
3234 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 / ATA_DATA14 */
3235 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */
3236 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */
3237 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR4 (0x10) /* FEC1_TXER / ATA_DATA0 */
3238 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 / ATA_DATA10 */
3239 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */
3240 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */
3242 +/* Bit definitions and macros for PCLRR_FBADH */
3243 +#define MCF_GPIO_PCLRR_FBADH_PCLRR0 (0x01) /* FB_AD24 */
3244 +#define MCF_GPIO_PCLRR_FBADH_PCLRR1 (0x02) /* FB_AD25 */
3245 +#define MCF_GPIO_PCLRR_FBADH_PCLRR2 (0x04) /* FB_AD26 */
3246 +#define MCF_GPIO_PCLRR_FBADH_PCLRR3 (0x08) /* FB_AD27 */
3247 +#define MCF_GPIO_PCLRR_FBADH_PCLRR4 (0x10) /* FB_AD28 */
3248 +#define MCF_GPIO_PCLRR_FBADH_PCLRR5 (0x20) /* FB_AD29 */
3249 +#define MCF_GPIO_PCLRR_FBADH_PCLRR6 (0x40) /* FB_AD30 */
3250 +#define MCF_GPIO_PCLRR_FBADH_PCLRR7 (0x80) /* FB_AD31 */
3252 +/* Bit definitions and macros for PCLRR_FBADMH */
3253 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR0 (0x01) /* FB_AD16 */
3254 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR1 (0x02) /* FB_AD17 */
3255 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR2 (0x04) /* FB_AD18 */
3256 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR3 (0x08) /* FB_AD19 */
3257 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR4 (0x10) /* FB_AD20 */
3258 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR5 (0x20) /* FB_AD21 */
3259 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR6 (0x40) /* FB_AD22 */
3260 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR7 (0x80) /* FB_AD23 */
3262 +/* Bit definitions and macros for PCLRR_FBADML */
3263 +#define MCF_GPIO_PCLRR_FBADML_PCLRR0 (0x01) /* FB_AD8 */
3264 +#define MCF_GPIO_PCLRR_FBADML_PCLRR1 (0x02) /* FB_AD9 */
3265 +#define MCF_GPIO_PCLRR_FBADML_PCLRR2 (0x04) /* FB_AD10 */
3266 +#define MCF_GPIO_PCLRR_FBADML_PCLRR3 (0x08) /* FB_AD11 */
3267 +#define MCF_GPIO_PCLRR_FBADML_PCLRR4 (0x10) /* FB_AD12 */
3268 +#define MCF_GPIO_PCLRR_FBADML_PCLRR5 (0x20) /* FB_AD13 */
3269 +#define MCF_GPIO_PCLRR_FBADML_PCLRR6 (0x40) /* FB_AD14 */
3270 +#define MCF_GPIO_PCLRR_FBADML_PCLRR7 (0x80) /* FB_AD15 */
3272 +/* Bit definitions and macros for PCLRR_FBADL */
3273 +#define MCF_GPIO_PCLRR_FBADL_PCLRR0 (0x01) /* FB_AD0 */
3274 +#define MCF_GPIO_PCLRR_FBADL_PCLRR1 (0x02) /* FB_AD1 */
3275 +#define MCF_GPIO_PCLRR_FBADL_PCLRR2 (0x04) /* FB_AD2 */
3276 +#define MCF_GPIO_PCLRR_FBADL_PCLRR3 (0x08) /* FB_AD3 */
3277 +#define MCF_GPIO_PCLRR_FBADL_PCLRR4 (0x10) /* FB_AD4 */
3278 +#define MCF_GPIO_PCLRR_FBADL_PCLRR5 (0x20) /* FB_AD5 */
3279 +#define MCF_GPIO_PCLRR_FBADL_PCLRR6 (0x40) /* FB_AD6 */
3280 +#define MCF_GPIO_PCLRR_FBADL_PCLRR7 (0x80) /* FB_AD7 */
3282 +/* Bit definitions and macros for PAR_FEC */
3283 +#define MCF_GPIO_PAR_FEC_FEC0(x) (((x)&0x07))
3284 +#define MCF_GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4)
3285 +#define MCF_GPIO_PAR_FEC_FEC1_MASK (0x8F)
3286 +#define MCF_GPIO_PAR_FEC_FEC1_MII (0x70)
3287 +#define MCF_GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30)
3288 +#define MCF_GPIO_PAR_FEC_FEC1_RMII_ATA (0x20)
3289 +#define MCF_GPIO_PAR_FEC_FEC1_ATA (0x10)
3290 +#define MCF_GPIO_PAR_FEC_FEC1_GPIO (0x00)
3291 +#define MCF_GPIO_PAR_FEC_FEC0_MASK (0xF8)
3292 +#define MCF_GPIO_PAR_FEC_FEC0_MII (0x07)
3293 +#define MCF_GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03)
3294 +#define MCF_GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02)
3295 +#define MCF_GPIO_PAR_FEC_FEC0_ULPI (0x01)
3296 +#define MCF_GPIO_PAR_FEC_FEC0_GPIO (0x00)
3298 +/* Bit definitions and macros for PAR_DMA */
3299 +#define MCF_GPIO_PAR_DMA_DREQ0 (0x01)
3300 +#define MCF_GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2)
3301 +#define MCF_GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4)
3302 +#define MCF_GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6)
3303 +#define MCF_GPIO_PAR_DMA_DACK1_MASK (0x3F)
3304 +#define MCF_GPIO_PAR_DMA_DACK1_DACK1 (0xC0)
3305 +#define MCF_GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40)
3306 +#define MCF_GPIO_PAR_DMA_DACK1_GPIO (0x00)
3307 +#define MCF_GPIO_PAR_DMA_DREQ1_MASK (0xCF)
3308 +#define MCF_GPIO_PAR_DMA_DREQ1_DREQ1 (0x30)
3309 +#define MCF_GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10)
3310 +#define MCF_GPIO_PAR_DMA_DREQ1_GPIO (0x00)
3311 +#define MCF_GPIO_PAR_DMA_DACK0_MASK (0xF3)
3312 +#define MCF_GPIO_PAR_DMA_DACK0_DACK1 (0x0C)
3313 +#define MCF_GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04)
3314 +#define MCF_GPIO_PAR_DMA_DACK0_GPIO (0x00)
3315 +#define MCF_GPIO_PAR_DMA_DREQ0_DREQ0 (0x01)
3316 +#define MCF_GPIO_PAR_DMA_DREQ0_GPIO (0x00)
3318 +/* Bit definitions and macros for PAR_FBCTL */
3319 +#define MCF_GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3)
3320 +#define MCF_GPIO_PAR_FBCTL_RW (0x20)
3321 +#define MCF_GPIO_PAR_FBCTL_TA (0x40)
3322 +#define MCF_GPIO_PAR_FBCTL_OE (0x80)
3323 +#define MCF_GPIO_PAR_FBCTL_OE_OE (0x80)
3324 +#define MCF_GPIO_PAR_FBCTL_OE_GPIO (0x00)
3325 +#define MCF_GPIO_PAR_FBCTL_TA_TA (0x40)
3326 +#define MCF_GPIO_PAR_FBCTL_TA_GPIO (0x00)
3327 +#define MCF_GPIO_PAR_FBCTL_RW_RW (0x20)
3328 +#define MCF_GPIO_PAR_FBCTL_RW_GPIO (0x00)
3329 +#define MCF_GPIO_PAR_FBCTL_TS_MASK (0xE7)
3330 +#define MCF_GPIO_PAR_FBCTL_TS_TS (0x18)
3331 +#define MCF_GPIO_PAR_FBCTL_TS_ALE (0x10)
3332 +#define MCF_GPIO_PAR_FBCTL_TS_TBST (0x08)
3333 +#define MCF_GPIO_PAR_FBCTL_TS_GPIO (0x80)
3335 +/* Bit definitions and macros for PAR_DSPI */
3336 +#define MCF_GPIO_PAR_DSPI_SCK (0x01)
3337 +#define MCF_GPIO_PAR_DSPI_SOUT (0x02)
3338 +#define MCF_GPIO_PAR_DSPI_SIN (0x04)
3339 +#define MCF_GPIO_PAR_DSPI_PCS0 (0x08)
3340 +#define MCF_GPIO_PAR_DSPI_PCS1 (0x10)
3341 +#define MCF_GPIO_PAR_DSPI_PCS2 (0x20)
3342 +#define MCF_GPIO_PAR_DSPI_PCS5 (0x40)
3343 +#define MCF_GPIO_PAR_DSPI_PCS5_PCS5 (0x40)
3344 +#define MCF_GPIO_PAR_DSPI_PCS5_GPIO (0x00)
3345 +#define MCF_GPIO_PAR_DSPI_PCS2_PCS2 (0x20)
3346 +#define MCF_GPIO_PAR_DSPI_PCS2_GPIO (0x00)
3347 +#define MCF_GPIO_PAR_DSPI_PCS1_PCS1 (0x10)
3348 +#define MCF_GPIO_PAR_DSPI_PCS1_GPIO (0x00)
3349 +#define MCF_GPIO_PAR_DSPI_PCS0_PCS0 (0x08)
3350 +#define MCF_GPIO_PAR_DSPI_PCS0_GPIO (0x00)
3351 +#define MCF_GPIO_PAR_DSPI_SIN_SIN (0x04)
3352 +#define MCF_GPIO_PAR_DSPI_SIN_GPIO (0x00)
3353 +#define MCF_GPIO_PAR_DSPI_SOUT_SOUT (0x02)
3354 +#define MCF_GPIO_PAR_DSPI_SOUT_GPIO (0x00)
3355 +#define MCF_GPIO_PAR_DSPI_SCK_SCK (0x01)
3356 +#define MCF_GPIO_PAR_DSPI_SCK_GPIO (0x00)
3358 +/* Bit definitions and macros for PAR_BE */
3359 +#define MCF_GPIO_PAR_BE_BE0 (0x01)
3360 +#define MCF_GPIO_PAR_BE_BE1 (0x04)
3361 +#define MCF_GPIO_PAR_BE_BE2(x) (((x)&0x03)<<4)
3362 +#define MCF_GPIO_PAR_BE_BE3(x) (((x)&0x03)<<6)
3363 +#define MCF_GPIO_PAR_BE_BE3_MASK (0x3F)
3364 +#define MCF_GPIO_PAR_BE_BE3_BE3 (0xC0)
3365 +#define MCF_GPIO_PAR_BE_BE3_TSIZ1 (0x80)
3366 +#define MCF_GPIO_PAR_BE_BE3_GPIO (0x00)
3367 +#define MCF_GPIO_PAR_BE_BE2_MASK (0xCF)
3368 +#define MCF_GPIO_PAR_BE_BE2_BE2 (0x30)
3369 +#define MCF_GPIO_PAR_BE_BE2_TSIZ0 (0x20)
3370 +#define MCF_GPIO_PAR_BE_BE2_GPIO (0x00)
3371 +#define MCF_GPIO_PAR_BE_BE1_BE1 (0x04)
3372 +#define MCF_GPIO_PAR_BE_BE1_GPIO (0x00)
3373 +#define MCF_GPIO_PAR_BE_BE0_BE0 (0x01)
3374 +#define MCF_GPIO_PAR_BE_BE0_GPIO (0x00)
3376 +/* Bit definitions and macros for PAR_CS */
3377 +#define MCF_GPIO_PAR_CS_CS1 (0x02)
3378 +#define MCF_GPIO_PAR_CS_CS2 (0x04)
3379 +#define MCF_GPIO_PAR_CS_CS3 (0x08)
3380 +#define MCF_GPIO_PAR_CS_CS3_CS3 (0x08)
3381 +#define MCF_GPIO_PAR_CS_CS3_GPIO (0x00)
3382 +#define MCF_GPIO_PAR_CS_CS2_CS2 (0x04)
3383 +#define MCF_GPIO_PAR_CS_CS2_GPIO (0x00)
3384 +#define MCF_GPIO_PAR_CS_CS1_CS1 (0x02)
3385 +#define MCF_GPIO_PAR_CS_CS1_GPIO (0x00)
3387 +/* Bit definitions and macros for PAR_TIMER */
3388 +#define MCF_GPIO_PAR_TIMER_T0IN(x) (((x)&0x03))
3389 +#define MCF_GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2)
3390 +#define MCF_GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4)
3391 +#define MCF_GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6)
3392 +#define MCF_GPIO_PAR_TIMER_T3IN_MASK (0x3F)
3393 +#define MCF_GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
3394 +#define MCF_GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
3395 +#define MCF_GPIO_PAR_TIMER_T3IN_U2RXD (0x40)
3396 +#define MCF_GPIO_PAR_TIMER_T3IN_GPIO (0x00)
3397 +#define MCF_GPIO_PAR_TIMER_T2IN_MASK (0xCF)
3398 +#define MCF_GPIO_PAR_TIMER_T2IN_T2IN (0x30)
3399 +#define MCF_GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
3400 +#define MCF_GPIO_PAR_TIMER_T2IN_U2TXD (0x10)
3401 +#define MCF_GPIO_PAR_TIMER_T2IN_GPIO (0x00)
3402 +#define MCF_GPIO_PAR_TIMER_T1IN_MASK (0xF3)
3403 +#define MCF_GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
3404 +#define MCF_GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
3405 +#define MCF_GPIO_PAR_TIMER_T1IN_U2CTS (0x04)
3406 +#define MCF_GPIO_PAR_TIMER_T1IN_GPIO (0x00)
3407 +#define MCF_GPIO_PAR_TIMER_T0IN_MASK (0xFC)
3408 +#define MCF_GPIO_PAR_TIMER_T0IN_T0IN (0x03)
3409 +#define MCF_GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
3410 +#define MCF_GPIO_PAR_TIMER_T0IN_U2RTS (0x01)
3411 +#define MCF_GPIO_PAR_TIMER_T0IN_GPIO (0x00)
3413 +/* Bit definitions and macros for PAR_USB */
3414 +#define MCF_GPIO_PAR_USB_VBUSOC(x) (((x)&0x03))
3415 +#define MCF_GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2)
3416 +#define MCF_GPIO_PAR_USB_VBUSEN_MASK (0xF3)
3417 +#define MCF_GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C)
3418 +#define MCF_GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08)
3419 +#define MCF_GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04)
3420 +#define MCF_GPIO_PAR_USB_VBUSEN_GPIO (0x00)
3421 +#define MCF_GPIO_PAR_USB_VBUSOC_MASK (0xFC)
3422 +#define MCF_GPIO_PAR_USB_VBUSOC_VBUSOC (0x03)
3423 +#define MCF_GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01)
3424 +#define MCF_GPIO_PAR_USB_VBUSOC_GPIO (0x00)
3426 +/* Bit definitions and macros for PAR_UART */
3427 +#define MCF_GPIO_PAR_UART_U0TXD (0x01)
3428 +#define MCF_GPIO_PAR_UART_U0RXD (0x02)
3429 +#define MCF_GPIO_PAR_UART_U0RTS (0x04)
3430 +#define MCF_GPIO_PAR_UART_U0CTS (0x08)
3431 +#define MCF_GPIO_PAR_UART_U1TXD (0x10)
3432 +#define MCF_GPIO_PAR_UART_U1RXD (0x20)
3433 +#define MCF_GPIO_PAR_UART_U1RTS (0x40)
3434 +#define MCF_GPIO_PAR_UART_U1CTS (0x80)
3435 +#define MCF_GPIO_PAR_UART_U1CTS_U1CTS (0x80)
3436 +#define MCF_GPIO_PAR_UART_U1CTS_GPIO (0x00)
3437 +#define MCF_GPIO_PAR_UART_U1RTS_U1RTS (0x40)
3438 +#define MCF_GPIO_PAR_UART_U1RTS_GPIO (0x00)
3439 +#define MCF_GPIO_PAR_UART_U1RXD_U1RXD (0x20)
3440 +#define MCF_GPIO_PAR_UART_U1RXD_GPIO (0x00)
3441 +#define MCF_GPIO_PAR_UART_U1TXD_U1TXD (0x10)
3442 +#define MCF_GPIO_PAR_UART_U1TXD_GPIO (0x00)
3443 +#define MCF_GPIO_PAR_UART_U0CTS_U0CTS (0x08)
3444 +#define MCF_GPIO_PAR_UART_U0CTS_GPIO (0x00)
3445 +#define MCF_GPIO_PAR_UART_U0RTS_U0RTS (0x04)
3446 +#define MCF_GPIO_PAR_UART_U0RTS_GPIO (0x00)
3447 +#define MCF_GPIO_PAR_UART_U0RXD_U0RXD (0x02)
3448 +#define MCF_GPIO_PAR_UART_U0RXD_GPIO (0x00)
3449 +#define MCF_GPIO_PAR_UART_U0TXD_U0TXD (0x01)
3450 +#define MCF_GPIO_PAR_UART_U0TXD_GPIO (0x00)
3452 +/* Bit definitions and macros for PAR_FECI2C */
3453 +#define MCF_GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003))
3454 +#define MCF_GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2)
3455 +#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x0003))
3456 +#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x0003)<<2)
3457 +#define MCF_GPIO_PAR_FECI2C_MDIO0 (0x0010)
3458 +#define MCF_GPIO_PAR_FECI2C_MDC0 (0x0040)
3459 +#define MCF_GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8)
3460 +#define MCF_GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10)
3461 +#define MCF_GPIO_PAR_FECI2C_MDC1_MASK (0xF3FF)
3462 +#define MCF_GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00)
3463 +#define MCF_GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800)
3464 +#define MCF_GPIO_PAR_FECI2C_MDC1_GPIO (0x0000)
3465 +#define MCF_GPIO_PAR_FECI2C_MDIO1_MASK (0xFCFF)
3466 +#define MCF_GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300)
3467 +#define MCF_GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200)
3468 +#define MCF_GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000)
3469 +#define MCF_GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040)
3470 +#define MCF_GPIO_PAR_FECI2C_MDC0_GPIO (0x0000)
3471 +#define MCF_GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010)
3472 +#define MCF_GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000)
3473 +#define MCF_GPIO_PAR_FECI2C_SCL_MASK (0xFFF3)
3474 +#define MCF_GPIO_PAR_FECI2C_SCL_SCL (0x000C)
3475 +#define MCF_GPIO_PAR_FECI2C_SCL_U2TXD (0x0004)
3476 +#define MCF_GPIO_PAR_FECI2C_SCL_GPIO (0x0000)
3477 +#define MCF_GPIO_PAR_FECI2C_SDA_MASK (0xFFFC)
3478 +#define MCF_GPIO_PAR_FECI2C_SDA_SDA (0x0003)
3479 +#define MCF_GPIO_PAR_FECI2C_SDA_U2RXD (0x0001)
3480 +#define MCF_GPIO_PAR_FECI2C_SDA_GPIO (0x0000)
3482 +/* Bit definitions and macros for PAR_SSI */
3483 +#define MCF_GPIO_PAR_SSI_MCLK (0x0001)
3484 +#define MCF_GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2)
3485 +#define MCF_GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4)
3486 +#define MCF_GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6)
3487 +#define MCF_GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8)
3488 +#define MCF_GPIO_PAR_SSI_BCLK_MASK (0xFCFF)
3489 +#define MCF_GPIO_PAR_SSI_BCLK_BCLK (0x0300)
3490 +#define MCF_GPIO_PAR_SSI_BCLK_U1CTS (0x0200)
3491 +#define MCF_GPIO_PAR_SSI_BCLK_GPIO (0x0000)
3492 +#define MCF_GPIO_PAR_SSI_FS_MASK (0xFF3F)
3493 +#define MCF_GPIO_PAR_SSI_FS_FS (0x00C0)
3494 +#define MCF_GPIO_PAR_SSI_FS_U1RTS (0x0080)
3495 +#define MCF_GPIO_PAR_SSI_FS_GPIO (0x0000)
3496 +#define MCF_GPIO_PAR_SSI_SRXD_MASK (0xFFCF)
3497 +#define MCF_GPIO_PAR_SSI_SRXD_SRXD (0x0030)
3498 +#define MCF_GPIO_PAR_SSI_SRXD_U1RXD (0x0020)
3499 +#define MCF_GPIO_PAR_SSI_SRXD_GPIO (0x0000)
3500 +#define MCF_GPIO_PAR_SSI_STXD_MASK (0xFFF3)
3501 +#define MCF_GPIO_PAR_SSI_STXD_STXD (0x000C)
3502 +#define MCF_GPIO_PAR_SSI_STXD_U1TXD (0x0008)
3503 +#define MCF_GPIO_PAR_SSI_STXD_GPIO (0x0000)
3504 +#define MCF_GPIO_PAR_SSI_MCLK_MCLK (0x0001)
3505 +#define MCF_GPIO_PAR_SSI_MCLK_GPIO (0x0000)
3507 +/* Bit definitions and macros for PAR_ATA */
3508 +#define MCF_GPIO_PAR_ATA_IORDY (0x0001)
3509 +#define MCF_GPIO_PAR_ATA_DMARQ (0x0002)
3510 +#define MCF_GPIO_PAR_ATA_RESET (0x0004)
3511 +#define MCF_GPIO_PAR_ATA_DA0 (0x0020)
3512 +#define MCF_GPIO_PAR_ATA_DA1 (0x0040)
3513 +#define MCF_GPIO_PAR_ATA_DA2 (0x0080)
3514 +#define MCF_GPIO_PAR_ATA_CS0 (0x0100)
3515 +#define MCF_GPIO_PAR_ATA_CS1 (0x0200)
3516 +#define MCF_GPIO_PAR_ATA_BUFEN (0x0400)
3517 +#define MCF_GPIO_PAR_ATA_BUFEN_BUFEN (0x0400)
3518 +#define MCF_GPIO_PAR_ATA_BUFEN_GPIO (0x0000)
3519 +#define MCF_GPIO_PAR_ATA_CS1_CS1 (0x0200)
3520 +#define MCF_GPIO_PAR_ATA_CS1_GPIO (0x0000)
3521 +#define MCF_GPIO_PAR_ATA_CS0_CS0 (0x0100)
3522 +#define MCF_GPIO_PAR_ATA_CS0_GPIO (0x0000)
3523 +#define MCF_GPIO_PAR_ATA_DA2_DA2 (0x0080)
3524 +#define MCF_GPIO_PAR_ATA_DA2_GPIO (0x0000)
3525 +#define MCF_GPIO_PAR_ATA_DA1_DA1 (0x0040)
3526 +#define MCF_GPIO_PAR_ATA_DA1_GPIO (0x0000)
3527 +#define MCF_GPIO_PAR_ATA_DA0_DA0 (0x0020)
3528 +#define MCF_GPIO_PAR_ATA_DA0_GPIO (0x0000)
3529 +#define MCF_GPIO_PAR_ATA_RESET_RESET (0x0004)
3530 +#define MCF_GPIO_PAR_ATA_RESET_GPIO (0x0000)
3531 +#define MCF_GPIO_PAR_ATA_DMARQ_DMARQ (0x0002)
3532 +#define MCF_GPIO_PAR_ATA_DMARQ_GPIO (0x0000)
3533 +#define MCF_GPIO_PAR_ATA_IORDY_IORDY (0x0001)
3534 +#define MCF_GPIO_PAR_ATA_IORDY_GPIO (0x0000)
3536 +/* Bit definitions and macros for PAR_IRQ */
3537 +#define MCF_GPIO_PAR_IRQ_IRQ1 (0x02)
3538 +#define MCF_GPIO_PAR_IRQ_IRQ4 (0x10)
3539 +#define MCF_GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10)
3540 +#define MCF_GPIO_PAR_IRQ_IRQ4_GPIO (0x00)
3541 +#define MCF_GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02)
3542 +#define MCF_GPIO_PAR_IRQ_IRQ1_GPIO (0x00)
3544 +/* Bit definitions and macros for PAR_PCI */
3545 +#define MCF_GPIO_PAR_PCI_REQ0 (0x0001)
3546 +#define MCF_GPIO_PAR_PCI_REQ1 (0x0004)
3547 +#define MCF_GPIO_PAR_PCI_REQ2 (0x0010)
3548 +#define MCF_GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6)
3549 +#define MCF_GPIO_PAR_PCI_GNT0 (0x0100)
3550 +#define MCF_GPIO_PAR_PCI_GNT1 (0x0400)
3551 +#define MCF_GPIO_PAR_PCI_GNT2 (0x1000)
3552 +#define MCF_GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14)
3553 +#define MCF_GPIO_PAR_PCI_GNT3_MASK (0x3FFF)
3554 +#define MCF_GPIO_PAR_PCI_GNT3_GNT3 (0xC000)
3555 +#define MCF_GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000)
3556 +#define MCF_GPIO_PAR_PCI_GNT3_GPIO (0x0000)
3557 +#define MCF_GPIO_PAR_PCI_GNT2_GNT2 (0x1000)
3558 +#define MCF_GPIO_PAR_PCI_GNT2_GPIO (0x0000)
3559 +#define MCF_GPIO_PAR_PCI_GNT1_GNT1 (0x0400)
3560 +#define MCF_GPIO_PAR_PCI_GNT1_GPIO (0x0000)
3561 +#define MCF_GPIO_PAR_PCI_GNT0_GNT0 (0x0100)
3562 +#define MCF_GPIO_PAR_PCI_GNT0_GPIO (0x0000)
3563 +#define MCF_GPIO_PAR_PCI_REQ3_MASK (0xFF3F)
3564 +#define MCF_GPIO_PAR_PCI_REQ3_REQ3 (0x00C0)
3565 +#define MCF_GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080)
3566 +#define MCF_GPIO_PAR_PCI_REQ3_GPIO (0x0000)
3567 +#define MCF_GPIO_PAR_PCI_REQ2_REQ2 (0x0010)
3568 +#define MCF_GPIO_PAR_PCI_REQ2_GPIO (0x0000)
3569 +#define MCF_GPIO_PAR_PCI_REQ1_REQ1 (0x0040)
3570 +#define MCF_GPIO_PAR_PCI_REQ1_GPIO (0x0000)
3571 +#define MCF_GPIO_PAR_PCI_REQ0_REQ0 (0x0001)
3572 +#define MCF_GPIO_PAR_PCI_REQ0_GPIO (0x0000)
3574 +/* Bit definitions and macros for MSCR_SDRAM */
3575 +#define MCF_GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03))
3576 +#define MCF_GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2)
3577 +#define MCF_GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4)
3578 +#define MCF_GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6)
3579 +#define MCF_GPIO_MSCR_SDRAM_SDDATA_MASK (0x3F)
3580 +#define MCF_GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0)
3581 +#define MCF_GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80)
3582 +#define MCF_GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40)
3583 +#define MCF_GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00)
3584 +#define MCF_GPIO_MSCR_SDRAM_SDDQS_MASK (0xCF)
3585 +#define MCF_GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30)
3586 +#define MCF_GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20)
3587 +#define MCF_GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10)
3588 +#define MCF_GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00)
3589 +#define MCF_GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3)
3590 +#define MCF_GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C)
3591 +#define MCF_GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08)
3592 +#define MCF_GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04)
3593 +#define MCF_GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00)
3594 +#define MCF_GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC)
3595 +#define MCF_GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03)
3596 +#define MCF_GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02)
3597 +#define MCF_GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01)
3598 +#define MCF_GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00)
3600 +/* Bit definitions and macros for MSCR_PCI */
3601 +#define MCF_GPIO_MSCR_PCI_PCI (0x01)
3602 +#define MCF_GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01)
3603 +#define MCF_GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00)
3605 +/* Bit definitions and macros for DSCR_I2C */
3606 +#define MCF_GPIO_DSCR_I2C_I2C(x) (((x)&0x03))
3607 +#define MCF_GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03)
3608 +#define MCF_GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02)
3609 +#define MCF_GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01)
3610 +#define MCF_GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00)
3612 +/* Bit definitions and macros for DSCR_FLEXBUS */
3613 +#define MCF_GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03))
3614 +#define MCF_GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2)
3615 +#define MCF_GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4)
3616 +#define MCF_GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6)
3617 +#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0)
3618 +#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30P (0x80)
3619 +#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40)
3620 +#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00)
3621 +#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30)
3622 +#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20)
3623 +#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10)
3624 +#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00)
3625 +#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C)
3626 +#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08)
3627 +#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04)
3628 +#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00)
3629 +#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03)
3630 +#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02)
3631 +#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01)
3632 +#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00)
3634 +/* Bit definitions and macros for DSCR_FEC */
3635 +#define MCF_GPIO_DSCR_FEC_FEC0(x) (((x)&0x03))
3636 +#define MCF_GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2)
3637 +#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C)
3638 +#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08)
3639 +#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04)
3640 +#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00)
3641 +#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03)
3642 +#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02)
3643 +#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01)
3644 +#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00)
3646 +/* Bit definitions and macros for DSCR_UART */
3647 +#define MCF_GPIO_DSCR_UART_UART0(x) (((x)&0x03))
3648 +#define MCF_GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2)
3649 +#define MCF_GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C)
3650 +#define MCF_GPIO_DSCR_UART_UART1_LOAD_30PF (0x08)
3651 +#define MCF_GPIO_DSCR_UART_UART1_LOAD_20PF (0x04)
3652 +#define MCF_GPIO_DSCR_UART_UART1_LOAD_10PF (0x00)
3653 +#define MCF_GPIO_DSCR_UART_UART0_LOAD_50PF (0x03)
3654 +#define MCF_GPIO_DSCR_UART_UART0_LOAD_30PF (0x02)
3655 +#define MCF_GPIO_DSCR_UART_UART0_LOAD_20PF (0x01)
3656 +#define MCF_GPIO_DSCR_UART_UART0_LOAD_10PF (0x00)
3658 +/* Bit definitions and macros for DSCR_DSPI */
3659 +#define MCF_GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03))
3660 +#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03)
3661 +#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02)
3662 +#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01)
3663 +#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00)
3665 +/* Bit definitions and macros for DSCR_TIMER */
3666 +#define MCF_GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03))
3667 +#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03)
3668 +#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02)
3669 +#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01)
3670 +#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00)
3672 +/* Bit definitions and macros for DSCR_SSI */
3673 +#define MCF_GPIO_DSCR_SSI_SSI(x) (((x)&0x03))
3674 +#define MCF_GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03)
3675 +#define MCF_GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02)
3676 +#define MCF_GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01)
3677 +#define MCF_GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00)
3679 +/* Bit definitions and macros for DSCR_DMA */
3680 +#define MCF_GPIO_DSCR_DMA_DMA(x) (((x)&0x03))
3681 +#define MCF_GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03)
3682 +#define MCF_GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02)
3683 +#define MCF_GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01)
3684 +#define MCF_GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00)
3686 +/* Bit definitions and macros for DSCR_DEBUG */
3687 +#define MCF_GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03))
3688 +#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03)
3689 +#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02)
3690 +#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01)
3691 +#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00)
3693 +/* Bit definitions and macros for DSCR_RESET */
3694 +#define MCF_GPIO_DSCR_RESET_RESET(x) (((x)&0x03))
3695 +#define MCF_GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03)
3696 +#define MCF_GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02)
3697 +#define MCF_GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01)
3698 +#define MCF_GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00)
3700 +/* Bit definitions and macros for DSCR_IRQ */
3701 +#define MCF_GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03))
3702 +#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03)
3703 +#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02)
3704 +#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01)
3705 +#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00)
3707 +/* Bit definitions and macros for DSCR_USB */
3708 +#define MCF_GPIO_DSCR_USB_USB(x) (((x)&0x03))
3709 +#define MCF_GPIO_DSCR_USB_USB_LOAD_50PF (0x03)
3710 +#define MCF_GPIO_DSCR_USB_USB_LOAD_30PF (0x02)
3711 +#define MCF_GPIO_DSCR_USB_USB_LOAD_20PF (0x01)
3712 +#define MCF_GPIO_DSCR_USB_USB_LOAD_10PF (0x00)
3714 +/* Bit definitions and macros for DSCR_ATA */
3715 +#define MCF_GPIO_DSCR_ATA_ATA(x) (((x)&0x03))
3716 +#define MCF_GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03)
3717 +#define MCF_GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02)
3718 +#define MCF_GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01)
3719 +#define MCF_GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00)
3721 +/********************************************************************/
3723 +#endif /* __MCF5445X_GPIO_H__ */
3725 +++ b/include/asm-m68k/mcf5445x_i2c.h
3728 + * Matt Waddel Matt.Waddel@freescale.com
3730 + * Copyright Freescale Semiconductor, Inc. 2007
3732 + * This program is free software; you can redistribute it and/or modify it
3733 + * under the terms of the GNU General Public License as published by the
3734 + * Free Software Foundation; either version 2 of the License, or (at your
3735 + * option) any later version.
3738 +#ifndef __MCF5445X_I2C_H__
3739 +#define __MCF5445X_I2C_H__
3741 +/*********************************************************************
3745 +*********************************************************************/
3747 +/* Register read/write macros */
3748 +#define MCF_I2C_I2ADR (volatile u8 *)(0xFC058000)
3749 +#define MCF_I2C_I2FDR (volatile u8 *)(0xFC058004)
3750 +#define MCF_I2C_I2CR (volatile u8 *)(0xFC058008)
3751 +#define MCF_I2C_I2SR (volatile u8 *)(0xFC05800C)
3752 +#define MCF_I2C_I2DR (volatile u8 *)(0xFC058010)
3754 +/* Bit definitions and macros for I2AR */
3755 +#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1)
3757 +/* Bit definitions and macros for I2FDR */
3758 +#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F))
3760 +/* Bit definitions and macros for I2DR */
3761 +#define MCF_I2C_I2DR_DATA(x) (x)
3763 +/********************************************************************/
3765 +#endif /* __MCF5445X_I2C_H__ */
3767 +++ b/include/asm-m68k/mcf5445x_intc.h
3770 + * Matt Waddel Matt.Waddel@freescale.com
3772 + * Copyright Freescale Semiconductor, Inc. 2007
3774 + * This program is free software; you can redistribute it and/or modify it
3775 + * under the terms of the GNU General Public License as published by the
3776 + * Free Software Foundation; either version 2 of the License, or (at your
3777 + * option) any later version.
3780 +#ifndef __MCF5445X_INTC_H__
3781 +#define __MCF5445X_INTC_H__
3783 +/*********************************************************************
3785 +* Interrupt Controller (INTC)
3787 +*********************************************************************/
3789 +/* Register read/write macros */
3790 +#define MCF_INTC0_IPRH MCF_REG32(0xFC048000)
3791 +#define MCF_INTC0_IPRL MCF_REG32(0xFC048004)
3792 +#define MCF_INTC0_IMRH MCF_REG32(0xFC048008)
3793 +#define MCF_INTC0_IMRL MCF_REG32(0xFC04800C)
3794 +#define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010)
3795 +#define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014)
3796 +#define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A)
3797 +#define MCF_INTC0_SIMR MCF_REG08(0xFC04801C)
3798 +#define MCF_INTC0_CIMR MCF_REG08(0xFC04801D)
3799 +#define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E)
3800 +#define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F)
3801 +#define MCF_INTC0_ICR1 MCF_REG08(0xFC048041)
3802 +#define MCF_INTC0_ICR2 MCF_REG08(0xFC048042)
3803 +#define MCF_INTC0_ICR3 MCF_REG08(0xFC048043)
3804 +#define MCF_INTC0_ICR4 MCF_REG08(0xFC048044)
3805 +#define MCF_INTC0_ICR5 MCF_REG08(0xFC048045)
3806 +#define MCF_INTC0_ICR6 MCF_REG08(0xFC048046)
3807 +#define MCF_INTC0_ICR7 MCF_REG08(0xFC048047)
3808 +#define MCF_INTC0_ICR8 MCF_REG08(0xFC048048)
3809 +#define MCF_INTC0_ICR9 MCF_REG08(0xFC048049)
3810 +#define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A)
3811 +#define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B)
3812 +#define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C)
3813 +#define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D)
3814 +#define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E)
3815 +#define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F)
3816 +#define MCF_INTC0_ICR16 MCF_REG08(0xFC048050)
3817 +#define MCF_INTC0_ICR17 MCF_REG08(0xFC048051)
3818 +#define MCF_INTC0_ICR18 MCF_REG08(0xFC048052)
3819 +#define MCF_INTC0_ICR19 MCF_REG08(0xFC048053)
3820 +#define MCF_INTC0_ICR20 MCF_REG08(0xFC048054)
3821 +#define MCF_INTC0_ICR21 MCF_REG08(0xFC048055)
3822 +#define MCF_INTC0_ICR22 MCF_REG08(0xFC048056)
3823 +#define MCF_INTC0_ICR23 MCF_REG08(0xFC048057)
3824 +#define MCF_INTC0_ICR24 MCF_REG08(0xFC048058)
3825 +#define MCF_INTC0_ICR25 MCF_REG08(0xFC048059)
3826 +#define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A)
3827 +#define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B)
3828 +#define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C)
3829 +#define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D)
3830 +#define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E)
3831 +#define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F)
3832 +#define MCF_INTC0_ICR32 MCF_REG08(0xFC048060)
3833 +#define MCF_INTC0_ICR33 MCF_REG08(0xFC048061)
3834 +#define MCF_INTC0_ICR34 MCF_REG08(0xFC048062)
3835 +#define MCF_INTC0_ICR35 MCF_REG08(0xFC048063)
3836 +#define MCF_INTC0_ICR36 MCF_REG08(0xFC048064)
3837 +#define MCF_INTC0_ICR37 MCF_REG08(0xFC048065)
3838 +#define MCF_INTC0_ICR38 MCF_REG08(0xFC048066)
3839 +#define MCF_INTC0_ICR39 MCF_REG08(0xFC048067)
3840 +#define MCF_INTC0_ICR40 MCF_REG08(0xFC048068)
3841 +#define MCF_INTC0_ICR41 MCF_REG08(0xFC048069)
3842 +#define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A)
3843 +#define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B)
3844 +#define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C)
3845 +#define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D)
3846 +#define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E)
3847 +#define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F)
3848 +#define MCF_INTC0_ICR48 MCF_REG08(0xFC048070)
3849 +#define MCF_INTC0_ICR49 MCF_REG08(0xFC048071)
3850 +#define MCF_INTC0_ICR50 MCF_REG08(0xFC048072)
3851 +#define MCF_INTC0_ICR51 MCF_REG08(0xFC048073)
3852 +#define MCF_INTC0_ICR52 MCF_REG08(0xFC048074)
3853 +#define MCF_INTC0_ICR53 MCF_REG08(0xFC048075)
3854 +#define MCF_INTC0_ICR54 MCF_REG08(0xFC048076)
3855 +#define MCF_INTC0_ICR55 MCF_REG08(0xFC048077)
3856 +#define MCF_INTC0_ICR56 MCF_REG08(0xFC048078)
3857 +#define MCF_INTC0_ICR57 MCF_REG08(0xFC048079)
3858 +#define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A)
3859 +#define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B)
3860 +#define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C)
3861 +#define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D)
3862 +#define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E)
3863 +#define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F)
3864 +#define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0)
3865 +#define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4)
3866 +#define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8)
3867 +#define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC)
3868 +#define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0)
3869 +#define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4)
3870 +#define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8)
3871 +#define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC)
3872 +#define MCF_INTC1_IPRH MCF_REG32(0xFC04C000)
3873 +#define MCF_INTC1_IPRL MCF_REG32(0xFC04C004)
3874 +#define MCF_INTC1_IMRH MCF_REG32(0xFC04C008)
3875 +#define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C)
3876 +#define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010)
3877 +#define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014)
3878 +#define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A)
3879 +#define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C)
3880 +#define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D)
3881 +#define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E)
3882 +#define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F)
3883 +#define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041)
3884 +#define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042)
3885 +#define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043)
3886 +#define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044)
3887 +#define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045)
3888 +#define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046)
3889 +#define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047)
3890 +#define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048)
3891 +#define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049)
3892 +#define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A)
3893 +#define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B)
3894 +#define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C)
3895 +#define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D)
3896 +#define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E)
3897 +#define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F)
3898 +#define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050)
3899 +#define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051)
3900 +#define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052)
3901 +#define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053)
3902 +#define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054)
3903 +#define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055)
3904 +#define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056)
3905 +#define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057)
3906 +#define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058)
3907 +#define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059)
3908 +#define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A)
3909 +#define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B)
3910 +#define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C)
3911 +#define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D)
3912 +#define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E)
3913 +#define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F)
3914 +#define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060)
3915 +#define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061)
3916 +#define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062)
3917 +#define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063)
3918 +#define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064)
3919 +#define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065)
3920 +#define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066)
3921 +#define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067)
3922 +#define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068)
3923 +#define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069)
3924 +#define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A)
3925 +#define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B)
3926 +#define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C)
3927 +#define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D)
3928 +#define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E)
3929 +#define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F)
3930 +#define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070)
3931 +#define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071)
3932 +#define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072)
3933 +#define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073)
3934 +#define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074)
3935 +#define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075)
3936 +#define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076)
3937 +#define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077)
3938 +#define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078)
3939 +#define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079)
3940 +#define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A)
3941 +#define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B)
3942 +#define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C)
3943 +#define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D)
3944 +#define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E)
3945 +#define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F)
3946 +#define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0)
3947 +#define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4)
3948 +#define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8)
3949 +#define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC)
3950 +#define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0)
3951 +#define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4)
3952 +#define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8
3953 +#define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC)
3955 +/* Parameterized register read/write macros for multiple registers */
3956 +#define MCF_INTC0_ICR(x) MCF_REG08(0xFC048041+((x-1)*0x001))
3957 +#define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x-1)*0x004))
3958 +#define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C041+((x-1)*0x001))
3959 +#define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x-1)*0x004))
3961 +/* Parameterized register read/write macros for multiple modules */
3962 +#define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000))
3963 +#define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000))
3964 +#define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000))
3965 +#define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000))
3966 +#define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000))
3967 +#define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000))
3968 +#define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000))
3969 +#define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000))
3970 +#define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000))
3971 +#define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000))
3972 +#define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000))
3973 +#define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000))
3974 +#define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000))
3975 +#define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000))
3976 +#define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000))
3977 +#define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000))
3978 +#define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000))
3979 +#define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000))
3980 +#define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000))
3981 +#define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000))
3982 +#define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000))
3983 +#define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000))
3984 +#define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000))
3985 +#define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000))
3986 +#define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000))
3987 +#define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000))
3988 +#define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000))
3989 +#define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000))
3990 +#define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000))
3991 +#define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000))
3992 +#define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000))
3993 +#define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000))
3994 +#define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000))
3995 +#define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000))
3996 +#define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000))
3997 +#define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000))
3998 +#define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000))
3999 +#define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000))
4000 +#define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000))
4001 +#define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000))
4002 +#define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000))
4003 +#define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000))
4004 +#define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000))
4005 +#define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000))
4006 +#define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000))
4007 +#define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000))
4008 +#define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000))
4009 +#define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000))
4010 +#define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000))
4011 +#define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000))
4012 +#define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000))
4013 +#define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000))
4014 +#define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000))
4015 +#define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000))
4016 +#define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000))
4017 +#define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000))
4018 +#define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000))
4019 +#define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000))
4020 +#define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000))
4021 +#define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000))
4022 +#define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000))
4023 +#define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000))
4024 +#define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000))
4025 +#define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000))
4026 +#define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000))
4027 +#define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000))
4028 +#define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000))
4029 +#define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000))
4030 +#define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000))
4031 +#define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000))
4032 +#define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000))
4033 +#define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000))
4034 +#define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000))
4035 +#define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000))
4036 +#define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000))
4037 +#define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000))
4038 +#define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000))
4039 +#define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000))
4040 +#define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000))
4041 +#define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000))
4042 +#define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000))
4043 +#define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000))
4045 +/* Bit definitions and macros for IPRH */
4046 +#define MCF_INTC_IPRH_INT32 (0x00000001)
4047 +#define MCF_INTC_IPRH_INT33 (0x00000002)
4048 +#define MCF_INTC_IPRH_INT34 (0x00000004)
4049 +#define MCF_INTC_IPRH_INT35 (0x00000008)
4050 +#define MCF_INTC_IPRH_INT36 (0x00000010)
4051 +#define MCF_INTC_IPRH_INT37 (0x00000020)
4052 +#define MCF_INTC_IPRH_INT38 (0x00000040)
4053 +#define MCF_INTC_IPRH_INT39 (0x00000080)
4054 +#define MCF_INTC_IPRH_INT40 (0x00000100)
4055 +#define MCF_INTC_IPRH_INT41 (0x00000200)
4056 +#define MCF_INTC_IPRH_INT42 (0x00000400)
4057 +#define MCF_INTC_IPRH_INT43 (0x00000800)
4058 +#define MCF_INTC_IPRH_INT44 (0x00001000)
4059 +#define MCF_INTC_IPRH_INT45 (0x00002000)
4060 +#define MCF_INTC_IPRH_INT46 (0x00004000)
4061 +#define MCF_INTC_IPRH_INT47 (0x00008000)
4062 +#define MCF_INTC_IPRH_INT48 (0x00010000)
4063 +#define MCF_INTC_IPRH_INT49 (0x00020000)
4064 +#define MCF_INTC_IPRH_INT50 (0x00040000)
4065 +#define MCF_INTC_IPRH_INT51 (0x00080000)
4066 +#define MCF_INTC_IPRH_INT52 (0x00100000)
4067 +#define MCF_INTC_IPRH_INT53 (0x00200000)
4068 +#define MCF_INTC_IPRH_INT54 (0x00400000)
4069 +#define MCF_INTC_IPRH_INT55 (0x00800000)
4070 +#define MCF_INTC_IPRH_INT56 (0x01000000)
4071 +#define MCF_INTC_IPRH_INT57 (0x02000000)
4072 +#define MCF_INTC_IPRH_INT58 (0x04000000)
4073 +#define MCF_INTC_IPRH_INT59 (0x08000000)
4074 +#define MCF_INTC_IPRH_INT60 (0x10000000)
4075 +#define MCF_INTC_IPRH_INT61 (0x20000000)
4076 +#define MCF_INTC_IPRH_INT62 (0x40000000)
4077 +#define MCF_INTC_IPRH_INT63 (0x80000000)
4079 +/* Bit definitions and macros for IPRL */
4080 +#define MCF_INTC_IPRL_INT0 (0x00000001)
4081 +#define MCF_INTC_IPRL_INT1 (0x00000002)
4082 +#define MCF_INTC_IPRL_INT2 (0x00000004)
4083 +#define MCF_INTC_IPRL_INT3 (0x00000008)
4084 +#define MCF_INTC_IPRL_INT4 (0x00000010)
4085 +#define MCF_INTC_IPRL_INT5 (0x00000020)
4086 +#define MCF_INTC_IPRL_INT6 (0x00000040)
4087 +#define MCF_INTC_IPRL_INT7 (0x00000080)
4088 +#define MCF_INTC_IPRL_INT8 (0x00000100)
4089 +#define MCF_INTC_IPRL_INT9 (0x00000200)
4090 +#define MCF_INTC_IPRL_INT10 (0x00000400)
4091 +#define MCF_INTC_IPRL_INT11 (0x00000800)
4092 +#define MCF_INTC_IPRL_INT12 (0x00001000)
4093 +#define MCF_INTC_IPRL_INT13 (0x00002000)
4094 +#define MCF_INTC_IPRL_INT14 (0x00004000)
4095 +#define MCF_INTC_IPRL_INT15 (0x00008000)
4096 +#define MCF_INTC_IPRL_INT16 (0x00010000)
4097 +#define MCF_INTC_IPRL_INT17 (0x00020000)
4098 +#define MCF_INTC_IPRL_INT18 (0x00040000)
4099 +#define MCF_INTC_IPRL_INT19 (0x00080000)
4100 +#define MCF_INTC_IPRL_INT20 (0x00100000)
4101 +#define MCF_INTC_IPRL_INT21 (0x00200000)
4102 +#define MCF_INTC_IPRL_INT22 (0x00400000)
4103 +#define MCF_INTC_IPRL_INT23 (0x00800000)
4104 +#define MCF_INTC_IPRL_INT24 (0x01000000)
4105 +#define MCF_INTC_IPRL_INT25 (0x02000000)
4106 +#define MCF_INTC_IPRL_INT26 (0x04000000)
4107 +#define MCF_INTC_IPRL_INT27 (0x08000000)
4108 +#define MCF_INTC_IPRL_INT28 (0x10000000)
4109 +#define MCF_INTC_IPRL_INT29 (0x20000000)
4110 +#define MCF_INTC_IPRL_INT30 (0x40000000)
4111 +#define MCF_INTC_IPRL_INT31 (0x80000000)
4113 +/* Bit definitions and macros for IMRH */
4114 +#define MCF_INTC_IMRH_INT_MASK32 (0x00000001)
4115 +#define MCF_INTC_IMRH_INT_MASK33 (0x00000002)
4116 +#define MCF_INTC_IMRH_INT_MASK34 (0x00000004)
4117 +#define MCF_INTC_IMRH_INT_MASK35 (0x00000008)
4118 +#define MCF_INTC_IMRH_INT_MASK36 (0x00000010)
4119 +#define MCF_INTC_IMRH_INT_MASK37 (0x00000020)
4120 +#define MCF_INTC_IMRH_INT_MASK38 (0x00000040)
4121 +#define MCF_INTC_IMRH_INT_MASK39 (0x00000080)
4122 +#define MCF_INTC_IMRH_INT_MASK40 (0x00000100)
4123 +#define MCF_INTC_IMRH_INT_MASK41 (0x00000200)
4124 +#define MCF_INTC_IMRH_INT_MASK42 (0x00000400)
4125 +#define MCF_INTC_IMRH_INT_MASK43 (0x00000800)
4126 +#define MCF_INTC_IMRH_INT_MASK44 (0x00001000)
4127 +#define MCF_INTC_IMRH_INT_MASK45 (0x00002000)
4128 +#define MCF_INTC_IMRH_INT_MASK46 (0x00004000)
4129 +#define MCF_INTC_IMRH_INT_MASK47 (0x00008000)
4130 +#define MCF_INTC_IMRH_INT_MASK48 (0x00010000)
4131 +#define MCF_INTC_IMRH_INT_MASK49 (0x00020000)
4132 +#define MCF_INTC_IMRH_INT_MASK50 (0x00040000)
4133 +#define MCF_INTC_IMRH_INT_MASK51 (0x00080000)
4134 +#define MCF_INTC_IMRH_INT_MASK52 (0x00100000)
4135 +#define MCF_INTC_IMRH_INT_MASK53 (0x00200000)
4136 +#define MCF_INTC_IMRH_INT_MASK54 (0x00400000)
4137 +#define MCF_INTC_IMRH_INT_MASK55 (0x00800000)
4138 +#define MCF_INTC_IMRH_INT_MASK56 (0x01000000)
4139 +#define MCF_INTC_IMRH_INT_MASK57 (0x02000000)
4140 +#define MCF_INTC_IMRH_INT_MASK58 (0x04000000)
4141 +#define MCF_INTC_IMRH_INT_MASK59 (0x08000000)
4142 +#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
4143 +#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
4144 +#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
4145 +#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
4147 +/* Bit definitions and macros for IMRL */
4148 +#define MCF_INTC_IMRL_INT_MASK0 (0x00000001)
4149 +#define MCF_INTC_IMRL_INT_MASK1 (0x00000002)
4150 +#define MCF_INTC_IMRL_INT_MASK2 (0x00000004)
4151 +#define MCF_INTC_IMRL_INT_MASK3 (0x00000008)
4152 +#define MCF_INTC_IMRL_INT_MASK4 (0x00000010)
4153 +#define MCF_INTC_IMRL_INT_MASK5 (0x00000020)
4154 +#define MCF_INTC_IMRL_INT_MASK6 (0x00000040)
4155 +#define MCF_INTC_IMRL_INT_MASK7 (0x00000080)
4156 +#define MCF_INTC_IMRL_INT_MASK8 (0x00000100)
4157 +#define MCF_INTC_IMRL_INT_MASK9 (0x00000200)
4158 +#define MCF_INTC_IMRL_INT_MASK10 (0x00000400)
4159 +#define MCF_INTC_IMRL_INT_MASK11 (0x00000800)
4160 +#define MCF_INTC_IMRL_INT_MASK12 (0x00001000)
4161 +#define MCF_INTC_IMRL_INT_MASK13 (0x00002000)
4162 +#define MCF_INTC_IMRL_INT_MASK14 (0x00004000)
4163 +#define MCF_INTC_IMRL_INT_MASK15 (0x00008000)
4164 +#define MCF_INTC_IMRL_INT_MASK16 (0x00010000)
4165 +#define MCF_INTC_IMRL_INT_MASK17 (0x00020000)
4166 +#define MCF_INTC_IMRL_INT_MASK18 (0x00040000)
4167 +#define MCF_INTC_IMRL_INT_MASK19 (0x00080000)
4168 +#define MCF_INTC_IMRL_INT_MASK20 (0x00100000)
4169 +#define MCF_INTC_IMRL_INT_MASK21 (0x00200000)
4170 +#define MCF_INTC_IMRL_INT_MASK22 (0x00400000)
4171 +#define MCF_INTC_IMRL_INT_MASK23 (0x00800000)
4172 +#define MCF_INTC_IMRL_INT_MASK24 (0x01000000)
4173 +#define MCF_INTC_IMRL_INT_MASK25 (0x02000000)
4174 +#define MCF_INTC_IMRL_INT_MASK26 (0x04000000)
4175 +#define MCF_INTC_IMRL_INT_MASK27 (0x08000000)
4176 +#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
4177 +#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
4178 +#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
4179 +#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
4181 +/* Bit definitions and macros for INTFRCH */
4182 +#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001)
4183 +#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002)
4184 +#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004)
4185 +#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008)
4186 +#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010)
4187 +#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020)
4188 +#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040)
4189 +#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080)
4190 +#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100)
4191 +#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200)
4192 +#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400)
4193 +#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800)
4194 +#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000)
4195 +#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000)
4196 +#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000)
4197 +#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000)
4198 +#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000)
4199 +#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000)
4200 +#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000)
4201 +#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000)
4202 +#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000)
4203 +#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000)
4204 +#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000)
4205 +#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000)
4206 +#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000)
4207 +#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000)
4208 +#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000)
4209 +#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000)
4210 +#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
4211 +#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
4212 +#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
4213 +#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
4215 +/* Bit definitions and macros for INTFRCL */
4216 +#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001)
4217 +#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002)
4218 +#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004)
4219 +#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008)
4220 +#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010)
4221 +#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020)
4222 +#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040)
4223 +#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080)
4224 +#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100)
4225 +#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200)
4226 +#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400)
4227 +#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800)
4228 +#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000)
4229 +#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000)
4230 +#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000)
4231 +#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000)
4232 +#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000)
4233 +#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000)
4234 +#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000)
4235 +#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000)
4236 +#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000)
4237 +#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000)
4238 +#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000)
4239 +#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000)
4240 +#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000)
4241 +#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000)
4242 +#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000)
4243 +#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000)
4244 +#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
4245 +#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
4246 +#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
4247 +#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
4249 +/* Bit definitions and macros for ICONFIG */
4250 +#define MCF_INTC_ICONFIG_EMASK (0x0020)
4251 +#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200)
4252 +#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400)
4253 +#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800)
4254 +#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000)
4255 +#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000)
4256 +#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000)
4257 +#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000)
4259 +/* Bit definitions and macros for SIMR */
4260 +#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F))
4262 +/* Bit definitions and macros for CIMR */
4263 +#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F))
4265 +/* Bit definitions and macros for CLMASK */
4266 +#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F))
4268 +/* Bit definitions and macros for SLMASK */
4269 +#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F))
4271 +/* Bit definitions and macros for ICR group */
4272 +#define MCF_INTC_ICR_IL(x) (((x)&0x07))
4274 +/* Bit definitions and macros for ICR1 */
4275 +#define MCF_INTC_ICR1_IL(x) (((x)&0x07))
4277 +/* Bit definitions and macros for ICR2 */
4278 +#define MCF_INTC_ICR2_IL(x) (((x)&0x07))
4280 +/* Bit definitions and macros for ICR3 */
4281 +#define MCF_INTC_ICR3_IL(x) (((x)&0x07))
4283 +/* Bit definitions and macros for ICR4 */
4284 +#define MCF_INTC_ICR4_IL(x) (((x)&0x07))
4286 +/* Bit definitions and macros for ICR5 */
4287 +#define MCF_INTC_ICR5_IL(x) (((x)&0x07))
4289 +/* Bit definitions and macros for ICR6 */
4290 +#define MCF_INTC_ICR6_IL(x) (((x)&0x07))
4292 +/* Bit definitions and macros for ICR7 */
4293 +#define MCF_INTC_ICR7_IL(x) (((x)&0x07))
4295 +/* Bit definitions and macros for ICR8 */
4296 +#define MCF_INTC_ICR8_IL(x) (((x)&0x07))
4298 +/* Bit definitions and macros for ICR9 */
4299 +#define MCF_INTC_ICR9_IL(x) (((x)&0x07))
4301 +/* Bit definitions and macros for ICR10 */
4302 +#define MCF_INTC_ICR10_IL(x) (((x)&0x07))
4304 +/* Bit definitions and macros for ICR11 */
4305 +#define MCF_INTC_ICR11_IL(x) (((x)&0x07))
4307 +/* Bit definitions and macros for ICR12 */
4308 +#define MCF_INTC_ICR12_IL(x) (((x)&0x07))
4310 +/* Bit definitions and macros for ICR13 */
4311 +#define MCF_INTC_ICR13_IL(x) (((x)&0x07))
4313 +/* Bit definitions and macros for ICR14 */
4314 +#define MCF_INTC_ICR14_IL(x) (((x)&0x07))
4316 +/* Bit definitions and macros for ICR15 */
4317 +#define MCF_INTC_ICR15_IL(x) (((x)&0x07))
4319 +/* Bit definitions and macros for ICR16 */
4320 +#define MCF_INTC_ICR16_IL(x) (((x)&0x07))
4322 +/* Bit definitions and macros for ICR17 */
4323 +#define MCF_INTC_ICR17_IL(x) (((x)&0x07))
4325 +/* Bit definitions and macros for ICR18 */
4326 +#define MCF_INTC_ICR18_IL(x) (((x)&0x07))
4328 +/* Bit definitions and macros for ICR19 */
4329 +#define MCF_INTC_ICR19_IL(x) (((x)&0x07))
4331 +/* Bit definitions and macros for ICR20 */
4332 +#define MCF_INTC_ICR20_IL(x) (((x)&0x07))
4334 +/* Bit definitions and macros for ICR21 */
4335 +#define MCF_INTC_ICR21_IL(x) (((x)&0x07))
4337 +/* Bit definitions and macros for ICR22 */
4338 +#define MCF_INTC_ICR22_IL(x) (((x)&0x07))
4340 +/* Bit definitions and macros for ICR23 */
4341 +#define MCF_INTC_ICR23_IL(x) (((x)&0x07))
4343 +/* Bit definitions and macros for ICR24 */
4344 +#define MCF_INTC_ICR24_IL(x) (((x)&0x07))
4346 +/* Bit definitions and macros for ICR25 */
4347 +#define MCF_INTC_ICR25_IL(x) (((x)&0x07))
4349 +/* Bit definitions and macros for ICR26 */
4350 +#define MCF_INTC_ICR26_IL(x) (((x)&0x07))
4352 +/* Bit definitions and macros for ICR27 */
4353 +#define MCF_INTC_ICR27_IL(x) (((x)&0x07))
4355 +/* Bit definitions and macros for ICR28 */
4356 +#define MCF_INTC_ICR28_IL(x) (((x)&0x07))
4358 +/* Bit definitions and macros for ICR29 */
4359 +#define MCF_INTC_ICR29_IL(x) (((x)&0x07))
4361 +/* Bit definitions and macros for ICR30 */
4362 +#define MCF_INTC_ICR30_IL(x) (((x)&0x07))
4364 +/* Bit definitions and macros for ICR31 */
4365 +#define MCF_INTC_ICR31_IL(x) (((x)&0x07))
4367 +/* Bit definitions and macros for ICR32 */
4368 +#define MCF_INTC_ICR32_IL(x) (((x)&0x07))
4370 +/* Bit definitions and macros for ICR33 */
4371 +#define MCF_INTC_ICR33_IL(x) (((x)&0x07))
4373 +/* Bit definitions and macros for ICR34 */
4374 +#define MCF_INTC_ICR34_IL(x) (((x)&0x07))
4376 +/* Bit definitions and macros for ICR35 */
4377 +#define MCF_INTC_ICR35_IL(x) (((x)&0x07))
4379 +/* Bit definitions and macros for ICR36 */
4380 +#define MCF_INTC_ICR36_IL(x) (((x)&0x07))
4382 +/* Bit definitions and macros for ICR37 */
4383 +#define MCF_INTC_ICR37_IL(x) (((x)&0x07))
4385 +/* Bit definitions and macros for ICR38 */
4386 +#define MCF_INTC_ICR38_IL(x) (((x)&0x07))
4388 +/* Bit definitions and macros for ICR39 */
4389 +#define MCF_INTC_ICR39_IL(x) (((x)&0x07))
4391 +/* Bit definitions and macros for ICR40 */
4392 +#define MCF_INTC_ICR40_IL(x) (((x)&0x07))
4394 +/* Bit definitions and macros for ICR41 */
4395 +#define MCF_INTC_ICR41_IL(x) (((x)&0x07))
4397 +/* Bit definitions and macros for ICR42 */
4398 +#define MCF_INTC_ICR42_IL(x) (((x)&0x07))
4400 +/* Bit definitions and macros for ICR43 */
4401 +#define MCF_INTC_ICR43_IL(x) (((x)&0x07))
4403 +/* Bit definitions and macros for ICR44 */
4404 +#define MCF_INTC_ICR44_IL(x) (((x)&0x07))
4406 +/* Bit definitions and macros for ICR45 */
4407 +#define MCF_INTC_ICR45_IL(x) (((x)&0x07))
4409 +/* Bit definitions and macros for ICR46 */
4410 +#define MCF_INTC_ICR46_IL(x) (((x)&0x07))
4412 +/* Bit definitions and macros for ICR47 */
4413 +#define MCF_INTC_ICR47_IL(x) (((x)&0x07))
4415 +/* Bit definitions and macros for ICR48 */
4416 +#define MCF_INTC_ICR48_IL(x) (((x)&0x07))
4418 +/* Bit definitions and macros for ICR49 */
4419 +#define MCF_INTC_ICR49_IL(x) (((x)&0x07))
4421 +/* Bit definitions and macros for ICR50 */
4422 +#define MCF_INTC_ICR50_IL(x) (((x)&0x07))
4424 +/* Bit definitions and macros for ICR51 */
4425 +#define MCF_INTC_ICR51_IL(x) (((x)&0x07))
4427 +/* Bit definitions and macros for ICR52 */
4428 +#define MCF_INTC_ICR52_IL(x) (((x)&0x07))
4430 +/* Bit definitions and macros for ICR53 */
4431 +#define MCF_INTC_ICR53_IL(x) (((x)&0x07))
4433 +/* Bit definitions and macros for ICR54 */
4434 +#define MCF_INTC_ICR54_IL(x) (((x)&0x07))
4436 +/* Bit definitions and macros for ICR55 */
4437 +#define MCF_INTC_ICR55_IL(x) (((x)&0x07))
4439 +/* Bit definitions and macros for ICR56 */
4440 +#define MCF_INTC_ICR56_IL(x) (((x)&0x07))
4442 +/* Bit definitions and macros for ICR57 */
4443 +#define MCF_INTC_ICR57_IL(x) (((x)&0x07))
4445 +/* Bit definitions and macros for ICR58 */
4446 +#define MCF_INTC_ICR58_IL(x) (((x)&0x07))
4448 +/* Bit definitions and macros for ICR59 */
4449 +#define MCF_INTC_ICR59_IL(x) (((x)&0x07))
4451 +/* Bit definitions and macros for ICR60 */
4452 +#define MCF_INTC_ICR60_IL(x) (((x)&0x07))
4454 +/* Bit definitions and macros for ICR61 */
4455 +#define MCF_INTC_ICR61_IL(x) (((x)&0x07))
4457 +/* Bit definitions and macros for ICR62 */
4458 +#define MCF_INTC_ICR62_IL(x) (((x)&0x07))
4460 +/* Bit definitions and macros for ICR63 */
4461 +#define MCF_INTC_ICR63_IL(x) (((x)&0x07))
4463 +/* Bit definitions and macros for SWIACK */
4464 +#define MCF_INTC_SWIACK_VECTOR(x) (x)
4466 +/* Bit definitions and macros for LIACK group */
4467 +#define MCF_INTC_LIACK_VECTOR(x) (x)
4469 +/* Bit definitions and macros for L1IACK */
4470 +#define MCF_INTC_L1IACK_VECTOR(x) (x)
4472 +/* Bit definitions and macros for L2IACK */
4473 +#define MCF_INTC_L2IACK_VECTOR(x) (x)
4475 +/* Bit definitions and macros for L3IACK */
4476 +#define MCF_INTC_L3IACK_VECTOR(x) (x)
4478 +/* Bit definitions and macros for L4IACK */
4479 +#define MCF_INTC_L4IACK_VECTOR(x) (x)
4481 +/* Bit definitions and macros for L5IACK */
4482 +#define MCF_INTC_L5IACK_VECTOR(x) (x)
4484 +/* Bit definitions and macros for L6IACK */
4485 +#define MCF_INTC_L6IACK_VECTOR(x) (x)
4487 +/* Bit definitions and macros for L7IACK */
4488 +#define MCF_INTC_L7IACK_VECTOR(x) (x)
4490 +/********************************************************************/
4492 +#endif /* __MCF5445X_INTC_H__ */
4494 +++ b/include/asm-m68k/mcf5445x_pci.h
4497 + * Kurt Mahan kmahan@freescale.com
4499 + * Copyright Freescale Semiconductor, Inc. 2007
4501 + * This program is free software; you can redistribute it and/or modify it
4502 + * under the terms of the GNU General Public License as published by the
4503 + * Free Software Foundation; either version 2 of the License, or (at your
4504 + * option) any later version.
4507 +#ifndef __MCF5445X_PCI_H__
4508 +#define __MCF5445X_PCI_H__
4510 +/*********************************************************************
4512 +* PCI Bus Controller (PCI)
4514 +*********************************************************************/
4516 +/* Register read/write macros */
4517 +#define MCF_PCI_PCIIDR MCF_REG32(0xFC0A8000)
4518 +#define MCF_PCI_PCISCR MCF_REG32(0xFC0A8004)
4519 +#define MCF_PCI_PCICCRIR MCF_REG32(0xFC0A8008)
4520 +#define MCF_PCI_PCICR1 MCF_REG32(0xFC0A800C)
4521 +#define MCF_PCI_PCIBAR0 MCF_REG32(0xFC0A8010)
4522 +#define MCF_PCI_PCIBAR1 MCF_REG32(0xFC0A8014)
4523 +#define MCF_PCI_PCIBAR2 MCF_REG32(0xFC0A8018)
4524 +#define MCF_PCI_PCIBAR3 MCF_REG32(0xFC0A801C)
4525 +#define MCF_PCI_PCIBAR4 MCF_REG32(0xFC0A8020)
4526 +#define MCF_PCI_PCIBAR5 MCF_REG32(0xFC0A8024)
4527 +#define MCF_PCI_PCISID MCF_REG32(0xFC0A802C)
4528 +#define MCF_PCI_PCICR2 MCF_REG32(0xFC0A803C)
4529 +#define MCF_PCI_PCIGSCR MCF_REG32(0xFC0A8060)
4530 +#define MCF_PCI_PCITBATR0A MCF_REG32(0xFC0A8064)
4531 +#define MCF_PCI_PCITBATR1A MCF_REG32(0xFC0A8068)
4532 +#define MCF_PCI_PCITCR MCF_REG32(0xFC0A806C)
4533 +#define MCF_PCI_PCIIW0BTAR MCF_REG32(0xFC0A8070)
4534 +#define MCF_PCI_PCIIW1BTAR MCF_REG32(0xFC0A8074)
4535 +#define MCF_PCI_PCIIW2BTAR MCF_REG32(0xFC0A8078)
4536 +#define MCF_PCI_PCIIWCR MCF_REG32(0xFC0A8080)
4537 +#define MCF_PCI_PCIICR MCF_REG32(0xFC0A8084)
4538 +#define MCF_PCI_PCIISR MCF_REG32(0xFC0A8088)
4539 +#define MCF_PCI_PCITCR2 MCF_REG32(0xFC0A808C)
4540 +#define MCF_PCI_PCITBATR0 MCF_REG32(0xFC0A8090)
4541 +#define MCF_PCI_PCITBATR1 MCF_REG32(0xFC0A8094)
4542 +#define MCF_PCI_PCITBATR2 MCF_REG32(0xFC0A8098)
4543 +#define MCF_PCI_PCITBATR3 MCF_REG32(0xFC0A809C)
4544 +#define MCF_PCI_PCITBATR4 MCF_REG32(0xFC0A80A0)
4545 +#define MCF_PCI_PCITBATR5 MCF_REG32(0xFC0A80A4)
4546 +#define MCF_PCI_PCICAR MCF_REG32(0xFC0A80F8)
4548 +/* Parameterized register read/write macros for multiple registers */
4549 +#define MCF_PCI_PCIIWBTAR(x) MCF_REG32(0xFC0A8070+((x)*0x004))
4551 +/* Bit definitions and macros for PCIIDR */
4552 +#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0x0000FFFF))
4553 +#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16)
4555 +/* Bit definitions and macros for PCISCR */
4556 +#define MCF_PCI_PCISCR_M (0x00000002)
4557 +#define MCF_PCI_PCISCR_B (0x00000004)
4558 +#define MCF_PCI_PCISCR_SP (0x00000008)
4559 +#define MCF_PCI_PCISCR_MW (0x00000010)
4560 +#define MCF_PCI_PCISCR_PER (0x00000040)
4561 +#define MCF_PCI_PCISCR_S (0x00000100)
4562 +#define MCF_PCI_PCISCR_F (0x00000200)
4563 +#define MCF_PCI_PCISCR_C (0x00100000)
4564 +#define MCF_PCI_PCISCR_66M (0x00200000)
4565 +#define MCF_PCI_PCISCR_R (0x00400000)
4566 +#define MCF_PCI_PCISCR_FC (0x00800000)
4567 +#define MCF_PCI_PCISCR_DP (0x01000000)
4568 +#define MCF_PCI_PCISCR_DT(x) (((x)&0x00000003)<<25)
4569 +#define MCF_PCI_PCISCR_TS (0x08000000)
4570 +#define MCF_PCI_PCISCR_TR (0x10000000)
4571 +#define MCF_PCI_PCISCR_MA (0x20000000)
4572 +#define MCF_PCI_PCISCR_SE (0x40000000)
4573 +#define MCF_PCI_PCISCR_PE (0x80000000)
4575 +/* Bit definitions and macros for PCICCRIR */
4576 +#define MCF_PCI_PCICCRIR_REVID(x) (((x)&0x000000FF))
4577 +#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8)
4579 +/* Bit definitions and macros for PCICR1 */
4580 +#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F))
4581 +#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8)
4582 +#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16)
4583 +#define MCF_PCI_PCICR1_BIST(x) (((x)&0x000000FF)<<24)
4585 +/* Bit definitions and macros for PCIBAR0 */
4586 +#define MCF_PCI_PCIBAR0_IO (0x00000001)
4587 +#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x00000003)<<1)
4588 +#define MCF_PCI_PCIBAR0_PREF (0x00000008)
4589 +#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x00003FFF)<<18)
4591 +/* Bit definitions and macros for PCIBAR1 */
4592 +#define MCF_PCI_PCIBAR1_IO (0x00000001)
4593 +#define MCF_PCI_PCIBAR1_PREF (0x00000008)
4594 +#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x00000FFF)<<20)
4596 +/* Bit definitions and macros for PCIBAR2 */
4597 +#define MCF_PCI_PCIBAR2_IO (0x00000001)
4598 +#define MCF_PCI_PCIBAR2_RANGE(x) (((x)&0x00000003)<<1)
4599 +#define MCF_PCI_PCIBAR2_PREF (0x00000008)
4600 +#define MCF_PCI_PCIBAR2_BAR2(x) (((x)&0x000003FF)<<22)
4602 +/* Bit definitions and macros for PCIBAR3 */
4603 +#define MCF_PCI_PCIBAR3_IO (0x00000001)
4604 +#define MCF_PCI_PCIBAR3_PREF (0x00000008)
4605 +#define MCF_PCI_PCIBAR3_BAR3(x) (((x)&0x000000FF)<<24)
4607 +/* Bit definitions and macros for PCIBAR4 */
4608 +#define MCF_PCI_PCIBAR4_IO (0x00000001)
4609 +#define MCF_PCI_PCIBAR4_RANGE(x) (((x)&0x00000003)<<1)
4610 +#define MCF_PCI_PCIBAR4_PREF (0x00000008)
4611 +#define MCF_PCI_PCIBAR4_BAR4(x) (((x)&0x0000001F)<<27)
4613 +/* Bit definitions and macros for PCIBAR5 */
4614 +#define MCF_PCI_PCIBAR5_IO (0x00000001)
4615 +#define MCF_PCI_PCIBAR5_PREF (0x00000008)
4616 +#define MCF_PCI_PCIBAR5_BAR5(x) (((x)&0x0000000F)<<28)
4618 +/* Bit definitions and macros for PCISID */
4619 +#define MCF_PCI_PCISID_VENDORID(x) (((x)&0x0000FFFF))
4620 +#define MCF_PCI_PCISID_ID(x) (((x)&0x0000FFFF)<<16)
4622 +/* Bit definitions and macros for PCICR2 */
4623 +#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0x000000FF))
4624 +#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8)
4625 +#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16)
4626 +#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24)
4628 +/* Bit definitions and macros for PCIGSCR */
4629 +#define MCF_PCI_PCIGSCR_PR (0x00000001)
4630 +#define MCF_PCI_PCIGSCR_SEE (0x00001000)
4631 +#define MCF_PCI_PCIGSCR_PEE (0x00002000)
4632 +#define MCF_PCI_PCIGSCR_SE (0x10000000)
4633 +#define MCF_PCI_PCIGSCR_PE (0x20000000)
4635 +/* Bit definitions and macros for PCITBATR0A */
4636 +#define MCF_PCI_PCITBATR0A_EN (0x00000001)
4637 +#define MCF_PCI_PCITBATR0A_BAT0(x) (((x)&0x00003FFF)<<18)
4639 +/* Bit definitions and macros for PCITBATR1A */
4640 +#define MCF_PCI_PCITBATR1A_EN (0x00000001)
4641 +#define MCF_PCI_PCITBATR1A_BAT1(x) (((x)&0x00000FFF)<<20)
4643 +/* Bit definitions and macros for PCITCR */
4644 +#define MCF_PCI_PCITCR_WCT(x) (((x)&0x000000FF))
4645 +#define MCF_PCI_PCITCR_WCD (0x00000100)
4646 +#define MCF_PCI_PCITCR_P (0x00010000)
4647 +#define MCF_PCI_PCITCR_PID (0x00020000)
4648 +#define MCF_PCI_PCITCR_LD (0x01000000)
4650 +/* Bit definitions and macros for PCIIWBTAR group */
4651 +#define MCF_PCI_PCIIWBTAR_WBA(x) ((((x)&0xFF000000)))
4652 +#define MCF_PCI_PCIIWBTAR_WAM(x) ((((x)&0xFF000000)
4653 +#define MCF_PCI_PCIIWBTAR_WTA(x) ((((x)&0xFF000000)
4655 +/* Bit definitions and macros for PCIIW0BTAR */
4656 +#define MCF_PCI_PCIIW0BTAR_WBA(x) ((((x)&0xFF000000)))
4657 +#define MCF_PCI_PCIIW0BTAR_WAM(x) ((((x)&0xFF000000)
4658 +#define MCF_PCI_PCIIW0BTAR_WTA(x) ((((x)&0xFF000000)
4660 +/* Bit definitions and macros for PCIIWCR */
4661 +#define MCF_PCI_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8)
4662 +#define MCF_PCI_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16)
4663 +#define MCF_PCI_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24)
4664 +#define MCF_PCI_PCIIWCR_WINCTRL0_ENABLE (0x01000000)
4665 +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x01000000)
4666 +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000)
4667 +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000)
4668 +#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x09000000)
4669 +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x00010000)
4670 +#define MCF_PCI_PCIIWCR_WINCTRL1_ENABLE (0x00010000)
4671 +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000)
4672 +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000)
4673 +#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x00090000)
4674 +#define MCF_PCI_PCIIWCR_WINCTRL2_ENABLE (0x00000100)
4675 +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x00000100)
4676 +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300)
4677 +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500)
4678 +#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x00000900)
4680 +/* Bit definitions and macros for PCIICR */
4681 +#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0x000000FF))
4682 +#define MCF_PCI_PCIICR_TAE (0x01000000)
4683 +#define MCF_PCI_PCIICR_IAE (0x02000000)
4684 +#define MCF_PCI_PCIICR_REE (0x04000000)
4686 +/* Bit definitions and macros for PCIISR */
4687 +#define MCF_PCI_PCIISR_TA (0x01000000)
4688 +#define MCF_PCI_PCIISR_IA (0x02000000)
4689 +#define MCF_PCI_PCIISR_RE (0x04000000)
4691 +/* Bit definitions and macros for PCITCR2 */
4692 +#define MCF_PCI_PCITCR2_CR (0x00000001)
4693 +#define MCF_PCI_PCITCR2_B0E (0x00000100)
4694 +#define MCF_PCI_PCITCR2_B1E (0x00000200)
4695 +#define MCF_PCI_PCITCR2_B2E (0x00000400)
4696 +#define MCF_PCI_PCITCR2_B3E (0x00000800)
4697 +#define MCF_PCI_PCITCR2_B4E (0x00001000)
4698 +#define MCF_PCI_PCITCR2_B5E (0x00002000)
4700 +/* Bit definitions and macros for PCITBATR0 */
4701 +#define MCF_PCI_PCITBATR0_EN (0x00000001)
4702 +#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18)
4704 +/* Bit definitions and macros for PCITBATR1 */
4705 +#define MCF_PCI_PCITBATR1_EN (0x00000001)
4706 +#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x00000FFF)<<20)
4708 +/* Bit definitions and macros for PCITBATR2 */
4709 +#define MCF_PCI_PCITBATR2_EN (0x00000001)
4710 +#define MCF_PCI_PCITBATR2_BAT2(x) (((x)&0x000003FF)<<22)
4712 +/* Bit definitions and macros for PCITBATR3 */
4713 +#define MCF_PCI_PCITBATR3_EN (0x00000001)
4714 +#define MCF_PCI_PCITBATR3_BAT3(x) (((x)&0x000000FF)<<24)
4716 +/* Bit definitions and macros for PCITBATR4 */
4717 +#define MCF_PCI_PCITBATR4_EN (0x00000001)
4718 +#define MCF_PCI_PCITBATR4_BAT4(x) (((x)&0x0000001F)<<27)
4720 +/* Bit definitions and macros for PCITBATR5 */
4721 +#define MCF_PCI_PCITBATR5_EN (0x00000001)
4722 +#define MCF_PCI_PCITBATR5_BAT5(x) (((x)&0x0000000F)<<28)
4724 +/* Bit definitions and macros for PCICAR */
4725 +#define MCF_PCI_PCICAR_DWORD(x) ((x)&0x000000FC)
4726 +#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8)
4727 +#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11)
4728 +#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16)
4729 +#define MCF_PCI_PCICAR_E (0x80000000)
4731 +/********************************************************************/
4733 +#endif /* __MCF5445X_PCI_H__ */
4735 +++ b/include/asm-m68k/mcf5445x_pciarb.h
4738 + * Kurt Mahan kmahan@freescale.com
4740 + * Copyright Freescale Semiconductor, Inc. 2007
4742 + * This program is free software; you can redistribute it and/or modify it
4743 + * under the terms of the GNU General Public License as published by the
4744 + * Free Software Foundation; either version 2 of the License, or (at your
4745 + * option) any later version.
4748 +#ifndef __MCF5445X_PCIARB_H__
4749 +#define __MCF5445X_PCIARB_H__
4751 +/*********************************************************************
4753 +* PCI Arbiter Module (PCIARB)
4755 +*********************************************************************/
4757 +/* Register read/write macros */
4758 +#define MCF_PCIARB_PACR MCF_REG32(0xFC0AC000)
4759 +#define MCF_PCIARB_PASR MCF_REG32(0xFC0AC004)
4761 +/* Bit definitions and macros for PACR */
4762 +#define MCF_PCIARB_PACR_INTMPRI (0x00000001)
4763 +#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1)
4764 +#define MCF_PCIARB_PACR_RA (0x00008000)
4765 +#define MCF_PCIARB_PACR_INTMINTEN (0x00010000)
4766 +#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17)
4767 +#define MCF_PCIARB_PACR_PKMD (0x40000000)
4768 +#define MCF_PCIARB_PACR_DS (0x80000000)
4770 +/* Bit definitions and macros for PASR */
4771 +#define MCF_PCIARB_PASR_ITLMBK (0x00010000)
4772 +#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17)
4774 +/********************************************************************/
4776 +#endif /* __MCF5445X_PCIARB_H__ */
4778 +++ b/include/asm-m68k/mcf5445x_sdramc.h
4781 + * Matt Waddel Matt.Waddel@freescale.com
4783 + * Copyright Freescale Semiconductor, Inc. 2007
4785 + * This program is free software; you can redistribute it and/or modify it
4786 + * under the terms of the GNU General Public License as published by the
4787 + * Free Software Foundation; either version 2 of the License, or (at your
4788 + * option) any later version.
4791 +#ifndef __MCF5445X_SDRAMC_H__
4792 +#define __MCF5445X_SDRAMC_H__
4794 +/*********************************************************************
4796 +* SDRAM Controller (SDRAMC)
4798 +*********************************************************************/
4800 +/* Register read/write macros */
4801 +#define MCF_SDRAMC_SDMR (*(vuint32 *)(0xFC0B8000)) /* SDRAM Mode/Extended Mode Register */
4802 +#define MCF_SDRAMC_SDCR (*(vuint32 *)(0xFC0B8004)) /* SDRAM Control Register */
4803 +#define MCF_SDRAMC_SDCFG1 (*(vuint32 *)(0xFC0B8008)) /* SDRAM Configuration Register 1 */
4804 +#define MCF_SDRAMC_SDCFG2 (*(vuint32 *)(0xFC0B800C)) /* SDRAM Configuration Register 2 */
4805 +#define MCF_SDRAMC_SDCS0 (*(vuint32 *)(0xFC0B8110)) /* SDRAM Chip Select Register */
4806 +#define MCF_SDRAMC_SDCS1 (*(vuint32 *)(0xFC0B8114)) /* SDRAM Chip Select Register */
4808 +/* Parameterized register read/write macros for multiple registers */
4809 +#define MCF_SDRAMC_SDCS(x) (*(vuint32 *)(0xFC0B8110+((x)*0x004))) /* SDRAM Chip Select Register */
4811 +/* Bit definitions and macros for SDMR */
4812 +#define MCF_SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */
4813 +#define MCF_SDRAMC_SDMR_CMD (0x00010000) /* Command */
4814 +#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */
4815 +#define MCF_SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */
4816 +#define MCF_SDRAMC_SDMR_BK_LMR (0x00000000)
4817 +#define MCF_SDRAMC_SDMR_BK_LEMR (0x40000000)
4819 +/* Bit definitions and macros for SDCR */
4820 +#define MCF_SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */
4821 +#define MCF_SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */
4822 +#define MCF_SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */
4823 +#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */
4824 +#define MCF_SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */
4825 +#define MCF_SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */
4826 +#define MCF_SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */
4827 +#define MCF_SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */
4828 +#define MCF_SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */
4829 +#define MCF_SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */
4830 +#define MCF_SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */
4831 +#define MCF_SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */
4832 +#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */
4833 +#define MCF_SDRAMC_SDCR_DQS_OE_BOTH (0x00000C00)
4835 +/* Bit definitions and macros for SDCFG1 */
4836 +#define MCF_SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */
4837 +#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */
4838 +#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */
4839 +#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */
4840 +#define MCF_SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */
4841 +#define MCF_SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */
4842 +#define MCF_SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */
4844 +/* Bit definitions and macros for SDCFG2 */
4845 +#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */
4846 +#define MCF_SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */
4847 +#define MCF_SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */
4848 +#define MCF_SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */
4850 +/* Bit definitions and macros for SDCS group */
4851 +#define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */
4852 +#define MCF_SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
4853 +#define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
4854 +#define MCF_SDRAMC_SDCS_CSSZ_DISABLE (0x00000000)
4855 +#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
4856 +#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
4857 +#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
4858 +#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
4859 +#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
4860 +#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
4861 +#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
4862 +#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
4863 +#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
4864 +#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
4865 +#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
4866 +#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
4867 +#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
4869 +/* Bit definitions and macros for SDCS0 */
4870 +#define MCF_SDRAMC_SDCS0_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */
4871 +#define MCF_SDRAMC_SDCS0_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
4872 +#define MCF_SDRAMC_SDCS0_BA(x) ((x)&0xFFF00000)
4873 +#define MCF_SDRAMC_SDCS0_CSSZ_DISABLE (0x00000000)
4874 +#define MCF_SDRAMC_SDCS0_CSSZ_1MBYTE (0x00000013)
4875 +#define MCF_SDRAMC_SDCS0_CSSZ_2MBYTE (0x00000014)
4876 +#define MCF_SDRAMC_SDCS0_CSSZ_4MBYTE (0x00000015)
4877 +#define MCF_SDRAMC_SDCS0_CSSZ_8MBYTE (0x00000016)
4878 +#define MCF_SDRAMC_SDCS0_CSSZ_16MBYTE (0x00000017)
4879 +#define MCF_SDRAMC_SDCS0_CSSZ_32MBYTE (0x00000018)
4880 +#define MCF_SDRAMC_SDCS0_CSSZ_64MBYTE (0x00000019)
4881 +#define MCF_SDRAMC_SDCS0_CSSZ_128MBYTE (0x0000001A)
4882 +#define MCF_SDRAMC_SDCS0_CSSZ_256MBYTE (0x0000001B)
4883 +#define MCF_SDRAMC_SDCS0_CSSZ_512MBYTE (0x0000001C)
4884 +#define MCF_SDRAMC_SDCS0_CSSZ_1GBYTE (0x0000001D)
4885 +#define MCF_SDRAMC_SDCS0_CSSZ_2GBYTE (0x0000001E)
4886 +#define MCF_SDRAMC_SDCS0_CSSZ_4GBYTE (0x0000001F)
4888 +/* Bit definitions and macros for SDCS1 */
4889 +#define MCF_SDRAMC_SDCS1_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */
4890 +#define MCF_SDRAMC_SDCS1_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
4892 +/********************************************************************/
4894 +#endif /* __MCF5445X_SDRAMC_H__ */
4896 +++ b/include/asm-m68k/mcf5445x_ssi.h
4899 + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
4901 + * Copyright Freescale Semiconductor, Inc. 2007
4903 + * This program is free software; you can redistribute it and/or modify it
4904 + * under the terms of the GNU General Public License as published by the
4905 + * Free Software Foundation; either version 2 of the License, or (at your
4906 + * option) any later version.
4909 +#ifndef __MCF5445X_SSI_H__
4910 +#define __MCF5445X_SSI_H__
4912 +/*********************************************************************
4914 +* Synchronous Serial Interface (SSI)
4916 +*********************************************************************/
4918 +/* Register read/write macros */
4919 +#define MCF_SSI_TX0 MCF_REG32(0xFC0BC000)
4920 +#define MCF_SSI_TX1 MCF_REG32(0xFC0BC004)
4921 +#define MCF_SSI_RX0 MCF_REG32(0xFC0BC008)
4922 +#define MCF_SSI_RX1 MCF_REG32(0xFC0BC00C)
4923 +#define MCF_SSI_CR MCF_REG32(0xFC0BC010)
4924 +#define MCF_SSI_ISR MCF_REG32(0xFC0BC014)
4925 +#define MCF_SSI_IER MCF_REG32(0xFC0BC018)
4926 +#define MCF_SSI_TCR MCF_REG32(0xFC0BC01C)
4927 +#define MCF_SSI_RCR MCF_REG32(0xFC0BC020)
4928 +#define MCF_SSI_CCR MCF_REG32(0xFC0BC024)
4929 +#define MCF_SSI_FCSR MCF_REG32(0xFC0BC02C)
4930 +#define MCF_SSI_ACR MCF_REG32(0xFC0BC038)
4931 +#define MCF_SSI_ACADD MCF_REG32(0xFC0BC03C)
4932 +#define MCF_SSI_ACDAT MCF_REG32(0xFC0BC040)
4933 +#define MCF_SSI_ATAG MCF_REG32(0xFC0BC044)
4934 +#define MCF_SSI_TMASK MCF_REG32(0xFC0BC048)
4935 +#define MCF_SSI_RMASK MCF_REG32(0xFC0BC04C)
4937 +/* Parameterized register read/write macros for multiple registers */
4938 +#define MCF_SSI_TX(x) MCF_REG32(0xFC0BC000+((x)*0x004))
4939 +#define MCF_SSI_RX(x) MCF_REG32(0xFC0BC008+((x)*0x004))
4941 +/* Bit definitions and macros for TX group */
4942 +#define MCF_SSI_TX_SSI_TX(x) (x)
4944 +/* Bit definitions and macros for TX0 */
4945 +#define MCF_SSI_TX0_SSI_TX(x) (x)
4947 +/* Bit definitions and macros for TX1 */
4948 +#define MCF_SSI_TX1_SSI_TX(x) (x)
4950 +/* Bit definitions and macros for RX group */
4951 +#define MCF_SSI_RX_SSI_RX(x) (x)
4953 +/* Bit definitions and macros for RX0 */
4954 +#define MCF_SSI_RX0_SSI_RX(x) (x)
4956 +/* Bit definitions and macros for RX1 */
4957 +#define MCF_SSI_RX1_SSI_RX(x) (x)
4959 +/* Bit definitions and macros for CR */
4960 +#define MCF_SSI_CR_SSI_EN (0x00000001)
4961 +#define MCF_SSI_CR_TE (0x00000002)
4962 +#define MCF_SSI_CR_RE (0x00000004)
4963 +#define MCF_SSI_CR_NET (0x00000008)
4964 +#define MCF_SSI_CR_SYN (0x00000010)
4965 +#define MCF_SSI_CR_I2S(x) (((x)&0x00000003)<<5)
4966 +#define MCF_SSI_CR_MCE (0x00000080)
4967 +#define MCF_SSI_CR_TCH (0x00000100)
4968 +#define MCF_SSI_CR_CIS (0x00000200)
4969 +#define MCF_SSI_CR_I2S_NORMAL (0x00000000)
4970 +#define MCF_SSI_CR_I2S_MASTER (0x00000020)
4971 +#define MCF_SSI_CR_I2S_SLAVE (0x00000040)
4973 +/* Bit definitions and macros for ISR */
4974 +#define MCF_SSI_ISR_TFE0 (0x00000001)
4975 +#define MCF_SSI_ISR_TFE1 (0x00000002)
4976 +#define MCF_SSI_ISR_RFF0 (0x00000004)
4977 +#define MCF_SSI_ISR_RFF1 (0x00000008)
4978 +#define MCF_SSI_ISR_RLS (0x00000010)
4979 +#define MCF_SSI_ISR_TLS (0x00000020)
4980 +#define MCF_SSI_ISR_RFS (0x00000040)
4981 +#define MCF_SSI_ISR_TFS (0x00000080)
4982 +#define MCF_SSI_ISR_TUE0 (0x00000100)
4983 +#define MCF_SSI_ISR_TUE1 (0x00000200)
4984 +#define MCF_SSI_ISR_ROE0 (0x00000400)
4985 +#define MCF_SSI_ISR_ROE1 (0x00000800)
4986 +#define MCF_SSI_ISR_TDE0 (0x00001000)
4987 +#define MCF_SSI_ISR_TDE1 (0x00002000)
4988 +#define MCF_SSI_ISR_RDR0 (0x00004000)
4989 +#define MCF_SSI_ISR_RDR1 (0x00008000)
4990 +#define MCF_SSI_ISR_RXT (0x00010000)
4991 +#define MCF_SSI_ISR_CMDDU (0x00020000)
4992 +#define MCF_SSI_ISR_CMDAU (0x00040000)
4994 +/* Bit definitions and macros for IER */
4995 +#define MCF_SSI_IER_TFE0 (0x00000001)
4996 +#define MCF_SSI_IER_TFE1 (0x00000002)
4997 +#define MCF_SSI_IER_RFF0 (0x00000004)
4998 +#define MCF_SSI_IER_RFF1 (0x00000008)
4999 +#define MCF_SSI_IER_RLS (0x00000010)
5000 +#define MCF_SSI_IER_TLS (0x00000020)
5001 +#define MCF_SSI_IER_RFS (0x00000040)
5002 +#define MCF_SSI_IER_TFS (0x00000080)
5003 +#define MCF_SSI_IER_TUE0 (0x00000100)
5004 +#define MCF_SSI_IER_TUE1 (0x00000200)
5005 +#define MCF_SSI_IER_ROE0 (0x00000400)
5006 +#define MCF_SSI_IER_ROE1 (0x00000800)
5007 +#define MCF_SSI_IER_TDE0 (0x00001000)
5008 +#define MCF_SSI_IER_TDE1 (0x00002000)
5009 +#define MCF_SSI_IER_RDR0 (0x00004000)
5010 +#define MCF_SSI_IER_RDR1 (0x00008000)
5011 +#define MCF_SSI_IER_RXT (0x00010000)
5012 +#define MCF_SSI_IER_CMDU (0x00020000)
5013 +#define MCF_SSI_IER_CMDAU (0x00040000)
5014 +#define MCF_SSI_IER_TIE (0x00080000)
5015 +#define MCF_SSI_IER_TDMAE (0x00100000)
5016 +#define MCF_SSI_IER_RIE (0x00200000)
5017 +#define MCF_SSI_IER_RDMAE (0x00400000)
5019 +/* Bit definitions and macros for TCR */
5020 +#define MCF_SSI_TCR_TEFS (0x00000001)
5021 +#define MCF_SSI_TCR_TFSL (0x00000002)
5022 +#define MCF_SSI_TCR_TFSI (0x00000004)
5023 +#define MCF_SSI_TCR_TSCKP (0x00000008)
5024 +#define MCF_SSI_TCR_TSHFD (0x00000010)
5025 +#define MCF_SSI_TCR_TXDIR (0x00000020)
5026 +#define MCF_SSI_TCR_TFDIR (0x00000040)
5027 +#define MCF_SSI_TCR_TFEN0 (0x00000080)
5028 +#define MCF_SSI_TCR_TFEN1 (0x00000100)
5029 +#define MCF_SSI_TCR_TXBIT0 (0x00000200)
5031 +/* Bit definitions and macros for RCR */
5032 +#define MCF_SSI_RCR_REFS (0x00000001)
5033 +#define MCF_SSI_RCR_RFSL (0x00000002)
5034 +#define MCF_SSI_RCR_RFSI (0x00000004)
5035 +#define MCF_SSI_RCR_RSCKP (0x00000008)
5036 +#define MCF_SSI_RCR_RSHFD (0x00000010)
5037 +#define MCF_SSI_RCR_RFEN0 (0x00000080)
5038 +#define MCF_SSI_RCR_RFEN1 (0x00000100)
5039 +#define MCF_SSI_RCR_RXBIT0 (0x00000200)
5040 +#define MCF_SSI_RCR_RXEXT (0x00000400)
5042 +/* Bit definitions and macros for CCR */
5043 +#define MCF_SSI_CCR_PM(x) (((x)&0x000000FF))
5044 +#define MCF_SSI_CCR_DC(x) (((x)&0x0000001F)<<8)
5045 +#define MCF_SSI_CCR_WL(x) (((x)&0x0000000F)<<13)
5046 +#define MCF_SSI_CCR_PSR (0x00020000)
5047 +#define MCF_SSI_CCR_DIV2 (0x00040000)
5049 +/* Bit definitions and macros for FCSR */
5050 +#define MCF_SSI_FCSR_TFWM0(x) (((x)&0x0000000F))
5051 +#define MCF_SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)
5052 +#define MCF_SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)
5053 +#define MCF_SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)
5054 +#define MCF_SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)
5055 +#define MCF_SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)
5056 +#define MCF_SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)
5057 +#define MCF_SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)
5059 +/* Bit definitions and macros for ACR */
5060 +#define MCF_SSI_ACR_AC97EN (0x00000001)
5061 +#define MCF_SSI_ACR_FV (0x00000002)
5062 +#define MCF_SSI_ACR_TIF (0x00000004)
5063 +#define MCF_SSI_ACR_RD (0x00000008)
5064 +#define MCF_SSI_ACR_WR (0x00000010)
5065 +#define MCF_SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)
5067 +/* Bit definitions and macros for ACADD */
5068 +#define MCF_SSI_ACADD_SSI_ACADD(x) (((x)&0x0007FFFF))
5070 +/* Bit definitions and macros for ACDAT */
5071 +#define MCF_SSI_ACDAT_SSI_ACDAT(x) (((x)&0x0007FFFF))
5073 +/* Bit definitions and macros for ATAG */
5074 +#define MCF_SSI_ATAG_DDI_ATAG(x) (((x)&0x0000FFFF))
5076 +/* Bit definitions and macros for TMASK */
5077 +#define MCF_SSI_TMASK_SSI_TMASK(x) (x)
5079 +/* Bit definitions and macros for RMASK */
5080 +#define MCF_SSI_RMASK_SSI_RMASK(x) (x)
5082 +/********************************************************************/
5084 +#endif /* __MCF5445X_SSI_H__ */
5086 +++ b/include/asm-m68k/mcf5445x_usb.h
5089 + * Duck Schmid duck@freescale.com
5091 + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5095 + * The code contained herein is licensed under the GNU General Public
5096 + * License. You may obtain a copy of the GNU General Public License
5097 + * Version 2 or later at the following locations:
5099 + * http://www.opensource.org/licenses/gpl-license.html
5100 + * http://www.gnu.org/copyleft/gpl.html
5103 +#include <asm/mcfsim.h>
5105 +/* ehci_arc_hc_driver.flags value */
5106 +#define FSL_PLATFORM_HC_FLAGS (HCD_USB2 | HCD_MEMORY)
5108 +static inline int fsl_platform_verify(struct platform_device *pdev)
5113 +static inline void fsl_platform_usb_setup(struct usb_hcd *hcd)
5117 +static inline void fsl_platform_set_host_mode(struct usb_hcd *hcd)
5119 + unsigned int temp;
5120 + struct fsl_usb2_platform_data *pdata;
5121 + struct fsl_usb_host_regs *regs;
5123 + pdata = hcd->self.controller->platform_data;
5124 + regs = pdata->regs;
5126 + if (pdata->xcvr_ops && pdata->xcvr_ops->set_host)
5127 + pdata->xcvr_ops->set_host();
5129 + /* set host mode and select "big endian" */
5130 + temp = fsl_readl(®s->usbmode);
5131 + fsl_writel(temp | USBMODE_CM_HOST | USBMODE_ES, ®s->usbmode);
5133 + pr_debug("%s: set usbmode to 0x%x\n\n", __FUNCTION__,
5134 + fsl_readl(®s->usbmode));
projects / openwrt.git / blob