2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
23 #include <asm/mach-ar71xx/ar71xx.h>
24 #include <asm/mach-ar71xx/ar933x_uart_platform.h>
28 unsigned char ar71xx_mac_base
[ETH_ALEN
] __initdata
;
30 static struct resource ar71xx_uart_resources
[] = {
32 .start
= AR71XX_UART_BASE
,
33 .end
= AR71XX_UART_BASE
+ AR71XX_UART_SIZE
- 1,
34 .flags
= IORESOURCE_MEM
,
38 #define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
39 static struct plat_serial8250_port ar71xx_uart_data
[] = {
41 .mapbase
= AR71XX_UART_BASE
,
42 .irq
= AR71XX_MISC_IRQ_UART
,
43 .flags
= AR71XX_UART_FLAGS
,
47 /* terminating entry */
51 static struct platform_device ar71xx_uart_device
= {
53 .id
= PLAT8250_DEV_PLATFORM
,
54 .resource
= ar71xx_uart_resources
,
55 .num_resources
= ARRAY_SIZE(ar71xx_uart_resources
),
57 .platform_data
= ar71xx_uart_data
61 static struct resource ar933x_uart_resources
[] = {
63 .start
= AR933X_UART_BASE
,
64 .end
= AR933X_UART_BASE
+ AR71XX_UART_SIZE
- 1,
65 .flags
= IORESOURCE_MEM
,
68 .start
= AR71XX_MISC_IRQ_UART
,
69 .end
= AR71XX_MISC_IRQ_UART
,
70 .flags
= IORESOURCE_IRQ
,
74 static struct ar933x_uart_platform_data ar933x_uart_data
;
75 static struct platform_device ar933x_uart_device
= {
76 .name
= "ar933x-uart",
78 .resource
= ar933x_uart_resources
,
79 .num_resources
= ARRAY_SIZE(ar933x_uart_resources
),
81 .platform_data
= &ar933x_uart_data
,
85 void __init
ar71xx_add_device_uart(void)
87 struct platform_device
*pdev
;
90 case AR71XX_SOC_AR7130
:
91 case AR71XX_SOC_AR7141
:
92 case AR71XX_SOC_AR7161
:
93 case AR71XX_SOC_AR7240
:
94 case AR71XX_SOC_AR7241
:
95 case AR71XX_SOC_AR7242
:
96 case AR71XX_SOC_AR9130
:
97 case AR71XX_SOC_AR9132
:
98 pdev
= &ar71xx_uart_device
;
99 ar71xx_uart_data
[0].uartclk
= ar71xx_ahb_freq
;
102 case AR71XX_SOC_AR9330
:
103 case AR71XX_SOC_AR9331
:
104 pdev
= &ar933x_uart_device
;
105 ar933x_uart_data
.uartclk
= ar71xx_ref_freq
;
108 case AR71XX_SOC_AR9341
:
109 case AR71XX_SOC_AR9342
:
110 case AR71XX_SOC_AR9344
:
111 pdev
= &ar71xx_uart_device
;
112 ar71xx_uart_data
[0].uartclk
= ar71xx_ref_freq
;
119 platform_device_register(pdev
);
122 static struct resource ar71xx_mdio0_resources
[] = {
125 .flags
= IORESOURCE_MEM
,
126 .start
= AR71XX_GE0_BASE
,
127 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
131 static struct ag71xx_mdio_platform_data ar71xx_mdio0_data
;
133 struct platform_device ar71xx_mdio0_device
= {
134 .name
= "ag71xx-mdio",
136 .resource
= ar71xx_mdio0_resources
,
137 .num_resources
= ARRAY_SIZE(ar71xx_mdio0_resources
),
139 .platform_data
= &ar71xx_mdio0_data
,
143 static void ar71xx_set_pll(u32 cfg_reg
, u32 pll_reg
, u32 pll_val
, u32 shift
)
148 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
150 t
= __raw_readl(base
+ cfg_reg
);
153 __raw_writel(t
, base
+ cfg_reg
);
156 __raw_writel(pll_val
, base
+ pll_reg
);
159 __raw_writel(t
, base
+ cfg_reg
);
163 __raw_writel(t
, base
+ cfg_reg
);
166 printk(KERN_DEBUG
"ar71xx: pll_reg %#x: %#x\n",
167 (unsigned int)(base
+ pll_reg
), __raw_readl(base
+ pll_reg
));
172 void __init
ar71xx_add_device_mdio(unsigned int id
, u32 phy_mask
)
175 printk(KERN_ERR
"ar71xx: invalid MDIO id %u\n", id
);
179 switch (ar71xx_soc
) {
180 case AR71XX_SOC_AR7240
:
181 ar71xx_mdio0_data
.is_ar7240
= 1;
183 case AR71XX_SOC_AR7241
:
184 ar71xx_mdio0_data
.is_ar7240
= 1;
185 ar71xx_mdio0_resources
[0].start
= AR71XX_GE1_BASE
;
186 ar71xx_mdio0_resources
[0].end
= AR71XX_GE1_BASE
+ 0x200 - 1;
188 case AR71XX_SOC_AR7242
:
189 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG
,
190 AR7242_PLL_REG_ETH0_INT_CLOCK
, 0x62000000,
191 AR71XX_ETH0_PLL_SHIFT
);
193 case AR71XX_SOC_AR9330
:
194 case AR71XX_SOC_AR9331
:
195 ar71xx_mdio0_data
.is_ar7240
= 1;
196 ar71xx_mdio0_resources
[0].start
= AR71XX_GE1_BASE
;
197 ar71xx_mdio0_resources
[0].end
= AR71XX_GE1_BASE
+ 0x200 - 1;
203 ar71xx_mdio0_data
.phy_mask
= phy_mask
;
205 platform_device_register(&ar71xx_mdio0_device
);
208 struct ar71xx_eth_pll_data ar71xx_eth0_pll_data
;
209 struct ar71xx_eth_pll_data ar71xx_eth1_pll_data
;
211 static u32
ar71xx_get_eth_pll(unsigned int mac
, int speed
)
213 struct ar71xx_eth_pll_data
*pll_data
;
218 pll_data
= &ar71xx_eth0_pll_data
;
221 pll_data
= &ar71xx_eth1_pll_data
;
229 pll_val
= pll_data
->pll_10
;
232 pll_val
= pll_data
->pll_100
;
235 pll_val
= pll_data
->pll_1000
;
244 static void ar71xx_set_pll_ge0(int speed
)
246 u32 val
= ar71xx_get_eth_pll(0, speed
);
248 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH0_INT_CLOCK
,
249 val
, AR71XX_ETH0_PLL_SHIFT
);
252 static void ar71xx_set_pll_ge1(int speed
)
254 u32 val
= ar71xx_get_eth_pll(1, speed
);
256 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH1_INT_CLOCK
,
257 val
, AR71XX_ETH1_PLL_SHIFT
);
260 static void ar724x_set_pll_ge0(int speed
)
265 static void ar724x_set_pll_ge1(int speed
)
270 static void ar7242_set_pll_ge0(int speed
)
272 u32 val
= ar71xx_get_eth_pll(0, speed
);
275 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
276 __raw_writel(val
, base
+ AR7242_PLL_REG_ETH0_INT_CLOCK
);
280 static void ar91xx_set_pll_ge0(int speed
)
282 u32 val
= ar71xx_get_eth_pll(0, speed
);
284 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG
, AR91XX_PLL_REG_ETH0_INT_CLOCK
,
285 val
, AR91XX_ETH0_PLL_SHIFT
);
288 static void ar91xx_set_pll_ge1(int speed
)
290 u32 val
= ar71xx_get_eth_pll(1, speed
);
292 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG
, AR91XX_PLL_REG_ETH1_INT_CLOCK
,
293 val
, AR91XX_ETH1_PLL_SHIFT
);
296 static void ar933x_set_pll_ge0(int speed
)
301 static void ar933x_set_pll_ge1(int speed
)
306 static void ar934x_set_pll_ge0(int speed
)
311 static void ar934x_set_pll_ge1(int speed
)
316 static void ar71xx_ddr_flush_ge0(void)
318 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0
);
321 static void ar71xx_ddr_flush_ge1(void)
323 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1
);
326 static void ar724x_ddr_flush_ge0(void)
328 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0
);
331 static void ar724x_ddr_flush_ge1(void)
333 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1
);
336 static void ar91xx_ddr_flush_ge0(void)
338 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0
);
341 static void ar91xx_ddr_flush_ge1(void)
343 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1
);
346 static void ar933x_ddr_flush_ge0(void)
348 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0
);
351 static void ar933x_ddr_flush_ge1(void)
353 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1
);
356 static void ar934x_ddr_flush_ge0(void)
358 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE0
);
361 static void ar934x_ddr_flush_ge1(void)
363 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE1
);
366 static struct resource ar71xx_eth0_resources
[] = {
369 .flags
= IORESOURCE_MEM
,
370 .start
= AR71XX_GE0_BASE
,
371 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
374 .flags
= IORESOURCE_MEM
,
375 .start
= AR71XX_MII_BASE
+ MII_REG_MII0_CTRL
,
376 .end
= AR71XX_MII_BASE
+ MII_REG_MII0_CTRL
+ 3,
379 .flags
= IORESOURCE_IRQ
,
380 .start
= AR71XX_CPU_IRQ_GE0
,
381 .end
= AR71XX_CPU_IRQ_GE0
,
385 struct ag71xx_platform_data ar71xx_eth0_data
= {
386 .reset_bit
= RESET_MODULE_GE0_MAC
,
389 struct platform_device ar71xx_eth0_device
= {
392 .resource
= ar71xx_eth0_resources
,
393 .num_resources
= ARRAY_SIZE(ar71xx_eth0_resources
),
395 .platform_data
= &ar71xx_eth0_data
,
399 static struct resource ar71xx_eth1_resources
[] = {
402 .flags
= IORESOURCE_MEM
,
403 .start
= AR71XX_GE1_BASE
,
404 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
407 .flags
= IORESOURCE_MEM
,
408 .start
= AR71XX_MII_BASE
+ MII_REG_MII1_CTRL
,
409 .end
= AR71XX_MII_BASE
+ MII_REG_MII1_CTRL
+ 3,
412 .flags
= IORESOURCE_IRQ
,
413 .start
= AR71XX_CPU_IRQ_GE1
,
414 .end
= AR71XX_CPU_IRQ_GE1
,
418 struct ag71xx_platform_data ar71xx_eth1_data
= {
419 .reset_bit
= RESET_MODULE_GE1_MAC
,
422 struct platform_device ar71xx_eth1_device
= {
425 .resource
= ar71xx_eth1_resources
,
426 .num_resources
= ARRAY_SIZE(ar71xx_eth1_resources
),
428 .platform_data
= &ar71xx_eth1_data
,
432 #define AR71XX_PLL_VAL_1000 0x00110000
433 #define AR71XX_PLL_VAL_100 0x00001099
434 #define AR71XX_PLL_VAL_10 0x00991099
436 #define AR724X_PLL_VAL_1000 0x00110000
437 #define AR724X_PLL_VAL_100 0x00001099
438 #define AR724X_PLL_VAL_10 0x00991099
440 #define AR7242_PLL_VAL_1000 0x16000000
441 #define AR7242_PLL_VAL_100 0x00000101
442 #define AR7242_PLL_VAL_10 0x00001616
444 #define AR91XX_PLL_VAL_1000 0x1a000000
445 #define AR91XX_PLL_VAL_100 0x13000a44
446 #define AR91XX_PLL_VAL_10 0x00441099
448 #define AR933X_PLL_VAL_1000 0x00110000
449 #define AR933X_PLL_VAL_100 0x00001099
450 #define AR933X_PLL_VAL_10 0x00991099
452 #define AR934X_PLL_VAL_1000 0x00110000
453 #define AR934X_PLL_VAL_100 0x00001099
454 #define AR934X_PLL_VAL_10 0x00991099
456 static void __init
ar71xx_init_eth_pll_data(unsigned int id
)
458 struct ar71xx_eth_pll_data
*pll_data
;
459 u32 pll_10
, pll_100
, pll_1000
;
463 pll_data
= &ar71xx_eth0_pll_data
;
466 pll_data
= &ar71xx_eth1_pll_data
;
472 switch (ar71xx_soc
) {
473 case AR71XX_SOC_AR7130
:
474 case AR71XX_SOC_AR7141
:
475 case AR71XX_SOC_AR7161
:
476 pll_10
= AR71XX_PLL_VAL_10
;
477 pll_100
= AR71XX_PLL_VAL_100
;
478 pll_1000
= AR71XX_PLL_VAL_1000
;
481 case AR71XX_SOC_AR7240
:
482 case AR71XX_SOC_AR7241
:
483 pll_10
= AR724X_PLL_VAL_10
;
484 pll_100
= AR724X_PLL_VAL_100
;
485 pll_1000
= AR724X_PLL_VAL_1000
;
488 case AR71XX_SOC_AR7242
:
489 pll_10
= AR7242_PLL_VAL_10
;
490 pll_100
= AR7242_PLL_VAL_100
;
491 pll_1000
= AR7242_PLL_VAL_1000
;
494 case AR71XX_SOC_AR9130
:
495 case AR71XX_SOC_AR9132
:
496 pll_10
= AR91XX_PLL_VAL_10
;
497 pll_100
= AR91XX_PLL_VAL_100
;
498 pll_1000
= AR91XX_PLL_VAL_1000
;
501 case AR71XX_SOC_AR9330
:
502 case AR71XX_SOC_AR9331
:
503 pll_10
= AR933X_PLL_VAL_10
;
504 pll_100
= AR933X_PLL_VAL_100
;
505 pll_1000
= AR933X_PLL_VAL_1000
;
508 case AR71XX_SOC_AR9341
:
509 case AR71XX_SOC_AR9342
:
510 case AR71XX_SOC_AR9344
:
511 pll_10
= AR934X_PLL_VAL_10
;
512 pll_100
= AR934X_PLL_VAL_100
;
513 pll_1000
= AR934X_PLL_VAL_1000
;
520 if (!pll_data
->pll_10
)
521 pll_data
->pll_10
= pll_10
;
523 if (!pll_data
->pll_100
)
524 pll_data
->pll_100
= pll_100
;
526 if (!pll_data
->pll_1000
)
527 pll_data
->pll_1000
= pll_1000
;
530 static int ar71xx_eth_instance __initdata
;
531 void __init
ar71xx_add_device_eth(unsigned int id
)
533 struct platform_device
*pdev
;
534 struct ag71xx_platform_data
*pdata
;
536 ar71xx_init_eth_pll_data(id
);
540 switch (ar71xx_eth0_data
.phy_if_mode
) {
541 case PHY_INTERFACE_MODE_MII
:
542 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_MII
;
544 case PHY_INTERFACE_MODE_GMII
:
545 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_GMII
;
547 case PHY_INTERFACE_MODE_RGMII
:
548 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_RGMII
;
550 case PHY_INTERFACE_MODE_RMII
:
551 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_RMII
;
554 printk(KERN_ERR
"ar71xx: invalid PHY interface mode "
558 pdev
= &ar71xx_eth0_device
;
561 switch (ar71xx_eth1_data
.phy_if_mode
) {
562 case PHY_INTERFACE_MODE_RMII
:
563 ar71xx_eth1_data
.mii_if
= MII1_CTRL_IF_RMII
;
565 case PHY_INTERFACE_MODE_RGMII
:
566 ar71xx_eth1_data
.mii_if
= MII1_CTRL_IF_RGMII
;
569 printk(KERN_ERR
"ar71xx: invalid PHY interface mode "
573 pdev
= &ar71xx_eth1_device
;
576 printk(KERN_ERR
"ar71xx: invalid ethernet id %d\n", id
);
580 pdata
= pdev
->dev
.platform_data
;
582 switch (ar71xx_soc
) {
583 case AR71XX_SOC_AR7130
:
584 pdata
->ddr_flush
= id
? ar71xx_ddr_flush_ge1
585 : ar71xx_ddr_flush_ge0
;
586 pdata
->set_pll
= id
? ar71xx_set_pll_ge1
587 : ar71xx_set_pll_ge0
;
590 case AR71XX_SOC_AR7141
:
591 case AR71XX_SOC_AR7161
:
592 pdata
->ddr_flush
= id
? ar71xx_ddr_flush_ge1
593 : ar71xx_ddr_flush_ge0
;
594 pdata
->set_pll
= id
? ar71xx_set_pll_ge1
595 : ar71xx_set_pll_ge0
;
599 case AR71XX_SOC_AR7242
:
600 ar71xx_eth0_data
.reset_bit
|= AR724X_RESET_GE0_MDIO
|
601 RESET_MODULE_GE0_PHY
;
602 ar71xx_eth1_data
.reset_bit
|= AR724X_RESET_GE1_MDIO
|
603 RESET_MODULE_GE1_PHY
;
604 pdata
->ddr_flush
= id
? ar724x_ddr_flush_ge1
605 : ar724x_ddr_flush_ge0
;
606 pdata
->set_pll
= id
? ar724x_set_pll_ge1
607 : ar7242_set_pll_ge0
;
609 pdata
->is_ar724x
= 1;
611 if (!pdata
->fifo_cfg1
)
612 pdata
->fifo_cfg1
= 0x0010ffff;
613 if (!pdata
->fifo_cfg2
)
614 pdata
->fifo_cfg2
= 0x015500aa;
615 if (!pdata
->fifo_cfg3
)
616 pdata
->fifo_cfg3
= 0x01f00140;
619 case AR71XX_SOC_AR7241
:
620 ar71xx_eth0_data
.reset_bit
|= AR724X_RESET_GE0_MDIO
;
621 ar71xx_eth1_data
.reset_bit
|= AR724X_RESET_GE1_MDIO
;
623 case AR71XX_SOC_AR7240
:
624 ar71xx_eth0_data
.reset_bit
|= RESET_MODULE_GE0_PHY
;
625 ar71xx_eth1_data
.reset_bit
|= RESET_MODULE_GE1_PHY
;
626 pdata
->ddr_flush
= id
? ar724x_ddr_flush_ge1
627 : ar724x_ddr_flush_ge0
;
628 pdata
->set_pll
= id
? ar724x_set_pll_ge1
629 : ar724x_set_pll_ge0
;
630 pdata
->is_ar724x
= 1;
631 if (ar71xx_soc
== AR71XX_SOC_AR7240
)
632 pdata
->is_ar7240
= 1;
634 if (!pdata
->fifo_cfg1
)
635 pdata
->fifo_cfg1
= 0x0010ffff;
636 if (!pdata
->fifo_cfg2
)
637 pdata
->fifo_cfg2
= 0x015500aa;
638 if (!pdata
->fifo_cfg3
)
639 pdata
->fifo_cfg3
= 0x01f00140;
642 case AR71XX_SOC_AR9130
:
643 pdata
->ddr_flush
= id
? ar91xx_ddr_flush_ge1
644 : ar91xx_ddr_flush_ge0
;
645 pdata
->set_pll
= id
? ar91xx_set_pll_ge1
646 : ar91xx_set_pll_ge0
;
647 pdata
->is_ar91xx
= 1;
650 case AR71XX_SOC_AR9132
:
651 pdata
->ddr_flush
= id
? ar91xx_ddr_flush_ge1
652 : ar91xx_ddr_flush_ge0
;
653 pdata
->set_pll
= id
? ar91xx_set_pll_ge1
654 : ar91xx_set_pll_ge0
;
655 pdata
->is_ar91xx
= 1;
659 case AR71XX_SOC_AR9330
:
660 case AR71XX_SOC_AR9331
:
661 ar71xx_eth0_data
.reset_bit
= AR933X_RESET_GE0_MAC
|
662 AR933X_RESET_GE0_MDIO
;
663 ar71xx_eth1_data
.reset_bit
= AR933X_RESET_GE1_MAC
|
664 AR933X_RESET_GE1_MDIO
;
665 pdata
->ddr_flush
= id
? ar933x_ddr_flush_ge1
666 : ar933x_ddr_flush_ge0
;
667 pdata
->set_pll
= id
? ar933x_set_pll_ge1
668 : ar933x_set_pll_ge0
;
670 pdata
->is_ar724x
= 1;
672 if (!pdata
->fifo_cfg1
)
673 pdata
->fifo_cfg1
= 0x0010ffff;
674 if (!pdata
->fifo_cfg2
)
675 pdata
->fifo_cfg2
= 0x015500aa;
676 if (!pdata
->fifo_cfg3
)
677 pdata
->fifo_cfg3
= 0x01f00140;
680 case AR71XX_SOC_AR9341
:
681 case AR71XX_SOC_AR9342
:
682 case AR71XX_SOC_AR9344
:
683 ar71xx_eth0_data
.reset_bit
= AR934X_RESET_GE0_MAC
|
684 AR934X_RESET_GE0_MDIO
;
685 ar71xx_eth1_data
.reset_bit
= AR934X_RESET_GE1_MAC
|
686 AR934X_RESET_GE1_MDIO
;
687 pdata
->ddr_flush
= id
? ar934x_ddr_flush_ge1
688 : ar934x_ddr_flush_ge0
;
689 pdata
->set_pll
= id
? ar934x_set_pll_ge1
690 : ar934x_set_pll_ge0
;
692 pdata
->is_ar724x
= 1;
694 if (!pdata
->fifo_cfg1
)
695 pdata
->fifo_cfg1
= 0x0010ffff;
696 if (!pdata
->fifo_cfg2
)
697 pdata
->fifo_cfg2
= 0x015500aa;
698 if (!pdata
->fifo_cfg3
)
699 pdata
->fifo_cfg3
= 0x01f00140;
706 switch (pdata
->phy_if_mode
) {
707 case PHY_INTERFACE_MODE_GMII
:
708 case PHY_INTERFACE_MODE_RGMII
:
709 if (!pdata
->has_gbit
) {
710 printk(KERN_ERR
"ar71xx: no gbit available on eth%d\n",
719 if (!is_valid_ether_addr(pdata
->mac_addr
)) {
720 random_ether_addr(pdata
->mac_addr
);
722 "ar71xx: using random MAC address for eth%d\n",
723 ar71xx_eth_instance
);
726 if (pdata
->mii_bus_dev
== NULL
)
727 pdata
->mii_bus_dev
= &ar71xx_mdio0_device
.dev
;
729 /* Reset the device */
730 ar71xx_device_stop(pdata
->reset_bit
);
733 ar71xx_device_start(pdata
->reset_bit
);
736 platform_device_register(pdev
);
737 ar71xx_eth_instance
++;
740 static struct resource ar71xx_spi_resources
[] = {
742 .start
= AR71XX_SPI_BASE
,
743 .end
= AR71XX_SPI_BASE
+ AR71XX_SPI_SIZE
- 1,
744 .flags
= IORESOURCE_MEM
,
748 static struct platform_device ar71xx_spi_device
= {
749 .name
= "ar71xx-spi",
751 .resource
= ar71xx_spi_resources
,
752 .num_resources
= ARRAY_SIZE(ar71xx_spi_resources
),
755 void __init
ar71xx_add_device_spi(struct ar71xx_spi_platform_data
*pdata
,
756 struct spi_board_info
const *info
,
759 spi_register_board_info(info
, n
);
760 ar71xx_spi_device
.dev
.platform_data
= pdata
;
761 platform_device_register(&ar71xx_spi_device
);
764 void __init
ar71xx_add_device_wdt(void)
766 platform_device_register_simple("ar71xx-wdt", -1, NULL
, 0);
769 void __init
ar71xx_set_mac_base(unsigned char *mac
)
771 memcpy(ar71xx_mac_base
, mac
, ETH_ALEN
);
774 void __init
ar71xx_parse_mac_addr(char *mac_str
)
779 t
= sscanf(mac_str
, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
780 &tmp
[0], &tmp
[1], &tmp
[2], &tmp
[3], &tmp
[4], &tmp
[5]);
783 t
= sscanf(mac_str
, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
784 &tmp
[0], &tmp
[1], &tmp
[2], &tmp
[3], &tmp
[4], &tmp
[5]);
787 ar71xx_set_mac_base(tmp
);
789 printk(KERN_DEBUG
"ar71xx: failed to parse mac address "
790 "\"%s\"\n", mac_str
);
793 static int __init
ar71xx_ethaddr_setup(char *str
)
795 ar71xx_parse_mac_addr(str
);
798 __setup("ethaddr=", ar71xx_ethaddr_setup
);
800 static int __init
ar71xx_kmac_setup(char *str
)
802 ar71xx_parse_mac_addr(str
);
805 __setup("kmac=", ar71xx_kmac_setup
);
807 void __init
ar71xx_init_mac(unsigned char *dst
, const unsigned char *src
,
812 if (!is_valid_ether_addr(src
)) {
813 memset(dst
, '\0', ETH_ALEN
);
817 t
= (((u32
) src
[3]) << 16) + (((u32
) src
[4]) << 8) + ((u32
) src
[5]);
823 dst
[3] = (t
>> 16) & 0xff;
824 dst
[4] = (t
>> 8) & 0xff;