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[openwrt.git] / target / linux / ar7 / files / drivers / net / cpmac.c
1 /*
2 * Copyright (C) 2006, 2007 OpenWrt.org
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/moduleparam.h>
22
23 #include <linux/sched.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/errno.h>
27 #include <linux/types.h>
28 #include <linux/delay.h>
29 #include <linux/version.h>
30
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/skbuff.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/platform_device.h>
38 #include <linux/dma-mapping.h>
39 #include <asm/gpio.h>
40
41 MODULE_AUTHOR("Eugene Konev");
42 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
43 MODULE_LICENSE("GPL");
44
45 static int disable_napi;
46 static int debug_level = 8;
47 static int dumb_switch;
48
49 module_param(disable_napi, int, 0644);
50 /* Next 2 are only used in cpmac_probe, so it's pointless to change them */
51 module_param(debug_level, int, 0444);
52 module_param(dumb_switch, int, 0444);
53
54 MODULE_PARM_DESC(disable_napi, "Disable NAPI polling");
55 MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
56 MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
57
58 /* stolen from net/ieee80211.h */
59 #ifndef MAC_FMT
60 #define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
61 #define MAC_ARG(x) ((u8*)(x))[0], ((u8*)(x))[1], ((u8*)(x))[2], \
62 ((u8*)(x))[3], ((u8*)(x))[4], ((u8*)(x))[5]
63 #endif
64 /* frame size + 802.1q tag */
65 #define CPMAC_SKB_SIZE (ETH_FRAME_LEN + 4)
66 #define CPMAC_TX_RING_SIZE 8
67
68 /* Ethernet registers */
69 #define CPMAC_TX_CONTROL 0x0004
70 #define CPMAC_TX_TEARDOWN 0x0008
71 #define CPMAC_RX_CONTROL 0x0014
72 #define CPMAC_RX_TEARDOWN 0x0018
73 #define CPMAC_MBP 0x0100
74 # define MBP_RXPASSCRC 0x40000000
75 # define MBP_RXQOS 0x20000000
76 # define MBP_RXNOCHAIN 0x10000000
77 # define MBP_RXCMF 0x01000000
78 # define MBP_RXSHORT 0x00800000
79 # define MBP_RXCEF 0x00400000
80 # define MBP_RXPROMISC 0x00200000
81 # define MBP_PROMISCCHAN(channel) (((channel) & 0x7) << 16)
82 # define MBP_RXBCAST 0x00002000
83 # define MBP_BCASTCHAN(channel) (((channel) & 0x7) << 8)
84 # define MBP_RXMCAST 0x00000020
85 # define MBP_MCASTCHAN(channel) ((channel) & 0x7)
86 #define CPMAC_UNICAST_ENABLE 0x0104
87 #define CPMAC_UNICAST_CLEAR 0x0108
88 #define CPMAC_MAX_LENGTH 0x010c
89 #define CPMAC_BUFFER_OFFSET 0x0110
90 #define CPMAC_MAC_CONTROL 0x0160
91 # define MAC_TXPTYPE 0x00000200
92 # define MAC_TXPACE 0x00000040
93 # define MAC_MII 0x00000020
94 # define MAC_TXFLOW 0x00000010
95 # define MAC_RXFLOW 0x00000008
96 # define MAC_MTEST 0x00000004
97 # define MAC_LOOPBACK 0x00000002
98 # define MAC_FDX 0x00000001
99 #define CPMAC_MAC_STATUS 0x0164
100 # define MAC_STATUS_QOS 0x00000004
101 # define MAC_STATUS_RXFLOW 0x00000002
102 # define MAC_STATUS_TXFLOW 0x00000001
103 #define CPMAC_TX_INT_ENABLE 0x0178
104 #define CPMAC_TX_INT_CLEAR 0x017c
105 #define CPMAC_MAC_INT_VECTOR 0x0180
106 # define MAC_INT_STATUS 0x00080000
107 # define MAC_INT_HOST 0x00040000
108 # define MAC_INT_RX 0x00020000
109 # define MAC_INT_TX 0x00010000
110 #define CPMAC_MAC_EOI_VECTOR 0x0184
111 #define CPMAC_RX_INT_ENABLE 0x0198
112 #define CPMAC_RX_INT_CLEAR 0x019c
113 #define CPMAC_MAC_INT_ENABLE 0x01a8
114 #define CPMAC_MAC_INT_CLEAR 0x01ac
115 #define CPMAC_MAC_ADDR_LO(channel) (0x01b0 + (channel) * 4)
116 #define CPMAC_MAC_ADDR_MID 0x01d0
117 #define CPMAC_MAC_ADDR_HI 0x01d4
118 #define CPMAC_MAC_HASH_LO 0x01d8
119 #define CPMAC_MAC_HASH_HI 0x01dc
120 #define CPMAC_TX_PTR(channel) (0x0600 + (channel) * 4)
121 #define CPMAC_RX_PTR(channel) (0x0620 + (channel) * 4)
122 #define CPMAC_TX_ACK(channel) (0x0640 + (channel) * 4)
123 #define CPMAC_RX_ACK(channel) (0x0660 + (channel) * 4)
124 #define CPMAC_REG_END 0x0680
125 /*
126 * Rx/Tx statistics
127 * TODO: use some of them to fill stats in cpmac_stats()
128 */
129 #define CPMAC_STATS_RX_GOOD 0x0200
130 #define CPMAC_STATS_RX_BCAST 0x0204
131 #define CPMAC_STATS_RX_MCAST 0x0208
132 #define CPMAC_STATS_RX_PAUSE 0x020c
133 #define CPMAC_STATS_RX_CRC 0x0210
134 #define CPMAC_STATS_RX_ALIGN 0x0214
135 #define CPMAC_STATS_RX_OVER 0x0218
136 #define CPMAC_STATS_RX_JABBER 0x021c
137 #define CPMAC_STATS_RX_UNDER 0x0220
138 #define CPMAC_STATS_RX_FRAG 0x0224
139 #define CPMAC_STATS_RX_FILTER 0x0228
140 #define CPMAC_STATS_RX_QOSFILTER 0x022c
141 #define CPMAC_STATS_RX_OCTETS 0x0230
142
143 #define CPMAC_STATS_TX_GOOD 0x0234
144 #define CPMAC_STATS_TX_BCAST 0x0238
145 #define CPMAC_STATS_TX_MCAST 0x023c
146 #define CPMAC_STATS_TX_PAUSE 0x0240
147 #define CPMAC_STATS_TX_DEFER 0x0244
148 #define CPMAC_STATS_TX_COLLISION 0x0248
149 #define CPMAC_STATS_TX_SINGLECOLL 0x024c
150 #define CPMAC_STATS_TX_MULTICOLL 0x0250
151 #define CPMAC_STATS_TX_EXCESSCOLL 0x0254
152 #define CPMAC_STATS_TX_LATECOLL 0x0258
153 #define CPMAC_STATS_TX_UNDERRUN 0x025c
154 #define CPMAC_STATS_TX_CARRIERSENSE 0x0260
155 #define CPMAC_STATS_TX_OCTETS 0x0264
156
157 #define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg)))
158 #define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \
159 (reg)))
160
161 /* MDIO bus */
162 #define CPMAC_MDIO_VERSION 0x0000
163 #define CPMAC_MDIO_CONTROL 0x0004
164 # define MDIOC_IDLE 0x80000000
165 # define MDIOC_ENABLE 0x40000000
166 # define MDIOC_PREAMBLE 0x00100000
167 # define MDIOC_FAULT 0x00080000
168 # define MDIOC_FAULTDETECT 0x00040000
169 # define MDIOC_INTTEST 0x00020000
170 # define MDIOC_CLKDIV(div) ((div) & 0xff)
171 #define CPMAC_MDIO_ALIVE 0x0008
172 #define CPMAC_MDIO_LINK 0x000c
173 #define CPMAC_MDIO_ACCESS(channel) (0x0080 + (channel) * 8)
174 # define MDIO_BUSY 0x80000000
175 # define MDIO_WRITE 0x40000000
176 # define MDIO_REG(reg) (((reg) & 0x1f) << 21)
177 # define MDIO_PHY(phy) (((phy) & 0x1f) << 16)
178 # define MDIO_DATA(data) ((data) & 0xffff)
179 #define CPMAC_MDIO_PHYSEL(channel) (0x0084 + (channel) * 8)
180 # define PHYSEL_LINKSEL 0x00000040
181 # define PHYSEL_LINKINT 0x00000020
182
183 struct cpmac_desc {
184 u32 hw_next;
185 u32 hw_data;
186 u16 buflen;
187 u16 bufflags;
188 u16 datalen;
189 u16 dataflags;
190 #define CPMAC_SOP 0x8000
191 #define CPMAC_EOP 0x4000
192 #define CPMAC_OWN 0x2000
193 #define CPMAC_EOQ 0x1000
194 struct sk_buff *skb;
195 struct cpmac_desc *next;
196 dma_addr_t mapping;
197 dma_addr_t data_mapping;
198 };
199
200 struct cpmac_priv {
201 spinlock_t lock;
202 struct cpmac_desc *rx_head;
203 int tx_head, tx_tail;
204 int ring_size;
205 struct cpmac_desc *desc_ring;
206 dma_addr_t dma_ring;
207 void __iomem *regs;
208 struct mii_bus *mii_bus;
209 struct phy_device *phy;
210 char phy_name[BUS_ID_SIZE];
211 int oldlink, oldspeed, oldduplex;
212 u32 msg_enable;
213 struct platform_device *pdev;
214 };
215
216 static irqreturn_t cpmac_irq(int, void *);
217 static void cpmac_reset(struct net_device *dev);
218 static void cpmac_hw_init(struct net_device *dev);
219 static int cpmac_stop(struct net_device *dev);
220 static int cpmac_open(struct net_device *dev);
221
222 static void cpmac_dump_regs(struct net_device *dev)
223 {
224 int i;
225 struct cpmac_priv *priv = netdev_priv(dev);
226 for (i = 0; i < CPMAC_REG_END; i += 4) {
227 if (i % 16 == 0) {
228 if (i)
229 printk("\n");
230 printk(KERN_DEBUG "%s: reg[%p]:", dev->name,
231 priv->regs + i);
232 }
233 printk(" %08x", cpmac_read(priv->regs, i));
234 }
235 printk("\n");
236 }
237
238 static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
239 {
240 int i;
241 printk(KERN_DEBUG "%s: desc[%p]:", dev->name, desc);
242 for (i = 0; i < sizeof(*desc) / 4; i++)
243 printk(" %08x", ((u32 *)desc)[i]);
244 printk("\n");
245 }
246
247 static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
248 {
249 int i;
250 printk(KERN_DEBUG "%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
251 for (i = 0; i < skb->len; i++) {
252 if (i % 16 == 0) {
253 if (i)
254 printk("\n");
255 printk(KERN_DEBUG "%s: data[%p]:", dev->name,
256 skb->data + i);
257 }
258 printk(" %02x", ((u8 *)skb->data)[i]);
259 }
260 printk("\n");
261 }
262
263 static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
264 {
265 u32 val;
266
267 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
268 cpu_relax();
269 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
270 MDIO_PHY(phy_id));
271 while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
272 cpu_relax();
273 return MDIO_DATA(val);
274 }
275
276 static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
277 int reg, u16 val)
278 {
279 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
280 cpu_relax();
281 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
282 MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
283 return 0;
284 }
285
286 static int cpmac_mdio_reset(struct mii_bus *bus)
287 {
288 ar7_device_reset(AR7_RESET_BIT_MDIO);
289 cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
290 MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1));
291 return 0;
292 }
293
294 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
295
296 static struct mii_bus cpmac_mii = {
297 .name = "cpmac-mii",
298 .read = cpmac_mdio_read,
299 .write = cpmac_mdio_write,
300 .reset = cpmac_mdio_reset,
301 .irq = mii_irqs,
302 };
303
304 static int cpmac_config(struct net_device *dev, struct ifmap *map)
305 {
306 if (dev->flags & IFF_UP)
307 return -EBUSY;
308
309 /* Don't allow changing the I/O address */
310 if (map->base_addr != dev->base_addr)
311 return -EOPNOTSUPP;
312
313 /* ignore other fields */
314 return 0;
315 }
316
317 static void cpmac_set_multicast_list(struct net_device *dev)
318 {
319 struct dev_mc_list *iter;
320 int i;
321 u8 tmp;
322 u32 mbp, bit, hash[2] = { 0, };
323 struct cpmac_priv *priv = netdev_priv(dev);
324
325 mbp = cpmac_read(priv->regs, CPMAC_MBP);
326 if (dev->flags & IFF_PROMISC) {
327 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
328 MBP_RXPROMISC);
329 } else {
330 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
331 if (dev->flags & IFF_ALLMULTI) {
332 /* enable all multicast mode */
333 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
334 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
335 } else {
336 /*
337 * cpmac uses some strange mac address hashing
338 * (not crc32)
339 */
340 for (i = 0, iter = dev->mc_list; i < dev->mc_count;
341 i++, iter = iter->next) {
342 bit = 0;
343 tmp = iter->dmi_addr[0];
344 bit ^= (tmp >> 2) ^ (tmp << 4);
345 tmp = iter->dmi_addr[1];
346 bit ^= (tmp >> 4) ^ (tmp << 2);
347 tmp = iter->dmi_addr[2];
348 bit ^= (tmp >> 6) ^ tmp;
349 tmp = iter->dmi_addr[3];
350 bit ^= (tmp >> 2) ^ (tmp << 4);
351 tmp = iter->dmi_addr[4];
352 bit ^= (tmp >> 4) ^ (tmp << 2);
353 tmp = iter->dmi_addr[5];
354 bit ^= (tmp >> 6) ^ tmp;
355 bit &= 0x3f;
356 hash[bit / 32] |= 1 << (bit % 32);
357 }
358
359 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
360 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
361 }
362 }
363 }
364
365 static struct sk_buff *cpmac_rx_one(struct net_device *dev,
366 struct cpmac_priv *priv,
367 struct cpmac_desc *desc)
368 {
369 unsigned long flags;
370 struct sk_buff *skb, *result = NULL;
371
372 if (unlikely(netif_msg_hw(priv)))
373 cpmac_dump_desc(dev, desc);
374 cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
375 if (unlikely(!desc->datalen)) {
376 if (netif_msg_rx_err(priv) && net_ratelimit())
377 printk(KERN_WARNING "%s: rx: spurious interrupt\n",
378 dev->name);
379 return NULL;
380 }
381
382 skb = netdev_alloc_skb(dev, CPMAC_SKB_SIZE);
383 spin_lock_irqsave(&priv->lock, flags);
384 if (likely(skb)) {
385 skb_reserve(skb, 2);
386 skb_put(desc->skb, desc->datalen);
387 desc->skb->protocol = eth_type_trans(desc->skb, dev);
388 desc->skb->ip_summed = CHECKSUM_NONE;
389 dev->stats.rx_packets++;
390 dev->stats.rx_bytes += desc->datalen;
391 result = desc->skb;
392 dma_unmap_single(&dev->dev, desc->data_mapping, CPMAC_SKB_SIZE,
393 DMA_FROM_DEVICE);
394 desc->skb = skb;
395 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
396 CPMAC_SKB_SIZE,
397 DMA_FROM_DEVICE);
398 desc->hw_data = (u32)desc->data_mapping;
399 if (unlikely(netif_msg_pktdata(priv))) {
400 printk(KERN_DEBUG "%s: received packet:\n", dev->name);
401 cpmac_dump_skb(dev, result);
402 }
403 } else {
404 if (netif_msg_rx_err(priv) && net_ratelimit())
405 printk(KERN_WARNING
406 "%s: low on skbs, dropping packet\n", dev->name);
407 dev->stats.rx_dropped++;
408 }
409 spin_unlock_irqrestore(&priv->lock, flags);
410
411 desc->buflen = CPMAC_SKB_SIZE;
412 desc->dataflags = CPMAC_OWN;
413
414 return result;
415 }
416
417 static void cpmac_rx(struct net_device *dev)
418 {
419 struct sk_buff *skb;
420 struct cpmac_desc *desc;
421 struct cpmac_priv *priv = netdev_priv(dev);
422
423 spin_lock(&priv->lock);
424 if (unlikely(!priv->rx_head)) {
425 spin_unlock(&priv->lock);
426 return;
427 }
428
429 desc = priv->rx_head;
430
431 while ((desc->dataflags & CPMAC_OWN) == 0) {
432 skb = cpmac_rx_one(dev, priv, desc);
433 if (likely(skb))
434 netif_rx(skb);
435 desc = desc->next;
436 }
437
438 priv->rx_head = desc;
439 cpmac_write(priv->regs, CPMAC_RX_PTR(0), (u32)desc->mapping);
440 spin_unlock(&priv->lock);
441 }
442
443 static int cpmac_poll(struct net_device *dev, int *budget)
444 {
445 struct sk_buff *skb;
446 struct cpmac_desc *desc;
447 int received = 0, quota = min(dev->quota, *budget);
448 struct cpmac_priv *priv = netdev_priv(dev);
449
450 if (unlikely(!priv->rx_head)) {
451 if (netif_msg_rx_err(priv) && net_ratelimit())
452 printk(KERN_WARNING "%s: rx: polling, but no queue\n",
453 dev->name);
454 netif_rx_complete(dev);
455 return 0;
456 }
457
458 desc = priv->rx_head;
459
460 while ((received < quota) && ((desc->dataflags & CPMAC_OWN) == 0)) {
461 skb = cpmac_rx_one(dev, priv, desc);
462 if (likely(skb)) {
463 netif_receive_skb(skb);
464 received++;
465 }
466 desc = desc->next;
467 }
468
469 priv->rx_head = desc;
470 *budget -= received;
471 dev->quota -= received;
472 if (unlikely(netif_msg_rx_status(priv)))
473 printk(KERN_DEBUG "%s: poll processed %d packets\n", dev->name,
474 received);
475 if (desc->dataflags & CPMAC_OWN) {
476 netif_rx_complete(dev);
477 cpmac_write(priv->regs, CPMAC_RX_PTR(0), (u32)desc->mapping);
478 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
479 return 0;
480 }
481
482 return 1;
483 }
484
485 static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
486 {
487 unsigned long flags;
488 int channel, len;
489 struct cpmac_desc *desc;
490 struct cpmac_priv *priv = netdev_priv(dev);
491
492 if (unlikely(skb_padto(skb, ETH_ZLEN))) {
493 if (netif_msg_tx_err(priv) && net_ratelimit())
494 printk(KERN_WARNING"%s: tx: padding failed, dropping\n",
495 dev->name);
496 spin_lock_irqsave(&priv->lock, flags);
497 dev->stats.tx_dropped++;
498 spin_unlock_irqrestore(&priv->lock, flags);
499 return -ENOMEM;
500 }
501
502 len = max(skb->len, ETH_ZLEN);
503 spin_lock_irqsave(&priv->lock, flags);
504 channel = priv->tx_tail++;
505 priv->tx_tail %= CPMAC_TX_RING_SIZE;
506 if (priv->tx_tail == priv->tx_head)
507 netif_stop_queue(dev);
508
509 desc = &priv->desc_ring[channel];
510 if (desc->dataflags & CPMAC_OWN) {
511 if (netif_msg_tx_err(priv) && net_ratelimit())
512 printk(KERN_WARNING "%s: tx dma ring full, dropping\n",
513 dev->name);
514 dev->stats.tx_dropped++;
515 spin_unlock_irqrestore(&priv->lock, flags);
516 dev_kfree_skb_any(skb);
517 return -ENOMEM;
518 }
519
520 dev->trans_start = jiffies;
521 spin_unlock_irqrestore(&priv->lock, flags);
522 desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
523 desc->skb = skb;
524 desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
525 DMA_TO_DEVICE);
526 desc->hw_data = (u32)desc->data_mapping;
527 desc->datalen = len;
528 desc->buflen = len;
529 if (unlikely(netif_msg_tx_queued(priv)))
530 printk(KERN_DEBUG "%s: sending 0x%p, len=%d\n", dev->name, skb,
531 skb->len);
532 if (unlikely(netif_msg_hw(priv)))
533 cpmac_dump_desc(dev, desc);
534 if (unlikely(netif_msg_pktdata(priv)))
535 cpmac_dump_skb(dev, skb);
536 cpmac_write(priv->regs, CPMAC_TX_PTR(channel), (u32)desc->mapping);
537
538 return 0;
539 }
540
541 static void cpmac_end_xmit(struct net_device *dev, int channel)
542 {
543 struct cpmac_desc *desc;
544 struct cpmac_priv *priv = netdev_priv(dev);
545
546 spin_lock(&priv->lock);
547 desc = &priv->desc_ring[channel];
548 cpmac_write(priv->regs, CPMAC_TX_ACK(channel), (u32)desc->mapping);
549 if (likely(desc->skb)) {
550 dev->stats.tx_packets++;
551 dev->stats.tx_bytes += desc->skb->len;
552 dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
553 DMA_TO_DEVICE);
554
555 if (unlikely(netif_msg_tx_done(priv)))
556 printk(KERN_DEBUG "%s: sent 0x%p, len=%d\n", dev->name,
557 desc->skb, desc->skb->len);
558
559 dev_kfree_skb_irq(desc->skb);
560 if (netif_queue_stopped(dev))
561 netif_wake_queue(dev);
562 } else
563 if (netif_msg_tx_err(priv) && net_ratelimit())
564 printk(KERN_WARNING
565 "%s: end_xmit: spurious interrupt\n", dev->name);
566 spin_unlock(&priv->lock);
567 }
568
569 static void cpmac_reset(struct net_device *dev)
570 {
571 int i;
572 struct cpmac_priv *priv = netdev_priv(dev);
573 struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
574
575 ar7_device_reset(pdata->reset_bit);
576 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
577 cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
578 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
579 cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
580 for (i = 0; i < 8; i++) {
581 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
582 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
583 }
584 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
585 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
586 }
587
588 static inline void cpmac_free_rx_ring(struct net_device *dev)
589 {
590 struct cpmac_desc *desc;
591 int i;
592 struct cpmac_priv *priv = netdev_priv(dev);
593
594 if (unlikely(!priv->rx_head))
595 return;
596
597 desc = priv->rx_head;
598
599 for (i = 0; i < priv->ring_size; i++) {
600 desc->buflen = CPMAC_SKB_SIZE;
601 if ((desc->dataflags & CPMAC_OWN) == 0) {
602 if (netif_msg_rx_err(priv) && net_ratelimit())
603 printk(KERN_WARNING "%s: packet dropped\n",
604 dev->name);
605 if (unlikely(netif_msg_hw(priv)))
606 cpmac_dump_desc(dev, desc);
607 desc->dataflags = CPMAC_OWN;
608 dev->stats.rx_dropped++;
609 }
610 desc = desc->next;
611 }
612 }
613
614 static irqreturn_t cpmac_irq(int irq, void *dev_id)
615 {
616 struct net_device *dev = dev_id;
617 struct cpmac_priv *priv;
618 u32 status;
619
620 if (!dev)
621 return IRQ_NONE;
622
623 priv = netdev_priv(dev);
624
625 status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
626
627 if (unlikely(netif_msg_intr(priv)))
628 printk(KERN_DEBUG "%s: interrupt status: 0x%08x\n", dev->name,
629 status);
630
631 if (status & MAC_INT_TX)
632 cpmac_end_xmit(dev, (status & 7));
633
634 if (status & MAC_INT_RX) {
635 if (disable_napi)
636 cpmac_rx(dev);
637 else {
638 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1);
639 netif_rx_schedule(dev);
640 }
641 }
642
643 cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
644
645 if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS))) {
646 if (netif_msg_drv(priv) && net_ratelimit())
647 printk(KERN_ERR "%s: hw error, resetting...\n",
648 dev->name);
649 if (unlikely(netif_msg_hw(priv)))
650 cpmac_dump_regs(dev);
651 spin_lock(&priv->lock);
652 phy_stop(priv->phy);
653 cpmac_reset(dev);
654 cpmac_free_rx_ring(dev);
655 cpmac_hw_init(dev);
656 spin_unlock(&priv->lock);
657 }
658
659 return IRQ_HANDLED;
660 }
661
662 static void cpmac_tx_timeout(struct net_device *dev)
663 {
664 struct cpmac_priv *priv = netdev_priv(dev);
665 struct cpmac_desc *desc;
666
667 dev->stats.tx_errors++;
668 desc = &priv->desc_ring[priv->tx_head++];
669 priv->tx_head %= 8;
670 if (netif_msg_tx_err(priv) && net_ratelimit())
671 printk(KERN_WARNING "%s: transmit timeout\n", dev->name);
672 if (desc->skb)
673 dev_kfree_skb_any(desc->skb);
674 netif_wake_queue(dev);
675 }
676
677 static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
678 {
679 struct cpmac_priv *priv = netdev_priv(dev);
680 if (!(netif_running(dev)))
681 return -EINVAL;
682 if (!priv->phy)
683 return -EINVAL;
684 if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) ||
685 (cmd == SIOCSMIIREG))
686 return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd);
687
688 return -EINVAL;
689 }
690
691 static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
692 {
693 struct cpmac_priv *priv = netdev_priv(dev);
694
695 if (priv->phy)
696 return phy_ethtool_gset(priv->phy, cmd);
697
698 return -EINVAL;
699 }
700
701 static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
702 {
703 struct cpmac_priv *priv = netdev_priv(dev);
704
705 if (!capable(CAP_NET_ADMIN))
706 return -EPERM;
707
708 if (priv->phy)
709 return phy_ethtool_sset(priv->phy, cmd);
710
711 return -EINVAL;
712 }
713
714 static void cpmac_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
715 {
716 struct cpmac_priv *priv = netdev_priv(dev);
717
718 ring->rx_max_pending = 1024;
719 ring->rx_mini_max_pending = 1;
720 ring->rx_jumbo_max_pending = 1;
721 ring->tx_max_pending = 1;
722
723 ring->rx_pending = priv->ring_size;
724 ring->rx_mini_pending = 1;
725 ring->rx_jumbo_pending = 1;
726 ring->tx_pending = 1;
727 }
728
729 static int cpmac_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
730 {
731 struct cpmac_priv *priv = netdev_priv(dev);
732
733 if (dev->flags && IFF_UP)
734 return -EBUSY;
735 priv->ring_size = ring->rx_pending;
736 return 0;
737 }
738
739 static void cpmac_get_drvinfo(struct net_device *dev,
740 struct ethtool_drvinfo *info)
741 {
742 strcpy(info->driver, "cpmac");
743 strcpy(info->version, "0.0.3");
744 info->fw_version[0] = '\0';
745 sprintf(info->bus_info, "%s", "cpmac");
746 info->regdump_len = 0;
747 }
748
749 static const struct ethtool_ops cpmac_ethtool_ops = {
750 .get_settings = cpmac_get_settings,
751 .set_settings = cpmac_set_settings,
752 .get_drvinfo = cpmac_get_drvinfo,
753 .get_link = ethtool_op_get_link,
754 .get_ringparam = cpmac_get_ringparam,
755 .set_ringparam = cpmac_set_ringparam,
756 };
757
758 static void cpmac_adjust_link(struct net_device *dev)
759 {
760 struct cpmac_priv *priv = netdev_priv(dev);
761 unsigned long flags;
762 int new_state = 0;
763
764 spin_lock_irqsave(&priv->lock, flags);
765 if (priv->phy->link) {
766 if (priv->phy->duplex != priv->oldduplex) {
767 new_state = 1;
768 priv->oldduplex = priv->phy->duplex;
769 }
770
771 if (priv->phy->speed != priv->oldspeed) {
772 new_state = 1;
773 priv->oldspeed = priv->phy->speed;
774 }
775
776 if (!priv->oldlink) {
777 new_state = 1;
778 priv->oldlink = 1;
779 netif_schedule(dev);
780 }
781 } else if (priv->oldlink) {
782 new_state = 1;
783 priv->oldlink = 0;
784 priv->oldspeed = 0;
785 priv->oldduplex = -1;
786 }
787
788 if (new_state && netif_msg_link(priv) && net_ratelimit())
789 phy_print_status(priv->phy);
790
791 spin_unlock_irqrestore(&priv->lock, flags);
792 }
793
794 static void cpmac_hw_init(struct net_device *dev)
795 {
796 int i;
797 struct cpmac_priv *priv = netdev_priv(dev);
798
799 for (i = 0; i < 8; i++) {
800 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
801 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
802 }
803 cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
804
805 cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
806 MBP_RXMCAST);
807 cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
808 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xfe);
809 cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
810 for (i = 0; i < 8; i++)
811 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
812 cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
813 cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
814 (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
815 (dev->dev_addr[3] << 24));
816 cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
817 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
818 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
819 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
820 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
821 cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
822 cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
823
824 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
825 cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
826 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
827 cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
828 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
829 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
830 MAC_FDX);
831
832 priv->phy->state = PHY_CHANGELINK;
833 phy_start(priv->phy);
834 }
835
836 static int cpmac_open(struct net_device *dev)
837 {
838 int i, size, res;
839 struct cpmac_priv *priv = netdev_priv(dev);
840 struct resource *mem;
841 struct cpmac_desc *desc;
842 struct sk_buff *skb;
843
844 priv->phy = phy_connect(dev, priv->phy_name, &cpmac_adjust_link,
845 0, PHY_INTERFACE_MODE_MII);
846 if (IS_ERR(priv->phy)) {
847 if (netif_msg_drv(priv))
848 printk(KERN_ERR "%s: Could not attach to PHY\n",
849 dev->name);
850 return PTR_ERR(priv->phy);
851 }
852
853 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
854 if (!request_mem_region(mem->start, mem->end - mem->start, dev->name)) {
855 if (netif_msg_drv(priv))
856 printk(KERN_ERR "%s: failed to request registers\n",
857 dev->name);
858 res = -ENXIO;
859 goto fail_reserve;
860 }
861
862 priv->regs = ioremap(mem->start, mem->end - mem->start);
863 if (!priv->regs) {
864 if (netif_msg_drv(priv))
865 printk(KERN_ERR "%s: failed to remap registers\n",
866 dev->name);
867 res = -ENXIO;
868 goto fail_remap;
869 }
870
871 priv->rx_head = NULL;
872 size = priv->ring_size + CPMAC_TX_RING_SIZE;
873 priv->desc_ring = dma_alloc_coherent(&dev->dev,
874 sizeof(struct cpmac_desc) * size,
875 &priv->dma_ring,
876 GFP_KERNEL);
877 if (!priv->desc_ring) {
878 res = -ENOMEM;
879 goto fail_alloc;
880 }
881
882 priv->rx_head = &priv->desc_ring[CPMAC_TX_RING_SIZE];
883 for (i = 0; i < size; i++)
884 priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
885
886 for (i = 0, desc = &priv->rx_head[i]; i < priv->ring_size; i++, desc++) {
887 skb = netdev_alloc_skb(dev, CPMAC_SKB_SIZE);
888 if (unlikely(!skb)) {
889 res = -ENOMEM;
890 goto fail_desc;
891 }
892 skb_reserve(skb, 2);
893 desc->skb = skb;
894 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
895 CPMAC_SKB_SIZE,
896 DMA_FROM_DEVICE);
897 desc->hw_data = (u32)desc->data_mapping;
898 desc->buflen = CPMAC_SKB_SIZE;
899 desc->dataflags = CPMAC_OWN;
900 desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
901 desc->hw_next = (u32)desc->next->mapping;
902 }
903
904 if ((res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED,
905 dev->name, dev))) {
906 if (netif_msg_drv(priv))
907 printk(KERN_ERR "%s: failed to obtain irq\n",
908 dev->name);
909 goto fail_irq;
910 }
911
912 cpmac_reset(dev);
913 cpmac_hw_init(dev);
914
915 netif_start_queue(dev);
916 return 0;
917
918 fail_irq:
919 fail_desc:
920 for (i = 0; i < priv->ring_size; i++) {
921 if (priv->rx_head[i].skb) {
922 kfree_skb(priv->rx_head[i].skb);
923 dma_unmap_single(&dev->dev,
924 priv->rx_head[i].data_mapping,
925 CPMAC_SKB_SIZE,
926 DMA_FROM_DEVICE);
927 }
928 }
929 fail_alloc:
930 kfree(priv->desc_ring);
931 iounmap(priv->regs);
932
933 fail_remap:
934 release_mem_region(mem->start, mem->end - mem->start);
935
936 fail_reserve:
937 phy_disconnect(priv->phy);
938
939 return res;
940 }
941
942 static int cpmac_stop(struct net_device *dev)
943 {
944 int i;
945 struct cpmac_priv *priv = netdev_priv(dev);
946 struct resource *mem;
947
948 netif_stop_queue(dev);
949
950 phy_stop(priv->phy);
951 phy_disconnect(priv->phy);
952 priv->phy = NULL;
953
954 cpmac_reset(dev);
955
956 for (i = 0; i < 8; i++)
957 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
958 cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
959 cpmac_write(priv->regs, CPMAC_MBP, 0);
960
961 free_irq(dev->irq, dev);
962 iounmap(priv->regs);
963 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
964 release_mem_region(mem->start, mem->end - mem->start);
965 priv->rx_head = &priv->desc_ring[CPMAC_TX_RING_SIZE];
966 for (i = 0; i < priv->ring_size; i++) {
967 if (priv->rx_head[i].skb) {
968 kfree_skb(priv->rx_head[i].skb);
969 dma_unmap_single(&dev->dev,
970 priv->rx_head[i].data_mapping,
971 CPMAC_SKB_SIZE,
972 DMA_FROM_DEVICE);
973 }
974 }
975
976 dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
977 (CPMAC_TX_RING_SIZE + priv->ring_size),
978 priv->desc_ring, priv->dma_ring);
979 return 0;
980 }
981
982 static int external_switch;
983
984 static int __devinit cpmac_probe(struct platform_device *pdev)
985 {
986 int rc, phy_id;
987 struct resource *mem;
988 struct cpmac_priv *priv;
989 struct net_device *dev;
990 struct plat_cpmac_data *pdata;
991
992 pdata = pdev->dev.platform_data;
993
994 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
995 if (!(pdata->phy_mask & (1 << phy_id)))
996 continue;
997 if (!cpmac_mii.phy_map[phy_id])
998 continue;
999 break;
1000 }
1001
1002 if (phy_id == PHY_MAX_ADDR) {
1003 if (external_switch || dumb_switch)
1004 phy_id = 0;
1005 else {
1006 printk(KERN_ERR "cpmac: no PHY present\n");
1007 return -ENODEV;
1008 }
1009 }
1010
1011 dev = alloc_etherdev(sizeof(struct cpmac_priv));
1012
1013 if (!dev) {
1014 printk(KERN_ERR "cpmac: Unable to allocate net_device\n");
1015 return -ENOMEM;
1016 }
1017
1018 platform_set_drvdata(pdev, dev);
1019 priv = netdev_priv(dev);
1020
1021 priv->pdev = pdev;
1022 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1023 if (!mem) {
1024 rc = -ENODEV;
1025 goto fail;
1026 }
1027
1028 dev->irq = platform_get_irq_byname(pdev, "irq");
1029
1030 dev->open = cpmac_open;
1031 dev->stop = cpmac_stop;
1032 dev->set_config = cpmac_config;
1033 dev->hard_start_xmit = cpmac_start_xmit;
1034 dev->do_ioctl = cpmac_ioctl;
1035 dev->set_multicast_list = cpmac_set_multicast_list;
1036 dev->tx_timeout = cpmac_tx_timeout;
1037 dev->ethtool_ops = &cpmac_ethtool_ops;
1038 if (!disable_napi) {
1039 dev->poll = cpmac_poll;
1040 dev->weight = 64;
1041 }
1042
1043 spin_lock_init(&priv->lock);
1044 priv->msg_enable = netif_msg_init(debug_level, 0xff);
1045 priv->ring_size = 64;
1046 memcpy(dev->dev_addr, pdata->dev_addr, sizeof(dev->dev_addr));
1047 if (phy_id == 31) {
1048 snprintf(priv->phy_name, BUS_ID_SIZE, PHY_ID_FMT,
1049 cpmac_mii.id, phy_id);
1050 /* cpmac_write(cpmac_mii.priv, CPMAC_MDIO_PHYSEL(0), PHYSEL_LINKSEL
1051 | PHYSEL_LINKINT | phy_id);*/
1052 } else
1053 snprintf(priv->phy_name, BUS_ID_SIZE, "fixed@%d:%d", 100, 1);
1054
1055 if ((rc = register_netdev(dev))) {
1056 printk(KERN_ERR "cpmac: error %i registering device %s\n", rc,
1057 dev->name);
1058 goto fail;
1059 }
1060
1061 if (netif_msg_probe(priv)) {
1062 printk(KERN_INFO
1063 "cpmac: device %s (regs: %p, irq: %d, phy: %s, mac: "
1064 MAC_FMT ")\n", dev->name, (void *)mem->start, dev->irq,
1065 priv->phy_name, MAC_ARG(dev->dev_addr));
1066 }
1067 return 0;
1068
1069 fail:
1070 free_netdev(dev);
1071 return rc;
1072 }
1073
1074 static int __devexit cpmac_remove(struct platform_device *pdev)
1075 {
1076 struct net_device *dev = platform_get_drvdata(pdev);
1077 unregister_netdev(dev);
1078 free_netdev(dev);
1079 return 0;
1080 }
1081
1082 static struct platform_driver cpmac_driver = {
1083 .driver.name = "cpmac",
1084 .probe = cpmac_probe,
1085 .remove = __devexit_p(cpmac_remove),
1086 };
1087
1088 int __devinit cpmac_init(void)
1089 {
1090 u32 mask;
1091 int i, res;
1092
1093 cpmac_mii.priv = ioremap(AR7_REGS_MDIO, 256);
1094
1095 if (!cpmac_mii.priv) {
1096 printk(KERN_ERR "Can't ioremap mdio registers\n");
1097 return -ENXIO;
1098 }
1099
1100 #warning FIXME: unhardcode gpio&reset bits
1101 ar7_gpio_disable(26);
1102 ar7_gpio_disable(27);
1103 ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
1104 ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
1105 ar7_device_reset(AR7_RESET_BIT_EPHY);
1106
1107 cpmac_mii.reset(&cpmac_mii);
1108
1109 for (i = 0; i < 300000; i++)
1110 if ((mask = cpmac_read(cpmac_mii.priv, CPMAC_MDIO_ALIVE)))
1111 break;
1112 else
1113 cpu_relax();
1114
1115 mask &= 0x7fffffff;
1116 if (mask & (mask - 1)) {
1117 external_switch = 1;
1118 mask = 0;
1119 }
1120
1121 cpmac_mii.phy_mask = ~(mask | 0x80000000);
1122
1123 res = mdiobus_register(&cpmac_mii);
1124 if (res)
1125 goto fail_mii;
1126
1127 res = platform_driver_register(&cpmac_driver);
1128 if (res)
1129 goto fail_cpmac;
1130
1131 return 0;
1132
1133 fail_cpmac:
1134 mdiobus_unregister(&cpmac_mii);
1135
1136 fail_mii:
1137 iounmap(cpmac_mii.priv);
1138
1139 return res;
1140 }
1141
1142 void __devexit cpmac_exit(void)
1143 {
1144 platform_driver_unregister(&cpmac_driver);
1145 mdiobus_unregister(&cpmac_mii);
1146 iounmap(cpmac_mii.priv);
1147 }
1148
1149 module_init(cpmac_init);
1150 module_exit(cpmac_exit);
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