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some additions to the ar7 system code, added cpmac network driver
[openwrt.git] / openwrt / target / linux / linux-2.4 / patches / brcm / 001-bcm47xx.patch
1 diff -Nur linux-2.4.30/arch/mips/bcm947xx/compressed/Makefile linux-2.4.30-brcm/arch/mips/bcm947xx/compressed/Makefile
2 --- linux-2.4.30/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/compressed/Makefile 2005-05-26 03:29:22.000000000 +0200
4 @@ -0,0 +1,33 @@
5 +#
6 +# Makefile for Broadcom BCM947XX boards
7 +#
8 +# Copyright 2001-2003, Broadcom Corporation
9 +# All Rights Reserved.
10 +#
11 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15 +#
16 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
17 +#
18 +
19 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
20 +SYSTEM ?= $(TOPDIR)/vmlinux
21 +
22 +all: vmlinuz
23 +
24 +# Don't build dependencies, this may die if $(CC) isn't gcc
25 +dep:
26 +
27 +# Create a gzipped version named vmlinuz for compatibility
28 +vmlinuz: piggy
29 + gzip -c9 $< > $@
30 +
31 +piggy: $(SYSTEM)
32 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
33 +
34 +mrproper: clean
35 +
36 +clean:
37 + rm -f vmlinuz piggy
38 diff -Nur linux-2.4.30/arch/mips/bcm947xx/generic/int-handler.S linux-2.4.30-brcm/arch/mips/bcm947xx/generic/int-handler.S
39 --- linux-2.4.30/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
40 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/generic/int-handler.S 2005-05-22 22:55:51.000000000 +0200
41 @@ -0,0 +1,51 @@
42 +/*
43 + * Generic interrupt handler for Broadcom MIPS boards
44 + *
45 + * Copyright 2004, Broadcom Corporation
46 + * All Rights Reserved.
47 + *
48 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
49 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
50 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
51 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
52 + *
53 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
54 + */
55 +
56 +#include <linux/config.h>
57 +
58 +#include <asm/asm.h>
59 +#include <asm/mipsregs.h>
60 +#include <asm/regdef.h>
61 +#include <asm/stackframe.h>
62 +
63 +/*
64 + * MIPS IRQ Source
65 + * -------- ------
66 + * 0 Software (ignored)
67 + * 1 Software (ignored)
68 + * 2 Combined hardware interrupt (hw0)
69 + * 3 Hardware
70 + * 4 Hardware
71 + * 5 Hardware
72 + * 6 Hardware
73 + * 7 R4k timer
74 + */
75 +
76 + .text
77 + .set noreorder
78 + .set noat
79 + .align 5
80 + NESTED(brcmIRQ, PT_SIZE, sp)
81 + SAVE_ALL
82 + CLI
83 + .set at
84 + .set noreorder
85 +
86 + jal brcm_irq_dispatch
87 + move a0, sp
88 +
89 + j ret_from_irq
90 + nop
91 +
92 + END(brcmIRQ)
93 diff -Nur linux-2.4.30/arch/mips/bcm947xx/generic/irq.c linux-2.4.30-brcm/arch/mips/bcm947xx/generic/irq.c
94 --- linux-2.4.30/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
95 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/generic/irq.c 2005-05-22 22:55:51.000000000 +0200
96 @@ -0,0 +1,130 @@
97 +/*
98 + * Generic interrupt control functions for Broadcom MIPS boards
99 + *
100 + * Copyright 2004, Broadcom Corporation
101 + * All Rights Reserved.
102 + *
103 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
104 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
105 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
106 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
107 + *
108 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
109 + */
110 +
111 +#include <linux/config.h>
112 +#include <linux/init.h>
113 +#include <linux/kernel.h>
114 +#include <linux/types.h>
115 +#include <linux/interrupt.h>
116 +#include <linux/irq.h>
117 +
118 +#include <asm/irq.h>
119 +#include <asm/mipsregs.h>
120 +#include <asm/gdb-stub.h>
121 +
122 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
123 +
124 +extern asmlinkage void brcmIRQ(void);
125 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
126 +
127 +void
128 +brcm_irq_dispatch(struct pt_regs *regs)
129 +{
130 + u32 cause;
131 +
132 + cause = read_c0_cause() &
133 + read_c0_status() &
134 + CAUSEF_IP;
135 +
136 +#ifdef CONFIG_KERNPROF
137 + change_c0_status(cause | 1, 1);
138 +#else
139 + clear_c0_status(cause);
140 +#endif
141 +
142 + if (cause & CAUSEF_IP7)
143 + do_IRQ(7, regs);
144 + if (cause & CAUSEF_IP2)
145 + do_IRQ(2, regs);
146 + if (cause & CAUSEF_IP3)
147 + do_IRQ(3, regs);
148 + if (cause & CAUSEF_IP4)
149 + do_IRQ(4, regs);
150 + if (cause & CAUSEF_IP5)
151 + do_IRQ(5, regs);
152 + if (cause & CAUSEF_IP6)
153 + do_IRQ(6, regs);
154 +}
155 +
156 +static void
157 +enable_brcm_irq(unsigned int irq)
158 +{
159 + if (irq < 8)
160 + set_c0_status(1 << (irq + 8));
161 + else
162 + set_c0_status(IE_IRQ0);
163 +}
164 +
165 +static void
166 +disable_brcm_irq(unsigned int irq)
167 +{
168 + if (irq < 8)
169 + clear_c0_status(1 << (irq + 8));
170 + else
171 + clear_c0_status(IE_IRQ0);
172 +}
173 +
174 +static void
175 +ack_brcm_irq(unsigned int irq)
176 +{
177 + /* Already done in brcm_irq_dispatch */
178 +}
179 +
180 +static unsigned int
181 +startup_brcm_irq(unsigned int irq)
182 +{
183 + enable_brcm_irq(irq);
184 +
185 + return 0; /* never anything pending */
186 +}
187 +
188 +static void
189 +end_brcm_irq(unsigned int irq)
190 +{
191 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
192 + enable_brcm_irq(irq);
193 +}
194 +
195 +static struct hw_interrupt_type brcm_irq_type = {
196 + typename: "MIPS",
197 + startup: startup_brcm_irq,
198 + shutdown: disable_brcm_irq,
199 + enable: enable_brcm_irq,
200 + disable: disable_brcm_irq,
201 + ack: ack_brcm_irq,
202 + end: end_brcm_irq,
203 + NULL
204 +};
205 +
206 +void __init
207 +init_IRQ(void)
208 +{
209 + int i;
210 +
211 + for (i = 0; i < NR_IRQS; i++) {
212 + irq_desc[i].status = IRQ_DISABLED;
213 + irq_desc[i].action = 0;
214 + irq_desc[i].depth = 1;
215 + irq_desc[i].handler = &brcm_irq_type;
216 + }
217 +
218 + set_except_vector(0, brcmIRQ);
219 + change_c0_status(ST0_IM, ALLINTS);
220 +
221 +#ifdef CONFIG_REMOTE_DEBUG
222 + printk("Breaking into debugger...\n");
223 + set_debug_traps();
224 + breakpoint();
225 +#endif
226 +}
227 diff -Nur linux-2.4.30/arch/mips/bcm947xx/generic/Makefile linux-2.4.30-brcm/arch/mips/bcm947xx/generic/Makefile
228 --- linux-2.4.30/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
229 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/generic/Makefile 2005-05-25 18:53:41.000000000 +0200
230 @@ -0,0 +1,15 @@
231 +#
232 +# Makefile for the BCM947xx specific kernel interface routines
233 +# under Linux.
234 +#
235 +
236 +.S.s:
237 + $(CPP) $(AFLAGS) $< -o $*.s
238 +.S.o:
239 + $(CC) $(AFLAGS) -c $< -o $*.o
240 +
241 +O_TARGET := brcm.o
242 +
243 +obj-y := int-handler.o irq.o
244 +
245 +include $(TOPDIR)/Rules.make
246 diff -Nur linux-2.4.30/arch/mips/bcm947xx/gpio.c linux-2.4.30-brcm/arch/mips/bcm947xx/gpio.c
247 --- linux-2.4.30/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
248 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/gpio.c 2005-05-22 22:55:51.000000000 +0200
249 @@ -0,0 +1,158 @@
250 +/*
251 + * GPIO char driver
252 + *
253 + * Copyright 2004, Broadcom Corporation
254 + * All Rights Reserved.
255 + *
256 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
257 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
258 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
259 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
260 + *
261 + * $Id: gpio.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
262 + */
263 +
264 +#include <linux/module.h>
265 +#include <linux/init.h>
266 +#include <linux/fs.h>
267 +#include <linux/miscdevice.h>
268 +#include <asm/uaccess.h>
269 +
270 +#include <typedefs.h>
271 +#include <bcmutils.h>
272 +#include <sbutils.h>
273 +#include <bcmdevs.h>
274 +
275 +static void *gpio_sbh;
276 +static int gpio_major;
277 +static devfs_handle_t gpio_dir;
278 +static struct {
279 + char *name;
280 + devfs_handle_t handle;
281 +} gpio_file[] = {
282 + { "in", NULL },
283 + { "out", NULL },
284 + { "outen", NULL },
285 + { "control", NULL }
286 +};
287 +
288 +static int
289 +gpio_open(struct inode *inode, struct file * file)
290 +{
291 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
292 + return -ENODEV;
293 +
294 + MOD_INC_USE_COUNT;
295 + return 0;
296 +}
297 +
298 +static int
299 +gpio_release(struct inode *inode, struct file * file)
300 +{
301 + MOD_DEC_USE_COUNT;
302 + return 0;
303 +}
304 +
305 +static ssize_t
306 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
307 +{
308 + u32 val;
309 +
310 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
311 + case 0:
312 + val = sb_gpioin(gpio_sbh);
313 + break;
314 + case 1:
315 + val = sb_gpioout(gpio_sbh, 0, 0);
316 + break;
317 + case 2:
318 + val = sb_gpioouten(gpio_sbh, 0, 0);
319 + break;
320 + case 3:
321 + val = sb_gpiocontrol(gpio_sbh, 0, 0);
322 + break;
323 + default:
324 + return -ENODEV;
325 + }
326 +
327 + if (put_user(val, (u32 *) buf))
328 + return -EFAULT;
329 +
330 + return sizeof(val);
331 +}
332 +
333 +static ssize_t
334 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
335 +{
336 + u32 val;
337 +
338 + if (get_user(val, (u32 *) buf))
339 + return -EFAULT;
340 +
341 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
342 + case 0:
343 + return -EACCES;
344 + case 1:
345 + sb_gpioout(gpio_sbh, ~0, val);
346 + break;
347 + case 2:
348 + sb_gpioouten(gpio_sbh, ~0, val);
349 + break;
350 + case 3:
351 + sb_gpiocontrol(gpio_sbh, ~0, val);
352 + break;
353 + default:
354 + return -ENODEV;
355 + }
356 +
357 + return sizeof(val);
358 +}
359 +
360 +static struct file_operations gpio_fops = {
361 + owner: THIS_MODULE,
362 + open: gpio_open,
363 + release: gpio_release,
364 + read: gpio_read,
365 + write: gpio_write,
366 +};
367 +
368 +static int __init
369 +gpio_init(void)
370 +{
371 + int i;
372 +
373 + if (!(gpio_sbh = sb_kattach()))
374 + return -ENODEV;
375 +
376 + sb_gpiosetcore(gpio_sbh);
377 +
378 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
379 + return gpio_major;
380 +
381 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
382 +
383 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
384 + gpio_file[i].handle = devfs_register(gpio_dir,
385 + gpio_file[i].name,
386 + DEVFS_FL_DEFAULT, gpio_major, i,
387 + S_IFCHR | S_IRUGO | S_IWUGO,
388 + &gpio_fops, NULL);
389 + }
390 +
391 + return 0;
392 +}
393 +
394 +static void __exit
395 +gpio_exit(void)
396 +{
397 + int i;
398 +
399 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
400 + devfs_unregister(gpio_file[i].handle);
401 + devfs_unregister(gpio_dir);
402 + devfs_unregister_chrdev(gpio_major, "gpio");
403 + sb_detach(gpio_sbh);
404 +}
405 +
406 +module_init(gpio_init);
407 +module_exit(gpio_exit);
408 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bcmdevs.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmdevs.h
409 --- linux-2.4.30/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
410 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmdevs.h 2005-05-25 20:30:26.000000000 +0200
411 @@ -0,0 +1,369 @@
412 +/*
413 + * Broadcom device-specific manifest constants.
414 + *
415 + * Copyright 2005, Broadcom Corporation
416 + * All Rights Reserved.
417 + *
418 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
419 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
420 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
421 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
422 + * $Id$
423 + */
424 +
425 +#ifndef _BCMDEVS_H
426 +#define _BCMDEVS_H
427 +
428 +
429 +/* Known PCI vendor Id's */
430 +#define VENDOR_EPIGRAM 0xfeda
431 +#define VENDOR_BROADCOM 0x14e4
432 +#define VENDOR_3COM 0x10b7
433 +#define VENDOR_NETGEAR 0x1385
434 +#define VENDOR_DIAMOND 0x1092
435 +#define VENDOR_DELL 0x1028
436 +#define VENDOR_HP 0x0e11
437 +#define VENDOR_APPLE 0x106b
438 +
439 +/* PCI Device Id's */
440 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
441 +#define BCM4211_DEVICE_ID 0x4211
442 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
443 +#define BCM4231_DEVICE_ID 0x4231
444 +
445 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
446 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
447 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
448 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
449 +
450 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
451 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
452 +
453 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
454 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
455 +
456 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
457 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
458 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
459 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
460 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
461 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
462 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
463 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
464 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
465 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
466 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
467 +
468 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
469 +
470 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
471 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
472 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
473 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
474 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
475 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
476 +
477 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
478 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
479 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
480 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
481 +
482 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
483 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
484 +
485 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
486 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
487 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
488 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
489 +
490 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
491 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
492 +#define BCM4306_D11G_ID2 0x4325
493 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
494 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
495 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
496 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
497 +
498 +#define BCM4309_PKG_ID 1 /* 4309 package id */
499 +
500 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
501 +#define BCM4303_PKG_ID 2 /* 4303 package id */
502 +
503 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
504 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
505 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
506 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
507 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
508 +
509 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
510 +
511 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
512 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
513 +
514 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
515 +
516 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
517 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
518 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
519 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
520 +
521 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
522 +
523 +/* Address map */
524 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
525 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
526 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
527 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
528 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
529 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
530 +
531 +/* Core register space */
532 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
533 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
534 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
535 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
536 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
537 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
538 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
539 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
540 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
541 +
542 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
543 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
544 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
545 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
546 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
547 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
548 +
549 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
550 +
551 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
552 +
553 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
554 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
555 +
556 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
557 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
558 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
559 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
560 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
561 +
562 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
563 +
564 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
565 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
566 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
567 +
568 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
569 +
570 +/* PCMCIA vendor Id's */
571 +
572 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
573 +
574 +/* SDIO vendor Id's */
575 +#define VENDOR_BROADCOM_SDIO 0x00BF
576 +
577 +
578 +/* boardflags */
579 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
580 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
581 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
582 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
583 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
584 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
585 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
586 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
587 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
588 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
589 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
590 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
591 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
592 +
593 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
594 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
595 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
596 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
597 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
598 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
599 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
600 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
601 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
602 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
603 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
604 +
605 +/* Bus types */
606 +#define SB_BUS 0 /* Silicon Backplane */
607 +#define PCI_BUS 1 /* PCI target */
608 +#define PCMCIA_BUS 2 /* PCMCIA target */
609 +#define SDIO_BUS 3 /* SDIO target */
610 +#define JTAG_BUS 4 /* JTAG */
611 +
612 +/* Allows optimization for single-bus support */
613 +#ifdef BCMBUSTYPE
614 +#define BUSTYPE(bus) (BCMBUSTYPE)
615 +#else
616 +#define BUSTYPE(bus) (bus)
617 +#endif
618 +
619 +/* power control defines */
620 +#define PLL_DELAY 150 /* 150us pll on delay */
621 +#define FREF_DELAY 200 /* 200us fref change delay */
622 +#define MIN_SLOW_CLK 32 /* 32us Slow clock period */
623 +
624 +/* Reference Board Types */
625 +
626 +#define BU4710_BOARD 0x0400
627 +#define VSIM4710_BOARD 0x0401
628 +#define QT4710_BOARD 0x0402
629 +
630 +#define BU4610_BOARD 0x0403
631 +#define VSIM4610_BOARD 0x0404
632 +
633 +#define BU4307_BOARD 0x0405
634 +#define BCM94301CB_BOARD 0x0406
635 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
636 +#define BCM94301MP_BOARD 0x0407
637 +#define BCM94307MP_BOARD 0x0408
638 +#define BCMAP4307_BOARD 0x0409
639 +
640 +#define BU4309_BOARD 0x040a
641 +#define BCM94309CB_BOARD 0x040b
642 +#define BCM94309MP_BOARD 0x040c
643 +#define BCM4309AP_BOARD 0x040d
644 +
645 +#define BCM94302MP_BOARD 0x040e
646 +
647 +#define VSIM4310_BOARD 0x040f
648 +#define BU4711_BOARD 0x0410
649 +#define BCM94310U_BOARD 0x0411
650 +#define BCM94310AP_BOARD 0x0412
651 +#define BCM94310MP_BOARD 0x0414
652 +
653 +#define BU4306_BOARD 0x0416
654 +#define BCM94306CB_BOARD 0x0417
655 +#define BCM94306MP_BOARD 0x0418
656 +
657 +#define BCM94710D_BOARD 0x041a
658 +#define BCM94710R1_BOARD 0x041b
659 +#define BCM94710R4_BOARD 0x041c
660 +#define BCM94710AP_BOARD 0x041d
661 +
662 +
663 +#define BU2050_BOARD 0x041f
664 +
665 +
666 +#define BCM94309G_BOARD 0x0421
667 +
668 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
669 +
670 +#define BU4704_BOARD 0x0423
671 +#define BU4702_BOARD 0x0424
672 +
673 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
674 +
675 +#define BU4317_BOARD 0x0426
676 +
677 +
678 +#define BCM94702MN_BOARD 0x0428
679 +
680 +/* BCM4702 1U CompactPCI Board */
681 +#define BCM94702CPCI_BOARD 0x0429
682 +
683 +/* BCM4702 with BCM95380 VLAN Router */
684 +#define BCM95380RR_BOARD 0x042a
685 +
686 +/* cb4306 with SiGe PA */
687 +#define BCM94306CBSG_BOARD 0x042b
688 +
689 +/* mp4301 with 2050 radio */
690 +#define BCM94301MPL_BOARD 0x042c
691 +
692 +/* cb4306 with SiGe PA */
693 +#define PCSG94306_BOARD 0x042d
694 +
695 +/* bu4704 with sdram */
696 +#define BU4704SD_BOARD 0x042e
697 +
698 +/* Dual 11a/11g Router */
699 +#define BCM94704AGR_BOARD 0x042f
700 +
701 +/* 11a-only minipci */
702 +#define BCM94308MP_BOARD 0x0430
703 +
704 +
705 +
706 +/* BCM94317 boards */
707 +#define BCM94317CB_BOARD 0x0440
708 +#define BCM94317MP_BOARD 0x0441
709 +#define BCM94317PCMCIA_BOARD 0x0442
710 +#define BCM94317SDIO_BOARD 0x0443
711 +
712 +#define BU4712_BOARD 0x0444
713 +#define BU4712SD_BOARD 0x045d
714 +#define BU4712L_BOARD 0x045f
715 +
716 +/* BCM4712 boards */
717 +#define BCM94712AP_BOARD 0x0445
718 +#define BCM94712P_BOARD 0x0446
719 +
720 +/* BCM4318 boards */
721 +#define BU4318_BOARD 0x0447
722 +#define CB4318_BOARD 0x0448
723 +#define MPG4318_BOARD 0x0449
724 +#define MP4318_BOARD 0x044a
725 +#define SD4318_BOARD 0x044b
726 +
727 +/* Another mp4306 with SiGe */
728 +#define BCM94306P_BOARD 0x044c
729 +
730 +/* CF-like 4317 modules */
731 +#define BCM94317CF_BOARD 0x044d
732 +
733 +/* mp4303 */
734 +#define BCM94303MP_BOARD 0x044e
735 +
736 +/* mpsgh4306 */
737 +#define BCM94306MPSGH_BOARD 0x044f
738 +
739 +/* BRCM 4306 w/ Front End Modules */
740 +#define BCM94306MPM 0x0450
741 +#define BCM94306MPL 0x0453
742 +
743 +/* 4712agr */
744 +#define BCM94712AGR_BOARD 0x0451
745 +
746 +/* The real CF 4317 board */
747 +#define CFI4317_BOARD 0x0452
748 +
749 +/* pcmcia 4303 */
750 +#define PC4303_BOARD 0x0454
751 +
752 +/* 5350K */
753 +#define BCM95350K_BOARD 0x0455
754 +
755 +/* 5350R */
756 +#define BCM95350R_BOARD 0x0456
757 +
758 +/* 4306mplna */
759 +#define BCM94306MPLNA_BOARD 0x0457
760 +
761 +
762 +/* 4306mph */
763 +#define BCM94306MPH_BOARD 0x045b
764 +
765 +/* 4306pciv */
766 +#define BCM94306PCIV_BOARD 0x045c
767 +
768 +#define BU4712SD_BOARD 0x045d
769 +
770 +
771 +#define BU4712L_BOARD 0x045f
772 +#define BCM94712LGR_BOARD 0x0460
773 +
774 +#define BU5352_BOARD 0x0462
775 +#define BCM95352GR_BOARD 0x0467
776 +
777 +/* # of GPIO pins */
778 +#define GPIO_NUMPINS 16
779 +
780 +#endif /* _BCMDEVS_H */
781 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bcmendian.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmendian.h
782 --- linux-2.4.30/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
783 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmendian.h 2005-02-02 23:16:39.000000000 +0100
784 @@ -0,0 +1,168 @@
785 +/*
786 + * local version of endian.h - byte order defines
787 + *
788 + * Copyright 2005, Broadcom Corporation
789 + * All Rights Reserved.
790 + *
791 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
792 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
793 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
794 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
795 + *
796 + * $Id$
797 +*/
798 +
799 +#ifndef _BCMENDIAN_H_
800 +#define _BCMENDIAN_H_
801 +
802 +#include <typedefs.h>
803 +
804 +/* Byte swap a 16 bit value */
805 +#define BCMSWAP16(val) \
806 + ((uint16)( \
807 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
808 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
809 +
810 +/* Byte swap a 32 bit value */
811 +#define BCMSWAP32(val) \
812 + ((uint32)( \
813 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
814 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
815 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
816 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
817 +
818 +static INLINE uint16
819 +bcmswap16(uint16 val)
820 +{
821 + return BCMSWAP16(val);
822 +}
823 +
824 +static INLINE uint32
825 +bcmswap32(uint32 val)
826 +{
827 + return BCMSWAP32(val);
828 +}
829 +
830 +/* buf - start of buffer of shorts to swap */
831 +/* len - byte length of buffer */
832 +static INLINE void
833 +bcmswap16_buf(uint16 *buf, uint len)
834 +{
835 + len = len/2;
836 +
837 + while(len--){
838 + *buf = bcmswap16(*buf);
839 + buf++;
840 + }
841 +}
842 +
843 +#ifndef hton16
844 +#ifndef IL_BIGENDIAN
845 +#define HTON16(i) BCMSWAP16(i)
846 +#define hton16(i) bcmswap16(i)
847 +#define hton32(i) bcmswap32(i)
848 +#define ntoh16(i) bcmswap16(i)
849 +#define ntoh32(i) bcmswap32(i)
850 +#define ltoh16(i) (i)
851 +#define ltoh32(i) (i)
852 +#define htol16(i) (i)
853 +#define htol32(i) (i)
854 +#else
855 +#define HTON16(i) (i)
856 +#define hton16(i) (i)
857 +#define hton32(i) (i)
858 +#define ntoh16(i) (i)
859 +#define ntoh32(i) (i)
860 +#define ltoh16(i) bcmswap16(i)
861 +#define ltoh32(i) bcmswap32(i)
862 +#define htol16(i) bcmswap16(i)
863 +#define htol32(i) bcmswap32(i)
864 +#endif
865 +#endif
866 +
867 +#ifndef IL_BIGENDIAN
868 +#define ltoh16_buf(buf, i)
869 +#define htol16_buf(buf, i)
870 +#else
871 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
872 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
873 +#endif
874 +
875 +/*
876 +* load 16-bit value from unaligned little endian byte array.
877 +*/
878 +static INLINE uint16
879 +ltoh16_ua(uint8 *bytes)
880 +{
881 + return (bytes[1]<<8)+bytes[0];
882 +}
883 +
884 +/*
885 +* load 32-bit value from unaligned little endian byte array.
886 +*/
887 +static INLINE uint32
888 +ltoh32_ua(uint8 *bytes)
889 +{
890 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
891 +}
892 +
893 +/*
894 +* load 16-bit value from unaligned big(network) endian byte array.
895 +*/
896 +static INLINE uint16
897 +ntoh16_ua(uint8 *bytes)
898 +{
899 + return (bytes[0]<<8)+bytes[1];
900 +}
901 +
902 +/*
903 +* load 32-bit value from unaligned big(network) endian byte array.
904 +*/
905 +static INLINE uint32
906 +ntoh32_ua(uint8 *bytes)
907 +{
908 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
909 +}
910 +
911 +/* get_ua adapted from Linux asm-mips/unaligned.h */
912 +#ifdef IL_BIGENDIAN
913 +#define get_ua(ptr) \
914 +({ \
915 + __typeof__(*(ptr)) __val; \
916 + \
917 + switch (sizeof(*(ptr))) { \
918 + case 1: \
919 + __val = *(uint8 *)ptr; \
920 + break; \
921 + case 2: \
922 + __val = ntoh16_ua((uint8 *)ptr); \
923 + break; \
924 + case 4: \
925 + __val = ntoh32_ua((uint8 *)ptr); \
926 + break; \
927 + } \
928 + \
929 + __val; \
930 +})
931 +#else
932 +#define get_ua(ptr) \
933 +({ \
934 + __typeof__(*(ptr)) __val; \
935 + \
936 + switch (sizeof(*(ptr))) { \
937 + case 1: \
938 + __val = *(uint8 *)ptr; \
939 + break; \
940 + case 2: \
941 + __val = ltoh16_ua((uint8 *)ptr); \
942 + break; \
943 + case 4: \
944 + __val = ltoh32_ua((uint8 *)ptr); \
945 + break; \
946 + } \
947 + \
948 + __val; \
949 +})
950 +#endif
951 +
952 +#endif /* _BCMENDIAN_H_ */
953 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bcmenet47xx.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmenet47xx.h
954 --- linux-2.4.30/arch/mips/bcm947xx/include/bcmenet47xx.h 1970-01-01 01:00:00.000000000 +0100
955 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmenet47xx.h 2005-02-02 23:16:39.000000000 +0100
956 @@ -0,0 +1,229 @@
957 +/*
958 + * Hardware-specific definitions for
959 + * Broadcom BCM47XX 10/100 Mbps Ethernet cores.
960 + *
961 + * Copyright 2005, Broadcom Corporation
962 + * All Rights Reserved.
963 + *
964 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
965 + * the contents of this file may not be disclosed to third parties, copied
966 + * or duplicated in any form, in whole or in part, without the prior
967 + * written permission of Broadcom Corporation.
968 + * $Id$
969 + */
970 +
971 +#ifndef _bcmenet_47xx_h_
972 +#define _bcmenet_47xx_h_
973 +
974 +#include <bcmenetmib.h>
975 +#include <bcmenetrxh.h>
976 +#include <bcmenetphy.h>
977 +
978 +#define BCMENET_NFILTERS 64 /* # ethernet address filter entries */
979 +#define BCMENET_MCHASHBASE 0x200 /* multicast hash filter base address */
980 +#define BCMENET_MCHASHSIZE 256 /* multicast hash filter size in bytes */
981 +#define BCMENET_MAX_DMA 4096 /* chip has 12 bits of DMA addressing */
982 +
983 +/* power management event wakeup pattern constants */
984 +#define BCMENET_NPMP 4 /* chip supports 4 wakeup patterns */
985 +#define BCMENET_PMPBASE 0x400 /* wakeup pattern base address */
986 +#define BCMENET_PMPSIZE 0x80 /* 128bytes each pattern */
987 +#define BCMENET_PMMBASE 0x600 /* wakeup mask base address */
988 +#define BCMENET_PMMSIZE 0x10 /* 128bits each mask */
989 +
990 +/* cpp contortions to concatenate w/arg prescan */
991 +#ifndef PAD
992 +#define _PADLINE(line) pad ## line
993 +#define _XSTR(line) _PADLINE(line)
994 +#define PAD _XSTR(__LINE__)
995 +#endif /* PAD */
996 +
997 +/*
998 + * Host Interface Registers
999 + */
1000 +typedef volatile struct _bcmenettregs {
1001 + /* Device and Power Control */
1002 + uint32 devcontrol;
1003 + uint32 PAD[2];
1004 + uint32 biststatus;
1005 + uint32 wakeuplength;
1006 + uint32 PAD[3];
1007 +
1008 + /* Interrupt Control */
1009 + uint32 intstatus;
1010 + uint32 intmask;
1011 + uint32 gptimer;
1012 + uint32 PAD[23];
1013 +
1014 + /* Ethernet MAC Address Filtering Control */
1015 + uint32 PAD[2];
1016 + uint32 enetftaddr;
1017 + uint32 enetftdata;
1018 + uint32 PAD[2];
1019 +
1020 + /* Ethernet MAC Control */
1021 + uint32 emactxmaxburstlen;
1022 + uint32 emacrxmaxburstlen;
1023 + uint32 emaccontrol;
1024 + uint32 emacflowcontrol;
1025 +
1026 + uint32 PAD[20];
1027 +
1028 + /* DMA Lazy Interrupt Control */
1029 + uint32 intrecvlazy;
1030 + uint32 PAD[63];
1031 +
1032 + /* DMA engine */
1033 + dmaregs_t dmaregs;
1034 + dmafifo_t dmafifo;
1035 + uint32 PAD[116];
1036 +
1037 + /* EMAC Registers */
1038 + uint32 rxconfig;
1039 + uint32 rxmaxlength;
1040 + uint32 txmaxlength;
1041 + uint32 PAD;
1042 + uint32 mdiocontrol;
1043 + uint32 mdiodata;
1044 + uint32 emacintmask;
1045 + uint32 emacintstatus;
1046 + uint32 camdatalo;
1047 + uint32 camdatahi;
1048 + uint32 camcontrol;
1049 + uint32 enetcontrol;
1050 + uint32 txcontrol;
1051 + uint32 txwatermark;
1052 + uint32 mibcontrol;
1053 + uint32 PAD[49];
1054 +
1055 + /* EMAC MIB counters */
1056 + bcmenetmib_t mib;
1057 +
1058 + uint32 PAD[585];
1059 +
1060 + /* Sonics SiliconBackplane config registers */
1061 + sbconfig_t sbconfig;
1062 +} bcmenetregs_t;
1063 +
1064 +/* device control */
1065 +#define DC_PM ((uint32)1 << 7) /* pattern filtering enable */
1066 +#define DC_IP ((uint32)1 << 10) /* internal ephy present (rev >= 1) */
1067 +#define DC_ER ((uint32)1 << 15) /* ephy reset */
1068 +#define DC_MP ((uint32)1 << 16) /* mii phy mode enable */
1069 +#define DC_CO ((uint32)1 << 17) /* mii phy mode: enable clocks */
1070 +#define DC_PA_MASK 0x7c0000 /* mii phy mode: mdc/mdio phy address */
1071 +#define DC_PA_SHIFT 18
1072 +#define DC_FS_MASK 0x03800000 /* fifo size (rev >= 8) */
1073 +#define DC_FS_SHIFT 23
1074 +#define DC_FS_4K 0 /* 4Kbytes */
1075 +#define DC_FS_512 1 /* 512bytes */
1076 +
1077 +/* wakeup length */
1078 +#define WL_P0_MASK 0x7f /* pattern 0 */
1079 +#define WL_D0 ((uint32)1 << 7)
1080 +#define WL_P1_MASK 0x7f00 /* pattern 1 */
1081 +#define WL_P1_SHIFT 8
1082 +#define WL_D1 ((uint32)1 << 15)
1083 +#define WL_P2_MASK 0x7f0000 /* pattern 2 */
1084 +#define WL_P2_SHIFT 16
1085 +#define WL_D2 ((uint32)1 << 23)
1086 +#define WL_P3_MASK 0x7f000000 /* pattern 3 */
1087 +#define WL_P3_SHIFT 24
1088 +#define WL_D3 ((uint32)1 << 31)
1089 +
1090 +/* intstatus and intmask */
1091 +#define I_PME ((uint32)1 << 6) /* power management event */
1092 +#define I_TO ((uint32)1 << 7) /* general purpose timeout */
1093 +#define I_PC ((uint32)1 << 10) /* descriptor error */
1094 +#define I_PD ((uint32)1 << 11) /* data error */
1095 +#define I_DE ((uint32)1 << 12) /* descriptor protocol error */
1096 +#define I_RU ((uint32)1 << 13) /* receive descriptor underflow */
1097 +#define I_RO ((uint32)1 << 14) /* receive fifo overflow */
1098 +#define I_XU ((uint32)1 << 15) /* transmit fifo underflow */
1099 +#define I_RI ((uint32)1 << 16) /* receive interrupt */
1100 +#define I_XI ((uint32)1 << 24) /* transmit interrupt */
1101 +#define I_EM ((uint32)1 << 26) /* emac interrupt */
1102 +#define I_MW ((uint32)1 << 27) /* mii write */
1103 +#define I_MR ((uint32)1 << 28) /* mii read */
1104 +
1105 +/* emaccontrol */
1106 +#define EMC_CG ((uint32)1 << 0) /* crc32 generation enable */
1107 +#define EMC_EP ((uint32)1 << 2) /* onchip ephy: powerdown (rev >= 1) */
1108 +#define EMC_ED ((uint32)1 << 3) /* onchip ephy: energy detected (rev >= 1) */
1109 +#define EMC_LC_MASK 0xe0 /* onchip ephy: led control (rev >= 1) */
1110 +#define EMC_LC_SHIFT 5
1111 +
1112 +/* emacflowcontrol */
1113 +#define EMF_RFH_MASK 0xff /* rx fifo hi water mark */
1114 +#define EMF_PG ((uint32)1 << 15) /* enable pause frame generation */
1115 +
1116 +/* interrupt receive lazy */
1117 +#define IRL_TO_MASK 0x00ffffff /* timeout */
1118 +#define IRL_FC_MASK 0xff000000 /* frame count */
1119 +#define IRL_FC_SHIFT 24 /* frame count */
1120 +
1121 +/* emac receive config */
1122 +#define ERC_DB ((uint32)1 << 0) /* disable broadcast */
1123 +#define ERC_AM ((uint32)1 << 1) /* accept all multicast */
1124 +#define ERC_RDT ((uint32)1 << 2) /* receive disable while transmitting */
1125 +#define ERC_PE ((uint32)1 << 3) /* promiscuous enable */
1126 +#define ERC_LE ((uint32)1 << 4) /* loopback enable */
1127 +#define ERC_FE ((uint32)1 << 5) /* enable flow control */
1128 +#define ERC_UF ((uint32)1 << 6) /* accept unicast flow control frame */
1129 +#define ERC_RF ((uint32)1 << 7) /* reject filter */
1130 +#define ERC_CA ((uint32)1 << 8) /* cam absent */
1131 +
1132 +/* emac mdio control */
1133 +#define MC_MF_MASK 0x7f /* mdc frequency */
1134 +#define MC_PE ((uint32)1 << 7) /* mii preamble enable */
1135 +
1136 +/* emac mdio data */
1137 +#define MD_DATA_MASK 0xffff /* r/w data */
1138 +#define MD_TA_MASK 0x30000 /* turnaround value */
1139 +#define MD_TA_SHIFT 16
1140 +#define MD_TA_VALID (2 << MD_TA_SHIFT) /* valid ta */
1141 +#define MD_RA_MASK 0x7c0000 /* register address */
1142 +#define MD_RA_SHIFT 18
1143 +#define MD_PMD_MASK 0xf800000 /* physical media device */
1144 +#define MD_PMD_SHIFT 23
1145 +#define MD_OP_MASK 0x30000000 /* opcode */
1146 +#define MD_OP_SHIFT 28
1147 +#define MD_OP_WRITE (1 << MD_OP_SHIFT) /* write op */
1148 +#define MD_OP_READ (2 << MD_OP_SHIFT) /* read op */
1149 +#define MD_SB_MASK 0xc0000000 /* start bits */
1150 +#define MD_SB_SHIFT 30
1151 +#define MD_SB_START (0x1 << MD_SB_SHIFT) /* start of frame */
1152 +
1153 +/* emac intstatus and intmask */
1154 +#define EI_MII ((uint32)1 << 0) /* mii mdio interrupt */
1155 +#define EI_MIB ((uint32)1 << 1) /* mib interrupt */
1156 +#define EI_FLOW ((uint32)1 << 2) /* flow control interrupt */
1157 +
1158 +/* emac cam data high */
1159 +#define CD_V ((uint32)1 << 16) /* valid bit */
1160 +
1161 +/* emac cam control */
1162 +#define CC_CE ((uint32)1 << 0) /* cam enable */
1163 +#define CC_MS ((uint32)1 << 1) /* mask select */
1164 +#define CC_RD ((uint32)1 << 2) /* read */
1165 +#define CC_WR ((uint32)1 << 3) /* write */
1166 +#define CC_INDEX_MASK 0x3f0000 /* index */
1167 +#define CC_INDEX_SHIFT 16
1168 +#define CC_CB ((uint32)1 << 31) /* cam busy */
1169 +
1170 +/* emac ethernet control */
1171 +#define EC_EE ((uint32)1 << 0) /* emac enable */
1172 +#define EC_ED ((uint32)1 << 1) /* emac disable */
1173 +#define EC_ES ((uint32)1 << 2) /* emac soft reset */
1174 +#define EC_EP ((uint32)1 << 3) /* external phy select */
1175 +
1176 +/* emac transmit control */
1177 +#define EXC_FD ((uint32)1 << 0) /* full duplex */
1178 +#define EXC_FM ((uint32)1 << 1) /* flowmode */
1179 +#define EXC_SB ((uint32)1 << 2) /* single backoff enable */
1180 +#define EXC_SS ((uint32)1 << 3) /* small slottime */
1181 +
1182 +/* emac mib control */
1183 +#define EMC_RZ ((uint32)1 << 0) /* autoclear on read */
1184 +
1185 +#endif /* _bcmenet_47xx_h_ */
1186 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bcmenetmib.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmenetmib.h
1187 --- linux-2.4.30/arch/mips/bcm947xx/include/bcmenetmib.h 1970-01-01 01:00:00.000000000 +0100
1188 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmenetmib.h 2005-02-02 23:16:39.000000000 +0100
1189 @@ -0,0 +1,81 @@
1190 +/*
1191 + * Hardware-specific MIB definition for
1192 + * Broadcom Home Networking Division
1193 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
1194 + *
1195 + * Copyright 2005, Broadcom Corporation
1196 + * All Rights Reserved.
1197 + *
1198 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1199 + * the contents of this file may not be disclosed to third parties, copied
1200 + * or duplicated in any form, in whole or in part, without the prior
1201 + * written permission of Broadcom Corporation.
1202 + * $Id$
1203 + */
1204 +
1205 +#ifndef _bcmenetmib_h_
1206 +#define _bcmenetmib_h_
1207 +
1208 +/* cpp contortions to concatenate w/arg prescan */
1209 +#ifndef PAD
1210 +#define _PADLINE(line) pad ## line
1211 +#define _XSTR(line) _PADLINE(line)
1212 +#define PAD _XSTR(__LINE__)
1213 +#endif /* PAD */
1214 +
1215 +/*
1216 + * EMAC MIB Registers
1217 + */
1218 +typedef volatile struct {
1219 + uint32 tx_good_octets;
1220 + uint32 tx_good_pkts;
1221 + uint32 tx_octets;
1222 + uint32 tx_pkts;
1223 + uint32 tx_broadcast_pkts;
1224 + uint32 tx_multicast_pkts;
1225 + uint32 tx_len_64;
1226 + uint32 tx_len_65_to_127;
1227 + uint32 tx_len_128_to_255;
1228 + uint32 tx_len_256_to_511;
1229 + uint32 tx_len_512_to_1023;
1230 + uint32 tx_len_1024_to_max;
1231 + uint32 tx_jabber_pkts;
1232 + uint32 tx_oversize_pkts;
1233 + uint32 tx_fragment_pkts;
1234 + uint32 tx_underruns;
1235 + uint32 tx_total_cols;
1236 + uint32 tx_single_cols;
1237 + uint32 tx_multiple_cols;
1238 + uint32 tx_excessive_cols;
1239 + uint32 tx_late_cols;
1240 + uint32 tx_defered;
1241 + uint32 tx_carrier_lost;
1242 + uint32 tx_pause_pkts;
1243 + uint32 PAD[8];
1244 +
1245 + uint32 rx_good_octets;
1246 + uint32 rx_good_pkts;
1247 + uint32 rx_octets;
1248 + uint32 rx_pkts;
1249 + uint32 rx_broadcast_pkts;
1250 + uint32 rx_multicast_pkts;
1251 + uint32 rx_len_64;
1252 + uint32 rx_len_65_to_127;
1253 + uint32 rx_len_128_to_255;
1254 + uint32 rx_len_256_to_511;
1255 + uint32 rx_len_512_to_1023;
1256 + uint32 rx_len_1024_to_max;
1257 + uint32 rx_jabber_pkts;
1258 + uint32 rx_oversize_pkts;
1259 + uint32 rx_fragment_pkts;
1260 + uint32 rx_missed_pkts;
1261 + uint32 rx_crc_align_errs;
1262 + uint32 rx_undersize;
1263 + uint32 rx_crc_errs;
1264 + uint32 rx_align_errs;
1265 + uint32 rx_symbol_errs;
1266 + uint32 rx_pause_pkts;
1267 + uint32 rx_nonpause_pkts;
1268 +} bcmenetmib_t;
1269 +
1270 +#endif /* _bcmenetmib_h_ */
1271 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bcmenetphy.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmenetphy.h
1272 --- linux-2.4.30/arch/mips/bcm947xx/include/bcmenetphy.h 1970-01-01 01:00:00.000000000 +0100
1273 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmenetphy.h 2005-02-02 23:16:39.000000000 +0100
1274 @@ -0,0 +1,58 @@
1275 +/*
1276 + * Misc Broadcom BCM47XX MDC/MDIO enet phy definitions.
1277 + *
1278 + * Copyright 2005, Broadcom Corporation
1279 + * All Rights Reserved.
1280 + *
1281 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1282 + * the contents of this file may not be disclosed to third parties, copied
1283 + * or duplicated in any form, in whole or in part, without the prior
1284 + * written permission of Broadcom Corporation.
1285 + * $Id$
1286 + */
1287 +
1288 +#ifndef _bcmenetphy_h_
1289 +#define _bcmenetphy_h_
1290 +
1291 +/* phy address */
1292 +#define MAXEPHY 32 /* mdio phy addresses are 5bit quantities */
1293 +#define EPHY_MASK 0x1f
1294 +#define EPHY_NONE 31 /* nvram: no phy present at all */
1295 +#define EPHY_NOREG 30 /* nvram: no local phy regs */
1296 +
1297 +/* just a few phy registers */
1298 +#define CTL_RESET (1 << 15) /* reset */
1299 +#define CTL_LOOP (1 << 14) /* loopback */
1300 +#define CTL_SPEED (1 << 13) /* speed selection 0=10, 1=100 */
1301 +#define CTL_ANENAB (1 << 12) /* autonegotiation enable */
1302 +#define CTL_RESTART (1 << 9) /* restart autonegotiation */
1303 +#define CTL_DUPLEX (1 << 8) /* duplex mode 0=half, 1=full */
1304 +
1305 +#define ADV_10FULL (1 << 6) /* autonegotiate advertise 10full */
1306 +#define ADV_10HALF (1 << 5) /* autonegotiate advertise 10half */
1307 +#define ADV_100FULL (1 << 8) /* autonegotiate advertise 100full */
1308 +#define ADV_100HALF (1 << 7) /* autonegotiate advertise 100half */
1309 +
1310 +/* link partner ability register */
1311 +#define LPA_SLCT 0x001f /* same as advertise selector */
1312 +#define LPA_10HALF 0x0020 /* can do 10mbps half-duplex */
1313 +#define LPA_10FULL 0x0040 /* can do 10mbps full-duplex */
1314 +#define LPA_100HALF 0x0080 /* can do 100mbps half-duplex */
1315 +#define LPA_100FULL 0x0100 /* can do 100mbps full-duplex */
1316 +#define LPA_100BASE4 0x0200 /* can do 100mbps 4k packets */
1317 +#define LPA_RESV 0x1c00 /* unused */
1318 +#define LPA_RFAULT 0x2000 /* link partner faulted */
1319 +#define LPA_LPACK 0x4000 /* link partner acked us */
1320 +#define LPA_NPAGE 0x8000 /* next page bit */
1321 +
1322 +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
1323 +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
1324 +
1325 +#define STAT_REMFAULT (1 << 4) /* remote fault */
1326 +#define STAT_LINK (1 << 2) /* link status */
1327 +#define STAT_JAB (1 << 1) /* jabber detected */
1328 +#define AUX_FORCED (1 << 2) /* forced 10/100 */
1329 +#define AUX_SPEED (1 << 1) /* speed 0=10mbps 1=100mbps */
1330 +#define AUX_DUPLEX (1 << 0) /* duplex 0=half 1=full */
1331 +
1332 +#endif /* _bcmenetphy_h_ */
1333 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bcmenetrxh.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmenetrxh.h
1334 --- linux-2.4.30/arch/mips/bcm947xx/include/bcmenetrxh.h 1970-01-01 01:00:00.000000000 +0100
1335 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmenetrxh.h 2005-02-02 23:16:39.000000000 +0100
1336 @@ -0,0 +1,43 @@
1337 +/*
1338 + * Hardware-specific Receive Data Header for the
1339 + * Broadcom Home Networking Division
1340 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
1341 + *
1342 + * Copyright 2005, Broadcom Corporation
1343 + * All Rights Reserved.
1344 + *
1345 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1346 + * the contents of this file may not be disclosed to third parties, copied
1347 + * or duplicated in any form, in whole or in part, without the prior
1348 + * written permission of Broadcom Corporation.
1349 + * $Id$
1350 + */
1351 +
1352 +#ifndef _bcmenetrxh_h_
1353 +#define _bcmenetrxh_h_
1354 +
1355 +/*
1356 + * The Ethernet MAC core returns an 8-byte Receive Frame Data Header
1357 + * with every frame consisting of
1358 + * 16bits of frame length, followed by
1359 + * 16bits of EMAC rx descriptor info, followed by 32bits of undefined.
1360 + */
1361 +typedef volatile struct {
1362 + uint16 len;
1363 + uint16 flags;
1364 + uint16 pad[12];
1365 +} bcmenetrxh_t;
1366 +
1367 +#define RXHDR_LEN 28
1368 +
1369 +#define RXF_L ((uint16)1 << 11) /* last buffer in a frame */
1370 +#define RXF_MISS ((uint16)1 << 7) /* received due to promisc mode */
1371 +#define RXF_BRDCAST ((uint16)1 << 6) /* dest is broadcast address */
1372 +#define RXF_MULT ((uint16)1 << 5) /* dest is multicast address */
1373 +#define RXF_LG ((uint16)1 << 4) /* frame length > rxmaxlength */
1374 +#define RXF_NO ((uint16)1 << 3) /* odd number of nibbles */
1375 +#define RXF_RXER ((uint16)1 << 2) /* receive symbol error */
1376 +#define RXF_CRC ((uint16)1 << 1) /* crc error */
1377 +#define RXF_OV ((uint16)1 << 0) /* fifo overflow */
1378 +
1379 +#endif /* _bcmenetrxh_h_ */
1380 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bcmnvram.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmnvram.h
1381 --- linux-2.4.30/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
1382 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmnvram.h 2005-02-02 23:16:39.000000000 +0100
1383 @@ -0,0 +1,132 @@
1384 +/*
1385 + * NVRAM variable manipulation
1386 + *
1387 + * Copyright 2005, Broadcom Corporation
1388 + * All Rights Reserved.
1389 + *
1390 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1391 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1392 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1393 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1394 + *
1395 + * $Id$
1396 + */
1397 +
1398 +#ifndef _bcmnvram_h_
1399 +#define _bcmnvram_h_
1400 +
1401 +#ifndef _LANGUAGE_ASSEMBLY
1402 +
1403 +#include <typedefs.h>
1404 +
1405 +struct nvram_header {
1406 + uint32 magic;
1407 + uint32 len;
1408 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:27 init, mem. test 28, 29-31 reserved */
1409 + uint32 config_refresh; /* 0:15 config, 16:31 refresh */
1410 + uint32 config_ncdl; /* ncdl values for memc */
1411 +};
1412 +
1413 +struct nvram_tuple {
1414 + char *name;
1415 + char *value;
1416 + struct nvram_tuple *next;
1417 +};
1418 +
1419 +/*
1420 + * Initialize NVRAM access. May be unnecessary or undefined on certain
1421 + * platforms.
1422 + */
1423 +extern int BCMINIT(nvram_init)(void *sbh);
1424 +
1425 +/*
1426 + * Disable NVRAM access. May be unnecessary or undefined on certain
1427 + * platforms.
1428 + */
1429 +extern void BCMINIT(nvram_exit)(void);
1430 +
1431 +/*
1432 + * Get the value of an NVRAM variable. The pointer returned may be
1433 + * invalid after a set.
1434 + * @param name name of variable to get
1435 + * @return value of variable or NULL if undefined
1436 + */
1437 +extern char * BCMINIT(nvram_get)(const char *name);
1438 +
1439 +/*
1440 + * Get the value of an NVRAM variable.
1441 + * @param name name of variable to get
1442 + * @return value of variable or NUL if undefined
1443 + */
1444 +#define nvram_safe_get(name) (BCMINIT(nvram_get)(name) ? : "")
1445 +
1446 +/*
1447 + * Match an NVRAM variable.
1448 + * @param name name of variable to match
1449 + * @param match value to compare against value of variable
1450 + * @return TRUE if variable is defined and its value is string equal
1451 + * to match or FALSE otherwise
1452 + */
1453 +static INLINE int
1454 +nvram_match(char *name, char *match) {
1455 + const char *value = BCMINIT(nvram_get)(name);
1456 + return (value && !strcmp(value, match));
1457 +}
1458 +
1459 +/*
1460 + * Inversely match an NVRAM variable.
1461 + * @param name name of variable to match
1462 + * @param match value to compare against value of variable
1463 + * @return TRUE if variable is defined and its value is not string
1464 + * equal to invmatch or FALSE otherwise
1465 + */
1466 +static INLINE int
1467 +nvram_invmatch(char *name, char *invmatch) {
1468 + const char *value = BCMINIT(nvram_get)(name);
1469 + return (value && strcmp(value, invmatch));
1470 +}
1471 +
1472 +/*
1473 + * Set the value of an NVRAM variable. The name and value strings are
1474 + * copied into private storage. Pointers to previously set values
1475 + * may become invalid. The new value may be immediately
1476 + * retrieved but will not be permanently stored until a commit.
1477 + * @param name name of variable to set
1478 + * @param value value of variable
1479 + * @return 0 on success and errno on failure
1480 + */
1481 +extern int BCMINIT(nvram_set)(const char *name, const char *value);
1482 +
1483 +/*
1484 + * Unset an NVRAM variable. Pointers to previously set values
1485 + * remain valid until a set.
1486 + * @param name name of variable to unset
1487 + * @return 0 on success and errno on failure
1488 + * NOTE: use nvram_commit to commit this change to flash.
1489 + */
1490 +extern int BCMINIT(nvram_unset)(const char *name);
1491 +
1492 +/*
1493 + * Commit NVRAM variables to permanent storage. All pointers to values
1494 + * may be invalid after a commit.
1495 + * NVRAM values are undefined after a commit.
1496 + * @return 0 on success and errno on failure
1497 + */
1498 +extern int BCMINIT(nvram_commit)(void);
1499 +
1500 +/*
1501 + * Get all NVRAM variables (format name=value\0 ... \0\0).
1502 + * @param buf buffer to store variables
1503 + * @param count size of buffer in bytes
1504 + * @return 0 on success and errno on failure
1505 + */
1506 +extern int BCMINIT(nvram_getall)(char *buf, int count);
1507 +
1508 +#endif /* _LANGUAGE_ASSEMBLY */
1509 +
1510 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
1511 +#define NVRAM_VERSION 1
1512 +#define NVRAM_HEADER_SIZE 20
1513 +#define NVRAM_SPACE 0x8000
1514 +
1515 +#endif /* _bcmnvram_h_ */
1516 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bcmparams.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmparams.h
1517 --- linux-2.4.30/arch/mips/bcm947xx/include/bcmparams.h 1970-01-01 01:00:00.000000000 +0100
1518 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmparams.h 2005-02-02 23:16:39.000000000 +0100
1519 @@ -0,0 +1,23 @@
1520 +/*
1521 + * Misc system wide parameters.
1522 + *
1523 + * Copyright 2005, Broadcom Corporation
1524 + * All Rights Reserved.
1525 + *
1526 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1527 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1528 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1529 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1530 + * $Id$
1531 + */
1532 +
1533 +#ifndef _bcmparams_h_
1534 +#define _bcmparams_h_
1535 +
1536 +#define VLAN_MAXVID 15 /* Max. VLAN ID supported/allowed */
1537 +
1538 +#define VLAN_NUMPRIS 8 /* # of prio, start from 0 */
1539 +
1540 +#define DEV_NUMIFS 16 /* Max. # of devices/interfaces supported */
1541 +
1542 +#endif
1543 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bcmsrom.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmsrom.h
1544 --- linux-2.4.30/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
1545 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmsrom.h 2005-02-02 23:16:39.000000000 +0100
1546 @@ -0,0 +1,22 @@
1547 +/*
1548 + * Misc useful routines to access NIC local SROM/OTP .
1549 + *
1550 + * Copyright 2005, Broadcom Corporation
1551 + * All Rights Reserved.
1552 + *
1553 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1554 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1555 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1556 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1557 + *
1558 + * $Id$
1559 + */
1560 +
1561 +#ifndef _bcmsrom_h_
1562 +#define _bcmsrom_h_
1563 +
1564 +extern int srom_var_init(void *sbh, uint bus, void *curmap, void *osh, char **vars, int *count);
1565 +extern int srom_read(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf);
1566 +extern int srom_write(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf);
1567 +
1568 +#endif /* _bcmsrom_h_ */
1569 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bcmutils.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmutils.h
1570 --- linux-2.4.30/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
1571 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmutils.h 2005-02-02 23:16:39.000000000 +0100
1572 @@ -0,0 +1,239 @@
1573 +/*
1574 + * Misc useful os-independent macros and functions.
1575 + *
1576 + * Copyright 2005, Broadcom Corporation
1577 + * All Rights Reserved.
1578 + *
1579 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1580 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1581 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1582 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1583 + * $Id$
1584 + */
1585 +
1586 +#ifndef _bcmutils_h_
1587 +#define _bcmutils_h_
1588 +
1589 +/*** driver-only section ***/
1590 +#ifdef BCMDRIVER
1591 +#include <osl.h>
1592 +
1593 +#define _BCM_U 0x01 /* upper */
1594 +#define _BCM_L 0x02 /* lower */
1595 +#define _BCM_D 0x04 /* digit */
1596 +#define _BCM_C 0x08 /* cntrl */
1597 +#define _BCM_P 0x10 /* punct */
1598 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
1599 +#define _BCM_X 0x40 /* hex digit */
1600 +#define _BCM_SP 0x80 /* hard space (0x20) */
1601 +
1602 +extern unsigned char bcm_ctype[];
1603 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
1604 +
1605 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
1606 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
1607 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
1608 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
1609 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
1610 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
1611 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
1612 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
1613 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
1614 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
1615 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
1616 +
1617 +/*
1618 + * Spin at most 'us' microseconds while 'exp' is true.
1619 + * Caller should explicitly test 'exp' when this completes
1620 + * and take appropriate error action if 'exp' is still true.
1621 + */
1622 +#define SPINWAIT(exp, us) { \
1623 + uint countdown = (us) + 9; \
1624 + while ((exp) && (countdown >= 10)) {\
1625 + OSL_DELAY(10); \
1626 + countdown -= 10; \
1627 + } \
1628 +}
1629 +
1630 +/* generic osl packet queue */
1631 +struct pktq {
1632 + void *head; /* first packet to dequeue */
1633 + void *tail; /* last packet to dequeue */
1634 + uint len; /* number of queued packets */
1635 + uint maxlen; /* maximum number of queued packets */
1636 + bool priority; /* enqueue by packet priority */
1637 + uint8 prio_map[MAXPRIO+1]; /* user priority to packet enqueue policy map */
1638 +};
1639 +#define DEFAULT_QLEN 128
1640 +
1641 +#define pktq_len(q) ((q)->len)
1642 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
1643 +#define pktq_head(q) ((q)->head)
1644 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
1645 +#define _pktq_pri(q, pri) ((q)->prio_map[pri])
1646 +#define pktq_tailpri(q) ((q)->tail ? _pktq_pri(q, PKTPRIO((q)->tail)) : _pktq_pri(q, 0))
1647 +
1648 +/* externs */
1649 +/* packet */
1650 +extern uint pktcopy(void *drv, void *p, uint offset, int len, uchar *buf);
1651 +extern uint pkttotlen(void *drv, void *);
1652 +extern void pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[]);
1653 +extern void pktenq(struct pktq *q, void *p, bool lifo);
1654 +extern void *pktdeq(struct pktq *q);
1655 +extern void *pktdeqtail(struct pktq *q);
1656 +/* string */
1657 +extern uint bcm_atoi(char *s);
1658 +extern uchar bcm_toupper(uchar c);
1659 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
1660 +extern char *bcmstrstr(char *haystack, char *needle);
1661 +extern char *bcmstrcat(char *dest, const char *src);
1662 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
1663 +/* ethernet address */
1664 +extern char *bcm_ether_ntoa(char *ea, char *buf);
1665 +extern int bcm_ether_atoe(char *p, char *ea);
1666 +/* delay */
1667 +extern void bcm_mdelay(uint ms);
1668 +/* variable access */
1669 +extern char *getvar(char *vars, char *name);
1670 +extern int getintvar(char *vars, char *name);
1671 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
1672 +#define bcmlog(fmt, a1, a2)
1673 +#define bcmdumplog(buf, size) *buf = '\0'
1674 +#define bcmdumplogent(buf, idx) -1
1675 +#endif /* #ifdef BCMDRIVER */
1676 +
1677 +/*** driver/apps-shared section ***/
1678 +#ifndef MIN
1679 +#define MIN(a, b) (((a)<(b))?(a):(b))
1680 +#endif
1681 +
1682 +#ifndef MAX
1683 +#define MAX(a, b) (((a)>(b))?(a):(b))
1684 +#endif
1685 +
1686 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
1687 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
1688 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
1689 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
1690 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
1691 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
1692 +
1693 +/* bit map related macros */
1694 +#ifndef setbit
1695 +#define NBBY 8 /* 8 bits per byte */
1696 +#define setbit(a,i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
1697 +#define clrbit(a,i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
1698 +#define isset(a,i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
1699 +#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
1700 +#endif
1701 +
1702 +#define NBITS(type) (sizeof (type) * 8)
1703 +
1704 +/* crc defines */
1705 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
1706 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
1707 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
1708 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
1709 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
1710 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
1711 +
1712 +/* bcm_format_flags() bit description structure */
1713 +typedef struct bcm_bit_desc {
1714 + uint32 bit;
1715 + char* name;
1716 +} bcm_bit_desc_t;
1717 +
1718 +/* tag_ID/length/value_buffer tuple */
1719 +typedef struct bcm_tlv {
1720 + uint8 id;
1721 + uint8 len;
1722 + uint8 data[1];
1723 +} bcm_tlv_t;
1724 +
1725 +/* Check that bcm_tlv_t fits into the given buflen */
1726 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (buflen) >= 2 + (elt)->len)
1727 +
1728 +/* buffer length for ethernet address from bcm_ether_ntoa() */
1729 +#define ETHER_ADDR_STR_LEN 18
1730 +
1731 +/* unaligned load and store macros */
1732 +#ifdef IL_BIGENDIAN
1733 +static INLINE uint32
1734 +load32_ua(uint8 *a)
1735 +{
1736 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
1737 +}
1738 +
1739 +static INLINE void
1740 +store32_ua(uint8 *a, uint32 v)
1741 +{
1742 + a[0] = (v >> 24) & 0xff;
1743 + a[1] = (v >> 16) & 0xff;
1744 + a[2] = (v >> 8) & 0xff;
1745 + a[3] = v & 0xff;
1746 +}
1747 +
1748 +static INLINE uint16
1749 +load16_ua(uint8 *a)
1750 +{
1751 + return ((a[0] << 8) | a[1]);
1752 +}
1753 +
1754 +static INLINE void
1755 +store16_ua(uint8 *a, uint16 v)
1756 +{
1757 + a[0] = (v >> 8) & 0xff;
1758 + a[1] = v & 0xff;
1759 +}
1760 +
1761 +#else
1762 +
1763 +static INLINE uint32
1764 +load32_ua(uint8 *a)
1765 +{
1766 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
1767 +}
1768 +
1769 +static INLINE void
1770 +store32_ua(uint8 *a, uint32 v)
1771 +{
1772 + a[3] = (v >> 24) & 0xff;
1773 + a[2] = (v >> 16) & 0xff;
1774 + a[1] = (v >> 8) & 0xff;
1775 + a[0] = v & 0xff;
1776 +}
1777 +
1778 +static INLINE uint16
1779 +load16_ua(uint8 *a)
1780 +{
1781 + return ((a[1] << 8) | a[0]);
1782 +}
1783 +
1784 +static INLINE void
1785 +store16_ua(uint8 *a, uint16 v)
1786 +{
1787 + a[1] = (v >> 8) & 0xff;
1788 + a[0] = v & 0xff;
1789 +}
1790 +
1791 +#endif
1792 +
1793 +/* externs */
1794 +/* crc */
1795 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
1796 +extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
1797 +extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
1798 +/* format/print */
1799 +/* IE parsing */
1800 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
1801 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
1802 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
1803 +
1804 +/* multi-bool data type: set of bools, mbool is true if any is set */
1805 +typedef uint32 mbool;
1806 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
1807 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
1808 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
1809 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
1810 +
1811 +#endif /* _bcmutils_h_ */
1812 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bitfuncs.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bitfuncs.h
1813 --- linux-2.4.30/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
1814 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bitfuncs.h 2005-02-02 23:16:39.000000000 +0100
1815 @@ -0,0 +1,85 @@
1816 +/*
1817 + * bit manipulation utility functions
1818 + *
1819 + * Copyright 2005, Broadcom Corporation
1820 + * All Rights Reserved.
1821 + *
1822 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1823 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1824 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1825 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1826 + * $Id$
1827 + */
1828 +
1829 +#ifndef _BITFUNCS_H
1830 +#define _BITFUNCS_H
1831 +
1832 +#include <typedefs.h>
1833 +
1834 +/* local prototypes */
1835 +static INLINE uint32 find_msbit(uint32 x);
1836 +
1837 +
1838 +/*
1839 + * find_msbit: returns index of most significant set bit in x, with index
1840 + * range defined as 0-31. NOTE: returns zero if input is zero.
1841 + */
1842 +
1843 +#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
1844 +
1845 +/*
1846 + * Implementation for Pentium processors and gcc. Note that this
1847 + * instruction is actually very slow on some processors (e.g., family 5,
1848 + * model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
1849 + * implementation instead.
1850 + */
1851 +static INLINE uint32 find_msbit(uint32 x)
1852 +{
1853 + uint msbit;
1854 + __asm__("bsrl %1,%0"
1855 + :"=r" (msbit)
1856 + :"r" (x));
1857 + return msbit;
1858 +}
1859 +
1860 +#else
1861 +
1862 +/*
1863 + * Generic Implementation
1864 + */
1865 +
1866 +#define DB_POW_MASK16 0xffff0000
1867 +#define DB_POW_MASK8 0x0000ff00
1868 +#define DB_POW_MASK4 0x000000f0
1869 +#define DB_POW_MASK2 0x0000000c
1870 +#define DB_POW_MASK1 0x00000002
1871 +
1872 +static INLINE uint32 find_msbit(uint32 x)
1873 +{
1874 + uint32 temp_x = x;
1875 + uint msbit = 0;
1876 + if (temp_x & DB_POW_MASK16) {
1877 + temp_x >>= 16;
1878 + msbit = 16;
1879 + }
1880 + if (temp_x & DB_POW_MASK8) {
1881 + temp_x >>= 8;
1882 + msbit += 8;
1883 + }
1884 + if (temp_x & DB_POW_MASK4) {
1885 + temp_x >>= 4;
1886 + msbit += 4;
1887 + }
1888 + if (temp_x & DB_POW_MASK2) {
1889 + temp_x >>= 2;
1890 + msbit += 2;
1891 + }
1892 + if (temp_x & DB_POW_MASK1) {
1893 + msbit += 1;
1894 + }
1895 + return(msbit);
1896 +}
1897 +
1898 +#endif
1899 +
1900 +#endif /* _BITFUNCS_H */
1901 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/cfe_osl.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/cfe_osl.h
1902 --- linux-2.4.30/arch/mips/bcm947xx/include/cfe_osl.h 1970-01-01 01:00:00.000000000 +0100
1903 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/cfe_osl.h 2005-02-02 23:16:39.000000000 +0100
1904 @@ -0,0 +1,184 @@
1905 +/*
1906 + * CFE boot loader OS Abstraction Layer.
1907 + *
1908 + * Copyright 2005, Broadcom Corporation
1909 + * All Rights Reserved.
1910 + *
1911 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1912 + * the contents of this file may not be disclosed to third parties, copied
1913 + * or duplicated in any form, in whole or in part, without the prior
1914 + * written permission of Broadcom Corporation.
1915 + *
1916 + * $Id$
1917 + */
1918 +
1919 +#ifndef _cfe_osl_h_
1920 +#define _cfe_osl_h_
1921 +
1922 +#include <lib_types.h>
1923 +#include <lib_string.h>
1924 +#include <lib_printf.h>
1925 +#include <lib_malloc.h>
1926 +#include <cpu_config.h>
1927 +#include <cfe_timer.h>
1928 +#include <cfe_iocb.h>
1929 +#include <cfe_devfuncs.h>
1930 +#include <addrspace.h>
1931 +
1932 +#include <typedefs.h>
1933 +
1934 +/* dump string */
1935 +extern int (*xprinthook)(const char *str);
1936 +#define puts(str) do { if (xprinthook) xprinthook(str); } while (0)
1937 +
1938 +/* assert and panic */
1939 +#define ASSERT(exp) do {} while (0)
1940 +
1941 +/* PCMCIA attribute space access macros */
1942 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
1943 + bzero(buf, size)
1944 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
1945 + do {} while (0)
1946 +
1947 +/* PCI configuration space access macros */
1948 +#define OSL_PCI_READ_CONFIG(loc, offset, size) \
1949 + (offset == 8 ? 0 : 0xffffffff)
1950 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
1951 + do {} while (0)
1952 +
1953 +/* register access macros */
1954 +#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
1955 +#define rreg32(r) (*(volatile uint32*)(r))
1956 +#ifdef IL_BIGENDIAN
1957 +#define wreg16(r, v) (*(volatile uint16*)((ulong)(r)^2) = (uint16)(v))
1958 +#define rreg16(r) (*(volatile uint16*)((ulong)(r)^2))
1959 +#define wreg8(r, v) (*(volatile uint8*)((ulong)(r)^3) = (uint8)(v))
1960 +#define rreg8(r) (*(volatile uint8*)((ulong)(r)^3))
1961 +#else
1962 +#define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v))
1963 +#define rreg16(r) (*(volatile uint16*)(r))
1964 +#define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v))
1965 +#define rreg8(r) (*(volatile uint8*)(r))
1966 +#endif
1967 +#define R_REG(r) ({ \
1968 + __typeof(*(r)) __osl_v; \
1969 + switch (sizeof(*(r))) { \
1970 + case sizeof(uint8): __osl_v = rreg8((r)); break; \
1971 + case sizeof(uint16): __osl_v = rreg16((r)); break; \
1972 + case sizeof(uint32): __osl_v = rreg32((r)); break; \
1973 + } \
1974 + __osl_v; \
1975 +})
1976 +#define W_REG(r, v) do { \
1977 + switch (sizeof(*(r))) { \
1978 + case sizeof(uint8): wreg8((r), (v)); break; \
1979 + case sizeof(uint16): wreg16((r), (v)); break; \
1980 + case sizeof(uint32): wreg32((r), (v)); break; \
1981 + } \
1982 +} while (0)
1983 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
1984 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
1985 +
1986 +/* bcopy, bcmp, and bzero */
1987 +#define bcmp(b1, b2, len) lib_memcmp((b1), (b2), (len))
1988 +
1989 +#define osl_attach(pdev) (pdev)
1990 +#define osl_detach(osh)
1991 +
1992 +/* general purpose memory allocation */
1993 +#define MALLOC(osh, size) KMALLOC((size),0)
1994 +#define MFREE(osh, addr, size) KFREE((addr))
1995 +#define MALLOCED(osh) (0)
1996 +#define MALLOC_DUMP(osh, buf, sz)
1997 +#define MALLOC_FAILED(osh) (0)
1998 +
1999 +/* uncached virtual address */
2000 +#define OSL_UNCACHED(va) ((void*)UNCADDR((ulong)(va)))
2001 +
2002 +/* host/bus architecture-specific address byte swap */
2003 +#define BUS_SWAP32(v) (v)
2004 +
2005 +/* get processor cycle count */
2006 +#define OSL_GETCYCLES(x) ((x) = 0)
2007 +
2008 +/* microsecond delay */
2009 +#define OSL_DELAY(usec) cfe_usleep((cfe_cpu_speed/CPUCFG_CYCLESPERCPUTICK/1000000*(usec)))
2010 +
2011 +/* map/unmap physical to virtual I/O */
2012 +#define REG_MAP(pa, size) ((void*)UNCADDR((ulong)(pa)))
2013 +#define REG_UNMAP(va) do {} while (0)
2014 +
2015 +/* dereference an address that may cause a bus exception */
2016 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (uint32)(addr))
2017 +extern int osl_busprobe(uint32 *val, uint32 addr);
2018 +
2019 +/* allocate/free shared (dma-able) consistent (uncached) memory */
2020 +#define DMA_CONSISTENT_ALIGN 4096
2021 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
2022 + osl_dma_alloc_consistent((size), (pap))
2023 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
2024 + osl_dma_free_consistent((void*)(va))
2025 +extern void *osl_dma_alloc_consistent(uint size, ulong *pap);
2026 +extern void osl_dma_free_consistent(void *va);
2027 +
2028 +/* map/unmap direction */
2029 +#define DMA_TX 1
2030 +#define DMA_RX 2
2031 +
2032 +/* map/unmap shared (dma-able) memory */
2033 +#define DMA_MAP(osh, va, size, direction, lb) ({ \
2034 + cfe_flushcache(CFE_CACHE_FLUSH_D); \
2035 + PHYSADDR((ulong)(va)); \
2036 +})
2037 +#define DMA_UNMAP(osh, pa, size, direction, p) \
2038 + do {} while (0)
2039 +
2040 +/* shared (dma-able) memory access macros */
2041 +#define R_SM(r) *(r)
2042 +#define W_SM(r, v) (*(r) = (v))
2043 +#define BZERO_SM(r, len) lib_memset((r), '\0', (len))
2044 +
2045 +/* generic packet structure */
2046 +#define LBUFSZ 4096
2047 +#define LBDATASZ (LBUFSZ - sizeof(struct lbuf))
2048 +struct lbuf {
2049 + struct lbuf *next; /* pointer to next lbuf if in a chain */
2050 + struct lbuf *link; /* pointer to next lbuf if in a list */
2051 + uchar *head; /* start of buffer */
2052 + uchar *end; /* end of buffer */
2053 + uchar *data; /* start of data */
2054 + uchar *tail; /* end of data */
2055 + uint len; /* nbytes of data */
2056 + void *cookie; /* generic cookie */
2057 +};
2058 +
2059 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
2060 +#define PKTBUFSZ 2048
2061 +
2062 +/* packet primitives */
2063 +#define PKTGET(drv, len, send) ((void*)osl_pktget((len)))
2064 +#define PKTFREE(drv, lb, send) osl_pktfree((struct lbuf*)(lb))
2065 +#define PKTDATA(drv, lb) (((struct lbuf*)(lb))->data)
2066 +#define PKTLEN(drv, lb) (((struct lbuf*)(lb))->len)
2067 +#define PKTHEADROOM(drv, lb) (PKTDATA(drv,lb)-(((struct lbuf*)(lb))->head))
2068 +#define PKTTAILROOM(drv, lb) ((((struct lbuf*)(lb))->end)-(((struct lbuf*)(lb))->tail))
2069 +#define PKTNEXT(drv, lb) (((struct lbuf*)(lb))->next)
2070 +#define PKTSETNEXT(lb, x) (((struct lbuf*)(lb))->next = (struct lbuf*)(x))
2071 +#define PKTSETLEN(drv, lb, len) osl_pktsetlen((struct lbuf*)(lb), (len))
2072 +#define PKTPUSH(drv, lb, bytes) osl_pktpush((struct lbuf*)(lb), (bytes))
2073 +#define PKTPULL(drv, lb, bytes) osl_pktpull((struct lbuf*)(lb), (bytes))
2074 +#define PKTDUP(drv, lb) osl_pktdup((struct lbuf*)(lb))
2075 +#define PKTCOOKIE(lb) (((struct lbuf*)(lb))->cookie)
2076 +#define PKTSETCOOKIE(lb, x) (((struct lbuf*)(lb))->cookie = (void*)(x))
2077 +#define PKTLINK(lb) (((struct lbuf*)(lb))->link)
2078 +#define PKTSETLINK(lb, x) (((struct lbuf*)(lb))->link = (struct lbuf*)(x))
2079 +#define PKTPRIO(lb) (0)
2080 +#define PKTSETPRIO(lb, x) do {} while (0)
2081 +extern struct lbuf *osl_pktget(uint len);
2082 +extern void osl_pktfree(struct lbuf *lb);
2083 +extern void osl_pktsetlen(struct lbuf *lb, uint len);
2084 +extern uchar *osl_pktpush(struct lbuf *lb, uint bytes);
2085 +extern uchar *osl_pktpull(struct lbuf *lb, uint bytes);
2086 +extern struct lbuf *osl_pktdup(struct lbuf *lb);
2087 +
2088 +#endif /* _cfe_osl_h_ */
2089 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/epivers.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/epivers.h
2090 --- linux-2.4.30/arch/mips/bcm947xx/include/epivers.h 1970-01-01 01:00:00.000000000 +0100
2091 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/epivers.h 2005-02-02 23:16:39.000000000 +0100
2092 @@ -0,0 +1,69 @@
2093 +/*
2094 + * Copyright 2005, Broadcom Corporation
2095 + * All Rights Reserved.
2096 + *
2097 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2098 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2099 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2100 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2101 + *
2102 + * $Id$
2103 + *
2104 +*/
2105 +
2106 +#ifndef _epivers_h_
2107 +#define _epivers_h_
2108 +
2109 +#ifdef linux
2110 +#include <linux/config.h>
2111 +#endif
2112 +
2113 +/* Vendor Name, ASCII, 32 chars max */
2114 +#ifdef COMPANYNAME
2115 +#define HPNA_VENDOR COMPANYNAME
2116 +#else
2117 +#define HPNA_VENDOR "Broadcom Corporation"
2118 +#endif
2119 +
2120 +/* Driver Date, ASCII, 32 chars max */
2121 +#define HPNA_DRV_BUILD_DATE __DATE__
2122 +
2123 +/* Hardware Manufacture Date, ASCII, 32 chars max */
2124 +#define HPNA_HW_MFG_DATE "Not Specified"
2125 +
2126 +/* See documentation for Device Type values, 32 values max */
2127 +#ifndef HPNA_DEV_TYPE
2128 +
2129 +#if defined(CONFIG_BRCM_VJ)
2130 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
2131 +
2132 +#elif defined(CONFIG_BCRM_93725)
2133 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
2134 +
2135 +#else
2136 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
2137 +
2138 +#endif
2139 +
2140 +#endif /* !HPNA_DEV_TYPE */
2141 +
2142 +
2143 +#define EPI_MAJOR_VERSION 3
2144 +
2145 +#define EPI_MINOR_VERSION 90
2146 +
2147 +#define EPI_RC_NUMBER 23
2148 +
2149 +#define EPI_INCREMENTAL_NUMBER 0
2150 +
2151 +#define EPI_BUILD_NUMBER 0
2152 +
2153 +#define EPI_VERSION 3,90,23,0
2154 +
2155 +#define EPI_VERSION_NUM 0x035a1700
2156 +
2157 +/* Driver Version String, ASCII, 32 chars max */
2158 +#define EPI_VERSION_STR "3.90.23.0"
2159 +#define EPI_ROUTER_VERSION_STR "3.91.23.0"
2160 +
2161 +#endif /* _epivers_h_ */
2162 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/epivers.h.in linux-2.4.30-brcm/arch/mips/bcm947xx/include/epivers.h.in
2163 --- linux-2.4.30/arch/mips/bcm947xx/include/epivers.h.in 1970-01-01 01:00:00.000000000 +0100
2164 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/epivers.h.in 2005-02-02 23:16:39.000000000 +0100
2165 @@ -0,0 +1,69 @@
2166 +/*
2167 + * Copyright 2005, Broadcom Corporation
2168 + * All Rights Reserved.
2169 + *
2170 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2171 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2172 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2173 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2174 + *
2175 + * $Id$
2176 + *
2177 +*/
2178 +
2179 +#ifndef _epivers_h_
2180 +#define _epivers_h_
2181 +
2182 +#ifdef linux
2183 +#include <linux/config.h>
2184 +#endif
2185 +
2186 +/* Vendor Name, ASCII, 32 chars max */
2187 +#ifdef COMPANYNAME
2188 +#define HPNA_VENDOR COMPANYNAME
2189 +#else
2190 +#define HPNA_VENDOR "Broadcom Corporation"
2191 +#endif
2192 +
2193 +/* Driver Date, ASCII, 32 chars max */
2194 +#define HPNA_DRV_BUILD_DATE __DATE__
2195 +
2196 +/* Hardware Manufacture Date, ASCII, 32 chars max */
2197 +#define HPNA_HW_MFG_DATE "Not Specified"
2198 +
2199 +/* See documentation for Device Type values, 32 values max */
2200 +#ifndef HPNA_DEV_TYPE
2201 +
2202 +#if defined(CONFIG_BRCM_VJ)
2203 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
2204 +
2205 +#elif defined(CONFIG_BCRM_93725)
2206 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
2207 +
2208 +#else
2209 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
2210 +
2211 +#endif
2212 +
2213 +#endif /* !HPNA_DEV_TYPE */
2214 +
2215 +
2216 +#define EPI_MAJOR_VERSION @EPI_MAJOR_VERSION@
2217 +
2218 +#define EPI_MINOR_VERSION @EPI_MINOR_VERSION@
2219 +
2220 +#define EPI_RC_NUMBER @EPI_RC_NUMBER@
2221 +
2222 +#define EPI_INCREMENTAL_NUMBER @EPI_INCREMENTAL_NUMBER@
2223 +
2224 +#define EPI_BUILD_NUMBER @EPI_BUILD_NUMBER@
2225 +
2226 +#define EPI_VERSION @EPI_VERSION@
2227 +
2228 +#define EPI_VERSION_NUM @EPI_VERSION_NUM@
2229 +
2230 +/* Driver Version String, ASCII, 32 chars max */
2231 +#define EPI_VERSION_STR "@EPI_VERSION_STR@"
2232 +#define EPI_ROUTER_VERSION_STR "@EPI_ROUTER_VERSION_STR@"
2233 +
2234 +#endif /* _epivers_h_ */
2235 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/etsockio.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/etsockio.h
2236 --- linux-2.4.30/arch/mips/bcm947xx/include/etsockio.h 1970-01-01 01:00:00.000000000 +0100
2237 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/etsockio.h 2005-02-02 23:16:39.000000000 +0100
2238 @@ -0,0 +1,59 @@
2239 +/*
2240 + * Driver-specific socket ioctls
2241 + * used by BSD, Linux, and PSOS
2242 + * Broadcom BCM44XX 10/100Mbps Ethernet Device Driver
2243 + *
2244 + * Copyright 2005, Broadcom Corporation
2245 + * All Rights Reserved.
2246 + *
2247 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2248 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2249 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2250 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2251 + *
2252 + * $Id$
2253 + */
2254 +
2255 +#ifndef _etsockio_h_
2256 +#define _etsockio_h_
2257 +
2258 +/* THESE MUST BE CONTIGUOUS AND CONSISTENT WITH VALUES IN ETC.H */
2259 +
2260 +
2261 +#if defined(linux)
2262 +#define SIOCSETCUP (SIOCDEVPRIVATE + 0)
2263 +#define SIOCSETCDOWN (SIOCDEVPRIVATE + 1)
2264 +#define SIOCSETCLOOP (SIOCDEVPRIVATE + 2)
2265 +#define SIOCGETCDUMP (SIOCDEVPRIVATE + 3)
2266 +#define SIOCSETCSETMSGLEVEL (SIOCDEVPRIVATE + 4)
2267 +#define SIOCSETCPROMISC (SIOCDEVPRIVATE + 5)
2268 +#define SIOCSETCTXDOWN (SIOCDEVPRIVATE + 6) /* obsolete */
2269 +#define SIOCSETCSPEED (SIOCDEVPRIVATE + 7)
2270 +#define SIOCTXGEN (SIOCDEVPRIVATE + 8)
2271 +#define SIOCGETCPHYRD (SIOCDEVPRIVATE + 9)
2272 +#define SIOCSETCPHYWR (SIOCDEVPRIVATE + 10)
2273 +#define SIOCSETCQOS (SIOCDEVPRIVATE + 11)
2274 +
2275 +#else /* !linux */
2276 +
2277 +#define SIOCSETCUP _IOWR('e', 130 + 0, struct ifreq)
2278 +#define SIOCSETCDOWN _IOWR('e', 130 + 1, struct ifreq)
2279 +#define SIOCSETCLOOP _IOWR('e', 130 + 2, struct ifreq)
2280 +#define SIOCGETCDUMP _IOWR('e', 130 + 3, struct ifreq)
2281 +#define SIOCSETCSETMSGLEVEL _IOWR('e', 130 + 4, struct ifreq)
2282 +#define SIOCSETCPROMISC _IOWR('e', 130 + 5, struct ifreq)
2283 +#define SIOCSETCTXDOWN _IOWR('e', 130 + 6, struct ifreq) /* obsolete */
2284 +#define SIOCSETCSPEED _IOWR('e', 130 + 7, struct ifreq)
2285 +#define SIOCTXGEN _IOWR('e', 130 + 8, struct ifreq)
2286 +
2287 +#endif
2288 +
2289 +/* arg to SIOCTXGEN */
2290 +struct txg {
2291 + uint32 num; /* number of frames to send */
2292 + uint32 delay; /* delay in microseconds between sending each */
2293 + uint32 size; /* size of ether frame to send */
2294 + uchar buf[1514]; /* starting ether frame data */
2295 +};
2296 +
2297 +#endif
2298 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/flash.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/flash.h
2299 --- linux-2.4.30/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
2300 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/flash.h 2005-02-02 23:16:39.000000000 +0100
2301 @@ -0,0 +1,188 @@
2302 +/*
2303 + * flash.h: Common definitions for flash access.
2304 + *
2305 + * Copyright 2005, Broadcom Corporation
2306 + * All Rights Reserved.
2307 + *
2308 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2309 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2310 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2311 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2312 + *
2313 + * $Id$
2314 + */
2315 +
2316 +/* Types of flashes we know about */
2317 +typedef enum _flash_type {OLD, BSC, SCS, AMD, SST, SFLASH} flash_type_t;
2318 +
2319 +/* Commands to write/erase the flases */
2320 +typedef struct _flash_cmds{
2321 + flash_type_t type;
2322 + bool need_unlock;
2323 + uint16 pre_erase;
2324 + uint16 erase_block;
2325 + uint16 erase_chip;
2326 + uint16 write_word;
2327 + uint16 write_buf;
2328 + uint16 clear_csr;
2329 + uint16 read_csr;
2330 + uint16 read_id;
2331 + uint16 confirm;
2332 + uint16 read_array;
2333 +} flash_cmds_t;
2334 +
2335 +#define UNLOCK_CMD_WORDS 2
2336 +
2337 +typedef struct _unlock_cmd {
2338 + uint addr[UNLOCK_CMD_WORDS];
2339 + uint16 cmd[UNLOCK_CMD_WORDS];
2340 +} unlock_cmd_t;
2341 +
2342 +/* Flash descriptors */
2343 +typedef struct _flash_desc {
2344 + uint16 mfgid; /* Manufacturer Id */
2345 + uint16 devid; /* Device Id */
2346 + uint size; /* Total size in bytes */
2347 + uint width; /* Device width in bytes */
2348 + flash_type_t type; /* Device type old, S, J */
2349 + uint bsize; /* Block size */
2350 + uint nb; /* Number of blocks */
2351 + uint ff; /* First full block */
2352 + uint lf; /* Last full block */
2353 + uint nsub; /* Number of subblocks */
2354 + uint *subblocks; /* Offsets for subblocks */
2355 + char *desc; /* Description */
2356 +} flash_desc_t;
2357 +
2358 +
2359 +#ifdef DECLARE_FLASHES
2360 +flash_cmds_t sflash_cmd_t =
2361 + { SFLASH, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
2362 +
2363 +flash_cmds_t flash_cmds[] = {
2364 +/* type needu preera eraseb erasech write wbuf clcsr rdcsr rdid confrm read */
2365 + { BSC, 0, 0x00, 0x20, 0x00, 0x40, 0x00, 0x50, 0x70, 0x90, 0xd0, 0xff },
2366 + { SCS, 0, 0x00, 0x20, 0x00, 0x40, 0xe8, 0x50, 0x70, 0x90, 0xd0, 0xff },
2367 + { AMD, 1, 0x80, 0x30, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
2368 + { SST, 1, 0x80, 0x50, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
2369 + { 0 }
2370 +};
2371 +
2372 +unlock_cmd_t unlock_cmd_amd = {
2373 +#ifdef MIPSEB
2374 +/* addr: */ { 0x0aa8, 0x0556},
2375 +#else
2376 +/* addr: */ { 0x0aaa, 0x0554},
2377 +#endif
2378 +/* data: */ { 0xaa, 0x55}
2379 +};
2380 +
2381 +unlock_cmd_t unlock_cmd_sst = {
2382 +#ifdef MIPSEB
2383 +/* addr: */ { 0xaaa8, 0x5556},
2384 +#else
2385 +/* addr: */ { 0xaaaa, 0x5554},
2386 +#endif
2387 +/* data: */ { 0xaa, 0x55}
2388 +};
2389 +
2390 +#define AMD_CMD 0xaaa
2391 +#define SST_CMD 0xaaaa
2392 +
2393 +/* intel unlock block cmds */
2394 +#define INTEL_UNLOCK1 0x60
2395 +#define INTEL_UNLOCK2 0xD0
2396 +
2397 +/* Just eight blocks of 8KB byte each */
2398 +
2399 +uint blk8x8k[] = { 0x00000000,
2400 + 0x00002000,
2401 + 0x00004000,
2402 + 0x00006000,
2403 + 0x00008000,
2404 + 0x0000a000,
2405 + 0x0000c000,
2406 + 0x0000e000,
2407 + 0x00010000
2408 +};
2409 +
2410 +/* Funky AMD arrangement for 29xx800's */
2411 +uint amd800[] = { 0x00000000, /* 16KB */
2412 + 0x00004000, /* 32KB */
2413 + 0x0000c000, /* 8KB */
2414 + 0x0000e000, /* 8KB */
2415 + 0x00010000, /* 8KB */
2416 + 0x00012000, /* 8KB */
2417 + 0x00014000, /* 32KB */
2418 + 0x0001c000, /* 16KB */
2419 + 0x00020000
2420 +};
2421 +
2422 +/* AMD arrangement for 29xx160's */
2423 +uint amd4112[] = { 0x00000000, /* 32KB */
2424 + 0x00008000, /* 8KB */
2425 + 0x0000a000, /* 8KB */
2426 + 0x0000c000, /* 16KB */
2427 + 0x00010000
2428 +};
2429 +uint amd2114[] = { 0x00000000, /* 16KB */
2430 + 0x00004000, /* 8KB */
2431 + 0x00006000, /* 8KB */
2432 + 0x00008000, /* 32KB */
2433 + 0x00010000
2434 +};
2435 +
2436 +
2437 +flash_desc_t sflash_desc =
2438 + { 0, 0, 0, 0, SFLASH, 0, 0, 0, 0, 0, NULL, "SFLASH" };
2439 +
2440 +flash_desc_t flashes[] = {
2441 + { 0x00b0, 0x00d0, 0x0200000, 2, SCS, 0x10000, 32, 0, 31, 0, NULL, "Intel 28F160S3/5 1Mx16" },
2442 + { 0x00b0, 0x00d4, 0x0400000, 2, SCS, 0x10000, 64, 0, 63, 0, NULL, "Intel 28F320S3/5 2Mx16" },
2443 + { 0x0089, 0x8890, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160B3 1Mx16 TopB" },
2444 + { 0x0089, 0x8891, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160B3 1Mx16 BotB" },
2445 + { 0x0089, 0x8896, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320B3 2Mx16 TopB" },
2446 + { 0x0089, 0x8897, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320B3 2Mx16 BotB" },
2447 + { 0x0089, 0x8898, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640B3 4Mx16 TopB" },
2448 + { 0x0089, 0x8899, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640B3 4Mx16 BotB" },
2449 + { 0x0089, 0x88C2, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160C3 1Mx16 TopB" },
2450 + { 0x0089, 0x88C3, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160C3 1Mx16 BotB" },
2451 + { 0x0089, 0x88C4, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320C3 2Mx16 TopB" },
2452 + { 0x0089, 0x88C5, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320C3 2Mx16 BotB" },
2453 + { 0x0089, 0x88CC, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640C3 4Mx16 TopB" },
2454 + { 0x0089, 0x88CD, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640C3 4Mx16 BotB" },
2455 + { 0x0089, 0x0014, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J5 2Mx16" },
2456 + { 0x0089, 0x0015, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J5 4Mx16" },
2457 + { 0x0089, 0x0016, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J3 2Mx16" },
2458 + { 0x0089, 0x0017, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J3 4Mx16" },
2459 + { 0x0089, 0x0018, 0x1000000, 2, SCS, 0x20000, 128, 0, 127, 0, NULL, "Intel 28F128J3 8Mx16" },
2460 + { 0x00b0, 0x00e3, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Sharp 28F320BJE 2Mx16 BotB" },
2461 + { 0x0001, 0x224a, 0x0100000, 2, AMD, 0x10000, 16, 0, 13, 8, amd800, "AMD 29DL800BT 512Kx16 TopB" },
2462 + { 0x0001, 0x22cb, 0x0100000, 2, AMD, 0x10000, 16, 2, 15, 8, amd800, "AMD 29DL800BB 512Kx16 BotB" },
2463 + { 0x0001, 0x22c4, 0x0200000, 2, AMD, 0x10000, 32, 0, 30, 4, amd2114, "AMD 29lv160DT 1Mx16 TopB" },
2464 + { 0x0001, 0x2249, 0x0200000, 2, AMD, 0x10000, 32, 1, 31, 4, amd4112, "AMD 29lv160DB 1Mx16 BotB" },
2465 + { 0x0001, 0x22f6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320DT 2Mx16 TopB" },
2466 + { 0x0001, 0x22f9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320DB 2Mx16 BotB" },
2467 + { 0x0001, 0x2201, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320MT 2Mx16 TopB" },
2468 + { 0x0001, 0x2200, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320MB 2Mx16 BotB" },
2469 + { 0x0020, 0x22CA, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "ST 29w320DT 2Mx16 TopB" },
2470 + { 0x0020, 0x22CB, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "ST 29w320DB 2Mx16 BotB" },
2471 + { 0x00C2, 0x00A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
2472 + { 0x00C2, 0x00A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
2473 + { 0x0004, 0x22F6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MBM29LV320TE 2Mx16 TopB" },
2474 + { 0x0004, 0x22F9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MBM29LV320BE 2Mx16 BotB" },
2475 + { 0x0098, 0x009A, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "TC58FVT321 2Mx16 TopB" },
2476 + { 0x0098, 0x009C, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "TC58FVB321 2Mx16 BotB" },
2477 + { 0x00C2, 0x22A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
2478 + { 0x00C2, 0x22A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
2479 + { 0x00BF, 0x2783, 0x0400000, 2, SST, 0x10000, 64, 0, 63, 0, NULL, "SST39VF320 2Mx16" },
2480 + { 0, 0, 0, 0, OLD, 0, 0, 0, 0, 0, NULL, NULL },
2481 +};
2482 +
2483 +#else
2484 +
2485 +extern flash_cmds_t flash_cmds[];
2486 +extern unlock_cmd_t unlock_cmd;
2487 +extern flash_desc_t flashes[];
2488 +
2489 +#endif
2490 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/flashutl.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/flashutl.h
2491 --- linux-2.4.30/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
2492 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/flashutl.h 2005-02-02 23:16:39.000000000 +0100
2493 @@ -0,0 +1,27 @@
2494 +/*
2495 + * BCM47XX FLASH driver interface
2496 + *
2497 + * Copyright 2005, Broadcom Corporation
2498 + * All Rights Reserved.
2499 + *
2500 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2501 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2502 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2503 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2504 + * $Id$
2505 + */
2506 +
2507 +#ifndef _flashutl_h_
2508 +#define _flashutl_h_
2509 +
2510 +
2511 +#ifndef _LANGUAGE_ASSEMBLY
2512 +
2513 +int sysFlashInit(char *flash_str);
2514 +int sysFlashRead(uint off, uchar *dst, uint bytes);
2515 +int sysFlashWrite(uint off, uchar *src, uint bytes);
2516 +void nvWrite(unsigned short *data, unsigned int len);
2517 +
2518 +#endif /* _LANGUAGE_ASSEMBLY */
2519 +
2520 +#endif /* _flashutl_h_ */
2521 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/hnddma.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/hnddma.h
2522 --- linux-2.4.30/arch/mips/bcm947xx/include/hnddma.h 1970-01-01 01:00:00.000000000 +0100
2523 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/hnddma.h 2005-02-02 23:16:39.000000000 +0100
2524 @@ -0,0 +1,184 @@
2525 +/*
2526 + * Generic Broadcom Home Networking Division (HND) DMA engine definitions.
2527 + * This supports the following chips: BCM42xx, 44xx, 47xx .
2528 + *
2529 + * Copyright 2005, Broadcom Corporation
2530 + * All Rights Reserved.
2531 + *
2532 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2533 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2534 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2535 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2536 + * $Id$
2537 + */
2538 +
2539 +#ifndef _hnddma_h_
2540 +#define _hnddma_h_
2541 +
2542 +/*
2543 + * Each DMA processor consists of a transmit channel and a receive channel.
2544 + */
2545 +typedef volatile struct {
2546 + /* transmit channel */
2547 + uint32 xmtcontrol; /* enable, et al */
2548 + uint32 xmtaddr; /* descriptor ring base address (4K aligned) */
2549 + uint32 xmtptr; /* last descriptor posted to chip */
2550 + uint32 xmtstatus; /* current active descriptor, et al */
2551 +
2552 + /* receive channel */
2553 + uint32 rcvcontrol; /* enable, et al */
2554 + uint32 rcvaddr; /* descriptor ring base address (4K aligned) */
2555 + uint32 rcvptr; /* last descriptor posted to chip */
2556 + uint32 rcvstatus; /* current active descriptor, et al */
2557 +} dmaregs_t;
2558 +
2559 +typedef volatile struct {
2560 + /* diag access */
2561 + uint32 fifoaddr; /* diag address */
2562 + uint32 fifodatalow; /* low 32bits of data */
2563 + uint32 fifodatahigh; /* high 32bits of data */
2564 + uint32 pad; /* reserved */
2565 +} dmafifo_t;
2566 +
2567 +/* transmit channel control */
2568 +#define XC_XE ((uint32)1 << 0) /* transmit enable */
2569 +#define XC_SE ((uint32)1 << 1) /* transmit suspend request */
2570 +#define XC_LE ((uint32)1 << 2) /* loopback enable */
2571 +#define XC_FL ((uint32)1 << 4) /* flush request */
2572 +
2573 +/* transmit descriptor table pointer */
2574 +#define XP_LD_MASK 0xfff /* last valid descriptor */
2575 +
2576 +/* transmit channel status */
2577 +#define XS_CD_MASK 0x0fff /* current descriptor pointer */
2578 +#define XS_XS_MASK 0xf000 /* transmit state */
2579 +#define XS_XS_SHIFT 12
2580 +#define XS_XS_DISABLED 0x0000 /* disabled */
2581 +#define XS_XS_ACTIVE 0x1000 /* active */
2582 +#define XS_XS_IDLE 0x2000 /* idle wait */
2583 +#define XS_XS_STOPPED 0x3000 /* stopped */
2584 +#define XS_XS_SUSP 0x4000 /* suspend pending */
2585 +#define XS_XE_MASK 0xf0000 /* transmit errors */
2586 +#define XS_XE_SHIFT 16
2587 +#define XS_XE_NOERR 0x00000 /* no error */
2588 +#define XS_XE_DPE 0x10000 /* descriptor protocol error */
2589 +#define XS_XE_DFU 0x20000 /* data fifo underrun */
2590 +#define XS_XE_BEBR 0x30000 /* bus error on buffer read */
2591 +#define XS_XE_BEDA 0x40000 /* bus error on descriptor access */
2592 +#define XS_AD_MASK 0xfff00000 /* active descriptor */
2593 +#define XS_AD_SHIFT 20
2594 +
2595 +/* receive channel control */
2596 +#define RC_RE ((uint32)1 << 0) /* receive enable */
2597 +#define RC_RO_MASK 0xfe /* receive frame offset */
2598 +#define RC_RO_SHIFT 1
2599 +#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */
2600 +
2601 +/* receive descriptor table pointer */
2602 +#define RP_LD_MASK 0xfff /* last valid descriptor */
2603 +
2604 +/* receive channel status */
2605 +#define RS_CD_MASK 0x0fff /* current descriptor pointer */
2606 +#define RS_RS_MASK 0xf000 /* receive state */
2607 +#define RS_RS_SHIFT 12
2608 +#define RS_RS_DISABLED 0x0000 /* disabled */
2609 +#define RS_RS_ACTIVE 0x1000 /* active */
2610 +#define RS_RS_IDLE 0x2000 /* idle wait */
2611 +#define RS_RS_STOPPED 0x3000 /* reserved */
2612 +#define RS_RE_MASK 0xf0000 /* receive errors */
2613 +#define RS_RE_SHIFT 16
2614 +#define RS_RE_NOERR 0x00000 /* no error */
2615 +#define RS_RE_DPE 0x10000 /* descriptor protocol error */
2616 +#define RS_RE_DFO 0x20000 /* data fifo overflow */
2617 +#define RS_RE_BEBW 0x30000 /* bus error on buffer write */
2618 +#define RS_RE_BEDA 0x40000 /* bus error on descriptor access */
2619 +#define RS_AD_MASK 0xfff00000 /* active descriptor */
2620 +#define RS_AD_SHIFT 20
2621 +
2622 +/* fifoaddr */
2623 +#define FA_OFF_MASK 0xffff /* offset */
2624 +#define FA_SEL_MASK 0xf0000 /* select */
2625 +#define FA_SEL_SHIFT 16
2626 +#define FA_SEL_XDD 0x00000 /* transmit dma data */
2627 +#define FA_SEL_XDP 0x10000 /* transmit dma pointers */
2628 +#define FA_SEL_RDD 0x40000 /* receive dma data */
2629 +#define FA_SEL_RDP 0x50000 /* receive dma pointers */
2630 +#define FA_SEL_XFD 0x80000 /* transmit fifo data */
2631 +#define FA_SEL_XFP 0x90000 /* transmit fifo pointers */
2632 +#define FA_SEL_RFD 0xc0000 /* receive fifo data */
2633 +#define FA_SEL_RFP 0xd0000 /* receive fifo pointers */
2634 +
2635 +/*
2636 + * DMA Descriptor
2637 + * Descriptors are only read by the hardware, never written back.
2638 + */
2639 +typedef volatile struct {
2640 + uint32 ctrl; /* misc control bits & bufcount */
2641 + uint32 addr; /* data buffer address */
2642 +} dmadd_t;
2643 +
2644 +/*
2645 + * Each descriptor ring must be 4096byte aligned
2646 + * and fit within a single 4096byte page.
2647 + */
2648 +#define DMAMAXRINGSZ 4096
2649 +#define DMARINGALIGN 4096
2650 +
2651 +/* control flags */
2652 +#define CTRL_BC_MASK 0x1fff /* buffer byte count */
2653 +#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */
2654 +#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */
2655 +#define CTRL_EOF ((uint32)1 << 30) /* end of frame */
2656 +#define CTRL_SOF ((uint32)1 << 31) /* start of frame */
2657 +
2658 +/* control flags in the range [27:20] are core-specific and not defined here */
2659 +#define CTRL_CORE_MASK 0x0ff00000
2660 +
2661 +/* export structure */
2662 +typedef volatile struct {
2663 + /* rx error counters */
2664 + uint rxgiants; /* rx giant frames */
2665 + uint rxnobuf; /* rx out of dma descriptors */
2666 + /* tx error counters */
2667 + uint txnobuf; /* tx out of dma descriptors */
2668 +} hnddma_t;
2669 +
2670 +#ifndef di_t
2671 +#define di_t void
2672 +#endif
2673 +
2674 +/* externs */
2675 +extern void * dma_attach(void *drv, void *dev, char *name, dmaregs_t *dmaregs,
2676 + uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset,
2677 + uint ddoffset, uint dataoffset, uint *msg_level);
2678 +extern void dma_detach(di_t *di);
2679 +extern void dma_txreset(di_t *di);
2680 +extern void dma_rxreset(di_t *di);
2681 +extern void dma_txinit(di_t *di);
2682 +extern bool dma_txenabled(di_t *di);
2683 +extern void dma_rxinit(di_t *di);
2684 +extern void dma_rxenable(di_t *di);
2685 +extern bool dma_rxenabled(di_t *di);
2686 +extern void dma_txsuspend(di_t *di);
2687 +extern void dma_txresume(di_t *di);
2688 +extern bool dma_txsuspended(di_t *di);
2689 +extern bool dma_txstopped(di_t *di);
2690 +extern bool dma_rxstopped(di_t *di);
2691 +extern int dma_txfast(di_t *di, void *p, uint32 coreflags);
2692 +extern int dma_tx(di_t *di, void *p, uint32 coreflags);
2693 +extern void dma_fifoloopbackenable(di_t *di);
2694 +extern void *dma_rx(di_t *di);
2695 +extern void dma_rxfill(di_t *di);
2696 +extern void dma_txreclaim(di_t *di, bool forceall);
2697 +extern void dma_rxreclaim(di_t *di);
2698 +extern uintptr dma_getvar(di_t *di, char *name);
2699 +extern void *dma_getnexttxp(di_t *di, bool forceall);
2700 +extern void *dma_peeknexttxp(di_t *di);
2701 +extern void *dma_getnextrxp(di_t *di, bool forceall);
2702 +extern void dma_txblock(di_t *di);
2703 +extern void dma_txunblock(di_t *di);
2704 +extern uint dma_txactive(di_t *di);
2705 +extern void dma_txrotate(di_t *di);
2706 +
2707 +
2708 +#endif /* _hnddma_h_ */
2709 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/hndmips.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/hndmips.h
2710 --- linux-2.4.30/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
2711 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/hndmips.h 2005-02-02 23:16:39.000000000 +0100
2712 @@ -0,0 +1,16 @@
2713 +/*
2714 + * Alternate include file for HND sbmips.h since CFE also ships with
2715 + * a sbmips.h.
2716 + *
2717 + * Copyright 2005, Broadcom Corporation
2718 + * All Rights Reserved.
2719 + *
2720 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2721 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2722 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2723 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2724 + *
2725 + * $Id$
2726 + */
2727 +
2728 +#include "sbmips.h"
2729 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/linux_osl.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/linux_osl.h
2730 --- linux-2.4.30/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
2731 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/linux_osl.h 2005-02-02 23:16:39.000000000 +0100
2732 @@ -0,0 +1,341 @@
2733 +/*
2734 + * Linux OS Independent Layer
2735 + *
2736 + * Copyright 2005, Broadcom Corporation
2737 + * All Rights Reserved.
2738 + *
2739 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2740 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2741 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2742 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2743 + *
2744 + * $Id$
2745 + */
2746 +
2747 +#ifndef _linux_osl_h_
2748 +#define _linux_osl_h_
2749 +
2750 +#include <typedefs.h>
2751 +
2752 +/* use current 2.4.x calling conventions */
2753 +#include <linuxver.h>
2754 +
2755 +/* assert and panic */
2756 +#define ASSERT(exp) do {} while (0)
2757 +
2758 +/* PCMCIA attribute space access macros */
2759 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
2760 +struct pcmcia_dev {
2761 + dev_link_t link; /* PCMCIA device pointer */
2762 + dev_node_t node; /* PCMCIA node structure */
2763 + void *base; /* Mapped attribute memory window */
2764 + size_t size; /* Size of window */
2765 + void *drv; /* Driver data */
2766 +};
2767 +#endif
2768 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
2769 + osl_pcmcia_read_attr((osh), (offset), (buf), (size))
2770 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
2771 + osl_pcmcia_write_attr((osh), (offset), (buf), (size))
2772 +extern void osl_pcmcia_read_attr(void *osh, uint offset, void *buf, int size);
2773 +extern void osl_pcmcia_write_attr(void *osh, uint offset, void *buf, int size);
2774 +
2775 +/* PCI configuration space access macros */
2776 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
2777 + osl_pci_read_config((osh), (offset), (size))
2778 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
2779 + osl_pci_write_config((osh), (offset), (size), (val))
2780 +extern uint32 osl_pci_read_config(void *osh, uint size, uint offset);
2781 +extern void osl_pci_write_config(void *osh, uint offset, uint size, uint val);
2782 +
2783 +/* OSL initialization */
2784 +extern void *osl_attach(void *pdev);
2785 +extern void osl_detach(void *osh);
2786 +
2787 +/* host/bus architecture-specific byte swap */
2788 +#define BUS_SWAP32(v) (v)
2789 +
2790 +/* general purpose memory allocation */
2791 +
2792 +#if defined(BCMDBG_MEM)
2793 +
2794 +#define MALLOC(osh, size) osl_debug_malloc((osh), (size), __LINE__, __FILE__)
2795 +#define MFREE(osh, addr, size) osl_debug_mfree((osh), (addr), (size), __LINE__, __FILE__)
2796 +#define MALLOCED(osh) osl_malloced((osh))
2797 +#define MALLOC_DUMP(osh, buf, sz) osl_debug_memdump((osh), (buf), (sz))
2798 +extern void *osl_debug_malloc(void *osh, uint size, int line, char* file);
2799 +extern void osl_debug_mfree(void *osh, void *addr, uint size, int line, char* file);
2800 +extern char *osl_debug_memdump(void *osh, char *buf, uint sz);
2801 +
2802 +#else
2803 +
2804 +#define MALLOC(osh, size) osl_malloc((osh), (size))
2805 +#define MFREE(osh, addr, size) osl_mfree((osh), (addr), (size))
2806 +#define MALLOCED(osh) osl_malloced((osh))
2807 +
2808 +#endif /* BCMDBG_MEM */
2809 +
2810 +#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
2811 +
2812 +extern void *osl_malloc(void *osh, uint size);
2813 +extern void osl_mfree(void *osh, void *addr, uint size);
2814 +extern uint osl_malloced(void *osh);
2815 +extern uint osl_malloc_failed(void *osh);
2816 +
2817 +/* allocate/free shared (dma-able) consistent memory */
2818 +#define DMA_CONSISTENT_ALIGN PAGE_SIZE
2819 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
2820 + osl_dma_alloc_consistent((osh), (size), (pap))
2821 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
2822 + osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
2823 +extern void *osl_dma_alloc_consistent(void *osh, uint size, ulong *pap);
2824 +extern void osl_dma_free_consistent(void *osh, void *va, uint size, ulong pa);
2825 +
2826 +/* map/unmap direction */
2827 +#define DMA_TX 1
2828 +#define DMA_RX 2
2829 +
2830 +/* map/unmap shared (dma-able) memory */
2831 +#define DMA_MAP(osh, va, size, direction, p) \
2832 + osl_dma_map((osh), (va), (size), (direction))
2833 +#define DMA_UNMAP(osh, pa, size, direction, p) \
2834 + osl_dma_unmap((osh), (pa), (size), (direction))
2835 +extern uint osl_dma_map(void *osh, void *va, uint size, int direction);
2836 +extern void osl_dma_unmap(void *osh, uint pa, uint size, int direction);
2837 +
2838 +/* register access macros */
2839 +#if defined(BCMJTAG)
2840 +struct bcmjtag_info;
2841 +extern uint32 bcmjtag_read(struct bcmjtag_info *ejh, uint32 addr, uint size);
2842 +extern void bcmjtag_write(struct bcmjtag_info *ejh, uint32 addr, uint32 val, uint size);
2843 +#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
2844 +#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
2845 +#endif
2846 +
2847 +/*
2848 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
2849 + * Macros expand to calls to functions defined in linux_osl.c .
2850 + */
2851 +#ifndef BINOSL
2852 +
2853 +/* string library, kernel mode */
2854 +#define printf(fmt, args...) printk(fmt, ## args)
2855 +#include <linux/kernel.h>
2856 +#include <linux/string.h>
2857 +
2858 +/* register access macros */
2859 +#if !defined(BCMJTAG)
2860 +#define R_REG(r) ( \
2861 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
2862 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
2863 + readl((volatile uint32*)(r)) \
2864 +)
2865 +#define W_REG(r, v) do { \
2866 + switch (sizeof(*(r))) { \
2867 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
2868 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
2869 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
2870 + } \
2871 +} while (0)
2872 +#endif
2873 +
2874 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
2875 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
2876 +
2877 +/* bcopy, bcmp, and bzero */
2878 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
2879 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
2880 +#define bzero(b, len) memset((b), '\0', (len))
2881 +
2882 +/* uncached virtual address */
2883 +#ifdef mips
2884 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
2885 +#include <asm/addrspace.h>
2886 +#else
2887 +#define OSL_UNCACHED(va) (va)
2888 +#endif
2889 +
2890 +/* get processor cycle count */
2891 +#if defined(mips)
2892 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
2893 +#elif defined(__i386__)
2894 +#define OSL_GETCYCLES(x) rdtscl((x))
2895 +#else
2896 +#define OSL_GETCYCLES(x) ((x) = 0)
2897 +#endif
2898 +
2899 +/* dereference an address that may cause a bus exception */
2900 +#ifdef mips
2901 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
2902 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
2903 +#else
2904 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
2905 +#include <asm/paccess.h>
2906 +#endif
2907 +#else
2908 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
2909 +#endif
2910 +
2911 +/* map/unmap physical to virtual I/O */
2912 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
2913 +#define REG_UNMAP(va) iounmap((void *)(va))
2914 +
2915 +/* microsecond delay */
2916 +#define OSL_DELAY(usec) udelay(usec)
2917 +#include <linux/delay.h>
2918 +
2919 +/* shared (dma-able) memory access macros */
2920 +#define R_SM(r) *(r)
2921 +#define W_SM(r, v) (*(r) = (v))
2922 +#define BZERO_SM(r, len) memset((r), '\0', (len))
2923 +
2924 +/* packet primitives */
2925 +#define PKTGET(drv, len, send) osl_pktget((drv), (len), (send))
2926 +#define PKTFREE(drv, skb, send) osl_pktfree((skb))
2927 +#define PKTDATA(drv, skb) (((struct sk_buff*)(skb))->data)
2928 +#define PKTLEN(drv, skb) (((struct sk_buff*)(skb))->len)
2929 +#define PKTHEADROOM(drv, skb) (PKTDATA(drv,skb)-(((struct sk_buff*)(skb))->head))
2930 +#define PKTTAILROOM(drv, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
2931 +#define PKTNEXT(drv, skb) (((struct sk_buff*)(skb))->next)
2932 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
2933 +#define PKTSETLEN(drv, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
2934 +#define PKTPUSH(drv, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
2935 +#define PKTPULL(drv, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
2936 +#define PKTDUP(drv, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
2937 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
2938 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
2939 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
2940 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
2941 +#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
2942 +#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
2943 +extern void *osl_pktget(void *drv, uint len, bool send);
2944 +extern void osl_pktfree(void *skb);
2945 +
2946 +#else /* BINOSL */
2947 +
2948 +/* string library */
2949 +#ifndef LINUX_OSL
2950 +#undef printf
2951 +#define printf(fmt, args...) osl_printf((fmt), ## args)
2952 +#undef sprintf
2953 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
2954 +#undef strcmp
2955 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
2956 +#undef strncmp
2957 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
2958 +#undef strlen
2959 +#define strlen(s) osl_strlen((s))
2960 +#undef strcpy
2961 +#define strcpy(d, s) osl_strcpy((d), (s))
2962 +#undef strncpy
2963 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
2964 +#endif
2965 +extern int osl_printf(const char *format, ...);
2966 +extern int osl_sprintf(char *buf, const char *format, ...);
2967 +extern int osl_strcmp(const char *s1, const char *s2);
2968 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
2969 +extern int osl_strlen(char *s);
2970 +extern char* osl_strcpy(char *d, const char *s);
2971 +extern char* osl_strncpy(char *d, const char *s, uint n);
2972 +
2973 +/* register access macros */
2974 +#if !defined(BCMJTAG)
2975 +#define R_REG(r) ( \
2976 + sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
2977 + sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
2978 + osl_readl((volatile uint32*)(r)) \
2979 +)
2980 +#define W_REG(r, v) do { \
2981 + switch (sizeof(*(r))) { \
2982 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
2983 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
2984 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
2985 + } \
2986 +} while (0)
2987 +#endif
2988 +
2989 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
2990 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
2991 +extern uint8 osl_readb(volatile uint8 *r);
2992 +extern uint16 osl_readw(volatile uint16 *r);
2993 +extern uint32 osl_readl(volatile uint32 *r);
2994 +extern void osl_writeb(uint8 v, volatile uint8 *r);
2995 +extern void osl_writew(uint16 v, volatile uint16 *r);
2996 +extern void osl_writel(uint32 v, volatile uint32 *r);
2997 +
2998 +/* bcopy, bcmp, and bzero */
2999 +extern void bcopy(const void *src, void *dst, int len);
3000 +extern int bcmp(const void *b1, const void *b2, int len);
3001 +extern void bzero(void *b, int len);
3002 +
3003 +/* uncached virtual address */
3004 +#define OSL_UNCACHED(va) osl_uncached((va))
3005 +extern void *osl_uncached(void *va);
3006 +
3007 +/* get processor cycle count */
3008 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
3009 +extern uint osl_getcycles(void);
3010 +
3011 +/* dereference an address that may target abort */
3012 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
3013 +extern int osl_busprobe(uint32 *val, uint32 addr);
3014 +
3015 +/* map/unmap physical to virtual */
3016 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
3017 +#define REG_UNMAP(va) osl_reg_unmap((va))
3018 +extern void *osl_reg_map(uint32 pa, uint size);
3019 +extern void osl_reg_unmap(void *va);
3020 +
3021 +/* microsecond delay */
3022 +#define OSL_DELAY(usec) osl_delay((usec))
3023 +extern void osl_delay(uint usec);
3024 +
3025 +/* shared (dma-able) memory access macros */
3026 +#define R_SM(r) *(r)
3027 +#define W_SM(r, v) (*(r) = (v))
3028 +#define BZERO_SM(r, len) bzero((r), (len))
3029 +
3030 +/* packet primitives */
3031 +#define PKTGET(drv, len, send) osl_pktget((drv), (len), (send))
3032 +#define PKTFREE(drv, skb, send) osl_pktfree((skb))
3033 +#define PKTDATA(drv, skb) osl_pktdata((drv), (skb))
3034 +#define PKTLEN(drv, skb) osl_pktlen((drv), (skb))
3035 +#define PKTHEADROOM(drv, skb) osl_pktheadroom((drv), (skb))
3036 +#define PKTTAILROOM(drv, skb) osl_pkttailroom((drv), (skb))
3037 +#define PKTNEXT(drv, skb) osl_pktnext((drv), (skb))
3038 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
3039 +#define PKTSETLEN(drv, skb, len) osl_pktsetlen((drv), (skb), (len))
3040 +#define PKTPUSH(drv, skb, bytes) osl_pktpush((drv), (skb), (bytes))
3041 +#define PKTPULL(drv, skb, bytes) osl_pktpull((drv), (skb), (bytes))
3042 +#define PKTDUP(drv, skb) osl_pktdup((drv), (skb))
3043 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
3044 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
3045 +#define PKTLINK(skb) osl_pktlink((skb))
3046 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
3047 +#define PKTPRIO(skb) osl_pktprio((skb))
3048 +#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
3049 +extern void *osl_pktget(void *drv, uint len, bool send);
3050 +extern void osl_pktfree(void *skb);
3051 +extern uchar *osl_pktdata(void *drv, void *skb);
3052 +extern uint osl_pktlen(void *drv, void *skb);
3053 +extern uint osl_pktheadroom(void *drv, void *skb);
3054 +extern uint osl_pkttailroom(void *drv, void *skb);
3055 +extern void *osl_pktnext(void *drv, void *skb);
3056 +extern void osl_pktsetnext(void *skb, void *x);
3057 +extern void osl_pktsetlen(void *drv, void *skb, uint len);
3058 +extern uchar *osl_pktpush(void *drv, void *skb, int bytes);
3059 +extern uchar *osl_pktpull(void *drv, void *skb, int bytes);
3060 +extern void *osl_pktdup(void *drv, void *skb);
3061 +extern void *osl_pktcookie(void *skb);
3062 +extern void osl_pktsetcookie(void *skb, void *x);
3063 +extern void *osl_pktlink(void *skb);
3064 +extern void osl_pktsetlink(void *skb, void *x);
3065 +extern uint osl_pktprio(void *skb);
3066 +extern void osl_pktsetprio(void *skb, uint x);
3067 +
3068 +#endif /* BINOSL */
3069 +
3070 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
3071 +#define PKTBUFSZ 2048
3072 +
3073 +#endif /* _linux_osl_h_ */
3074 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/linuxver.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/linuxver.h
3075 --- linux-2.4.30/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
3076 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/linuxver.h 2005-02-02 23:16:39.000000000 +0100
3077 @@ -0,0 +1,399 @@
3078 +/*
3079 + * Linux-specific abstractions to gain some independence from linux kernel versions.
3080 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
3081 + *
3082 + * Copyright 2005, Broadcom Corporation
3083 + * All Rights Reserved.
3084 + *
3085 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3086 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3087 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3088 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3089 + *
3090 + * $Id$
3091 + */
3092 +
3093 +#ifndef _linuxver_h_
3094 +#define _linuxver_h_
3095 +
3096 +#include <linux/config.h>
3097 +#include <linux/version.h>
3098 +
3099 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
3100 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
3101 +#ifdef __UNDEF_NO_VERSION__
3102 +#undef __NO_VERSION__
3103 +#else
3104 +#define __NO_VERSION__
3105 +#endif
3106 +#endif
3107 +
3108 +#if defined(MODULE) && defined(MODVERSIONS)
3109 +#include <linux/modversions.h>
3110 +#endif
3111 +
3112 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
3113 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
3114 +#include <linux/malloc.h>
3115 +#else
3116 +#include <linux/slab.h>
3117 +#endif
3118 +
3119 +#include <linux/types.h>
3120 +#include <linux/init.h>
3121 +#include <linux/mm.h>
3122 +#include <linux/string.h>
3123 +#include <linux/pci.h>
3124 +#include <linux/interrupt.h>
3125 +#include <linux/netdevice.h>
3126 +#include <asm/io.h>
3127 +
3128 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41))
3129 +#include <linux/workqueue.h>
3130 +#else
3131 +#include <linux/tqueue.h>
3132 +#ifndef work_struct
3133 +#define work_struct tq_struct
3134 +#endif
3135 +#ifndef INIT_WORK
3136 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
3137 +#endif
3138 +#ifndef schedule_work
3139 +#define schedule_work(_work) schedule_task((_work))
3140 +#endif
3141 +#ifndef flush_scheduled_work
3142 +#define flush_scheduled_work() flush_scheduled_tasks()
3143 +#endif
3144 +#endif
3145 +
3146 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
3147 +/* Some distributions have their own 2.6.x compatibility layers */
3148 +#ifndef IRQ_NONE
3149 +typedef void irqreturn_t;
3150 +#define IRQ_NONE
3151 +#define IRQ_HANDLED
3152 +#define IRQ_RETVAL(x)
3153 +#endif
3154 +#endif
3155 +
3156 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
3157 +
3158 +#include <pcmcia/version.h>
3159 +#include <pcmcia/cs_types.h>
3160 +#include <pcmcia/cs.h>
3161 +#include <pcmcia/cistpl.h>
3162 +#include <pcmcia/cisreg.h>
3163 +#include <pcmcia/ds.h>
3164 +
3165 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,69))
3166 +/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
3167 + * does this, but it's not in 2.4 so we do our own for now. */
3168 +static inline void
3169 +cs_error(client_handle_t handle, int func, int ret)
3170 +{
3171 + error_info_t err = { func, ret };
3172 + CardServices(ReportError, handle, &err);
3173 +}
3174 +#endif
3175 +
3176 +#endif /* CONFIG_PCMCIA */
3177 +
3178 +#ifndef __exit
3179 +#define __exit
3180 +#endif
3181 +#ifndef __devexit
3182 +#define __devexit
3183 +#endif
3184 +#ifndef __devinit
3185 +#define __devinit __init
3186 +#endif
3187 +#ifndef __devinitdata
3188 +#define __devinitdata
3189 +#endif
3190 +#ifndef __devexit_p
3191 +#define __devexit_p(x) x
3192 +#endif
3193 +
3194 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
3195 +
3196 +#define pci_get_drvdata(dev) (dev)->sysdata
3197 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
3198 +
3199 +/*
3200 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
3201 + */
3202 +
3203 +struct pci_device_id {
3204 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
3205 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
3206 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
3207 + unsigned long driver_data; /* Data private to the driver */
3208 +};
3209 +
3210 +struct pci_driver {
3211 + struct list_head node;
3212 + char *name;
3213 + const struct pci_device_id *id_table; /* NULL if wants all devices */
3214 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
3215 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
3216 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
3217 + void (*resume)(struct pci_dev *dev); /* Device woken up */
3218 +};
3219 +
3220 +#define MODULE_DEVICE_TABLE(type, name)
3221 +#define PCI_ANY_ID (~0)
3222 +
3223 +/* compatpci.c */
3224 +#define pci_module_init pci_register_driver
3225 +extern int pci_register_driver(struct pci_driver *drv);
3226 +extern void pci_unregister_driver(struct pci_driver *drv);
3227 +
3228 +#endif /* PCI registration */
3229 +
3230 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
3231 +#ifdef MODULE
3232 +#define module_init(x) int init_module(void) { return x(); }
3233 +#define module_exit(x) void cleanup_module(void) { x(); }
3234 +#else
3235 +#define module_init(x) __initcall(x);
3236 +#define module_exit(x) __exitcall(x);
3237 +#endif
3238 +#endif
3239 +
3240 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
3241 +#define list_for_each(pos, head) \
3242 + for (pos = (head)->next; pos != (head); pos = pos->next)
3243 +#endif
3244 +
3245 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
3246 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
3247 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
3248 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
3249 +#endif
3250 +
3251 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
3252 +#define pci_enable_device(dev) do { } while (0)
3253 +#endif
3254 +
3255 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
3256 +#define net_device device
3257 +#endif
3258 +
3259 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
3260 +
3261 +/*
3262 + * DMA mapping
3263 + *
3264 + * See linux/Documentation/DMA-mapping.txt
3265 + */
3266 +
3267 +#ifndef PCI_DMA_TODEVICE
3268 +#define PCI_DMA_TODEVICE 1
3269 +#define PCI_DMA_FROMDEVICE 2
3270 +#endif
3271 +
3272 +typedef u32 dma_addr_t;
3273 +
3274 +/* Pure 2^n version of get_order */
3275 +static inline int get_order(unsigned long size)
3276 +{
3277 + int order;
3278 +
3279 + size = (size-1) >> (PAGE_SHIFT-1);
3280 + order = -1;
3281 + do {
3282 + size >>= 1;
3283 + order++;
3284 + } while (size);
3285 + return order;
3286 +}
3287 +
3288 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
3289 + dma_addr_t *dma_handle)
3290 +{
3291 + void *ret;
3292 + int gfp = GFP_ATOMIC | GFP_DMA;
3293 +
3294 + ret = (void *)__get_free_pages(gfp, get_order(size));
3295 +
3296 + if (ret != NULL) {
3297 + memset(ret, 0, size);
3298 + *dma_handle = virt_to_bus(ret);
3299 + }
3300 + return ret;
3301 +}
3302 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
3303 + void *vaddr, dma_addr_t dma_handle)
3304 +{
3305 + free_pages((unsigned long)vaddr, get_order(size));
3306 +}
3307 +#ifdef ILSIM
3308 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
3309 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
3310 +#else
3311 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
3312 +#define pci_unmap_single(cookie, address, size, dir)
3313 +#endif
3314 +
3315 +#endif /* DMA mapping */
3316 +
3317 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
3318 +
3319 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
3320 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
3321 +
3322 +/* pcmcia-cs provides its own netdevice compatibility layer */
3323 +#ifndef _COMPAT_NETDEVICE_H
3324 +
3325 +/*
3326 + * SoftNet
3327 + *
3328 + * For pre-softnet kernels we need to tell the upper layer not to
3329 + * re-enter start_xmit() while we are in there. However softnet
3330 + * guarantees not to enter while we are in there so there is no need
3331 + * to do the netif_stop_queue() dance unless the transmit queue really
3332 + * gets stuck. This should also improve performance according to tests
3333 + * done by Aman Singla.
3334 + */
3335 +
3336 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
3337 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
3338 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
3339 +
3340 +static inline void netif_start_queue(struct net_device *dev)
3341 +{
3342 + dev->tbusy = 0;
3343 + dev->interrupt = 0;
3344 + dev->start = 1;
3345 +}
3346 +
3347 +#define netif_queue_stopped(dev) (dev)->tbusy
3348 +#define netif_running(dev) (dev)->start
3349 +
3350 +#endif /* _COMPAT_NETDEVICE_H */
3351 +
3352 +#define netif_device_attach(dev) netif_start_queue(dev)
3353 +#define netif_device_detach(dev) netif_stop_queue(dev)
3354 +
3355 +/* 2.4.x renamed bottom halves to tasklets */
3356 +#define tasklet_struct tq_struct
3357 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
3358 +{
3359 + queue_task(tasklet, &tq_immediate);
3360 + mark_bh(IMMEDIATE_BH);
3361 +}
3362 +
3363 +static inline void tasklet_init(struct tasklet_struct *tasklet,
3364 + void (*func)(unsigned long),
3365 + unsigned long data)
3366 +{
3367 + tasklet->next = NULL;
3368 + tasklet->sync = 0;
3369 + tasklet->routine = (void (*)(void *))func;
3370 + tasklet->data = (void *)data;
3371 +}
3372 +#define tasklet_kill(tasklet) {do{} while(0);}
3373 +
3374 +/* 2.4.x introduced del_timer_sync() */
3375 +#define del_timer_sync(timer) del_timer(timer)
3376 +
3377 +#else
3378 +
3379 +#define netif_down(dev)
3380 +
3381 +#endif /* SoftNet */
3382 +
3383 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
3384 +
3385 +/*
3386 + * Emit code to initialise a tq_struct's routine and data pointers
3387 + */
3388 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
3389 + do { \
3390 + (_tq)->routine = _routine; \
3391 + (_tq)->data = _data; \
3392 + } while (0)
3393 +
3394 +/*
3395 + * Emit code to initialise all of a tq_struct
3396 + */
3397 +#define INIT_TQUEUE(_tq, _routine, _data) \
3398 + do { \
3399 + INIT_LIST_HEAD(&(_tq)->list); \
3400 + (_tq)->sync = 0; \
3401 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
3402 + } while (0)
3403 +
3404 +#endif
3405 +
3406 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
3407 +
3408 +/* Power management related routines */
3409 +
3410 +static inline int
3411 +pci_save_state(struct pci_dev *dev, u32 *buffer)
3412 +{
3413 + int i;
3414 + if (buffer) {
3415 + for (i = 0; i < 16; i++)
3416 + pci_read_config_dword(dev, i * 4,&buffer[i]);
3417 + }
3418 + return 0;
3419 +}
3420 +
3421 +static inline int
3422 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
3423 +{
3424 + int i;
3425 +
3426 + if (buffer) {
3427 + for (i = 0; i < 16; i++)
3428 + pci_write_config_dword(dev,i * 4, buffer[i]);
3429 + }
3430 + /*
3431 + * otherwise, write the context information we know from bootup.
3432 + * This works around a problem where warm-booting from Windows
3433 + * combined with a D3(hot)->D0 transition causes PCI config
3434 + * header data to be forgotten.
3435 + */
3436 + else {
3437 + for (i = 0; i < 6; i ++)
3438 + pci_write_config_dword(dev,
3439 + PCI_BASE_ADDRESS_0 + (i * 4),
3440 + pci_resource_start(dev, i));
3441 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
3442 + }
3443 + return 0;
3444 +}
3445 +
3446 +#endif /* PCI power management */
3447 +
3448 +/* Old cp0 access macros deprecated in 2.4.19 */
3449 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
3450 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
3451 +#endif
3452 +
3453 +/* Module refcount handled internally in 2.6.x */
3454 +#ifndef SET_MODULE_OWNER
3455 +#define SET_MODULE_OWNER(dev) do {} while (0)
3456 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
3457 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
3458 +#else
3459 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
3460 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
3461 +#endif
3462 +
3463 +#ifndef SET_NETDEV_DEV
3464 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
3465 +#endif
3466 +
3467 +#ifndef HAVE_FREE_NETDEV
3468 +#define free_netdev(dev) kfree(dev)
3469 +#endif
3470 +
3471 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
3472 +/* struct packet_type redefined in 2.6.x */
3473 +#define af_packet_priv data
3474 +#endif
3475 +
3476 +#endif /* _linuxver_h_ */
3477 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/min_osl.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/min_osl.h
3478 --- linux-2.4.30/arch/mips/bcm947xx/include/min_osl.h 1970-01-01 01:00:00.000000000 +0100
3479 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/min_osl.h 2005-05-25 03:31:09.000000000 +0200
3480 @@ -0,0 +1,120 @@
3481 +/*
3482 + * HND Minimal OS Abstraction Layer.
3483 + *
3484 + * Copyright 2005, Broadcom Corporation
3485 + * All Rights Reserved.
3486 + *
3487 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3488 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3489 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3490 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3491 + *
3492 + * $Id$
3493 + */
3494 +
3495 +#ifndef _min_osl_h_
3496 +#define _min_osl_h_
3497 +
3498 +#include <typedefs.h>
3499 +#include <sbconfig.h>
3500 +
3501 +/* Cache support */
3502 +extern void caches_on(void);
3503 +extern void blast_dcache(void);
3504 +extern void blast_icache(void);
3505 +
3506 +/* uart output */
3507 +extern void putc(int c);
3508 +
3509 +/* lib functions */
3510 +extern int printf(const char *fmt, ...);
3511 +extern int sprintf(char *buf, const char *fmt, ...);
3512 +extern int strcmp(const char *s1, const char *s2);
3513 +extern int strncmp(const char *s1, const char *s2, uint n);
3514 +extern char *strcpy(char *dest, const char *src);
3515 +extern char *strncpy(char *dest, const char *src, uint n);
3516 +extern uint strlen(const char *s);
3517 +extern char *strchr(const char *str,int c);
3518 +extern char *strrchr(const char *str, int c);
3519 +extern char *strcat(char *d, const char *s);
3520 +extern void *memset(void *dest, int c, uint n);
3521 +extern void *memcpy(void *dest, const void *src, uint n);
3522 +extern int memcmp(const void *s1, const void *s2, uint n);
3523 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
3524 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
3525 +#define bzero(b, len) memset((b), '\0', (len))
3526 +
3527 +/* assert & debugging */
3528 +#define ASSERT(exp) do {} while (0)
3529 +
3530 +/* PCMCIA attribute space access macros */
3531 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
3532 + ASSERT(0)
3533 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
3534 + ASSERT(0)
3535 +
3536 +/* PCI configuration space access macros */
3537 +#define OSL_PCI_READ_CONFIG(loc, offset, size) \
3538 + (offset == 8 ? 0 : 0xffffffff)
3539 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
3540 + do {} while (0)
3541 +
3542 +/* register access macros */
3543 +#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
3544 +#define rreg32(r) (*(volatile uint32*)(r))
3545 +#define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v))
3546 +#define rreg16(r) (*(volatile uint16*)(r))
3547 +#define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v))
3548 +#define rreg8(r) (*(volatile uint8*)(r))
3549 +#define R_REG(r) ({ \
3550 + __typeof(*(r)) __osl_v; \
3551 + switch (sizeof(*(r))) { \
3552 + case sizeof(uint8): __osl_v = rreg8((r)); break; \
3553 + case sizeof(uint16): __osl_v = rreg16((r)); break; \
3554 + case sizeof(uint32): __osl_v = rreg32((r)); break; \
3555 + } \
3556 + __osl_v; \
3557 +})
3558 +#define W_REG(r, v) do { \
3559 + switch (sizeof(*(r))) { \
3560 + case sizeof(uint8): wreg8((r), (v)); break; \
3561 + case sizeof(uint16): wreg16((r), (v)); break; \
3562 + case sizeof(uint32): wreg32((r), (v)); break; \
3563 + } \
3564 +} while (0)
3565 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
3566 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
3567 +
3568 +/* general purpose memory allocation */
3569 +#define MALLOC(osh, size) malloc(size)
3570 +#define MFREE(osh, addr, size) free(addr)
3571 +#define MALLOCED(osh) 0
3572 +#define MALLOC_FAILED(osh) 0
3573 +#define MALLOC_DUMP(osh, buf, sz)
3574 +extern int free(void *ptr);
3575 +extern void *malloc(uint size);
3576 +
3577 +/* uncached virtual address */
3578 +#define OSL_UNCACHED(va) ((void*)KSEG1ADDR((ulong)(va)))
3579 +
3580 +/* host/bus architecture-specific address byte swap */
3581 +#define BUS_SWAP32(v) (v)
3582 +
3583 +/* microsecond delay */
3584 +#define OSL_DELAY(usec) udelay(usec)
3585 +extern void udelay(uint32 usec);
3586 +
3587 +/* map/unmap physical to virtual I/O */
3588 +#define REG_MAP(pa, size) ((void*)KSEG1ADDR((ulong)(pa)))
3589 +#define REG_UNMAP(va) do {} while (0)
3590 +
3591 +/* dereference an address that may cause a bus exception */
3592 +#define BUSPROBE(val, addr) (uint32 *)(addr) = (val)
3593 +
3594 +/* Misc stubs */
3595 +#define osl_attach(pdev) (pdev)
3596 +#define osl_detach(osh)
3597 +extern void *osl_init(void);
3598 +extern int getintvar(char *vars, char *name);
3599 +
3600 +#endif /* _min_osl_h_ */
3601 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/mipsinc.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/mipsinc.h
3602 --- linux-2.4.30/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
3603 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/mipsinc.h 2005-05-26 02:34:15.000000000 +0200
3604 @@ -0,0 +1,524 @@
3605 +/*
3606 + * HND Run Time Environment for standalone MIPS programs.
3607 + *
3608 + * Copyright 2005, Broadcom Corporation
3609 + * All Rights Reserved.
3610 + *
3611 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3612 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3613 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3614 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3615 + *
3616 + * $Id$
3617 + */
3618 +
3619 +#ifndef _MISPINC_H
3620 +#define _MISPINC_H
3621 +
3622 +
3623 +/* MIPS defines */
3624 +
3625 +#ifdef _LANGUAGE_ASSEMBLY
3626 +
3627 +/*
3628 + * Symbolic register names for 32 bit ABI
3629 + */
3630 +#define zero $0 /* wired zero */
3631 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
3632 +#define v0 $2 /* return value */
3633 +#define v1 $3
3634 +#define a0 $4 /* argument registers */
3635 +#define a1 $5
3636 +#define a2 $6
3637 +#define a3 $7
3638 +#define t0 $8 /* caller saved */
3639 +#define t1 $9
3640 +#define t2 $10
3641 +#define t3 $11
3642 +#define t4 $12
3643 +#define t5 $13
3644 +#define t6 $14
3645 +#define t7 $15
3646 +#define s0 $16 /* callee saved */
3647 +#define s1 $17
3648 +#define s2 $18
3649 +#define s3 $19
3650 +#define s4 $20
3651 +#define s5 $21
3652 +#define s6 $22
3653 +#define s7 $23
3654 +#define t8 $24 /* caller saved */
3655 +#define t9 $25
3656 +#define jp $25 /* PIC jump register */
3657 +#define k0 $26 /* kernel scratch */
3658 +#define k1 $27
3659 +#define gp $28 /* global pointer */
3660 +#define sp $29 /* stack pointer */
3661 +#define fp $30 /* frame pointer */
3662 +#define s8 $30 /* same like fp! */
3663 +#define ra $31 /* return address */
3664 +
3665 +
3666 +/* *********************************************************************
3667 + * CP0 Registers
3668 + ********************************************************************* */
3669 +
3670 +#define C0_INX $0
3671 +#define C0_RAND $1
3672 +#define C0_TLBLO0 $2
3673 +#define C0_TLBLO C0_TLBLO0
3674 +#define C0_TLBLO1 $3
3675 +#define C0_CTEXT $4
3676 +#define C0_PGMASK $5
3677 +#define C0_WIRED $6
3678 +#define C0_BADVADDR $8
3679 +#define C0_COUNT $9
3680 +#define C0_TLBHI $10
3681 +#define C0_COMPARE $11
3682 +#define C0_SR $12
3683 +#define C0_STATUS C0_SR
3684 +#define C0_CAUSE $13
3685 +#define C0_EPC $14
3686 +#define C0_PRID $15
3687 +#define C0_CONFIG $16
3688 +#define C0_LLADDR $17
3689 +#define C0_WATCHLO $18
3690 +#define C0_WATCHHI $19
3691 +#define C0_XCTEXT $20
3692 +#define C0_DIAGNOSTIC $22
3693 +#define C0_BROADCOM C0_DIAGNOSTIC
3694 +#define C0_ECC $26
3695 +#define C0_CACHEERR $27
3696 +#define C0_TAGLO $28
3697 +#define C0_TAGHI $29
3698 +#define C0_ERREPC $30
3699 +#define C0_DESAVE $31
3700 +
3701 +/*
3702 + * LEAF - declare leaf routine
3703 + */
3704 +#define LEAF(symbol) \
3705 + .globl symbol; \
3706 + .align 2; \
3707 + .type symbol,@function; \
3708 + .ent symbol,0; \
3709 +symbol: .frame sp,0,ra
3710 +
3711 +/*
3712 + * END - mark end of function
3713 + */
3714 +#define END(function) \
3715 + .end function; \
3716 + .size function,.-function
3717 +
3718 +#define _ULCAST_
3719 +
3720 +#else
3721 +
3722 +/*
3723 + * The following macros are especially useful for __asm__
3724 + * inline assembler.
3725 + */
3726 +#ifndef __STR
3727 +#define __STR(x) #x
3728 +#endif
3729 +#ifndef STR
3730 +#define STR(x) __STR(x)
3731 +#endif
3732 +
3733 +#define _ULCAST_ (unsigned long)
3734 +
3735 +
3736 +/* *********************************************************************
3737 + * CP0 Registers
3738 + ********************************************************************* */
3739 +
3740 +#define C0_INX 0 /* CP0: TLB Index */
3741 +#define C0_RAND 1 /* CP0: TLB Random */
3742 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
3743 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
3744 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
3745 +#define C0_CTEXT 4 /* CP0: Context */
3746 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
3747 +#define C0_WIRED 6 /* CP0: TLB Wired */
3748 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
3749 +#define C0_COUNT 9 /* CP0: Count */
3750 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
3751 +#define C0_COMPARE 11 /* CP0: Compare */
3752 +#define C0_SR 12 /* CP0: Processor Status */
3753 +#define C0_STATUS C0_SR /* CP0: Processor Status */
3754 +#define C0_CAUSE 13 /* CP0: Exception Cause */
3755 +#define C0_EPC 14 /* CP0: Exception PC */
3756 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
3757 +#define C0_CONFIG 16 /* CP0: Config */
3758 +#define C0_LLADDR 17 /* CP0: LLAddr */
3759 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
3760 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
3761 +#define C0_XCTEXT 20 /* CP0: XContext */
3762 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
3763 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
3764 +#define C0_ECC 26 /* CP0: ECC */
3765 +#define C0_CACHEERR 27 /* CP0: CacheErr */
3766 +#define C0_TAGLO 28 /* CP0: TagLo */
3767 +#define C0_TAGHI 29 /* CP0: TagHi */
3768 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
3769 +#define C0_DESAVE 31 /* CP0: DebugSave */
3770 +
3771 +#endif /* _LANGUAGE_ASSEMBLY */
3772 +
3773 +/*
3774 + * Memory segments (32bit kernel mode addresses)
3775 + */
3776 +#undef KUSEG
3777 +#undef KSEG0
3778 +#undef KSEG1
3779 +#undef KSEG2
3780 +#undef KSEG3
3781 +#define KUSEG 0x00000000
3782 +#define KSEG0 0x80000000
3783 +#define KSEG1 0xa0000000
3784 +#define KSEG2 0xc0000000
3785 +#define KSEG3 0xe0000000
3786 +#define PHYSADDR_MASK 0x1fffffff
3787 +
3788 +/*
3789 + * Map an address to a certain kernel segment
3790 + */
3791 +#undef PHYSADDR
3792 +#undef KSEG0ADDR
3793 +#undef KSEG1ADDR
3794 +#undef KSEG2ADDR
3795 +#undef KSEG3ADDR
3796 +
3797 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
3798 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
3799 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
3800 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
3801 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
3802 +
3803 +
3804 +#ifndef Index_Invalidate_I
3805 +/*
3806 + * Cache Operations
3807 + */
3808 +#define Index_Invalidate_I 0x00
3809 +#define Index_Writeback_Inv_D 0x01
3810 +#define Index_Invalidate_SI 0x02
3811 +#define Index_Writeback_Inv_SD 0x03
3812 +#define Index_Load_Tag_I 0x04
3813 +#define Index_Load_Tag_D 0x05
3814 +#define Index_Load_Tag_SI 0x06
3815 +#define Index_Load_Tag_SD 0x07
3816 +#define Index_Store_Tag_I 0x08
3817 +#define Index_Store_Tag_D 0x09
3818 +#define Index_Store_Tag_SI 0x0A
3819 +#define Index_Store_Tag_SD 0x0B
3820 +#define Create_Dirty_Excl_D 0x0d
3821 +#define Create_Dirty_Excl_SD 0x0f
3822 +#define Hit_Invalidate_I 0x10
3823 +#define Hit_Invalidate_D 0x11
3824 +#define Hit_Invalidate_SI 0x12
3825 +#define Hit_Invalidate_SD 0x13
3826 +#define Fill_I 0x14
3827 +#define Hit_Writeback_Inv_D 0x15
3828 + /* 0x16 is unused */
3829 +#define Hit_Writeback_Inv_SD 0x17
3830 +#define R5K_Page_Invalidate_S 0x17
3831 +#define Hit_Writeback_I 0x18
3832 +#define Hit_Writeback_D 0x19
3833 + /* 0x1a is unused */
3834 +#define Hit_Writeback_SD 0x1b
3835 + /* 0x1c is unused */
3836 + /* 0x1e is unused */
3837 +#define Hit_Set_Virtual_SI 0x1e
3838 +#define Hit_Set_Virtual_SD 0x1f
3839 +#endif
3840 +
3841 +#ifndef _LANGUAGE_ASSEMBLY
3842 +
3843 +/*
3844 + * Macros to access the system control coprocessor
3845 + */
3846 +
3847 +#define MFC0(source, sel) \
3848 +({ \
3849 + int __res; \
3850 + __asm__ __volatile__( \
3851 + ".set\tnoreorder\n\t" \
3852 + ".set\tnoat\n\t" \
3853 + ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
3854 + "move\t%0,$1\n\t" \
3855 + ".set\tat\n\t" \
3856 + ".set\treorder" \
3857 + :"=r" (__res) \
3858 + : \
3859 + :"$1"); \
3860 + __res; \
3861 +})
3862 +
3863 +#define MTC0(source, sel, value) \
3864 +do { \
3865 + __asm__ __volatile__( \
3866 + ".set\tnoreorder\n\t" \
3867 + ".set\tnoat\n\t" \
3868 + "move\t$1,%z0\n\t" \
3869 + ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
3870 + ".set\tat\n\t" \
3871 + ".set\treorder" \
3872 + : \
3873 + :"jr" (value) \
3874 + :"$1"); \
3875 +} while (0)
3876 +
3877 +#define get_c0_count() \
3878 +({ \
3879 + int __res; \
3880 + __asm__ __volatile__( \
3881 + ".set\tnoreorder\n\t" \
3882 + ".set\tnoat\n\t" \
3883 + "mfc0\t%0,$9\n\t" \
3884 + ".set\tat\n\t" \
3885 + ".set\treorder" \
3886 + :"=r" (__res)); \
3887 + __res; \
3888 +})
3889 +
3890 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
3891 +{
3892 + uint lsz, sets, ways;
3893 +
3894 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
3895 + if ((lsz = ((config1 >> 19) & 7)))
3896 + lsz = 2 << lsz;
3897 + sets = 64 << ((config1 >> 22) & 7);
3898 + ways = 1 + ((config1 >> 16) & 7);
3899 + *size = lsz * sets * ways;
3900 + *lsize = lsz;
3901 +}
3902 +
3903 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
3904 +{
3905 + uint lsz, sets, ways;
3906 +
3907 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
3908 + if ((lsz = ((config1 >> 10) & 7)))
3909 + lsz = 2 << lsz;
3910 + sets = 64 << ((config1 >> 13) & 7);
3911 + ways = 1 + ((config1 >> 7) & 7);
3912 + *size = lsz * sets * ways;
3913 + *lsize = lsz;
3914 +}
3915 +
3916 +#define cache_unroll(base,op) \
3917 + __asm__ __volatile__(" \
3918 + .set noreorder; \
3919 + .set mips3; \
3920 + cache %1, (%0); \
3921 + .set mips0; \
3922 + .set reorder" \
3923 + : \
3924 + : "r" (base), \
3925 + "i" (op));
3926 +
3927 +#endif /* !_LANGUAGE_ASSEMBLY */
3928 +
3929 +
3930 +/*
3931 + * R4x00 interrupt enable / cause bits
3932 + */
3933 +#undef IE_SW0
3934 +#undef IE_SW1
3935 +#undef IE_IRQ0
3936 +#undef IE_IRQ1
3937 +#undef IE_IRQ2
3938 +#undef IE_IRQ3
3939 +#undef IE_IRQ4
3940 +#undef IE_IRQ5
3941 +#define IE_SW0 (1<< 8)
3942 +#define IE_SW1 (1<< 9)
3943 +#define IE_IRQ0 (1<<10)
3944 +#define IE_IRQ1 (1<<11)
3945 +#define IE_IRQ2 (1<<12)
3946 +#define IE_IRQ3 (1<<13)
3947 +#define IE_IRQ4 (1<<14)
3948 +#define IE_IRQ5 (1<<15)
3949 +
3950 +/*
3951 + * Bitfields in the mips32 cp0 status register
3952 + */
3953 +#define ST0_IE 0x00000001
3954 +#define ST0_EXL 0x00000002
3955 +#define ST0_ERL 0x00000004
3956 +/* already defined
3957 +#define ST0_UM 0x00000010
3958 +#define ST0_SWINT0 0x00000100
3959 +#define ST0_SWINT1 0x00000200
3960 +*/
3961 +#define ST0_HWINT0 0x00000400
3962 +#define ST0_HWINT1 0x00000800
3963 +#define ST0_HWINT2 0x00001000
3964 +#define ST0_HWINT3 0x00002000
3965 +#define ST0_HWINT4 0x00004000
3966 +#define ST0_HWINT5 0x00008000
3967 +#define ST0_IM 0x0000ff00
3968 +#define ST0_NMI 0x00080000
3969 +#define ST0_SR 0x00100000
3970 +#define ST0_TS 0x00200000
3971 +#define ST0_BEV 0x00400000
3972 +#define ST0_RE 0x02000000
3973 +#define ST0_RP 0x08000000
3974 +#define ST0_CU 0xf0000000
3975 +#define ST0_CU0 0x10000000
3976 +#define ST0_CU1 0x20000000
3977 +#define ST0_CU2 0x40000000
3978 +#define ST0_CU3 0x80000000
3979 +
3980 +
3981 +/*
3982 + * Bitfields in the mips32 cp0 cause register
3983 + */
3984 +#define C_EXC 0x0000007c
3985 +#define C_EXC_SHIFT 2
3986 +#define C_INT 0x0000ff00
3987 +#define C_INT_SHIFT 8
3988 +/* already defined
3989 +#define C_SW0 0x00000100
3990 +#define C_SW1 0x00000200
3991 +#define C_IRQ0 0x00000400
3992 +#define C_IRQ1 0x00000800
3993 +#define C_IRQ2 0x00001000
3994 +#define C_IRQ3 0x00002000
3995 +#define C_IRQ4 0x00004000
3996 +#define C_IRQ5 0x00008000
3997 +*/
3998 +#define C_WP 0x00400000
3999 +#define C_IV 0x00800000
4000 +#define C_CE 0x30000000
4001 +#define C_CE_SHIFT 28
4002 +#define C_BD 0x80000000
4003 +
4004 +/* Values in C_EXC */
4005 +#define EXC_INT 0
4006 +#define EXC_TLBM 1
4007 +#define EXC_TLBL 2
4008 +#define EXC_TLBS 3
4009 +#define EXC_AEL 4
4010 +#define EXC_AES 5
4011 +#define EXC_IBE 6
4012 +#define EXC_DBE 7
4013 +#define EXC_SYS 8
4014 +#define EXC_BPT 9
4015 +#define EXC_RI 10
4016 +#define EXC_CU 11
4017 +#define EXC_OV 12
4018 +#define EXC_TR 13
4019 +#define EXC_WATCH 23
4020 +#define EXC_MCHK 24
4021 +
4022 +
4023 +/*
4024 + * Bits in the cp0 config register.
4025 + */
4026 +#define CONF_CM_CACHABLE_NO_WA 0
4027 +#define CONF_CM_CACHABLE_WA 1
4028 +#define CONF_CM_UNCACHED 2
4029 +#define CONF_CM_CACHABLE_NONCOHERENT 3
4030 +#define CONF_CM_CACHABLE_CE 4
4031 +#define CONF_CM_CACHABLE_COW 5
4032 +#define CONF_CM_CACHABLE_CUW 6
4033 +#define CONF_CM_CACHABLE_ACCELERATED 7
4034 +#define CONF_CM_CMASK 7
4035 +#define CONF_CU (_ULCAST_(1) << 3)
4036 +#define CONF_DB (_ULCAST_(1) << 4)
4037 +#define CONF_IB (_ULCAST_(1) << 5)
4038 +#define CONF_SE (_ULCAST_(1) << 12)
4039 +#define CONF_SC (_ULCAST_(1) << 17)
4040 +#define CONF_AC (_ULCAST_(1) << 23)
4041 +#define CONF_HALT (_ULCAST_(1) << 25)
4042 +
4043 +
4044 +/*
4045 + * Bits in the cp0 config register select 1.
4046 + */
4047 +#define CONF1_FP 0x00000001 /* FPU present */
4048 +#define CONF1_EP 0x00000002 /* EJTAG present */
4049 +#define CONF1_CA 0x00000004 /* mips16 implemented */
4050 +#define CONF1_WR 0x00000008 /* Watch registers present */
4051 +#define CONF1_PC 0x00000010 /* Performance counters present */
4052 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
4053 +#define CONF1_DA_MASK 0x00000380
4054 +#define CONF1_DA_BASE 1
4055 +#define CONF1_DL_SHIFT 10 /* D$ line size */
4056 +#define CONF1_DL_MASK 0x00001c00
4057 +#define CONF1_DL_BASE 2
4058 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
4059 +#define CONF1_DS_MASK 0x0000e000
4060 +#define CONF1_DS_BASE 64
4061 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
4062 +#define CONF1_IA_MASK 0x00070000
4063 +#define CONF1_IA_BASE 1
4064 +#define CONF1_IL_SHIFT 19 /* I$ line size */
4065 +#define CONF1_IL_MASK 0x00380000
4066 +#define CONF1_IL_BASE 2
4067 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
4068 +#define CONF1_IS_MASK 0x01c00000
4069 +#define CONF1_IS_BASE 64
4070 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
4071 +#define CONF1_MS_SHIFT 25
4072 +
4073 +/* PRID register */
4074 +#define PRID_COPT_MASK 0xff000000
4075 +#define PRID_COMP_MASK 0x00ff0000
4076 +#define PRID_IMP_MASK 0x0000ff00
4077 +#define PRID_REV_MASK 0x000000ff
4078 +
4079 +#define PRID_COMP_LEGACY 0x000000
4080 +#define PRID_COMP_MIPS 0x010000
4081 +#define PRID_COMP_BROADCOM 0x020000
4082 +#define PRID_COMP_ALCHEMY 0x030000
4083 +#define PRID_COMP_SIBYTE 0x040000
4084 +#define PRID_IMP_BCM4710 0x4000
4085 +#define PRID_IMP_BCM3302 0x9000
4086 +#define PRID_IMP_BCM3303 0x9100
4087 +#define PRID_IMP_BCM3303 0x9100
4088 +
4089 +#define PRID_IMP_UNKNOWN 0xff00
4090 +
4091 +#define BCM330X(id) \
4092 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
4093 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
4094 +
4095 +/* Bits in C0_BROADCOM */
4096 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
4097 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
4098 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
4099 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
4100 +
4101 +/* PreFetch Cache aka Read Ahead Cache */
4102 +
4103 +#define PFC_CR0 0xff400000 /* control reg 0 */
4104 +#define PFC_CR1 0xff400004 /* control reg 1 */
4105 +
4106 +/*
4107 + * These are the UART port assignments, expressed as offsets from the base
4108 + * register. These assignments should hold for any serial port based on
4109 + * a 8250, 16450, or 16550(A).
4110 + */
4111 +
4112 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
4113 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
4114 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
4115 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
4116 +#define UART_LCR 3 /* Out: Line Control Register */
4117 +#define UART_MCR 4 /* Out: Modem Control Register */
4118 +#define UART_LSR 5 /* In: Line Status Register */
4119 +#define UART_MSR 6 /* In: Modem Status Register */
4120 +#define UART_SCR 7 /* I/O: Scratch Register */
4121 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
4122 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
4123 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
4124 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
4125 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
4126 +
4127 +
4128 +#endif /* _MISPINC_H */
4129 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/nvports.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/nvports.h
4130 --- linux-2.4.30/arch/mips/bcm947xx/include/nvports.h 1970-01-01 01:00:00.000000000 +0100
4131 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/nvports.h 2005-02-02 23:41:24.000000000 +0100
4132 @@ -0,0 +1,55 @@
4133 +/*
4134 + * BCM53xx RoboSwitch utility functions
4135 + *
4136 + * Copyright (C) 2002 Broadcom Corporation
4137 + * $Id$
4138 + */
4139 +
4140 +#ifndef _nvports_h_
4141 +#define _nvports_h_
4142 +
4143 +#define uint32 unsigned long
4144 +#define uint16 unsigned short
4145 +#define uint unsigned int
4146 +#define uint8 unsigned char
4147 +#define uint64 unsigned long long
4148 +
4149 +enum FORCE_PORT {
4150 + FORCE_OFF,
4151 + FORCE_10H,
4152 + FORCE_10F,
4153 + FORCE_100H,
4154 + FORCE_100F,
4155 + FORCE_DOWN,
4156 + POWER_OFF
4157 +};
4158 +
4159 +typedef struct _PORT_ATTRIBS
4160 +{
4161 + uint autoneg;
4162 + uint force;
4163 + uint native;
4164 +} PORT_ATTRIBS;
4165 +
4166 +extern uint
4167 +nvExistsPortAttrib(char *attrib, uint portno);
4168 +
4169 +extern int
4170 +nvExistsAnyForcePortAttrib(uint portno);
4171 +
4172 +extern void
4173 +nvSetPortAttrib(char *attrib, uint portno);
4174 +
4175 +extern void
4176 +nvUnsetPortAttrib(char *attrib, uint portno);
4177 +
4178 +extern void
4179 +nvUnsetAllForcePortAttrib(uint portno);
4180 +
4181 +extern PORT_ATTRIBS
4182 +nvGetSwitchPortAttribs(uint portno);
4183 +
4184 +#endif /* _nvports_h_ */
4185 +
4186 +
4187 +
4188 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/osl.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/osl.h
4189 --- linux-2.4.30/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
4190 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/osl.h 2005-02-02 23:16:39.000000000 +0100
4191 @@ -0,0 +1,39 @@
4192 +/*
4193 + * OS Independent Layer
4194 + *
4195 + * Copyright 2005, Broadcom Corporation
4196 + * All Rights Reserved.
4197 + *
4198 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4199 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4200 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4201 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4202 + * $Id$
4203 + */
4204 +
4205 +#ifndef _osl_h_
4206 +#define _osl_h_
4207 +
4208 +#if defined(linux)
4209 +#include <linux_osl.h>
4210 +#elif defined(NDIS)
4211 +#include <ndis_osl.h>
4212 +#elif defined(_CFE_)
4213 +#include <cfe_osl.h>
4214 +#elif defined(_HNDRTE_)
4215 +#include <hndrte_osl.h>
4216 +#elif defined(_MINOSL_)
4217 +#include <min_osl.h>
4218 +#elif PMON
4219 +#include <pmon_osl.h>
4220 +#elif defined(MACOSX)
4221 +#include <macosx_osl.h>
4222 +#else
4223 +#error "Unsupported OSL requested"
4224 +#endif
4225 +
4226 +/* handy */
4227 +#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
4228 +#define MAXPRIO 7 /* 0-7 */
4229 +
4230 +#endif /* _osl_h_ */
4231 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/pcicfg.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/pcicfg.h
4232 --- linux-2.4.30/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
4233 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/pcicfg.h 2005-02-02 23:16:39.000000000 +0100
4234 @@ -0,0 +1,369 @@
4235 +/*
4236 + * pcicfg.h: PCI configuration constants and structures.
4237 + *
4238 + * Copyright 2005, Broadcom Corporation
4239 + * All Rights Reserved.
4240 + *
4241 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4242 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4243 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4244 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4245 + *
4246 + * $Id$
4247 + */
4248 +
4249 +#ifndef _h_pci_
4250 +#define _h_pci_
4251 +
4252 +/* The following inside ifndef's so we don't collide with NTDDK.H */
4253 +#ifndef PCI_MAX_BUS
4254 +#define PCI_MAX_BUS 0x100
4255 +#endif
4256 +#ifndef PCI_MAX_DEVICES
4257 +#define PCI_MAX_DEVICES 0x20
4258 +#endif
4259 +#ifndef PCI_MAX_FUNCTION
4260 +#define PCI_MAX_FUNCTION 0x8
4261 +#endif
4262 +
4263 +#ifndef PCI_INVALID_VENDORID
4264 +#define PCI_INVALID_VENDORID 0xffff
4265 +#endif
4266 +#ifndef PCI_INVALID_DEVICEID
4267 +#define PCI_INVALID_DEVICEID 0xffff
4268 +#endif
4269 +
4270 +
4271 +/* Convert between bus-slot-function-register and config addresses */
4272 +
4273 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
4274 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
4275 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
4276 +#define PCICFG_OFF_SHIFT 0 /* Bus shift */
4277 +
4278 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
4279 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
4280 +#define PCICFG_FUN_MASK 7 /* Function mask */
4281 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
4282 +
4283 +#define PCI_CONFIG_ADDR(b, s, f, o) \
4284 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
4285 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
4286 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
4287 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
4288 +
4289 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
4290 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
4291 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
4292 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
4293 +
4294 +
4295 +/* The actual config space */
4296 +
4297 +#define PCI_BAR_MAX 6
4298 +
4299 +#define PCI_ROM_BAR 8
4300 +
4301 +#define PCR_RSVDA_MAX 2
4302 +
4303 +typedef struct _pci_config_regs {
4304 + unsigned short vendor;
4305 + unsigned short device;
4306 + unsigned short command;
4307 + unsigned short status;
4308 + unsigned char rev_id;
4309 + unsigned char prog_if;
4310 + unsigned char sub_class;
4311 + unsigned char base_class;
4312 + unsigned char cache_line_size;
4313 + unsigned char latency_timer;
4314 + unsigned char header_type;
4315 + unsigned char bist;
4316 + unsigned long base[PCI_BAR_MAX];
4317 + unsigned long cardbus_cis;
4318 + unsigned short subsys_vendor;
4319 + unsigned short subsys_id;
4320 + unsigned long baserom;
4321 + unsigned long rsvd_a[PCR_RSVDA_MAX];
4322 + unsigned char int_line;
4323 + unsigned char int_pin;
4324 + unsigned char min_gnt;
4325 + unsigned char max_lat;
4326 + unsigned char dev_dep[192];
4327 +} pci_config_regs;
4328 +
4329 +#define SZPCR (sizeof (pci_config_regs))
4330 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
4331 +
4332 +/* A structure for the config registers is nice, but in most
4333 + * systems the config space is not memory mapped, so we need
4334 + * filed offsetts. :-(
4335 + */
4336 +#define PCI_CFG_VID 0
4337 +#define PCI_CFG_DID 2
4338 +#define PCI_CFG_CMD 4
4339 +#define PCI_CFG_STAT 6
4340 +#define PCI_CFG_REV 8
4341 +#define PCI_CFG_PROGIF 9
4342 +#define PCI_CFG_SUBCL 0xa
4343 +#define PCI_CFG_BASECL 0xb
4344 +#define PCI_CFG_CLSZ 0xc
4345 +#define PCI_CFG_LATTIM 0xd
4346 +#define PCI_CFG_HDR 0xe
4347 +#define PCI_CFG_BIST 0xf
4348 +#define PCI_CFG_BAR0 0x10
4349 +#define PCI_CFG_BAR1 0x14
4350 +#define PCI_CFG_BAR2 0x18
4351 +#define PCI_CFG_BAR3 0x1c
4352 +#define PCI_CFG_BAR4 0x20
4353 +#define PCI_CFG_BAR5 0x24
4354 +#define PCI_CFG_CIS 0x28
4355 +#define PCI_CFG_SVID 0x2c
4356 +#define PCI_CFG_SSID 0x2e
4357 +#define PCI_CFG_ROMBAR 0x30
4358 +#define PCI_CFG_INT 0x3c
4359 +#define PCI_CFG_PIN 0x3d
4360 +#define PCI_CFG_MINGNT 0x3e
4361 +#define PCI_CFG_MAXLAT 0x3f
4362 +
4363 +/* Classes and subclasses */
4364 +
4365 +typedef enum {
4366 + PCI_CLASS_OLD = 0,
4367 + PCI_CLASS_DASDI,
4368 + PCI_CLASS_NET,
4369 + PCI_CLASS_DISPLAY,
4370 + PCI_CLASS_MMEDIA,
4371 + PCI_CLASS_MEMORY,
4372 + PCI_CLASS_BRIDGE,
4373 + PCI_CLASS_COMM,
4374 + PCI_CLASS_BASE,
4375 + PCI_CLASS_INPUT,
4376 + PCI_CLASS_DOCK,
4377 + PCI_CLASS_CPU,
4378 + PCI_CLASS_SERIAL,
4379 + PCI_CLASS_INTELLIGENT = 0xe,
4380 + PCI_CLASS_SATELLITE,
4381 + PCI_CLASS_CRYPT,
4382 + PCI_CLASS_DSP,
4383 + PCI_CLASS_MAX
4384 +} pci_classes;
4385 +
4386 +typedef enum {
4387 + PCI_DASDI_SCSI,
4388 + PCI_DASDI_IDE,
4389 + PCI_DASDI_FLOPPY,
4390 + PCI_DASDI_IPI,
4391 + PCI_DASDI_RAID,
4392 + PCI_DASDI_OTHER = 0x80
4393 +} pci_dasdi_subclasses;
4394 +
4395 +typedef enum {
4396 + PCI_NET_ETHER,
4397 + PCI_NET_TOKEN,
4398 + PCI_NET_FDDI,
4399 + PCI_NET_ATM,
4400 + PCI_NET_OTHER = 0x80
4401 +} pci_net_subclasses;
4402 +
4403 +typedef enum {
4404 + PCI_DISPLAY_VGA,
4405 + PCI_DISPLAY_XGA,
4406 + PCI_DISPLAY_3D,
4407 + PCI_DISPLAY_OTHER = 0x80
4408 +} pci_display_subclasses;
4409 +
4410 +typedef enum {
4411 + PCI_MMEDIA_VIDEO,
4412 + PCI_MMEDIA_AUDIO,
4413 + PCI_MMEDIA_PHONE,
4414 + PCI_MEDIA_OTHER = 0x80
4415 +} pci_mmedia_subclasses;
4416 +
4417 +typedef enum {
4418 + PCI_MEMORY_RAM,
4419 + PCI_MEMORY_FLASH,
4420 + PCI_MEMORY_OTHER = 0x80
4421 +} pci_memory_subclasses;
4422 +
4423 +typedef enum {
4424 + PCI_BRIDGE_HOST,
4425 + PCI_BRIDGE_ISA,
4426 + PCI_BRIDGE_EISA,
4427 + PCI_BRIDGE_MC,
4428 + PCI_BRIDGE_PCI,
4429 + PCI_BRIDGE_PCMCIA,
4430 + PCI_BRIDGE_NUBUS,
4431 + PCI_BRIDGE_CARDBUS,
4432 + PCI_BRIDGE_RACEWAY,
4433 + PCI_BRIDGE_OTHER = 0x80
4434 +} pci_bridge_subclasses;
4435 +
4436 +typedef enum {
4437 + PCI_COMM_UART,
4438 + PCI_COMM_PARALLEL,
4439 + PCI_COMM_MULTIUART,
4440 + PCI_COMM_MODEM,
4441 + PCI_COMM_OTHER = 0x80
4442 +} pci_comm_subclasses;
4443 +
4444 +typedef enum {
4445 + PCI_BASE_PIC,
4446 + PCI_BASE_DMA,
4447 + PCI_BASE_TIMER,
4448 + PCI_BASE_RTC,
4449 + PCI_BASE_PCI_HOTPLUG,
4450 + PCI_BASE_OTHER = 0x80
4451 +} pci_base_subclasses;
4452 +
4453 +typedef enum {
4454 + PCI_INPUT_KBD,
4455 + PCI_INPUT_PEN,
4456 + PCI_INPUT_MOUSE,
4457 + PCI_INPUT_SCANNER,
4458 + PCI_INPUT_GAMEPORT,
4459 + PCI_INPUT_OTHER = 0x80
4460 +} pci_input_subclasses;
4461 +
4462 +typedef enum {
4463 + PCI_DOCK_GENERIC,
4464 + PCI_DOCK_OTHER = 0x80
4465 +} pci_dock_subclasses;
4466 +
4467 +typedef enum {
4468 + PCI_CPU_386,
4469 + PCI_CPU_486,
4470 + PCI_CPU_PENTIUM,
4471 + PCI_CPU_ALPHA = 0x10,
4472 + PCI_CPU_POWERPC = 0x20,
4473 + PCI_CPU_MIPS = 0x30,
4474 + PCI_CPU_COPROC = 0x40,
4475 + PCI_CPU_OTHER = 0x80
4476 +} pci_cpu_subclasses;
4477 +
4478 +typedef enum {
4479 + PCI_SERIAL_IEEE1394,
4480 + PCI_SERIAL_ACCESS,
4481 + PCI_SERIAL_SSA,
4482 + PCI_SERIAL_USB,
4483 + PCI_SERIAL_FIBER,
4484 + PCI_SERIAL_SMBUS,
4485 + PCI_SERIAL_OTHER = 0x80
4486 +} pci_serial_subclasses;
4487 +
4488 +typedef enum {
4489 + PCI_INTELLIGENT_I2O,
4490 +} pci_intelligent_subclasses;
4491 +
4492 +typedef enum {
4493 + PCI_SATELLITE_TV,
4494 + PCI_SATELLITE_AUDIO,
4495 + PCI_SATELLITE_VOICE,
4496 + PCI_SATELLITE_DATA,
4497 + PCI_SATELLITE_OTHER = 0x80
4498 +} pci_satellite_subclasses;
4499 +
4500 +typedef enum {
4501 + PCI_CRYPT_NETWORK,
4502 + PCI_CRYPT_ENTERTAINMENT,
4503 + PCI_CRYPT_OTHER = 0x80
4504 +} pci_crypt_subclasses;
4505 +
4506 +typedef enum {
4507 + PCI_DSP_DPIO,
4508 + PCI_DSP_OTHER = 0x80
4509 +} pci_dsp_subclasses;
4510 +
4511 +/* Header types */
4512 +typedef enum {
4513 + PCI_HEADER_NORMAL,
4514 + PCI_HEADER_BRIDGE,
4515 + PCI_HEADER_CARDBUS
4516 +} pci_header_types;
4517 +
4518 +
4519 +/* Overlay for a PCI-to-PCI bridge */
4520 +
4521 +#define PPB_RSVDA_MAX 2
4522 +#define PPB_RSVDD_MAX 8
4523 +
4524 +typedef struct _ppb_config_regs {
4525 + unsigned short vendor;
4526 + unsigned short device;
4527 + unsigned short command;
4528 + unsigned short status;
4529 + unsigned char rev_id;
4530 + unsigned char prog_if;
4531 + unsigned char sub_class;
4532 + unsigned char base_class;
4533 + unsigned char cache_line_size;
4534 + unsigned char latency_timer;
4535 + unsigned char header_type;
4536 + unsigned char bist;
4537 + unsigned long rsvd_a[PPB_RSVDA_MAX];
4538 + unsigned char prim_bus;
4539 + unsigned char sec_bus;
4540 + unsigned char sub_bus;
4541 + unsigned char sec_lat;
4542 + unsigned char io_base;
4543 + unsigned char io_lim;
4544 + unsigned short sec_status;
4545 + unsigned short mem_base;
4546 + unsigned short mem_lim;
4547 + unsigned short pf_mem_base;
4548 + unsigned short pf_mem_lim;
4549 + unsigned long pf_mem_base_hi;
4550 + unsigned long pf_mem_lim_hi;
4551 + unsigned short io_base_hi;
4552 + unsigned short io_lim_hi;
4553 + unsigned short subsys_vendor;
4554 + unsigned short subsys_id;
4555 + unsigned long rsvd_b;
4556 + unsigned char rsvd_c;
4557 + unsigned char int_pin;
4558 + unsigned short bridge_ctrl;
4559 + unsigned char chip_ctrl;
4560 + unsigned char diag_ctrl;
4561 + unsigned short arb_ctrl;
4562 + unsigned long rsvd_d[PPB_RSVDD_MAX];
4563 + unsigned char dev_dep[192];
4564 +} ppb_config_regs;
4565 +
4566 +/* Eveything below is BRCM HND proprietary */
4567 +
4568 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
4569 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
4570 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
4571 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
4572 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
4573 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
4574 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
4575 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
4576 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
4577 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
4578 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
4579 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
4580 +
4581 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
4582 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
4583 +
4584 +/* PCI_INT_STATUS */
4585 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
4586 +
4587 +/* PCI_INT_MASK */
4588 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
4589 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
4590 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
4591 +
4592 +/* PCI_SPROM_CONTROL */
4593 +#define SPROM_BLANK 0x04 /* indicating a blank sprom */
4594 +#define SPROM_WRITEEN 0x10 /* sprom write enable */
4595 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
4596 +
4597 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
4598 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
4599 +
4600 +/* PCI_CFG_CMD_STAT */
4601 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
4602 +
4603 +#endif
4604 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/pmon_osl.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/pmon_osl.h
4605 --- linux-2.4.30/arch/mips/bcm947xx/include/pmon_osl.h 1970-01-01 01:00:00.000000000 +0100
4606 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/pmon_osl.h 2005-02-02 23:16:39.000000000 +0100
4607 @@ -0,0 +1,126 @@
4608 +/*
4609 + * MIPS PMON boot loader OS Abstraction Layer.
4610 + *
4611 + * Copyright 2005, Broadcom Corporation
4612 + * All Rights Reserved.
4613 + *
4614 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
4615 + * the contents of this file may not be disclosed to third parties, copied
4616 + * or duplicated in any form, in whole or in part, without the prior
4617 + * written permission of Broadcom Corporation.
4618 + * $Id$
4619 + */
4620 +
4621 +#ifndef _pmon_osl_h_
4622 +#define _pmon_osl_h_
4623 +
4624 +#include <typedefs.h>
4625 +#include <mips.h>
4626 +#include <string.h>
4627 +#include <utypes.h>
4628 +
4629 +extern int printf(char *fmt,...);
4630 +extern int sprintf(char *dst,char *fmt,...);
4631 +
4632 +#define OSL_UNCACHED(va) phy2k1(log2phy((va)))
4633 +#define REG_MAP(pa, size) phy2k1((pa))
4634 +#define REG_UNMAP(va) /* nop */
4635 +
4636 +/* Common macros */
4637 +
4638 +#define BUSPROBE(val, addr) ((val) = *(addr))
4639 +
4640 +#define ASSERT(exp)
4641 +
4642 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) bzero(buf, size)
4643 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size)
4644 +
4645 +/* kludge */
4646 +#define OSL_PCI_READ_CONFIG(loc, offset, size) ((offset == 8)? 0: 0xffffffff)
4647 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) ASSERT(0)
4648 +
4649 +#define wreg32(r,v) (*(volatile uint32 *)(r) = (v))
4650 +#define rreg32(r) (*(volatile uint32 *)(r))
4651 +#ifdef IL_BIGENDIAN
4652 +#define wreg16(r,v) (*(volatile uint16 *)((uint32)r^2) = (v))
4653 +#define rreg16(r) (*(volatile uint16 *)((uint32)r^2))
4654 +#else
4655 +#define wreg16(r,v) (*(volatile uint16 *)(r) = (v))
4656 +#define rreg16(r) (*(volatile uint16 *)(r))
4657 +#endif
4658 +
4659 +#include <memory.h>
4660 +#define bcopy(src, dst, len) memcpy(dst, src, len)
4661 +#define bcmp(b1, b2, len) memcmp(b1, b2, len)
4662 +#define bzero(b, len) memset(b, '\0', len)
4663 +
4664 +/* register access macros */
4665 +#define R_REG(r) ((sizeof *(r) == sizeof (uint32))? rreg32(r): rreg16(r))
4666 +#define W_REG(r,v) ((sizeof *(r) == sizeof (uint32))? wreg32(r,(uint32)v): wreg16(r,(uint16)v))
4667 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
4668 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
4669 +
4670 +#define R_SM(r) *(r)
4671 +#define W_SM(r, v) (*(r) = (v))
4672 +#define BZERO_SM(r, len) memset(r, '\0', len)
4673 +
4674 +/* Host/Bus architecture specific swap. Noop for little endian systems, possible swap on big endian */
4675 +#define BUS_SWAP32(v) (v)
4676 +
4677 +#define OSL_DELAY(usec) delay_us(usec)
4678 +extern void delay_us(uint usec);
4679 +
4680 +#define OSL_GETCYCLES(x) ((x) = 0)
4681 +
4682 +#define osl_attach(pdev) (pdev)
4683 +#define osl_detach(osh)
4684 +
4685 +#define MALLOC(osh, size) malloc(size)
4686 +#define MFREE(osh, addr, size) free(addr)
4687 +#define MALLOCED(osh) (0)
4688 +#define MALLOC_DUMP(osh, buf, sz)
4689 +#define MALLOC_FAILED(osh)
4690 +extern void *malloc();
4691 +extern void free(void *addr);
4692 +
4693 +#define DMA_CONSISTENT_ALIGN sizeof (int)
4694 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) et_dma_alloc_consistent(osh, size, pap)
4695 +#define DMA_FREE_CONSISTENT(osh, va, size, pa)
4696 +extern void* et_dma_alloc_consistent(void *osh, uint size, ulong *pap);
4697 +#define DMA_TX 0
4698 +#define DMA_RX 1
4699 +
4700 +#define DMA_MAP(osh, va, size, direction, p) osl_dma_map(osh, (void*)va, size, direction)
4701 +#define DMA_UNMAP(osh, pa, size, direction, p) /* nop */
4702 +extern void* osl_dma_map(void *osh, void *va, uint size, uint direction);
4703 +
4704 +struct lbuf {
4705 + struct lbuf *next; /* pointer to next lbuf on freelist */
4706 + uchar *buf; /* pointer to buffer */
4707 + uint len; /* nbytes of data */
4708 +};
4709 +
4710 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
4711 +#define PKTBUFSZ 2048
4712 +
4713 +/* packet primitives */
4714 +#define PKTGET(drv, len, send) et_pktget(drv, len, send)
4715 +#define PKTFREE(drv, lb, send) et_pktfree(drv, (struct lbuf*)lb, send)
4716 +#define PKTDATA(drv, lb) ((uchar*)OSL_UNCACHED(((struct lbuf*)lb)->buf))
4717 +#define PKTLEN(drv, lb) ((struct lbuf*)lb)->len
4718 +#define PKTHEADROOM(drv, lb) (0)
4719 +#define PKTTAILROOM(drv, lb) (0)
4720 +#define PKTNEXT(drv, lb) NULL
4721 +#define PKTSETNEXT(lb, x) ASSERT(0)
4722 +#define PKTSETLEN(drv, lb, bytes) ((struct lbuf*)lb)->len = bytes
4723 +#define PKTPUSH(drv, lb, bytes) ASSERT(0)
4724 +#define PKTPULL(drv, lb, bytes) ASSERT(0)
4725 +#define PKTDUP(drv, lb) ASSERT(0)
4726 +#define PKTLINK(lb) ((struct lbuf*)lb)->next
4727 +#define PKTSETLINK(lb, x) ((struct lbuf*)lb)->next = (struct lbuf*)x
4728 +#define PKTPRIO(lb) (0)
4729 +#define PKTSETPRIO(lb, x) do {} while (0)
4730 +extern void *et_pktget(void *drv, uint len, bool send);
4731 +extern void et_pktfree(void *drv, struct lbuf *lb, bool send);
4732 +
4733 +#endif /* _pmon_osl_h_ */
4734 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/proto/802.11.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/proto/802.11.h
4735 --- linux-2.4.30/arch/mips/bcm947xx/include/proto/802.11.h 1970-01-01 01:00:00.000000000 +0100
4736 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/proto/802.11.h 2005-02-02 23:16:40.000000000 +0100
4737 @@ -0,0 +1,897 @@
4738 +/*
4739 + * Copyright 2005, Broadcom Corporation
4740 + * All Rights Reserved.
4741 + *
4742 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4743 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4744 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4745 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4746 + *
4747 + * Fundamental types and constants relating to 802.11
4748 + *
4749 + * $Id$
4750 + */
4751 +
4752 +#ifndef _802_11_H_
4753 +#define _802_11_H_
4754 +
4755 +#ifndef _TYPEDEFS_H_
4756 +#include <typedefs.h>
4757 +#endif
4758 +
4759 +#ifndef _NET_ETHERNET_H_
4760 +#include <proto/ethernet.h>
4761 +#endif
4762 +
4763 +#include <proto/wpa.h>
4764 +
4765 +
4766 +/* enable structure packing */
4767 +#if defined(__GNUC__)
4768 +#define PACKED __attribute__((packed))
4769 +#else
4770 +#pragma pack(1)
4771 +#define PACKED
4772 +#endif
4773 +
4774 +#define DOT11_TU_TO_US 1024 /* 802.11 Time Unit is 1024 microseconds */
4775 +
4776 +/* Generic 802.11 frame constants */
4777 +#define DOT11_A3_HDR_LEN 24
4778 +#define DOT11_A4_HDR_LEN 30
4779 +#define DOT11_MAC_HDR_LEN DOT11_A3_HDR_LEN
4780 +#define DOT11_FCS_LEN 4
4781 +#define DOT11_ICV_LEN 4
4782 +#define DOT11_ICV_AES_LEN 8
4783 +#define DOT11_QOS_LEN 2
4784 +
4785 +#define DOT11_KEY_INDEX_SHIFT 6
4786 +#define DOT11_IV_LEN 4
4787 +#define DOT11_IV_TKIP_LEN 8
4788 +#define DOT11_IV_AES_OCB_LEN 4
4789 +#define DOT11_IV_AES_CCM_LEN 8
4790 +
4791 +/* Includes MIC */
4792 +#define DOT11_MAX_MPDU_BODY_LEN 2304
4793 +/* A4 header + QoS + CCMP + PDU + ICV + FCS = 2352 */
4794 +#define DOT11_MAX_MPDU_LEN (DOT11_A4_HDR_LEN + \
4795 + DOT11_QOS_LEN + \
4796 + DOT11_IV_AES_CCM_LEN + \
4797 + DOT11_MAX_MPDU_BODY_LEN + \
4798 + DOT11_ICV_LEN + \
4799 + DOT11_FCS_LEN)
4800 +
4801 +#define DOT11_MAX_SSID_LEN 32
4802 +
4803 +/* dot11RTSThreshold */
4804 +#define DOT11_DEFAULT_RTS_LEN 2347
4805 +#define DOT11_MAX_RTS_LEN 2347
4806 +
4807 +/* dot11FragmentationThreshold */
4808 +#define DOT11_MIN_FRAG_LEN 256
4809 +#define DOT11_MAX_FRAG_LEN 2346 /* Max frag is also limited by aMPDUMaxLength of the attached PHY */
4810 +#define DOT11_DEFAULT_FRAG_LEN 2346
4811 +
4812 +/* dot11BeaconPeriod */
4813 +#define DOT11_MIN_BEACON_PERIOD 1
4814 +#define DOT11_MAX_BEACON_PERIOD 0xFFFF
4815 +
4816 +/* dot11DTIMPeriod */
4817 +#define DOT11_MIN_DTIM_PERIOD 1
4818 +#define DOT11_MAX_DTIM_PERIOD 0xFF
4819 +
4820 +/* 802.2 LLC/SNAP header used by 802.11 per 802.1H */
4821 +#define DOT11_LLC_SNAP_HDR_LEN 8
4822 +#define DOT11_OUI_LEN 3
4823 +struct dot11_llc_snap_header {
4824 + uint8 dsap; /* always 0xAA */
4825 + uint8 ssap; /* always 0xAA */
4826 + uint8 ctl; /* always 0x03 */
4827 + uint8 oui[DOT11_OUI_LEN]; /* RFC1042: 0x00 0x00 0x00
4828 + Bridge-Tunnel: 0x00 0x00 0xF8 */
4829 + uint16 type; /* ethertype */
4830 +} PACKED;
4831 +
4832 +/* RFC1042 header used by 802.11 per 802.1H */
4833 +#define RFC1042_HDR_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN)
4834 +
4835 +/* Generic 802.11 MAC header */
4836 +/*
4837 + * N.B.: This struct reflects the full 4 address 802.11 MAC header.
4838 + * The fields are defined such that the shorter 1, 2, and 3
4839 + * address headers just use the first k fields.
4840 + */
4841 +struct dot11_header {
4842 + uint16 fc; /* frame control */
4843 + uint16 durid; /* duration/ID */
4844 + struct ether_addr a1; /* address 1 */
4845 + struct ether_addr a2; /* address 2 */
4846 + struct ether_addr a3; /* address 3 */
4847 + uint16 seq; /* sequence control */
4848 + struct ether_addr a4; /* address 4 */
4849 +} PACKED;
4850 +
4851 +/* Control frames */
4852 +
4853 +struct dot11_rts_frame {
4854 + uint16 fc; /* frame control */
4855 + uint16 durid; /* duration/ID */
4856 + struct ether_addr ra; /* receiver address */
4857 + struct ether_addr ta; /* transmitter address */
4858 +} PACKED;
4859 +#define DOT11_RTS_LEN 16
4860 +
4861 +struct dot11_cts_frame {
4862 + uint16 fc; /* frame control */
4863 + uint16 durid; /* duration/ID */
4864 + struct ether_addr ra; /* receiver address */
4865 +} PACKED;
4866 +#define DOT11_CTS_LEN 10
4867 +
4868 +struct dot11_ack_frame {
4869 + uint16 fc; /* frame control */
4870 + uint16 durid; /* duration/ID */
4871 + struct ether_addr ra; /* receiver address */
4872 +} PACKED;
4873 +#define DOT11_ACK_LEN 10
4874 +
4875 +struct dot11_ps_poll_frame {
4876 + uint16 fc; /* frame control */
4877 + uint16 durid; /* AID */
4878 + struct ether_addr bssid; /* receiver address, STA in AP */
4879 + struct ether_addr ta; /* transmitter address */
4880 +} PACKED;
4881 +#define DOT11_PS_POLL_LEN 16
4882 +
4883 +struct dot11_cf_end_frame {
4884 + uint16 fc; /* frame control */
4885 + uint16 durid; /* duration/ID */
4886 + struct ether_addr ra; /* receiver address */
4887 + struct ether_addr bssid; /* transmitter address, STA in AP */
4888 +} PACKED;
4889 +#define DOT11_CS_END_LEN 16
4890 +
4891 +/* Management frame header */
4892 +struct dot11_management_header {
4893 + uint16 fc; /* frame control */
4894 + uint16 durid; /* duration/ID */
4895 + struct ether_addr da; /* receiver address */
4896 + struct ether_addr sa; /* transmitter address */
4897 + struct ether_addr bssid; /* BSS ID */
4898 + uint16 seq; /* sequence control */
4899 +} PACKED;
4900 +#define DOT11_MGMT_HDR_LEN 24
4901 +
4902 +/* Management frame payloads */
4903 +
4904 +struct dot11_bcn_prb {
4905 + uint32 timestamp[2];
4906 + uint16 beacon_interval;
4907 + uint16 capability;
4908 +} PACKED;
4909 +#define DOT11_BCN_PRB_LEN 12
4910 +
4911 +struct dot11_auth {
4912 + uint16 alg; /* algorithm */
4913 + uint16 seq; /* sequence control */
4914 + uint16 status; /* status code */
4915 +} PACKED;
4916 +#define DOT11_AUTH_FIXED_LEN 6 /* length of auth frame without challenge info elt */
4917 +
4918 +struct dot11_assoc_req {
4919 + uint16 capability; /* capability information */
4920 + uint16 listen; /* listen interval */
4921 +} PACKED;
4922 +
4923 +struct dot11_assoc_resp {
4924 + uint16 capability; /* capability information */
4925 + uint16 status; /* status code */
4926 + uint16 aid; /* association ID */
4927 +} PACKED;
4928 +
4929 +struct dot11_action_measure {
4930 + uint8 category;
4931 + uint8 action;
4932 + uint8 token;
4933 + uint8 data[1];
4934 +} PACKED;
4935 +#define DOT11_ACTION_MEASURE_LEN 3
4936 +
4937 +/**************
4938 + 802.11h related definitions.
4939 +**************/
4940 +typedef struct {
4941 + uint8 id;
4942 + uint8 len;
4943 + uint8 power;
4944 +} dot11_power_cnst_t;
4945 +
4946 +typedef struct {
4947 + uint8 min;
4948 + uint8 max;
4949 +} dot11_power_cap_t;
4950 +
4951 +typedef struct {
4952 + uint8 id;
4953 + uint8 len;
4954 + uint8 tx_pwr;
4955 + uint8 margin;
4956 +} dot11_tpc_rep_t;
4957 +#define DOT11_MNG_IE_TPC_REPORT_LEN 2 /* length of IE data, not including 2 byte header */
4958 +
4959 +typedef struct {
4960 + uint8 id;
4961 + uint8 len;
4962 + uint8 first_channel;
4963 + uint8 num_channels;
4964 +} dot11_supp_channels_t;
4965 +
4966 +struct dot11_channel_switch {
4967 + uint8 id;
4968 + uint8 len;
4969 + uint8 mode;
4970 + uint8 channel;
4971 + uint8 count;
4972 +} PACKED;
4973 +typedef struct dot11_channel_switch dot11_channel_switch_t;
4974 +
4975 +/* 802.11h Measurement Request/Report IEs */
4976 +/* Measurement Type field */
4977 +#define DOT11_MEASURE_TYPE_BASIC 0
4978 +#define DOT11_MEASURE_TYPE_CCA 1
4979 +#define DOT11_MEASURE_TYPE_RPI 2
4980 +
4981 +/* Measurement Mode field */
4982 +
4983 +/* Measurement Request Modes */
4984 +#define DOT11_MEASURE_MODE_ENABLE (1<<1)
4985 +#define DOT11_MEASURE_MODE_REQUEST (1<<2)
4986 +#define DOT11_MEASURE_MODE_REPORT (1<<3)
4987 +/* Measurement Report Modes */
4988 +#define DOT11_MEASURE_MODE_LATE (1<<0)
4989 +#define DOT11_MEASURE_MODE_INCAPABLE (1<<1)
4990 +#define DOT11_MEASURE_MODE_REFUSED (1<<2)
4991 +/* Basic Measurement Map bits */
4992 +#define DOT11_MEASURE_BASIC_MAP_BSS ((uint8)(1<<0))
4993 +#define DOT11_MEASURE_BASIC_MAP_OFDM ((uint8)(1<<1))
4994 +#define DOT11_MEASURE_BASIC_MAP_UKNOWN ((uint8)(1<<2))
4995 +#define DOT11_MEASURE_BASIC_MAP_RADAR ((uint8)(1<<3))
4996 +#define DOT11_MEASURE_BASIC_MAP_UNMEAS ((uint8)(1<<4))
4997 +
4998 +typedef struct {
4999 + uint8 id;
5000 + uint8 len;
5001 + uint8 token;
5002 + uint8 mode;
5003 + uint8 type;
5004 + uint8 channel;
5005 + uint8 start_time[8];
5006 + uint16 duration;
5007 +} dot11_meas_req_t;
5008 +#define DOT11_MNG_IE_MREQ_LEN 14
5009 +/* length of Measure Request IE data not including variable len */
5010 +#define DOT11_MNG_IE_MREQ_FIXED_LEN 3
5011 +
5012 +struct dot11_meas_rep {
5013 + uint8 id;
5014 + uint8 len;
5015 + uint8 token;
5016 + uint8 mode;
5017 + uint8 type;
5018 + union
5019 + {
5020 + struct {
5021 + uint8 channel;
5022 + uint8 start_time[8];
5023 + uint16 duration;
5024 + uint8 map;
5025 + } PACKED basic;
5026 + uint8 data[1];
5027 + } PACKED rep;
5028 +} PACKED;
5029 +typedef struct dot11_meas_rep dot11_meas_rep_t;
5030 +
5031 +/* length of Measure Report IE data not including variable len */
5032 +#define DOT11_MNG_IE_MREP_FIXED_LEN 3
5033 +
5034 +struct dot11_meas_rep_basic {
5035 + uint8 channel;
5036 + uint8 start_time[8];
5037 + uint16 duration;
5038 + uint8 map;
5039 +} PACKED;
5040 +typedef struct dot11_meas_rep_basic dot11_meas_rep_basic_t;
5041 +#define DOT11_MEASURE_BASIC_REP_LEN 12
5042 +
5043 +struct dot11_quiet {
5044 + uint8 id;
5045 + uint8 len;
5046 + uint8 count; /* TBTTs until beacon interval in quiet starts */
5047 + uint8 period; /* Beacon intervals between periodic quiet periods ? */
5048 + uint16 duration;/* Length of quiet period, in TU's */
5049 + uint16 offset; /* TU's offset from TBTT in Count field */
5050 +} PACKED;
5051 +typedef struct dot11_quiet dot11_quiet_t;
5052 +
5053 +typedef struct {
5054 + uint8 channel;
5055 + uint8 map;
5056 +} chan_map_tuple_t;
5057 +
5058 +typedef struct {
5059 + uint8 id;
5060 + uint8 len;
5061 + uint8 eaddr[ETHER_ADDR_LEN];
5062 + uint8 interval;
5063 + chan_map_tuple_t map[1];
5064 +} dot11_ibss_dfs_t;
5065 +
5066 +/* WME Elements */
5067 +#define WME_OUI "\x00\x50\xf2"
5068 +#define WME_VER 1
5069 +#define WME_TYPE 2
5070 +#define WME_SUBTYPE_IE 0 /* Information Element */
5071 +#define WME_SUBTYPE_PARAM_IE 1 /* Parameter Element */
5072 +#define WME_SUBTYPE_TSPEC 2 /* Traffic Specification */
5073 +
5074 +/* WME Access Category Indices (ACIs) */
5075 +#define AC_BE 0 /* Best Effort */
5076 +#define AC_BK 1 /* Background */
5077 +#define AC_VI 2 /* Video */
5078 +#define AC_VO 3 /* Voice */
5079 +#define AC_MAX 4
5080 +
5081 +/* WME Information Element (IE) */
5082 +struct wme_ie {
5083 + uint8 oui[3];
5084 + uint8 type;
5085 + uint8 subtype;
5086 + uint8 version;
5087 + uint8 acinfo;
5088 +} PACKED;
5089 +typedef struct wme_ie wme_ie_t;
5090 +#define WME_IE_LEN 7
5091 +
5092 +struct wme_acparam {
5093 + uint8 ACI;
5094 + uint8 ECW;
5095 + uint16 TXOP; /* stored in network order (ls octet first) */
5096 +} PACKED;
5097 +typedef struct wme_acparam wme_acparam_t;
5098 +
5099 +/* WME Parameter Element (PE) */
5100 +struct wme_params {
5101 + uint8 oui[3];
5102 + uint8 type;
5103 + uint8 subtype;
5104 + uint8 version;
5105 + uint8 acinfo;
5106 + uint8 rsvd;
5107 + wme_acparam_t acparam[4];
5108 +} PACKED;
5109 +typedef struct wme_params wme_params_t;
5110 +#define WME_PARAMS_IE_LEN 24
5111 +
5112 +/* acinfo */
5113 +#define WME_COUNT_MASK 0x0f
5114 +/* ACI */
5115 +#define WME_AIFS_MASK 0x0f
5116 +#define WME_ACM_MASK 0x10
5117 +#define WME_ACI_MASK 0x60
5118 +#define WME_ACI_SHIFT 5
5119 +/* ECW */
5120 +#define WME_CWMIN_MASK 0x0f
5121 +#define WME_CWMAX_MASK 0xf0
5122 +#define WME_CWMAX_SHIFT 4
5123 +
5124 +#define WME_TXOP_UNITS 32
5125 +
5126 +/* AP: default params to be announced in the Beacon Frames/Probe Responses Table 12 WME Draft*/
5127 +/* AP: default params to be Used in the AP Side Table 14 WME Draft January 2004 802.11-03-504r5 */
5128 +#define WME_AC_BK_ACI_STA 0x27
5129 +#define WME_AC_BK_ECW_STA 0xA4
5130 +#define WME_AC_BK_TXOP_STA 0x0000
5131 +#define WME_AC_BE_ACI_STA 0x03
5132 +#define WME_AC_BE_ECW_STA 0xA4
5133 +#define WME_AC_BE_TXOP_STA 0x0000
5134 +#define WME_AC_VI_ACI_STA 0x42
5135 +#define WME_AC_VI_ECW_STA 0x43
5136 +#define WME_AC_VI_TXOP_STA 0x005e
5137 +#define WME_AC_VO_ACI_STA 0x62
5138 +#define WME_AC_VO_ECW_STA 0x32
5139 +#define WME_AC_VO_TXOP_STA 0x002f
5140 +
5141 +#define WME_AC_BK_ACI_AP 0x27
5142 +#define WME_AC_BK_ECW_AP 0xA4
5143 +#define WME_AC_BK_TXOP_AP 0x0000
5144 +#define WME_AC_BE_ACI_AP 0x03
5145 +#define WME_AC_BE_ECW_AP 0x64
5146 +#define WME_AC_BE_TXOP_AP 0x0000
5147 +#define WME_AC_VI_ACI_AP 0x41
5148 +#define WME_AC_VI_ECW_AP 0x43
5149 +#define WME_AC_VI_TXOP_AP 0x005e
5150 +#define WME_AC_VO_ACI_AP 0x61
5151 +#define WME_AC_VO_ECW_AP 0x32
5152 +#define WME_AC_VO_TXOP_AP 0x002f
5153 +
5154 +/* WME Traffic Specification (TSPEC) element */
5155 +#define WME_SUBTYPE_TSPEC 2
5156 +#define WME_TSPEC_HDR_LEN 2
5157 +#define WME_TSPEC_BODY_OFF 2
5158 +struct wme_tspec {
5159 + uint8 oui[DOT11_OUI_LEN]; /* WME_OUI */
5160 + uint8 type; /* WME_TYPE */
5161 + uint8 subtype; /* WME_SUBTYPE_TSPEC */
5162 + uint8 version; /* WME_VERSION */
5163 + uint16 ts_info; /* TS Info */
5164 + uint16 nom_msdu_size; /* (Nominal or fixed) MSDU Size (bytes) */
5165 + uint16 max_msdu_size; /* Maximum MSDU Size (bytes) */
5166 + uint32 min_service_interval; /* Minimum Service Interval (us) */
5167 + uint32 max_service_interval; /* Maximum Service Interval (us) */
5168 + uint32 inactivity_interval; /* Inactivity Interval (us) */
5169 + uint32 service_start; /* Service Start Time (us) */
5170 + uint32 min_rate; /* Minimum Data Rate (bps) */
5171 + uint32 mean_rate; /* Mean Data Rate (bps) */
5172 + uint32 max_burst_size; /* Maximum Burst Size (bytes) */
5173 + uint32 min_phy_rate; /* Minimum PHY Rate (bps) */
5174 + uint32 peak_rate; /* Peak Data Rate (bps) */
5175 + uint32 delay_bound; /* Delay Bound (us) */
5176 + uint16 surplus_bandwidth; /* Surplus Bandwidth Allowance Factor */
5177 + uint16 medium_time; /* Medium Time (32 us/s periods) */
5178 +} PACKED;
5179 +typedef struct wme_tspec wme_tspec_t;
5180 +#define WME_TSPEC_LEN 56 /* not including 2-byte header */
5181 +
5182 +/* ts_info */
5183 +/* 802.1D priority is duplicated - bits 13-11 AND bits 3-1 */
5184 +#define TS_INFO_PRIO_SHIFT_HI 11
5185 +#define TS_INFO_PRIO_MASK_HI (0x7 << TS_INFO_PRIO_SHIFT_HI)
5186 +#define TS_INFO_PRIO_SHIFT_LO 1
5187 +#define TS_INFO_PRIO_MASK_LO (0x7 << TS_INFO_PRIO_SHIFT_LO)
5188 +#define TS_INFO_CONTENTION_SHIFT 7
5189 +#define TS_INFO_CONTENTION_MASK (0x1 << TS_INFO_CONTENTION_SHIFT)
5190 +#define TS_INFO_DIRECTION_SHIFT 5
5191 +#define TS_INFO_DIRECTION_MASK (0x3 << TS_INFO_DIRECTION_SHIFT)
5192 +#define TS_INFO_UPLINK (0 << TS_INFO_DIRECTION_SHIFT)
5193 +#define TS_INFO_DOWNLINK (1 << TS_INFO_DIRECTION_SHIFT)
5194 +#define TS_INFO_BIDIRECTIONAL (3 << TS_INFO_DIRECTION_SHIFT)
5195 +
5196 +/* nom_msdu_size */
5197 +#define FIXED_MSDU_SIZE 0x8000 /* MSDU size is fixed */
5198 +#define MSDU_SIZE_MASK 0x7fff /* (Nominal or fixed) MSDU size */
5199 +
5200 +/* surplus_bandwidth */
5201 +/* Represented as 3 bits of integer, binary point, 13 bits fraction */
5202 +#define INTEGER_SHIFT 13
5203 +#define FRACTION_MASK 0x1FFF
5204 +
5205 +/* Management Notification Frame */
5206 +struct dot11_management_notification {
5207 + uint8 category; /* DOT11_ACTION_NOTIFICATION */
5208 + uint8 action;
5209 + uint8 token;
5210 + uint8 status;
5211 + uint8 data[1]; /* Elements */
5212 +} PACKED;
5213 +#define DOT11_MGMT_NOTIFICATION_LEN 4 /* Fixed length */
5214 +
5215 +/* WME Action Codes */
5216 +#define WME_SETUP_REQUEST 0
5217 +#define WME_SETUP_RESPONSE 1
5218 +#define WME_TEARDOWN 2
5219 +
5220 +/* WME Setup Response Status Codes */
5221 +#define WME_ADMISSION_ACCEPTED 0
5222 +#define WME_INVALID_PARAMETERS 1
5223 +#define WME_ADMISSION_REFUSED 3
5224 +
5225 +/* Macro to take a pointer to a beacon or probe response
5226 + * header and return the char* pointer to the SSID info element
5227 + */
5228 +#define BCN_PRB_SSID(hdr) ((char*)(hdr) + DOT11_MGMT_HDR_LEN + DOT11_BCN_PRB_LEN)
5229 +
5230 +/* Authentication frame payload constants */
5231 +#define DOT11_OPEN_SYSTEM 0
5232 +#define DOT11_SHARED_KEY 1
5233 +#define DOT11_CHALLENGE_LEN 128
5234 +
5235 +/* Frame control macros */
5236 +#define FC_PVER_MASK 0x3
5237 +#define FC_PVER_SHIFT 0
5238 +#define FC_TYPE_MASK 0xC
5239 +#define FC_TYPE_SHIFT 2
5240 +#define FC_SUBTYPE_MASK 0xF0
5241 +#define FC_SUBTYPE_SHIFT 4
5242 +#define FC_TODS 0x100
5243 +#define FC_TODS_SHIFT 8
5244 +#define FC_FROMDS 0x200
5245 +#define FC_FROMDS_SHIFT 9
5246 +#define FC_MOREFRAG 0x400
5247 +#define FC_MOREFRAG_SHIFT 10
5248 +#define FC_RETRY 0x800
5249 +#define FC_RETRY_SHIFT 11
5250 +#define FC_PM 0x1000
5251 +#define FC_PM_SHIFT 12
5252 +#define FC_MOREDATA 0x2000
5253 +#define FC_MOREDATA_SHIFT 13
5254 +#define FC_WEP 0x4000
5255 +#define FC_WEP_SHIFT 14
5256 +#define FC_ORDER 0x8000
5257 +#define FC_ORDER_SHIFT 15
5258 +
5259 +/* sequence control macros */
5260 +#define SEQNUM_SHIFT 4
5261 +#define FRAGNUM_MASK 0xF
5262 +
5263 +/* Frame Control type/subtype defs */
5264 +
5265 +/* FC Types */
5266 +#define FC_TYPE_MNG 0
5267 +#define FC_TYPE_CTL 1
5268 +#define FC_TYPE_DATA 2
5269 +
5270 +/* Management Subtypes */
5271 +#define FC_SUBTYPE_ASSOC_REQ 0
5272 +#define FC_SUBTYPE_ASSOC_RESP 1
5273 +#define FC_SUBTYPE_REASSOC_REQ 2
5274 +#define FC_SUBTYPE_REASSOC_RESP 3
5275 +#define FC_SUBTYPE_PROBE_REQ 4
5276 +#define FC_SUBTYPE_PROBE_RESP 5
5277 +#define FC_SUBTYPE_BEACON 8
5278 +#define FC_SUBTYPE_ATIM 9
5279 +#define FC_SUBTYPE_DISASSOC 10
5280 +#define FC_SUBTYPE_AUTH 11
5281 +#define FC_SUBTYPE_DEAUTH 12
5282 +#define FC_SUBTYPE_ACTION 13
5283 +
5284 +/* Control Subtypes */
5285 +#define FC_SUBTYPE_PS_POLL 10
5286 +#define FC_SUBTYPE_RTS 11
5287 +#define FC_SUBTYPE_CTS 12
5288 +#define FC_SUBTYPE_ACK 13
5289 +#define FC_SUBTYPE_CF_END 14
5290 +#define FC_SUBTYPE_CF_END_ACK 15
5291 +
5292 +/* Data Subtypes */
5293 +#define FC_SUBTYPE_DATA 0
5294 +#define FC_SUBTYPE_DATA_CF_ACK 1
5295 +#define FC_SUBTYPE_DATA_CF_POLL 2
5296 +#define FC_SUBTYPE_DATA_CF_ACK_POLL 3
5297 +#define FC_SUBTYPE_NULL 4
5298 +#define FC_SUBTYPE_CF_ACK 5
5299 +#define FC_SUBTYPE_CF_POLL 6
5300 +#define FC_SUBTYPE_CF_ACK_POLL 7
5301 +#define FC_SUBTYPE_QOS_DATA 8
5302 +#define FC_SUBTYPE_QOS_NULL 12
5303 +
5304 +/* type-subtype combos */
5305 +#define FC_KIND_MASK (FC_TYPE_MASK | FC_SUBTYPE_MASK)
5306 +
5307 +#define FC_KIND(t, s) (((t) << FC_TYPE_SHIFT) | ((s) << FC_SUBTYPE_SHIFT))
5308 +
5309 +#define FC_ASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_REQ)
5310 +#define FC_ASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_RESP)
5311 +#define FC_REASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_REQ)
5312 +#define FC_REASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_RESP)
5313 +#define FC_PROBE_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_REQ)
5314 +#define FC_PROBE_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_RESP)
5315 +#define FC_BEACON FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_BEACON)
5316 +#define FC_DISASSOC FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DISASSOC)
5317 +#define FC_AUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_AUTH)
5318 +#define FC_DEAUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DEAUTH)
5319 +#define FC_ACTION FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ACTION)
5320 +
5321 +#define FC_PS_POLL FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_PS_POLL)
5322 +#define FC_RTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_RTS)
5323 +#define FC_CTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CTS)
5324 +#define FC_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_ACK)
5325 +#define FC_CF_END FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END)
5326 +#define FC_CF_END_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END_ACK)
5327 +
5328 +#define FC_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA)
5329 +#define FC_NULL_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_NULL)
5330 +#define FC_DATA_CF_ACK FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA_CF_ACK)
5331 +#define FC_QOS_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_QOS_DATA)
5332 +#define FC_QOS_NULL FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_QOS_NULL)
5333 +
5334 +/* QoS Control Field */
5335 +
5336 +/* 802.1D Tag */
5337 +#define QOS_PRIO_SHIFT 0
5338 +#define QOS_PRIO_MASK 0x0007
5339 +#define QOS_PRIO(qos) (((qos) & QOS_PRIO_MASK) >> QOS_PRIO_SHIFT)
5340 +
5341 +/* Ack Policy (0 means Acknowledge) */
5342 +#define QOS_ACK_SHIFT 5
5343 +#define QOS_ACK_MASK 0x0060
5344 +#define QOS_ACK(qos) (((qos) & QOS_ACK_MASK) >> QOS_ACK_SHIFT)
5345 +
5346 +/* Management Frames */
5347 +
5348 +/* Management Frame Constants */
5349 +
5350 +/* Fixed fields */
5351 +#define DOT11_MNG_AUTH_ALGO_LEN 2
5352 +#define DOT11_MNG_AUTH_SEQ_LEN 2
5353 +#define DOT11_MNG_BEACON_INT_LEN 2
5354 +#define DOT11_MNG_CAP_LEN 2
5355 +#define DOT11_MNG_AP_ADDR_LEN 6
5356 +#define DOT11_MNG_LISTEN_INT_LEN 2
5357 +#define DOT11_MNG_REASON_LEN 2
5358 +#define DOT11_MNG_AID_LEN 2
5359 +#define DOT11_MNG_STATUS_LEN 2
5360 +#define DOT11_MNG_TIMESTAMP_LEN 8
5361 +
5362 +/* DUR/ID field in assoc resp is 0xc000 | AID */
5363 +#define DOT11_AID_MASK 0x3fff
5364 +
5365 +/* Reason Codes */
5366 +#define DOT11_RC_RESERVED 0
5367 +#define DOT11_RC_UNSPECIFIED 1 /* Unspecified reason */
5368 +#define DOT11_RC_AUTH_INVAL 2 /* Previous authentication no longer valid */
5369 +#define DOT11_RC_DEAUTH_LEAVING 3 /* Deauthenticated because sending station is
5370 + leaving (or has left) IBSS or ESS */
5371 +#define DOT11_RC_INACTIVITY 4 /* Disassociated due to inactivity */
5372 +#define DOT11_RC_BUSY 5 /* Disassociated because AP is unable to handle
5373 + all currently associated stations */
5374 +#define DOT11_RC_INVAL_CLASS_2 6 /* Class 2 frame received from
5375 + nonauthenticated station */
5376 +#define DOT11_RC_INVAL_CLASS_3 7 /* Class 3 frame received from
5377 + nonassociated station */
5378 +#define DOT11_RC_DISASSOC_LEAVING 8 /* Disassociated because sending station is
5379 + leaving (or has left) BSS */
5380 +#define DOT11_RC_NOT_AUTH 9 /* Station requesting (re)association is
5381 + not authenticated with responding station */
5382 +#define DOT11_RC_MAX 23 /* Reason codes > 23 are reserved */
5383 +
5384 +/* Status Codes */
5385 +#define DOT11_STATUS_SUCCESS 0 /* Successful */
5386 +#define DOT11_STATUS_FAILURE 1 /* Unspecified failure */
5387 +#define DOT11_STATUS_CAP_MISMATCH 10 /* Cannot support all requested capabilities
5388 + in the Capability Information field */
5389 +#define DOT11_STATUS_REASSOC_FAIL 11 /* Reassociation denied due to inability to
5390 + confirm that association exists */
5391 +#define DOT11_STATUS_ASSOC_FAIL 12 /* Association denied due to reason outside
5392 + the scope of this standard */
5393 +#define DOT11_STATUS_AUTH_MISMATCH 13 /* Responding station does not support the
5394 + specified authentication algorithm */
5395 +#define DOT11_STATUS_AUTH_SEQ 14 /* Received an Authentication frame with
5396 + authentication transaction sequence number
5397 + out of expected sequence */
5398 +#define DOT11_STATUS_AUTH_CHALLENGE_FAIL 15 /* Authentication rejected because of challenge failure */
5399 +#define DOT11_STATUS_AUTH_TIMEOUT 16 /* Authentication rejected due to timeout waiting
5400 + for next frame in sequence */
5401 +#define DOT11_STATUS_ASSOC_BUSY_FAIL 17 /* Association denied because AP is unable to
5402 + handle additional associated stations */
5403 +#define DOT11_STATUS_ASSOC_RATE_MISMATCH 18 /* Association denied due to requesting station
5404 + not supporting all of the data rates in the
5405 + BSSBasicRateSet parameter */
5406 +#define DOT11_STATUS_ASSOC_SHORT_REQUIRED 19 /* Association denied due to requesting station
5407 + not supporting the Short Preamble option */
5408 +#define DOT11_STATUS_ASSOC_PBCC_REQUIRED 20 /* Association denied due to requesting station
5409 + not supporting the PBCC Modulation option */
5410 +#define DOT11_STATUS_ASSOC_AGILITY_REQUIRED 21 /* Association denied due to requesting station
5411 + not supporting the Channel Agility option */
5412 +#define DOT11_STATUS_ASSOC_SPECTRUM_REQUIRED 22 /* Association denied because Spectrum Management
5413 + capability is required. */
5414 +#define DOT11_STATUS_ASSOC_BAD_POWER_CAP 23 /* Association denied because the info in the
5415 + Power Cap element is unacceptable. */
5416 +#define DOT11_STATUS_ASSOC_BAD_SUP_CHANNELS 24 /* Association denied because the info in the
5417 + Supported Channel element is unacceptable */
5418 +#define DOT11_STATUS_ASSOC_SHORTSLOT_REQUIRED 25 /* Association denied due to requesting station
5419 + not supporting the Short Slot Time option */
5420 +#define DOT11_STATUS_ASSOC_ERPBCC_REQUIRED 26 /* Association denied due to requesting station
5421 + not supporting the ER-PBCC Modulation option */
5422 +#define DOT11_STATUS_ASSOC_DSSOFDM_REQUIRED 27 /* Association denied due to requesting station
5423 + not supporting the DSS-OFDM option */
5424 +
5425 +/* Info Elts, length of INFORMATION portion of Info Elts */
5426 +#define DOT11_MNG_DS_PARAM_LEN 1
5427 +#define DOT11_MNG_IBSS_PARAM_LEN 2
5428 +
5429 +/* TIM Info element has 3 bytes fixed info in INFORMATION field,
5430 + * followed by 1 to 251 bytes of Partial Virtual Bitmap */
5431 +#define DOT11_MNG_TIM_FIXED_LEN 3
5432 +#define DOT11_MNG_TIM_DTIM_COUNT 0
5433 +#define DOT11_MNG_TIM_DTIM_PERIOD 1
5434 +#define DOT11_MNG_TIM_BITMAP_CTL 2
5435 +#define DOT11_MNG_TIM_PVB 3
5436 +
5437 +/* TLV defines */
5438 +#define TLV_TAG_OFF 0
5439 +#define TLV_LEN_OFF 1
5440 +#define TLV_HDR_LEN 2
5441 +#define TLV_BODY_OFF 2
5442 +
5443 +/* Management Frame Information Element IDs */
5444 +#define DOT11_MNG_SSID_ID 0
5445 +#define DOT11_MNG_RATES_ID 1
5446 +#define DOT11_MNG_FH_PARMS_ID 2
5447 +#define DOT11_MNG_DS_PARMS_ID 3
5448 +#define DOT11_MNG_CF_PARMS_ID 4
5449 +#define DOT11_MNG_TIM_ID 5
5450 +#define DOT11_MNG_IBSS_PARMS_ID 6
5451 +#define DOT11_MNG_COUNTRY_ID 7
5452 +#define DOT11_MNG_HOPPING_PARMS_ID 8
5453 +#define DOT11_MNG_HOPPING_TABLE_ID 9
5454 +#define DOT11_MNG_REQUEST_ID 10
5455 +#define DOT11_MNG_CHALLENGE_ID 16
5456 +#define DOT11_MNG_PWR_CONSTRAINT_ID 32 /* 11H PowerConstraint */
5457 +#define DOT11_MNG_PWR_CAP_ID 33 /* 11H PowerCapability */
5458 +#define DOT11_MNG_TPC_REQUEST_ID 34 /* 11H TPC Request */
5459 +#define DOT11_MNG_TPC_REPORT_ID 35 /* 11H TPC Report */
5460 +#define DOT11_MNG_SUPP_CHANNELS_ID 36 /* 11H Supported Channels */
5461 +#define DOT11_MNG_CHANNEL_SWITCH_ID 37 /* 11H ChannelSwitch Announcement*/
5462 +#define DOT11_MNG_MEASURE_REQUEST_ID 38 /* 11H MeasurementRequest */
5463 +#define DOT11_MNG_MEASURE_REPORT_ID 39 /* 11H MeasurementReport */
5464 +#define DOT11_MNG_QUIET_ID 40 /* 11H Quiet */
5465 +#define DOT11_MNG_IBSS_DFS_ID 41 /* 11H IBSS_DFS */
5466 +#define DOT11_MNG_ERP_ID 42
5467 +#define DOT11_MNG_NONERP_ID 47
5468 +#define DOT11_MNG_RSN_ID 48
5469 +#define DOT11_MNG_EXT_RATES_ID 50
5470 +#define DOT11_MNG_WPA_ID 221
5471 +#define DOT11_MNG_PROPR_ID 221
5472 +
5473 +/* ERP info element bit values */
5474 +#define DOT11_MNG_ERP_LEN 1 /* ERP is currently 1 byte long */
5475 +#define DOT11_MNG_NONERP_PRESENT 0x01 /* NonERP (802.11b) STAs are present in the BSS */
5476 +#define DOT11_MNG_USE_PROTECTION 0x02 /* Use protection mechanisms for ERP-OFDM frames */
5477 +#define DOT11_MNG_BARKER_PREAMBLE 0x04 /* Short Preambles: 0 == allowed, 1 == not allowed */
5478 +
5479 +/* Capability Information Field */
5480 +#define DOT11_CAP_ESS 0x0001
5481 +#define DOT11_CAP_IBSS 0x0002
5482 +#define DOT11_CAP_POLLABLE 0x0004
5483 +#define DOT11_CAP_POLL_RQ 0x0008
5484 +#define DOT11_CAP_PRIVACY 0x0010
5485 +#define DOT11_CAP_SHORT 0x0020
5486 +#define DOT11_CAP_PBCC 0x0040
5487 +#define DOT11_CAP_AGILITY 0x0080
5488 +#define DOT11_CAP_SPECTRUM 0x0100
5489 +#define DOT11_CAP_SHORTSLOT 0x0400
5490 +#define DOT11_CAP_CCK_OFDM 0x2000
5491 +
5492 +/* Action Frame Constants */
5493 +#define DOT11_ACTION_CAT_ERR_MASK 0x80
5494 +#define DOT11_ACTION_CAT_SPECT_MNG 0x00
5495 +#define DOT11_ACTION_NOTIFICATION 0x11 /* 17 */
5496 +
5497 +#define DOT11_ACTION_ID_M_REQ 0
5498 +#define DOT11_ACTION_ID_M_REP 1
5499 +#define DOT11_ACTION_ID_TPC_REQ 2
5500 +#define DOT11_ACTION_ID_TPC_REP 3
5501 +#define DOT11_ACTION_ID_CHANNEL_SWITCH 4
5502 +
5503 +/* MLME Enumerations */
5504 +#define DOT11_BSSTYPE_INFRASTRUCTURE 0
5505 +#define DOT11_BSSTYPE_INDEPENDENT 1
5506 +#define DOT11_BSSTYPE_ANY 2
5507 +#define DOT11_SCANTYPE_ACTIVE 0
5508 +#define DOT11_SCANTYPE_PASSIVE 1
5509 +
5510 +/* 802.11 A PHY constants */
5511 +#define APHY_SLOT_TIME 9
5512 +#define APHY_SIFS_TIME 16
5513 +#define APHY_DIFS_TIME (APHY_SIFS_TIME + (2 * APHY_SLOT_TIME))
5514 +#define APHY_PREAMBLE_TIME 16
5515 +#define APHY_SIGNAL_TIME 4
5516 +#define APHY_SYMBOL_TIME 4
5517 +#define APHY_SERVICE_NBITS 16
5518 +#define APHY_TAIL_NBITS 6
5519 +#define APHY_CWMIN 15
5520 +
5521 +/* 802.11 B PHY constants */
5522 +#define BPHY_SLOT_TIME 20
5523 +#define BPHY_SIFS_TIME 10
5524 +#define BPHY_DIFS_TIME 50
5525 +#define BPHY_PLCP_TIME 192
5526 +#define BPHY_PLCP_SHORT_TIME 96
5527 +#define BPHY_CWMIN 31
5528 +
5529 +/* 802.11 G constants */
5530 +#define DOT11_OFDM_SIGNAL_EXTENSION 6
5531 +
5532 +#define PHY_CWMAX 1023
5533 +
5534 +#define DOT11_MAXNUMFRAGS 16 /* max # fragments per MSDU */
5535 +
5536 +/* dot11Counters Table - 802.11 spec., Annex D */
5537 +typedef struct d11cnt {
5538 + uint32 txfrag; /* dot11TransmittedFragmentCount */
5539 + uint32 txmulti; /* dot11MulticastTransmittedFrameCount */
5540 + uint32 txfail; /* dot11FailedCount */
5541 + uint32 txretry; /* dot11RetryCount */
5542 + uint32 txretrie; /* dot11MultipleRetryCount */
5543 + uint32 rxdup; /* dot11FrameduplicateCount */
5544 + uint32 txrts; /* dot11RTSSuccessCount */
5545 + uint32 txnocts; /* dot11RTSFailureCount */
5546 + uint32 txnoack; /* dot11ACKFailureCount */
5547 + uint32 rxfrag; /* dot11ReceivedFragmentCount */
5548 + uint32 rxmulti; /* dot11MulticastReceivedFrameCount */
5549 + uint32 rxcrc; /* dot11FCSErrorCount */
5550 + uint32 txfrmsnt; /* dot11TransmittedFrameCount */
5551 + uint32 rxundec; /* dot11WEPUndecryptableCount */
5552 +} d11cnt_t;
5553 +
5554 +/* BRCM OUI */
5555 +#define BRCM_OUI "\x00\x10\x18"
5556 +
5557 +/* BRCM info element */
5558 +struct brcm_ie {
5559 + uchar id; /* 221, DOT11_MNG_PROPR_ID */
5560 + uchar len;
5561 + uchar oui[3];
5562 + uchar ver;
5563 + uchar assoc; /* # of assoc STAs */
5564 + uchar flags; /* misc flags */
5565 +} PACKED;
5566 +#define BRCM_IE_LEN 8
5567 +typedef struct brcm_ie brcm_ie_t;
5568 +#define BRCM_IE_VER 2
5569 +#define BRCM_IE_LEGACY_AES_VER 1
5570 +
5571 +/* brcm_ie flags */
5572 +#define BRF_ABCAP 0x1 /* afterburner capable */
5573 +#define BRF_ABRQRD 0x2 /* afterburner requested */
5574 +#define BRF_LZWDS 0x4 /* lazy wds enabled */
5575 +
5576 +
5577 +/* OUI for BRCM proprietary IE */
5578 +#define BRCM_PROP_OUI "\x00\x90\x4C"
5579 +
5580 +/* Vendor IE structure */
5581 +struct vndr_ie {
5582 + uchar id;
5583 + uchar len;
5584 + uchar oui [3];
5585 + uchar data [1]; /* Variable size data */
5586 +}PACKED;
5587 +typedef struct vndr_ie vndr_ie_t;
5588 +
5589 +#define VNDR_IE_HDR_LEN 2 /* id + len field */
5590 +#define VNDR_IE_MIN_LEN 3 /* size of the oui field */
5591 +#define VNDR_IE_MAX_LEN 256
5592 +
5593 +/* WPA definitions */
5594 +#define WPA_VERSION 1
5595 +#define WPA_OUI "\x00\x50\xF2"
5596 +
5597 +#define WPA2_VERSION 1
5598 +#define WPA2_VERSION_LEN 2
5599 +#define WPA2_OUI "\x00\x0F\xAC"
5600 +
5601 +#define WPA_OUI_LEN 3
5602 +
5603 +/* RSN authenticated key managment suite */
5604 +#define RSN_AKM_NONE 0 /* None (IBSS) */
5605 +#define RSN_AKM_UNSPECIFIED 1 /* Over 802.1x */
5606 +#define RSN_AKM_PSK 2 /* Pre-shared Key */
5607 +
5608 +
5609 +/* Key related defines */
5610 +#define DOT11_MAX_DEFAULT_KEYS 4 /* number of default keys */
5611 +#define DOT11_MAX_KEY_SIZE 32 /* max size of any key */
5612 +#define DOT11_MAX_IV_SIZE 16 /* max size of any IV */
5613 +#define DOT11_EXT_IV_FLAG (1<<5) /* flag to indicate IV is > 4 bytes */
5614 +
5615 +#define WEP1_KEY_SIZE 5 /* max size of any WEP key */
5616 +#define WEP1_KEY_HEX_SIZE 10 /* size of WEP key in hex. */
5617 +#define WEP128_KEY_SIZE 13 /* max size of any WEP key */
5618 +#define WEP128_KEY_HEX_SIZE 26 /* size of WEP key in hex. */
5619 +#define TKIP_MIC_SIZE 8 /* size of TKIP MIC */
5620 +#define TKIP_EOM_SIZE 7 /* max size of TKIP EOM */
5621 +#define TKIP_EOM_FLAG 0x5a /* TKIP EOM flag byte */
5622 +#define TKIP_KEY_SIZE 32 /* size of any TKIP key */
5623 +#define TKIP_MIC_AUTH_TX 16 /* offset to Authenticator MIC TX key */
5624 +#define TKIP_MIC_AUTH_RX 24 /* offset to Authenticator MIC RX key */
5625 +#define TKIP_MIC_SUP_RX 16 /* offset to Supplicant MIC RX key */
5626 +#define TKIP_MIC_SUP_TX 24 /* offset to Supplicant MIC TX key */
5627 +#define AES_KEY_SIZE 16 /* size of AES key */
5628 +
5629 +#undef PACKED
5630 +#if !defined(__GNUC__)
5631 +#pragma pack()
5632 +#endif
5633 +
5634 +#endif /* _802_11_H_ */
5635 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/proto/bcmeth.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/proto/bcmeth.h
5636 --- linux-2.4.30/arch/mips/bcm947xx/include/proto/bcmeth.h 1970-01-01 01:00:00.000000000 +0100
5637 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/proto/bcmeth.h 2005-02-02 23:16:40.000000000 +0100
5638 @@ -0,0 +1,97 @@
5639 +/*
5640 + * Broadcom Ethernettype protocol definitions
5641 + *
5642 + * Copyright 2005, Broadcom Corporation
5643 + * All Rights Reserved.
5644 + *
5645 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5646 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5647 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5648 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5649 + *
5650 + */
5651 +
5652 +/*
5653 + * Broadcom Ethernet protocol defines
5654 + *
5655 + */
5656 +
5657 +#ifndef _BCMETH_H_
5658 +#define _BCMETH_H_
5659 +
5660 +/* enable structure packing */
5661 +#if defined(__GNUC__)
5662 +#define PACKED __attribute__((packed))
5663 +#else
5664 +#pragma pack(1)
5665 +#define PACKED
5666 +#endif
5667 +
5668 +/* ETHER_TYPE_BRCM is defined in ethernet.h */
5669 +
5670 +/*
5671 + * Following the 2byte BRCM ether_type is a 16bit BRCM subtype field
5672 + * in one of two formats: (only subtypes 32768-65535 are in use now)
5673 + *
5674 + * subtypes 0-32767:
5675 + * 8 bit subtype (0-127)
5676 + * 8 bit length in bytes (0-255)
5677 + *
5678 + * subtypes 32768-65535:
5679 + * 16 bit big-endian subtype
5680 + * 16 bit big-endian length in bytes (0-65535)
5681 + *
5682 + * length is the number of additional bytes beyond the 4 or 6 byte header
5683 + *
5684 + * Reserved values:
5685 + * 0 reserved
5686 + * 5-15 reserved for iLine protocol assignments
5687 + * 17-126 reserved, assignable
5688 + * 127 reserved
5689 + * 32768 reserved
5690 + * 32769-65534 reserved, assignable
5691 + * 65535 reserved
5692 + */
5693 +
5694 +/*
5695 + * While adding the subtypes and their specific processing code make sure
5696 + * bcmeth_bcm_hdr_t is the first data structure in the user specific data structure definition
5697 + */
5698 +
5699 +#define BCMILCP_SUBTYPE_RATE 1
5700 +#define BCMILCP_SUBTYPE_LINK 2
5701 +#define BCMILCP_SUBTYPE_CSA 3
5702 +#define BCMILCP_SUBTYPE_LARQ 4
5703 +#define BCMILCP_SUBTYPE_VENDOR 5
5704 +#define BCMILCP_SUBTYPE_FLH 17
5705 +
5706 +#define BCMILCP_SUBTYPE_VENDOR_LONG 32769
5707 +#define BCMILCP_SUBTYPE_CERT 32770
5708 +#define BCMILCP_SUBTYPE_SES 32771
5709 +
5710 +
5711 +#define BCMILCP_BCM_SUBTYPE_RESERVED 0
5712 +#define BCMILCP_BCM_SUBTYPE_WPA 1
5713 +#define BCMILCP_BCM_SUBTYPE_EAPOL 2
5714 +#define BCMILCP_BCM_SUBTYPE_SES 3
5715 +
5716 +#define BCMILCP_BCM_SUBTYPEHDR_MINLENGTH 8
5717 +#define BCMILCP_BCM_SUBTYPEHDR_VERSION 0
5718 +
5719 +typedef struct bcmeth_bcm_hdr
5720 +{
5721 + uint16 subtype; /* Vendor specific..32769*/
5722 + uint16 length;
5723 + uint8 version; /* Version is 0*/
5724 + uint8 oui[3]; /* Broadcom OUI*/
5725 + /* user specific Data */
5726 + uint16 usr_subtype;
5727 +} PACKED bcmeth_bcm_hdr_t;
5728 +
5729 +
5730 +#undef PACKED
5731 +#if !defined(__GNUC__)
5732 +#pragma pack()
5733 +#endif
5734 +
5735 +#endif
5736 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/proto/ethernet.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/proto/ethernet.h
5737 --- linux-2.4.30/arch/mips/bcm947xx/include/proto/ethernet.h 1970-01-01 01:00:00.000000000 +0100
5738 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/proto/ethernet.h 2005-02-02 23:16:40.000000000 +0100
5739 @@ -0,0 +1,161 @@
5740 +/*******************************************************************************
5741 + * $Id$
5742 + * Copyright 2005, Broadcom Corporation
5743 + * All Rights Reserved.
5744 + *
5745 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5746 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5747 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5748 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5749 + * From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
5750 + ******************************************************************************/
5751 +
5752 +#ifndef _NET_ETHERNET_H_ /* use native BSD ethernet.h when available */
5753 +#define _NET_ETHERNET_H_
5754 +
5755 +#ifndef _TYPEDEFS_H_
5756 +#include "typedefs.h"
5757 +#endif
5758 +
5759 +/* enable structure packing */
5760 +#if defined(__GNUC__)
5761 +#define PACKED __attribute__((packed))
5762 +#else
5763 +#pragma pack(1)
5764 +#define PACKED
5765 +#endif
5766 +
5767 +/*
5768 + * The number of bytes in an ethernet (MAC) address.
5769 + */
5770 +#define ETHER_ADDR_LEN 6
5771 +
5772 +/*
5773 + * The number of bytes in the type field.
5774 + */
5775 +#define ETHER_TYPE_LEN 2
5776 +
5777 +/*
5778 + * The number of bytes in the trailing CRC field.
5779 + */
5780 +#define ETHER_CRC_LEN 4
5781 +
5782 +/*
5783 + * The length of the combined header.
5784 + */
5785 +#define ETHER_HDR_LEN (ETHER_ADDR_LEN*2+ETHER_TYPE_LEN)
5786 +
5787 +/*
5788 + * The minimum packet length.
5789 + */
5790 +#define ETHER_MIN_LEN 64
5791 +
5792 +/*
5793 + * The minimum packet user data length.
5794 + */
5795 +#define ETHER_MIN_DATA 46
5796 +
5797 +/*
5798 + * The maximum packet length.
5799 + */
5800 +#define ETHER_MAX_LEN 1518
5801 +
5802 +/*
5803 + * The maximum packet user data length.
5804 + */
5805 +#define ETHER_MAX_DATA 1500
5806 +
5807 +/* ether types */
5808 +#define ETHER_TYPE_IP 0x0800 /* IP */
5809 +#define ETHER_TYPE_ARP 0x0806 /* ARP */
5810 +#define ETHER_TYPE_8021Q 0x8100 /* 802.1Q */
5811 +#define ETHER_TYPE_BRCM 0x886c /* Broadcom Corp. */
5812 +#define ETHER_TYPE_802_1X 0x888e /* 802.1x */
5813 +#define ETHER_TYPE_802_1X_PREAUTH 0x88c7 /* 802.1x preauthentication*/
5814 +
5815 +/* Broadcom subtype follows ethertype; First 2 bytes are reserved; Next 2 are subtype; */
5816 +#define ETHER_BRCM_SUBTYPE_LEN 4 /* Broadcom 4 byte subtype */
5817 +#define ETHER_BRCM_CRAM 0x1 /* Broadcom subtype cram protocol */
5818 +
5819 +/* ether header */
5820 +#define ETHER_DEST_OFFSET 0 /* dest address offset */
5821 +#define ETHER_SRC_OFFSET 6 /* src address offset */
5822 +#define ETHER_TYPE_OFFSET 12 /* ether type offset */
5823 +
5824 +/*
5825 + * A macro to validate a length with
5826 + */
5827 +#define ETHER_IS_VALID_LEN(foo) \
5828 + ((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
5829 +
5830 +
5831 +#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
5832 +/*
5833 + * Structure of a 10Mb/s Ethernet header.
5834 + */
5835 +struct ether_header {
5836 + uint8 ether_dhost[ETHER_ADDR_LEN];
5837 + uint8 ether_shost[ETHER_ADDR_LEN];
5838 + uint16 ether_type;
5839 +} PACKED;
5840 +
5841 +/*
5842 + * Structure of a 48-bit Ethernet address.
5843 + */
5844 +struct ether_addr {
5845 + uint8 octet[ETHER_ADDR_LEN];
5846 +} PACKED;
5847 +#endif
5848 +
5849 +/*
5850 + * Takes a pointer, returns true if a 48-bit multicast address
5851 + * (including broadcast, since it is all ones)
5852 + */
5853 +#define ETHER_ISMULTI(ea) (((uint8 *)(ea))[0] & 1)
5854 +
5855 +/* compare two ethernet addresses - assumes the pointers can be referenced as shorts */
5856 +#define ether_cmp(a, b) ( \
5857 + !(((short*)a)[0] == ((short*)b)[0]) | \
5858 + !(((short*)a)[1] == ((short*)b)[1]) | \
5859 + !(((short*)a)[2] == ((short*)b)[2]))
5860 +
5861 +/* copy an ethernet address - assumes the pointers can be referenced as shorts */
5862 +#define ether_copy(s, d) { \
5863 + ((short*)d)[0] = ((short*)s)[0]; \
5864 + ((short*)d)[1] = ((short*)s)[1]; \
5865 + ((short*)d)[2] = ((short*)s)[2]; }
5866 +
5867 +/*
5868 + * Takes a pointer, returns true if a 48-bit broadcast (all ones)
5869 + */
5870 +#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
5871 + ((uint8 *)(ea))[1] & \
5872 + ((uint8 *)(ea))[2] & \
5873 + ((uint8 *)(ea))[3] & \
5874 + ((uint8 *)(ea))[4] & \
5875 + ((uint8 *)(ea))[5]) == 0xff)
5876 +
5877 +static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
5878 +
5879 +/*
5880 + * Takes a pointer, returns true if a 48-bit null address (all zeros)
5881 + */
5882 +#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
5883 + ((uint8 *)(ea))[1] | \
5884 + ((uint8 *)(ea))[2] | \
5885 + ((uint8 *)(ea))[3] | \
5886 + ((uint8 *)(ea))[4] | \
5887 + ((uint8 *)(ea))[5]) == 0)
5888 +
5889 +/* Differentiated Services Codepoint - upper 6 bits of tos in iphdr */
5890 +#define DSCP_MASK 0xFC /* upper 6 bits */
5891 +#define DSCP_SHIFT 2
5892 +#define DSCP_WME_PRI_MASK 0xE0 /* upper 3 bits */
5893 +#define DSCP_WME_PRI_SHIFT 5
5894 +
5895 +#undef PACKED
5896 +#if !defined(__GNUC__)
5897 +#pragma pack()
5898 +#endif
5899 +
5900 +#endif /* _NET_ETHERNET_H_ */
5901 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/proto/vlan.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/proto/vlan.h
5902 --- linux-2.4.30/arch/mips/bcm947xx/include/proto/vlan.h 1970-01-01 01:00:00.000000000 +0100
5903 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/proto/vlan.h 2005-02-02 23:16:40.000000000 +0100
5904 @@ -0,0 +1,50 @@
5905 +/*
5906 + * 802.1Q VLAN protocol definitions
5907 + *
5908 + * Copyright 2005, Broadcom Corporation
5909 + * All Rights Reserved.
5910 + *
5911 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5912 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5913 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5914 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5915 + *
5916 + * $Id$
5917 + */
5918 +
5919 +#ifndef _vlan_h_
5920 +#define _vlan_h_
5921 +
5922 +/* enable structure packing */
5923 +#if defined(__GNUC__)
5924 +#define PACKED __attribute__((packed))
5925 +#else
5926 +#pragma pack(1)
5927 +#define PACKED
5928 +#endif
5929 +
5930 +#define VLAN_VID_MASK 0xfff /* low 12 bits are vlan id */
5931 +#define VLAN_CFI_SHIFT 12 /* canonical format indicator bit */
5932 +#define VLAN_PRI_SHIFT 13 /* user priority */
5933 +
5934 +#define VLAN_PRI_MASK 7 /* 3 bits of priority */
5935 +
5936 +#define VLAN_TAG_LEN 4
5937 +#define VLAN_TAG_OFFSET (2 * ETHER_ADDR_LEN)
5938 +
5939 +struct ethervlan_header {
5940 + uint8 ether_dhost[ETHER_ADDR_LEN];
5941 + uint8 ether_shost[ETHER_ADDR_LEN];
5942 + uint16 vlan_type; /* 0x8100 */
5943 + uint16 vlan_tag; /* priority, cfi and vid */
5944 + uint16 ether_type;
5945 +};
5946 +
5947 +#define ETHERVLAN_HDR_LEN (ETHER_HDR_LEN + VLAN_TAG_LEN)
5948 +
5949 +#undef PACKED
5950 +#if !defined(__GNUC__)
5951 +#pragma pack()
5952 +#endif
5953 +
5954 +#endif /* _vlan_h_ */
5955 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/proto/wpa.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/proto/wpa.h
5956 --- linux-2.4.30/arch/mips/bcm947xx/include/proto/wpa.h 1970-01-01 01:00:00.000000000 +0100
5957 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/proto/wpa.h 2005-02-02 23:16:40.000000000 +0100
5958 @@ -0,0 +1,140 @@
5959 +/*
5960 + * Fundamental types and constants relating to WPA
5961 + *
5962 + * Copyright 2005, Broadcom Corporation
5963 + * All Rights Reserved.
5964 + *
5965 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5966 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5967 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5968 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5969 + *
5970 + * $Id$
5971 + */
5972 +
5973 +#ifndef _proto_wpa_h_
5974 +#define _proto_wpa_h_
5975 +
5976 +#include <typedefs.h>
5977 +#include <proto/ethernet.h>
5978 +
5979 +/* enable structure packing */
5980 +#if defined(__GNUC__)
5981 +#define PACKED __attribute__((packed))
5982 +#else
5983 +#pragma pack(1)
5984 +#define PACKED
5985 +#endif
5986 +
5987 +/* Reason Codes */
5988 +
5989 +/* 10 and 11 are from TGh. */
5990 +#define DOT11_RC_BAD_PC 10 /* Unacceptable power capability element */
5991 +#define DOT11_RC_BAD_CHANNELS 11 /* Unacceptable supported channels element */
5992 +/* 12 is unused */
5993 +/* 13 through 23 taken from P802.11i/D3.0, November 2002 */
5994 +#define DOT11_RC_INVALID_WPA_IE 13 /* Invalid info. element */
5995 +#define DOT11_RC_MIC_FAILURE 14 /* Michael failure */
5996 +#define DOT11_RC_4WH_TIMEOUT 15 /* 4-way handshake timeout */
5997 +#define DOT11_RC_GTK_UPDATE_TIMEOUT 16 /* Group key update timeout */
5998 +#define DOT11_RC_WPA_IE_MISMATCH 17 /* WPA IE in 4-way handshake differs from (re-)assoc. request/probe response */
5999 +#define DOT11_RC_INVALID_MC_CIPHER 18 /* Invalid multicast cipher */
6000 +#define DOT11_RC_INVALID_UC_CIPHER 19 /* Invalid unicast cipher */
6001 +#define DOT11_RC_INVALID_AKMP 20 /* Invalid authenticated key management protocol */
6002 +#define DOT11_RC_BAD_WPA_VERSION 21 /* Unsupported WPA version */
6003 +#define DOT11_RC_INVALID_WPA_CAP 22 /* Invalid WPA IE capabilities */
6004 +#define DOT11_RC_8021X_AUTH_FAIL 23 /* 802.1X authentication failure */
6005 +
6006 +#define WPA2_PMKID_LEN 16
6007 +
6008 +/* WPA IE fixed portion */
6009 +typedef struct
6010 +{
6011 + uint8 tag; /* TAG */
6012 + uint8 length; /* TAG length */
6013 + uint8 oui[3]; /* IE OUI */
6014 + uint8 oui_type; /* OUI type */
6015 + struct {
6016 + uint8 low;
6017 + uint8 high;
6018 + } PACKED version; /* IE version */
6019 +} PACKED wpa_ie_fixed_t;
6020 +#define WPA_IE_OUITYPE_LEN 4
6021 +#define WPA_IE_FIXED_LEN 8
6022 +#define WPA_IE_TAG_FIXED_LEN 6
6023 +
6024 +typedef struct {
6025 + uint8 tag; /* TAG */
6026 + uint8 length; /* TAG length */
6027 + struct {
6028 + uint8 low;
6029 + uint8 high;
6030 + } PACKED version; /* IE version */
6031 +} PACKED wpa_rsn_ie_fixed_t;
6032 +#define WPA_RSN_IE_FIXED_LEN 4
6033 +#define WPA_RSN_IE_TAG_FIXED_LEN 2
6034 +typedef uint8 wpa_pmkid_t[WPA2_PMKID_LEN];
6035 +
6036 +/* WPA suite/multicast suite */
6037 +typedef struct
6038 +{
6039 + uint8 oui[3];
6040 + uint8 type;
6041 +} PACKED wpa_suite_t, wpa_suite_mcast_t;
6042 +#define WPA_SUITE_LEN 4
6043 +
6044 +/* WPA unicast suite list/key management suite list */
6045 +typedef struct
6046 +{
6047 + struct {
6048 + uint8 low;
6049 + uint8 high;
6050 + } PACKED count;
6051 + wpa_suite_t list[1];
6052 +} PACKED wpa_suite_ucast_t, wpa_suite_auth_key_mgmt_t;
6053 +#define WPA_IE_SUITE_COUNT_LEN 2
6054 +typedef struct
6055 +{
6056 + struct {
6057 + uint8 low;
6058 + uint8 high;
6059 + } PACKED count;
6060 + wpa_pmkid_t list[1];
6061 +} PACKED wpa_pmkid_list_t;
6062 +
6063 +/* WPA cipher suites */
6064 +#define WPA_CIPHER_NONE 0 /* None */
6065 +#define WPA_CIPHER_WEP_40 1 /* WEP (40-bit) */
6066 +#define WPA_CIPHER_TKIP 2 /* TKIP: default for WPA */
6067 +#define WPA_CIPHER_AES_OCB 3 /* AES (OCB) */
6068 +#define WPA_CIPHER_AES_CCM 4 /* AES (CCM) */
6069 +#define WPA_CIPHER_WEP_104 5 /* WEP (104-bit) */
6070 +
6071 +#define IS_WPA_CIPHER(cipher) ((cipher) == WPA_CIPHER_NONE || \
6072 + (cipher) == WPA_CIPHER_WEP_40 || \
6073 + (cipher) == WPA_CIPHER_WEP_104 || \
6074 + (cipher) == WPA_CIPHER_TKIP || \
6075 + (cipher) == WPA_CIPHER_AES_OCB || \
6076 + (cipher) == WPA_CIPHER_AES_CCM)
6077 +
6078 +/* WPA TKIP countermeasures parameters */
6079 +#define WPA_TKIP_CM_DETECT 60 /* multiple MIC failure window (seconds) */
6080 +#define WPA_TKIP_CM_BLOCK 60 /* countermeasures active window (seconds) */
6081 +
6082 +/* WPA capabilities defined in 802.11i */
6083 +#define WPA_CAP_4_REPLAY_CNTRS 2
6084 +#define WPA_CAP_16_REPLAY_CNTRS 3
6085 +#define WPA_CAP_REPLAY_CNTR_SHIFT 2
6086 +#define WPA_CAP_REPLAY_CNTR_MASK 0x000c
6087 +
6088 +/* WPA Specific defines */
6089 +#define WPA_CAP_LEN 2
6090 +
6091 +#define WPA_CAP_WPA2_PREAUTH 1
6092 +
6093 +#undef PACKED
6094 +#if !defined(__GNUC__)
6095 +#pragma pack()
6096 +#endif
6097 +
6098 +#endif /* _proto_wpa_h_ */
6099 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/rts/crc.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/rts/crc.h
6100 --- linux-2.4.30/arch/mips/bcm947xx/include/rts/crc.h 1970-01-01 01:00:00.000000000 +0100
6101 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/rts/crc.h 2005-02-02 23:16:40.000000000 +0100
6102 @@ -0,0 +1,69 @@
6103 +/*******************************************************************************
6104 + * $Id$
6105 + * Copyright 2005, Broadcom Corporation
6106 + * All Rights Reserved.
6107 + *
6108 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6109 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6110 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6111 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6112 + * crc.h - a function to compute crc for iLine10 headers
6113 + ******************************************************************************/
6114 +
6115 +#ifndef _RTS_CRC_H_
6116 +#define _RTS_CRC_H_ 1
6117 +
6118 +#include "typedefs.h"
6119 +
6120 +#ifdef __cplusplus
6121 +extern "C" {
6122 +#endif
6123 +
6124 +
6125 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
6126 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
6127 +#define HCS_GOOD_VALUE 0x39 /* Good final header checksum value */
6128 +
6129 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
6130 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
6131 +
6132 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
6133 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
6134 +
6135 +void hcs(uint8 *, uint);
6136 +uint8 crc8(uint8 *, uint, uint8);
6137 +uint16 crc16(uint8 *, uint, uint16);
6138 +uint32 crc32(uint8 *, uint, uint32);
6139 +
6140 +/* macros for common usage */
6141 +
6142 +#define APPEND_CRC8(pbytes, nbytes) \
6143 +do { \
6144 + uint8 tmp = crc8(pbytes, nbytes, CRC8_INIT_VALUE) ^ 0xff; \
6145 + (pbytes)[(nbytes)] = tmp; \
6146 + (nbytes) += 1; \
6147 +} while (0)
6148 +
6149 +#define APPEND_CRC16(pbytes, nbytes) \
6150 +do { \
6151 + uint16 tmp = crc16(pbytes, nbytes, CRC16_INIT_VALUE) ^ 0xffff; \
6152 + (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
6153 + (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
6154 + (nbytes) += 2; \
6155 +} while (0)
6156 +
6157 +#define APPEND_CRC32(pbytes, nbytes) \
6158 +do { \
6159 + uint32 tmp = crc32(pbytes, nbytes, CRC32_INIT_VALUE) ^ 0xffffffff; \
6160 + (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
6161 + (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
6162 + (pbytes)[(nbytes) + 2] = (tmp >> 16) & 0xff; \
6163 + (pbytes)[(nbytes) + 3] = (tmp >> 24) & 0xff; \
6164 + (nbytes) += 4; \
6165 +} while (0)
6166 +
6167 +#ifdef __cplusplus
6168 +}
6169 +#endif
6170 +
6171 +#endif /* _RTS_CRC_H_ */
6172 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/sbchipc.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/sbchipc.h
6173 --- linux-2.4.30/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
6174 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/sbchipc.h 2005-02-02 23:16:40.000000000 +0100
6175 @@ -0,0 +1,394 @@
6176 +/*
6177 + * SiliconBackplane Chipcommon core hardware definitions.
6178 + *
6179 + * The chipcommon core provides chip identification, SB control,
6180 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
6181 + * gpio interface, extbus, and support for serial and parallel flashes.
6182 + *
6183 + * $Id$
6184 + * Copyright 2005, Broadcom Corporation
6185 + * All Rights Reserved.
6186 + *
6187 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6188 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6189 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6190 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6191 + *
6192 + */
6193 +
6194 +#ifndef _SBCHIPC_H
6195 +#define _SBCHIPC_H
6196 +
6197 +
6198 +#ifndef _LANGUAGE_ASSEMBLY
6199 +
6200 +/* cpp contortions to concatenate w/arg prescan */
6201 +#ifndef PAD
6202 +#define _PADLINE(line) pad ## line
6203 +#define _XSTR(line) _PADLINE(line)
6204 +#define PAD _XSTR(__LINE__)
6205 +#endif /* PAD */
6206 +
6207 +typedef volatile struct {
6208 + uint32 chipid; /* 0x0 */
6209 + uint32 capabilities;
6210 + uint32 corecontrol; /* corerev >= 1 */
6211 + uint32 bist;
6212 +
6213 + /* OTP */
6214 + uint32 otpstatus; /* 0x10, corerev >= 10 */
6215 + uint32 otpcontrol;
6216 + uint32 otpprog;
6217 + uint32 PAD;
6218 +
6219 + /* Interrupt control */
6220 + uint32 intstatus; /* 0x20 */
6221 + uint32 intmask;
6222 + uint32 chipcontrol; /* 0x28, rev >= 11 */
6223 + uint32 chipstatus; /* 0x2c, rev >= 11 */
6224 +
6225 + /* Jtag Master */
6226 + uint32 jtagcmd; /* 0x30, rev >= 10 */
6227 + uint32 jtagir;
6228 + uint32 jtagdr;
6229 + uint32 jtagctrl;
6230 +
6231 + /* serial flash interface registers */
6232 + uint32 flashcontrol; /* 0x40 */
6233 + uint32 flashaddress;
6234 + uint32 flashdata;
6235 + uint32 PAD[1];
6236 +
6237 + /* Silicon backplane configuration broadcast control */
6238 + uint32 broadcastaddress; /* 0x50 */
6239 + uint32 broadcastdata;
6240 + uint32 PAD[2];
6241 +
6242 + /* gpio - cleared only by power-on-reset */
6243 + uint32 gpioin; /* 0x60 */
6244 + uint32 gpioout;
6245 + uint32 gpioouten;
6246 + uint32 gpiocontrol;
6247 + uint32 gpiointpolarity;
6248 + uint32 gpiointmask;
6249 + uint32 PAD[2];
6250 +
6251 + /* Watchdog timer */
6252 + uint32 watchdog; /* 0x80 */
6253 + uint32 PAD[3];
6254 +
6255 + /* clock control */
6256 + uint32 clockcontrol_n; /* 0x90 */
6257 + uint32 clockcontrol_sb; /* aka m0 */
6258 + uint32 clockcontrol_pci; /* aka m1 */
6259 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
6260 + uint32 clockcontrol_mips; /* aka m3 */
6261 + uint32 clkdiv; /* corerev >= 3 */
6262 + uint32 PAD[2];
6263 +
6264 + /* pll delay registers (corerev >= 4) */
6265 + uint32 pll_on_delay; /* 0xb0 */
6266 + uint32 fref_sel_delay;
6267 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
6268 + uint32 PAD[1];
6269 +
6270 + /* Instaclock registers (corerev >= 10) */
6271 + uint32 system_clk_ctl; /* 0xc0 */
6272 + uint32 clkstatestretch;
6273 + uint32 PAD[14];
6274 +
6275 + /* ExtBus control registers (corerev >= 3) */
6276 + uint32 pcmcia_config; /* 0x100 */
6277 + uint32 pcmcia_memwait;
6278 + uint32 pcmcia_attrwait;
6279 + uint32 pcmcia_iowait;
6280 + uint32 ide_config;
6281 + uint32 ide_memwait;
6282 + uint32 ide_attrwait;
6283 + uint32 ide_iowait;
6284 + uint32 prog_config;
6285 + uint32 prog_waitcount;
6286 + uint32 flash_config;
6287 + uint32 flash_waitcount;
6288 + uint32 PAD[116];
6289 +
6290 + /* uarts */
6291 + uint8 uart0data; /* 0x300 */
6292 + uint8 uart0imr;
6293 + uint8 uart0fcr;
6294 + uint8 uart0lcr;
6295 + uint8 uart0mcr;
6296 + uint8 uart0lsr;
6297 + uint8 uart0msr;
6298 + uint8 uart0scratch;
6299 + uint8 PAD[248]; /* corerev >= 1 */
6300 +
6301 + uint8 uart1data; /* 0x400 */
6302 + uint8 uart1imr;
6303 + uint8 uart1fcr;
6304 + uint8 uart1lcr;
6305 + uint8 uart1mcr;
6306 + uint8 uart1lsr;
6307 + uint8 uart1msr;
6308 + uint8 uart1scratch;
6309 +} chipcregs_t;
6310 +
6311 +#endif /* _LANGUAGE_ASSEMBLY */
6312 +
6313 +#define CC_CHIPID 0
6314 +#define CC_CAPABILITIES 4
6315 +#define CC_JTAGCMD 0x30
6316 +#define CC_JTAGIR 0x34
6317 +#define CC_JTAGDR 0x38
6318 +#define CC_JTAGCTRL 0x3c
6319 +#define CC_CLKDIV 0xa4
6320 +#define CC_OTP 0x800
6321 +
6322 +/* chipid */
6323 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
6324 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
6325 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
6326 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
6327 +#define CID_PKG_SHIFT 20 /* Package Option shift */
6328 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
6329 +#define CID_CC_SHIFT 24
6330 +
6331 +/* capabilities */
6332 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
6333 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
6334 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
6335 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
6336 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
6337 +#define CAP_EXTBUS 0x00000040 /* External bus present */
6338 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
6339 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
6340 +#define CAP_PWR_CTL 0x00040000 /* Power control */
6341 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
6342 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
6343 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
6344 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
6345 +
6346 +/* PLL type */
6347 +#define PLL_NONE 0x00000000
6348 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
6349 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
6350 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
6351 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
6352 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
6353 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
6354 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
6355 +
6356 +/* corecontrol */
6357 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
6358 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
6359 +
6360 +/* jtagcmd */
6361 +#define JCMD_START 0x80000000
6362 +#define JCMD_BUSY 0x80000000
6363 +#define JCMD_PAUSE 0x40000000
6364 +#define JCMD0_ACC_MASK 0x0000f000
6365 +#define JCMD0_ACC_IRDR 0x00000000
6366 +#define JCMD0_ACC_DR 0x00001000
6367 +#define JCMD0_ACC_IR 0x00002000
6368 +#define JCMD0_ACC_RESET 0x00003000
6369 +#define JCMD0_ACC_IRPDR 0x00004000
6370 +#define JCMD0_ACC_PDR 0x00005000
6371 +#define JCMD0_IRW_MASK 0x00000f00
6372 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
6373 +#define JCMD_ACC_IRDR 0x00000000
6374 +#define JCMD_ACC_DR 0x00010000
6375 +#define JCMD_ACC_IR 0x00020000
6376 +#define JCMD_ACC_RESET 0x00030000
6377 +#define JCMD_ACC_IRPDR 0x00040000
6378 +#define JCMD_ACC_PDR 0x00050000
6379 +#define JCMD_IRW_MASK 0x00001f00
6380 +#define JCMD_IRW_SHIFT 8
6381 +#define JCMD_DRW_MASK 0x0000003f
6382 +
6383 +/* jtagctrl */
6384 +#define JCTRL_FORCE_CLK 4 /* Force clock */
6385 +#define JCTRL_EXT_EN 2 /* Enable external targets */
6386 +#define JCTRL_EN 1 /* Enable Jtag master */
6387 +
6388 +/* Fields in clkdiv */
6389 +#define CLKD_SFLASH 0x0f000000
6390 +#define CLKD_SFLASH_SHIFT 24
6391 +#define CLKD_OTP 0x000f0000
6392 +#define CLKD_OTP_SHIFT 16
6393 +#define CLKD_JTAG 0x00000f00
6394 +#define CLKD_JTAG_SHIFT 8
6395 +#define CLKD_UART 0x000000ff
6396 +
6397 +/* intstatus/intmask */
6398 +#define CI_GPIO 0x00000001 /* gpio intr */
6399 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
6400 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
6401 +
6402 +/* slow_clk_ctl */
6403 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
6404 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
6405 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
6406 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
6407 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
6408 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
6409 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
6410 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
6411 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
6412 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
6413 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider mask, SlowClk = 1/(4+divisor) * crystal/PCI clock */
6414 +#define SCC_CD_SHF 16 /* CLockDivider shift */
6415 +
6416 +/* sys_clk_ctl */
6417 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
6418 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
6419 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
6420 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
6421 +#define SYCC_HR 0x00000010 /* Force HT */
6422 +#define SYCC_CD_MASK 0xffff0000 /* ClockDivider mask, SlowClk = 1/(4+divisor) * crystal/PCI clock */
6423 +#define SYCC_CD_SHF 16 /* CLockDivider shift */
6424 +
6425 +/* clockcontrol_n */
6426 +#define CN_N1_MASK 0x3f /* n1 control */
6427 +#define CN_N2_MASK 0x3f00 /* n2 control */
6428 +#define CN_N2_SHIFT 8
6429 +#define CN_PLLC_MASK 0xf0000 /* pll control */
6430 +#define CN_PLLC_SHIFT 16
6431 +
6432 +/* clockcontrol_sb/pci/uart */
6433 +#define CC_M1_MASK 0x3f /* m1 control */
6434 +#define CC_M2_MASK 0x3f00 /* m2 control */
6435 +#define CC_M2_SHIFT 8
6436 +#define CC_M3_MASK 0x3f0000 /* m3 control */
6437 +#define CC_M3_SHIFT 16
6438 +#define CC_MC_MASK 0x1f000000 /* mux control */
6439 +#define CC_MC_SHIFT 24
6440 +
6441 +/* N3M Clock control values for 125Mhz */
6442 +#define CC_125_N 0x0802 /* Default values for bcm4310 */
6443 +#define CC_125_M 0x04020009
6444 +#define CC_125_M25 0x11090009
6445 +#define CC_125_M33 0x11090005
6446 +
6447 +/* N3M Clock control magic field values */
6448 +#define CC_F6_2 0x02 /* A factor of 2 in */
6449 +#define CC_F6_3 0x03 /* 6-bit fields like */
6450 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
6451 +#define CC_F6_5 0x09
6452 +#define CC_F6_6 0x11
6453 +#define CC_F6_7 0x21
6454 +
6455 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
6456 +
6457 +#define CC_MC_BYPASS 0x08
6458 +#define CC_MC_M1 0x04
6459 +#define CC_MC_M1M2 0x02
6460 +#define CC_MC_M1M2M3 0x01
6461 +#define CC_MC_M1M3 0x11
6462 +
6463 +/* Type 2 Clock control magic field values */
6464 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
6465 +#define CC_T2M2_BIAS 3 /* m2 bias */
6466 +
6467 +#define CC_T2MC_M1BYP 1
6468 +#define CC_T2MC_M2BYP 2
6469 +#define CC_T2MC_M3BYP 4
6470 +
6471 +/* Type 6 Clock control magic field values */
6472 +#define CC_T6_MMASK 1 /* bits of interest in m */
6473 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
6474 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
6475 +#define SB2MIPS_T6(sb) (2 * (sb))
6476 +
6477 +/* Common clock base */
6478 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
6479 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
6480 +
6481 +/* Flash types in the chipcommon capabilities register */
6482 +#define FLASH_NONE 0x000 /* No flash */
6483 +#define SFLASH_ST 0x100 /* ST serial flash */
6484 +#define SFLASH_AT 0x200 /* Atmel serial flash */
6485 +#define PFLASH 0x700 /* Parallel flash */
6486 +
6487 +/* Bits in the config registers */
6488 +#define CC_CFG_EN 0x0001 /* Enable */
6489 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
6490 +#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
6491 +#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
6492 +#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
6493 +#define CC_CFG_EM_IDE 0x000a /* IDE */
6494 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
6495 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
6496 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
6497 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
6498 +
6499 +/* Start/busy bit in flashcontrol */
6500 +#define SFLASH_START 0x80000000
6501 +#define SFLASH_BUSY SFLASH_START
6502 +
6503 +/* flashcontrol opcodes for ST flashes */
6504 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
6505 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
6506 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
6507 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
6508 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
6509 +#define SFLASH_ST_PP 0x0302 /* Page Program */
6510 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
6511 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
6512 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
6513 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
6514 +
6515 +/* Status register bits for ST flashes */
6516 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
6517 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
6518 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
6519 +#define SFLASH_ST_BP_SHIFT 2
6520 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
6521 +
6522 +/* flashcontrol opcodes for Atmel flashes */
6523 +#define SFLASH_AT_READ 0x07e8
6524 +#define SFLASH_AT_PAGE_READ 0x07d2
6525 +#define SFLASH_AT_BUF1_READ
6526 +#define SFLASH_AT_BUF2_READ
6527 +#define SFLASH_AT_STATUS 0x01d7
6528 +#define SFLASH_AT_BUF1_WRITE 0x0384
6529 +#define SFLASH_AT_BUF2_WRITE 0x0387
6530 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
6531 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
6532 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
6533 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
6534 +#define SFLASH_AT_PAGE_ERASE 0x0281
6535 +#define SFLASH_AT_BLOCK_ERASE 0x0250
6536 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
6537 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
6538 +#define SFLASH_AT_BUF1_LOAD 0x0253
6539 +#define SFLASH_AT_BUF2_LOAD 0x0255
6540 +#define SFLASH_AT_BUF1_COMPARE 0x0260
6541 +#define SFLASH_AT_BUF2_COMPARE 0x0261
6542 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
6543 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
6544 +
6545 +/* Status register bits for Atmel flashes */
6546 +#define SFLASH_AT_READY 0x80
6547 +#define SFLASH_AT_MISMATCH 0x40
6548 +#define SFLASH_AT_ID_MASK 0x38
6549 +#define SFLASH_AT_ID_SHIFT 3
6550 +
6551 +/* OTP conventions */
6552 +#define OTP_HWBASE 0
6553 +#define OTP_SWLIM 256
6554 +#define OTP_CIDBASE 256
6555 +#define OTP_CIDLIM 260
6556 +
6557 +#define OTP_BOUNDARY 252
6558 +#define OTP_HWSIGN 253
6559 +#define OTP_SWSIGN 254
6560 +#define OTP_CIDSIGN 255
6561 +
6562 +#define OTP_CID 256
6563 +#define OTP_PKG 257
6564 +#define OTP_FID 258
6565 +
6566 +#define OTP_SIGNATURE 0x578a
6567 +#define OTP_MAGIC 0x4e56
6568 +
6569 +#endif /* _SBCHIPC_H */
6570 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/sbconfig.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/sbconfig.h
6571 --- linux-2.4.30/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
6572 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/sbconfig.h 2005-02-02 23:16:40.000000000 +0100
6573 @@ -0,0 +1,324 @@
6574 +/*
6575 + * Broadcom SiliconBackplane hardware register definitions.
6576 + *
6577 + * Copyright 2005, Broadcom Corporation
6578 + * All Rights Reserved.
6579 + *
6580 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6581 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6582 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6583 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6584 + * $Id$
6585 + */
6586 +
6587 +#ifndef _SBCONFIG_H
6588 +#define _SBCONFIG_H
6589 +
6590 +/* cpp contortions to concatenate w/arg prescan */
6591 +#ifndef PAD
6592 +#define _PADLINE(line) pad ## line
6593 +#define _XSTR(line) _PADLINE(line)
6594 +#define PAD _XSTR(__LINE__)
6595 +#endif
6596 +
6597 +/*
6598 + * SiliconBackplane Address Map.
6599 + * All regions may not exist on all chips.
6600 + */
6601 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
6602 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
6603 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
6604 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
6605 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
6606 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
6607 +
6608 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
6609 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
6610 +
6611 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
6612 +#define SB_FLASH1 0x1fc00000 /* Flash Region 1 */
6613 +#define SB_FLASH1_SZ 0x00400000 /* Size of Flash Region 1 */
6614 +
6615 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
6616 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
6617 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
6618 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
6619 +
6620 +/* enumeration space related defs */
6621 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
6622 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
6623 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
6624 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
6625 +
6626 +/* mips address */
6627 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
6628 +
6629 +/*
6630 + * Sonics Configuration Space Registers.
6631 + */
6632 +#define SBIPSFLAG 0x08
6633 +#define SBTPSFLAG 0x18
6634 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
6635 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
6636 +#define SBADMATCH3 0x60
6637 +#define SBADMATCH2 0x68
6638 +#define SBADMATCH1 0x70
6639 +#define SBIMSTATE 0x90
6640 +#define SBINTVEC 0x94
6641 +#define SBTMSTATELOW 0x98
6642 +#define SBTMSTATEHIGH 0x9c
6643 +#define SBBWA0 0xa0
6644 +#define SBIMCONFIGLOW 0xa8
6645 +#define SBIMCONFIGHIGH 0xac
6646 +#define SBADMATCH0 0xb0
6647 +#define SBTMCONFIGLOW 0xb8
6648 +#define SBTMCONFIGHIGH 0xbc
6649 +#define SBBCONFIG 0xc0
6650 +#define SBBSTATE 0xc8
6651 +#define SBACTCNFG 0xd8
6652 +#define SBFLAGST 0xe8
6653 +#define SBIDLOW 0xf8
6654 +#define SBIDHIGH 0xfc
6655 +
6656 +#ifndef _LANGUAGE_ASSEMBLY
6657 +
6658 +typedef volatile struct _sbconfig {
6659 + uint32 PAD[2];
6660 + uint32 sbipsflag; /* initiator port ocp slave flag */
6661 + uint32 PAD[3];
6662 + uint32 sbtpsflag; /* target port ocp slave flag */
6663 + uint32 PAD[11];
6664 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
6665 + uint32 PAD;
6666 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
6667 + uint32 PAD[3];
6668 + uint32 sbadmatch3; /* address match3 */
6669 + uint32 PAD;
6670 + uint32 sbadmatch2; /* address match2 */
6671 + uint32 PAD;
6672 + uint32 sbadmatch1; /* address match1 */
6673 + uint32 PAD[7];
6674 + uint32 sbimstate; /* initiator agent state */
6675 + uint32 sbintvec; /* interrupt mask */
6676 + uint32 sbtmstatelow; /* target state */
6677 + uint32 sbtmstatehigh; /* target state */
6678 + uint32 sbbwa0; /* bandwidth allocation table0 */
6679 + uint32 PAD;
6680 + uint32 sbimconfiglow; /* initiator configuration */
6681 + uint32 sbimconfighigh; /* initiator configuration */
6682 + uint32 sbadmatch0; /* address match0 */
6683 + uint32 PAD;
6684 + uint32 sbtmconfiglow; /* target configuration */
6685 + uint32 sbtmconfighigh; /* target configuration */
6686 + uint32 sbbconfig; /* broadcast configuration */
6687 + uint32 PAD;
6688 + uint32 sbbstate; /* broadcast state */
6689 + uint32 PAD[3];
6690 + uint32 sbactcnfg; /* activate configuration */
6691 + uint32 PAD[3];
6692 + uint32 sbflagst; /* current sbflags */
6693 + uint32 PAD[3];
6694 + uint32 sbidlow; /* identification */
6695 + uint32 sbidhigh; /* identification */
6696 +} sbconfig_t;
6697 +
6698 +#endif /* _LANGUAGE_ASSEMBLY */
6699 +
6700 +/* sbipsflag */
6701 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
6702 +#define SBIPS_INT1_SHIFT 0
6703 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
6704 +#define SBIPS_INT2_SHIFT 8
6705 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
6706 +#define SBIPS_INT3_SHIFT 16
6707 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
6708 +#define SBIPS_INT4_SHIFT 24
6709 +
6710 +/* sbtpsflag */
6711 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
6712 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
6713 +
6714 +/* sbtmerrlog */
6715 +#define SBTMEL_CM 0x00000007 /* command */
6716 +#define SBTMEL_CI 0x0000ff00 /* connection id */
6717 +#define SBTMEL_EC 0x0f000000 /* error code */
6718 +#define SBTMEL_ME 0x80000000 /* multiple error */
6719 +
6720 +/* sbimstate */
6721 +#define SBIM_PC 0xf /* pipecount */
6722 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
6723 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
6724 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
6725 +#define SBIM_AP_TK 0x20 /* use token only */
6726 +#define SBIM_AP_RSV 0x30 /* reserved */
6727 +#define SBIM_IBE 0x20000 /* inbanderror */
6728 +#define SBIM_TO 0x40000 /* timeout */
6729 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
6730 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
6731 +
6732 +/* sbtmstatelow */
6733 +#define SBTML_RESET 0x1 /* reset */
6734 +#define SBTML_REJ 0x2 /* reject */
6735 +#define SBTML_CLK 0x10000 /* clock enable */
6736 +#define SBTML_FGC 0x20000 /* force gated clocks on */
6737 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
6738 +#define SBTML_PE 0x40000000 /* pme enable */
6739 +#define SBTML_BE 0x80000000 /* bist enable */
6740 +
6741 +/* sbtmstatehigh */
6742 +#define SBTMH_SERR 0x1 /* serror */
6743 +#define SBTMH_INT 0x2 /* interrupt */
6744 +#define SBTMH_BUSY 0x4 /* busy */
6745 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
6746 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
6747 +#define SBTMH_GCR 0x20000000 /* gated clock request */
6748 +#define SBTMH_BISTF 0x40000000 /* bist failed */
6749 +#define SBTMH_BISTD 0x80000000 /* bist done */
6750 +
6751 +/* sbbwa0 */
6752 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
6753 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
6754 +#define SBBWA_TAB1_SHIFT 16
6755 +
6756 +/* sbimconfiglow */
6757 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
6758 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
6759 +#define SBIMCL_RTO_SHIFT 4
6760 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
6761 +#define SBIMCL_CID_SHIFT 16
6762 +
6763 +/* sbimconfighigh */
6764 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
6765 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
6766 +#define SBIMCH_TEM_SHIFT 4
6767 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
6768 +#define SBIMCH_BEM_SHIFT 6
6769 +
6770 +/* sbadmatch0 */
6771 +#define SBAM_TYPE_MASK 0x3 /* address type */
6772 +#define SBAM_AD64 0x4 /* reserved */
6773 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
6774 +#define SBAM_ADINT0_SHIFT 3
6775 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
6776 +#define SBAM_ADINT1_SHIFT 3
6777 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
6778 +#define SBAM_ADINT2_SHIFT 3
6779 +#define SBAM_ADEN 0x400 /* enable */
6780 +#define SBAM_ADNEG 0x800 /* negative decode */
6781 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
6782 +#define SBAM_BASE0_SHIFT 8
6783 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
6784 +#define SBAM_BASE1_SHIFT 12
6785 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
6786 +#define SBAM_BASE2_SHIFT 16
6787 +
6788 +/* sbtmconfiglow */
6789 +#define SBTMCL_CD_MASK 0xff /* clock divide */
6790 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
6791 +#define SBTMCL_CO_SHIFT 11
6792 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
6793 +#define SBTMCL_IF_SHIFT 18
6794 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
6795 +#define SBTMCL_IM_SHIFT 24
6796 +
6797 +/* sbtmconfighigh */
6798 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
6799 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
6800 +#define SBTMCH_RM_SHIFT 2
6801 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
6802 +#define SBTMCH_SM_SHIFT 4
6803 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
6804 +#define SBTMCH_EM_SHIFT 8
6805 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
6806 +#define SBTMCH_IM_SHIFT 10
6807 +
6808 +/* sbbconfig */
6809 +#define SBBC_LAT_MASK 0x3 /* sb latency */
6810 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
6811 +#define SBBC_MAX0_SHIFT 16
6812 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
6813 +#define SBBC_MAX1_SHIFT 20
6814 +
6815 +/* sbbstate */
6816 +#define SBBS_SRD 0x1 /* st reg disable */
6817 +#define SBBS_HRD 0x2 /* hold reg disable */
6818 +
6819 +/* sbidlow */
6820 +#define SBIDL_CS_MASK 0x3 /* config space */
6821 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
6822 +#define SBIDL_AR_SHIFT 3
6823 +#define SBIDL_SYNCH 0x40 /* sync */
6824 +#define SBIDL_INIT 0x80 /* initiator */
6825 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
6826 +#define SBIDL_MINLAT_SHIFT 8
6827 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
6828 +#define SBIDL_MAXLAT_SHIFT 12
6829 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
6830 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
6831 +#define SBIDL_CW_SHIFT 18
6832 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
6833 +#define SBIDL_TP_SHIFT 20
6834 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
6835 +#define SBIDL_IP_SHIFT 24
6836 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
6837 +#define SBIDL_RV_SHIFT 28
6838 +
6839 +/* sbidhigh */
6840 +#define SBIDH_RC_MASK 0xf /* revision code*/
6841 +#define SBIDH_CC_MASK 0xfff0 /* core code */
6842 +#define SBIDH_CC_SHIFT 4
6843 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
6844 +#define SBIDH_VC_SHIFT 16
6845 +
6846 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
6847 +
6848 +/* vendor codes */
6849 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
6850 +
6851 +/* core codes */
6852 +#define SB_CC 0x800 /* chipcommon core */
6853 +#define SB_ILINE20 0x801 /* iline20 core */
6854 +#define SB_SDRAM 0x803 /* sdram core */
6855 +#define SB_PCI 0x804 /* pci core */
6856 +#define SB_MIPS 0x805 /* mips core */
6857 +#define SB_ENET 0x806 /* enet mac core */
6858 +#define SB_CODEC 0x807 /* v90 codec core */
6859 +#define SB_USB 0x808 /* usb 1.1 host/device core */
6860 +#define SB_ADSL 0x809 /* ADSL core */
6861 +#define SB_ILINE100 0x80a /* iline100 core */
6862 +#define SB_IPSEC 0x80b /* ipsec core */
6863 +#define SB_PCMCIA 0x80d /* pcmcia core */
6864 +#define SB_SOCRAM 0x80e /* internal memory core */
6865 +#define SB_MEMC 0x80f /* memc sdram core */
6866 +#define SB_EXTIF 0x811 /* external interface core */
6867 +#define SB_D11 0x812 /* 802.11 MAC core */
6868 +#define SB_MIPS33 0x816 /* mips3302 core */
6869 +#define SB_USB11H 0x817 /* usb 1.1 host core */
6870 +#define SB_USB11D 0x818 /* usb 1.1 device core */
6871 +#define SB_USB20H 0x819 /* usb 2.0 host core */
6872 +#define SB_USB20D 0x81a /* usb 2.0 device core */
6873 +#define SB_SDIOH 0x81b /* sdio host core */
6874 +#define SB_ROBO 0x81c /* roboswitch core */
6875 +#define SB_ATA100 0x81d /* parallel ATA core */
6876 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
6877 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
6878 +
6879 +/* Not really related to Silicon Backplane, but a couple of software
6880 + * conventions for the use the flash space:
6881 + */
6882 +
6883 +/* Minumum amount of flash we support */
6884 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
6885 +
6886 +/* A boot/binary may have an embedded block that describes its size */
6887 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
6888 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
6889 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
6890 +#define BISZ_TXTST_IDX 1 /* 1: text start */
6891 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
6892 +#define BISZ_DATAST_IDX 3 /* 3: text start */
6893 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
6894 +#define BISZ_BSSST_IDX 5 /* 5: text start */
6895 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
6896 +
6897 +#endif /* _SBCONFIG_H */
6898 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/sbextif.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/sbextif.h
6899 --- linux-2.4.30/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
6900 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/sbextif.h 2005-02-02 23:16:40.000000000 +0100
6901 @@ -0,0 +1,242 @@
6902 +/*
6903 + * Hardware-specific External Interface I/O core definitions
6904 + * for the BCM47xx family of SiliconBackplane-based chips.
6905 + *
6906 + * The External Interface core supports a total of three external chip selects
6907 + * supporting external interfaces. One of the external chip selects is
6908 + * used for Flash, one is used for PCMCIA, and the other may be
6909 + * programmed to support either a synchronous interface or an
6910 + * asynchronous interface. The asynchronous interface can be used to
6911 + * support external devices such as UARTs and the BCM2019 Bluetooth
6912 + * baseband processor.
6913 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
6914 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
6915 + *
6916 + * Copyright 2005, Broadcom Corporation
6917 + * All Rights Reserved.
6918 + *
6919 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6920 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6921 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6922 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6923 + * $Id$
6924 + */
6925 +
6926 +#ifndef _SBEXTIF_H
6927 +#define _SBEXTIF_H
6928 +
6929 +/* external interface address space */
6930 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
6931 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
6932 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
6933 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
6934 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
6935 +
6936 +/* cpp contortions to concatenate w/arg prescan */
6937 +#ifndef PAD
6938 +#define _PADLINE(line) pad ## line
6939 +#define _XSTR(line) _PADLINE(line)
6940 +#define PAD _XSTR(__LINE__)
6941 +#endif /* PAD */
6942 +
6943 +/*
6944 + * The multiple instances of output and output enable registers
6945 + * are present to allow driver software for multiple cores to control
6946 + * gpio outputs without needing to share a single register pair.
6947 + */
6948 +struct gpiouser {
6949 + uint32 out;
6950 + uint32 outen;
6951 +};
6952 +#define NGPIOUSER 5
6953 +
6954 +typedef volatile struct {
6955 + uint32 corecontrol;
6956 + uint32 extstatus;
6957 + uint32 PAD[2];
6958 +
6959 + /* pcmcia control registers */
6960 + uint32 pcmcia_config;
6961 + uint32 pcmcia_memwait;
6962 + uint32 pcmcia_attrwait;
6963 + uint32 pcmcia_iowait;
6964 +
6965 + /* programmable interface control registers */
6966 + uint32 prog_config;
6967 + uint32 prog_waitcount;
6968 +
6969 + /* flash control registers */
6970 + uint32 flash_config;
6971 + uint32 flash_waitcount;
6972 + uint32 PAD[4];
6973 +
6974 + uint32 watchdog;
6975 +
6976 + /* clock control */
6977 + uint32 clockcontrol_n;
6978 + uint32 clockcontrol_sb;
6979 + uint32 clockcontrol_pci;
6980 + uint32 clockcontrol_mii;
6981 + uint32 PAD[3];
6982 +
6983 + /* gpio */
6984 + uint32 gpioin;
6985 + struct gpiouser gpio[NGPIOUSER];
6986 + uint32 PAD;
6987 + uint32 ejtagouten;
6988 + uint32 gpiointpolarity;
6989 + uint32 gpiointmask;
6990 + uint32 PAD[153];
6991 +
6992 + uint8 uartdata;
6993 + uint8 PAD[3];
6994 + uint8 uartimer;
6995 + uint8 PAD[3];
6996 + uint8 uartfcr;
6997 + uint8 PAD[3];
6998 + uint8 uartlcr;
6999 + uint8 PAD[3];
7000 + uint8 uartmcr;
7001 + uint8 PAD[3];
7002 + uint8 uartlsr;
7003 + uint8 PAD[3];
7004 + uint8 uartmsr;
7005 + uint8 PAD[3];
7006 + uint8 uartscratch;
7007 + uint8 PAD[3];
7008 +} extifregs_t;
7009 +
7010 +/* corecontrol */
7011 +#define CC_UE (1 << 0) /* uart enable */
7012 +
7013 +/* extstatus */
7014 +#define ES_EM (1 << 0) /* endian mode (ro) */
7015 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
7016 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
7017 +
7018 +/* gpio bit mask */
7019 +#define GPIO_BIT0 (1 << 0)
7020 +#define GPIO_BIT1 (1 << 1)
7021 +#define GPIO_BIT2 (1 << 2)
7022 +#define GPIO_BIT3 (1 << 3)
7023 +#define GPIO_BIT4 (1 << 4)
7024 +#define GPIO_BIT5 (1 << 5)
7025 +#define GPIO_BIT6 (1 << 6)
7026 +#define GPIO_BIT7 (1 << 7)
7027 +
7028 +
7029 +/* pcmcia/prog/flash_config */
7030 +#define CF_EN (1 << 0) /* enable */
7031 +#define CF_EM_MASK 0xe /* mode */
7032 +#define CF_EM_SHIFT 1
7033 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
7034 +#define CF_EM_SYNC 0x2 /* synchronous mode */
7035 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
7036 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
7037 +#define CF_BS (1 << 5) /* byteswap */
7038 +#define CF_CD_MASK 0xc0 /* clock divider */
7039 +#define CF_CD_SHIFT 6
7040 +#define CF_CD_DIV2 0x0 /* backplane/2 */
7041 +#define CF_CD_DIV3 0x40 /* backplane/3 */
7042 +#define CF_CD_DIV4 0x80 /* backplane/4 */
7043 +#define CF_CE (1 << 8) /* clock enable */
7044 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
7045 +
7046 +/* pcmcia_memwait */
7047 +#define PM_W0_MASK 0x3f /* waitcount0 */
7048 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
7049 +#define PM_W1_SHIFT 8
7050 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
7051 +#define PM_W2_SHIFT 16
7052 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
7053 +#define PM_W3_SHIFT 24
7054 +
7055 +/* pcmcia_attrwait */
7056 +#define PA_W0_MASK 0x3f /* waitcount0 */
7057 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
7058 +#define PA_W1_SHIFT 8
7059 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
7060 +#define PA_W2_SHIFT 16
7061 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
7062 +#define PA_W3_SHIFT 24
7063 +
7064 +/* pcmcia_iowait */
7065 +#define PI_W0_MASK 0x3f /* waitcount0 */
7066 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
7067 +#define PI_W1_SHIFT 8
7068 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
7069 +#define PI_W2_SHIFT 16
7070 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
7071 +#define PI_W3_SHIFT 24
7072 +
7073 +/* prog_waitcount */
7074 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
7075 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
7076 +#define PW_W1_SHIFT 8
7077 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
7078 +#define PW_W2_SHIFT 16
7079 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
7080 +#define PW_W3_SHIFT 24
7081 +
7082 +#define PW_W0 0x0000000c
7083 +#define PW_W1 0x00000a00
7084 +#define PW_W2 0x00020000
7085 +#define PW_W3 0x01000000
7086 +
7087 +/* flash_waitcount */
7088 +#define FW_W0_MASK 0x1f /* waitcount0 */
7089 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
7090 +#define FW_W1_SHIFT 8
7091 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
7092 +#define FW_W2_SHIFT 16
7093 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
7094 +#define FW_W3_SHIFT 24
7095 +
7096 +/* watchdog */
7097 +#define WATCHDOG_CLOCK 48000000 /* Hz */
7098 +
7099 +/* clockcontrol_n */
7100 +#define CN_N1_MASK 0x3f /* n1 control */
7101 +#define CN_N2_MASK 0x3f00 /* n2 control */
7102 +#define CN_N2_SHIFT 8
7103 +
7104 +/* clockcontrol_sb/pci/mii */
7105 +#define CC_M1_MASK 0x3f /* m1 control */
7106 +#define CC_M2_MASK 0x3f00 /* m2 control */
7107 +#define CC_M2_SHIFT 8
7108 +#define CC_M3_MASK 0x3f0000 /* m3 control */
7109 +#define CC_M3_SHIFT 16
7110 +#define CC_MC_MASK 0x1f000000 /* mux control */
7111 +#define CC_MC_SHIFT 24
7112 +
7113 +/* Clock control default values */
7114 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
7115 +#define CC_DEF_100 0x04020011
7116 +#define CC_DEF_33 0x11030011
7117 +#define CC_DEF_25 0x11050011
7118 +
7119 +/* Clock control values for 125Mhz */
7120 +#define CC_125_N 0x0802
7121 +#define CC_125_M 0x04020009
7122 +#define CC_125_M25 0x11090009
7123 +#define CC_125_M33 0x11090005
7124 +
7125 +/* Clock control magic field values */
7126 +#define CC_F6_2 0x02 /* A factor of 2 in */
7127 +#define CC_F6_3 0x03 /* 6-bit fields like */
7128 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
7129 +#define CC_F6_5 0x09
7130 +#define CC_F6_6 0x11
7131 +#define CC_F6_7 0x21
7132 +
7133 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
7134 +
7135 +#define CC_MC_BYPASS 0x08
7136 +#define CC_MC_M1 0x04
7137 +#define CC_MC_M1M2 0x02
7138 +#define CC_MC_M1M2M3 0x01
7139 +#define CC_MC_M1M3 0x11
7140 +
7141 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
7142 +
7143 +#endif /* _SBEXTIF_H */
7144 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/sbmemc.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/sbmemc.h
7145 --- linux-2.4.30/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
7146 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/sbmemc.h 2005-02-02 23:16:40.000000000 +0100
7147 @@ -0,0 +1,147 @@
7148 +/*
7149 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
7150 + *
7151 + * Copyright 2005, Broadcom Corporation
7152 + * All Rights Reserved.
7153 + *
7154 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7155 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7156 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7157 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7158 + *
7159 + * $Id$
7160 + */
7161 +
7162 +#ifndef _SBMEMC_H
7163 +#define _SBMEMC_H
7164 +
7165 +#ifdef _LANGUAGE_ASSEMBLY
7166 +
7167 +#define MEMC_CONTROL 0x00
7168 +#define MEMC_CONFIG 0x04
7169 +#define MEMC_REFRESH 0x08
7170 +#define MEMC_BISTSTAT 0x0c
7171 +#define MEMC_MODEBUF 0x10
7172 +#define MEMC_BKCLS 0x14
7173 +#define MEMC_PRIORINV 0x18
7174 +#define MEMC_DRAMTIM 0x1c
7175 +#define MEMC_INTSTAT 0x20
7176 +#define MEMC_INTMASK 0x24
7177 +#define MEMC_INTINFO 0x28
7178 +#define MEMC_NCDLCTL 0x30
7179 +#define MEMC_RDNCDLCOR 0x34
7180 +#define MEMC_WRNCDLCOR 0x38
7181 +#define MEMC_MISCDLYCTL 0x3c
7182 +#define MEMC_DQSGATENCDL 0x40
7183 +#define MEMC_SPARE 0x44
7184 +#define MEMC_TPADDR 0x48
7185 +#define MEMC_TPDATA 0x4c
7186 +#define MEMC_BARRIER 0x50
7187 +#define MEMC_CORE 0x54
7188 +
7189 +
7190 +#else
7191 +
7192 +/* Sonics side: MEMC core registers */
7193 +typedef volatile struct sbmemcregs {
7194 + uint32 control;
7195 + uint32 config;
7196 + uint32 refresh;
7197 + uint32 biststat;
7198 + uint32 modebuf;
7199 + uint32 bkcls;
7200 + uint32 priorinv;
7201 + uint32 dramtim;
7202 + uint32 intstat;
7203 + uint32 intmask;
7204 + uint32 intinfo;
7205 + uint32 reserved1;
7206 + uint32 ncdlctl;
7207 + uint32 rdncdlcor;
7208 + uint32 wrncdlcor;
7209 + uint32 miscdlyctl;
7210 + uint32 dqsgatencdl;
7211 + uint32 spare;
7212 + uint32 tpaddr;
7213 + uint32 tpdata;
7214 + uint32 barrier;
7215 + uint32 core;
7216 +} sbmemcregs_t;
7217 +
7218 +#endif
7219 +
7220 +/* MEMC Core Init values (OCP ID 0x80f) */
7221 +
7222 +/* For sdr: */
7223 +#define MEMC_SD_CONFIG_INIT 0x00048000
7224 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
7225 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
7226 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
7227 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
7228 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
7229 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
7230 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
7231 +#define MEMC_SD_CONTROL_INIT0 0x00000002
7232 +#define MEMC_SD_CONTROL_INIT1 0x00000008
7233 +#define MEMC_SD_CONTROL_INIT2 0x00000004
7234 +#define MEMC_SD_CONTROL_INIT3 0x00000010
7235 +#define MEMC_SD_CONTROL_INIT4 0x00000001
7236 +#define MEMC_SD_MODEBUF_INIT 0x00000000
7237 +#define MEMC_SD_REFRESH_INIT 0x0000840f
7238 +
7239 +
7240 +/* This is for SDRM8X8X4 */
7241 +#define MEMC_SDR_INIT 0x0008
7242 +#define MEMC_SDR_MODE 0x32
7243 +#define MEMC_SDR_NCDL 0x00020032
7244 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
7245 +
7246 +/* For ddr: */
7247 +#define MEMC_CONFIG_INIT 0x00048000
7248 +#define MEMC_DRAMTIM2_INIT 0x000754d8
7249 +#define MEMC_DRAMTIM25_INIT 0x000754d9
7250 +#define MEMC_RDNCDLCOR_INIT 0x00000000
7251 +#define MEMC_WRNCDLCOR_INIT 0x49351200
7252 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
7253 +#define MEMC_DQSGATENCDL_INIT 0x00030000
7254 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
7255 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
7256 +#define MEMC_NCDLCTL_INIT 0x00002001
7257 +#define MEMC_CONTROL_INIT0 0x00000002
7258 +#define MEMC_CONTROL_INIT1 0x00000008
7259 +#define MEMC_MODEBUF_INIT0 0x00004000
7260 +#define MEMC_CONTROL_INIT2 0x00000010
7261 +#define MEMC_MODEBUF_INIT1 0x00000100
7262 +#define MEMC_CONTROL_INIT3 0x00000010
7263 +#define MEMC_CONTROL_INIT4 0x00000008
7264 +#define MEMC_REFRESH_INIT 0x0000840f
7265 +#define MEMC_CONTROL_INIT5 0x00000004
7266 +#define MEMC_MODEBUF_INIT2 0x00000000
7267 +#define MEMC_CONTROL_INIT6 0x00000010
7268 +#define MEMC_CONTROL_INIT7 0x00000001
7269 +
7270 +
7271 +/* This is for DDRM16X16X2 */
7272 +#define MEMC_DDR_INIT 0x0009
7273 +#define MEMC_DDR_MODE 0x62
7274 +#define MEMC_DDR_NCDL 0x0005050a
7275 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
7276 +
7277 +/* mask for sdr/ddr calibration registers */
7278 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
7279 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
7280 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
7281 +
7282 +/* masks for miscdlyctl registers */
7283 +#define MEMC_MISC_SM_MASK 0x30000000
7284 +#define MEMC_MISC_SM_SHIFT 28
7285 +#define MEMC_MISC_SD_MASK 0x0f000000
7286 +#define MEMC_MISC_SD_SHIFT 24
7287 +
7288 +/* hw threshhold for calculating wr/rd for sdr memc */
7289 +#define MEMC_CD_THRESHOLD 128
7290 +
7291 +/* Low bit of init register says if memc is ddr or sdr */
7292 +#define MEMC_CONFIG_DDR 0x00000001
7293 +
7294 +#endif /* _SBMEMC_H */
7295 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/sbmips.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/sbmips.h
7296 --- linux-2.4.30/arch/mips/bcm947xx/include/sbmips.h 1970-01-01 01:00:00.000000000 +0100
7297 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/sbmips.h 2005-02-02 23:16:40.000000000 +0100
7298 @@ -0,0 +1,60 @@
7299 +/*
7300 + * Broadcom SiliconBackplane MIPS definitions
7301 + *
7302 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
7303 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
7304 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
7305 + * interface. The core revision is stored in the SB ID register in SB
7306 + * configuration space.
7307 + *
7308 + * Copyright 2005, Broadcom Corporation
7309 + * All Rights Reserved.
7310 + *
7311 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7312 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7313 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7314 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7315 + *
7316 + * $Id$
7317 + */
7318 +
7319 +#ifndef _SBMIPS_H
7320 +#define _SBMIPS_H
7321 +
7322 +#ifndef _LANGUAGE_ASSEMBLY
7323 +
7324 +/* cpp contortions to concatenate w/arg prescan */
7325 +#ifndef PAD
7326 +#define _PADLINE(line) pad ## line
7327 +#define _XSTR(line) _PADLINE(line)
7328 +#define PAD _XSTR(__LINE__)
7329 +#endif /* PAD */
7330 +
7331 +typedef volatile struct {
7332 + uint32 corecontrol;
7333 + uint32 PAD[2];
7334 + uint32 biststatus;
7335 + uint32 PAD[4];
7336 + uint32 intstatus;
7337 + uint32 intmask;
7338 + uint32 timer;
7339 +} mipsregs_t;
7340 +
7341 +extern uint32 sb_flag(void *sbh);
7342 +extern uint sb_irq(void *sbh);
7343 +
7344 +extern void BCMINIT(sb_serial_init)(void *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
7345 +
7346 +extern void *sb_jtagm_init(void *sbh, uint clkd, bool exttap);
7347 +extern void sb_jtagm_disable(void *h);
7348 +extern uint32 jtag_rwreg(void *h, uint32 ir, uint32 dr);
7349 +extern void BCMINIT(sb_mips_init)(void *sbh);
7350 +extern uint32 BCMINIT(sb_mips_clock)(void *sbh);
7351 +extern bool BCMINIT(sb_mips_setclock)(void *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
7352 +
7353 +extern uint32 BCMINIT(sb_memc_get_ncdl)(void *sbh);
7354 +extern uint32 BCMINIT(sb_mips_get_pfc)(void *sbh);
7355 +
7356 +#endif /* _LANGUAGE_ASSEMBLY */
7357 +
7358 +#endif /* _SBMIPS_H */
7359 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/sbpci.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/sbpci.h
7360 --- linux-2.4.30/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
7361 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/sbpci.h 2005-02-02 23:16:40.000000000 +0100
7362 @@ -0,0 +1,117 @@
7363 +/*
7364 + * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
7365 + *
7366 + * $Id$
7367 + * Copyright 2005, Broadcom Corporation
7368 + * All Rights Reserved.
7369 + *
7370 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7371 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7372 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7373 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7374 + */
7375 +
7376 +#ifndef _SBPCI_H
7377 +#define _SBPCI_H
7378 +
7379 +/* cpp contortions to concatenate w/arg prescan */
7380 +#ifndef PAD
7381 +#define _PADLINE(line) pad ## line
7382 +#define _XSTR(line) _PADLINE(line)
7383 +#define PAD _XSTR(__LINE__)
7384 +#endif
7385 +
7386 +/* Sonics side: PCI core and host control registers */
7387 +typedef struct sbpciregs {
7388 + uint32 control; /* PCI control */
7389 + uint32 PAD[3];
7390 + uint32 arbcontrol; /* PCI arbiter control */
7391 + uint32 PAD[3];
7392 + uint32 intstatus; /* Interrupt status */
7393 + uint32 intmask; /* Interrupt mask */
7394 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
7395 + uint32 PAD[9];
7396 + uint32 bcastaddr; /* Sonics broadcast address */
7397 + uint32 bcastdata; /* Sonics broadcast data */
7398 + uint32 PAD[2];
7399 + uint32 gpioin; /* ro: gpio input (>=rev2) */
7400 + uint32 gpioout; /* rw: gpio output (>=rev2) */
7401 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
7402 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
7403 + uint32 PAD[36];
7404 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
7405 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
7406 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
7407 + uint32 PAD[445];
7408 + uint16 sprom[36]; /* SPROM shadow Area */
7409 + uint32 PAD[46];
7410 +} sbpciregs_t;
7411 +
7412 +/* PCI control */
7413 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
7414 +#define PCI_RST 0x02 /* Value driven out to pin */
7415 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
7416 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
7417 +
7418 +/* PCI arbiter control */
7419 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
7420 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
7421 +#define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
7422 +#define PCI_PARKID_SHIFT 1
7423 +#define PCI_PARKID_LAST 0 /* Last requestor */
7424 +#define PCI_PARKID_4710 1 /* 4710 */
7425 +#define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
7426 +#define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
7427 +
7428 +/* Interrupt status/mask */
7429 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
7430 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
7431 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
7432 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
7433 +#define PCI_PME 0x10 /* PCI PME# is asserted */
7434 +
7435 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
7436 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
7437 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
7438 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
7439 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
7440 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
7441 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
7442 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
7443 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
7444 +
7445 +/* Sonics broadcast address */
7446 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
7447 +
7448 +/* Sonics to PCI translation types */
7449 +#define SBTOPCI0_MASK 0xfc000000
7450 +#define SBTOPCI1_MASK 0xfc000000
7451 +#define SBTOPCI2_MASK 0xc0000000
7452 +#define SBTOPCI_MEM 0
7453 +#define SBTOPCI_IO 1
7454 +#define SBTOPCI_CFG0 2
7455 +#define SBTOPCI_CFG1 3
7456 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
7457 +#define SBTOPCI_BURST 0x8 /* burst enable */
7458 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
7459 +#define SBTOPCI_RC_READ 0x00 /* memory read */
7460 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
7461 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
7462 +
7463 +/* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
7464 +#define cap_list rsvd_a[0]
7465 +#define bar0_window dev_dep[0x80 - 0x40]
7466 +#define bar1_window dev_dep[0x84 - 0x40]
7467 +#define sprom_control dev_dep[0x88 - 0x40]
7468 +
7469 +#ifndef _LANGUAGE_ASSEMBLY
7470 +
7471 +extern int sbpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
7472 +extern int sbpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
7473 +extern void sbpci_ban(uint16 core);
7474 +extern int sbpci_init(void *sbh);
7475 +extern void sbpci_check(void *sbh);
7476 +
7477 +#endif /* !_LANGUAGE_ASSEMBLY */
7478 +
7479 +#endif /* _SBPCI_H */
7480 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/sbpcmcia.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/sbpcmcia.h
7481 --- linux-2.4.30/arch/mips/bcm947xx/include/sbpcmcia.h 1970-01-01 01:00:00.000000000 +0100
7482 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/sbpcmcia.h 2005-02-02 23:16:40.000000000 +0100
7483 @@ -0,0 +1,139 @@
7484 +/*
7485 + * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
7486 + *
7487 + * $Id$
7488 + * Copyright 2005, Broadcom Corporation
7489 + * All Rights Reserved.
7490 + *
7491 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7492 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7493 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7494 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7495 + */
7496 +
7497 +#ifndef _SBPCMCIA_H
7498 +#define _SBPCMCIA_H
7499 +
7500 +
7501 +/* All the addresses that are offsets in attribute space are divided
7502 + * by two to account for the fact that odd bytes are invalid in
7503 + * attribute space and our read/write routines make the space appear
7504 + * as if they didn't exist. Still we want to show the original numbers
7505 + * as documented in the hnd_pcmcia core manual.
7506 + */
7507 +
7508 +/* PCMCIA Function Configuration Registers */
7509 +#define PCMCIA_FCR (0x700 / 2)
7510 +
7511 +#define FCR0_OFF 0
7512 +#define FCR1_OFF (0x40 / 2)
7513 +#define FCR2_OFF (0x80 / 2)
7514 +#define FCR3_OFF (0xc0 / 2)
7515 +
7516 +#define PCMCIA_FCR0 (0x700 / 2)
7517 +#define PCMCIA_FCR1 (0x740 / 2)
7518 +#define PCMCIA_FCR2 (0x780 / 2)
7519 +#define PCMCIA_FCR3 (0x7c0 / 2)
7520 +
7521 +/* Standard PCMCIA FCR registers */
7522 +
7523 +#define PCMCIA_COR 0
7524 +
7525 +#define COR_RST 0x80
7526 +#define COR_LEV 0x40
7527 +#define COR_IRQEN 0x04
7528 +#define COR_BLREN 0x01
7529 +#define COR_FUNEN 0x01
7530 +
7531 +
7532 +#define PCICIA_FCSR (2 / 2)
7533 +#define PCICIA_PRR (4 / 2)
7534 +#define PCICIA_SCR (6 / 2)
7535 +#define PCICIA_ESR (8 / 2)
7536 +
7537 +
7538 +#define PCM_MEMOFF 0x0000
7539 +#define F0_MEMOFF 0x1000
7540 +#define F1_MEMOFF 0x2000
7541 +#define F2_MEMOFF 0x3000
7542 +#define F3_MEMOFF 0x4000
7543 +
7544 +/* Memory base in the function fcr's */
7545 +#define MEM_ADDR0 (0x728 / 2)
7546 +#define MEM_ADDR1 (0x72a / 2)
7547 +#define MEM_ADDR2 (0x72c / 2)
7548 +
7549 +/* PCMCIA base plus Srom access in fcr0: */
7550 +#define PCMCIA_ADDR0 (0x072e / 2)
7551 +#define PCMCIA_ADDR1 (0x0730 / 2)
7552 +#define PCMCIA_ADDR2 (0x0732 / 2)
7553 +
7554 +#define MEM_SEG (0x0734 / 2)
7555 +#define SROM_CS (0x0736 / 2)
7556 +#define SROM_DATAL (0x0738 / 2)
7557 +#define SROM_DATAH (0x073a / 2)
7558 +#define SROM_ADDRL (0x073c / 2)
7559 +#define SROM_ADDRH (0x073e / 2)
7560 +
7561 +/* Values for srom_cs: */
7562 +#define SROM_IDLE 0
7563 +#define SROM_WRITE 1
7564 +#define SROM_READ 2
7565 +#define SROM_WEN 4
7566 +#define SROM_WDS 7
7567 +#define SROM_DONE 8
7568 +
7569 +/* CIS stuff */
7570 +
7571 +/* The CIS stops where the FCRs start */
7572 +#define CIS_SIZE PCMCIA_FCR
7573 +
7574 +/* Standard tuples we know about */
7575 +
7576 +#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
7577 +#define CISTPL_FUNCE 0x22 /* Function extensions */
7578 +#define CISTPL_CFTABLE 0x1b /* Config table entry */
7579 +
7580 +/* Function extensions for LANs */
7581 +
7582 +#define LAN_TECH 1 /* Technology type */
7583 +#define LAN_SPEED 2 /* Raw bit rate */
7584 +#define LAN_MEDIA 3 /* Transmission media */
7585 +#define LAN_NID 4 /* Node identification (aka MAC addr) */
7586 +#define LAN_CONN 5 /* Connector standard */
7587 +
7588 +
7589 +/* CFTable */
7590 +#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
7591 +#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
7592 +#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
7593 +
7594 +/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
7595 + * take one for HNBU, and use "extensions" (a la FUNCE) within it.
7596 + */
7597 +
7598 +#define CISTPL_BRCM_HNBU 0x80
7599 +
7600 +/* Subtypes of BRCM_HNBU: */
7601 +
7602 +#define HNBU_CHIPID 0x01 /* Six bytes with PCI vendor &
7603 + * device id and chiprev
7604 + */
7605 +#define HNBU_BOARDREV 0x02 /* Two bytes board revision */
7606 +#define HNBU_PAPARMS 0x03 /* Eleven bytes PA parameters */
7607 +#define HNBU_OEM 0x04 /* Eight bytes OEM data */
7608 +#define HNBU_CC 0x05 /* Default country code */
7609 +#define HNBU_AA 0x06 /* Antennas available */
7610 +#define HNBU_AG 0x07 /* Antenna gain */
7611 +#define HNBU_BOARDFLAGS 0x08 /* board flags */
7612 +#define HNBU_LED 0x09 /* LED set */
7613 +
7614 +
7615 +/* sbtmstatelow */
7616 +#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
7617 +#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
7618 +
7619 +/* sbtmstatehigh */
7620 +#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
7621 +
7622 +#endif /* _SBPCMCIA_H */
7623 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/sbsdram.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/sbsdram.h
7624 --- linux-2.4.30/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
7625 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/sbsdram.h 2005-02-02 23:16:40.000000000 +0100
7626 @@ -0,0 +1,75 @@
7627 +/*
7628 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
7629 + *
7630 + * Copyright 2005, Broadcom Corporation
7631 + * All Rights Reserved.
7632 + *
7633 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7634 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7635 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7636 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7637 + * $Id$
7638 + */
7639 +
7640 +#ifndef _SBSDRAM_H
7641 +#define _SBSDRAM_H
7642 +
7643 +#ifndef _LANGUAGE_ASSEMBLY
7644 +
7645 +/* Sonics side: SDRAM core registers */
7646 +typedef volatile struct sbsdramregs {
7647 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
7648 + uint32 config; /* Initializes external SDRAM mode register */
7649 + uint32 refresh; /* Controls external SDRAM refresh rate */
7650 + uint32 pad1;
7651 + uint32 pad2;
7652 +} sbsdramregs_t;
7653 +
7654 +#endif
7655 +
7656 +/* SDRAM initialization control (initcontrol) register bits */
7657 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
7658 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
7659 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
7660 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
7661 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
7662 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
7663 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
7664 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
7665 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
7666 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
7667 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
7668 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
7669 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
7670 +
7671 +/* SDRAM configuration (config) register bits */
7672 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
7673 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
7674 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
7675 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
7676 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
7677 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
7678 +
7679 +/* SDRAM refresh control (refresh) register bits */
7680 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
7681 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
7682 +
7683 +/* SDRAM Core default Init values (OCP ID 0x803) */
7684 +#define SDRAM_INIT MEM4MX16X2
7685 +#define SDRAM_CONFIG SDRAM_BURSTFULL
7686 +#define SDRAM_REFRESH SDRAM_REF(0x40)
7687 +
7688 +#define MEM1MX16 0x009 /* 2 MB */
7689 +#define MEM1MX16X2 0x409 /* 4 MB */
7690 +#define MEM2MX8X2 0x809 /* 4 MB */
7691 +#define MEM2MX8X4 0xc09 /* 8 MB */
7692 +#define MEM2MX32 0x439 /* 8 MB */
7693 +#define MEM4MX16 0x019 /* 8 MB */
7694 +#define MEM4MX16X2 0x419 /* 16 MB */
7695 +#define MEM8MX8X2 0x819 /* 16 MB */
7696 +#define MEM8MX16 0x829 /* 16 MB */
7697 +#define MEM4MX32 0x429 /* 16 MB */
7698 +#define MEM8MX8X4 0xc19 /* 32 MB */
7699 +#define MEM8MX16X2 0xc29 /* 32 MB */
7700 +
7701 +#endif /* _SBSDRAM_H */
7702 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/sbsocram.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/sbsocram.h
7703 --- linux-2.4.30/arch/mips/bcm947xx/include/sbsocram.h 1970-01-01 01:00:00.000000000 +0100
7704 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/sbsocram.h 2005-02-02 23:16:40.000000000 +0100
7705 @@ -0,0 +1,37 @@
7706 +/*
7707 + * BCM47XX Sonics SiliconBackplane embedded ram core
7708 + *
7709 + * Copyright 2005, Broadcom Corporation
7710 + * All Rights Reserved.
7711 + *
7712 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7713 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7714 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7715 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7716 + *
7717 + * $Id$
7718 + */
7719 +
7720 +#ifndef _SBSOCRAM_H
7721 +#define _SBSOCRAM_H
7722 +
7723 +#define SOCRAM_MEMSIZE 0x00
7724 +#define SOCRAM_BISTSTAT 0x0c
7725 +
7726 +
7727 +#ifndef _LANGUAGE_ASSEMBLY
7728 +
7729 +/* Memcsocram core registers */
7730 +typedef volatile struct sbsocramregs {
7731 + uint32 memsize;
7732 + uint32 biststat;
7733 +} sbsocramregs_t;
7734 +
7735 +#endif
7736 +
7737 +/* Them memory size is 2 to the power of the following
7738 + * base added to the contents of the memsize register.
7739 + */
7740 +#define SOCRAM_MEMSIZE_BASESHIFT 16
7741 +
7742 +#endif /* _SBSOCRAM_H */
7743 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/sbutils.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/sbutils.h
7744 --- linux-2.4.30/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
7745 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/sbutils.h 2005-02-02 23:16:40.000000000 +0100
7746 @@ -0,0 +1,87 @@
7747 +/*
7748 + * Misc utility routines for accessing chip-specific features
7749 + * of Broadcom HNBU SiliconBackplane-based chips.
7750 + *
7751 + * Copyright 2005, Broadcom Corporation
7752 + * All Rights Reserved.
7753 + *
7754 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7755 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7756 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7757 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7758 + *
7759 + * $Id$
7760 + */
7761 +
7762 +#ifndef _sbutils_h_
7763 +#define _sbutils_h_
7764 +
7765 +/*
7766 + * Many of the routines below take an 'sbh' handle as their first arg.
7767 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
7768 + * At any one time, the sbh is logically focused on one particular sb core
7769 + * (the "current core").
7770 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
7771 + */
7772 +
7773 +/* exported externs */
7774 +extern void * BCMINIT(sb_attach)(uint pcidev, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
7775 +extern void * BCMINIT(sb_kattach)(void);
7776 +extern void sb_detach(void *sbh);
7777 +extern uint BCMINIT(sb_chip)(void *sbh);
7778 +extern uint BCMINIT(sb_chiprev)(void *sbh);
7779 +extern uint BCMINIT(sb_chipcrev)(void *sbh);
7780 +extern uint BCMINIT(sb_chippkg)(void *sbh);
7781 +extern uint BCMINIT(sb_pcirev)(void *sbh);
7782 +extern uint BCMINIT(sb_pcmciarev)(void *sbh);
7783 +extern uint BCMINIT(sb_boardvendor)(void *sbh);
7784 +extern uint BCMINIT(sb_boardtype)(void *sbh);
7785 +extern uint sb_bus(void *sbh);
7786 +extern uint sb_corelist(void *sbh, uint coreid[]);
7787 +extern uint sb_coreid(void *sbh);
7788 +extern uint sb_coreidx(void *sbh);
7789 +extern uint sb_coreunit(void *sbh);
7790 +extern uint sb_corevendor(void *sbh);
7791 +extern uint sb_corerev(void *sbh);
7792 +extern void *sb_osh(void *sbh);
7793 +extern void *sb_coreregs(void *sbh);
7794 +extern uint32 sb_coreflags(void *sbh, uint32 mask, uint32 val);
7795 +extern uint32 sb_coreflagshi(void *sbh, uint32 mask, uint32 val);
7796 +extern bool sb_iscoreup(void *sbh);
7797 +extern void *sb_setcoreidx(void *sbh, uint coreidx);
7798 +extern void *sb_setcore(void *sbh, uint coreid, uint coreunit);
7799 +extern void sb_commit(void *sbh);
7800 +extern uint32 sb_base(uint32 admatch);
7801 +extern uint32 sb_size(uint32 admatch);
7802 +extern void sb_core_reset(void *sbh, uint32 bits);
7803 +extern void sb_core_tofixup(void *sbh);
7804 +extern void sb_core_disable(void *sbh, uint32 bits);
7805 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
7806 +extern uint32 sb_clock(void *sbh);
7807 +extern void sb_pci_setup(void *sbh, uint32 *dmaoffset, uint coremask);
7808 +extern void sb_pcmcia_init(void *sbh);
7809 +extern void sb_watchdog(void *sbh, uint ticks);
7810 +extern void *sb_gpiosetcore(void *sbh);
7811 +extern uint32 sb_gpiocontrol(void *sbh, uint32 mask, uint32 val);
7812 +extern uint32 sb_gpioouten(void *sbh, uint32 mask, uint32 val);
7813 +extern uint32 sb_gpioout(void *sbh, uint32 mask, uint32 val);
7814 +extern uint32 sb_gpioin(void *sbh);
7815 +extern uint32 sb_gpiointpolarity(void *sbh, uint32 mask, uint32 val);
7816 +extern uint32 sb_gpiointmask(void *sbh, uint32 mask, uint32 val);
7817 +extern void sb_pwrctl_init(void *sbh);
7818 +extern uint16 sb_pwrctl_fast_pwrup_delay(void *sbh);
7819 +extern bool sb_pwrctl_clk(void *sbh, uint mode);
7820 +extern int sb_pwrctl_xtal(void *sbh, uint what, bool on);
7821 +extern int sb_pwrctl_slowclk(void *sbh, bool set, uint *div);
7822 +extern void sb_register_intr_callback(void *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg);
7823 +
7824 +/* pwrctl xtal what flags */
7825 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
7826 +#define PLL 0x2 /* main chip pll */
7827 +
7828 +/* pwrctl clk mode */
7829 +#define CLK_FAST 0 /* force fast (pll) clock */
7830 +#define CLK_SLOW 1 /* force slow clock */
7831 +#define CLK_DYNAMIC 2 /* enable dynamic power control */
7832 +
7833 +#endif /* _sbutils_h_ */
7834 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/sflash.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/sflash.h
7835 --- linux-2.4.30/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
7836 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/sflash.h 2005-02-02 23:16:40.000000000 +0100
7837 @@ -0,0 +1,36 @@
7838 +/*
7839 + * Broadcom SiliconBackplane chipcommon serial flash interface
7840 + *
7841 + * Copyright 2005, Broadcom Corporation
7842 + * All Rights Reserved.
7843 + *
7844 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7845 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7846 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7847 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7848 + *
7849 + * $Id$
7850 + */
7851 +
7852 +#ifndef _sflash_h_
7853 +#define _sflash_h_
7854 +
7855 +#include <typedefs.h>
7856 +#include <sbchipc.h>
7857 +
7858 +struct sflash {
7859 + uint blocksize; /* Block size */
7860 + uint numblocks; /* Number of blocks */
7861 + uint32 type; /* Type */
7862 + uint size; /* Total size in bytes */
7863 +};
7864 +
7865 +/* Utility functions */
7866 +extern int sflash_poll(chipcregs_t *cc, uint offset);
7867 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
7868 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
7869 +extern int sflash_erase(chipcregs_t *cc, uint offset);
7870 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
7871 +extern struct sflash * sflash_init(chipcregs_t *cc);
7872 +
7873 +#endif /* _sflash_h_ */
7874 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/trxhdr.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/trxhdr.h
7875 --- linux-2.4.30/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
7876 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/trxhdr.h 2005-02-02 23:16:40.000000000 +0100
7877 @@ -0,0 +1,33 @@
7878 +/*
7879 + * TRX image file header format.
7880 + *
7881 + * Copyright 2005, Broadcom Corporation
7882 + * All Rights Reserved.
7883 + *
7884 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7885 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7886 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7887 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7888 + *
7889 + * $Id$
7890 + */
7891 +
7892 +#include <typedefs.h>
7893 +
7894 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
7895 +#define TRX_VERSION 1
7896 +#define TRX_MAX_LEN 0x3A0000
7897 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
7898 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
7899 +#define TRX_MAX_OFFSET 3
7900 +
7901 +struct trx_header {
7902 + uint32 magic; /* "HDR0" */
7903 + uint32 len; /* Length of file including header */
7904 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
7905 + uint32 flag_version; /* 0:15 flags, 16:31 version */
7906 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
7907 +};
7908 +
7909 +/* Compatibility */
7910 +typedef struct trx_header TRXHDR, *PTRXHDR;
7911 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/typedefs.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/typedefs.h
7912 --- linux-2.4.30/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
7913 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/typedefs.h 2005-02-02 23:16:40.000000000 +0100
7914 @@ -0,0 +1,322 @@
7915 +/*
7916 + * Copyright 2005, Broadcom Corporation
7917 + * All Rights Reserved.
7918 + *
7919 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7920 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7921 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7922 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7923 + * $Id$
7924 + */
7925 +
7926 +#ifndef _TYPEDEFS_H_
7927 +#define _TYPEDEFS_H_
7928 +
7929 +
7930 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
7931 + * typedef file "site_typedefs.h".
7932 + *
7933 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
7934 + * section of this file makes inferences about the compile environment
7935 + * based on defined symbols and possibly compiler pragmas.
7936 + *
7937 + * Following these two sections is the "Default Typedefs"
7938 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
7939 + * defined. This section has a default set of typedefs and a few
7940 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
7941 + */
7942 +
7943 +#ifdef SITE_TYPEDEFS
7944 +
7945 +/*******************************************************************************
7946 + * Site Specific Typedefs
7947 + *******************************************************************************/
7948 +
7949 +#include "site_typedefs.h"
7950 +
7951 +#else
7952 +
7953 +/*******************************************************************************
7954 + * Inferred Typedefs
7955 + *******************************************************************************/
7956 +
7957 +/* Infer the compile environment based on preprocessor symbols and pramas.
7958 + * Override type definitions as needed, and include configuration dependent
7959 + * header files to define types.
7960 + */
7961 +
7962 +#ifdef __cplusplus
7963 +
7964 +#define TYPEDEF_BOOL
7965 +#ifndef FALSE
7966 +#define FALSE false
7967 +#endif
7968 +#ifndef TRUE
7969 +#define TRUE true
7970 +#endif
7971 +
7972 +#else /* ! __cplusplus */
7973 +
7974 +#if defined(_WIN32)
7975 +
7976 +#define TYPEDEF_BOOL
7977 +typedef unsigned char bool; /* consistent w/BOOL */
7978 +
7979 +#endif /* _WIN32 */
7980 +
7981 +#endif /* ! __cplusplus */
7982 +
7983 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
7984 +#if defined(_WIN64)
7985 +#include <basetsd.h>
7986 +#define TYPEDEF_UINTPTR
7987 +typedef ULONG_PTR uintptr;
7988 +#endif
7989 +
7990 +#ifdef _MSC_VER /* Microsoft C */
7991 +#define TYPEDEF_INT64
7992 +#define TYPEDEF_UINT64
7993 +typedef signed __int64 int64;
7994 +typedef unsigned __int64 uint64;
7995 +#endif
7996 +
7997 +#if defined(MACOSX) && defined(KERNEL)
7998 +#define TYPEDEF_BOOL
7999 +#endif
8000 +
8001 +
8002 +#if defined(linux)
8003 +#define TYPEDEF_UINT
8004 +#define TYPEDEF_USHORT
8005 +#define TYPEDEF_ULONG
8006 +#endif
8007 +
8008 +#if !defined(linux) && !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
8009 +#define TYPEDEF_UINT
8010 +#define TYPEDEF_USHORT
8011 +#endif
8012 +
8013 +
8014 +/* Do not support the (u)int64 types with strict ansi for GNU C */
8015 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
8016 +#define TYPEDEF_INT64
8017 +#define TYPEDEF_UINT64
8018 +#endif
8019 +
8020 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
8021 + * for singned or unsigned */
8022 +#if defined(__ICL)
8023 +
8024 +#define TYPEDEF_INT64
8025 +
8026 +#if defined(__STDC__)
8027 +#define TYPEDEF_UINT64
8028 +#endif
8029 +
8030 +#endif /* __ICL */
8031 +
8032 +
8033 +#if !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
8034 +
8035 +/* pick up ushort & uint from standard types.h */
8036 +#if defined(linux) && defined(__KERNEL__)
8037 +
8038 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
8039 +
8040 +#else
8041 +
8042 +#include <sys/types.h>
8043 +
8044 +#endif
8045 +
8046 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ */
8047 +
8048 +#if defined(MACOSX) && defined(KERNEL)
8049 +#include <IOKit/IOTypes.h>
8050 +#endif
8051 +
8052 +
8053 +/* use the default typedefs in the next section of this file */
8054 +#define USE_TYPEDEF_DEFAULTS
8055 +
8056 +#endif /* SITE_TYPEDEFS */
8057 +
8058 +
8059 +/*******************************************************************************
8060 + * Default Typedefs
8061 + *******************************************************************************/
8062 +
8063 +#ifdef USE_TYPEDEF_DEFAULTS
8064 +#undef USE_TYPEDEF_DEFAULTS
8065 +
8066 +#ifndef TYPEDEF_BOOL
8067 +typedef /*@abstract@*/ unsigned char bool;
8068 +#endif
8069 +
8070 +/*----------------------- define uchar, ushort, uint, ulong ------------------*/
8071 +
8072 +#ifndef TYPEDEF_UCHAR
8073 +typedef unsigned char uchar;
8074 +#endif
8075 +
8076 +#ifndef TYPEDEF_USHORT
8077 +typedef unsigned short ushort;
8078 +#endif
8079 +
8080 +#ifndef TYPEDEF_UINT
8081 +typedef unsigned int uint;
8082 +#endif
8083 +
8084 +#ifndef TYPEDEF_ULONG
8085 +typedef unsigned long ulong;
8086 +#endif
8087 +
8088 +/*----------------------- define [u]int8/16/32/64, uintptr --------------------*/
8089 +
8090 +#ifndef TYPEDEF_UINT8
8091 +typedef unsigned char uint8;
8092 +#endif
8093 +
8094 +#ifndef TYPEDEF_UINT16
8095 +typedef unsigned short uint16;
8096 +#endif
8097 +
8098 +#ifndef TYPEDEF_UINT32
8099 +typedef unsigned int uint32;
8100 +#endif
8101 +
8102 +#ifndef TYPEDEF_UINT64
8103 +typedef unsigned long long uint64;
8104 +#endif
8105 +
8106 +#ifndef TYPEDEF_UINTPTR
8107 +typedef unsigned int uintptr;
8108 +#endif
8109 +
8110 +#ifndef TYPEDEF_INT8
8111 +typedef signed char int8;
8112 +#endif
8113 +
8114 +#ifndef TYPEDEF_INT16
8115 +typedef signed short int16;
8116 +#endif
8117 +
8118 +#ifndef TYPEDEF_INT32
8119 +typedef signed int int32;
8120 +#endif
8121 +
8122 +#ifndef TYPEDEF_INT64
8123 +typedef signed long long int64;
8124 +#endif
8125 +
8126 +/*----------------------- define float32/64, float_t -----------------------*/
8127 +
8128 +#ifndef TYPEDEF_FLOAT32
8129 +typedef float float32;
8130 +#endif
8131 +
8132 +#ifndef TYPEDEF_FLOAT64
8133 +typedef double float64;
8134 +#endif
8135 +
8136 +/*
8137 + * abstracted floating point type allows for compile time selection of
8138 + * single or double precision arithmetic. Compiling with -DFLOAT32
8139 + * selects single precision; the default is double precision.
8140 + */
8141 +
8142 +#ifndef TYPEDEF_FLOAT_T
8143 +
8144 +#if defined(FLOAT32)
8145 +typedef float32 float_t;
8146 +#else /* default to double precision floating point */
8147 +typedef float64 float_t;
8148 +#endif
8149 +
8150 +#endif /* TYPEDEF_FLOAT_T */
8151 +
8152 +/*----------------------- define macro values -----------------------------*/
8153 +
8154 +#ifndef FALSE
8155 +#define FALSE 0
8156 +#endif
8157 +
8158 +#ifndef TRUE
8159 +#define TRUE 1
8160 +#endif
8161 +
8162 +#ifndef NULL
8163 +#define NULL 0
8164 +#endif
8165 +
8166 +#ifndef OFF
8167 +#define OFF 0
8168 +#endif
8169 +
8170 +#ifndef ON
8171 +#define ON 1
8172 +#endif
8173 +
8174 +#define AUTO (-1)
8175 +
8176 +/* Reclaiming text and data :
8177 + The following macros specify special linker sections that can be reclaimed
8178 + after a system is considered 'up'.
8179 + */
8180 +#if defined(__GNUC__) && defined(BCMRECLAIM)
8181 +extern bool bcmreclaimed;
8182 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data##_ini
8183 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn##_ini
8184 +#define BCMINIT(_id) _id##_ini
8185 +#else
8186 +#define BCMINITDATA(_data) _data
8187 +#define BCMINITFN(_fn) _fn
8188 +#define BCMINIT(_id) _id
8189 +#define bcmreclaimed 0
8190 +#endif
8191 +
8192 +/*----------------------- define PTRSZ, INLINE ----------------------------*/
8193 +
8194 +#ifndef PTRSZ
8195 +#define PTRSZ sizeof (char*)
8196 +#endif
8197 +
8198 +#ifndef INLINE
8199 +
8200 +#ifdef _MSC_VER
8201 +
8202 +#define INLINE __inline
8203 +
8204 +#elif __GNUC__
8205 +
8206 +#define INLINE __inline__
8207 +
8208 +#else
8209 +
8210 +#define INLINE
8211 +
8212 +#endif /* _MSC_VER */
8213 +
8214 +#endif /* INLINE */
8215 +
8216 +#undef TYPEDEF_BOOL
8217 +#undef TYPEDEF_UCHAR
8218 +#undef TYPEDEF_USHORT
8219 +#undef TYPEDEF_UINT
8220 +#undef TYPEDEF_ULONG
8221 +#undef TYPEDEF_UINT8
8222 +#undef TYPEDEF_UINT16
8223 +#undef TYPEDEF_UINT32
8224 +#undef TYPEDEF_UINT64
8225 +#undef TYPEDEF_UINTPTR
8226 +#undef TYPEDEF_INT8
8227 +#undef TYPEDEF_INT16
8228 +#undef TYPEDEF_INT32
8229 +#undef TYPEDEF_INT64
8230 +#undef TYPEDEF_FLOAT32
8231 +#undef TYPEDEF_FLOAT64
8232 +#undef TYPEDEF_FLOAT_T
8233 +
8234 +#endif /* USE_TYPEDEF_DEFAULTS */
8235 +
8236 +#endif /* _TYPEDEFS_H_ */
8237 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/wlioctl.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/wlioctl.h
8238 --- linux-2.4.30/arch/mips/bcm947xx/include/wlioctl.h 1970-01-01 01:00:00.000000000 +0100
8239 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/wlioctl.h 2005-02-02 23:16:40.000000000 +0100
8240 @@ -0,0 +1,825 @@
8241 +/*
8242 + * Custom OID/ioctl definitions for
8243 + * Broadcom 802.11abg Networking Device Driver
8244 + *
8245 + * Definitions subject to change without notice.
8246 + *
8247 + * Copyright 2005, Broadcom Corporation
8248 + * All Rights Reserved.
8249 + *
8250 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8251 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8252 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8253 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8254 + *
8255 + * $Id$
8256 + */
8257 +
8258 +#ifndef _wlioctl_h_
8259 +#define _wlioctl_h_
8260 +
8261 +#include <typedefs.h>
8262 +#include <proto/ethernet.h>
8263 +#include <proto/802.11.h>
8264 +
8265 +/* require default structure packing */
8266 +#if !defined(__GNUC__)
8267 +#pragma pack(push,8)
8268 +#endif
8269 +
8270 +#define WL_NUMRATES 255 /* max # of rates in a rateset */
8271 +
8272 +typedef struct wl_rateset {
8273 + uint32 count; /* # rates in this set */
8274 + uint8 rates[WL_NUMRATES]; /* rates in 500kbps units w/hi bit set if basic */
8275 +} wl_rateset_t;
8276 +
8277 +#define WL_CHANSPEC_CHAN_MASK 0x0fff
8278 +#define WL_CHANSPEC_BAND_MASK 0xf000
8279 +#define WL_CHANSPEC_BAND_SHIFT 12
8280 +#define WL_CHANSPEC_BAND_A 0x1000
8281 +#define WL_CHANSPEC_BAND_B 0x2000
8282 +
8283 +/*
8284 + * Per-bss information structure.
8285 + */
8286 +
8287 +#define WL_BSS_INFO_VERSION 107 /* current version of wl_bss_info struct */
8288 +
8289 +typedef struct wl_bss_info {
8290 + uint32 version; /* version field */
8291 + uint32 length; /* byte length of data in this record, starting at version and including IEs */
8292 + struct ether_addr BSSID;
8293 + uint16 beacon_period; /* units are Kusec */
8294 + uint16 capability; /* Capability information */
8295 + uint8 SSID_len;
8296 + uint8 SSID[32];
8297 + struct {
8298 + uint count; /* # rates in this set */
8299 + uint8 rates[16]; /* rates in 500kbps units w/hi bit set if basic */
8300 + } rateset; /* supported rates */
8301 + uint8 channel; /* Channel no. */
8302 + uint16 atim_window; /* units are Kusec */
8303 + uint8 dtim_period; /* DTIM period */
8304 + int16 RSSI; /* receive signal strength (in dBm) */
8305 + int8 phy_noise; /* noise (in dBm) */
8306 + uint32 ie_length; /* byte length of Information Elements */
8307 + /* variable length Information Elements */
8308 +} wl_bss_info_t;
8309 +
8310 +typedef struct wlc_ssid {
8311 + uint32 SSID_len;
8312 + uchar SSID[32];
8313 +} wlc_ssid_t;
8314 +
8315 +typedef struct wl_scan_params {
8316 + wlc_ssid_t ssid; /* default is {0, ""} */
8317 + struct ether_addr bssid;/* default is bcast */
8318 + int8 bss_type; /* default is any, DOT11_BSSTYPE_ANY/INFRASTRUCTURE/INDEPENDENT */
8319 + int8 scan_type; /* -1 use default, DOT11_SCANTYPE_ACTIVE/PASSIVE */
8320 + int32 nprobes; /* -1 use default, number of probes per channel */
8321 + int32 active_time; /* -1 use default, dwell time per channel for active scanning */
8322 + int32 passive_time; /* -1 use default, dwell time per channel for passive scanning */
8323 + int32 home_time; /* -1 use default, dwell time for the home channel between channel scans */
8324 + int32 channel_num; /* 0 use default (all available channels), count of channels in channel_list */
8325 + uint16 channel_list[1]; /* list of chanspecs */
8326 +} wl_scan_params_t;
8327 +/* size of wl_scan_params not including variable length array */
8328 +#define WL_SCAN_PARAMS_FIXED_SIZE 64
8329 +
8330 +typedef struct wl_scan_results {
8331 + uint32 buflen;
8332 + uint32 version;
8333 + uint32 count;
8334 + wl_bss_info_t bss_info[1];
8335 +} wl_scan_results_t;
8336 +/* size of wl_scan_results not including variable length array */
8337 +#define WL_SCAN_RESULTS_FIXED_SIZE 12
8338 +
8339 +/* uint32 list */
8340 +typedef struct wl_uint32_list {
8341 + /* in - # of elements, out - # of entries */
8342 + uint32 count;
8343 + /* variable length uint32 list */
8344 + uint32 element[1];
8345 +} wl_uint32_list_t;
8346 +
8347 +#define WLC_CNTRY_BUF_SZ 4 /* Country string is 3 bytes + NULL */
8348 +
8349 +typedef struct wl_channels_in_country {
8350 + uint32 buflen;
8351 + uint32 band;
8352 + char country_abbrev[WLC_CNTRY_BUF_SZ];
8353 + uint32 count;
8354 + uint32 channel[1];
8355 +} wl_channels_in_country_t;
8356 +
8357 +typedef struct wl_country_list {
8358 + uint32 buflen;
8359 + uint32 band_set;
8360 + uint32 band;
8361 + uint32 count;
8362 + char country_abbrev[1];
8363 +} wl_country_list_t;
8364 +
8365 +#define WL_RM_TYPE_BASIC 1
8366 +#define WL_RM_TYPE_CCA 2
8367 +#define WL_RM_TYPE_RPI 3
8368 +
8369 +#define WL_RM_FLAG_PARALLEL (1<<0)
8370 +
8371 +#define WL_RM_FLAG_LATE (1<<1)
8372 +#define WL_RM_FLAG_INCAPABLE (1<<2)
8373 +#define WL_RM_FLAG_REFUSED (1<<3)
8374 +
8375 +typedef struct wl_rm_req_elt {
8376 + int8 type;
8377 + int8 flags;
8378 + uint16 chanspec;
8379 + uint32 token; /* token for this measurement */
8380 + uint32 tsf_h; /* TSF high 32-bits of Measurement start time */
8381 + uint32 tsf_l; /* TSF low 32-bits */
8382 + uint32 dur; /* TUs */
8383 +} wl_rm_req_elt_t;
8384 +
8385 +typedef struct wl_rm_req {
8386 + uint32 token; /* overall measurement set token */
8387 + uint32 count; /* number of measurement reqests */
8388 + wl_rm_req_elt_t req[1]; /* variable length block of requests */
8389 +} wl_rm_req_t;
8390 +#define WL_RM_REQ_FIXED_LEN 8
8391 +
8392 +typedef struct wl_rm_rep_elt {
8393 + int8 type;
8394 + int8 flags;
8395 + uint16 chanspec;
8396 + uint32 token; /* token for this measurement */
8397 + uint32 tsf_h; /* TSF high 32-bits of Measurement start time */
8398 + uint32 tsf_l; /* TSF low 32-bits */
8399 + uint32 dur; /* TUs */
8400 + uint32 len; /* byte length of data block */
8401 + uint8 data[1]; /* variable length data block */
8402 +} wl_rm_rep_elt_t;
8403 +#define WL_RM_REP_ELT_FIXED_LEN 24 /* length excluding data block */
8404 +
8405 +#define WL_RPI_REP_BIN_NUM 8
8406 +typedef struct wl_rm_rpi_rep {
8407 + uint8 rpi[WL_RPI_REP_BIN_NUM];
8408 + int8 rpi_max[WL_RPI_REP_BIN_NUM];
8409 +} wl_rm_rpi_rep_t;
8410 +
8411 +typedef struct wl_rm_rep {
8412 + uint32 token; /* overall measurement set token */
8413 + uint32 len; /* length of measurement report block */
8414 + wl_rm_rep_elt_t rep[1]; /* variable length block of reports */
8415 +} wl_rm_rep_t;
8416 +#define WL_RM_REP_FIXED_LEN 8
8417 +
8418 +
8419 +#if defined(BCMSUP_PSK)
8420 +typedef enum sup_auth_status {
8421 + WLC_SUP_DISCONNECTED = 0,
8422 + WLC_SUP_CONNECTING,
8423 + WLC_SUP_IDREQUIRED,
8424 + WLC_SUP_AUTHENTICATING,
8425 + WLC_SUP_AUTHENTICATED,
8426 + WLC_SUP_KEYXCHANGE,
8427 + WLC_SUP_KEYED
8428 +} sup_auth_status_t;
8429 +#endif /* BCMCCX | BCMSUP_PSK */
8430 +
8431 +/* Enumerate crypto algorithms */
8432 +#define CRYPTO_ALGO_OFF 0
8433 +#define CRYPTO_ALGO_WEP1 1
8434 +#define CRYPTO_ALGO_TKIP 2
8435 +#define CRYPTO_ALGO_WEP128 3
8436 +#define CRYPTO_ALGO_AES_CCM 4
8437 +#define CRYPTO_ALGO_AES_OCB_MSDU 5
8438 +#define CRYPTO_ALGO_AES_OCB_MPDU 6
8439 +#define CRYPTO_ALGO_NALG 7
8440 +
8441 +#define WSEC_GEN_MIC_ERROR 0x0001
8442 +#define WSEC_GEN_REPLAY 0x0002
8443 +
8444 +#define WL_SOFT_KEY (1 << 0) /* Indicates this key is using soft encrypt */
8445 +#define WL_PRIMARY_KEY (1 << 1) /* Indicates this key is the primary (ie tx) key */
8446 +#define WL_KF_RES_4 (1 << 4) /* Reserved for backward compat */
8447 +#define WL_KF_RES_5 (1 << 5) /* Reserved for backward compat */
8448 +
8449 +typedef struct wl_wsec_key {
8450 + uint32 index; /* key index */
8451 + uint32 len; /* key length */
8452 + uint8 data[DOT11_MAX_KEY_SIZE]; /* key data */
8453 + uint32 pad_1[18];
8454 + uint32 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
8455 + uint32 flags; /* misc flags */
8456 + uint32 pad_2[2];
8457 + int pad_3;
8458 + int iv_initialized; /* has IV been initialized already? */
8459 + int pad_4;
8460 + /* Rx IV */
8461 + struct {
8462 + uint32 hi; /* upper 32 bits of IV */
8463 + uint16 lo; /* lower 16 bits of IV */
8464 + } rxiv;
8465 + uint32 pad_5[2];
8466 + struct ether_addr ea; /* per station */
8467 +} wl_wsec_key_t;
8468 +
8469 +
8470 +#define WSEC_MIN_PSK_LEN 8
8471 +#define WSEC_MAX_PSK_LEN 64
8472 +
8473 +/* Flag for key material needing passhash'ing */
8474 +#define WSEC_PASSPHRASE (1<<0)
8475 +
8476 +/* recepticle for WLC_SET_WSEC_PMK parameter */
8477 +typedef struct {
8478 + ushort key_len; /* octets in key material */
8479 + ushort flags; /* key handling qualification */
8480 + uint8 key[WSEC_MAX_PSK_LEN]; /* PMK material */
8481 +} wsec_pmk_t;
8482 +
8483 +/* wireless security bitvec */
8484 +#define WEP_ENABLED 1
8485 +#define TKIP_ENABLED 2
8486 +#define AES_ENABLED 4
8487 +#define WSEC_SWFLAG 8
8488 +
8489 +/* WPA authentication mode bitvec */
8490 +#define WPA_AUTH_DISABLED 0x0000 /* Legacy (i.e., non-WPA) */
8491 +#define WPA_AUTH_NONE 0x0001 /* none (IBSS) */
8492 +#define WPA_AUTH_UNSPECIFIED 0x0002 /* over 802.1x */
8493 +#define WPA_AUTH_PSK 0x0004 /* Pre-shared key */
8494 +/*#define WPA_AUTH_8021X 0x0020*/ /* 802.1x, reserved */
8495 +#define WPA2_AUTH_UNSPECIFIED 0x0040 /* over 802.1x */
8496 +#define WPA2_AUTH_PSK 0x0080 /* Pre-shared key */
8497 +
8498 +typedef struct wl_led_info {
8499 + uint32 index; /* led index */
8500 + uint32 behavior;
8501 + bool activehi;
8502 +} wl_led_info_t;
8503 +
8504 +/*
8505 + * definitions for driver messages passed from WL to NAS.
8506 + */
8507 +/* Use this to recognize wpa and 802.1x driver messages. */
8508 +static const uint8 wl_wpa_snap_template[] =
8509 + { 0xaa, 0xaa, 0x03, 0x00, 0x90, 0x4c };
8510 +
8511 +#define WL_WPA_MSG_IFNAME_MAX 16
8512 +
8513 +/* WPA driver message */
8514 +typedef struct wl_wpa_header {
8515 + struct ether_header eth;
8516 + struct dot11_llc_snap_header snap;
8517 + uint8 version;
8518 + uint8 type;
8519 + /* version 2 additions */
8520 + char ifname[WL_WPA_MSG_IFNAME_MAX];
8521 + /* version specific data */
8522 + /* uint8 data[1]; */
8523 +} wl_wpa_header_t;
8524 +
8525 +#define WL_WPA_HEADER_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN + 2 + WL_WPA_MSG_IFNAME_MAX)
8526 +
8527 +/* WPA driver message ethertype - private between wlc and nas */
8528 +#define WL_WPA_ETHER_TYPE 0x9999
8529 +
8530 +/* WPA driver message current version */
8531 +#define WL_WPA_MSG_VERSION 2
8532 +
8533 +/* Type field values for the 802.2 driver messages for WPA. */
8534 +#define WLC_ASSOC_MSG 1
8535 +#define WLC_DISASSOC_MSG 2
8536 +#define WLC_PTK_MIC_MSG 3
8537 +#define WLC_GTK_MIC_MSG 4
8538 +
8539 +/* 802.1x driver message */
8540 +typedef struct wl_eapol_header {
8541 + struct ether_header eth;
8542 + struct dot11_llc_snap_header snap;
8543 + uint8 version;
8544 + uint8 reserved;
8545 + char ifname[WL_WPA_MSG_IFNAME_MAX];
8546 + /* version specific data */
8547 + /* uint8 802_1x_msg[1]; */
8548 +} wl_eapol_header_t;
8549 +
8550 +#define WL_EAPOL_HEADER_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN + 2 + WL_WPA_MSG_IFNAME_MAX)
8551 +
8552 +/* 802.1x driver message ethertype - private between wlc and nas */
8553 +#define WL_EAPOL_ETHER_TYPE 0x999A
8554 +
8555 +/* 802.1x driver message current version */
8556 +#define WL_EAPOL_MSG_VERSION 1
8557 +
8558 +#define WL_SECPVT_DATA_LEN (ETHER_HDR_LEN + 4 + WL_WPA_MSG_IFNAME_MAX)
8559 +
8560 +/* message header for the private data exchange between nas and wl*/
8561 +typedef struct wl_secpvt_data {
8562 + struct ether_header eth; /* use the Type field in the eth header with the private type*/
8563 + uint8 version;
8564 + uint8 sub_type;
8565 + uint16 data_len;
8566 + char ifname[WL_WPA_MSG_IFNAME_MAX];
8567 + /* version specific data */
8568 + /* uint8 802_1x_msg[1]; */
8569 +}wl_secpvt_data_t;
8570 +
8571 +
8572 +/* srom read/write struct passed through ioctl */
8573 +typedef struct {
8574 + uint byteoff; /* byte offset */
8575 + uint nbytes; /* number of bytes */
8576 + uint16 buf[1];
8577 +} srom_rw_t;
8578 +
8579 +/* R_REG and W_REG struct passed through ioctl */
8580 +typedef struct {
8581 + uint32 byteoff; /* byte offset of the field in d11regs_t */
8582 + uint32 val; /* read/write value of the field */
8583 + uint32 size; /* sizeof the field */
8584 +} rw_reg_t;
8585 +
8586 +/* Structure used by GET/SET_ATTEN ioctls */
8587 +typedef struct {
8588 + uint16 auto_ctrl; /* 1: Automatic control, 0: overriden */
8589 + uint16 bb; /* Baseband attenuation */
8590 + uint16 radio; /* Radio attenuation */
8591 + uint16 txctl1; /* Radio TX_CTL1 value */
8592 +} atten_t;
8593 +
8594 +/* Used to get specific STA parameters */
8595 +typedef struct {
8596 + uint32 val;
8597 + struct ether_addr ea;
8598 +} scb_val_t;
8599 +
8600 +/* Event data type */
8601 +typedef struct {
8602 + uint msg; /* Message (see below) */
8603 + struct ether_addr *addr; /* Station address (if applicable) */
8604 + uint status; /* Status code (see below) */
8605 + uint reason; /* Reason code (if applicable) */
8606 + uint auth_type; /* WLC_E_AUTH */
8607 + bool link; /* WLC_E_LINK */
8608 + bool group; /* WLC_E_MIC_ERROR */
8609 + bool flush_txq; /* WLC_E_MIC_ERROR */
8610 +} wlc_event_t;
8611 +
8612 +typedef struct {
8613 + uint16 ver; /* version of this struct */
8614 + uint16 len; /* length in bytes of this structure */
8615 + uint16 cap; /* sta's advertized capabilities */
8616 + uint32 flags; /* flags defined below */
8617 + uint32 idle; /* time since data pkt rx'd from sta */
8618 + struct ether_addr ea; /* Station address */
8619 + wl_rateset_t rateset; /* rateset in use */
8620 + uint32 in; /* seconds elapsed since associated */
8621 + uint32 listen_interval_inms; /* Min Listen interval in ms for this STA*/
8622 +} sta_info_t;
8623 +
8624 +#define WL_STA_VER 2
8625 +
8626 +/* flags fields */
8627 +#define WL_STA_BRCM 0x01
8628 +#define WL_STA_WME 0x02
8629 +#define WL_STA_ABCAP 0x04
8630 +#define WL_STA_AUTHE 0x08
8631 +#define WL_STA_ASSOC 0x10
8632 +#define WL_STA_AUTHO 0x20
8633 +#define WL_STA_WDS 0x40
8634 +#define WL_WDS_LINKUP 0x80
8635 +
8636 +/* Event messages */
8637 +#define WLC_E_SET_SSID 1
8638 +#define WLC_E_JOIN 2
8639 +#define WLC_E_START 3
8640 +#define WLC_E_AUTH 4
8641 +#define WLC_E_AUTH_IND 5
8642 +#define WLC_E_DEAUTH 6
8643 +#define WLC_E_DEAUTH_IND 7
8644 +#define WLC_E_ASSOC 8
8645 +#define WLC_E_ASSOC_IND 9
8646 +#define WLC_E_REASSOC 10
8647 +#define WLC_E_REASSOC_IND 11
8648 +#define WLC_E_DISASSOC 12
8649 +#define WLC_E_DISASSOC_IND 13
8650 +#define WLC_E_QUIET_START 14 /* 802.11h Quiet period started */
8651 +#define WLC_E_QUIET_END 15 /* 802.11h Quiet period ended */
8652 +#define WLC_E_GOT_BEACONS 16
8653 +#define WLC_E_LINK 17 /* Link indication */
8654 +#define WLC_E_MIC_ERROR 18 /* TKIP MIC error occurred */
8655 +#define WLC_E_NDIS_LINK 19 /* NDIS style link indication */
8656 +#define WLC_E_ROAM 20
8657 +#define WLC_E_TXFAIL 21 /* dot11FailedCount (txfail) */
8658 +#define WLC_E_LAST 22
8659 +
8660 +/* Event status codes */
8661 +#define WLC_E_STATUS_SUCCESS 0
8662 +#define WLC_E_STATUS_FAIL 1
8663 +#define WLC_E_STATUS_TIMEOUT 2
8664 +#define WLC_E_STATUS_NO_NETWORKS 3
8665 +#define WLC_E_STATUS_ABORT 4
8666 +
8667 +typedef struct wlc_event_cb {
8668 + uint msg; /* Event message or 0 for all */
8669 + void (*fn)(void *, wlc_event_t *); /* Callback function */
8670 + void *context; /* Passed to callback function */
8671 + struct wlc_event_cb *next; /* Next in the chain */
8672 +} wlc_event_cb_t;
8673 +
8674 +/*
8675 + * Country locale determines which channels are available to us.
8676 + */
8677 +typedef enum _wlc_locale {
8678 + WLC_WW = 0, /* Worldwide */
8679 + WLC_THA, /* Thailand */
8680 + WLC_ISR, /* Israel */
8681 + WLC_JDN, /* Jordan */
8682 + WLC_PRC, /* China */
8683 + WLC_JPN, /* Japan */
8684 + WLC_FCC, /* USA */
8685 + WLC_EUR, /* Europe */
8686 + WLC_USL, /* US Low Band only */
8687 + WLC_JPH, /* Japan High Band only */
8688 + WLC_ALL, /* All the channels in this band */
8689 + WLC_11D, /* Represents locale recieved by 11d beacons */
8690 + WLC_LAST_LOCALE,
8691 + WLC_UNDEFINED_LOCALE = 0xf
8692 +} wlc_locale_t;
8693 +
8694 +/* channel encoding */
8695 +typedef struct channel_info {
8696 + int hw_channel;
8697 + int target_channel;
8698 + int scan_channel;
8699 +} channel_info_t;
8700 +
8701 +/* For ioctls that take a list of MAC addresses */
8702 +struct maclist {
8703 + uint count; /* number of MAC addresses */
8704 + struct ether_addr ea[1]; /* variable length array of MAC addresses */
8705 +};
8706 +
8707 +/* get pkt count struct passed through ioctl */
8708 +typedef struct get_pktcnt {
8709 + uint rx_good_pkt;
8710 + uint rx_bad_pkt;
8711 + uint tx_good_pkt;
8712 + uint tx_bad_pkt;
8713 +} get_pktcnt_t;
8714 +
8715 +/* Linux network driver ioctl encoding */
8716 +typedef struct wl_ioctl {
8717 + uint cmd; /* common ioctl definition */
8718 + void *buf; /* pointer to user buffer */
8719 + uint len; /* length of user buffer */
8720 + bool set; /* get or set request (optional) */
8721 + uint used; /* bytes read or written (optional) */
8722 + uint needed; /* bytes needed (optional) */
8723 +} wl_ioctl_t;
8724 +
8725 +/*
8726 + * Structure for passing hardware and software
8727 + * revision info up from the driver.
8728 + */
8729 +typedef struct wlc_rev_info {
8730 + uint vendorid; /* PCI vendor id */
8731 + uint deviceid; /* device id of chip */
8732 + uint radiorev; /* radio revision */
8733 + uint chiprev; /* chip revision */
8734 + uint corerev; /* core revision */
8735 + uint boardid; /* board identifier (usu. PCI sub-device id) */
8736 + uint boardvendor; /* board vendor (usu. PCI sub-vendor id) */
8737 + uint boardrev; /* board revision */
8738 + uint driverrev; /* driver version */
8739 + uint ucoderev; /* microcode version */
8740 + uint bus; /* bus type */
8741 + uint chipnum; /* chip number */
8742 +} wlc_rev_info_t;
8743 +
8744 +/* check this magic number */
8745 +#define WLC_IOCTL_MAGIC 0x14e46c77
8746 +
8747 +/* bump this number if you change the ioctl interface */
8748 +#define WLC_IOCTL_VERSION 1
8749 +
8750 +#define WLC_IOCTL_MAXLEN 8192 /* max length ioctl buffer required */
8751 +#define WLC_IOCTL_SMLEN 256 /* "small" length ioctl buffer required */
8752 +
8753 +/* common ioctl definitions */
8754 +#define WLC_GET_MAGIC 0
8755 +#define WLC_GET_VERSION 1
8756 +#define WLC_UP 2
8757 +#define WLC_DOWN 3
8758 +#define WLC_DUMP 6
8759 +#define WLC_GET_MSGLEVEL 7
8760 +#define WLC_SET_MSGLEVEL 8
8761 +#define WLC_GET_PROMISC 9
8762 +#define WLC_SET_PROMISC 10
8763 +#define WLC_GET_RATE 12
8764 +#define WLC_SET_RATE 13
8765 +#define WLC_GET_INSTANCE 14
8766 +#define WLC_GET_FRAG 15
8767 +#define WLC_SET_FRAG 16
8768 +#define WLC_GET_RTS 17
8769 +#define WLC_SET_RTS 18
8770 +#define WLC_GET_INFRA 19
8771 +#define WLC_SET_INFRA 20
8772 +#define WLC_GET_AUTH 21
8773 +#define WLC_SET_AUTH 22
8774 +#define WLC_GET_BSSID 23
8775 +#define WLC_SET_BSSID 24
8776 +#define WLC_GET_SSID 25
8777 +#define WLC_SET_SSID 26
8778 +#define WLC_RESTART 27
8779 +#define WLC_GET_CHANNEL 29
8780 +#define WLC_SET_CHANNEL 30
8781 +#define WLC_GET_SRL 31
8782 +#define WLC_SET_SRL 32
8783 +#define WLC_GET_LRL 33
8784 +#define WLC_SET_LRL 34
8785 +#define WLC_GET_PLCPHDR 35
8786 +#define WLC_SET_PLCPHDR 36
8787 +#define WLC_GET_RADIO 37
8788 +#define WLC_SET_RADIO 38
8789 +#define WLC_GET_PHYTYPE 39
8790 +#define WLC_GET_WEP 42
8791 +#define WLC_SET_WEP 43
8792 +#define WLC_GET_KEY 44
8793 +#define WLC_SET_KEY 45
8794 +#define WLC_SCAN 50
8795 +#define WLC_SCAN_RESULTS 51
8796 +#define WLC_DISASSOC 52
8797 +#define WLC_REASSOC 53
8798 +#define WLC_GET_ROAM_TRIGGER 54
8799 +#define WLC_SET_ROAM_TRIGGER 55
8800 +#define WLC_GET_TXANT 61
8801 +#define WLC_SET_TXANT 62
8802 +#define WLC_GET_ANTDIV 63
8803 +#define WLC_SET_ANTDIV 64
8804 +#define WLC_GET_TXPWR 65
8805 +#define WLC_SET_TXPWR 66
8806 +#define WLC_GET_CLOSED 67
8807 +#define WLC_SET_CLOSED 68
8808 +#define WLC_GET_MACLIST 69
8809 +#define WLC_SET_MACLIST 70
8810 +#define WLC_GET_RATESET 71
8811 +#define WLC_SET_RATESET 72
8812 +#define WLC_GET_LOCALE 73
8813 +#define WLC_SET_LOCALE 74
8814 +#define WLC_GET_BCNPRD 75
8815 +#define WLC_SET_BCNPRD 76
8816 +#define WLC_GET_DTIMPRD 77
8817 +#define WLC_SET_DTIMPRD 78
8818 +#define WLC_GET_SROM 79
8819 +#define WLC_SET_SROM 80
8820 +#define WLC_GET_WEP_RESTRICT 81
8821 +#define WLC_SET_WEP_RESTRICT 82
8822 +#define WLC_GET_COUNTRY 83
8823 +#define WLC_SET_COUNTRY 84
8824 +#define WLC_GET_REVINFO 98
8825 +#define WLC_GET_MACMODE 105
8826 +#define WLC_SET_MACMODE 106
8827 +#define WLC_GET_GMODE 109
8828 +#define WLC_SET_GMODE 110
8829 +#define WLC_GET_CURR_RATESET 114 /* current rateset */
8830 +#define WLC_GET_SCANSUPPRESS 115
8831 +#define WLC_SET_SCANSUPPRESS 116
8832 +#define WLC_GET_AP 117
8833 +#define WLC_SET_AP 118
8834 +#define WLC_GET_EAP_RESTRICT 119
8835 +#define WLC_SET_EAP_RESTRICT 120
8836 +#define WLC_GET_WDSLIST 123
8837 +#define WLC_SET_WDSLIST 124
8838 +#define WLC_GET_RSSI 127
8839 +#define WLC_GET_WSEC 133
8840 +#define WLC_SET_WSEC 134
8841 +#define WLC_GET_BSS_INFO 136
8842 +#define WLC_GET_LAZYWDS 138
8843 +#define WLC_SET_LAZYWDS 139
8844 +#define WLC_GET_BANDLIST 140
8845 +#define WLC_GET_BAND 141
8846 +#define WLC_SET_BAND 142
8847 +#define WLC_GET_SHORTSLOT 144
8848 +#define WLC_GET_SHORTSLOT_OVERRIDE 145
8849 +#define WLC_SET_SHORTSLOT_OVERRIDE 146
8850 +#define WLC_GET_SHORTSLOT_RESTRICT 147
8851 +#define WLC_SET_SHORTSLOT_RESTRICT 148
8852 +#define WLC_GET_GMODE_PROTECTION 149
8853 +#define WLC_GET_GMODE_PROTECTION_OVERRIDE 150
8854 +#define WLC_SET_GMODE_PROTECTION_OVERRIDE 151
8855 +#define WLC_UPGRADE 152
8856 +#define WLC_GET_MRATE 153
8857 +#define WLC_SET_MRATE 154
8858 +#define WLC_GET_ASSOCLIST 159
8859 +#define WLC_GET_CLK 160
8860 +#define WLC_SET_CLK 161
8861 +#define WLC_GET_UP 162
8862 +#define WLC_OUT 163
8863 +#define WLC_GET_WPA_AUTH 164
8864 +#define WLC_SET_WPA_AUTH 165
8865 +#define WLC_GET_GMODE_PROTECTION_CONTROL 178
8866 +#define WLC_SET_GMODE_PROTECTION_CONTROL 179
8867 +#define WLC_GET_PHYLIST 180
8868 +#define WLC_GET_KEY_SEQ 183
8869 +#define WLC_GET_GMODE_PROTECTION_CTS 198
8870 +#define WLC_SET_GMODE_PROTECTION_CTS 199
8871 +#define WLC_GET_PIOMODE 203
8872 +#define WLC_SET_PIOMODE 204
8873 +#define WLC_SET_LED 209
8874 +#define WLC_GET_LED 210
8875 +#define WLC_GET_CHANNEL_SEL 215
8876 +#define WLC_START_CHANNEL_SEL 216
8877 +#define WLC_GET_VALID_CHANNELS 217
8878 +#define WLC_GET_FAKEFRAG 218
8879 +#define WLC_SET_FAKEFRAG 219
8880 +#define WLC_GET_WET 230
8881 +#define WLC_SET_WET 231
8882 +#define WLC_GET_KEY_PRIMARY 235
8883 +#define WLC_SET_KEY_PRIMARY 236
8884 +#define WLC_WDS_GET_REMOTE_HWADDR 246 /* currently handled in wl_linux.c/wl_vx.c */
8885 +#define WLC_SET_CS_SCAN_TIMER 248
8886 +#define WLC_GET_CS_SCAN_TIMER 249
8887 +#define WLC_CURRENT_PWR 256
8888 +#define WLC_GET_CHANNELS_IN_COUNTRY 260
8889 +#define WLC_GET_COUNTRY_LIST 261
8890 +#define WLC_GET_VAR 262 /* get value of named variable */
8891 +#define WLC_SET_VAR 263 /* set named variable to value */
8892 +#define WLC_NVRAM_GET 264
8893 +#define WLC_NVRAM_SET 265
8894 +#define WLC_SET_WSEC_PMK 268
8895 +#define WLC_GET_AUTH_MODE 269
8896 +#define WLC_SET_AUTH_MODE 270
8897 +#define WLC_LAST 273 /* do not change - use get_var/set_var */
8898 +
8899 +/*
8900 + * Minor kludge alert:
8901 + * Duplicate a few definitions that irelay requires from epiioctl.h here
8902 + * so caller doesn't have to include this file and epiioctl.h .
8903 + * If this grows any more, it would be time to move these irelay-specific
8904 + * definitions out of the epiioctl.h and into a separate driver common file.
8905 + */
8906 +#ifndef EPICTRL_COOKIE
8907 +#define EPICTRL_COOKIE 0xABADCEDE
8908 +#endif
8909 +
8910 +/* vx wlc ioctl's offset */
8911 +#define CMN_IOCTL_OFF 0x180
8912 +
8913 +/*
8914 + * custom OID support
8915 + *
8916 + * 0xFF - implementation specific OID
8917 + * 0xE4 - first byte of Broadcom PCI vendor ID
8918 + * 0x14 - second byte of Broadcom PCI vendor ID
8919 + * 0xXX - the custom OID number
8920 + */
8921 +
8922 +/* begin 0x1f values beyond the start of the ET driver range. */
8923 +#define WL_OID_BASE 0xFFE41420
8924 +
8925 +/* NDIS overrides */
8926 +#define OID_WL_GETINSTANCE (WL_OID_BASE + WLC_GET_INSTANCE)
8927 +
8928 +#define WL_DECRYPT_STATUS_SUCCESS 1
8929 +#define WL_DECRYPT_STATUS_FAILURE 2
8930 +#define WL_DECRYPT_STATUS_UNKNOWN 3
8931 +
8932 +/* allows user-mode app to poll the status of USB image upgrade */
8933 +#define WLC_UPGRADE_SUCCESS 0
8934 +#define WLC_UPGRADE_PENDING 1
8935 +
8936 +/* Bit masks for radio disabled status - returned by WL_GET_RADIO */
8937 +#define WL_RADIO_SW_DISABLE (1<<0)
8938 +#define WL_RADIO_HW_DISABLE (1<<1)
8939 +#define WL_RADIO_UNASSOC_DISABLE (1<<2)
8940 +
8941 +/* Override bit for WLC_SET_TXPWR. if set, ignore other level limits */
8942 +#define WL_TXPWR_OVERRIDE (1<<31)
8943 +
8944 +
8945 +/* Bus types */
8946 +#define WL_SB_BUS 0 /* Silicon Backplane */
8947 +#define WL_PCI_BUS 1 /* PCI target */
8948 +#define WL_PCMCIA_BUS 2 /* PCMCIA target */
8949 +
8950 +/* band types */
8951 +#define WLC_BAND_AUTO 0 /* auto-select */
8952 +#define WLC_BAND_A 1 /* "a" band (5 Ghz) */
8953 +#define WLC_BAND_B 2 /* "b" band (2.4 Ghz) */
8954 +
8955 +/* MAC list modes */
8956 +#define WLC_MACMODE_DISABLED 0 /* MAC list disabled */
8957 +#define WLC_MACMODE_DENY 1 /* Deny specified (i.e. allow unspecified) */
8958 +#define WLC_MACMODE_ALLOW 2 /* Allow specified (i.e. deny unspecified) */
8959 +
8960 +/*
8961 + *
8962 + */
8963 +#define GMODE_LEGACY_B 0
8964 +#define GMODE_AUTO 1
8965 +#define GMODE_ONLY 2
8966 +#define GMODE_B_DEFERRED 3
8967 +#define GMODE_PERFORMANCE 4
8968 +#define GMODE_LRS 5
8969 +#define GMODE_MAX 6
8970 +
8971 +/* values for PLCPHdr_override */
8972 +#define WLC_PLCP_AUTO -1
8973 +#define WLC_PLCP_SHORT 0
8974 +#define WLC_PLCP_LONG 1
8975 +
8976 +/* values for g_protection_override */
8977 +#define WLC_G_PROTECTION_AUTO -1
8978 +#define WLC_G_PROTECTION_OFF 0
8979 +#define WLC_G_PROTECTION_ON 1
8980 +
8981 +/* values for g_protection_control */
8982 +#define WLC_G_PROTECTION_CTL_OFF 0
8983 +#define WLC_G_PROTECTION_CTL_LOCAL 1
8984 +#define WLC_G_PROTECTION_CTL_OVERLAP 2
8985 +
8986 +/* Values for PM */
8987 +#define PM_OFF 0
8988 +#define PM_MAX 1
8989 +#define PM_FAST 2
8990 +
8991 +
8992 +
8993 +
8994 +
8995 +/* 802.11h enforcement levels */
8996 +#define SPECT_MNGMT_OFF 0 /* 11h disabled */
8997 +#define SPECT_MNGMT_LOOSE 1 /* qllow scan lists to contain non-11h AP */
8998 +#define SPECT_MNGMT_STRICT 2 /* prune out non-11h APs from scan list */
8999 +
9000 +
9001 +#define WL_CHAN_VALID_HW (1 << 0) /* valid with current HW */
9002 +#define WL_CHAN_VALID_SW (1 << 1) /* valid with current country setting */
9003 +#define WL_CHAN_BAND_A (1 << 2) /* A-band channel */
9004 +#define WL_CHAN_RADAR (1 << 3) /* radar sensitive channel */
9005 +#define WL_CHAN_INACTIVE (1 << 4) /* temporarily out of service due to radar */
9006 +#define WL_CHAN_RADAR_PASSIVE (1 << 5) /* radar channel is in passive mode */
9007 +
9008 +
9009 +/* max # of leds supported by GPIO (gpio pin# == led index#) */
9010 +#define WL_LED_NUMGPIO 16 /* gpio 0-15 */
9011 +
9012 +/* led per-pin behaviors */
9013 +#define WL_LED_OFF 0 /* always off */
9014 +#define WL_LED_ON 1 /* always on */
9015 +#define WL_LED_ACTIVITY 2 /* activity */
9016 +#define WL_LED_RADIO 3 /* radio enabled */
9017 +#define WL_LED_ARADIO 4 /* 5 Ghz radio enabled */
9018 +#define WL_LED_BRADIO 5 /* 2.4Ghz radio enabled */
9019 +#define WL_LED_BGMODE 6 /* on if gmode, off if bmode */
9020 +#define WL_LED_WI1 7
9021 +#define WL_LED_WI2 8
9022 +#define WL_LED_WI3 9
9023 +#define WL_LED_ASSOC 10 /* associated state indicator */
9024 +#define WL_LED_INACTIVE 11 /* null behavior (clears default behavior) */
9025 +#define WL_LED_NUMBEHAVIOR 12
9026 +
9027 +/* led behavior numeric value format */
9028 +#define WL_LED_BEH_MASK 0x7f /* behavior mask */
9029 +#define WL_LED_AL_MASK 0x80 /* activelow (polarity) bit */
9030 +
9031 +
9032 +/* WDS link local endpoint WPA role */
9033 +#define WL_WDS_WPA_ROLE_AUTH 0 /* authenticator */
9034 +#define WL_WDS_WPA_ROLE_SUP 1 /* supplicant */
9035 +#define WL_WDS_WPA_ROLE_AUTO 255 /* auto, based on mac addr value */
9036 +
9037 +/* Structures and constants used for "vndr_ie" IOVar interface */
9038 +#define VNDR_IE_CMD_LEN 4 /* length of the set command string: "add", "del" (+ NULL) */
9039 +
9040 +/* 802.11 Mgmt Packet flags */
9041 +#define VNDR_IE_BEACON_FLAG 0x1
9042 +#define VNDR_IE_PRBRSP_FLAG 0x2
9043 +#define VNDR_IE_ASSOCRSP_FLAG 0x4
9044 +#define VNDR_IE_AUTHRSP_FLAG 0x8
9045 +
9046 +typedef struct vndr_ie_info {
9047 + uint32 pktflag; /* bitmask indicating which packet(s) contain this IE */
9048 + vndr_ie_t vndr_ie_data; /* vendor IE data */
9049 +} vndr_ie_info_t;
9050 +
9051 +typedef struct vndr_ie_buf {
9052 + int iecount; /* number of entries in the vndr_ie_list[] array */
9053 + vndr_ie_info_t vndr_ie_list[1]; /* variable size list of vndr_ie_info_t structs */
9054 +} vndr_ie_buf_t;
9055 +
9056 +typedef struct vndr_ie_setbuf {
9057 + char cmd[VNDR_IE_CMD_LEN]; /* vndr_ie IOVar set command : "add", "del" + NULL */
9058 + vndr_ie_buf_t vndr_ie_buffer; /* buffer containing Vendor IE list information */
9059 +} vndr_ie_setbuf_t;
9060 +
9061 +#if !defined(__GNUC__)
9062 +#pragma pack(pop)
9063 +#endif
9064 +
9065 +#endif /* _wlioctl_h_ */
9066 diff -Nur linux-2.4.30/arch/mips/bcm947xx/Makefile linux-2.4.30-brcm/arch/mips/bcm947xx/Makefile
9067 --- linux-2.4.30/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
9068 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/Makefile 2005-05-26 15:07:37.000000000 +0200
9069 @@ -0,0 +1,15 @@
9070 +#
9071 +# Makefile for the BCM947xx specific kernel interface routines
9072 +# under Linux.
9073 +#
9074 +
9075 +EXTRA_CFLAGS+=-I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
9076 +
9077 +O_TARGET := bcm947xx.o
9078 +
9079 +export-objs := nvram_linux.o setup.o
9080 +obj-y := prom.o setup.o time.o sbmips.o gpio.o
9081 +obj-y += nvram.o nvram_linux.o
9082 +obj-$(CONFIG_PCI) += sbpci.o pcibios.o
9083 +
9084 +include $(TOPDIR)/Rules.make
9085 diff -Nur linux-2.4.30/arch/mips/bcm947xx/nvram.c linux-2.4.30-brcm/arch/mips/bcm947xx/nvram.c
9086 --- linux-2.4.30/arch/mips/bcm947xx/nvram.c 1970-01-01 01:00:00.000000000 +0100
9087 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/nvram.c 2005-05-24 17:58:29.000000000 +0200
9088 @@ -0,0 +1,321 @@
9089 +/*
9090 + * NVRAM variable manipulation (common)
9091 + *
9092 + * Copyright 2004, Broadcom Corporation
9093 + * All Rights Reserved.
9094 + *
9095 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9096 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9097 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9098 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9099 + *
9100 + * $Id$
9101 + */
9102 +
9103 +#include <typedefs.h>
9104 +#include <osl.h>
9105 +#include <bcmendian.h>
9106 +#include <bcmnvram.h>
9107 +#include <bcmutils.h>
9108 +#include <sbsdram.h>
9109 +
9110 +extern struct nvram_tuple * BCMINIT(_nvram_realloc)(struct nvram_tuple *t, const char *name, const char *value);
9111 +extern void BCMINIT(_nvram_free)(struct nvram_tuple *t);
9112 +extern int BCMINIT(_nvram_read)(void *buf);
9113 +
9114 +char * BCMINIT(_nvram_get)(const char *name);
9115 +int BCMINIT(_nvram_set)(const char *name, const char *value);
9116 +int BCMINIT(_nvram_unset)(const char *name);
9117 +int BCMINIT(_nvram_getall)(char *buf, int count);
9118 +int BCMINIT(_nvram_commit)(struct nvram_header *header);
9119 +int BCMINIT(_nvram_init)(void);
9120 +void BCMINIT(_nvram_exit)(void);
9121 +
9122 +static struct nvram_tuple * BCMINITDATA(nvram_hash)[257];
9123 +static struct nvram_tuple * nvram_dead;
9124 +
9125 +/* Free all tuples. Should be locked. */
9126 +static void
9127 +BCMINITFN(nvram_free)(void)
9128 +{
9129 + uint i;
9130 + struct nvram_tuple *t, *next;
9131 +
9132 + /* Free hash table */
9133 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
9134 + for (t = BCMINIT(nvram_hash)[i]; t; t = next) {
9135 + next = t->next;
9136 + BCMINIT(_nvram_free)(t);
9137 + }
9138 + BCMINIT(nvram_hash)[i] = NULL;
9139 + }
9140 +
9141 + /* Free dead table */
9142 + for (t = nvram_dead; t; t = next) {
9143 + next = t->next;
9144 + BCMINIT(_nvram_free)(t);
9145 + }
9146 + nvram_dead = NULL;
9147 +
9148 + /* Indicate to per-port code that all tuples have been freed */
9149 + BCMINIT(_nvram_free)(NULL);
9150 +}
9151 +
9152 +/* String hash */
9153 +static INLINE uint
9154 +hash(const char *s)
9155 +{
9156 + uint hash = 0;
9157 +
9158 + while (*s)
9159 + hash = 31 * hash + *s++;
9160 +
9161 + return hash;
9162 +}
9163 +
9164 +/* (Re)initialize the hash table. Should be locked. */
9165 +static int
9166 +BCMINITFN(nvram_rehash)(struct nvram_header *header)
9167 +{
9168 + char buf[] = "0xXXXXXXXX", *name, *value, *end, *eq;
9169 +
9170 + /* (Re)initialize hash table */
9171 + BCMINIT(nvram_free)();
9172 +
9173 + /* Parse and set "name=value\0 ... \0\0" */
9174 + name = (char *) &header[1];
9175 + end = (char *) header + NVRAM_SPACE - 2;
9176 + end[0] = end[1] = '\0';
9177 + for (; *name; name = value + strlen(value) + 1) {
9178 + if (!(eq = strchr(name, '=')))
9179 + break;
9180 + *eq = '\0';
9181 + value = eq + 1;
9182 + BCMINIT(_nvram_set)(name, value);
9183 + *eq = '=';
9184 + }
9185 +
9186 + /* Set special SDRAM parameters */
9187 + if (!BCMINIT(_nvram_get)("sdram_init")) {
9188 + sprintf(buf, "0x%04X", (uint16)(header->crc_ver_init >> 16));
9189 + BCMINIT(_nvram_set)("sdram_init", buf);
9190 + }
9191 + if (!BCMINIT(_nvram_get)("sdram_config")) {
9192 + sprintf(buf, "0x%04X", (uint16)(header->config_refresh & 0xffff));
9193 + BCMINIT(_nvram_set)("sdram_config", buf);
9194 + }
9195 + if (!BCMINIT(_nvram_get)("sdram_refresh")) {
9196 + sprintf(buf, "0x%04X", (uint16)((header->config_refresh >> 16) & 0xffff));
9197 + BCMINIT(_nvram_set)("sdram_refresh", buf);
9198 + }
9199 + if (!BCMINIT(_nvram_get)("sdram_ncdl")) {
9200 + sprintf(buf, "0x%08X", header->config_ncdl);
9201 + BCMINIT(_nvram_set)("sdram_ncdl", buf);
9202 + }
9203 +
9204 + return 0;
9205 +}
9206 +
9207 +/* Get the value of an NVRAM variable. Should be locked. */
9208 +char *
9209 +BCMINITFN(_nvram_get)(const char *name)
9210 +{
9211 + uint i;
9212 + struct nvram_tuple *t;
9213 + char *value;
9214 +
9215 + if (!name)
9216 + return NULL;
9217 +
9218 + /* Hash the name */
9219 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
9220 +
9221 + /* Find the associated tuple in the hash table */
9222 + for (t = BCMINIT(nvram_hash)[i]; t && strcmp(t->name, name); t = t->next);
9223 +
9224 + value = t ? t->value : NULL;
9225 +
9226 + return value;
9227 +}
9228 +
9229 +/* Get the value of an NVRAM variable. Should be locked. */
9230 +int
9231 +BCMINITFN(_nvram_set)(const char *name, const char *value)
9232 +{
9233 + uint i;
9234 + struct nvram_tuple *t, *u, **prev;
9235 +
9236 + /* Hash the name */
9237 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
9238 +
9239 + /* Find the associated tuple in the hash table */
9240 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
9241 +
9242 + /* (Re)allocate tuple */
9243 + if (!(u = BCMINIT(_nvram_realloc)(t, name, value)))
9244 + return -12; /* -ENOMEM */
9245 +
9246 + /* Value reallocated */
9247 + if (t && t == u)
9248 + return 0;
9249 +
9250 + /* Move old tuple to the dead table */
9251 + if (t) {
9252 + *prev = t->next;
9253 + t->next = nvram_dead;
9254 + nvram_dead = t;
9255 + }
9256 +
9257 + /* Add new tuple to the hash table */
9258 + u->next = BCMINIT(nvram_hash)[i];
9259 + BCMINIT(nvram_hash)[i] = u;
9260 +
9261 + return 0;
9262 +}
9263 +
9264 +/* Unset the value of an NVRAM variable. Should be locked. */
9265 +int
9266 +BCMINITFN(_nvram_unset)(const char *name)
9267 +{
9268 + uint i;
9269 + struct nvram_tuple *t, **prev;
9270 +
9271 + if (!name)
9272 + return 0;
9273 +
9274 + /* Hash the name */
9275 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
9276 +
9277 + /* Find the associated tuple in the hash table */
9278 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
9279 +
9280 + /* Move it to the dead table */
9281 + if (t) {
9282 + *prev = t->next;
9283 + t->next = nvram_dead;
9284 + nvram_dead = t;
9285 + }
9286 +
9287 + return 0;
9288 +}
9289 +
9290 +/* Get all NVRAM variables. Should be locked. */
9291 +int
9292 +BCMINITFN(_nvram_getall)(char *buf, int count)
9293 +{
9294 + uint i;
9295 + struct nvram_tuple *t;
9296 + int len = 0;
9297 +
9298 + bzero(buf, count);
9299 +
9300 + /* Write name=value\0 ... \0\0 */
9301 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
9302 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
9303 + if ((count - len) > (strlen(t->name) + 1 + strlen(t->value) + 1))
9304 + len += sprintf(buf + len, "%s=%s", t->name, t->value) + 1;
9305 + else
9306 + break;
9307 + }
9308 + }
9309 +
9310 + return 0;
9311 +}
9312 +
9313 +/* Regenerate NVRAM. Should be locked. */
9314 +int
9315 +BCMINITFN(_nvram_commit)(struct nvram_header *header)
9316 +{
9317 + char *init, *config, *refresh, *ncdl;
9318 + char *ptr, *end;
9319 + int i;
9320 + struct nvram_tuple *t;
9321 + struct nvram_header tmp;
9322 + uint8 crc;
9323 +
9324 + /* Regenerate header */
9325 + header->magic = NVRAM_MAGIC;
9326 + header->crc_ver_init = (NVRAM_VERSION << 8);
9327 + if (!(init = BCMINIT(_nvram_get)("sdram_init")) ||
9328 + !(config = BCMINIT(_nvram_get)("sdram_config")) ||
9329 + !(refresh = BCMINIT(_nvram_get)("sdram_refresh")) ||
9330 + !(ncdl = BCMINIT(_nvram_get)("sdram_ncdl"))) {
9331 + header->crc_ver_init |= SDRAM_INIT << 16;
9332 + header->config_refresh = SDRAM_CONFIG;
9333 + header->config_refresh |= SDRAM_REFRESH << 16;
9334 + header->config_ncdl = 0;
9335 + } else {
9336 + header->crc_ver_init |= (bcm_strtoul(init, NULL, 0) & 0xffff) << 16;
9337 + header->config_refresh = bcm_strtoul(config, NULL, 0) & 0xffff;
9338 + header->config_refresh |= (bcm_strtoul(refresh, NULL, 0) & 0xffff) << 16;
9339 + header->config_ncdl = bcm_strtoul(ncdl, NULL, 0);
9340 + }
9341 +
9342 + /* Clear data area */
9343 + ptr = (char *) header + sizeof(struct nvram_header);
9344 + bzero(ptr, NVRAM_SPACE - sizeof(struct nvram_header));
9345 +
9346 + /* Leave space for a double NUL at the end */
9347 + end = (char *) header + NVRAM_SPACE - 2;
9348 +
9349 + /* Write out all tuples */
9350 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
9351 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
9352 + if ((ptr + strlen(t->name) + 1 + strlen(t->value) + 1) > end)
9353 + break;
9354 + ptr += sprintf(ptr, "%s=%s", t->name, t->value) + 1;
9355 + }
9356 + }
9357 +
9358 + /* End with a double NUL */
9359 + ptr += 2;
9360 +
9361 + /* Set new length */
9362 + header->len = ROUNDUP(ptr - (char *) header, 4);
9363 +
9364 + /* Little-endian CRC8 over the last 11 bytes of the header */
9365 + tmp.crc_ver_init = htol32(header->crc_ver_init);
9366 + tmp.config_refresh = htol32(header->config_refresh);
9367 + tmp.config_ncdl = htol32(header->config_ncdl);
9368 + crc = hndcrc8((char *) &tmp + 9, sizeof(struct nvram_header) - 9, CRC8_INIT_VALUE);
9369 +
9370 + /* Continue CRC8 over data bytes */
9371 + crc = hndcrc8((char *) &header[1], header->len - sizeof(struct nvram_header), crc);
9372 +
9373 + /* Set new CRC8 */
9374 + header->crc_ver_init |= crc;
9375 +
9376 + /* Reinitialize hash table */
9377 + return BCMINIT(nvram_rehash)(header);
9378 +}
9379 +
9380 +/* Initialize hash table. Should be locked. */
9381 +int
9382 +BCMINITFN(_nvram_init)(void)
9383 +{
9384 + struct nvram_header *header;
9385 + int ret;
9386 + void *osh;
9387 +
9388 + /* get kernel osl handler */
9389 + osh = osl_attach(NULL);
9390 +
9391 + if (!(header = (struct nvram_header *) MALLOC(osh, NVRAM_SPACE))) {
9392 + printf("nvram_init: out of memory, malloced %d bytes\n", MALLOCED(osh));
9393 + return -12; /* -ENOMEM */
9394 + }
9395 +
9396 + if ((ret = BCMINIT(_nvram_read)(header)) == 0 &&
9397 + header->magic == NVRAM_MAGIC)
9398 + BCMINIT(nvram_rehash)(header);
9399 +
9400 + MFREE(osh, header, NVRAM_SPACE);
9401 + return ret;
9402 +}
9403 +
9404 +/* Free hash table. Should be locked. */
9405 +void
9406 +BCMINITFN(_nvram_exit)(void)
9407 +{
9408 + BCMINIT(nvram_free)();
9409 +}
9410 diff -Nur linux-2.4.30/arch/mips/bcm947xx/nvram_linux.c linux-2.4.30-brcm/arch/mips/bcm947xx/nvram_linux.c
9411 --- linux-2.4.30/arch/mips/bcm947xx/nvram_linux.c 1970-01-01 01:00:00.000000000 +0100
9412 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/nvram_linux.c 2005-05-25 20:02:50.000000000 +0200
9413 @@ -0,0 +1,617 @@
9414 +/*
9415 + * NVRAM variable manipulation (Linux kernel half)
9416 + *
9417 + * Copyright 2004, Broadcom Corporation
9418 + * All Rights Reserved.
9419 + *
9420 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9421 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9422 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9423 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9424 + *
9425 + * $Id$
9426 + */
9427 +
9428 +#include <linux/config.h>
9429 +#include <linux/init.h>
9430 +#include <linux/module.h>
9431 +#include <linux/kernel.h>
9432 +#include <linux/string.h>
9433 +#include <linux/interrupt.h>
9434 +#include <linux/spinlock.h>
9435 +#include <linux/slab.h>
9436 +#include <linux/bootmem.h>
9437 +#include <linux/wrapper.h>
9438 +#include <linux/fs.h>
9439 +#include <linux/miscdevice.h>
9440 +#include <linux/mtd/mtd.h>
9441 +#include <asm/addrspace.h>
9442 +#include <asm/io.h>
9443 +#include <asm/uaccess.h>
9444 +
9445 +#include <typedefs.h>
9446 +#include <bcmendian.h>
9447 +#include <bcmnvram.h>
9448 +#include <bcmutils.h>
9449 +#include <sbconfig.h>
9450 +#include <sbchipc.h>
9451 +#include <sbutils.h>
9452 +#include <sbmips.h>
9453 +
9454 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
9455 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
9456 +
9457 +#ifdef MODULE
9458 +
9459 +#define early_nvram_get(name) nvram_get(name)
9460 +
9461 +#else /* !MODULE */
9462 +
9463 +/* Global SB handle */
9464 +extern void *bcm947xx_sbh;
9465 +extern spinlock_t bcm947xx_sbh_lock;
9466 +
9467 +/* Convenience */
9468 +#define sbh bcm947xx_sbh
9469 +#define sbh_lock bcm947xx_sbh_lock
9470 +#define KB * 1024
9471 +#define MB * 1024 * 1024
9472 +
9473 +/* Probe for NVRAM header */
9474 +static void __init
9475 +early_nvram_init(void)
9476 +{
9477 + struct nvram_header *header;
9478 + chipcregs_t *cc;
9479 + int i;
9480 + uint32 base, off, lim;
9481 +
9482 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
9483 + base = KSEG1ADDR(SB_FLASH2);
9484 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
9485 + case PFLASH:
9486 + lim = SB_FLASH2_SZ;
9487 + break;
9488 +
9489 + case SFLASH_ST:
9490 + case SFLASH_AT:
9491 + case FLASH_NONE:
9492 + default:
9493 + return;
9494 + }
9495 + } else {
9496 + /* extif assumed, Stop at 4 MB */
9497 + base = KSEG1ADDR(SB_FLASH1);
9498 + lim = SB_FLASH1_SZ;
9499 + }
9500 +
9501 + off = FLASH_MIN;
9502 + while (off <= lim) {
9503 + /* Windowed flash access */
9504 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
9505 + if (header->magic == NVRAM_MAGIC) {
9506 + u32 *src = (u32 *) header;
9507 + u32 *dst = (u32 *) nvram_buf;
9508 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
9509 + *dst++ = *src++;
9510 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
9511 + *dst++ = ltoh32(*src++);
9512 + return;
9513 + }
9514 +
9515 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
9516 + if (off == 1 KB)
9517 + break;
9518 + else if (off == 4 KB)
9519 + off = 1 KB;
9520 + else if (off == lim)
9521 + off = 4 KB;
9522 + else
9523 + off <<= 1;
9524 + }
9525 +}
9526 +
9527 +/* Early (before mm or mtd) read-only access to NVRAM */
9528 +static char * __init
9529 +early_nvram_get(const char *name)
9530 +{
9531 + char *var, *value, *end, *eq;
9532 +
9533 + if (!name)
9534 + return NULL;
9535 +
9536 + if (!nvram_buf[0])
9537 + early_nvram_init();
9538 +
9539 + /* Look for name=value and return value */
9540 + var = &nvram_buf[sizeof(struct nvram_header)];
9541 + end = nvram_buf + sizeof(nvram_buf) - 2;
9542 + end[0] = end[1] = '\0';
9543 + for (; *var; var = value + strlen(value) + 1) {
9544 + if (!(eq = strchr(var, '=')))
9545 + break;
9546 + value = eq + 1;
9547 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
9548 + return value;
9549 + }
9550 +
9551 + return NULL;
9552 +}
9553 +
9554 +#endif /* !MODULE */
9555 +
9556 +extern char * _nvram_get(const char *name);
9557 +extern int _nvram_set(const char *name, const char *value);
9558 +extern int _nvram_unset(const char *name);
9559 +extern int _nvram_getall(char *buf, int count);
9560 +extern int _nvram_commit(struct nvram_header *header);
9561 +extern int _nvram_init(void);
9562 +extern void _nvram_exit(void);
9563 +
9564 +/* Globals */
9565 +static spinlock_t nvram_lock = SPIN_LOCK_UNLOCKED;
9566 +static struct semaphore nvram_sem;
9567 +static unsigned long nvram_offset = 0;
9568 +static int nvram_major = -1;
9569 +static devfs_handle_t nvram_handle = NULL;
9570 +static struct mtd_info *nvram_mtd = NULL;
9571 +
9572 +int
9573 +_nvram_read(char *buf)
9574 +{
9575 + struct nvram_header *header = (struct nvram_header *) buf;
9576 + size_t len;
9577 +
9578 + if (!nvram_mtd ||
9579 + MTD_READ(nvram_mtd, nvram_mtd->size - NVRAM_SPACE, NVRAM_SPACE, &len, buf) ||
9580 + len != NVRAM_SPACE ||
9581 + header->magic != NVRAM_MAGIC) {
9582 + /* Maybe we can recover some data from early initialization */
9583 + memcpy(buf, nvram_buf, NVRAM_SPACE);
9584 + }
9585 +
9586 + return 0;
9587 +}
9588 +
9589 +struct nvram_tuple *
9590 +_nvram_realloc(struct nvram_tuple *t, const char *name, const char *value)
9591 +{
9592 + if ((nvram_offset + strlen(value) + 1) > NVRAM_SPACE)
9593 + return NULL;
9594 +
9595 + if (!t) {
9596 + if (!(t = kmalloc(sizeof(struct nvram_tuple) + strlen(name) + 1, GFP_ATOMIC)))
9597 + return NULL;
9598 +
9599 + /* Copy name */
9600 + t->name = (char *) &t[1];
9601 + strcpy(t->name, name);
9602 +
9603 + t->value = NULL;
9604 + }
9605 +
9606 + /* Copy value */
9607 + if (!t->value || strcmp(t->value, value)) {
9608 + t->value = &nvram_buf[nvram_offset];
9609 + strcpy(t->value, value);
9610 + nvram_offset += strlen(value) + 1;
9611 + }
9612 +
9613 + return t;
9614 +}
9615 +
9616 +void
9617 +_nvram_free(struct nvram_tuple *t)
9618 +{
9619 + if (!t)
9620 + nvram_offset = 0;
9621 + else
9622 + kfree(t);
9623 +}
9624 +
9625 +int
9626 +nvram_set(const char *name, const char *value)
9627 +{
9628 + unsigned long flags;
9629 + int ret;
9630 + struct nvram_header *header;
9631 +
9632 + spin_lock_irqsave(&nvram_lock, flags);
9633 + if ((ret = _nvram_set(name, value))) {
9634 + /* Consolidate space and try again */
9635 + if ((header = kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
9636 + if (_nvram_commit(header) == 0)
9637 + ret = _nvram_set(name, value);
9638 + kfree(header);
9639 + }
9640 + }
9641 + spin_unlock_irqrestore(&nvram_lock, flags);
9642 +
9643 + return ret;
9644 +}
9645 +
9646 +char *
9647 +real_nvram_get(const char *name)
9648 +{
9649 + unsigned long flags;
9650 + char *value;
9651 +
9652 + spin_lock_irqsave(&nvram_lock, flags);
9653 + value = _nvram_get(name);
9654 + spin_unlock_irqrestore(&nvram_lock, flags);
9655 +
9656 + return value;
9657 +}
9658 +
9659 +char *
9660 +nvram_get(const char *name)
9661 +{
9662 + if (nvram_major >= 0)
9663 + return real_nvram_get(name);
9664 + else
9665 + return early_nvram_get(name);
9666 +}
9667 +
9668 +int
9669 +nvram_unset(const char *name)
9670 +{
9671 + unsigned long flags;
9672 + int ret;
9673 +
9674 + spin_lock_irqsave(&nvram_lock, flags);
9675 + ret = _nvram_unset(name);
9676 + spin_unlock_irqrestore(&nvram_lock, flags);
9677 +
9678 + return ret;
9679 +}
9680 +
9681 +static void
9682 +erase_callback(struct erase_info *done)
9683 +{
9684 + wait_queue_head_t *wait_q = (wait_queue_head_t *) done->priv;
9685 + wake_up(wait_q);
9686 +}
9687 +
9688 +int
9689 +nvram_commit(void)
9690 +{
9691 + char *buf;
9692 + size_t erasesize, len;
9693 + unsigned int i;
9694 + int ret;
9695 + struct nvram_header *header;
9696 + unsigned long flags;
9697 + u_int32_t offset;
9698 + DECLARE_WAITQUEUE(wait, current);
9699 + wait_queue_head_t wait_q;
9700 + struct erase_info erase;
9701 +
9702 + if (!nvram_mtd) {
9703 + printk("nvram_commit: NVRAM not found\n");
9704 + return -ENODEV;
9705 + }
9706 +
9707 + if (in_interrupt()) {
9708 + printk("nvram_commit: not committing in interrupt\n");
9709 + return -EINVAL;
9710 + }
9711 +
9712 + /* Backup sector blocks to be erased */
9713 + erasesize = ROUNDUP(NVRAM_SPACE, nvram_mtd->erasesize);
9714 + if (!(buf = kmalloc(erasesize, GFP_KERNEL))) {
9715 + printk("nvram_commit: out of memory\n");
9716 + return -ENOMEM;
9717 + }
9718 +
9719 + down(&nvram_sem);
9720 +
9721 + if ((i = erasesize - NVRAM_SPACE) > 0) {
9722 + offset = nvram_mtd->size - erasesize;
9723 + len = 0;
9724 + ret = MTD_READ(nvram_mtd, offset, i, &len, buf);
9725 + if (ret || len != i) {
9726 + printk("nvram_commit: read error ret = %d, len = %d/%d\n", ret, len, i);
9727 + ret = -EIO;
9728 + goto done;
9729 + }
9730 + header = (struct nvram_header *)(buf + i);
9731 + } else {
9732 + offset = nvram_mtd->size - NVRAM_SPACE;
9733 + header = (struct nvram_header *)buf;
9734 + }
9735 +
9736 + /* Regenerate NVRAM */
9737 + spin_lock_irqsave(&nvram_lock, flags);
9738 + ret = _nvram_commit(header);
9739 + spin_unlock_irqrestore(&nvram_lock, flags);
9740 + if (ret)
9741 + goto done;
9742 +
9743 + /* Erase sector blocks */
9744 + init_waitqueue_head(&wait_q);
9745 + for (; offset < nvram_mtd->size - NVRAM_SPACE + header->len; offset += nvram_mtd->erasesize) {
9746 + erase.mtd = nvram_mtd;
9747 + erase.addr = offset;
9748 + erase.len = nvram_mtd->erasesize;
9749 + erase.callback = erase_callback;
9750 + erase.priv = (u_long) &wait_q;
9751 +
9752 + set_current_state(TASK_INTERRUPTIBLE);
9753 + add_wait_queue(&wait_q, &wait);
9754 +
9755 + /* Unlock sector blocks */
9756 + if (nvram_mtd->unlock)
9757 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
9758 +
9759 + if ((ret = MTD_ERASE(nvram_mtd, &erase))) {
9760 + set_current_state(TASK_RUNNING);
9761 + remove_wait_queue(&wait_q, &wait);
9762 + printk("nvram_commit: erase error\n");
9763 + goto done;
9764 + }
9765 +
9766 + /* Wait for erase to finish */
9767 + schedule();
9768 + remove_wait_queue(&wait_q, &wait);
9769 + }
9770 +
9771 + /* Write partition up to end of data area */
9772 + offset = nvram_mtd->size - erasesize;
9773 + i = erasesize - NVRAM_SPACE + header->len;
9774 + ret = MTD_WRITE(nvram_mtd, offset, i, &len, buf);
9775 + if (ret || len != i) {
9776 + printk("nvram_commit: write error\n");
9777 + ret = -EIO;
9778 + goto done;
9779 + }
9780 +
9781 + offset = nvram_mtd->size - erasesize;
9782 + ret = MTD_READ(nvram_mtd, offset, 4, &len, buf);
9783 +
9784 + done:
9785 + up(&nvram_sem);
9786 + kfree(buf);
9787 + return ret;
9788 +}
9789 +
9790 +int
9791 +nvram_getall(char *buf, int count)
9792 +{
9793 + unsigned long flags;
9794 + int ret;
9795 +
9796 + spin_lock_irqsave(&nvram_lock, flags);
9797 + ret = _nvram_getall(buf, count);
9798 + spin_unlock_irqrestore(&nvram_lock, flags);
9799 +
9800 + return ret;
9801 +}
9802 +
9803 +EXPORT_SYMBOL(nvram_get);
9804 +EXPORT_SYMBOL(nvram_getall);
9805 +EXPORT_SYMBOL(nvram_set);
9806 +EXPORT_SYMBOL(nvram_unset);
9807 +EXPORT_SYMBOL(nvram_commit);
9808 +
9809 +/* User mode interface below */
9810 +
9811 +static ssize_t
9812 +dev_nvram_read(struct file *file, char *buf, size_t count, loff_t *ppos)
9813 +{
9814 + char tmp[100], *name = tmp, *value;
9815 + ssize_t ret;
9816 + unsigned long off;
9817 +
9818 + if (count > sizeof(tmp)) {
9819 + if (!(name = kmalloc(count, GFP_KERNEL)))
9820 + return -ENOMEM;
9821 + }
9822 +
9823 + if (copy_from_user(name, buf, count)) {
9824 + ret = -EFAULT;
9825 + goto done;
9826 + }
9827 +
9828 + if (*name == '\0') {
9829 + /* Get all variables */
9830 + ret = nvram_getall(name, count);
9831 + if (ret == 0) {
9832 + if (copy_to_user(buf, name, count)) {
9833 + ret = -EFAULT;
9834 + goto done;
9835 + }
9836 + ret = count;
9837 + }
9838 + } else {
9839 + if (!(value = nvram_get(name))) {
9840 + ret = 0;
9841 + goto done;
9842 + }
9843 +
9844 + /* Provide the offset into mmap() space */
9845 + off = (unsigned long) value - (unsigned long) nvram_buf;
9846 +
9847 + if (put_user(off, (unsigned long *) buf)) {
9848 + ret = -EFAULT;
9849 + goto done;
9850 + }
9851 +
9852 + ret = sizeof(unsigned long);
9853 + }
9854 +
9855 + flush_cache_all();
9856 +
9857 +done:
9858 + if (name != tmp)
9859 + kfree(name);
9860 +
9861 + return ret;
9862 +}
9863 +
9864 +static ssize_t
9865 +dev_nvram_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
9866 +{
9867 + char tmp[100], *name = tmp, *value;
9868 + ssize_t ret;
9869 +
9870 + if (count > sizeof(tmp)) {
9871 + if (!(name = kmalloc(count, GFP_KERNEL)))
9872 + return -ENOMEM;
9873 + }
9874 +
9875 + if (copy_from_user(name, buf, count)) {
9876 + ret = -EFAULT;
9877 + goto done;
9878 + }
9879 +
9880 + value = name;
9881 + name = strsep(&value, "=");
9882 + if (value)
9883 + ret = nvram_set(name, value) ? : count;
9884 + else
9885 + ret = nvram_unset(name) ? : count;
9886 +
9887 + done:
9888 + if (name != tmp)
9889 + kfree(name);
9890 +
9891 + return ret;
9892 +}
9893 +
9894 +static int
9895 +dev_nvram_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
9896 +{
9897 + if (cmd != NVRAM_MAGIC)
9898 + return -EINVAL;
9899 + return nvram_commit();
9900 +}
9901 +
9902 +static int
9903 +dev_nvram_mmap(struct file *file, struct vm_area_struct *vma)
9904 +{
9905 + unsigned long offset = virt_to_phys(nvram_buf);
9906 +
9907 + if (remap_page_range(vma->vm_start, offset, vma->vm_end-vma->vm_start,
9908 + vma->vm_page_prot))
9909 + return -EAGAIN;
9910 +
9911 + return 0;
9912 +}
9913 +
9914 +static int
9915 +dev_nvram_open(struct inode *inode, struct file * file)
9916 +{
9917 + MOD_INC_USE_COUNT;
9918 + return 0;
9919 +}
9920 +
9921 +static int
9922 +dev_nvram_release(struct inode *inode, struct file * file)
9923 +{
9924 + MOD_DEC_USE_COUNT;
9925 + return 0;
9926 +}
9927 +
9928 +static struct file_operations dev_nvram_fops = {
9929 + owner: THIS_MODULE,
9930 + open: dev_nvram_open,
9931 + release: dev_nvram_release,
9932 + read: dev_nvram_read,
9933 + write: dev_nvram_write,
9934 + ioctl: dev_nvram_ioctl,
9935 + mmap: dev_nvram_mmap,
9936 +};
9937 +
9938 +static void
9939 +dev_nvram_exit(void)
9940 +{
9941 + int order = 0;
9942 + struct page *page, *end;
9943 +
9944 + if (nvram_handle)
9945 + devfs_unregister(nvram_handle);
9946 +
9947 + if (nvram_major >= 0)
9948 + devfs_unregister_chrdev(nvram_major, "nvram");
9949 +
9950 + if (nvram_mtd)
9951 + put_mtd_device(nvram_mtd);
9952 +
9953 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
9954 + order++;
9955 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
9956 + for (page = virt_to_page(nvram_buf); page <= end; page++)
9957 + mem_map_unreserve(page);
9958 +
9959 + _nvram_exit();
9960 +}
9961 +
9962 +static int __init
9963 +dev_nvram_init(void)
9964 +{
9965 + int order = 0, ret = 0;
9966 + struct page *page, *end;
9967 + unsigned int i;
9968 +
9969 + /* Allocate and reserve memory to mmap() */
9970 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
9971 + order++;
9972 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
9973 + for (page = virt_to_page(nvram_buf); page <= end; page++)
9974 + mem_map_reserve(page);
9975 +
9976 +#ifdef CONFIG_MTD
9977 + /* Find associated MTD device */
9978 + for (i = 0; i < MAX_MTD_DEVICES; i++) {
9979 + nvram_mtd = get_mtd_device(NULL, i);
9980 + if (nvram_mtd) {
9981 + if (!strcmp(nvram_mtd->name, "nvram") &&
9982 + nvram_mtd->size >= NVRAM_SPACE)
9983 + break;
9984 + put_mtd_device(nvram_mtd);
9985 + }
9986 + }
9987 + if (i >= MAX_MTD_DEVICES)
9988 + nvram_mtd = NULL;
9989 +#endif
9990 +
9991 + /* Initialize hash table lock */
9992 + spin_lock_init(&nvram_lock);
9993 +
9994 + /* Initialize commit semaphore */
9995 + init_MUTEX(&nvram_sem);
9996 +
9997 + /* Register char device */
9998 + if ((nvram_major = devfs_register_chrdev(0, "nvram", &dev_nvram_fops)) < 0) {
9999 + ret = nvram_major;
10000 + goto err;
10001 + }
10002 +
10003 + /* Initialize hash table */
10004 + _nvram_init();
10005 +
10006 + /* Create /dev/nvram handle */
10007 + nvram_handle = devfs_register(NULL, "nvram", DEVFS_FL_NONE, nvram_major, 0,
10008 + S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, &dev_nvram_fops, NULL);
10009 +
10010 + /* Set the SDRAM NCDL value into NVRAM if not already done */
10011 + if (getintvar(NULL, "sdram_ncdl") == 0) {
10012 + unsigned int ncdl;
10013 + char buf[] = "0x00000000";
10014 +
10015 + if ((ncdl = sb_memc_get_ncdl(sbh))) {
10016 + sprintf(buf, "0x%08x", ncdl);
10017 + nvram_set("sdram_ncdl", buf);
10018 + nvram_commit();
10019 + }
10020 + }
10021 +
10022 + return 0;
10023 +
10024 + err:
10025 + dev_nvram_exit();
10026 + return ret;
10027 +}
10028 +
10029 +module_init(dev_nvram_init);
10030 +module_exit(dev_nvram_exit);
10031 diff -Nur linux-2.4.30/arch/mips/bcm947xx/pcibios.c linux-2.4.30-brcm/arch/mips/bcm947xx/pcibios.c
10032 --- linux-2.4.30/arch/mips/bcm947xx/pcibios.c 1970-01-01 01:00:00.000000000 +0100
10033 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/pcibios.c 2005-05-26 01:15:53.000000000 +0200
10034 @@ -0,0 +1,355 @@
10035 +/*
10036 + * Low-Level PCI and SB support for BCM47xx (Linux support code)
10037 + *
10038 + * Copyright 2004, Broadcom Corporation
10039 + * All Rights Reserved.
10040 + *
10041 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10042 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10043 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10044 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10045 + *
10046 + * $Id$
10047 + */
10048 +
10049 +#include <linux/config.h>
10050 +#include <linux/types.h>
10051 +#include <linux/kernel.h>
10052 +#include <linux/sched.h>
10053 +#include <linux/pci.h>
10054 +#include <linux/init.h>
10055 +#include <linux/delay.h>
10056 +#include <asm/io.h>
10057 +#include <asm/irq.h>
10058 +#include <asm/paccess.h>
10059 +
10060 +#include <typedefs.h>
10061 +#include <bcmutils.h>
10062 +#include <sbconfig.h>
10063 +#include <sbpci.h>
10064 +#include <pcicfg.h>
10065 +#include <sbutils.h>
10066 +#include <bcmdevs.h>
10067 +#include <bcmnvram.h>
10068 +
10069 +/* Global SB handle */
10070 +extern void *bcm947xx_sbh;
10071 +extern spinlock_t bcm947xx_sbh_lock;
10072 +
10073 +/* Convenience */
10074 +#define sbh bcm947xx_sbh
10075 +#define sbh_lock bcm947xx_sbh_lock
10076 +
10077 +static int
10078 +sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
10079 +{
10080 + unsigned long flags;
10081 + int ret;
10082 +
10083 + spin_lock_irqsave(&sbh_lock, flags);
10084 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
10085 + spin_unlock_irqrestore(&sbh_lock, flags);
10086 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
10087 +}
10088 +
10089 +static int
10090 +sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
10091 +{
10092 + unsigned long flags;
10093 + int ret;
10094 +
10095 + spin_lock_irqsave(&sbh_lock, flags);
10096 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
10097 + spin_unlock_irqrestore(&sbh_lock, flags);
10098 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
10099 +}
10100 +
10101 +static int
10102 +sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
10103 +{
10104 + unsigned long flags;
10105 + int ret;
10106 +
10107 + spin_lock_irqsave(&sbh_lock, flags);
10108 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
10109 + spin_unlock_irqrestore(&sbh_lock, flags);
10110 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
10111 +}
10112 +
10113 +static int
10114 +sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
10115 +{
10116 + unsigned long flags;
10117 + int ret;
10118 +
10119 + spin_lock_irqsave(&sbh_lock, flags);
10120 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
10121 + spin_unlock_irqrestore(&sbh_lock, flags);
10122 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
10123 +}
10124 +
10125 +static int
10126 +sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
10127 +{
10128 + unsigned long flags;
10129 + int ret;
10130 +
10131 + spin_lock_irqsave(&sbh_lock, flags);
10132 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
10133 + spin_unlock_irqrestore(&sbh_lock, flags);
10134 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
10135 +}
10136 +
10137 +static int
10138 +sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
10139 +{
10140 + unsigned long flags;
10141 + int ret;
10142 +
10143 + spin_lock_irqsave(&sbh_lock, flags);
10144 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
10145 + spin_unlock_irqrestore(&sbh_lock, flags);
10146 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
10147 +}
10148 +
10149 +static struct pci_ops pcibios_ops = {
10150 + sbpci_read_config_byte,
10151 + sbpci_read_config_word,
10152 + sbpci_read_config_dword,
10153 + sbpci_write_config_byte,
10154 + sbpci_write_config_word,
10155 + sbpci_write_config_dword
10156 +};
10157 +
10158 +
10159 +void __init
10160 +pcibios_init(void)
10161 +{
10162 + ulong flags;
10163 +
10164 + if (!(sbh = sb_kattach()))
10165 + panic("sb_kattach failed");
10166 + spin_lock_init(&sbh_lock);
10167 +
10168 + spin_lock_irqsave(&sbh_lock, flags);
10169 + sbpci_init(sbh);
10170 + spin_unlock_irqrestore(&sbh_lock, flags);
10171 +
10172 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
10173 +
10174 + mdelay(300); //By Joey for Atheros Card
10175 +
10176 + /* Scan the SB bus */
10177 + pci_scan_bus(0, &pcibios_ops, NULL);
10178 +
10179 +}
10180 +
10181 +char * __init
10182 +pcibios_setup(char *str)
10183 +{
10184 + if (!strncmp(str, "ban=", 4)) {
10185 + sbpci_ban(simple_strtoul(str + 4, NULL, 0));
10186 + return NULL;
10187 + }
10188 +
10189 + return (str);
10190 +}
10191 +
10192 +static u32 pci_iobase = 0x100;
10193 +static u32 pci_membase = SB_PCI_DMA;
10194 +
10195 +void __init
10196 +pcibios_fixup_bus(struct pci_bus *b)
10197 +{
10198 + struct list_head *ln;
10199 + struct pci_dev *d;
10200 + struct resource *res;
10201 + int pos, size;
10202 + u32 *base;
10203 + u8 irq;
10204 +
10205 + printk("PCI: Fixing up bus %d\n", b->number);
10206 +
10207 + /* Fix up SB */
10208 + if (b->number == 0) {
10209 + for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
10210 + d = pci_dev_b(ln);
10211 + /* Fix up interrupt lines */
10212 + pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
10213 + d->irq = irq + 2;
10214 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
10215 + }
10216 + }
10217 +
10218 + /* Fix up external PCI */
10219 + else {
10220 + for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
10221 + d = pci_dev_b(ln);
10222 + /* Fix up resource bases */
10223 + for (pos = 0; pos < 6; pos++) {
10224 + res = &d->resource[pos];
10225 + base = (res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase;
10226 + if (res->end) {
10227 + size = res->end - res->start + 1;
10228 + if (*base & (size - 1))
10229 + *base = (*base + size) & ~(size - 1);
10230 + res->start = *base;
10231 + res->end = res->start + size - 1;
10232 + *base += size;
10233 + pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
10234 + }
10235 + /* Fix up PCI bridge BAR0 only */
10236 + if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
10237 + break;
10238 + }
10239 + /* Fix up interrupt lines */
10240 + if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
10241 + d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
10242 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
10243 + }
10244 + }
10245 +}
10246 +
10247 +unsigned int
10248 +pcibios_assign_all_busses(void)
10249 +{
10250 + return 1;
10251 +}
10252 +
10253 +void
10254 +pcibios_align_resource(void *data, struct resource *res,
10255 + unsigned long size, unsigned long align)
10256 +{
10257 +}
10258 +
10259 +int
10260 +pcibios_enable_resources(struct pci_dev *dev)
10261 +{
10262 + u16 cmd, old_cmd;
10263 + int idx;
10264 + struct resource *r;
10265 +
10266 + /* External PCI only */
10267 + if (dev->bus->number == 0)
10268 + return 0;
10269 +
10270 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
10271 + old_cmd = cmd;
10272 + for(idx=0; idx<6; idx++) {
10273 + r = &dev->resource[idx];
10274 + if (r->flags & IORESOURCE_IO)
10275 + cmd |= PCI_COMMAND_IO;
10276 + if (r->flags & IORESOURCE_MEM)
10277 + cmd |= PCI_COMMAND_MEMORY;
10278 + }
10279 + if (dev->resource[PCI_ROM_RESOURCE].start)
10280 + cmd |= PCI_COMMAND_MEMORY;
10281 + if (cmd != old_cmd) {
10282 + printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
10283 + pci_write_config_word(dev, PCI_COMMAND, cmd);
10284 + }
10285 + return 0;
10286 +}
10287 +
10288 +int
10289 +pcibios_enable_device(struct pci_dev *dev, int mask)
10290 +{
10291 + ulong flags;
10292 + uint coreidx;
10293 +
10294 + /* External PCI device enable */
10295 + if (dev->bus->number != 0)
10296 + return pcibios_enable_resources(dev);
10297 +
10298 + /* These cores come out of reset enabled */
10299 + if (dev->device == SB_MIPS ||
10300 + dev->device == SB_MIPS33 ||
10301 + dev->device == SB_EXTIF ||
10302 + dev->device == SB_CC)
10303 + return 0;
10304 +
10305 + spin_lock_irqsave(&sbh_lock, flags);
10306 + coreidx = sb_coreidx(sbh);
10307 + if (!sb_setcoreidx(sbh, PCI_SLOT(dev->devfn)))
10308 + return PCIBIOS_DEVICE_NOT_FOUND;
10309 +
10310 + /*
10311 + * The USB core requires a special bit to be set during core
10312 + * reset to enable host (OHCI) mode. Resetting the SB core in
10313 + * pcibios_enable_device() is a hack for compatibility with
10314 + * vanilla usb-ohci so that it does not have to know about
10315 + * SB. A driver that wants to use the USB core in device mode
10316 + * should know about SB and should reset the bit back to 0
10317 + * after calling pcibios_enable_device().
10318 + */
10319 + if (sb_coreid(sbh) == SB_USB) {
10320 + sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
10321 + sb_core_reset(sbh, 1 << 29);
10322 + } else
10323 + sb_core_reset(sbh, 0);
10324 +
10325 + sb_setcoreidx(sbh, coreidx);
10326 + spin_unlock_irqrestore(&sbh_lock, flags);
10327 +
10328 + return 0;
10329 +}
10330 +
10331 +void
10332 +pcibios_update_resource(struct pci_dev *dev, struct resource *root,
10333 + struct resource *res, int resource)
10334 +{
10335 + unsigned long where, size;
10336 + u32 reg;
10337 +
10338 + /* External PCI only */
10339 + if (dev->bus->number == 0)
10340 + return;
10341 +
10342 + where = PCI_BASE_ADDRESS_0 + (resource * 4);
10343 + size = res->end - res->start;
10344 + pci_read_config_dword(dev, where, &reg);
10345 + reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
10346 + pci_write_config_dword(dev, where, reg);
10347 +}
10348 +
10349 +static void __init
10350 +quirk_sbpci_bridge(struct pci_dev *dev)
10351 +{
10352 + if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
10353 + return;
10354 +
10355 + printk("PCI: Fixing up bridge\n");
10356 +
10357 + /* Enable PCI bridge bus mastering and memory space */
10358 + pci_set_master(dev);
10359 + pcibios_enable_resources(dev);
10360 +
10361 + /* Enable PCI bridge BAR1 prefetch and burst */
10362 + pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
10363 +}
10364 +
10365 +struct pci_fixup pcibios_fixups[] = {
10366 + { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
10367 + { 0 }
10368 +};
10369 +
10370 +/*
10371 + * If we set up a device for bus mastering, we need to check the latency
10372 + * timer as certain crappy BIOSes forget to set it properly.
10373 + */
10374 +unsigned int pcibios_max_latency = 255;
10375 +
10376 +void pcibios_set_master(struct pci_dev *dev)
10377 +{
10378 + u8 lat;
10379 + pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
10380 + if (lat < 16)
10381 + lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
10382 + else if (lat > pcibios_max_latency)
10383 + lat = pcibios_max_latency;
10384 + else
10385 + return;
10386 + printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
10387 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
10388 +}
10389 +
10390 diff -Nur linux-2.4.30/arch/mips/bcm947xx/prom.c linux-2.4.30-brcm/arch/mips/bcm947xx/prom.c
10391 --- linux-2.4.30/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
10392 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/prom.c 2005-05-22 22:55:51.000000000 +0200
10393 @@ -0,0 +1,41 @@
10394 +/*
10395 + * Early initialization code for BCM94710 boards
10396 + *
10397 + * Copyright 2004, Broadcom Corporation
10398 + * All Rights Reserved.
10399 + *
10400 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10401 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10402 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10403 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10404 + *
10405 + * $Id: prom.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
10406 + */
10407 +
10408 +#include <linux/config.h>
10409 +#include <linux/init.h>
10410 +#include <linux/kernel.h>
10411 +#include <linux/types.h>
10412 +#include <asm/bootinfo.h>
10413 +
10414 +void __init
10415 +prom_init(int argc, const char **argv)
10416 +{
10417 + unsigned long mem;
10418 +
10419 + mips_machgroup = MACH_GROUP_BRCM;
10420 + mips_machtype = MACH_BCM947XX;
10421 +
10422 + /* Figure out memory size by finding aliases */
10423 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
10424 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
10425 + *(unsigned long *)(prom_init))
10426 + break;
10427 + }
10428 + add_memory_region(0, mem, BOOT_MEM_RAM);
10429 +}
10430 +
10431 +void __init
10432 +prom_free_prom_memory(void)
10433 +{
10434 +}
10435 diff -Nur linux-2.4.30/arch/mips/bcm947xx/sbmips.c linux-2.4.30-brcm/arch/mips/bcm947xx/sbmips.c
10436 --- linux-2.4.30/arch/mips/bcm947xx/sbmips.c 1970-01-01 01:00:00.000000000 +0100
10437 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/sbmips.c 2005-05-25 05:06:08.000000000 +0200
10438 @@ -0,0 +1,982 @@
10439 +/*
10440 + * BCM47XX Sonics SiliconBackplane MIPS core routines
10441 + *
10442 + * Copyright 2004, Broadcom Corporation
10443 + * All Rights Reserved.
10444 + *
10445 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10446 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10447 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10448 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10449 + *
10450 + * $Id$
10451 + */
10452 +
10453 +#include <typedefs.h>
10454 +#include <osl.h>
10455 +#include <sbutils.h>
10456 +#include <bcmdevs.h>
10457 +#include <bcmnvram.h>
10458 +#include <bcmutils.h>
10459 +#include <hndmips.h>
10460 +#include <sbconfig.h>
10461 +#include <sbextif.h>
10462 +#include <sbchipc.h>
10463 +#include <sbmemc.h>
10464 +#include <mipsinc.h>
10465 +
10466 +/*
10467 + * Returns TRUE if an external UART exists at the given base
10468 + * register.
10469 + */
10470 +static bool
10471 +BCMINITFN(serial_exists)(uint8 *regs)
10472 +{
10473 + uint8 save_mcr, status1;
10474 +
10475 + save_mcr = R_REG(&regs[UART_MCR]);
10476 + W_REG(&regs[UART_MCR], UART_MCR_LOOP | 0x0a);
10477 + status1 = R_REG(&regs[UART_MSR]) & 0xf0;
10478 + W_REG(&regs[UART_MCR], save_mcr);
10479 +
10480 + return (status1 == 0x90);
10481 +}
10482 +
10483 +/*
10484 + * Initializes UART access. The callback function will be called once
10485 + * per found UART.
10486 + */
10487 +void
10488 +BCMINITFN(sb_serial_init)(void *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
10489 +{
10490 + void *regs;
10491 + ulong base;
10492 + uint irq;
10493 + int i, n;
10494 +
10495 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
10496 + extifregs_t *eir = (extifregs_t *) regs;
10497 + sbconfig_t *sb;
10498 +
10499 + /* Determine external UART register base */
10500 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
10501 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
10502 +
10503 + /* Determine IRQ */
10504 + irq = sb_irq(sbh);
10505 +
10506 + /* Disable GPIO interrupt initially */
10507 + W_REG(&eir->gpiointpolarity, 0);
10508 + W_REG(&eir->gpiointmask, 0);
10509 +
10510 + /* Search for external UARTs */
10511 + n = 2;
10512 + for (i = 0; i < 2; i++) {
10513 + regs = (void *) REG_MAP(base + (i * 8), 8);
10514 + if (BCMINIT(serial_exists)(regs)) {
10515 + /* Set GPIO 1 to be the external UART IRQ */
10516 + W_REG(&eir->gpiointmask, 2);
10517 + if (add)
10518 + add(regs, irq, 13500000, 0);
10519 + }
10520 + }
10521 +
10522 + /* Add internal UART if enabled */
10523 + if (R_REG(&eir->corecontrol) & CC_UE)
10524 + if (add)
10525 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
10526 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
10527 + chipcregs_t *cc = (chipcregs_t *) regs;
10528 + uint32 rev, cap, pll, baud_base, div;
10529 +
10530 + /* Determine core revision and capabilities */
10531 + rev = sb_corerev(sbh);
10532 + cap = R_REG(&cc->capabilities);
10533 + pll = cap & CAP_PLL_MASK;
10534 +
10535 + /* Determine IRQ */
10536 + irq = sb_irq(sbh);
10537 +
10538 + if (pll == PLL_TYPE1) {
10539 + /* PLL clock */
10540 + baud_base = sb_clock_rate(pll,
10541 + R_REG(&cc->clockcontrol_n),
10542 + R_REG(&cc->clockcontrol_m2));
10543 + div = 1;
10544 + } else if (rev >= 3) {
10545 + if (pll == PLL_TYPE6) {
10546 + /* Fixed ALP clock on 4320 */
10547 + baud_base = 20000000;
10548 + /* Set the override bit so we don't divide it */
10549 + W_REG(&cc->corecontrol, CC_UARTCLKO);
10550 + } else {
10551 + /* Internal backplane clock */
10552 + baud_base = sb_clock(sbh);
10553 + }
10554 + div = 2; /* Minimum divisor */
10555 + W_REG(&cc->clkdiv, ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
10556 + } else {
10557 + /* Fixed internal backplane clock */
10558 + baud_base = 88000000;
10559 + div = 48;
10560 + }
10561 +
10562 + /* Clock source depends on strapping if UartClkOverride is unset */
10563 + if ((rev > 0) && ((R_REG(&cc->corecontrol) & CC_UARTCLKO) == 0)) {
10564 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
10565 + /* Internal divided backplane clock */
10566 + baud_base /= div;
10567 + } else {
10568 + /* Assume external clock of 1.8432 MHz */
10569 + baud_base = 1843200;
10570 + }
10571 + }
10572 +
10573 + /* Add internal UARTs */
10574 + n = cap & CAP_UARTS_MASK;
10575 + for (i = 0; i < n; i++) {
10576 + /* Register offset changed after revision 0 */
10577 + if (rev)
10578 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
10579 + else
10580 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
10581 +
10582 + if (add)
10583 + add(regs, irq, baud_base, 0);
10584 + }
10585 + }
10586 +}
10587 +
10588 +/*
10589 + * Initialize jtag master and return handle for
10590 + * jtag_rwreg. Returns NULL on failure.
10591 + */
10592 +void *
10593 +sb_jtagm_init(void *sbh, uint clkd, bool exttap)
10594 +{
10595 + void *regs;
10596 +
10597 + if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
10598 + chipcregs_t *cc = (chipcregs_t *) regs;
10599 + uint32 tmp;
10600 +
10601 + /*
10602 + * Determine jtagm availability from
10603 + * core revision and capabilities.
10604 + */
10605 + tmp = sb_corerev(sbh);
10606 + /*
10607 + * Corerev 10 has jtagm, but the only chip
10608 + * with it does not have a mips, and
10609 + * the layout of the jtagcmd register is
10610 + * different. We'll only accept >= 11.
10611 + */
10612 + if (tmp < 11)
10613 + return (NULL);
10614 +
10615 + tmp = R_REG(&cc->capabilities);
10616 + if ((tmp & CAP_JTAGP) == 0)
10617 + return (NULL);
10618 +
10619 + /* Set clock divider if requested */
10620 + if (clkd != 0) {
10621 + tmp = R_REG(&cc->clkdiv);
10622 + tmp = (tmp & ~CLKD_JTAG) |
10623 + ((clkd << CLKD_JTAG_SHIFT) & CLKD_JTAG);
10624 + W_REG(&cc->clkdiv, tmp);
10625 + }
10626 +
10627 + /* Enable jtagm */
10628 + tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
10629 + W_REG(&cc->jtagctrl, tmp);
10630 + }
10631 +
10632 + return (regs);
10633 +}
10634 +
10635 +void
10636 +sb_jtagm_disable(void *h)
10637 +{
10638 + chipcregs_t *cc = (chipcregs_t *)h;
10639 +
10640 + W_REG(&cc->jtagctrl, R_REG(&cc->jtagctrl) & ~JCTRL_EN);
10641 +}
10642 +
10643 +/*
10644 + * Read/write a jtag register. Assumes a target with
10645 + * 8 bit IR and 32 bit DR.
10646 + */
10647 +#define IRWIDTH 8
10648 +#define DRWIDTH 32
10649 +uint32
10650 +jtag_rwreg(void *h, uint32 ir, uint32 dr)
10651 +{
10652 + chipcregs_t *cc = (chipcregs_t *) h;
10653 + uint32 tmp;
10654 +
10655 + W_REG(&cc->jtagir, ir);
10656 + W_REG(&cc->jtagdr, dr);
10657 + tmp = JCMD_START | JCMD_ACC_IRDR |
10658 + ((IRWIDTH - 1) << JCMD_IRW_SHIFT) |
10659 + (DRWIDTH - 1);
10660 + W_REG(&cc->jtagcmd, tmp);
10661 + while (((tmp = R_REG(&cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
10662 + /* OSL_DELAY(1); */
10663 + }
10664 +
10665 + tmp = R_REG(&cc->jtagdr);
10666 + return (tmp);
10667 +}
10668 +
10669 +/* Returns the SB interrupt flag of the current core. */
10670 +uint32
10671 +sb_flag(void *sbh)
10672 +{
10673 + void *regs;
10674 + sbconfig_t *sb;
10675 +
10676 + regs = sb_coreregs(sbh);
10677 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10678 +
10679 + return (R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK);
10680 +}
10681 +
10682 +static const uint32 sbips_int_mask[] = {
10683 + 0,
10684 + SBIPS_INT1_MASK,
10685 + SBIPS_INT2_MASK,
10686 + SBIPS_INT3_MASK,
10687 + SBIPS_INT4_MASK
10688 +};
10689 +
10690 +static const uint32 sbips_int_shift[] = {
10691 + 0,
10692 + 0,
10693 + SBIPS_INT2_SHIFT,
10694 + SBIPS_INT3_SHIFT,
10695 + SBIPS_INT4_SHIFT
10696 +};
10697 +
10698 +/*
10699 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
10700 + * 0 is returned.
10701 + */
10702 +uint
10703 +sb_irq(void *sbh)
10704 +{
10705 + uint idx;
10706 + void *regs;
10707 + sbconfig_t *sb;
10708 + uint32 flag, sbipsflag;
10709 + uint irq = 0;
10710 +
10711 + flag = sb_flag(sbh);
10712 +
10713 + idx = sb_coreidx(sbh);
10714 +
10715 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
10716 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
10717 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10718 +
10719 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
10720 + sbipsflag = R_REG(&sb->sbipsflag);
10721 + for (irq = 1; irq <= 4; irq++) {
10722 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
10723 + break;
10724 + }
10725 + if (irq == 5)
10726 + irq = 0;
10727 + }
10728 +
10729 + sb_setcoreidx(sbh, idx);
10730 +
10731 + return irq;
10732 +}
10733 +
10734 +/* Clears the specified MIPS IRQ. */
10735 +static void
10736 +BCMINITFN(sb_clearirq)(void *sbh, uint irq)
10737 +{
10738 + void *regs;
10739 + sbconfig_t *sb;
10740 +
10741 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
10742 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
10743 + ASSERT(regs);
10744 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10745 +
10746 + if (irq == 0)
10747 + W_REG(&sb->sbintvec, 0);
10748 + else
10749 + OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
10750 +}
10751 +
10752 +/*
10753 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
10754 + * IRQ 0 may be assigned more than once.
10755 + */
10756 +static void
10757 +BCMINITFN(sb_setirq)(void *sbh, uint irq, uint coreid, uint coreunit)
10758 +{
10759 + void *regs;
10760 + sbconfig_t *sb;
10761 + uint32 flag;
10762 +
10763 + regs = sb_setcore(sbh, coreid, coreunit);
10764 + ASSERT(regs);
10765 + flag = sb_flag(sbh);
10766 +
10767 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
10768 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
10769 + ASSERT(regs);
10770 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10771 +
10772 + if (irq == 0)
10773 + OR_REG(&sb->sbintvec, 1 << flag);
10774 + else {
10775 + flag <<= sbips_int_shift[irq];
10776 + ASSERT(!(flag & ~sbips_int_mask[irq]));
10777 + flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
10778 + W_REG(&sb->sbipsflag, flag);
10779 + }
10780 +}
10781 +
10782 +/*
10783 + * Initializes clocks and interrupts. SB and NVRAM access must be
10784 + * initialized prior to calling.
10785 + */
10786 +void
10787 +BCMINITFN(sb_mips_init)(void *sbh)
10788 +{
10789 + ulong hz, ns, tmp;
10790 + extifregs_t *eir;
10791 + chipcregs_t *cc;
10792 + char *value;
10793 + uint irq;
10794 +
10795 + /* Figure out current SB clock speed */
10796 + if ((hz = sb_clock(sbh)) == 0)
10797 + hz = 100000000;
10798 + ns = 1000000000 / hz;
10799 +
10800 + /* Setup external interface timing */
10801 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
10802 + /* Initialize extif so we can get to the LEDs and external UART */
10803 + W_REG(&eir->prog_config, CF_EN);
10804 +
10805 + /* Set timing for the flash */
10806 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10807 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
10808 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
10809 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10810 +
10811 + /* Set programmable interface timing for external uart */
10812 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10813 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
10814 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
10815 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
10816 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10817 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
10818 + /* Set timing for the flash */
10819 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10820 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
10821 + tmp |= CEIL(120, ns); /* W0 = 120nS */
10822 +
10823 + // Added by Chen-I for 5365
10824 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
10825 + {
10826 + W_REG(&cc->flash_waitcount, tmp);
10827 + W_REG(&cc->pcmcia_memwait, tmp);
10828 + }
10829 + else
10830 + {
10831 + if (sb_corerev(sbh) < 9)
10832 + W_REG(&cc->flash_waitcount, tmp);
10833 +
10834 + if ( (sb_corerev(sbh) < 9) ||
10835 + ((BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID) && BCMINIT(sb_chiprev)(sbh) == 0) ) {
10836 + W_REG(&cc->pcmcia_memwait, tmp);
10837 + }
10838 + }
10839 +
10840 + // Added by Chen-I & Yen for enabling 5350 EXTIF
10841 + if (BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID)
10842 + {
10843 + /* Set programmable interface timing for external uart */
10844 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10845 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
10846 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
10847 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
10848 + W_REG(&cc->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10849 + //printf("===========config_REG=%d\n", R_REG(&cc->prog_config));
10850 + //printf("-----------config_REG_addr=%x\n", &cc->prog_config);
10851 + //printf("===========waitcount_REG=%d\n", R_REG(&cc->prog_waitcount));
10852 + //printf("-----------waitcount_REG=%x\n", &cc->prog_waitcount);
10853 + }
10854 + }
10855 +
10856 + /* Chip specific initialization */
10857 + switch (BCMINIT(sb_chip)(sbh)) {
10858 + case BCM4710_DEVICE_ID:
10859 + /* Clear interrupt map */
10860 + for (irq = 0; irq <= 4; irq++)
10861 + BCMINIT(sb_clearirq)(sbh, irq);
10862 + BCMINIT(sb_setirq)(sbh, 0, SB_CODEC, 0);
10863 + BCMINIT(sb_setirq)(sbh, 0, SB_EXTIF, 0);
10864 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 1);
10865 + BCMINIT(sb_setirq)(sbh, 3, SB_ILINE20, 0);
10866 + BCMINIT(sb_setirq)(sbh, 4, SB_PCI, 0);
10867 + ASSERT(eir);
10868 + value = BCMINIT(nvram_get)("et0phyaddr");
10869 + if (value && !strcmp(value, "31")) {
10870 + /* Enable internal UART */
10871 + W_REG(&eir->corecontrol, CC_UE);
10872 + /* Give USB its own interrupt */
10873 + BCMINIT(sb_setirq)(sbh, 1, SB_USB, 0);
10874 + } else {
10875 + /* Disable internal UART */
10876 + W_REG(&eir->corecontrol, 0);
10877 + /* Give Ethernet its own interrupt */
10878 + BCMINIT(sb_setirq)(sbh, 1, SB_ENET, 0);
10879 + BCMINIT(sb_setirq)(sbh, 0, SB_USB, 0);
10880 + }
10881 + break;
10882 + case BCM4310_DEVICE_ID:
10883 + MTC0(C0_BROADCOM, 0, MFC0(C0_BROADCOM, 0) & ~(1 << 22));
10884 + break;
10885 + case BCM5350_DEVICE_ID:
10886 + /* Clear interrupt map */
10887 + for (irq = 0; irq <= 4; irq++)
10888 + BCMINIT(sb_clearirq)(sbh, irq);
10889 + BCMINIT(sb_setirq)(sbh, 0, SB_CC, 0);
10890 + BCMINIT(sb_setirq)(sbh, 1, SB_D11, 0);
10891 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 0);
10892 + BCMINIT(sb_setirq)(sbh, 3, SB_IPSEC, 0);
10893 + BCMINIT(sb_setirq)(sbh, 4, SB_USB, 0);
10894 + break;
10895 + }
10896 +}
10897 +
10898 +uint32
10899 +BCMINITFN(sb_mips_clock)(void *sbh)
10900 +{
10901 + extifregs_t *eir;
10902 + chipcregs_t *cc;
10903 + uint32 n, m;
10904 + uint idx;
10905 + uint32 pll_type, rate = 0;
10906 +
10907 + /* get index of the current core */
10908 + idx = sb_coreidx(sbh);
10909 + pll_type = PLL_TYPE1;
10910 +
10911 + /* switch to extif or chipc core */
10912 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
10913 + n = R_REG(&eir->clockcontrol_n);
10914 + m = R_REG(&eir->clockcontrol_sb);
10915 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
10916 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
10917 + n = R_REG(&cc->clockcontrol_n);
10918 + if ((pll_type == PLL_TYPE2) ||
10919 + (pll_type == PLL_TYPE4) ||
10920 + (pll_type == PLL_TYPE6))
10921 + m = R_REG(&cc->clockcontrol_mips);
10922 + else if (pll_type == PLL_TYPE5) {
10923 + rate = 200000000;
10924 + goto out;
10925 + }
10926 + else if (pll_type == PLL_TYPE3) {
10927 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID) { /* 5365 is also type3 */
10928 + rate = 200000000;
10929 + goto out;
10930 + } else
10931 + m = R_REG(&cc->clockcontrol_m2); /* 5350 uses m2 to control mips */
10932 + } else
10933 + m = R_REG(&cc->clockcontrol_sb);
10934 + } else
10935 + goto out;
10936 +
10937 + // Added by Chen-I for 5365
10938 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
10939 + rate = 100000000;
10940 + else
10941 + /* calculate rate */
10942 + rate = sb_clock_rate(pll_type, n, m);
10943 +
10944 + if (pll_type == PLL_TYPE6)
10945 + rate = SB2MIPS_T6(rate);
10946 +
10947 +out:
10948 + /* switch back to previous core */
10949 + sb_setcoreidx(sbh, idx);
10950 +
10951 + return rate;
10952 +}
10953 +
10954 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
10955 +
10956 +static void
10957 +BCMINITFN(handler)(void)
10958 +{
10959 + /* Step 11 */
10960 + __asm__ (
10961 + ".set\tmips32\n\t"
10962 + "ssnop\n\t"
10963 + "ssnop\n\t"
10964 + /* Disable interrupts */
10965 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
10966 + "mfc0 $15, $12\n\t"
10967 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
10968 + "li $14, -31746\n\t"
10969 + "and $15, $15, $14\n\t"
10970 + "mtc0 $15, $12\n\t"
10971 + "eret\n\t"
10972 + "nop\n\t"
10973 + "nop\n\t"
10974 + ".set\tmips0"
10975 + );
10976 +}
10977 +
10978 +/* The following MUST come right after handler() */
10979 +static void
10980 +BCMINITFN(afterhandler)(void)
10981 +{
10982 +}
10983 +
10984 +/*
10985 + * Set the MIPS, backplane and PCI clocks as closely as possible.
10986 + */
10987 +bool
10988 +BCMINITFN(sb_mips_setclock)(void *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
10989 +{
10990 + extifregs_t *eir = NULL;
10991 + chipcregs_t *cc = NULL;
10992 + mipsregs_t *mipsr = NULL;
10993 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
10994 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, new_ratio;
10995 + uint32 pll_type, sync_mode;
10996 + uint ic_size, ic_lsize;
10997 + uint idx, i;
10998 + typedef struct {
10999 + uint32 mipsclock;
11000 + uint16 n;
11001 + uint32 sb;
11002 + uint32 pci33;
11003 + uint32 pci25;
11004 + } n3m_table_t;
11005 + static n3m_table_t BCMINITDATA(type1_table)[] = {
11006 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 }, /* 96.000 32.000 24.000 */
11007 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 }, /* 100.000 33.333 25.000 */
11008 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 }, /* 104.000 31.200 24.960 */
11009 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 }, /* 108.000 32.400 24.923 */
11010 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 }, /* 112.000 32.000 24.889 */
11011 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 }, /* 115.200 32.000 24.000 */
11012 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 }, /* 120.000 30.000 24.000 */
11013 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 }, /* 124.800 31.200 24.960 */
11014 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 }, /* 128.000 32.000 24.000 */
11015 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 }, /* 132.000 33.000 24.750 */
11016 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 }, /* 136.000 32.640 24.727 */
11017 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 }, /* 140.000 30.000 24.706 */
11018 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 }, /* 144.000 30.857 24.686 */
11019 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 }, /* 150.857 33.000 24.000 */
11020 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 }, /* 152.000 32.571 24.000 */
11021 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 }, /* 156.000 31.200 24.960 */
11022 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 }, /* 160.000 32.000 24.000 */
11023 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 }, /* 163.200 32.640 24.727 */
11024 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 }, /* 168.000 32.000 24.889 */
11025 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 }, /* 176.000 33.000 24.000 */
11026 + };
11027 + typedef struct {
11028 + uint32 mipsclock;
11029 + uint16 n;
11030 + uint32 m2; /* that is the clockcontrol_m2 */
11031 + } type3_table_t;
11032 + static type3_table_t type3_table[] = { /* for 5350, mips clock is always double sb clock */
11033 + { 150000000, 0x311, 0x4020005 },
11034 +// { 180000000, 0x, 0x }, /* later we may want this frequency */
11035 + { 200000000, 0x311, 0x4020003 },
11036 + };
11037 + typedef struct {
11038 + uint32 mipsclock;
11039 + uint32 sbclock;
11040 + uint16 n;
11041 + uint32 sb;
11042 + uint32 pci33;
11043 + uint32 m2;
11044 + uint32 m3;
11045 + uint32 ratio;
11046 + uint32 ratio_parm;
11047 + } n4m_table_t;
11048 +
11049 + static n4m_table_t BCMINITDATA(type2_table)[] = {
11050 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 0x94, 0x012a00a9 },
11051 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 0x21, 0x0aaa0555 },
11052 + { 200000000, 100000000, 0x0303, 0x01000000, 0x01000600, 0x01000000, 0x05000000, 0x21, 0x0aaa0555 },
11053 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
11054 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
11055 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
11056 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 0x94, 0x012a00a9 },
11057 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
11058 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 0x21, 0x0aaa0555 },
11059 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
11060 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 0x94, 0x012a00a9 },
11061 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 0x94, 0x012a00a9 },
11062 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 0x21, 0x0aaa0555 },
11063 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 0x94, 0x012a00a9 },
11064 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 0x21, 0x0aaa0555 },
11065 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01020600, 0x05000100, 0x94, 0x012a00a9 },
11066 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01000100, 0x05000100, 0x21, 0x0aaa0555 }
11067 + };
11068 +
11069 + static n4m_table_t BCMINITDATA(type4_table)[] = {
11070 + { 192000000, 96000000, 0x0702, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 0x21, 0x0aaa0555 },
11071 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 0x21, 0x0aaa0555 },
11072 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 0x21, 0x0aaa0555 },
11073 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x11030305, 0x04000005, 0x94, 0x012a00a9 },
11074 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 0x21, 0x0aaa0555 },
11075 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 0x21, 0x0aaa0555 },
11076 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 0x21, 0x0aaa0555 },
11077 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 0x21, 0x0aaa0555 },
11078 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 0x73, 0x254a14a9 },
11079 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 0x73, 0x254a14a9 },
11080 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 0x73, 0x254a14a9 },
11081 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 0x52, 0x02520129 }
11082 + };
11083 + ulong start, end, dst;
11084 + bool ret = FALSE;
11085 +
11086 + /* get index of the current core */
11087 + idx = sb_coreidx(sbh);
11088 + clockcontrol_m2 = NULL;
11089 +
11090 + /* switch to extif or chipc core */
11091 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
11092 + pll_type = PLL_TYPE1;
11093 + clockcontrol_n = &eir->clockcontrol_n;
11094 + clockcontrol_sb = &eir->clockcontrol_sb;
11095 + clockcontrol_pci = &eir->clockcontrol_pci;
11096 + clockcontrol_m2 = &cc->clockcontrol_m2;
11097 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
11098 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
11099 + if (pll_type == PLL_TYPE6) {
11100 + clockcontrol_n = NULL;
11101 + clockcontrol_sb = NULL;
11102 + clockcontrol_pci = NULL;
11103 + } else {
11104 + clockcontrol_n = &cc->clockcontrol_n;
11105 + clockcontrol_sb = &cc->clockcontrol_sb;
11106 + clockcontrol_pci = &cc->clockcontrol_pci;
11107 + clockcontrol_m2 = &cc->clockcontrol_m2;
11108 + }
11109 + } else
11110 + goto done;
11111 +
11112 + if (pll_type == PLL_TYPE6) {
11113 + /* Silence compilers */
11114 + orig_n = orig_sb = orig_pci = 0;
11115 + } else {
11116 + /* Store the current clock register values */
11117 + orig_n = R_REG(clockcontrol_n);
11118 + orig_sb = R_REG(clockcontrol_sb);
11119 + orig_pci = R_REG(clockcontrol_pci);
11120 + }
11121 +
11122 + if (pll_type == PLL_TYPE1) {
11123 + /* Keep the current PCI clock if not specified */
11124 + if (pciclock == 0) {
11125 + pciclock = sb_clock_rate(pll_type, R_REG(clockcontrol_n), R_REG(clockcontrol_pci));
11126 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
11127 + }
11128 +
11129 + /* Search for the closest MIPS clock less than or equal to a preferred value */
11130 + for (i = 0; i < ARRAYSIZE(BCMINIT(type1_table)); i++) {
11131 + ASSERT(BCMINIT(type1_table)[i].mipsclock ==
11132 + sb_clock_rate(pll_type, BCMINIT(type1_table)[i].n, BCMINIT(type1_table)[i].sb));
11133 + if (BCMINIT(type1_table)[i].mipsclock > mipsclock)
11134 + break;
11135 + }
11136 + if (i == 0) {
11137 + ret = FALSE;
11138 + goto done;
11139 + } else {
11140 + ret = TRUE;
11141 + i--;
11142 + }
11143 + ASSERT(BCMINIT(type1_table)[i].mipsclock <= mipsclock);
11144 +
11145 + /* No PLL change */
11146 + if ((orig_n == BCMINIT(type1_table)[i].n) &&
11147 + (orig_sb == BCMINIT(type1_table)[i].sb) &&
11148 + (orig_pci == BCMINIT(type1_table)[i].pci33))
11149 + goto done;
11150 +
11151 + /* Set the PLL controls */
11152 + W_REG(clockcontrol_n, BCMINIT(type1_table)[i].n);
11153 + W_REG(clockcontrol_sb, BCMINIT(type1_table)[i].sb);
11154 + if (pciclock == 25000000)
11155 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci25);
11156 + else
11157 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci33);
11158 +
11159 + /* Reset */
11160 + sb_watchdog(sbh, 1);
11161 +
11162 + while (1);
11163 + } else if ((pll_type == PLL_TYPE3) &&
11164 + (BCMINIT(sb_chip)(sbh) != BCM5365_DEVICE_ID)) {
11165 + /* 5350 */
11166 + /* Search for the closest MIPS clock less than or equal to a preferred value */
11167 +
11168 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
11169 + if (type3_table[i].mipsclock > mipsclock)
11170 + break;
11171 + }
11172 + if (i == 0) {
11173 + ret = FALSE;
11174 + goto done;
11175 + } else {
11176 + ret = TRUE;
11177 + i--;
11178 + }
11179 + ASSERT(type3_table[i].mipsclock <= mipsclock);
11180 +
11181 + /* No PLL change */
11182 + orig_m2 = R_REG(&cc->clockcontrol_m2);
11183 + if ((orig_n == type3_table[i].n) &&
11184 + (orig_m2 == type3_table[i].m2)) {
11185 + goto done;
11186 + }
11187 +
11188 + /* Set the PLL controls */
11189 + W_REG(clockcontrol_n, type3_table[i].n);
11190 + W_REG(clockcontrol_m2, type3_table[i].m2);
11191 +
11192 + /* Reset */
11193 + sb_watchdog(sbh, 1);
11194 + while (1);
11195 + } else if ((pll_type == PLL_TYPE2) ||
11196 + (pll_type == PLL_TYPE4) ||
11197 + (pll_type == PLL_TYPE6)) {
11198 + n4m_table_t *table = NULL;
11199 + uint tabsz = 0;
11200 +
11201 + ASSERT(cc);
11202 +
11203 + orig_mips = R_REG(&cc->clockcontrol_mips);
11204 +
11205 + if (pll_type == PLL_TYPE6) {
11206 + uint32 new_mips = 0;
11207 +
11208 + ret = TRUE;
11209 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
11210 + new_mips = CC_T6_MMASK;
11211 +
11212 + if (orig_mips == new_mips)
11213 + goto done;
11214 +
11215 + W_REG(&cc->clockcontrol_mips, new_mips);
11216 + goto end_fill;
11217 + }
11218 +
11219 + table = (pll_type == PLL_TYPE2) ? BCMINIT(type2_table) : BCMINIT(type4_table);
11220 + tabsz = (pll_type == PLL_TYPE2) ? ARRAYSIZE(BCMINIT(type2_table)) :
11221 + ARRAYSIZE(BCMINIT(type4_table));
11222 +
11223 + /* Store the current clock register values */
11224 + orig_m2 = R_REG(&cc->clockcontrol_m2);
11225 + orig_ratio_parm = 0;
11226 +
11227 + /* Look up current ratio */
11228 + for (i = 0; i < tabsz; i++) {
11229 + if ((orig_n == table[i].n) &&
11230 + (orig_sb == table[i].sb) &&
11231 + (orig_pci == table[i].pci33) &&
11232 + (orig_m2 == table[i].m2) &&
11233 + (orig_mips == table[i].m3)) {
11234 + orig_ratio_parm = table[i].ratio_parm;
11235 + break;
11236 + }
11237 + }
11238 +
11239 + /* Search for the closest MIPS clock greater or equal to a preferred value */
11240 + for (i = 0; i < tabsz; i++) {
11241 + ASSERT(table[i].mipsclock ==
11242 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
11243 + if ((mipsclock <= table[i].mipsclock) &&
11244 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
11245 + break;
11246 + }
11247 + if (i == tabsz) {
11248 + ret = FALSE;
11249 + goto done;
11250 + } else {
11251 + ret = TRUE;
11252 + }
11253 +
11254 + /* No PLL change */
11255 + if ((orig_n == table[i].n) &&
11256 + (orig_sb == table[i].sb) &&
11257 + (orig_pci == table[i].pci33) &&
11258 + (orig_m2 == table[i].m2) &&
11259 + (orig_mips == table[i].m3))
11260 + goto done;
11261 +
11262 + /* Set the PLL controls */
11263 + W_REG(clockcontrol_n, table[i].n);
11264 + W_REG(clockcontrol_sb, table[i].sb);
11265 + W_REG(clockcontrol_pci, table[i].pci33);
11266 + W_REG(&cc->clockcontrol_m2, table[i].m2);
11267 + W_REG(&cc->clockcontrol_mips, table[i].m3);
11268 +
11269 + /* No ratio change */
11270 + if (orig_ratio_parm == table[i].ratio_parm)
11271 + goto end_fill;
11272 +
11273 + new_ratio = table[i].ratio_parm;
11274 +
11275 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
11276 +
11277 + /* Preload the code into the cache */
11278 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
11279 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
11280 + while (start < end) {
11281 + cache_unroll(start, Fill_I);
11282 + start += ic_lsize;
11283 + }
11284 +
11285 + /* Copy the handler */
11286 + start = (ulong) &BCMINIT(handler);
11287 + end = (ulong) &BCMINIT(afterhandler);
11288 + dst = KSEG1ADDR(0x180);
11289 + for (i = 0; i < (end - start); i += 4)
11290 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
11291 +
11292 + /* Preload handler into the cache one line at a time */
11293 + for (i = 0; i < (end - start); i += 4)
11294 + cache_unroll(dst + i, Fill_I);
11295 +
11296 + /* Clear BEV bit */
11297 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
11298 +
11299 + /* Enable interrupts */
11300 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
11301 +
11302 + /* Enable MIPS timer interrupt */
11303 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
11304 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
11305 + ASSERT(mipsr);
11306 + W_REG(&mipsr->intmask, 1);
11307 +
11308 + start_fill:
11309 + /* step 1, set clock ratios */
11310 + MTC0(C0_BROADCOM, 3, new_ratio);
11311 + MTC0(C0_BROADCOM, 1, 8);
11312 +
11313 + /* step 2: program timer intr */
11314 + W_REG(&mipsr->timer, 100);
11315 + (void) R_REG(&mipsr->timer);
11316 +
11317 + /* step 3, switch to async */
11318 + sync_mode = MFC0(C0_BROADCOM, 4);
11319 + MTC0(C0_BROADCOM, 4, 1 << 22);
11320 +
11321 + /* step 4, set cfg active */
11322 + MTC0(C0_BROADCOM, 2, 0x9);
11323 +
11324 +
11325 + /* steps 5 & 6 */
11326 + __asm__ __volatile__ (
11327 + ".set\tmips3\n\t"
11328 + "wait\n\t"
11329 + ".set\tmips0"
11330 + );
11331 +
11332 + /* step 7, clear cfg_active */
11333 + MTC0(C0_BROADCOM, 2, 0);
11334 +
11335 + /* Additional Step: set back to orig sync mode */
11336 + MTC0(C0_BROADCOM, 4, sync_mode);
11337 +
11338 + /* step 8, fake soft reset */
11339 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | 4);
11340 +
11341 + end_fill:
11342 + /* step 9 set watchdog timer */
11343 + sb_watchdog(sbh, 20);
11344 + (void) R_REG(&cc->chipid);
11345 +
11346 + /* step 11 */
11347 + __asm__ __volatile__ (
11348 + ".set\tmips3\n\t"
11349 + "sync\n\t"
11350 + "wait\n\t"
11351 + ".set\tmips0"
11352 + );
11353 + while (1);
11354 + }
11355 +
11356 +done:
11357 + /* switch back to previous core */
11358 + sb_setcoreidx(sbh, idx);
11359 +
11360 + return ret;
11361 +}
11362 +
11363 +
11364 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
11365 +uint32
11366 +BCMINITFN(sb_memc_get_ncdl)(void *sbh)
11367 +{
11368 + sbmemcregs_t *memc;
11369 + uint32 ret = 0;
11370 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
11371 + uint idx, rev;
11372 +
11373 + idx = sb_coreidx(sbh);
11374 +
11375 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
11376 + if (memc == 0)
11377 + goto out;
11378 +
11379 + rev = sb_corerev(sbh);
11380 +
11381 + config = R_REG(&memc->config);
11382 + wr = R_REG(&memc->wrncdlcor);
11383 + rd = R_REG(&memc->rdncdlcor);
11384 + misc = R_REG(&memc->miscdlyctl);
11385 + dqsg = R_REG(&memc->dqsgatencdl);
11386 +
11387 + rd &= MEMC_RDNCDLCOR_RD_MASK;
11388 + wr &= MEMC_WRNCDLCOR_WR_MASK;
11389 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
11390 +
11391 + if (config & MEMC_CONFIG_DDR) {
11392 + ret = (wr << 16) | (rd << 8) | dqsg;
11393 + } else {
11394 + if ( (rev > 0) || (sb_chip(sbh) == BCM5365_DEVICE_ID))
11395 +
11396 + cd = rd;
11397 + else
11398 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
11399 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
11400 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
11401 + ret = (sm << 16) | (sd << 8) | cd;
11402 + }
11403 +
11404 +out:
11405 + /* switch back to previous core */
11406 + sb_setcoreidx(sbh, idx);
11407 +
11408 + return ret;
11409 +}
11410 +
11411 +/* returns the PFC values to be used based on the chip ID*/
11412 +
11413 +uint32
11414 +BCMINITFN(sb_mips_get_pfc)(void *sbh)
11415 +{
11416 + if (BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID)
11417 + return 0x11;
11418 + else
11419 + return 0x15;
11420 +}
11421 diff -Nur linux-2.4.30/arch/mips/bcm947xx/sbpci.c linux-2.4.30-brcm/arch/mips/bcm947xx/sbpci.c
11422 --- linux-2.4.30/arch/mips/bcm947xx/sbpci.c 1970-01-01 01:00:00.000000000 +0100
11423 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/sbpci.c 2005-05-26 21:56:08.000000000 +0200
11424 @@ -0,0 +1,569 @@
11425 +/*
11426 + * Low-Level PCI and SB support for BCM47xx
11427 + *
11428 + * Copyright 2004, Broadcom Corporation
11429 + * All Rights Reserved.
11430 + *
11431 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11432 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11433 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11434 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11435 + *
11436 + * $Id$
11437 + */
11438 +
11439 +#include <typedefs.h>
11440 +#include <pcicfg.h>
11441 +#include <bcmdevs.h>
11442 +#include <sbconfig.h>
11443 +#include <sbpci.h>
11444 +#include <osl.h>
11445 +#include <bcmendian.h>
11446 +#include <bcmutils.h>
11447 +#include <sbutils.h>
11448 +#include <bcmnvram.h>
11449 +#include <hndmips.h>
11450 +
11451 +/* Can free sbpci_init() memory after boot */
11452 +#ifndef linux
11453 +#define __init
11454 +#endif
11455 +
11456 +/* Emulated configuration space */
11457 +static pci_config_regs sb_config_regs[SB_MAXCORES];
11458 +
11459 +/* Banned cores */
11460 +static uint16 pci_ban[32] = { 0 };
11461 +static uint pci_banned = 0;
11462 +
11463 +/* CardBus mode */
11464 +static bool cardbus = FALSE;
11465 +
11466 +/* Disable PCI host core */
11467 +static bool pci_disabled = FALSE;
11468 +
11469 +/*
11470 + * Functions for accessing external PCI configuration space
11471 + */
11472 +
11473 +/* Assume one-hot slot wiring */
11474 +#define PCI_SLOT_MAX 16
11475 +
11476 +static uint32
11477 +config_cmd(void *sbh, uint bus, uint dev, uint func, uint off)
11478 +{
11479 + uint coreidx;
11480 + sbpciregs_t *regs;
11481 + uint32 addr = 0;
11482 +
11483 + /* CardBusMode supports only one device */
11484 + if (cardbus && dev > 1)
11485 + return 0;
11486 +
11487 + coreidx = sb_coreidx(sbh);
11488 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
11489 +
11490 + /* Type 0 transaction */
11491 + if (bus == 1) {
11492 + /* Skip unwired slots */
11493 + if (dev < PCI_SLOT_MAX) {
11494 + /* Slide the PCI window to the appropriate slot */
11495 + W_REG(&regs->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
11496 + addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
11497 + (func << 8) | (off & ~3);
11498 + }
11499 + }
11500 +
11501 + /* Type 1 transaction */
11502 + else {
11503 + W_REG(&regs->sbtopci1, SBTOPCI_CFG1);
11504 + addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
11505 + }
11506 +
11507 + sb_setcoreidx(sbh, coreidx);
11508 +
11509 + return addr;
11510 +}
11511 +
11512 +static int
11513 +extpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11514 +{
11515 + uint32 addr, *reg = NULL, val;
11516 + int ret = 0;
11517 +
11518 + if (pci_disabled ||
11519 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
11520 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
11521 + BUSPROBE(val, reg))
11522 + val = 0xffffffff;
11523 +
11524 + val >>= 8 * (off & 3);
11525 + if (len == 4)
11526 + *((uint32 *) buf) = val;
11527 + else if (len == 2)
11528 + *((uint16 *) buf) = (uint16) val;
11529 + else if (len == 1)
11530 + *((uint8 *) buf) = (uint8) val;
11531 + else
11532 + ret = -1;
11533 +
11534 + if (reg)
11535 + REG_UNMAP(reg);
11536 +
11537 + return ret;
11538 +}
11539 +
11540 +static int
11541 +extpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11542 +{
11543 + uint32 addr, *reg = NULL, val;
11544 + int ret = 0;
11545 +
11546 + if (pci_disabled ||
11547 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
11548 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
11549 + BUSPROBE(val, reg))
11550 + goto done;
11551 +
11552 + if (len == 4)
11553 + val = *((uint32 *) buf);
11554 + else if (len == 2) {
11555 + val &= ~(0xffff << (8 * (off & 3)));
11556 + val |= *((uint16 *) buf) << (8 * (off & 3));
11557 + } else if (len == 1) {
11558 + val &= ~(0xff << (8 * (off & 3)));
11559 + val |= *((uint8 *) buf) << (8 * (off & 3));
11560 + } else
11561 + ret = -1;
11562 +
11563 + W_REG(reg, val);
11564 +
11565 + done:
11566 + if (reg)
11567 + REG_UNMAP(reg);
11568 +
11569 + return ret;
11570 +}
11571 +
11572 +/*
11573 + * Functions for accessing translated SB configuration space
11574 + */
11575 +
11576 +static int
11577 +sb_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11578 +{
11579 + pci_config_regs *cfg;
11580 +
11581 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
11582 + return -1;
11583 + cfg = &sb_config_regs[dev];
11584 +
11585 + ASSERT(ISALIGNED(off, len));
11586 + ASSERT(ISALIGNED((uintptr)buf, len));
11587 +
11588 + if (len == 4)
11589 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
11590 + else if (len == 2)
11591 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
11592 + else if (len == 1)
11593 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
11594 + else
11595 + return -1;
11596 +
11597 + return 0;
11598 +}
11599 +
11600 +static int
11601 +sb_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11602 +{
11603 + uint coreidx, n;
11604 + void *regs;
11605 + sbconfig_t *sb;
11606 + pci_config_regs *cfg;
11607 +
11608 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
11609 + return -1;
11610 + cfg = &sb_config_regs[dev];
11611 +
11612 + ASSERT(ISALIGNED(off, len));
11613 + ASSERT(ISALIGNED((uintptr)buf, len));
11614 +
11615 + /* Emulate BAR sizing */
11616 + if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
11617 + len == 4 && *((uint32 *) buf) == ~0) {
11618 + coreidx = sb_coreidx(sbh);
11619 + if ((regs = sb_setcoreidx(sbh, dev))) {
11620 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11621 + /* Highest numbered address match register */
11622 + n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
11623 + if (off == OFFSETOF(pci_config_regs, base[0]))
11624 + cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
11625 + else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
11626 + cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
11627 + else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
11628 + cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
11629 + else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
11630 + cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);
11631 + }
11632 + sb_setcoreidx(sbh, coreidx);
11633 + return 0;
11634 + }
11635 +
11636 + if (len == 4)
11637 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
11638 + else if (len == 2)
11639 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
11640 + else if (len == 1)
11641 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
11642 + else
11643 + return -1;
11644 +
11645 + return 0;
11646 +}
11647 +
11648 +int
11649 +sbpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11650 +{
11651 + if (bus == 0)
11652 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
11653 + else
11654 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
11655 +}
11656 +
11657 +int
11658 +sbpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11659 +{
11660 + if (bus == 0)
11661 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
11662 + else
11663 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
11664 +}
11665 +
11666 +void
11667 +sbpci_ban(uint16 core)
11668 +{
11669 + if (pci_banned < ARRAYSIZE(pci_ban))
11670 + pci_ban[pci_banned++] = core;
11671 +}
11672 +
11673 +int __init
11674 +sbpci_init(void *sbh)
11675 +{
11676 + uint chip, chiprev, chippkg, coreidx, host, i;
11677 + uint32 boardflags;
11678 + sbpciregs_t *pci;
11679 + sbconfig_t *sb;
11680 + pci_config_regs *cfg;
11681 + void *regs;
11682 + char varname[8];
11683 + int CT4712_WR;
11684 + uint wlidx = 0;
11685 + uint16 vendor, core;
11686 + uint8 class, subclass, progif;
11687 + uint32 val;
11688 + uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
11689 + uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
11690 +
11691 + chip = sb_chip(sbh);
11692 + chiprev = sb_chiprev(sbh);
11693 + chippkg = sb_chippkg(sbh);
11694 + coreidx = sb_coreidx(sbh);
11695 +
11696 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0)))
11697 + return -1;
11698 + sb_core_reset(sbh, 0);
11699 +
11700 + /* In some board,
11701 + if(nvram_match("boardtype", "bcm94710dev"))
11702 + CT4712_WR = 0;
11703 + else
11704 + CT4712_WR = 1;
11705 + */
11706 +
11707 + boardflags = (uint32) getintvar(NULL, "boardflags");
11708 +
11709 + if ((chip == BCM4310_DEVICE_ID) && (chiprev == 0))
11710 + pci_disabled = TRUE;
11711 +
11712 + /*
11713 + * The 200-pin BCM4712 package does not bond out PCI. Even when
11714 + * PCI is bonded out, some boards may leave the pins
11715 + * floating.
11716 + */
11717 + if (((chip == BCM4712_DEVICE_ID) &&
11718 + ((chippkg == BCM4712SMALL_PKG_ID) ||
11719 + (chippkg == BCM4712MID_PKG_ID))) )
11720 + pci_disabled = TRUE;
11721 +
11722 + /*
11723 + * If the PCI core should not be touched (disabled, not bonded
11724 + * out, or pins floating), do not even attempt to access core
11725 + * registers. Otherwise, try to determine if it is in host
11726 + * mode.
11727 + */
11728 + if (pci_disabled)
11729 + host = 0;
11730 + else
11731 + host = !BUSPROBE(val, &pci->control);
11732 +
11733 + if (!host) {
11734 + /* Disable PCI interrupts in client mode */
11735 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
11736 + W_REG(&sb->sbintvec, 0);
11737 +
11738 + /* Disable the PCI bridge in client mode */
11739 + sbpci_ban(SB_PCI);
11740 + printf("PCI: Disabled\n");
11741 + } else {
11742 + /* Reset the external PCI bus and enable the clock */
11743 + W_REG(&pci->control, 0x5); /* enable the tristate drivers */
11744 + W_REG(&pci->control, 0xd); /* enable the PCI clock */
11745 + OSL_DELAY(150); /* delay > 100 us */
11746 + W_REG(&pci->control, 0xf); /* deassert PCI reset */
11747 + W_REG(&pci->arbcontrol, PCI_INT_ARB); /* use internal arbiter */
11748 + OSL_DELAY(1); /* delay 1 us */
11749 +
11750 + /* Enable CardBusMode */
11751 + cardbus = nvram_match("cardbus", "1");
11752 + if (cardbus) {
11753 + printf("PCI: Enabling CardBus\n");
11754 + /* GPIO 1 resets the CardBus device on bcm94710ap */
11755 + sb_gpioout(sbh, 1, 1);
11756 + sb_gpioouten(sbh, 1, 1);
11757 + W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
11758 + }
11759 +
11760 + /* 64 MB I/O access window */
11761 + W_REG(&pci->sbtopci0, SBTOPCI_IO);
11762 + /* 64 MB configuration access window */
11763 + W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
11764 + /* 1 GB memory access window */
11765 + W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
11766 +
11767 + /* Enable PCI bridge BAR0 prefetch and burst */
11768 + val = 6;
11769 + sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
11770 +
11771 + /* Enable PCI interrupts */
11772 + W_REG(&pci->intmask, PCI_INTA);
11773 + }
11774 +
11775 + /* Scan the SB bus */
11776 + bzero(sb_config_regs, sizeof(sb_config_regs));
11777 + for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
11778 + cfg->vendor = 0xffff;
11779 + if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
11780 + continue;
11781 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11782 +
11783 + /* Read ID register and parse vendor and core */
11784 + val = R_REG(&sb->sbidhigh);
11785 + vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
11786 + core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
11787 + progif = 0;
11788 +
11789 + /* Check if this core is banned */
11790 + for (i = 0; i < pci_banned; i++)
11791 + if (core == pci_ban[i])
11792 + break;
11793 + if (i < pci_banned)
11794 + continue;
11795 +
11796 + /* Known vendor translations */
11797 + switch (vendor) {
11798 + case SB_VEND_BCM:
11799 + vendor = VENDOR_BROADCOM;
11800 + break;
11801 + }
11802 +
11803 + /* Determine class based on known core codes */
11804 + switch (core) {
11805 + case SB_ILINE20:
11806 + class = PCI_CLASS_NET;
11807 + subclass = PCI_NET_ETHER;
11808 + core = BCM47XX_ILINE_ID;
11809 + break;
11810 + case SB_ILINE100:
11811 + class = PCI_CLASS_NET;
11812 + subclass = PCI_NET_ETHER;
11813 + core = BCM4610_ILINE_ID;
11814 + break;
11815 + case SB_ENET:
11816 + class = PCI_CLASS_NET;
11817 + subclass = PCI_NET_ETHER;
11818 + core = BCM47XX_ENET_ID;
11819 + break;
11820 + case SB_SDRAM:
11821 + case SB_MEMC:
11822 + class = PCI_CLASS_MEMORY;
11823 + subclass = PCI_MEMORY_RAM;
11824 + break;
11825 + case SB_PCI:
11826 + class = PCI_CLASS_BRIDGE;
11827 + subclass = PCI_BRIDGE_PCI;
11828 + break;
11829 + case SB_MIPS:
11830 + case SB_MIPS33:
11831 + class = PCI_CLASS_CPU;
11832 + subclass = PCI_CPU_MIPS;
11833 + break;
11834 + case SB_CODEC:
11835 + class = PCI_CLASS_COMM;
11836 + subclass = PCI_COMM_MODEM;
11837 + core = BCM47XX_V90_ID;
11838 + break;
11839 + case SB_USB:
11840 + class = PCI_CLASS_SERIAL;
11841 + subclass = PCI_SERIAL_USB;
11842 + progif = 0x10; /* OHCI */
11843 + core = BCM47XX_USB_ID;
11844 + break;
11845 + case SB_USB11H:
11846 + class = PCI_CLASS_SERIAL;
11847 + subclass = PCI_SERIAL_USB;
11848 + progif = 0x10; /* OHCI */
11849 + core = BCM47XX_USBH_ID;
11850 + break;
11851 + case SB_USB11D:
11852 + class = PCI_CLASS_SERIAL;
11853 + subclass = PCI_SERIAL_USB;
11854 + core = BCM47XX_USBD_ID;
11855 + break;
11856 + case SB_IPSEC:
11857 + class = PCI_CLASS_CRYPT;
11858 + subclass = PCI_CRYPT_NETWORK;
11859 + core = BCM47XX_IPSEC_ID;
11860 + break;
11861 + case SB_ROBO:
11862 + class = PCI_CLASS_NET;
11863 + subclass = PCI_NET_OTHER;
11864 + core = BCM47XX_ROBO_ID;
11865 + break;
11866 + case SB_EXTIF:
11867 + case SB_CC:
11868 + class = PCI_CLASS_MEMORY;
11869 + subclass = PCI_MEMORY_FLASH;
11870 + break;
11871 + case SB_D11:
11872 + class = PCI_CLASS_NET;
11873 + subclass = PCI_NET_OTHER;
11874 + /* Let an nvram variable override this */
11875 + sprintf(varname, "wl%did", wlidx);
11876 + wlidx++;
11877 + if ((core = getintvar(NULL, varname)) == 0) {
11878 + if (chip == BCM4712_DEVICE_ID) {
11879 + if (chippkg == BCM4712SMALL_PKG_ID)
11880 + core = BCM4306_D11G_ID;
11881 + else
11882 + core = BCM4306_D11DUAL_ID;
11883 + } else {
11884 + /* 4310 */
11885 + core = BCM4310_D11B_ID;
11886 + }
11887 + }
11888 + break;
11889 +
11890 + default:
11891 + class = subclass = progif = 0xff;
11892 + break;
11893 + }
11894 +
11895 + /* Supported translations */
11896 + cfg->vendor = htol16(vendor);
11897 + cfg->device = htol16(core);
11898 + cfg->rev_id = chiprev;
11899 + cfg->prog_if = progif;
11900 + cfg->sub_class = subclass;
11901 + cfg->base_class = class;
11902 + cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
11903 + cfg->base[1] = htol32(sb_base(R_REG(&sb->sbadmatch1)));
11904 + cfg->base[2] = htol32(sb_base(R_REG(&sb->sbadmatch2)));
11905 + cfg->base[3] = htol32(sb_base(R_REG(&sb->sbadmatch3)));
11906 + cfg->base[4] = 0;
11907 + cfg->base[5] = 0;
11908 + if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
11909 + cfg->header_type = PCI_HEADER_BRIDGE;
11910 + else
11911 + cfg->header_type = PCI_HEADER_NORMAL;
11912 + /* Save core interrupt flag */
11913 + cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
11914 + /* Default to MIPS shared interrupt 0 */
11915 + cfg->int_line = 0;
11916 + /* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
11917 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
11918 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
11919 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11920 + val = R_REG(&sb->sbipsflag);
11921 + for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
11922 + if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
11923 + break;
11924 + }
11925 + if (cfg->int_line > 4)
11926 + cfg->int_line = 0;
11927 + }
11928 + /* Emulated core */
11929 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
11930 + }
11931 +
11932 + sb_setcoreidx(sbh, coreidx);
11933 + return 0;
11934 +}
11935 +
11936 +void
11937 +sbpci_check(void *sbh)
11938 +{
11939 + uint coreidx;
11940 + sbpciregs_t *pci;
11941 + uint32 sbtopci1;
11942 + uint32 buf[64], *ptr, i;
11943 + ulong pa;
11944 + volatile uint j;
11945 +
11946 + coreidx = sb_coreidx(sbh);
11947 + pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
11948 +
11949 + /* Clear the test array */
11950 + pa = (ulong) DMA_MAP(NULL, buf, sizeof(buf), DMA_RX, NULL);
11951 + ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
11952 + memset(ptr, 0, sizeof(buf));
11953 +
11954 + /* Point PCI window 1 to memory */
11955 + sbtopci1 = R_REG(&pci->sbtopci1);
11956 + W_REG(&pci->sbtopci1, SBTOPCI_MEM | (pa & SBTOPCI1_MASK));
11957 +
11958 + /* Fill the test array via PCI window 1 */
11959 + ptr = (uint32 *) REG_MAP(SB_PCI_CFG + (pa & ~SBTOPCI1_MASK), sizeof(buf));
11960 + for (i = 0; i < ARRAYSIZE(buf); i++) {
11961 + for (j = 0; j < 2; j++);
11962 + W_REG(&ptr[i], i);
11963 + }
11964 + REG_UNMAP(ptr);
11965 +
11966 + /* Restore PCI window 1 */
11967 + W_REG(&pci->sbtopci1, sbtopci1);
11968 +
11969 + /* Check the test array */
11970 + DMA_UNMAP(NULL, pa, sizeof(buf), DMA_RX, NULL);
11971 + ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
11972 + for (i = 0; i < ARRAYSIZE(buf); i++) {
11973 + if (ptr[i] != i)
11974 + break;
11975 + }
11976 +
11977 + /* Change the clock if the test fails */
11978 + if (i < ARRAYSIZE(buf)) {
11979 + uint32 req, cur;
11980 +
11981 + cur = sb_clock(sbh);
11982 + printf("PCI: Test failed at %d MHz\n", (cur + 500000) / 1000000);
11983 + for (req = 104000000; req < 176000000; req += 4000000) {
11984 + printf("PCI: Resetting to %d MHz\n", (req + 500000) / 1000000);
11985 + /* This will only reset if the clocks are valid and have changed */
11986 + sb_mips_setclock(sbh, req, 0, 0);
11987 + }
11988 + /* Should not reach here */
11989 + ASSERT(0);
11990 + }
11991 +
11992 + sb_setcoreidx(sbh, coreidx);
11993 +}
11994 diff -Nur linux-2.4.30/arch/mips/bcm947xx/setup.c linux-2.4.30-brcm/arch/mips/bcm947xx/setup.c
11995 --- linux-2.4.30/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
11996 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/setup.c 2005-05-25 17:50:08.000000000 +0200
11997 @@ -0,0 +1,261 @@
11998 +/*
11999 + * Generic setup routines for Broadcom MIPS boards
12000 + *
12001 + * Copyright 2004, Broadcom Corporation
12002 + * All Rights Reserved.
12003 + *
12004 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12005 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
12006 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
12007 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12008 + *
12009 + * $Id: setup.c,v 1.2 2005/04/02 12:12:57 wbx Exp $
12010 + */
12011 +
12012 +#include <linux/config.h>
12013 +#include <linux/init.h>
12014 +#include <linux/kernel.h>
12015 +#include <linux/serialP.h>
12016 +#include <linux/ide.h>
12017 +#include <asm/bootinfo.h>
12018 +#include <asm/time.h>
12019 +#include <asm/reboot.h>
12020 +
12021 +#ifdef CONFIG_MTD_PARTITIONS
12022 +#include <linux/mtd/mtd.h>
12023 +#include <linux/mtd/partitions.h>
12024 +#endif
12025 +
12026 +#include <typedefs.h>
12027 +#include <bcmutils.h>
12028 +#include <bcmnvram.h>
12029 +#include <sbmips.h>
12030 +#include <sbutils.h>
12031 +#include <trxhdr.h>
12032 +
12033 +extern void bcm947xx_time_init(void);
12034 +extern void bcm947xx_timer_setup(struct irqaction *irq);
12035 +extern void check_enable_mips_pfc(int val);
12036 +
12037 +#ifdef CONFIG_REMOTE_DEBUG
12038 +extern void set_debug_traps(void);
12039 +extern void rs_kgdb_hook(struct serial_state *);
12040 +extern void breakpoint(void);
12041 +#endif
12042 +
12043 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
12044 +extern struct ide_ops std_ide_ops;
12045 +#endif
12046 +
12047 +/* Global SB handle */
12048 +void *bcm947xx_sbh = NULL;
12049 +spinlock_t bcm947xx_sbh_lock = SPIN_LOCK_UNLOCKED;
12050 +EXPORT_SYMBOL(bcm947xx_sbh);
12051 +EXPORT_SYMBOL(bcm947xx_sbh_lock);
12052 +
12053 +/* Convenience */
12054 +#define sbh bcm947xx_sbh
12055 +#define sbh_lock bcm947xx_sbh_lock
12056 +
12057 +/* Kernel command line */
12058 +char arcs_cmdline[CL_SIZE] __initdata = CONFIG_CMDLINE;
12059 +
12060 +void
12061 +bcm947xx_machine_restart(char *command)
12062 +{
12063 + printk("Please stand by while rebooting the system...\n");
12064 +
12065 + /* Set the watchdog timer to reset immediately */
12066 + __cli();
12067 + sb_watchdog(sbh, 1);
12068 + while (1);
12069 +}
12070 +
12071 +void
12072 +bcm947xx_machine_halt(void)
12073 +{
12074 + printk("System halted\n");
12075 +
12076 + /* Disable interrupts and watchdog and spin forever */
12077 + __cli();
12078 + sb_watchdog(sbh, 0);
12079 + while (1);
12080 +}
12081 +
12082 +#ifdef CONFIG_SERIAL
12083 +
12084 +static struct serial_struct rs = {
12085 + line: 0,
12086 + flags: ASYNC_BOOT_AUTOCONF,
12087 + io_type: SERIAL_IO_MEM,
12088 +};
12089 +
12090 +static void __init
12091 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
12092 +{
12093 + rs.iomem_base = regs;
12094 + rs.irq = irq + 2;
12095 + rs.baud_base = baud_base / 16;
12096 + rs.iomem_reg_shift = reg_shift;
12097 +
12098 + early_serial_setup(&rs);
12099 +
12100 + rs.line++;
12101 +}
12102 +
12103 +static void __init
12104 +serial_setup(void *sbh)
12105 +{
12106 + sb_serial_init(sbh, serial_add);
12107 +
12108 +#ifdef CONFIG_REMOTE_DEBUG
12109 + /* Use the last port for kernel debugging */
12110 + if (rs.iomem_base)
12111 + rs_kgdb_hook(&rs);
12112 +#endif
12113 +}
12114 +
12115 +#endif /* CONFIG_SERIAL */
12116 +
12117 +void __init
12118 +brcm_setup(void)
12119 +{
12120 + char *value;
12121 + uint pfc_val;
12122 +
12123 + /* Get global SB handle */
12124 + sbh = sb_kattach();
12125 +
12126 + /* Initialize clocks and interrupts */
12127 + sb_mips_init(sbh);
12128 +
12129 + /*
12130 + * Now that the sbh is inited set the proper PFC value
12131 + */
12132 + pfc_val = sb_mips_get_pfc(sbh);
12133 + printk("Setting the PFC value as 0x%x\n", pfc_val);
12134 + check_enable_mips_pfc(pfc_val);
12135 +
12136 +#ifdef CONFIG_SERIAL
12137 + /* Initialize UARTs */
12138 + serial_setup(sbh);
12139 +#endif
12140 +
12141 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
12142 + ide_ops = &std_ide_ops;
12143 +#endif
12144 +
12145 + /* Override default command line arguments */
12146 + value = nvram_get("kernel_cmdline");
12147 + if (value && strlen(value) && strncmp(value, "empty", 5))
12148 + strncpy(arcs_cmdline, value, sizeof(arcs_cmdline));
12149 +
12150 +
12151 + /* Generic setup */
12152 + _machine_restart = bcm947xx_machine_restart;
12153 + _machine_halt = bcm947xx_machine_halt;
12154 + _machine_power_off = bcm947xx_machine_halt;
12155 +
12156 + board_time_init = bcm947xx_time_init;
12157 + board_timer_setup = bcm947xx_timer_setup;
12158 +}
12159 +
12160 +const char *
12161 +get_system_type(void)
12162 +{
12163 + return "Broadcom BCM947XX";
12164 +}
12165 +
12166 +void __init
12167 +bus_error_init(void)
12168 +{
12169 +}
12170 +
12171 +#ifdef CONFIG_MTD_PARTITIONS
12172 +
12173 +static struct mtd_partition bcm947xx_parts[] = {
12174 + { name: "pmon", offset: 0, size: 0, mask_flags: MTD_WRITEABLE, },
12175 + { name: "linux", offset: 0, size: 0, },
12176 + { name: "rootfs", offset: 0, size: 0, },
12177 + { name: "nvram", offset: 0, size: 0, },
12178 + { name: "OpenWrt", offset: 0, size: 0, },
12179 + { name: NULL, },
12180 +};
12181 +
12182 +static int __init
12183 +find_root(struct mtd_info *mtd, size_t size, struct mtd_partition *part)
12184 +{
12185 + struct trx_header *trx;
12186 + unsigned char buf[512];
12187 + int off;
12188 + size_t len;
12189 +
12190 + trx = (struct trx_header *) buf;
12191 +
12192 + for (off = (256*1024); off < size; off += mtd->erasesize) {
12193 + memset(buf, 0xe5, sizeof(buf));
12194 +
12195 + /*
12196 + * Read into buffer
12197 + */
12198 + if (MTD_READ(mtd, off, sizeof(buf), &len, buf) ||
12199 + len != sizeof(buf))
12200 + continue;
12201 +
12202 + /* found a TRX header */
12203 + if (le32_to_cpu(trx->magic) == TRX_MAGIC) {
12204 + part->offset = le32_to_cpu(trx->offsets[2]) ? :
12205 + le32_to_cpu(trx->offsets[1]);
12206 + part->size = le32_to_cpu(trx->len);
12207 +
12208 + part->size -= part->offset;
12209 + part->offset += off;
12210 +
12211 + goto done;
12212 + }
12213 + }
12214 +
12215 + printk(KERN_NOTICE
12216 + "%s: Couldn't find root filesystem\n",
12217 + mtd->name);
12218 + return -1;
12219 +
12220 + done:
12221 + return part->size;
12222 +}
12223 +
12224 +struct mtd_partition * __init
12225 +init_mtd_partitions(struct mtd_info *mtd, size_t size)
12226 +{
12227 +
12228 + /* boot loader */
12229 + bcm947xx_parts[0].offset=0;
12230 + bcm947xx_parts[0].size=256*1024;
12231 +
12232 + /* nvram */
12233 + bcm947xx_parts[3].offset = size - ROUNDUP(NVRAM_SPACE, mtd->erasesize);
12234 + bcm947xx_parts[3].size = size - bcm947xx_parts[3].offset;
12235 +
12236 + /* Size linux (kernel and rootfs) */
12237 + bcm947xx_parts[1].offset = bcm947xx_parts[0].size;
12238 + bcm947xx_parts[1].size = bcm947xx_parts[3].offset - bcm947xx_parts[1].offset;
12239 +
12240 + /* Find and size rootfs */
12241 + if (find_root(mtd,size,&bcm947xx_parts[2])==0) {
12242 + /* entirely jffs2 */
12243 + bcm947xx_parts[2].size = bcm947xx_parts[3].offset - bcm947xx_parts[2].offset;
12244 + bcm947xx_parts[4].name = NULL;
12245 + } else {
12246 + /* legacy setup */
12247 + /* calculate leftover flash, and assign it to the jffs2 partition */
12248 + bcm947xx_parts[4].offset = bcm947xx_parts[2].offset + bcm947xx_parts[2].size;
12249 + bcm947xx_parts[4].offset = ROUNDUP(bcm947xx_parts[4].offset, mtd->erasesize);
12250 + bcm947xx_parts[4].size = bcm947xx_parts[3].offset - bcm947xx_parts[4].offset;
12251 + }
12252 +
12253 + return bcm947xx_parts;
12254 +}
12255 +
12256 +EXPORT_SYMBOL(init_mtd_partitions);
12257 +
12258 +#endif
12259 diff -Nur linux-2.4.30/arch/mips/bcm947xx/time.c linux-2.4.30-brcm/arch/mips/bcm947xx/time.c
12260 --- linux-2.4.30/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
12261 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/time.c 2005-05-22 22:55:51.000000000 +0200
12262 @@ -0,0 +1,117 @@
12263 +/*
12264 + * Copyright 2004, Broadcom Corporation
12265 + * All Rights Reserved.
12266 + *
12267 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12268 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
12269 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
12270 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12271 + *
12272 + * $Id: time.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
12273 + */
12274 +#include <linux/config.h>
12275 +#include <linux/init.h>
12276 +#include <linux/kernel.h>
12277 +#include <linux/sched.h>
12278 +#include <linux/serial_reg.h>
12279 +#include <linux/interrupt.h>
12280 +#include <asm/addrspace.h>
12281 +#include <asm/io.h>
12282 +#include <asm/time.h>
12283 +
12284 +#include <typedefs.h>
12285 +#include <bcmnvram.h>
12286 +#include <sbconfig.h>
12287 +#include <sbextif.h>
12288 +#include <sbutils.h>
12289 +#include <sbmips.h>
12290 +
12291 +/* Global SB handle */
12292 +extern void *bcm947xx_sbh;
12293 +extern spinlock_t bcm947xx_sbh_lock;
12294 +
12295 +/* Convenience */
12296 +#define sbh bcm947xx_sbh
12297 +#define sbh_lock bcm947xx_sbh_lock
12298 +
12299 +extern int panic_timeout;
12300 +static int watchdog = 0;
12301 +static u8 *mcr = NULL;
12302 +
12303 +void __init
12304 +bcm947xx_time_init(void)
12305 +{
12306 + unsigned int hz;
12307 + extifregs_t *eir;
12308 +
12309 + /*
12310 + * Use deterministic values for initial counter interrupt
12311 + * so that calibrate delay avoids encountering a counter wrap.
12312 + */
12313 + write_c0_count(0);
12314 + write_c0_compare(0xffff);
12315 +
12316 + if (!(hz = sb_mips_clock(sbh)))
12317 + hz = 100000000;
12318 +
12319 + printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
12320 + (hz + 500000) / 1000000);
12321 +
12322 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
12323 + mips_hpt_frequency = hz / 2;
12324 +
12325 + /* Set watchdog interval in ms */
12326 + watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
12327 +
12328 + /* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
12329 + if (watchdog > 0) {
12330 + if (watchdog < 3000)
12331 + watchdog = 3000;
12332 + }
12333 +
12334 +
12335 + /* Set panic timeout in seconds */
12336 + panic_timeout = watchdog / 1000;
12337 +
12338 + /* Setup blink */
12339 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
12340 + sbconfig_t *sb = (sbconfig_t *)((unsigned int) eir + SBCONFIGOFF);
12341 + unsigned long base = EXTIF_CFGIF_BASE(sb_base(readl(&sb->sbadmatch1)));
12342 + mcr = (u8 *) ioremap_nocache(base + UART_MCR, 1);
12343 + }
12344 +}
12345 +
12346 +static void
12347 +bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
12348 +{
12349 + /* Generic MIPS timer code */
12350 + timer_interrupt(irq, dev_id, regs);
12351 +
12352 + /* Set the watchdog timer to reset after the specified number of ms */
12353 + if (watchdog > 0)
12354 + sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
12355 +
12356 +#ifdef CONFIG_HWSIM
12357 + (*((int *)0xa0000f1c))++;
12358 +#else
12359 + /* Blink one of the LEDs in the external UART */
12360 + if (mcr && !(jiffies % (HZ/2)))
12361 + writeb(readb(mcr) ^ UART_MCR_OUT2, mcr);
12362 +#endif
12363 +}
12364 +
12365 +static struct irqaction bcm947xx_timer_irqaction = {
12366 + bcm947xx_timer_interrupt,
12367 + SA_INTERRUPT,
12368 + 0,
12369 + "timer",
12370 + NULL,
12371 + NULL
12372 +};
12373 +
12374 +void __init
12375 +bcm947xx_timer_setup(struct irqaction *irq)
12376 +{
12377 + /* Enable the timer interrupt */
12378 + setup_irq(7, &bcm947xx_timer_irqaction);
12379 +}
12380 diff -Nur linux-2.4.30/arch/mips/config-shared.in linux-2.4.30-brcm/arch/mips/config-shared.in
12381 --- linux-2.4.30/arch/mips/config-shared.in 2005-01-19 15:09:27.000000000 +0100
12382 +++ linux-2.4.30-brcm/arch/mips/config-shared.in 2005-05-26 16:34:10.000000000 +0200
12383 @@ -205,6 +205,14 @@
12384 fi
12385 define_bool CONFIG_MIPS_RTC y
12386 fi
12387 +dep_bool 'Support for Broadcom MIPS-based boards' CONFIG_MIPS_BRCM $CONFIG_EXPERIMENTAL
12388 +dep_bool 'Support for Broadcom BCM947XX' CONFIG_BCM947XX $CONFIG_MIPS_BRCM
12389 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
12390 + bool ' Support for Broadcom BCM4710' CONFIG_BCM4710
12391 + bool ' Support for Broadcom BCM4310' CONFIG_BCM4310
12392 + bool ' Support for Broadcom BCM4704' CONFIG_BCM4704
12393 + bool ' Support for Broadcom BCM5365' CONFIG_BCM5365
12394 +fi
12395 bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI
12396 bool 'Support for TANBAC TB0226 (Mbase)' CONFIG_TANBAC_TB0226
12397 bool 'Support for TANBAC TB0229 (VR4131DIMM)' CONFIG_TANBAC_TB0229
12398 @@ -226,6 +234,11 @@
12399 define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
12400
12401 #
12402 +# Provide an option for a default kernel command line
12403 +#
12404 +string 'Default kernel command string' CONFIG_CMDLINE ""
12405 +
12406 +#
12407 # Select some configuration options automatically based on user selections.
12408 #
12409 if [ "$CONFIG_ACER_PICA_61" = "y" ]; then
12410 @@ -533,6 +546,13 @@
12411 define_bool CONFIG_SWAP_IO_SPACE_L y
12412 define_bool CONFIG_BOOT_ELF32 y
12413 fi
12414 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
12415 + define_bool CONFIG_PCI y
12416 + define_bool CONFIG_NONCOHERENT_IO y
12417 + define_bool CONFIG_NEW_TIME_C y
12418 + define_bool CONFIG_NEW_IRQ y
12419 + define_bool CONFIG_HND y
12420 +fi
12421 if [ "$CONFIG_SNI_RM200_PCI" = "y" ]; then
12422 define_bool CONFIG_ARC32 y
12423 define_bool CONFIG_ARC_MEMORY y
12424 @@ -1011,7 +1031,11 @@
12425
12426 bool 'Are you using a crosscompiler' CONFIG_CROSSCOMPILE
12427 bool 'Enable run-time debugging' CONFIG_RUNTIME_DEBUG
12428 -bool 'Remote GDB kernel debugging' CONFIG_KGDB
12429 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
12430 + bool 'Remote GDB kernel debugging' CONFIG_REMOTE_DEBUG
12431 +else
12432 + bool 'Remote GDB kernel debugging' CONFIG_KGDB
12433 +fi
12434 dep_bool ' Console output to GDB' CONFIG_GDB_CONSOLE $CONFIG_KGDB
12435 if [ "$CONFIG_KGDB" = "y" ]; then
12436 define_bool CONFIG_DEBUG_INFO y
12437 diff -Nur linux-2.4.30/arch/mips/kernel/cpu-probe.c linux-2.4.30-brcm/arch/mips/kernel/cpu-probe.c
12438 --- linux-2.4.30/arch/mips/kernel/cpu-probe.c 2005-01-19 15:09:29.000000000 +0100
12439 +++ linux-2.4.30-brcm/arch/mips/kernel/cpu-probe.c 2005-05-22 22:55:51.000000000 +0200
12440 @@ -174,7 +174,7 @@
12441
12442 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
12443 {
12444 - switch (c->processor_id & 0xff00) {
12445 + switch (c->processor_id & PRID_IMP_MASK) {
12446 case PRID_IMP_R2000:
12447 c->cputype = CPU_R2000;
12448 c->isa_level = MIPS_CPU_ISA_I;
12449 @@ -184,7 +184,7 @@
12450 c->tlbsize = 64;
12451 break;
12452 case PRID_IMP_R3000:
12453 - if ((c->processor_id & 0xff) == PRID_REV_R3000A)
12454 + if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A)
12455 if (cpu_has_confreg())
12456 c->cputype = CPU_R3081E;
12457 else
12458 @@ -199,12 +199,12 @@
12459 break;
12460 case PRID_IMP_R4000:
12461 if (read_c0_config() & CONF_SC) {
12462 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
12463 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
12464 c->cputype = CPU_R4400PC;
12465 else
12466 c->cputype = CPU_R4000PC;
12467 } else {
12468 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
12469 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
12470 c->cputype = CPU_R4400SC;
12471 else
12472 c->cputype = CPU_R4000SC;
12473 @@ -450,7 +450,7 @@
12474 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
12475 {
12476 decode_config1(c);
12477 - switch (c->processor_id & 0xff00) {
12478 + switch (c->processor_id & PRID_IMP_MASK) {
12479 case PRID_IMP_4KC:
12480 c->cputype = CPU_4KC;
12481 c->isa_level = MIPS_CPU_ISA_M32;
12482 @@ -491,10 +491,10 @@
12483 {
12484 decode_config1(c);
12485 c->options |= MIPS_CPU_PREFETCH;
12486 - switch (c->processor_id & 0xff00) {
12487 + switch (c->processor_id & PRID_IMP_MASK) {
12488 case PRID_IMP_AU1_REV1:
12489 case PRID_IMP_AU1_REV2:
12490 - switch ((c->processor_id >> 24) & 0xff) {
12491 + switch ((c->processor_id >> 24) & PRID_REV_MASK) {
12492 case 0:
12493 c->cputype = CPU_AU1000;
12494 break;
12495 @@ -522,10 +522,34 @@
12496 }
12497 }
12498
12499 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
12500 +{
12501 + decode_config1(c);
12502 + c->options |= MIPS_CPU_PREFETCH;
12503 + switch (c->processor_id & PRID_IMP_MASK) {
12504 + case PRID_IMP_BCM4710:
12505 + c->cputype = CPU_BCM4710;
12506 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
12507 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
12508 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
12509 + break;
12510 + case PRID_IMP_4KC:
12511 + case PRID_IMP_BCM3302:
12512 + c->cputype = CPU_BCM3302;
12513 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
12514 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
12515 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
12516 + break;
12517 + default:
12518 + c->cputype = CPU_UNKNOWN;
12519 + break;
12520 + }
12521 +}
12522 +
12523 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
12524 {
12525 decode_config1(c);
12526 - switch (c->processor_id & 0xff00) {
12527 + switch (c->processor_id & PRID_IMP_MASK) {
12528 case PRID_IMP_SB1:
12529 c->cputype = CPU_SB1;
12530 c->isa_level = MIPS_CPU_ISA_M64;
12531 @@ -547,7 +571,7 @@
12532 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
12533 {
12534 decode_config1(c);
12535 - switch (c->processor_id & 0xff00) {
12536 + switch (c->processor_id & PRID_IMP_MASK) {
12537 case PRID_IMP_SR71000:
12538 c->cputype = CPU_SR71000;
12539 c->isa_level = MIPS_CPU_ISA_M64;
12540 @@ -572,7 +596,7 @@
12541 c->cputype = CPU_UNKNOWN;
12542
12543 c->processor_id = read_c0_prid();
12544 - switch (c->processor_id & 0xff0000) {
12545 + switch (c->processor_id & PRID_COMP_MASK) {
12546
12547 case PRID_COMP_LEGACY:
12548 cpu_probe_legacy(c);
12549 @@ -583,6 +607,9 @@
12550 case PRID_COMP_ALCHEMY:
12551 cpu_probe_alchemy(c);
12552 break;
12553 + case PRID_COMP_BROADCOM:
12554 + cpu_probe_broadcom(c);
12555 + break;
12556 case PRID_COMP_SIBYTE:
12557 cpu_probe_sibyte(c);
12558 break;
12559 diff -Nur linux-2.4.30/arch/mips/kernel/head.S linux-2.4.30-brcm/arch/mips/kernel/head.S
12560 --- linux-2.4.30/arch/mips/kernel/head.S 2005-01-19 15:09:29.000000000 +0100
12561 +++ linux-2.4.30-brcm/arch/mips/kernel/head.S 2005-05-22 22:55:51.000000000 +0200
12562 @@ -28,12 +28,20 @@
12563 #include <asm/mipsregs.h>
12564 #include <asm/stackframe.h>
12565
12566 +#ifdef CONFIG_BCM4710
12567 +#undef eret
12568 +#define eret nop; nop; eret
12569 +#endif
12570 +
12571 .text
12572 + j kernel_entry
12573 + nop
12574 +
12575 /*
12576 * Reserved space for exception handlers.
12577 * Necessary for machines which link their kernels at KSEG0.
12578 */
12579 - .fill 0x400
12580 + .fill 0x3f4
12581
12582 /* The following two symbols are used for kernel profiling. */
12583 EXPORT(stext)
12584 diff -Nur linux-2.4.30/arch/mips/kernel/proc.c linux-2.4.30-brcm/arch/mips/kernel/proc.c
12585 --- linux-2.4.30/arch/mips/kernel/proc.c 2005-01-19 15:09:29.000000000 +0100
12586 +++ linux-2.4.30-brcm/arch/mips/kernel/proc.c 2005-05-22 22:55:51.000000000 +0200
12587 @@ -78,9 +78,10 @@
12588 [CPU_AU1550] "Au1550",
12589 [CPU_24K] "MIPS 24K",
12590 [CPU_AU1200] "Au1200",
12591 + [CPU_BCM4710] "BCM4710",
12592 + [CPU_BCM3302] "BCM3302",
12593 };
12594
12595 -
12596 static int show_cpuinfo(struct seq_file *m, void *v)
12597 {
12598 unsigned int version = current_cpu_data.processor_id;
12599 diff -Nur linux-2.4.30/arch/mips/kernel/setup.c linux-2.4.30-brcm/arch/mips/kernel/setup.c
12600 --- linux-2.4.30/arch/mips/kernel/setup.c 2005-01-19 15:09:29.000000000 +0100
12601 +++ linux-2.4.30-brcm/arch/mips/kernel/setup.c 2005-05-25 19:00:43.000000000 +0200
12602 @@ -495,6 +495,7 @@
12603 void swarm_setup(void);
12604 void hp_setup(void);
12605 void au1x00_setup(void);
12606 + void brcm_setup(void);
12607 void frame_info_init(void);
12608
12609 frame_info_init();
12610 @@ -693,6 +694,11 @@
12611 pmc_yosemite_setup();
12612 break;
12613 #endif
12614 +#if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4310)
12615 + case MACH_GROUP_BRCM:
12616 + brcm_setup();
12617 + break;
12618 +#endif
12619 default:
12620 panic("Unsupported architecture");
12621 }
12622 diff -Nur linux-2.4.30/arch/mips/kernel/traps.c linux-2.4.30-brcm/arch/mips/kernel/traps.c
12623 --- linux-2.4.30/arch/mips/kernel/traps.c 2005-01-19 15:09:29.000000000 +0100
12624 +++ linux-2.4.30-brcm/arch/mips/kernel/traps.c 2005-05-22 22:55:51.000000000 +0200
12625 @@ -913,6 +913,7 @@
12626 void __init trap_init(void)
12627 {
12628 extern char except_vec1_generic;
12629 + extern char except_vec2_generic;
12630 extern char except_vec3_generic, except_vec3_r4000;
12631 extern char except_vec_ejtag_debug;
12632 extern char except_vec4;
12633 @@ -922,6 +923,7 @@
12634
12635 /* Copy the generic exception handler code to it's final destination. */
12636 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
12637 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
12638
12639 /*
12640 * Setup default vectors
12641 @@ -980,6 +982,12 @@
12642 set_except_vector(13, handle_tr);
12643 set_except_vector(22, handle_mdmx);
12644
12645 + if (current_cpu_data.cputype == CPU_SB1) {
12646 + /* Enable timer interrupt and scd mapped interrupt */
12647 + clear_c0_status(0xf000);
12648 + set_c0_status(0xc00);
12649 + }
12650 +
12651 if (cpu_has_fpu && !cpu_has_nofpuex)
12652 set_except_vector(15, handle_fpe);
12653
12654 diff -Nur linux-2.4.30/arch/mips/Makefile linux-2.4.30-brcm/arch/mips/Makefile
12655 --- linux-2.4.30/arch/mips/Makefile 2005-01-19 15:09:26.000000000 +0100
12656 +++ linux-2.4.30-brcm/arch/mips/Makefile 2005-05-25 18:53:09.000000000 +0200
12657 @@ -46,10 +46,10 @@
12658 GCCFLAGS := -I $(TOPDIR)/include/asm/gcc
12659 GCCFLAGS += -G 0 -mno-abicalls -fno-pic -pipe
12660 GCCFLAGS += $(call check_gcc, -finline-limit=100000,)
12661 -LINKFLAGS += -G 0 -static -n
12662 -MODFLAGS += -mlong-calls
12663 +LINKFLAGS += -G 0 -static -n -nostdlib
12664 +MODFLAGS += -mlong-calls -fno-common
12665
12666 -ifdef CONFIG_DEBUG_INFO
12667 +ifdef CONFIG_REMOTE_DEBUG
12668 GCCFLAGS += -g
12669 ifdef CONFIG_SB1XXX_CORELIS
12670 GCCFLAGS += -mno-sched-prolog -fno-omit-frame-pointer
12671 @@ -71,13 +71,13 @@
12672 set_gccflags = $(shell \
12673 while :; do \
12674 cpu=$(1); isa=-$(2); \
12675 - for gcc_opt in -march= -mcpu=; do \
12676 + for gcc_opt in -march= -mtune=; do \
12677 $(CC) $$gcc_opt$$cpu $$isa -S -o /dev/null \
12678 -xc /dev/null > /dev/null 2>&1 && \
12679 break 2; \
12680 done; \
12681 cpu=$(3); isa=-$(4); \
12682 - for gcc_opt in -march= -mcpu=; do \
12683 + for gcc_opt in -march= -mtune=; do \
12684 $(CC) $$gcc_opt$$cpu $$isa -S -o /dev/null \
12685 -xc /dev/null > /dev/null 2>&1 && \
12686 break 2; \
12687 @@ -92,7 +92,7 @@
12688 fi; \
12689 gas_abi=-Wa,-32; gas_cpu=$$cpu; gas_isa=-Wa,$$isa; \
12690 while :; do \
12691 - for gas_opt in -Wa,-march= -Wa,-mcpu=; do \
12692 + for gas_opt in -Wa,-march= -Wa,-mtune=; do \
12693 $(CC) $$gas_abi $$gas_opt$$cpu $$gas_isa -Wa,-Z -c \
12694 -o /dev/null -xassembler /dev/null > /dev/null 2>&1 && \
12695 break 2; \
12696 @@ -174,6 +174,7 @@
12697 endif
12698
12699 AFLAGS += $(GCCFLAGS)
12700 +ASFLAGS += $(GCCFLAGS)
12701 CFLAGS += $(GCCFLAGS)
12702
12703 LD += -m $(ld-emul)
12704 @@ -715,6 +716,19 @@
12705 endif
12706
12707 #
12708 +# Broadcom BCM947XX variants
12709 +#
12710 +ifdef CONFIG_BCM947XX
12711 +LIBS += arch/mips/bcm947xx/generic/brcm.o arch/mips/bcm947xx/bcm947xx.o
12712 +SUBDIRS += arch/mips/bcm947xx/generic arch/mips/bcm947xx
12713 +LOADADDR := 0x80001000
12714 +
12715 +zImage: vmlinux
12716 + $(MAKE) -C arch/$(ARCH)/bcm947xx/compressed
12717 +export LOADADDR
12718 +endif
12719 +
12720 +#
12721 # Choosing incompatible machines durings configuration will result in
12722 # error messages during linking. Select a default linkscript if
12723 # none has been choosen above.
12724 @@ -767,6 +781,7 @@
12725 $(MAKE) -C arch/$(ARCH)/tools clean
12726 $(MAKE) -C arch/mips/baget clean
12727 $(MAKE) -C arch/mips/lasat clean
12728 + $(MAKE) -C arch/mips/bcm947xx/compressed clean
12729
12730 archmrproper:
12731 @$(MAKEBOOT) mrproper
12732 diff -Nur linux-2.4.30/arch/mips/mm/c-r4k.c linux-2.4.30-brcm/arch/mips/mm/c-r4k.c
12733 --- linux-2.4.30/arch/mips/mm/c-r4k.c 2005-01-19 15:09:29.000000000 +0100
12734 +++ linux-2.4.30-brcm/arch/mips/mm/c-r4k.c 2005-05-26 08:53:48.000000000 +0200
12735 @@ -1114,3 +1114,47 @@
12736 build_clear_page();
12737 build_copy_page();
12738 }
12739 +
12740 +#ifdef CONFIG_BCM4704
12741 +static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
12742 +{
12743 + unsigned long ic_lsize = current_cpu_data.icache.linesz;
12744 + int i;
12745 + for (i = 0; i < nbytes; i += ic_lsize)
12746 + fill_icache_line((addr + i));
12747 +}
12748 +
12749 +/*
12750 + * This must be run from the cache on 4704A0
12751 + * so there are no mips core BIU ops in progress
12752 + * when the PFC is enabled.
12753 + */
12754 +#define PFC_CR0 0xff400000 /* control reg 0 */
12755 +#define PFC_CR1 0xff400004 /* control reg 1 */
12756 +static void __init enable_pfc(u32 mode)
12757 +{
12758 + /* write range */
12759 + *(volatile u32 *)PFC_CR1 = 0xffff0000;
12760 +
12761 + /* enable */
12762 + *(volatile u32 *)PFC_CR0 = mode;
12763 +}
12764 +#endif
12765 +
12766 +
12767 +void check_enable_mips_pfc(int val)
12768 +{
12769 +
12770 +#ifdef CONFIG_BCM4704
12771 + struct cpuinfo_mips *c = &current_cpu_data;
12772 +
12773 + /* enable prefetch cache */
12774 + if (((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) == PRID_IMP_BCM3302)
12775 + && (read_c0_diag() & (1 << 29))) {
12776 + mips32_icache_fill((unsigned long) &enable_pfc, 64);
12777 + enable_pfc(val);
12778 + }
12779 +#endif
12780 +}
12781 +
12782 +
12783 diff -Nur linux-2.4.30/arch/mips/pci/Makefile linux-2.4.30-brcm/arch/mips/pci/Makefile
12784 --- linux-2.4.30/arch/mips/pci/Makefile 2005-01-19 15:09:29.000000000 +0100
12785 +++ linux-2.4.30-brcm/arch/mips/pci/Makefile 2005-05-26 01:02:53.000000000 +0200
12786 @@ -13,7 +13,9 @@
12787 obj-$(CONFIG_MIPS_MSC) += ops-msc.o
12788 obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
12789 obj-$(CONFIG_SNI_RM200_PCI) += ops-sni.o
12790 +ifndef CONFIG_BCM947XX
12791 obj-y += pci.o
12792 +endif
12793 obj-$(CONFIG_PCI_AUTO) += pci_auto.o
12794
12795 include $(TOPDIR)/Rules.make
12796 diff -Nur linux-2.4.30/drivers/char/serial.c linux-2.4.30-brcm/drivers/char/serial.c
12797 --- linux-2.4.30/drivers/char/serial.c 2005-01-19 15:09:50.000000000 +0100
12798 +++ linux-2.4.30-brcm/drivers/char/serial.c 2005-05-22 22:55:52.000000000 +0200
12799 @@ -422,6 +422,10 @@
12800 return inb(info->port+1);
12801 #endif
12802 case SERIAL_IO_MEM:
12803 +#ifdef CONFIG_BCM4310
12804 + readb((unsigned long) info->iomem_base +
12805 + (UART_SCR<<info->iomem_reg_shift));
12806 +#endif
12807 return readb((unsigned long) info->iomem_base +
12808 (offset<<info->iomem_reg_shift));
12809 default:
12810 @@ -442,6 +446,9 @@
12811 case SERIAL_IO_MEM:
12812 writeb(value, (unsigned long) info->iomem_base +
12813 (offset<<info->iomem_reg_shift));
12814 +#ifdef CONFIG_BCM4704
12815 + *((volatile unsigned int *) KSEG1ADDR(0x18000000));
12816 +#endif
12817 break;
12818 default:
12819 outb(value, info->port+offset);
12820 @@ -5972,6 +5979,13 @@
12821 * Divisor, bytesize and parity
12822 */
12823 state = rs_table + co->index;
12824 + /*
12825 + * Safe guard: state structure must have been initialized
12826 + */
12827 + if (state->iomem_base == NULL) {
12828 + printk("!unable to setup serial console!\n");
12829 + return -1;
12830 + }
12831 if (doflow)
12832 state->flags |= ASYNC_CONS_FLOW;
12833 info = &async_sercons;
12834 diff -Nur linux-2.4.30/drivers/mtd/maps/bcm947xx-flash.c linux-2.4.30-brcm/drivers/mtd/maps/bcm947xx-flash.c
12835 --- linux-2.4.30/drivers/mtd/maps/bcm947xx-flash.c 1970-01-01 01:00:00.000000000 +0100
12836 +++ linux-2.4.30-brcm/drivers/mtd/maps/bcm947xx-flash.c 2005-05-22 22:55:52.000000000 +0200
12837 @@ -0,0 +1,236 @@
12838 +/*
12839 + * Flash mapping for BCM947XX boards
12840 + *
12841 + * Copyright 2004, Broadcom Corporation
12842 + * All Rights Reserved.
12843 + *
12844 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12845 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
12846 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
12847 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12848 + *
12849 + * $Id: bcm947xx-flash.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
12850 + */
12851 +
12852 +#include <linux/module.h>
12853 +#include <linux/types.h>
12854 +#include <linux/kernel.h>
12855 +#include <asm/io.h>
12856 +#include <linux/mtd/mtd.h>
12857 +#include <linux/mtd/map.h>
12858 +#include <linux/mtd/partitions.h>
12859 +#include <linux/config.h>
12860 +
12861 +#include <typedefs.h>
12862 +#include <bcmnvram.h>
12863 +#include <bcmutils.h>
12864 +#include <sbconfig.h>
12865 +#include <sbchipc.h>
12866 +#include <sbutils.h>
12867 +#include <trxhdr.h>
12868 +
12869 +/* Global SB handle */
12870 +extern void *bcm947xx_sbh;
12871 +extern spinlock_t bcm947xx_sbh_lock;
12872 +
12873 +/* Convenience */
12874 +#define sbh bcm947xx_sbh
12875 +#define sbh_lock bcm947xx_sbh_lock
12876 +
12877 +#ifdef CONFIG_MTD_PARTITIONS
12878 +extern struct mtd_partition * init_mtd_partitions(struct mtd_info *mtd, size_t size);
12879 +#endif
12880 +
12881 +#define WINDOW_ADDR 0x1fc00000
12882 +#define WINDOW_SIZE 0x400000
12883 +#define BUSWIDTH 2
12884 +
12885 +/* e.g., flash=2M or flash=4M */
12886 +static int flash = 0;
12887 +MODULE_PARM(flash, "i");
12888 +static int __init
12889 +bcm947xx_setup(char *str)
12890 +{
12891 + flash = memparse(str, &str);
12892 + return 1;
12893 +}
12894 +__setup("flash=", bcm947xx_setup);
12895 +
12896 +static struct mtd_info *bcm947xx_mtd;
12897 +
12898 +__u8 bcm947xx_map_read8(struct map_info *map, unsigned long ofs)
12899 +{
12900 + if (map->map_priv_2 == 1)
12901 + return __raw_readb(map->map_priv_1 + ofs);
12902 +
12903 + u16 val = __raw_readw(map->map_priv_1 + (ofs & ~1));
12904 + if (ofs & 1)
12905 + return ((val >> 8) & 0xff);
12906 + else
12907 + return (val & 0xff);
12908 +}
12909 +
12910 +__u16 bcm947xx_map_read16(struct map_info *map, unsigned long ofs)
12911 +{
12912 + return __raw_readw(map->map_priv_1 + ofs);
12913 +}
12914 +
12915 +__u32 bcm947xx_map_read32(struct map_info *map, unsigned long ofs)
12916 +{
12917 + return __raw_readl(map->map_priv_1 + ofs);
12918 +}
12919 +
12920 +void bcm947xx_map_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
12921 +{
12922 + if (len==1) {
12923 + memcpy_fromio(to, map->map_priv_1 + from, len);
12924 + } else {
12925 + int i;
12926 + u16 *dest = (u16 *) to;
12927 + u16 *src = (u16 *) (map->map_priv_1 + from);
12928 + for (i = 0; i < (len / 2); i++) {
12929 + dest[i] = src[i];
12930 + }
12931 + if (len & 1)
12932 + *((u8 *)dest+len-1) = src[i] & 0xff;
12933 + }
12934 +}
12935 +
12936 +void bcm947xx_map_write8(struct map_info *map, __u8 d, unsigned long adr)
12937 +{
12938 + __raw_writeb(d, map->map_priv_1 + adr);
12939 + mb();
12940 +}
12941 +
12942 +void bcm947xx_map_write16(struct map_info *map, __u16 d, unsigned long adr)
12943 +{
12944 + __raw_writew(d, map->map_priv_1 + adr);
12945 + mb();
12946 +}
12947 +
12948 +void bcm947xx_map_write32(struct map_info *map, __u32 d, unsigned long adr)
12949 +{
12950 + __raw_writel(d, map->map_priv_1 + adr);
12951 + mb();
12952 +}
12953 +
12954 +void bcm947xx_map_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
12955 +{
12956 + memcpy_toio(map->map_priv_1 + to, from, len);
12957 +}
12958 +
12959 +struct map_info bcm947xx_map = {
12960 + name: "Physically mapped flash",
12961 + size: WINDOW_SIZE,
12962 + buswidth: BUSWIDTH,
12963 + read8: bcm947xx_map_read8,
12964 + read16: bcm947xx_map_read16,
12965 + read32: bcm947xx_map_read32,
12966 + copy_from: bcm947xx_map_copy_from,
12967 + write8: bcm947xx_map_write8,
12968 + write16: bcm947xx_map_write16,
12969 + write32: bcm947xx_map_write32,
12970 + copy_to: bcm947xx_map_copy_to
12971 +};
12972 +
12973 +#if LINUX_VERSION_CODE < 0x20212 && defined(MODULE)
12974 +#define init_bcm947xx_map init_module
12975 +#define cleanup_bcm947xx_map cleanup_module
12976 +#endif
12977 +
12978 +mod_init_t init_bcm947xx_map(void)
12979 +{
12980 + ulong flags;
12981 + uint coreidx;
12982 + chipcregs_t *cc;
12983 + uint32 fltype;
12984 + uint window_addr = 0, window_size = 0;
12985 + size_t size;
12986 + int ret = 0;
12987 +#ifdef CONFIG_MTD_PARTITIONS
12988 + struct mtd_partition *parts;
12989 + int i;
12990 +#endif
12991 +
12992 + spin_lock_irqsave(&sbh_lock, flags);
12993 + coreidx = sb_coreidx(sbh);
12994 +
12995 + /* Check strapping option if chipcommon exists */
12996 + if ((cc = sb_setcore(sbh, SB_CC, 0))) {
12997 + fltype = readl(&cc->capabilities) & CAP_FLASH_MASK;
12998 + if (fltype == PFLASH) {
12999 + bcm947xx_map.map_priv_2 = 1;
13000 + window_addr = 0x1c000000;
13001 + bcm947xx_map.size = window_size = 32 * 1024 * 1024;
13002 + if ((readl(&cc->flash_config) & CC_CFG_DS) == 0)
13003 + bcm947xx_map.buswidth = 1;
13004 + }
13005 + } else {
13006 + fltype = PFLASH;
13007 + bcm947xx_map.map_priv_2 = 0;
13008 + window_addr = WINDOW_ADDR;
13009 + window_size = WINDOW_SIZE;
13010 + }
13011 +
13012 + sb_setcoreidx(sbh, coreidx);
13013 + spin_unlock_irqrestore(&sbh_lock, flags);
13014 +
13015 + if (fltype != PFLASH) {
13016 + printk(KERN_ERR "pflash: found no supported devices\n");
13017 + ret = -ENODEV;
13018 + goto fail;
13019 + }
13020 +
13021 + bcm947xx_map.map_priv_1 = (unsigned long) ioremap(window_addr, window_size);
13022 + if (!bcm947xx_map.map_priv_1) {
13023 + printk(KERN_ERR "pflash: ioremap failed\n");
13024 + ret = -EIO;
13025 + goto fail;
13026 + }
13027 +
13028 + if (!(bcm947xx_mtd = do_map_probe("cfi_probe", &bcm947xx_map))) {
13029 + printk(KERN_ERR "pflash: cfi_probe failed\n");
13030 + ret = -ENXIO;
13031 + goto fail;
13032 + }
13033 +
13034 + bcm947xx_mtd->module = THIS_MODULE;
13035 +
13036 + /* Allow size override for testing */
13037 + size = flash ? : bcm947xx_mtd->size;
13038 +
13039 + printk(KERN_NOTICE "Flash device: 0x%x at 0x%x\n", size, window_addr);
13040 +
13041 +#ifdef CONFIG_MTD_PARTITIONS
13042 + parts = init_mtd_partitions(bcm947xx_mtd, size);
13043 + for (i = 0; parts[i].name; i++);
13044 + ret = add_mtd_partitions(bcm947xx_mtd, parts, i);
13045 + if (ret) {
13046 + printk(KERN_ERR "pflash: add_mtd_partitions failed\n");
13047 + goto fail;
13048 + }
13049 +#endif
13050 +
13051 + return 0;
13052 +
13053 + fail:
13054 + if (bcm947xx_mtd)
13055 + map_destroy(bcm947xx_mtd);
13056 + if (bcm947xx_map.map_priv_1)
13057 + iounmap((void *) bcm947xx_map.map_priv_1);
13058 + bcm947xx_map.map_priv_1 = 0;
13059 + return ret;
13060 +}
13061 +
13062 +mod_exit_t cleanup_bcm947xx_map(void)
13063 +{
13064 +#ifdef CONFIG_MTD_PARTITIONS
13065 + del_mtd_partitions(bcm947xx_mtd);
13066 +#endif
13067 + map_destroy(bcm947xx_mtd);
13068 + iounmap((void *) bcm947xx_map.map_priv_1);
13069 + bcm947xx_map.map_priv_1 = 0;
13070 +}
13071 +
13072 +module_init(init_bcm947xx_map);
13073 +module_exit(cleanup_bcm947xx_map);
13074 diff -Nur linux-2.4.30/drivers/mtd/maps/Config.in linux-2.4.30-brcm/drivers/mtd/maps/Config.in
13075 --- linux-2.4.30/drivers/mtd/maps/Config.in 2003-06-13 16:51:34.000000000 +0200
13076 +++ linux-2.4.30-brcm/drivers/mtd/maps/Config.in 2005-05-25 18:58:03.000000000 +0200
13077 @@ -48,6 +48,7 @@
13078 fi
13079
13080 if [ "$CONFIG_MIPS" = "y" ]; then
13081 + dep_tristate ' CFI Flash device mapped on Broadcom BCM947XX boards' CONFIG_MTD_BCM947XX $CONFIG_MTD_CFI
13082 dep_tristate ' Pb1000 MTD support' CONFIG_MTD_PB1000 $CONFIG_MIPS_PB1000
13083 dep_tristate ' Pb1500 MTD support' CONFIG_MTD_PB1500 $CONFIG_MIPS_PB1500
13084 dep_tristate ' Pb1100 MTD support' CONFIG_MTD_PB1100 $CONFIG_MIPS_PB1100
13085 diff -Nur linux-2.4.30/drivers/mtd/maps/Makefile linux-2.4.30-brcm/drivers/mtd/maps/Makefile
13086 --- linux-2.4.30/drivers/mtd/maps/Makefile 2003-06-13 16:51:34.000000000 +0200
13087 +++ linux-2.4.30-brcm/drivers/mtd/maps/Makefile 2005-05-25 18:57:31.000000000 +0200
13088 @@ -3,6 +3,8 @@
13089 #
13090 # $Id: Makefile,v 1.37 2003/01/24 14:26:38 dwmw2 Exp $
13091
13092 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
13093 +
13094 BELOW25 := $(shell echo $(PATCHLEVEL) | sed s/[1234]/y/)
13095
13096 ifeq ($(BELOW25),y)
13097 @@ -10,6 +12,7 @@
13098 endif
13099
13100 # Chip mappings
13101 +obj-$(CONFIG_MTD_BCM947XX) += bcm947xx-flash.o
13102 obj-$(CONFIG_MTD_CDB89712) += cdb89712.o
13103 obj-$(CONFIG_MTD_ARM_INTEGRATOR)+= integrator-flash.o
13104 obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o
13105 diff -Nur linux-2.4.30/drivers/net/Config.in linux-2.4.30-brcm/drivers/net/Config.in
13106 --- linux-2.4.30/drivers/net/Config.in 2005-01-19 15:09:56.000000000 +0100
13107 +++ linux-2.4.30-brcm/drivers/net/Config.in 2005-05-25 04:34:51.000000000 +0200
13108 @@ -2,6 +2,8 @@
13109 # Network device configuration
13110 #
13111
13112 +tristate 'Broadcom Home Network Division' CONFIG_HND $CONFIG_PCI
13113 +
13114 source drivers/net/arcnet/Config.in
13115
13116 tristate 'Dummy net driver support' CONFIG_DUMMY
13117 @@ -173,6 +175,7 @@
13118
13119 dep_tristate ' Apricot Xen-II on board Ethernet' CONFIG_APRICOT $CONFIG_ISA
13120 dep_tristate ' Broadcom 4400 ethernet support (EXPERIMENTAL)' CONFIG_B44 $CONFIG_PCI $CONFIG_EXPERIMENTAL
13121 + dep_tristate ' Proprietary Broadcom 10/100 Ethernet support' CONFIG_ET $CONFIG_PCI
13122 dep_tristate ' CS89x0 support' CONFIG_CS89x0 $CONFIG_ISA
13123 dep_tristate ' DECchip Tulip (dc21x4x) PCI support' CONFIG_TULIP $CONFIG_PCI
13124 if [ "$CONFIG_TULIP" = "y" -o "$CONFIG_TULIP" = "m" ]; then
13125 diff -Nur linux-2.4.30/drivers/net/et/Makefile linux-2.4.30-brcm/drivers/net/et/Makefile
13126 --- linux-2.4.30/drivers/net/et/Makefile 1970-01-01 01:00:00.000000000 +0100
13127 +++ linux-2.4.30-brcm/drivers/net/et/Makefile 2005-05-26 02:37:05.000000000 +0200
13128 @@ -0,0 +1,21 @@
13129 +#
13130 +# Makefile for the Broadcom et driver
13131 +#
13132 +# Copyright 2004, Broadcom Corporation
13133 +# All Rights Reserved.
13134 +#
13135 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
13136 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13137 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
13138 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
13139 +#
13140 +# $Id: Makefile,v 1.1 2005/03/16 13:50:00 wbx Exp $
13141 +#
13142 +
13143 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include -DBCM47XX_CHOPS -DDMA -DBCMDRIVER
13144 +
13145 +O_TARGET := et.o
13146 +obj-y := et_linux.o etc.o etc47xx.o etc_robo.o etc_adm.o
13147 +obj-m := $(O_TARGET)
13148 +
13149 +include $(TOPDIR)/Rules.make
13150 diff -Nur linux-2.4.30/drivers/net/hnd/bcmsrom.c linux-2.4.30-brcm/drivers/net/hnd/bcmsrom.c
13151 --- linux-2.4.30/drivers/net/hnd/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
13152 +++ linux-2.4.30-brcm/drivers/net/hnd/bcmsrom.c 2005-05-22 23:00:53.000000000 +0200
13153 @@ -0,0 +1,714 @@
13154 +/*
13155 + * Misc useful routines to access NIC SROM/OTP .
13156 + *
13157 + * Copyright 2004, Broadcom Corporation
13158 + * All Rights Reserved.
13159 + *
13160 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
13161 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13162 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
13163 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
13164 + * $Id$
13165 + */
13166 +
13167 +#include <typedefs.h>
13168 +#include <osl.h>
13169 +#include <bcmutils.h>
13170 +#include <bcmsrom.h>
13171 +#include <bcmdevs.h>
13172 +#include <bcmendian.h>
13173 +#include <sbpcmcia.h>
13174 +#include <pcicfg.h>
13175 +#include <sbutils.h>
13176 +
13177 +#include <proto/ethernet.h> /* for sprom content groking */
13178 +
13179 +#define VARS_MAX 4096 /* should be reduced */
13180 +
13181 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
13182 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
13183 +
13184 +static int initvars_srom_pci(void *osh, void *curmap, char **vars, int *count);
13185 +static int initvars_cis_pcmcia(void *sbh, void *curmap, void *osh, char **vars, int *count);
13186 +static int srom_parsecis(void *osh, uint8 *cis, char **vars, int *count);
13187 +static int sprom_cmd_pcmcia(void *osh, uint8 cmd);
13188 +static int sprom_read_pcmcia(void *osh, uint16 addr, uint16 *data);
13189 +static int sprom_write_pcmcia(void *osh, uint16 addr, uint16 data);
13190 +static int sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc);
13191 +
13192 +/*
13193 + * Initialize local vars from the right source for this platform.
13194 + * Return 0 on success, nonzero on error.
13195 + */
13196 +int
13197 +srom_var_init(void *sbh, uint bustype, void *curmap, void *osh, char **vars, int *count)
13198 +{
13199 + ASSERT(bustype == BUSTYPE(bustype));
13200 + if (vars == NULL)
13201 + return (0);
13202 +
13203 + switch (BUSTYPE(bustype)) {
13204 + case SB_BUS:
13205 + /* These two could be asserts ... */
13206 + *vars = NULL;
13207 + *count = 0;
13208 + return(0);
13209 +
13210 + case PCI_BUS:
13211 + ASSERT(curmap); /* can not be NULL */
13212 + return(initvars_srom_pci(osh, curmap, vars, count));
13213 +
13214 + case PCMCIA_BUS:
13215 + return(initvars_cis_pcmcia(sbh, curmap, osh, vars, count));
13216 +
13217 +
13218 + default:
13219 + ASSERT(0);
13220 + }
13221 + return (-1);
13222 +}
13223 +
13224 +/* support only 16-bit word read from srom */
13225 +int
13226 +srom_read(uint bustype, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf)
13227 +{
13228 + void *srom;
13229 + uint i, off, nw;
13230 +
13231 + ASSERT(bustype == BUSTYPE(bustype));
13232 +
13233 + /* check input - 16-bit access only */
13234 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
13235 + return 1;
13236 +
13237 + off = byteoff / 2;
13238 + nw = nbytes / 2;
13239 +
13240 + if (BUSTYPE(bustype) == PCI_BUS) {
13241 + if (!curmap)
13242 + return 1;
13243 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
13244 + if (sprom_read_pci(srom, off, buf, nw, FALSE))
13245 + return 1;
13246 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
13247 + for (i = 0; i < nw; i++) {
13248 + if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
13249 + return 1;
13250 + }
13251 + } else {
13252 + return 1;
13253 + }
13254 +
13255 + return 0;
13256 +}
13257 +
13258 +/* support only 16-bit word write into srom */
13259 +int
13260 +srom_write(uint bustype, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf)
13261 +{
13262 + uint16 *srom;
13263 + uint i, off, nw, crc_range;
13264 + uint16 image[SPROM_SIZE], *p;
13265 + uint8 crc;
13266 + volatile uint32 val32;
13267 +
13268 + ASSERT(bustype == BUSTYPE(bustype));
13269 +
13270 + /* check input - 16-bit access only */
13271 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
13272 + return 1;
13273 +
13274 + crc_range = (((BUSTYPE(bustype) == PCMCIA_BUS) || (BUSTYPE(bustype) == SDIO_BUS)) ? SPROM_SIZE : SPROM_CRC_RANGE) * 2;
13275 +
13276 + /* if changes made inside crc cover range */
13277 + if (byteoff < crc_range) {
13278 + nw = (((byteoff + nbytes) > crc_range) ? byteoff + nbytes : crc_range) / 2;
13279 + /* read data including entire first 64 words from srom */
13280 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
13281 + return 1;
13282 + /* make changes */
13283 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
13284 + /* calculate crc */
13285 + htol16_buf(image, crc_range);
13286 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
13287 + ltoh16_buf(image, crc_range);
13288 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
13289 + p = image;
13290 + off = 0;
13291 + } else {
13292 + p = buf;
13293 + off = byteoff / 2;
13294 + nw = nbytes / 2;
13295 + }
13296 +
13297 + if (BUSTYPE(bustype) == PCI_BUS) {
13298 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
13299 + /* enable writes to the SPROM */
13300 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
13301 + val32 |= SPROM_WRITEEN;
13302 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
13303 + bcm_mdelay(WRITE_ENABLE_DELAY);
13304 + /* write srom */
13305 + for (i = 0; i < nw; i++) {
13306 + W_REG(&srom[off + i], p[i]);
13307 + bcm_mdelay(WRITE_WORD_DELAY);
13308 + }
13309 + /* disable writes to the SPROM */
13310 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 & ~SPROM_WRITEEN);
13311 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
13312 + /* enable writes to the SPROM */
13313 + if (sprom_cmd_pcmcia(osh, SROM_WEN))
13314 + return 1;
13315 + bcm_mdelay(WRITE_ENABLE_DELAY);
13316 + /* write srom */
13317 + for (i = 0; i < nw; i++) {
13318 + sprom_write_pcmcia(osh, (uint16)(off + i), p[i]);
13319 + bcm_mdelay(WRITE_WORD_DELAY);
13320 + }
13321 + /* disable writes to the SPROM */
13322 + if (sprom_cmd_pcmcia(osh, SROM_WDS))
13323 + return 1;
13324 + } else {
13325 + return 1;
13326 + }
13327 +
13328 + bcm_mdelay(WRITE_ENABLE_DELAY);
13329 + return 0;
13330 +}
13331 +
13332 +
13333 +static int
13334 +srom_parsecis(void *osh, uint8 *cis, char **vars, int *count)
13335 +{
13336 + char eabuf[32];
13337 + char *vp, *base;
13338 + uint8 tup, tlen, sromrev = 1;
13339 + int i, j;
13340 + uint varsize;
13341 + bool ag_init = FALSE;
13342 + uint16 w;
13343 +
13344 + ASSERT(vars);
13345 + ASSERT(count);
13346 +
13347 + base = vp = MALLOC(osh, VARS_MAX);
13348 + ASSERT(vp);
13349 +
13350 + i = 0;
13351 + do {
13352 + tup = cis[i++];
13353 + tlen = cis[i++];
13354 + if ((i + tlen) >= CIS_SIZE)
13355 + break;
13356 +
13357 + switch (tup) {
13358 + case CISTPL_MANFID:
13359 + vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
13360 + vp++;
13361 + vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
13362 + vp++;
13363 + break;
13364 +
13365 + case CISTPL_FUNCE:
13366 + if (cis[i] == LAN_NID) {
13367 + ASSERT(cis[i + 1] == ETHER_ADDR_LEN);
13368 + bcm_ether_ntoa((uchar*)&cis[i + 2], eabuf);
13369 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
13370 + vp++;
13371 + }
13372 + break;
13373 +
13374 + case CISTPL_CFTABLE:
13375 + vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
13376 + vp++;
13377 + break;
13378 +
13379 + case CISTPL_BRCM_HNBU:
13380 + switch (cis[i]) {
13381 + case HNBU_CHIPID:
13382 + vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) + cis[i + 1]);
13383 + vp++;
13384 + vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) + cis[i + 3]);
13385 + vp++;
13386 + if (tlen == 7) {
13387 + vp += sprintf(vp, "chiprev=%d", (cis[i + 6] << 8) + cis[i + 5]);
13388 + vp++;
13389 + }
13390 + break;
13391 +
13392 + case HNBU_BOARDREV:
13393 + vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
13394 + vp++;
13395 + break;
13396 +
13397 + case HNBU_AA:
13398 + vp += sprintf(vp, "aa0=%d", cis[i + 1]);
13399 + vp++;
13400 + break;
13401 +
13402 + case HNBU_AG:
13403 + vp += sprintf(vp, "ag0=%d", cis[i + 1]);
13404 + vp++;
13405 + ag_init = TRUE;
13406 + break;
13407 +
13408 + case HNBU_CC:
13409 + vp += sprintf(vp, "cc=%d", cis[i + 1]);
13410 + vp++;
13411 + break;
13412 +
13413 + case HNBU_PAPARMS:
13414 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + tlen - 1]);
13415 + vp++;
13416 + if (tlen == 9) {
13417 + /* New version */
13418 + for (j = 0; j < 3; j++) {
13419 + vp += sprintf(vp, "pa0b%d=%d", j,
13420 + (cis[i + (j * 2) + 2] << 8) + cis[i + (j * 2) + 1]);
13421 + vp++;
13422 + }
13423 + vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
13424 + vp++;
13425 + }
13426 + break;
13427 +
13428 + case HNBU_OEM:
13429 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
13430 + cis[i + 1], cis[i + 2], cis[i + 3], cis[i + 4],
13431 + cis[i + 5], cis[i + 6], cis[i + 7], cis[i + 8]);
13432 + vp++;
13433 + break;
13434 + case HNBU_BOARDFLAGS:
13435 + w = (cis[i + 2] << 8) + cis[i + 1];
13436 + if (w == 0xffff) w = 0;
13437 + vp += sprintf(vp, "boardflags=%d", w);
13438 + vp++;
13439 + break;
13440 + case HNBU_LED:
13441 + if (cis[i + 1] != 0xff) {
13442 + vp += sprintf(vp, "wl0gpio0=%d", cis[i + 1]);
13443 + vp++;
13444 + }
13445 + if (cis[i + 2] != 0xff) {
13446 + vp += sprintf(vp, "wl0gpio1=%d", cis[i + 2]);
13447 + vp++;
13448 + }
13449 + if (cis[i + 3] != 0xff) {
13450 + vp += sprintf(vp, "wl0gpio2=%d", cis[i + 3]);
13451 + vp++;
13452 + }
13453 + if (cis[i + 4] != 0xff) {
13454 + vp += sprintf(vp, "wl0gpio3=%d", cis[i + 4]);
13455 + vp++;
13456 + }
13457 + break;
13458 + }
13459 + break;
13460 +
13461 + }
13462 + i += tlen;
13463 + } while (tup != 0xff);
13464 +
13465 + /* Set the srom version */
13466 + vp += sprintf(vp, "sromrev=%d", sromrev);
13467 + vp++;
13468 +
13469 + /* For now just set boardflags2 to zero */
13470 + vp += sprintf(vp, "boardflags2=0");
13471 + vp++;
13472 +
13473 + /* if there is no antenna gain field, set default */
13474 + if (ag_init == FALSE) {
13475 + vp += sprintf(vp, "ag0=%d", 0xff);
13476 + vp++;
13477 + }
13478 +
13479 + /* final nullbyte terminator */
13480 + *vp++ = '\0';
13481 + varsize = (uint)(vp - base);
13482 +
13483 + ASSERT((vp - base) < VARS_MAX);
13484 +
13485 + if (varsize == VARS_MAX) {
13486 + *vars = base;
13487 + } else {
13488 + vp = MALLOC(osh, varsize);
13489 + ASSERT(vp);
13490 + bcopy(base, vp, varsize);
13491 + MFREE(osh, base, VARS_MAX);
13492 + *vars = vp;
13493 + }
13494 + *count = varsize;
13495 +
13496 + return (0);
13497 +}
13498 +
13499 +
13500 +/* set PCMCIA sprom command register */
13501 +static int
13502 +sprom_cmd_pcmcia(void *osh, uint8 cmd)
13503 +{
13504 + uint8 status = 0;
13505 + uint wait_cnt = 1000;
13506 +
13507 + /* write sprom command register */
13508 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
13509 +
13510 + /* wait status */
13511 + while (wait_cnt--) {
13512 + OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
13513 + if (status & SROM_DONE)
13514 + return 0;
13515 + }
13516 +
13517 + return 1;
13518 +}
13519 +
13520 +/* read a word from the PCMCIA srom */
13521 +static int
13522 +sprom_read_pcmcia(void *osh, uint16 addr, uint16 *data)
13523 +{
13524 + uint8 addr_l, addr_h, data_l, data_h;
13525 +
13526 + addr_l = (uint8)((addr * 2) & 0xff);
13527 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
13528 +
13529 + /* set address */
13530 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
13531 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
13532 +
13533 + /* do read */
13534 + if (sprom_cmd_pcmcia(osh, SROM_READ))
13535 + return 1;
13536 +
13537 + /* read data */
13538 + data_h = data_l = 0;
13539 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
13540 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
13541 +
13542 + *data = (data_h << 8) | data_l;
13543 + return 0;
13544 +}
13545 +
13546 +/* write a word to the PCMCIA srom */
13547 +static int
13548 +sprom_write_pcmcia(void *osh, uint16 addr, uint16 data)
13549 +{
13550 + uint8 addr_l, addr_h, data_l, data_h;
13551 +
13552 + addr_l = (uint8)((addr * 2) & 0xff);
13553 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
13554 + data_l = (uint8)(data & 0xff);
13555 + data_h = (uint8)((data >> 8) & 0xff);
13556 +
13557 + /* set address */
13558 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
13559 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
13560 +
13561 + /* write data */
13562 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
13563 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
13564 +
13565 + /* do write */
13566 + return sprom_cmd_pcmcia(osh, SROM_WRITE);
13567 +}
13568 +
13569 +/*
13570 + * Read in and validate sprom.
13571 + * Return 0 on success, nonzero on error.
13572 + */
13573 +static int
13574 +sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
13575 +{
13576 + uint8 chk8;
13577 + uint i;
13578 +
13579 + /* read the sprom */
13580 + for (i = 0; i < nwords; i++)
13581 + buf[i] = R_REG(&sprom[wordoff + i]);
13582 +
13583 + if (check_crc) {
13584 + /* fixup the endianness so crc8 will pass */
13585 + htol16_buf(buf, nwords * 2);
13586 + if ((chk8 = hndcrc8((uchar*)buf, nwords * 2, CRC8_INIT_VALUE)) != CRC8_GOOD_VALUE)
13587 + return (1);
13588 + /* now correct the endianness of the byte array */
13589 + ltoh16_buf(buf, nwords * 2);
13590 + }
13591 +
13592 + return (0);
13593 +}
13594 +
13595 +/*
13596 + * Initialize nonvolatile variable table from sprom.
13597 + * Return 0 on success, nonzero on error.
13598 + */
13599 +
13600 +static int
13601 +initvars_srom_pci(void *osh, void *curmap, char **vars, int *count)
13602 +{
13603 + uint16 w, b[64];
13604 + uint8 sromrev;
13605 + struct ether_addr ea;
13606 + char eabuf[32];
13607 + uint32 bfl;
13608 + int c, woff, i;
13609 + char *vp, *base;
13610 +
13611 + if (sprom_read_pci((void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof(b)/sizeof(b[0]), TRUE))
13612 + return (-1);
13613 +
13614 + /* top word of sprom contains version and crc8 */
13615 + sromrev = b[63] & 0xff;
13616 + /* bcm4401 sroms misprogrammed */
13617 + if (sromrev == 0x10)
13618 + sromrev = 1;
13619 + if ((sromrev != 1) && (sromrev != 2))
13620 + return (-2);
13621 +
13622 + ASSERT(vars);
13623 + ASSERT(count);
13624 +
13625 + base = vp = MALLOC(osh, VARS_MAX);
13626 + ASSERT(vp);
13627 +
13628 + vp += sprintf(vp, "sromrev=%d", sromrev);
13629 + vp++;
13630 +
13631 + if (sromrev >= 2) {
13632 + /* New section takes over the 4th hardware function space */
13633 +
13634 + /* Word 29 is max power 11a high/low */
13635 + w = b[29];
13636 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
13637 + vp++;
13638 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
13639 + vp++;
13640 +
13641 + /* Words 30-32 set the 11alow pa settings,
13642 + * 33-35 are the 11ahigh ones.
13643 + */
13644 + for (i = 0; i < 3; i++) {
13645 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
13646 + vp++;
13647 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
13648 + vp++;
13649 + }
13650 + w = b[59];
13651 + if (w == 0)
13652 + vp += sprintf(vp, "ccode=");
13653 + else
13654 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
13655 + vp++;
13656 +
13657 + }
13658 +
13659 + /* parameter section of sprom starts at byte offset 72 */
13660 + woff = 72/2;
13661 +
13662 + /* first 6 bytes are il0macaddr */
13663 + ea.octet[0] = (b[woff] >> 8) & 0xff;
13664 + ea.octet[1] = b[woff] & 0xff;
13665 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
13666 + ea.octet[3] = b[woff+1] & 0xff;
13667 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
13668 + ea.octet[5] = b[woff+2] & 0xff;
13669 + woff += ETHER_ADDR_LEN/2 ;
13670 + bcm_ether_ntoa((uchar*)&ea, eabuf);
13671 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
13672 + vp++;
13673 +
13674 + /* next 6 bytes are et0macaddr */
13675 + ea.octet[0] = (b[woff] >> 8) & 0xff;
13676 + ea.octet[1] = b[woff] & 0xff;
13677 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
13678 + ea.octet[3] = b[woff+1] & 0xff;
13679 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
13680 + ea.octet[5] = b[woff+2] & 0xff;
13681 + woff += ETHER_ADDR_LEN/2 ;
13682 + bcm_ether_ntoa((uchar*)&ea, eabuf);
13683 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
13684 + vp++;
13685 +
13686 + /* next 6 bytes are et1macaddr */
13687 + ea.octet[0] = (b[woff] >> 8) & 0xff;
13688 + ea.octet[1] = b[woff] & 0xff;
13689 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
13690 + ea.octet[3] = b[woff+1] & 0xff;
13691 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
13692 + ea.octet[5] = b[woff+2] & 0xff;
13693 + woff += ETHER_ADDR_LEN/2 ;
13694 + bcm_ether_ntoa((uchar*)&ea, eabuf);
13695 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
13696 + vp++;
13697 +
13698 + /*
13699 + * Enet phy settings one or two singles or a dual
13700 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
13701 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
13702 + * Bit 14 : Mdio for enet0
13703 + * Bit 15 : Mdio for enet1
13704 + */
13705 + w = b[woff];
13706 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
13707 + vp++;
13708 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
13709 + vp++;
13710 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
13711 + vp++;
13712 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
13713 + vp++;
13714 +
13715 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
13716 + w = b[46];
13717 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
13718 + vp++;
13719 +
13720 + if (sromrev > 1)
13721 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
13722 + else
13723 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
13724 + vp++;
13725 +
13726 + vp += sprintf(vp, "aa0=%d", (w >> 12) & 0x3);
13727 + vp++;
13728 +
13729 + vp += sprintf(vp, "aa1=%d", (w >> 14) & 0x3);
13730 + vp++;
13731 +
13732 + /* Words 47-49 set the (wl) pa settings */
13733 + woff = 47;
13734 +
13735 + for (i = 0; i < 3; i++) {
13736 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
13737 + vp++;
13738 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
13739 + vp++;
13740 + }
13741 +
13742 + /*
13743 + * Words 50-51 set the customer-configured wl led behavior.
13744 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
13745 + * LED behavior values defined in wlioctl.h .
13746 + */
13747 + w = b[50];
13748 + if ((w != 0) && (w != 0xffff)) {
13749 + /* gpio0 */
13750 + vp += sprintf(vp, "wl0gpio0=%d", (w & 0xff));
13751 + vp++;
13752 +
13753 + /* gpio1 */
13754 + vp += sprintf(vp, "wl0gpio1=%d", (w >> 8) & 0xff);
13755 + vp++;
13756 + }
13757 + w = b[51];
13758 + if ((w != 0) && (w != 0xffff)) {
13759 + /* gpio2 */
13760 + vp += sprintf(vp, "wl0gpio2=%d", w & 0xff);
13761 + vp++;
13762 +
13763 + /* gpio3 */
13764 + vp += sprintf(vp, "wl0gpio3=%d", (w >> 8) & 0xff);
13765 + vp++;
13766 + }
13767 +
13768 + /* Word 52 is max power 0/1 */
13769 + w = b[52];
13770 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
13771 + vp++;
13772 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
13773 + vp++;
13774 +
13775 + /* Word 56 is idle tssi target 0/1 */
13776 + w = b[56];
13777 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
13778 + vp++;
13779 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
13780 + vp++;
13781 +
13782 + /* Word 57 is boardflags, if not programmed make it zero */
13783 + bfl = (uint32)b[57];
13784 + if (bfl == 0xffff) bfl = 0;
13785 + if (sromrev > 1) {
13786 + /* Word 28 is boardflags2 */
13787 + bfl |= (uint32)b[28] << 16;
13788 + }
13789 + vp += sprintf(vp, "boardflags=%d", bfl);
13790 + vp++;
13791 +
13792 + /* Word 58 is antenna gain 0/1 */
13793 + w = b[58];
13794 + vp += sprintf(vp, "ag0=%d", w & 0xff);
13795 + vp++;
13796 +
13797 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
13798 + vp++;
13799 +
13800 + if (sromrev == 1) {
13801 + /* set the oem string */
13802 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
13803 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
13804 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
13805 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
13806 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
13807 + vp++;
13808 + } else {
13809 + /* Word 60 OFDM tx power offset from CCK level */
13810 + /* OFDM Power Offset - opo */
13811 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
13812 + vp++;
13813 + }
13814 +
13815 + /* final nullbyte terminator */
13816 + *vp++ = '\0';
13817 +
13818 + c = (int)(vp - base);
13819 + ASSERT((vp - base) <= VARS_MAX);
13820 +
13821 + if (c == VARS_MAX) {
13822 + *vars = base;
13823 + } else {
13824 + vp = MALLOC(osh, c);
13825 + ASSERT(vp);
13826 + bcopy(base, vp, c);
13827 + MFREE(osh, base, VARS_MAX);
13828 + *vars = vp;
13829 + }
13830 + *count = c;
13831 +
13832 + return (0);
13833 +}
13834 +
13835 +/*
13836 + * Read the cis and call parsecis to initialize the vars.
13837 + * Return 0 on success, nonzero on error.
13838 + */
13839 +static int
13840 +initvars_cis_pcmcia(void *sbh, void *curmap, void *osh, char **vars, int *count)
13841 +{
13842 + uint8 *cis = NULL;
13843 + int rc;
13844 + uint data_sz;
13845 +
13846 + data_sz = (sb_pcmciarev(sbh) == 1) ? (SPROM_SIZE * 2) : CIS_SIZE;
13847 +
13848 + if ((cis = MALLOC(osh, data_sz)) == NULL)
13849 + return (-2);
13850 +
13851 + if (sb_pcmciarev(sbh) == 1) {
13852 + if (srom_read(PCMCIA_BUS, (void *)NULL, osh, 0, data_sz, (uint16 *)cis)) {
13853 + MFREE(osh, cis, data_sz);
13854 + return (-1);
13855 + }
13856 + /* fix up endianess for 16-bit data vs 8-bit parsing */
13857 + ltoh16_buf((uint16 *)cis, data_sz);
13858 + } else
13859 + OSL_PCMCIA_READ_ATTR(osh, 0, cis, data_sz);
13860 +
13861 + rc = srom_parsecis(osh, cis, vars, count);
13862 +
13863 + MFREE(osh, cis, data_sz);
13864 +
13865 + return (rc);
13866 +}
13867 +
13868 diff -Nur linux-2.4.30/drivers/net/hnd/bcmutils.c linux-2.4.30-brcm/drivers/net/hnd/bcmutils.c
13869 --- linux-2.4.30/drivers/net/hnd/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
13870 +++ linux-2.4.30-brcm/drivers/net/hnd/bcmutils.c 2005-05-24 20:26:25.000000000 +0200
13871 @@ -0,0 +1,862 @@
13872 +/*
13873 + * Misc useful OS-independent routines.
13874 + *
13875 + * Copyright 2004, Broadcom Corporation
13876 + * All Rights Reserved.
13877 + *
13878 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
13879 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13880 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
13881 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
13882 + * $Id$
13883 + */
13884 +
13885 +#include <typedefs.h>
13886 +#include <osl.h>
13887 +#include <bcmnvram.h>
13888 +#include <bcmutils.h>
13889 +#include <bcmendian.h>
13890 +#include <bcmdevs.h>
13891 +
13892 +#ifdef BCMDRIVER
13893 +/* copy a pkt buffer chain into a buffer */
13894 +uint
13895 +pktcopy(void *drv, void *p, uint offset, int len, uchar *buf)
13896 +{
13897 + uint n, ret = 0;
13898 +
13899 + if (len < 0)
13900 + len = 4096; /* "infinite" */
13901 +
13902 + /* skip 'offset' bytes */
13903 + for (; p && offset; p = PKTNEXT(drv, p)) {
13904 + if (offset < (uint)PKTLEN(drv, p))
13905 + break;
13906 + offset -= PKTLEN(drv, p);
13907 + }
13908 +
13909 + if (!p)
13910 + return 0;
13911 +
13912 + /* copy the data */
13913 + for (; p && len; p = PKTNEXT(drv, p)) {
13914 + n = MIN((uint)PKTLEN(drv, p) - offset, (uint)len);
13915 + bcopy(PKTDATA(drv, p) + offset, buf, n);
13916 + buf += n;
13917 + len -= n;
13918 + ret += n;
13919 + offset = 0;
13920 + }
13921 +
13922 + return ret;
13923 +}
13924 +
13925 +/* return total length of buffer chain */
13926 +uint
13927 +pkttotlen(void *drv, void *p)
13928 +{
13929 + uint total;
13930 +
13931 + total = 0;
13932 + for (; p; p = PKTNEXT(drv, p))
13933 + total += PKTLEN(drv, p);
13934 + return (total);
13935 +}
13936 +
13937 +void
13938 +pktq_init(struct pktq *q, uint maxlen, const bool prio_map[])
13939 +{
13940 + q->head = q->tail = NULL;
13941 + q->maxlen = maxlen;
13942 + q->len = 0;
13943 + if (prio_map) {
13944 + q->priority = TRUE;
13945 + bcopy(prio_map, q->prio_map, sizeof(q->prio_map));
13946 + }
13947 + else
13948 + q->priority = FALSE;
13949 +}
13950 +
13951 +/* should always check pktq_full before calling pktenq */
13952 +void
13953 +pktenq(struct pktq *q, void *p, bool lifo)
13954 +{
13955 + void *next, *prev;
13956 +
13957 + /* allow 10 pkts slack */
13958 + ASSERT(q->len < (q->maxlen + 10));
13959 +
13960 + /* Queueing chains not allowed */
13961 + ASSERT(PKTLINK(p) == NULL);
13962 +
13963 + /* Queue is empty */
13964 + if (q->tail == NULL) {
13965 + ASSERT(q->head == NULL);
13966 + q->head = q->tail = p;
13967 + }
13968 +
13969 + /* Insert at head or tail */
13970 + else if (q->priority == FALSE) {
13971 + /* Insert at head (LIFO) */
13972 + if (lifo) {
13973 + PKTSETLINK(p, q->head);
13974 + q->head = p;
13975 + }
13976 + /* Insert at tail (FIFO) */
13977 + else {
13978 + ASSERT(PKTLINK(q->tail) == NULL);
13979 + PKTSETLINK(q->tail, p);
13980 + PKTSETLINK(p, NULL);
13981 + q->tail = p;
13982 + }
13983 + }
13984 +
13985 + /* Insert by priority */
13986 + else {
13987 + /* legal priorities 0-7 */
13988 + ASSERT(PKTPRIO(p) <= MAXPRIO);
13989 +
13990 + ASSERT(q->head);
13991 + ASSERT(q->tail);
13992 + /* Shortcut to insertion at tail */
13993 + if (_pktq_pri(q, PKTPRIO(p)) < _pktq_pri(q, PKTPRIO(q->tail)) ||
13994 + (!lifo && _pktq_pri(q, PKTPRIO(p)) <= _pktq_pri(q, PKTPRIO(q->tail)))) {
13995 + prev = q->tail;
13996 + next = NULL;
13997 + }
13998 + /* Insert at head or in the middle */
13999 + else {
14000 + prev = NULL;
14001 + next = q->head;
14002 + }
14003 + /* Walk the queue */
14004 + for (; next; prev = next, next = PKTLINK(next)) {
14005 + /* Priority queue invariant */
14006 + ASSERT(!prev || _pktq_pri(q, PKTPRIO(prev)) >= _pktq_pri(q, PKTPRIO(next)));
14007 + /* Insert at head of string of packets of same priority (LIFO) */
14008 + if (lifo) {
14009 + if (_pktq_pri(q, PKTPRIO(p)) >= _pktq_pri(q, PKTPRIO(next)))
14010 + break;
14011 + }
14012 + /* Insert at tail of string of packets of same priority (FIFO) */
14013 + else {
14014 + if (_pktq_pri(q, PKTPRIO(p)) > _pktq_pri(q, PKTPRIO(next)))
14015 + break;
14016 + }
14017 + }
14018 + /* Insert at tail */
14019 + if (next == NULL) {
14020 + ASSERT(PKTLINK(q->tail) == NULL);
14021 + PKTSETLINK(q->tail, p);
14022 + PKTSETLINK(p, NULL);
14023 + q->tail = p;
14024 + }
14025 + /* Insert in the middle */
14026 + else if (prev) {
14027 + PKTSETLINK(prev, p);
14028 + PKTSETLINK(p, next);
14029 + }
14030 + /* Insert at head */
14031 + else {
14032 + PKTSETLINK(p, q->head);
14033 + q->head = p;
14034 + }
14035 + }
14036 +
14037 + /* List invariants after insertion */
14038 + ASSERT(q->head);
14039 + ASSERT(PKTLINK(q->tail) == NULL);
14040 +
14041 + q->len++;
14042 +}
14043 +
14044 +/* dequeue packet at head */
14045 +void*
14046 +pktdeq(struct pktq *q)
14047 +{
14048 + void *p;
14049 +
14050 + if ((p = q->head)) {
14051 + ASSERT(q->tail);
14052 + q->head = PKTLINK(p);
14053 + PKTSETLINK(p, NULL);
14054 + q->len--;
14055 + if (q->head == NULL)
14056 + q->tail = NULL;
14057 + }
14058 + else {
14059 + ASSERT(q->tail == NULL);
14060 + }
14061 +
14062 + return (p);
14063 +}
14064 +
14065 +/* dequeue packet at tail */
14066 +void*
14067 +pktdeqtail(struct pktq *q)
14068 +{
14069 + void *p;
14070 + void *next, *prev;
14071 +
14072 + if (q->head == q->tail) { /* last packet on queue or queue empty */
14073 + p = q->head;
14074 + q->head = q->tail = NULL;
14075 + q->len = 0;
14076 + return(p);
14077 + }
14078 +
14079 + /* start walk at head */
14080 + prev = NULL;
14081 + next = q->head;
14082 +
14083 + /* Walk the queue to find prev of q->tail */
14084 + for (; next; prev = next, next = PKTLINK(next)) {
14085 + if (next == q->tail)
14086 + break;
14087 + }
14088 +
14089 + ASSERT(prev);
14090 +
14091 + PKTSETLINK(prev, NULL);
14092 + q->tail = prev;
14093 + q->len--;
14094 + p = next;
14095 +
14096 + return (p);
14097 +}
14098 +
14099 +unsigned char bcm_ctype[] = {
14100 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
14101 + _BCM_C,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C,_BCM_C, /* 8-15 */
14102 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
14103 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
14104 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
14105 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
14106 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
14107 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
14108 + _BCM_P,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U, /* 64-71 */
14109 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
14110 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
14111 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
14112 + _BCM_P,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L, /* 96-103 */
14113 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
14114 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
14115 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
14116 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
14117 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
14118 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 160-175 */
14119 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 176-191 */
14120 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 192-207 */
14121 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_L, /* 208-223 */
14122 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 224-239 */
14123 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L /* 240-255 */
14124 +};
14125 +
14126 +uchar
14127 +bcm_toupper(uchar c)
14128 +{
14129 + if (bcm_islower(c))
14130 + c -= 'a'-'A';
14131 + return (c);
14132 +}
14133 +
14134 +ulong
14135 +bcm_strtoul(char *cp, char **endp, uint base)
14136 +{
14137 + ulong result, value;
14138 + bool minus;
14139 +
14140 + minus = FALSE;
14141 +
14142 + while (bcm_isspace(*cp))
14143 + cp++;
14144 +
14145 + if (cp[0] == '+')
14146 + cp++;
14147 + else if (cp[0] == '-') {
14148 + minus = TRUE;
14149 + cp++;
14150 + }
14151 +
14152 + if (base == 0) {
14153 + if (cp[0] == '0') {
14154 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
14155 + base = 16;
14156 + cp = &cp[2];
14157 + } else {
14158 + base = 8;
14159 + cp = &cp[1];
14160 + }
14161 + } else
14162 + base = 10;
14163 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
14164 + cp = &cp[2];
14165 + }
14166 +
14167 + result = 0;
14168 +
14169 + while (bcm_isxdigit(*cp) &&
14170 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
14171 + result = result*base + value;
14172 + cp++;
14173 + }
14174 +
14175 + if (minus)
14176 + result = (ulong)(result * -1);
14177 +
14178 + if (endp)
14179 + *endp = (char *)cp;
14180 +
14181 + return (result);
14182 +}
14183 +
14184 +uint
14185 +bcm_atoi(char *s)
14186 +{
14187 + uint n;
14188 +
14189 + n = 0;
14190 +
14191 + while (bcm_isdigit(*s))
14192 + n = (n * 10) + *s++ - '0';
14193 + return (n);
14194 +}
14195 +
14196 +/* return pointer to location of substring 'needle' in 'haystack' */
14197 +char*
14198 +bcmstrstr(char *haystack, char *needle)
14199 +{
14200 + int len, nlen;
14201 + int i;
14202 +
14203 + if ((haystack == NULL) || (needle == NULL))
14204 + return (haystack);
14205 +
14206 + nlen = strlen(needle);
14207 + len = strlen(haystack) - nlen + 1;
14208 +
14209 + for (i = 0; i < len; i++)
14210 + if (bcmp(needle, &haystack[i], nlen) == 0)
14211 + return (&haystack[i]);
14212 + return (NULL);
14213 +}
14214 +
14215 +char*
14216 +bcmstrcat(char *dest, const char *src)
14217 +{
14218 + strcpy(&dest[strlen(dest)], src);
14219 + return (dest);
14220 +}
14221 +
14222 +#if defined(CONFIG_USBRNDIS_RETAIL) || defined(NDIS_MINIPORT_DRIVER)
14223 +/* registry routine buffer preparation utility functions:
14224 + * parameter order is like strncpy, but returns count
14225 + * of bytes copied. Minimum bytes copied is null char(1)/wchar(2)
14226 + */
14227 +ulong
14228 +wchar2ascii(
14229 + char *abuf,
14230 + ushort *wbuf,
14231 + ushort wbuflen,
14232 + ulong abuflen
14233 +)
14234 +{
14235 + ulong copyct = 1;
14236 + ushort i;
14237 +
14238 + if (abuflen == 0)
14239 + return 0;
14240 +
14241 + /* wbuflen is in bytes */
14242 + wbuflen /= sizeof(ushort);
14243 +
14244 + for (i = 0; i < wbuflen; ++i) {
14245 + if (--abuflen == 0)
14246 + break;
14247 + *abuf++ = (char) *wbuf++;
14248 + ++copyct;
14249 + }
14250 + *abuf = '\0';
14251 +
14252 + return copyct;
14253 +}
14254 +#endif
14255 +
14256 +char*
14257 +bcm_ether_ntoa(char *ea, char *buf)
14258 +{
14259 + sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
14260 + (uchar)ea[0]&0xff, (uchar)ea[1]&0xff, (uchar)ea[2]&0xff,
14261 + (uchar)ea[3]&0xff, (uchar)ea[4]&0xff, (uchar)ea[5]&0xff);
14262 + return (buf);
14263 +}
14264 +
14265 +/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
14266 +int
14267 +bcm_ether_atoe(char *p, char *ea)
14268 +{
14269 + int i = 0;
14270 +
14271 + for (;;) {
14272 + ea[i++] = (char) bcm_strtoul(p, &p, 16);
14273 + if (!*p++ || i == 6)
14274 + break;
14275 + }
14276 +
14277 + return (i == 6);
14278 +}
14279 +
14280 +void
14281 +bcm_mdelay(uint ms)
14282 +{
14283 + uint i;
14284 +
14285 + for (i = 0; i < ms; i++) {
14286 + OSL_DELAY(1000);
14287 + }
14288 +}
14289 +
14290 +/*
14291 + * Search the name=value vars for a specific one and return its value.
14292 + * Returns NULL if not found.
14293 + */
14294 +char*
14295 +getvar(char *vars, char *name)
14296 +{
14297 + char *s;
14298 + int len;
14299 +
14300 + len = strlen(name);
14301 +
14302 + /* first look in vars[] */
14303 + for (s = vars; s && *s; ) {
14304 + if ((bcmp(s, name, len) == 0) && (s[len] == '='))
14305 + return (&s[len+1]);
14306 +
14307 + while (*s++)
14308 + ;
14309 + }
14310 +
14311 + /* then query nvram */
14312 + return (BCMINIT(nvram_get)(name));
14313 +}
14314 +
14315 +/*
14316 + * Search the vars for a specific one and return its value as
14317 + * an integer. Returns 0 if not found.
14318 + */
14319 +int
14320 +getintvar(char *vars, char *name)
14321 +{
14322 + char *val;
14323 +
14324 + if ((val = getvar(vars, name)) == NULL)
14325 + return (0);
14326 +
14327 + return (bcm_strtoul(val, NULL, 0));
14328 +}
14329 +
14330 +/* Return gpio pin number assigned to the named pin */
14331 +/*
14332 +* Variable should be in format:
14333 +*
14334 +* gpio<N>=pin_name
14335 +*
14336 +* 'def_pin' is returned if there is no such variable found.
14337 +*/
14338 +uint
14339 +getgpiopin(char *vars, char *pin_name, uint def_pin)
14340 +{
14341 + char name[] = "gpioXXXX";
14342 + char *val;
14343 + uint pin;
14344 +
14345 + /* Go thru all possibilities till a match in pin name */
14346 + for (pin = 0; pin < GPIO_NUMPINS; pin ++) {
14347 + sprintf(name, "gpio%d", pin);
14348 + val = getvar(vars, name);
14349 + if (val && !strcmp(val, pin_name))
14350 + return pin;
14351 + }
14352 + return def_pin;
14353 +}
14354 +
14355 +#endif /* #ifdef BCMDRIVER */
14356 +
14357 +/*******************************************************************************
14358 + * crc8
14359 + *
14360 + * Computes a crc8 over the input data using the polynomial:
14361 + *
14362 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
14363 + *
14364 + * The caller provides the initial value (either CRC8_INIT_VALUE
14365 + * or the previous returned value) to allow for processing of
14366 + * discontiguous blocks of data. When generating the CRC the
14367 + * caller is responsible for complementing the final return value
14368 + * and inserting it into the byte stream. When checking, a final
14369 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
14370 + *
14371 + * Reference: Dallas Semiconductor Application Note 27
14372 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
14373 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
14374 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
14375 + *
14376 + ******************************************************************************/
14377 +
14378 +static uint8 crc8_table[256] = {
14379 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
14380 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
14381 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
14382 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
14383 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
14384 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
14385 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
14386 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
14387 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
14388 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
14389 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
14390 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
14391 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
14392 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
14393 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
14394 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
14395 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
14396 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
14397 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
14398 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
14399 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
14400 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
14401 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
14402 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
14403 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
14404 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
14405 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
14406 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
14407 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
14408 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
14409 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
14410 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
14411 +};
14412 +
14413 +#define CRC_INNER_LOOP(n, c, x) \
14414 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
14415 +
14416 +uint8
14417 +hndcrc8(
14418 + uint8 *pdata, /* pointer to array of data to process */
14419 + uint nbytes, /* number of input data bytes to process */
14420 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
14421 +)
14422 +{
14423 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
14424 + * to avoid the undefined and unnecessary (uint8 >> 8) operation. */
14425 + while (nbytes-- > 0)
14426 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
14427 +
14428 + return crc;
14429 +}
14430 +
14431 +/*******************************************************************************
14432 + * crc16
14433 + *
14434 + * Computes a crc16 over the input data using the polynomial:
14435 + *
14436 + * x^16 + x^12 +x^5 + 1
14437 + *
14438 + * The caller provides the initial value (either CRC16_INIT_VALUE
14439 + * or the previous returned value) to allow for processing of
14440 + * discontiguous blocks of data. When generating the CRC the
14441 + * caller is responsible for complementing the final return value
14442 + * and inserting it into the byte stream. When checking, a final
14443 + * return value of CRC16_GOOD_VALUE indicates a valid CRC.
14444 + *
14445 + * Reference: Dallas Semiconductor Application Note 27
14446 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
14447 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
14448 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
14449 + *
14450 + ******************************************************************************/
14451 +
14452 +static uint16 crc16_table[256] = {
14453 + 0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF,
14454 + 0x8C48, 0x9DC1, 0xAF5A, 0xBED3, 0xCA6C, 0xDBE5, 0xE97E, 0xF8F7,
14455 + 0x1081, 0x0108, 0x3393, 0x221A, 0x56A5, 0x472C, 0x75B7, 0x643E,
14456 + 0x9CC9, 0x8D40, 0xBFDB, 0xAE52, 0xDAED, 0xCB64, 0xF9FF, 0xE876,
14457 + 0x2102, 0x308B, 0x0210, 0x1399, 0x6726, 0x76AF, 0x4434, 0x55BD,
14458 + 0xAD4A, 0xBCC3, 0x8E58, 0x9FD1, 0xEB6E, 0xFAE7, 0xC87C, 0xD9F5,
14459 + 0x3183, 0x200A, 0x1291, 0x0318, 0x77A7, 0x662E, 0x54B5, 0x453C,
14460 + 0xBDCB, 0xAC42, 0x9ED9, 0x8F50, 0xFBEF, 0xEA66, 0xD8FD, 0xC974,
14461 + 0x4204, 0x538D, 0x6116, 0x709F, 0x0420, 0x15A9, 0x2732, 0x36BB,
14462 + 0xCE4C, 0xDFC5, 0xED5E, 0xFCD7, 0x8868, 0x99E1, 0xAB7A, 0xBAF3,
14463 + 0x5285, 0x430C, 0x7197, 0x601E, 0x14A1, 0x0528, 0x37B3, 0x263A,
14464 + 0xDECD, 0xCF44, 0xFDDF, 0xEC56, 0x98E9, 0x8960, 0xBBFB, 0xAA72,
14465 + 0x6306, 0x728F, 0x4014, 0x519D, 0x2522, 0x34AB, 0x0630, 0x17B9,
14466 + 0xEF4E, 0xFEC7, 0xCC5C, 0xDDD5, 0xA96A, 0xB8E3, 0x8A78, 0x9BF1,
14467 + 0x7387, 0x620E, 0x5095, 0x411C, 0x35A3, 0x242A, 0x16B1, 0x0738,
14468 + 0xFFCF, 0xEE46, 0xDCDD, 0xCD54, 0xB9EB, 0xA862, 0x9AF9, 0x8B70,
14469 + 0x8408, 0x9581, 0xA71A, 0xB693, 0xC22C, 0xD3A5, 0xE13E, 0xF0B7,
14470 + 0x0840, 0x19C9, 0x2B52, 0x3ADB, 0x4E64, 0x5FED, 0x6D76, 0x7CFF,
14471 + 0x9489, 0x8500, 0xB79B, 0xA612, 0xD2AD, 0xC324, 0xF1BF, 0xE036,
14472 + 0x18C1, 0x0948, 0x3BD3, 0x2A5A, 0x5EE5, 0x4F6C, 0x7DF7, 0x6C7E,
14473 + 0xA50A, 0xB483, 0x8618, 0x9791, 0xE32E, 0xF2A7, 0xC03C, 0xD1B5,
14474 + 0x2942, 0x38CB, 0x0A50, 0x1BD9, 0x6F66, 0x7EEF, 0x4C74, 0x5DFD,
14475 + 0xB58B, 0xA402, 0x9699, 0x8710, 0xF3AF, 0xE226, 0xD0BD, 0xC134,
14476 + 0x39C3, 0x284A, 0x1AD1, 0x0B58, 0x7FE7, 0x6E6E, 0x5CF5, 0x4D7C,
14477 + 0xC60C, 0xD785, 0xE51E, 0xF497, 0x8028, 0x91A1, 0xA33A, 0xB2B3,
14478 + 0x4A44, 0x5BCD, 0x6956, 0x78DF, 0x0C60, 0x1DE9, 0x2F72, 0x3EFB,
14479 + 0xD68D, 0xC704, 0xF59F, 0xE416, 0x90A9, 0x8120, 0xB3BB, 0xA232,
14480 + 0x5AC5, 0x4B4C, 0x79D7, 0x685E, 0x1CE1, 0x0D68, 0x3FF3, 0x2E7A,
14481 + 0xE70E, 0xF687, 0xC41C, 0xD595, 0xA12A, 0xB0A3, 0x8238, 0x93B1,
14482 + 0x6B46, 0x7ACF, 0x4854, 0x59DD, 0x2D62, 0x3CEB, 0x0E70, 0x1FF9,
14483 + 0xF78F, 0xE606, 0xD49D, 0xC514, 0xB1AB, 0xA022, 0x92B9, 0x8330,
14484 + 0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78
14485 +};
14486 +
14487 +uint16
14488 +hndcrc16(
14489 + uint8 *pdata, /* pointer to array of data to process */
14490 + uint nbytes, /* number of input data bytes to process */
14491 + uint16 crc /* either CRC16_INIT_VALUE or previous return value */
14492 +)
14493 +{
14494 + while (nbytes-- > 0)
14495 + CRC_INNER_LOOP(16, crc, *pdata++);
14496 + return crc;
14497 +}
14498 +
14499 +static uint32 crc32_table[256] = {
14500 + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
14501 + 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
14502 + 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
14503 + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
14504 + 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
14505 + 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
14506 + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
14507 + 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
14508 + 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
14509 + 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
14510 + 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
14511 + 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
14512 + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
14513 + 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
14514 + 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
14515 + 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
14516 + 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
14517 + 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
14518 + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
14519 + 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
14520 + 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
14521 + 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
14522 + 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
14523 + 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
14524 + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
14525 + 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
14526 + 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
14527 + 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
14528 + 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
14529 + 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
14530 + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
14531 + 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
14532 + 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
14533 + 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
14534 + 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
14535 + 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
14536 + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
14537 + 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
14538 + 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
14539 + 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
14540 + 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
14541 + 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
14542 + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
14543 + 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
14544 + 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
14545 + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
14546 + 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04,
14547 + 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
14548 + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
14549 + 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
14550 + 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
14551 + 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
14552 + 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
14553 + 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
14554 + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
14555 + 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
14556 + 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
14557 + 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
14558 + 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
14559 + 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
14560 + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
14561 + 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
14562 + 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
14563 + 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
14564 +};
14565 +
14566 +uint32
14567 +hndcrc32(
14568 + uint8 *pdata, /* pointer to array of data to process */
14569 + uint nbytes, /* number of input data bytes to process */
14570 + uint32 crc /* either CRC32_INIT_VALUE or previous return value */
14571 +)
14572 +{
14573 + uint8 *pend;
14574 +#ifdef __mips__
14575 + uint8 tmp[4];
14576 + ulong *tptr = (ulong *)tmp;
14577 +
14578 + /* in case the beginning of the buffer isn't aligned */
14579 + pend = (uint8 *)((uint)(pdata + 3) & 0xfffffffc);
14580 + nbytes -= (pend - pdata);
14581 + while (pdata < pend)
14582 + CRC_INNER_LOOP(32, crc, *pdata++);
14583 +
14584 + /* handle bulk of data as 32-bit words */
14585 + pend = pdata + (nbytes & 0xfffffffc);
14586 + while (pdata < pend) {
14587 + *tptr = *((ulong *)pdata)++;
14588 + CRC_INNER_LOOP(32, crc, tmp[0]);
14589 + CRC_INNER_LOOP(32, crc, tmp[1]);
14590 + CRC_INNER_LOOP(32, crc, tmp[2]);
14591 + CRC_INNER_LOOP(32, crc, tmp[3]);
14592 + }
14593 +
14594 + /* 1-3 bytes at end of buffer */
14595 + pend = pdata + (nbytes & 0x03);
14596 + while (pdata < pend)
14597 + CRC_INNER_LOOP(32, crc, *pdata++);
14598 +#else
14599 + pend = pdata + nbytes;
14600 + while (pdata < pend)
14601 + CRC_INNER_LOOP(32, crc, *pdata++);
14602 +#endif
14603 +
14604 + return crc;
14605 +}
14606 +
14607 +#ifdef notdef
14608 +#define CLEN 1499
14609 +#define CBUFSIZ (CLEN+4)
14610 +#define CNBUFS 5
14611 +
14612 +void testcrc32(void)
14613 +{
14614 + uint j,k,l;
14615 + uint8 *buf;
14616 + uint len[CNBUFS];
14617 + uint32 crcr;
14618 + uint32 crc32tv[CNBUFS] =
14619 + {0xd2cb1faa, 0xd385c8fa, 0xf5b4f3f3, 0x55789e20, 0x00343110};
14620 +
14621 + ASSERT((buf = MALLOC(CBUFSIZ*CNBUFS)) != NULL);
14622 +
14623 + /* step through all possible alignments */
14624 + for (l=0;l<=4;l++) {
14625 + for (j=0; j<CNBUFS; j++) {
14626 + len[j] = CLEN;
14627 + for (k=0; k<len[j]; k++)
14628 + *(buf + j*CBUFSIZ + (k+l)) = (j+k) & 0xff;
14629 + }
14630 +
14631 + for (j=0; j<CNBUFS; j++) {
14632 + crcr = crc32(buf + j*CBUFSIZ + l, len[j], CRC32_INIT_VALUE);
14633 + ASSERT(crcr == crc32tv[j]);
14634 + }
14635 + }
14636 +
14637 + MFREE(buf, CBUFSIZ*CNBUFS);
14638 + return;
14639 +}
14640 +#endif
14641 +
14642 +
14643 +/*
14644 + * Advance from the current 1-byte tag/1-byte length/variable-length value
14645 + * triple, to the next, returning a pointer to the next.
14646 + */
14647 +bcm_tlv_t *
14648 +bcm_next_tlv(bcm_tlv_t *elt, int *buflen)
14649 +{
14650 + int len;
14651 +
14652 + /* validate current elt */
14653 + if (*buflen < 2) {
14654 + return NULL;
14655 + }
14656 +
14657 + len = elt->len;
14658 +
14659 + /* validate remaining buflen */
14660 + if (*buflen >= (2 + len + 2)) {
14661 + elt = (bcm_tlv_t*)(elt->data + len);
14662 + *buflen -= (2 + len);
14663 + } else {
14664 + elt = NULL;
14665 + }
14666 +
14667 + return elt;
14668 +}
14669 +
14670 +/*
14671 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
14672 + * triples, returning a pointer to the substring whose first element
14673 + * matches tag
14674 + */
14675 +bcm_tlv_t *
14676 +bcm_parse_tlvs(void *buf, int buflen, uint key)
14677 +{
14678 + bcm_tlv_t *elt;
14679 + int totlen;
14680 +
14681 + elt = (bcm_tlv_t*)buf;
14682 + totlen = buflen;
14683 +
14684 + /* find tagged parameter */
14685 + while (totlen >= 2) {
14686 + int len = elt->len;
14687 +
14688 + /* validate remaining totlen */
14689 + if ((elt->id == key) && (totlen >= (len + 2)))
14690 + return (elt);
14691 +
14692 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
14693 + totlen -= (len + 2);
14694 + }
14695 +
14696 + return NULL;
14697 +}
14698 +
14699 +/*
14700 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
14701 + * triples, returning a pointer to the substring whose first element
14702 + * matches tag. Stop parsing when we see an element whose ID is greater
14703 + * than the target key.
14704 + */
14705 +bcm_tlv_t *
14706 +bcm_parse_ordered_tlvs(void *buf, int buflen, uint key)
14707 +{
14708 + bcm_tlv_t *elt;
14709 + int totlen;
14710 +
14711 + elt = (bcm_tlv_t*)buf;
14712 + totlen = buflen;
14713 +
14714 + /* find tagged parameter */
14715 + while (totlen >= 2) {
14716 + uint id = elt->id;
14717 + int len = elt->len;
14718 +
14719 + /* Punt if we start seeing IDs > than target key */
14720 + if (id > key)
14721 + return(NULL);
14722 +
14723 + /* validate remaining totlen */
14724 + if ((id == key) && (totlen >= (len + 2)))
14725 + return (elt);
14726 +
14727 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
14728 + totlen -= (len + 2);
14729 + }
14730 + return NULL;
14731 +}
14732 +
14733 +
14734 diff -Nur linux-2.4.30/drivers/net/hnd/hnddma.c linux-2.4.30-brcm/drivers/net/hnd/hnddma.c
14735 --- linux-2.4.30/drivers/net/hnd/hnddma.c 1970-01-01 01:00:00.000000000 +0100
14736 +++ linux-2.4.30-brcm/drivers/net/hnd/hnddma.c 2005-05-25 01:12:49.000000000 +0200
14737 @@ -0,0 +1,865 @@
14738 +/*
14739 + * Generic Broadcom Home Networking Division (HND) DMA module.
14740 + * This supports the following chips: BCM42xx, 44xx, 47xx .
14741 + *
14742 + * Copyright 2004, Broadcom Corporation
14743 + * All Rights Reserved.
14744 + *
14745 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
14746 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
14747 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14748 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
14749 + *
14750 + * $Id$
14751 + */
14752 +
14753 +#include <typedefs.h>
14754 +#include <osl.h>
14755 +#include <bcmendian.h>
14756 +#include <sbconfig.h>
14757 +#include <bcmutils.h>
14758 +
14759 +struct dma_info; /* forward declaration */
14760 +#define di_t struct dma_info
14761 +#include <hnddma.h>
14762 +
14763 +/* debug/trace */
14764 +#define DMA_ERROR(args)
14765 +#define DMA_TRACE(args)
14766 +
14767 +/* default dma message level(if input msg_level pointer is null in dma_attach()) */
14768 +static uint dma_msg_level = 0;
14769 +
14770 +#define MAXNAMEL 8
14771 +#define MAXDD (DMAMAXRINGSZ / sizeof (dmadd_t))
14772 +
14773 +/* dma engine software state */
14774 +typedef struct dma_info {
14775 + hnddma_t hnddma; /* exported structure */
14776 + uint *msg_level; /* message level pointer */
14777 +
14778 + char name[MAXNAMEL]; /* callers name for diag msgs */
14779 + void *drv; /* driver handle */
14780 + void *osh; /* os handle */
14781 + dmaregs_t *regs; /* dma engine registers */
14782 +
14783 + dmadd_t *txd; /* pointer to chip-specific tx descriptor ring */
14784 + uint txin; /* index of next descriptor to reclaim */
14785 + uint txout; /* index of next descriptor to post */
14786 + uint txavail; /* # free tx descriptors */
14787 + void **txp; /* pointer to parallel array of pointers to packets */
14788 + ulong txdpa; /* physical address of descriptor ring */
14789 + uint txdalign; /* #bytes added to alloc'd mem to align txd */
14790 + uint txdalloc; /* #bytes allocated for the ring */
14791 +
14792 + dmadd_t *rxd; /* pointer to chip-specific rx descriptor ring */
14793 + uint rxin; /* index of next descriptor to reclaim */
14794 + uint rxout; /* index of next descriptor to post */
14795 + void **rxp; /* pointer to parallel array of pointers to packets */
14796 + ulong rxdpa; /* physical address of descriptor ring */
14797 + uint rxdalign; /* #bytes added to alloc'd mem to align rxd */
14798 + uint rxdalloc; /* #bytes allocated for the ring */
14799 +
14800 + /* tunables */
14801 + uint ntxd; /* # tx descriptors */
14802 + uint nrxd; /* # rx descriptors */
14803 + uint rxbufsize; /* rx buffer size in bytes */
14804 + uint nrxpost; /* # rx buffers to keep posted */
14805 + uint rxoffset; /* rxcontrol offset */
14806 + uint ddoffset; /* add to get dma address of descriptor ring */
14807 + uint dataoffset; /* add to get dma address of data buffer */
14808 +} dma_info_t;
14809 +
14810 +/* descriptor bumping macros */
14811 +#define XXD(x, n) ((x) & ((n) - 1))
14812 +#define TXD(x) XXD((x), di->ntxd)
14813 +#define RXD(x) XXD((x), di->nrxd)
14814 +#define NEXTTXD(i) TXD(i + 1)
14815 +#define PREVTXD(i) TXD(i - 1)
14816 +#define NEXTRXD(i) RXD(i + 1)
14817 +#define NTXDACTIVE(h, t) TXD(t - h)
14818 +#define NRXDACTIVE(h, t) RXD(t - h)
14819 +
14820 +/* macros to convert between byte offsets and indexes */
14821 +#define B2I(bytes) ((bytes) / sizeof (dmadd_t))
14822 +#define I2B(index) ((index) * sizeof (dmadd_t))
14823 +
14824 +/*
14825 + * This assume the largest i/o address is, in fact, the pci big window
14826 + * and that the pci core sb2pcitranslation2 register has been left with
14827 + * the default 0x0 pci base address.
14828 + */
14829 +#define MAXDMAADDR SB_PCI_DMA_SZ
14830 +#define DMA_ADDRESSABLE(x) !((x) & ~(MAXDMAADDR - 1))
14831 +
14832 +/* prototypes */
14833 +
14834 +void*
14835 +dma_attach(void *drv, void *osh, char *name, dmaregs_t *regs, uint ntxd, uint nrxd,
14836 + uint rxbufsize, uint nrxpost, uint rxoffset, uint ddoffset, uint dataoffset, uint *msg_level)
14837 +{
14838 + dma_info_t *di;
14839 + uint size;
14840 + void *va;
14841 +
14842 + ASSERT(ntxd <= MAXDD);
14843 + ASSERT(ISPOWEROF2(ntxd));
14844 + ASSERT(nrxd <= MAXDD);
14845 + ASSERT(ISPOWEROF2(nrxd));
14846 +
14847 + /* allocate private info structure */
14848 + if ((di = MALLOC(osh, sizeof (dma_info_t))) == NULL) {
14849 + return (NULL);
14850 + }
14851 + bzero((char*)di, sizeof (dma_info_t));
14852 +
14853 + /* allocate tx packet pointer vector */
14854 + if (ntxd) {
14855 + size = ntxd * sizeof (void*);
14856 + if ((di->txp = MALLOC(osh, size)) == NULL)
14857 + goto fail;
14858 + bzero((char*)di->txp, size);
14859 + }
14860 +
14861 + /* allocate rx packet pointer vector */
14862 + if (nrxd) {
14863 + size = nrxd * sizeof (void*);
14864 + if ((di->rxp = MALLOC(osh, size)) == NULL)
14865 + goto fail;
14866 + bzero((char*)di->rxp, size);
14867 + }
14868 +
14869 + /* set message level */
14870 + di->msg_level = msg_level ? msg_level : &dma_msg_level;
14871 +
14872 + DMA_TRACE(("%s: dma_attach: drv %p osh %p regs %p ntxd %d nrxd %d rxbufsize %d nrxpost %d rxoffset %d ddoffset 0x%x dataoffset 0x%x\n", name, drv, osh, regs, ntxd, nrxd, rxbufsize, nrxpost, rxoffset, ddoffset, dataoffset));
14873 +
14874 + /* make a private copy of our callers name */
14875 + strncpy(di->name, name, MAXNAMEL);
14876 + di->name[MAXNAMEL-1] = '\0';
14877 +
14878 + di->drv = drv;
14879 + di->osh = osh;
14880 + di->regs = regs;
14881 +
14882 + /* allocate transmit descriptor ring */
14883 + if (ntxd) {
14884 + /* only need ntxd descriptors but it must be DMARINGALIGNed */
14885 + size = ntxd * sizeof (dmadd_t);
14886 + if (!ISALIGNED(DMA_CONSISTENT_ALIGN, DMARINGALIGN))
14887 + size += DMARINGALIGN;
14888 + if ((va = DMA_ALLOC_CONSISTENT(osh, size, &di->txdpa)) == NULL)
14889 + goto fail;
14890 + di->txd = (dmadd_t*) ROUNDUP((uintptr)va, DMARINGALIGN);
14891 + di->txdalign = (uint)((int8*)di->txd - (int8*)va);
14892 + di->txdpa += di->txdalign;
14893 + di->txdalloc = size;
14894 + ASSERT(ISALIGNED((uintptr)di->txd, DMARINGALIGN));
14895 + ASSERT(DMA_ADDRESSABLE(di->txdpa));
14896 + }
14897 +
14898 + /* allocate receive descriptor ring */
14899 + if (nrxd) {
14900 + /* only need nrxd descriptors but it must be DMARINGALIGNed */
14901 + size = nrxd * sizeof (dmadd_t);
14902 + if (!ISALIGNED(DMA_CONSISTENT_ALIGN, DMARINGALIGN))
14903 + size += DMARINGALIGN;
14904 + if ((va = DMA_ALLOC_CONSISTENT(osh, size, &di->rxdpa)) == NULL)
14905 + goto fail;
14906 + di->rxd = (dmadd_t*) ROUNDUP((uintptr)va, DMARINGALIGN);
14907 + di->rxdalign = (uint)((int8*)di->rxd - (int8*)va);
14908 + di->rxdpa += di->rxdalign;
14909 + di->rxdalloc = size;
14910 + ASSERT(ISALIGNED((uintptr)di->rxd, DMARINGALIGN));
14911 + ASSERT(DMA_ADDRESSABLE(di->rxdpa));
14912 + }
14913 +
14914 + /* save tunables */
14915 + di->ntxd = ntxd;
14916 + di->nrxd = nrxd;
14917 + di->rxbufsize = rxbufsize;
14918 + di->nrxpost = nrxpost;
14919 + di->rxoffset = rxoffset;
14920 + di->ddoffset = ddoffset;
14921 + di->dataoffset = dataoffset;
14922 +
14923 + return ((void*)di);
14924 +
14925 +fail:
14926 + dma_detach((void*)di);
14927 + return (NULL);
14928 +}
14929 +
14930 +/* may be called with core in reset */
14931 +void
14932 +dma_detach(dma_info_t *di)
14933 +{
14934 + if (di == NULL)
14935 + return;
14936 +
14937 + DMA_TRACE(("%s: dma_detach\n", di->name));
14938 +
14939 + /* shouldn't be here if descriptors are unreclaimed */
14940 + ASSERT(di->txin == di->txout);
14941 + ASSERT(di->rxin == di->rxout);
14942 +
14943 + /* free dma descriptor rings */
14944 + if (di->txd)
14945 + DMA_FREE_CONSISTENT(di->osh, ((int8*)di->txd - di->txdalign),
14946 + di->txdalloc, (di->txdpa - di->txdalign));
14947 + if (di->rxd)
14948 + DMA_FREE_CONSISTENT(di->osh, ((int8*)di->rxd - di->rxdalign),
14949 + di->rxdalloc, (di->rxdpa - di->rxdalign));
14950 +
14951 + /* free packet pointer vectors */
14952 + if (di->txp)
14953 + MFREE(di->osh, (void*)di->txp, (di->ntxd * sizeof (void*)));
14954 + if (di->rxp)
14955 + MFREE(di->osh, (void*)di->rxp, (di->nrxd * sizeof (void*)));
14956 +
14957 + /* free our private info structure */
14958 + MFREE(di->osh, (void*)di, sizeof (dma_info_t));
14959 +}
14960 +
14961 +
14962 +void
14963 +dma_txreset(dma_info_t *di)
14964 +{
14965 + uint32 status;
14966 +
14967 + DMA_TRACE(("%s: dma_txreset\n", di->name));
14968 +
14969 + /* suspend tx DMA first */
14970 + W_REG(&di->regs->xmtcontrol, XC_SE);
14971 + SPINWAIT((status = (R_REG(&di->regs->xmtstatus) & XS_XS_MASK)) != XS_XS_DISABLED &&
14972 + status != XS_XS_IDLE &&
14973 + status != XS_XS_STOPPED,
14974 + 10000);
14975 +
14976 + W_REG(&di->regs->xmtcontrol, 0);
14977 + SPINWAIT((status = (R_REG(&di->regs->xmtstatus) & XS_XS_MASK)) != XS_XS_DISABLED,
14978 + 10000);
14979 +
14980 + if (status != XS_XS_DISABLED) {
14981 + DMA_ERROR(("%s: dma_txreset: dma cannot be stopped\n", di->name));
14982 + }
14983 +
14984 + /* wait for the last transaction to complete */
14985 + OSL_DELAY(300);
14986 +}
14987 +
14988 +void
14989 +dma_rxreset(dma_info_t *di)
14990 +{
14991 + uint32 status;
14992 +
14993 + DMA_TRACE(("%s: dma_rxreset\n", di->name));
14994 +
14995 + W_REG(&di->regs->rcvcontrol, 0);
14996 + SPINWAIT((status = (R_REG(&di->regs->rcvstatus) & RS_RS_MASK)) != RS_RS_DISABLED,
14997 + 10000);
14998 +
14999 + if (status != RS_RS_DISABLED) {
15000 + DMA_ERROR(("%s: dma_rxreset: dma cannot be stopped\n", di->name));
15001 + }
15002 +}
15003 +
15004 +void
15005 +dma_txinit(dma_info_t *di)
15006 +{
15007 + DMA_TRACE(("%s: dma_txinit\n", di->name));
15008 +
15009 + di->txin = di->txout = 0;
15010 + di->txavail = di->ntxd - 1;
15011 +
15012 + /* clear tx descriptor ring */
15013 + BZERO_SM((void*)di->txd, (di->ntxd * sizeof (dmadd_t)));
15014 +
15015 + W_REG(&di->regs->xmtcontrol, XC_XE);
15016 + W_REG(&di->regs->xmtaddr, (di->txdpa + di->ddoffset));
15017 +}
15018 +
15019 +bool
15020 +dma_txenabled(dma_info_t *di)
15021 +{
15022 + uint32 xc;
15023 +
15024 + /* If the chip is dead, it is not enabled :-) */
15025 + xc = R_REG(&di->regs->xmtcontrol);
15026 + return ((xc != 0xffffffff) && (xc & XC_XE));
15027 +}
15028 +
15029 +void
15030 +dma_txsuspend(dma_info_t *di)
15031 +{
15032 + DMA_TRACE(("%s: dma_txsuspend\n", di->name));
15033 + OR_REG(&di->regs->xmtcontrol, XC_SE);
15034 +}
15035 +
15036 +void
15037 +dma_txresume(dma_info_t *di)
15038 +{
15039 + DMA_TRACE(("%s: dma_txresume\n", di->name));
15040 + AND_REG(&di->regs->xmtcontrol, ~XC_SE);
15041 +}
15042 +
15043 +bool
15044 +dma_txsuspended(dma_info_t *di)
15045 +{
15046 + if (!(R_REG(&di->regs->xmtcontrol) & XC_SE))
15047 + return 0;
15048 +
15049 + if ((R_REG(&di->regs->xmtstatus) & XS_XS_MASK) != XS_XS_IDLE)
15050 + return 0;
15051 +
15052 + OSL_DELAY(2);
15053 + return ((R_REG(&di->regs->xmtstatus) & XS_XS_MASK) == XS_XS_IDLE);
15054 +}
15055 +
15056 +bool
15057 +dma_txstopped(dma_info_t *di)
15058 +{
15059 + return ((R_REG(&di->regs->xmtstatus) & XS_XS_MASK) == XS_XS_STOPPED);
15060 +}
15061 +
15062 +bool
15063 +dma_rxstopped(dma_info_t *di)
15064 +{
15065 + return ((R_REG(&di->regs->rcvstatus) & RS_RS_MASK) == RS_RS_STOPPED);
15066 +}
15067 +
15068 +void
15069 +dma_fifoloopbackenable(dma_info_t *di)
15070 +{
15071 + DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
15072 + OR_REG(&di->regs->xmtcontrol, XC_LE);
15073 +}
15074 +
15075 +void
15076 +dma_rxinit(dma_info_t *di)
15077 +{
15078 + DMA_TRACE(("%s: dma_rxinit\n", di->name));
15079 +
15080 + di->rxin = di->rxout = 0;
15081 +
15082 + /* clear rx descriptor ring */
15083 + BZERO_SM((void*)di->rxd, (di->nrxd * sizeof (dmadd_t)));
15084 +
15085 + dma_rxenable(di);
15086 + W_REG(&di->regs->rcvaddr, (di->rxdpa + di->ddoffset));
15087 +}
15088 +
15089 +void
15090 +dma_rxenable(dma_info_t *di)
15091 +{
15092 + DMA_TRACE(("%s: dma_rxenable\n", di->name));
15093 + W_REG(&di->regs->rcvcontrol, ((di->rxoffset << RC_RO_SHIFT) | RC_RE));
15094 +}
15095 +
15096 +bool
15097 +dma_rxenabled(dma_info_t *di)
15098 +{
15099 + uint32 rc;
15100 +
15101 + rc = R_REG(&di->regs->rcvcontrol);
15102 + return ((rc != 0xffffffff) && (rc & RC_RE));
15103 +}
15104 +
15105 +/*
15106 + * The BCM47XX family supports full 32bit dma engine buffer addressing so
15107 + * dma buffers can cross 4 Kbyte page boundaries.
15108 + */
15109 +int
15110 +dma_txfast(dma_info_t *di, void *p0, uint32 coreflags)
15111 +{
15112 + void *p, *next;
15113 + uchar *data;
15114 + uint len;
15115 + uint txout;
15116 + uint32 ctrl;
15117 + uint32 pa;
15118 +
15119 + DMA_TRACE(("%s: dma_txfast\n", di->name));
15120 +
15121 + txout = di->txout;
15122 + ctrl = 0;
15123 +
15124 + /*
15125 + * Walk the chain of packet buffers
15126 + * allocating and initializing transmit descriptor entries.
15127 + */
15128 + for (p = p0; p; p = next) {
15129 + data = PKTDATA(di->drv, p);
15130 + len = PKTLEN(di->drv, p);
15131 + next = PKTNEXT(di->drv, p);
15132 +
15133 + /* return nonzero if out of tx descriptors */
15134 + if (NEXTTXD(txout) == di->txin)
15135 + goto outoftxd;
15136 +
15137 + if (len == 0)
15138 + continue;
15139 +
15140 + /* get physical address of buffer start */
15141 + pa = (uint32) DMA_MAP(di->osh, data, len, DMA_TX, p);
15142 + ASSERT(DMA_ADDRESSABLE(pa));
15143 +
15144 + /* build the descriptor control value */
15145 + ctrl = len & CTRL_BC_MASK;
15146 +
15147 + ctrl |= coreflags;
15148 +
15149 + if (p == p0)
15150 + ctrl |= CTRL_SOF;
15151 + if (next == NULL)
15152 + ctrl |= (CTRL_IOC | CTRL_EOF);
15153 + if (txout == (di->ntxd - 1))
15154 + ctrl |= CTRL_EOT;
15155 +
15156 + /* init the tx descriptor */
15157 + W_SM(&di->txd[txout].ctrl, BUS_SWAP32(ctrl));
15158 + W_SM(&di->txd[txout].addr, BUS_SWAP32(pa + di->dataoffset));
15159 +
15160 + ASSERT(di->txp[txout] == NULL);
15161 +
15162 + txout = NEXTTXD(txout);
15163 + }
15164 +
15165 + /* if last txd eof not set, fix it */
15166 + if (!(ctrl & CTRL_EOF))
15167 + W_SM(&di->txd[PREVTXD(txout)].ctrl, BUS_SWAP32(ctrl | CTRL_IOC | CTRL_EOF));
15168 +
15169 + /* save the packet */
15170 + di->txp[PREVTXD(txout)] = p0;
15171 +
15172 + /* bump the tx descriptor index */
15173 + di->txout = txout;
15174 +
15175 + /* kick the chip */
15176 + W_REG(&di->regs->xmtptr, I2B(txout));
15177 +
15178 + /* tx flow control */
15179 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
15180 +
15181 + return (0);
15182 +
15183 +outoftxd:
15184 + DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
15185 + PKTFREE(di->drv, p0, TRUE);
15186 + di->txavail = 0;
15187 + di->hnddma.txnobuf++;
15188 + return (-1);
15189 +}
15190 +
15191 +#define PAGESZ 4096
15192 +#define PAGEBASE(x) ((uintptr)(x) & ~4095)
15193 +
15194 +/*
15195 + * Just like above except go through the extra effort of splitting
15196 + * buffers that cross 4Kbyte boundaries into multiple tx descriptors.
15197 + */
15198 +int
15199 +dma_tx(dma_info_t *di, void *p0, uint32 coreflags)
15200 +{
15201 + void *p, *next;
15202 + uchar *data;
15203 + uint plen, len;
15204 + uchar *page, *start, *end;
15205 + uint txout;
15206 + uint32 ctrl;
15207 + uint32 pa;
15208 +
15209 + DMA_TRACE(("%s: dma_tx\n", di->name));
15210 +
15211 + txout = di->txout;
15212 + ctrl = 0;
15213 +
15214 + /*
15215 + * Walk the chain of packet buffers
15216 + * splitting those that cross 4 Kbyte boundaries
15217 + * allocating and initializing transmit descriptor entries.
15218 + */
15219 + for (p = p0; p; p = next) {
15220 + data = PKTDATA(di->drv, p);
15221 + plen = PKTLEN(di->drv, p);
15222 + next = PKTNEXT(di->drv, p);
15223 +
15224 + if (plen == 0)
15225 + continue;
15226 +
15227 + for (page = (uchar*)PAGEBASE(data);
15228 + page <= (uchar*)PAGEBASE(data + plen - 1);
15229 + page += PAGESZ) {
15230 +
15231 + /* return nonzero if out of tx descriptors */
15232 + if (NEXTTXD(txout) == di->txin)
15233 + goto outoftxd;
15234 +
15235 + start = (page == (uchar*)PAGEBASE(data))? data: page;
15236 + end = (page == (uchar*)PAGEBASE(data + plen))?
15237 + (data + plen): (page + PAGESZ);
15238 + len = (uint)(end - start);
15239 +
15240 + /* build the descriptor control value */
15241 + ctrl = len & CTRL_BC_MASK;
15242 +
15243 + ctrl |= coreflags;
15244 +
15245 + if ((p == p0) && (start == data))
15246 + ctrl |= CTRL_SOF;
15247 + if ((next == NULL) && (end == (data + plen)))
15248 + ctrl |= (CTRL_IOC | CTRL_EOF);
15249 + if (txout == (di->ntxd - 1))
15250 + ctrl |= CTRL_EOT;
15251 +
15252 + /* get physical address of buffer start */
15253 + pa = (uint32) DMA_MAP(di->osh, start, len, DMA_TX, p);
15254 + ASSERT(DMA_ADDRESSABLE(pa));
15255 +
15256 + /* init the tx descriptor */
15257 + W_SM(&di->txd[txout].ctrl, BUS_SWAP32(ctrl));
15258 + W_SM(&di->txd[txout].addr, BUS_SWAP32(pa + di->dataoffset));
15259 +
15260 + ASSERT(di->txp[txout] == NULL);
15261 +
15262 + txout = NEXTTXD(txout);
15263 + }
15264 + }
15265 +
15266 + /* if last txd eof not set, fix it */
15267 + if (!(ctrl & CTRL_EOF))
15268 + W_SM(&di->txd[PREVTXD(txout)].ctrl, BUS_SWAP32(ctrl | CTRL_IOC | CTRL_EOF));
15269 +
15270 + /* save the packet */
15271 + di->txp[PREVTXD(txout)] = p0;
15272 +
15273 + /* bump the tx descriptor index */
15274 + di->txout = txout;
15275 +
15276 + /* kick the chip */
15277 + W_REG(&di->regs->xmtptr, I2B(txout));
15278 +
15279 + /* tx flow control */
15280 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
15281 +
15282 + return (0);
15283 +
15284 +outoftxd:
15285 + DMA_ERROR(("%s: dma_tx: out of txds\n", di->name));
15286 + PKTFREE(di->drv, p0, TRUE);
15287 + di->txavail = 0;
15288 + di->hnddma.txnobuf++;
15289 + return (-1);
15290 +}
15291 +
15292 +/* returns a pointer to the next frame received, or NULL if there are no more */
15293 +void*
15294 +dma_rx(dma_info_t *di)
15295 +{
15296 + void *p;
15297 + uint len;
15298 + int skiplen = 0;
15299 +
15300 + while ((p = dma_getnextrxp(di, FALSE))) {
15301 + /* skip giant packets which span multiple rx descriptors */
15302 + if (skiplen > 0) {
15303 + skiplen -= di->rxbufsize;
15304 + if (skiplen < 0)
15305 + skiplen = 0;
15306 + PKTFREE(di->drv, p, FALSE);
15307 + continue;
15308 + }
15309 +
15310 + len = ltoh16(*(uint16*)(PKTDATA(di->drv, p)));
15311 + DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
15312 +
15313 + /* bad frame length check */
15314 + if (len > (di->rxbufsize - di->rxoffset)) {
15315 + DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n", di->name, len));
15316 + if (len > 0)
15317 + skiplen = len - (di->rxbufsize - di->rxoffset);
15318 + PKTFREE(di->drv, p, FALSE);
15319 + di->hnddma.rxgiants++;
15320 + continue;
15321 + }
15322 +
15323 + /* set actual length */
15324 + PKTSETLEN(di->drv, p, (di->rxoffset + len));
15325 +
15326 + break;
15327 + }
15328 +
15329 + return (p);
15330 +}
15331 +
15332 +/* post receive buffers */
15333 +void
15334 +dma_rxfill(dma_info_t *di)
15335 +{
15336 + void *p;
15337 + uint rxin, rxout;
15338 + uint ctrl;
15339 + uint n;
15340 + uint i;
15341 + uint32 pa;
15342 + uint rxbufsize;
15343 +
15344 + /*
15345 + * Determine how many receive buffers we're lacking
15346 + * from the full complement, allocate, initialize,
15347 + * and post them, then update the chip rx lastdscr.
15348 + */
15349 +
15350 + rxin = di->rxin;
15351 + rxout = di->rxout;
15352 + rxbufsize = di->rxbufsize;
15353 +
15354 + n = di->nrxpost - NRXDACTIVE(rxin, rxout);
15355 +
15356 + DMA_TRACE(("%s: dma_rxfill: post %d\n", di->name, n));
15357 +
15358 + for (i = 0; i < n; i++) {
15359 + if ((p = PKTGET(di->drv, rxbufsize, FALSE)) == NULL) {
15360 + DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n", di->name));
15361 + di->hnddma.rxnobuf++;
15362 + break;
15363 + }
15364 +
15365 + *(uint32*)(OSL_UNCACHED(PKTDATA(di->drv, p))) = 0;
15366 +
15367 + pa = (uint32) DMA_MAP(di->osh, PKTDATA(di->drv, p), rxbufsize, DMA_RX, p);
15368 + ASSERT(ISALIGNED(pa, 4));
15369 + ASSERT(DMA_ADDRESSABLE(pa));
15370 +
15371 + /* save the free packet pointer */
15372 + ASSERT(di->rxp[rxout] == NULL);
15373 + di->rxp[rxout] = p;
15374 +
15375 + /* prep the descriptor control value */
15376 + ctrl = rxbufsize;
15377 + if (rxout == (di->nrxd - 1))
15378 + ctrl |= CTRL_EOT;
15379 +
15380 + /* init the rx descriptor */
15381 + W_SM(&di->rxd[rxout].ctrl, BUS_SWAP32(ctrl));
15382 + W_SM(&di->rxd[rxout].addr, BUS_SWAP32(pa + di->dataoffset));
15383 +
15384 + rxout = NEXTRXD(rxout);
15385 + }
15386 +
15387 + di->rxout = rxout;
15388 +
15389 + /* update the chip lastdscr pointer */
15390 + W_REG(&di->regs->rcvptr, I2B(rxout));
15391 +}
15392 +
15393 +void
15394 +dma_txreclaim(dma_info_t *di, bool forceall)
15395 +{
15396 + void *p;
15397 +
15398 + DMA_TRACE(("%s: dma_txreclaim %s\n", di->name, forceall ? "all" : ""));
15399 +
15400 + while ((p = dma_getnexttxp(di, forceall)))
15401 + PKTFREE(di->drv, p, TRUE);
15402 +}
15403 +
15404 +/*
15405 + * Reclaim next completed txd (txds if using chained buffers) and
15406 + * return associated packet.
15407 + * If 'force' is true, reclaim txd(s) and return associated packet
15408 + * regardless of the value of the hardware "curr" pointer.
15409 + */
15410 +void*
15411 +dma_getnexttxp(dma_info_t *di, bool forceall)
15412 +{
15413 + uint start, end, i;
15414 + void *txp;
15415 +
15416 + DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
15417 +
15418 + txp = NULL;
15419 +
15420 + start = di->txin;
15421 + if (forceall)
15422 + end = di->txout;
15423 + else
15424 + end = B2I(R_REG(&di->regs->xmtstatus) & XS_CD_MASK);
15425 +
15426 + if ((start == 0) && (end > di->txout))
15427 + goto bogus;
15428 +
15429 + for (i = start; i != end && !txp; i = NEXTTXD(i)) {
15430 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->txd[i].addr)) - di->dataoffset),
15431 + (BUS_SWAP32(R_SM(&di->txd[i].ctrl)) & CTRL_BC_MASK), DMA_TX, di->txp[i]);
15432 + W_SM(&di->txd[i].addr, 0xdeadbeef);
15433 + txp = di->txp[i];
15434 + di->txp[i] = NULL;
15435 + }
15436 +
15437 + di->txin = i;
15438 +
15439 + /* tx flow control */
15440 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
15441 +
15442 + return (txp);
15443 +
15444 +bogus:
15445 +/*
15446 + DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
15447 + start, end, di->txout, forceall));
15448 +*/
15449 + return (NULL);
15450 +}
15451 +
15452 +/* like getnexttxp but no reclaim */
15453 +void*
15454 +dma_peeknexttxp(dma_info_t *di)
15455 +{
15456 + uint end, i;
15457 +
15458 + end = B2I(R_REG(&di->regs->xmtstatus) & XS_CD_MASK);
15459 +
15460 + for (i = di->txin; i != end; i = NEXTTXD(i))
15461 + if (di->txp[i])
15462 + return (di->txp[i]);
15463 +
15464 + return (NULL);
15465 +}
15466 +
15467 +void
15468 +dma_rxreclaim(dma_info_t *di)
15469 +{
15470 + void *p;
15471 +
15472 + DMA_TRACE(("%s: dma_rxreclaim\n", di->name));
15473 +
15474 + while ((p = dma_getnextrxp(di, TRUE)))
15475 + PKTFREE(di->drv, p, FALSE);
15476 +}
15477 +
15478 +void *
15479 +dma_getnextrxp(dma_info_t *di, bool forceall)
15480 +{
15481 + uint i;
15482 + void *rxp;
15483 +
15484 + /* if forcing, dma engine must be disabled */
15485 + ASSERT(!forceall || !dma_rxenabled(di));
15486 +
15487 + i = di->rxin;
15488 +
15489 + /* return if no packets posted */
15490 + if (i == di->rxout)
15491 + return (NULL);
15492 +
15493 + /* ignore curr if forceall */
15494 + if (!forceall && (i == B2I(R_REG(&di->regs->rcvstatus) & RS_CD_MASK)))
15495 + return (NULL);
15496 +
15497 + /* get the packet pointer that corresponds to the rx descriptor */
15498 + rxp = di->rxp[i];
15499 + ASSERT(rxp);
15500 + di->rxp[i] = NULL;
15501 +
15502 + /* clear this packet from the descriptor ring */
15503 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->rxd[i].addr)) - di->dataoffset),
15504 + di->rxbufsize, DMA_RX, rxp);
15505 + W_SM(&di->rxd[i].addr, 0xdeadbeef);
15506 +
15507 + di->rxin = NEXTRXD(i);
15508 +
15509 + return (rxp);
15510 +}
15511 +
15512 +
15513 +uintptr
15514 +dma_getvar(dma_info_t *di, char *name)
15515 +{
15516 + if (!strcmp(name, "&txavail"))
15517 + return ((uintptr) &di->txavail);
15518 + else {
15519 + ASSERT(0);
15520 + }
15521 + return (0);
15522 +}
15523 +
15524 +void
15525 +dma_txblock(dma_info_t *di)
15526 +{
15527 + di->txavail = 0;
15528 +}
15529 +
15530 +void
15531 +dma_txunblock(dma_info_t *di)
15532 +{
15533 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
15534 +}
15535 +
15536 +uint
15537 +dma_txactive(dma_info_t *di)
15538 +{
15539 + return (NTXDACTIVE(di->txin, di->txout));
15540 +}
15541 +
15542 +/*
15543 + * Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin).
15544 + */
15545 +void
15546 +dma_txrotate(di_t *di)
15547 +{
15548 + uint ad;
15549 + uint nactive;
15550 + uint rot;
15551 + uint old, new;
15552 + uint32 w;
15553 + uint first, last;
15554 +
15555 + ASSERT(dma_txsuspended(di));
15556 +
15557 + nactive = dma_txactive(di);
15558 + ad = B2I((R_REG(&di->regs->xmtstatus) & XS_AD_MASK) >> XS_AD_SHIFT);
15559 + rot = TXD(ad - di->txin);
15560 +
15561 + ASSERT(rot < di->ntxd);
15562 +
15563 + /* full-ring case is a lot harder - don't worry about this */
15564 + if (rot >= (di->ntxd - nactive)) {
15565 + DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
15566 + return;
15567 + }
15568 +
15569 + first = di->txin;
15570 + last = PREVTXD(di->txout);
15571 +
15572 + /* move entries starting at last and moving backwards to first */
15573 + for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
15574 + new = TXD(old + rot);
15575 +
15576 + /*
15577 + * Move the tx dma descriptor.
15578 + * EOT is set only in the last entry in the ring.
15579 + */
15580 + w = R_SM(&di->txd[old].ctrl) & ~CTRL_EOT;
15581 + if (new == (di->ntxd - 1))
15582 + w |= CTRL_EOT;
15583 + W_SM(&di->txd[new].ctrl, w);
15584 + W_SM(&di->txd[new].addr, R_SM(&di->txd[old].addr));
15585 +
15586 + /* zap the old tx dma descriptor address field */
15587 + W_SM(&di->txd[old].addr, 0xdeadbeef);
15588 +
15589 + /* move the corresponding txp[] entry */
15590 + ASSERT(di->txp[new] == NULL);
15591 + di->txp[new] = di->txp[old];
15592 + di->txp[old] = NULL;
15593 + }
15594 +
15595 + /* update txin and txout */
15596 + di->txin = ad;
15597 + di->txout = TXD(di->txout + rot);
15598 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
15599 +
15600 + /* kick the chip */
15601 + W_REG(&di->regs->xmtptr, I2B(di->txout));
15602 +}
15603 diff -Nur linux-2.4.30/drivers/net/hnd/linux_osl.c linux-2.4.30-brcm/drivers/net/hnd/linux_osl.c
15604 --- linux-2.4.30/drivers/net/hnd/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
15605 +++ linux-2.4.30-brcm/drivers/net/hnd/linux_osl.c 2005-05-22 23:01:31.000000000 +0200
15606 @@ -0,0 +1,640 @@
15607 +/*
15608 + * Linux OS Independent Layer
15609 + *
15610 + * Copyright 2004, Broadcom Corporation
15611 + * All Rights Reserved.
15612 + *
15613 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15614 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15615 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15616 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15617 + *
15618 + * $Id$
15619 + */
15620 +
15621 +#define LINUX_OSL
15622 +
15623 +#include <typedefs.h>
15624 +#include <bcmendian.h>
15625 +#include <linux/module.h>
15626 +#include <linuxver.h>
15627 +#include <linux_osl.h>
15628 +#include <bcmutils.h>
15629 +#include <linux/delay.h>
15630 +#ifdef mips
15631 +#include <asm/paccess.h>
15632 +#endif
15633 +#include <pcicfg.h>
15634 +
15635 +#define PCI_CFG_RETRY 10
15636 +
15637 +#define OS_HANDLE_MAGIC 0x1234abcd
15638 +#define BCM_MEM_FILENAME_LEN 24
15639 +
15640 +typedef struct bcm_mem_link {
15641 + struct bcm_mem_link *prev;
15642 + struct bcm_mem_link *next;
15643 + uint size;
15644 + int line;
15645 + char file[BCM_MEM_FILENAME_LEN];
15646 +} bcm_mem_link_t;
15647 +
15648 +typedef struct os_handle {
15649 + uint magic;
15650 + void *pdev;
15651 + uint malloced;
15652 + uint failed;
15653 + bcm_mem_link_t *dbgmem_list;
15654 +} os_handle_t;
15655 +
15656 +void *
15657 +osl_attach(void *pdev)
15658 +{
15659 + os_handle_t *osh;
15660 +
15661 + osh = kmalloc(sizeof(os_handle_t), GFP_ATOMIC);
15662 + ASSERT(osh);
15663 +
15664 + osh->magic = OS_HANDLE_MAGIC;
15665 + osh->malloced = 0;
15666 + osh->failed = 0;
15667 + osh->dbgmem_list = NULL;
15668 + osh->pdev = pdev;
15669 +
15670 + return osh;
15671 +}
15672 +
15673 +void
15674 +osl_detach(void *osh)
15675 +{
15676 + ASSERT((osh && (((os_handle_t *)osh)->magic == OS_HANDLE_MAGIC)));
15677 + kfree(osh);
15678 +}
15679 +
15680 +void*
15681 +osl_pktget(void *drv, uint len, bool send)
15682 +{
15683 + struct sk_buff *skb;
15684 +
15685 + if ((skb = dev_alloc_skb(len)) == NULL)
15686 + return (NULL);
15687 +
15688 + skb_put(skb, len);
15689 +
15690 + /* ensure the cookie field is cleared */
15691 + PKTSETCOOKIE(skb, NULL);
15692 +
15693 + return ((void*) skb);
15694 +}
15695 +
15696 +void
15697 +osl_pktfree(void *p)
15698 +{
15699 + struct sk_buff *skb, *nskb;
15700 +
15701 + skb = (struct sk_buff*) p;
15702 +
15703 + /* perversion: we use skb->next to chain multi-skb packets */
15704 + while (skb) {
15705 + nskb = skb->next;
15706 + skb->next = NULL;
15707 + if (skb->destructor) {
15708 + /* cannot kfree_skb() on hard IRQ (net/core/skbuff.c) if destructor exists */
15709 + dev_kfree_skb_any(skb);
15710 + } else {
15711 + /* can free immediately (even in_irq()) if destructor does not exist */
15712 + dev_kfree_skb(skb);
15713 + }
15714 + skb = nskb;
15715 + }
15716 +}
15717 +
15718 +uint32
15719 +osl_pci_read_config(void *osh, uint offset, uint size)
15720 +{
15721 + struct pci_dev *pdev;
15722 + uint val;
15723 + uint retry=PCI_CFG_RETRY;
15724 +
15725 + ASSERT((osh && (((os_handle_t *)osh)->magic == OS_HANDLE_MAGIC)));
15726 +
15727 + /* only 4byte access supported */
15728 + ASSERT(size == 4);
15729 +
15730 + pdev = ((os_handle_t *)osh)->pdev;
15731 + do {
15732 + pci_read_config_dword(pdev, offset, &val);
15733 + if (val != 0xffffffff)
15734 + break;
15735 + } while (retry--);
15736 +
15737 +
15738 + return (val);
15739 +}
15740 +
15741 +void
15742 +osl_pci_write_config(void *osh, uint offset, uint size, uint val)
15743 +{
15744 + struct pci_dev *pdev;
15745 + uint retry=PCI_CFG_RETRY;
15746 +
15747 + ASSERT((osh && (((os_handle_t *)osh)->magic == OS_HANDLE_MAGIC)));
15748 +
15749 + /* only 4byte access supported */
15750 + ASSERT(size == 4);
15751 +
15752 + pdev = ((os_handle_t *)osh)->pdev;
15753 +
15754 + do {
15755 + pci_write_config_dword(pdev, offset, val);
15756 + if (offset!=PCI_BAR0_WIN)
15757 + break;
15758 + if (osl_pci_read_config(osh,offset,size) == val)
15759 + break;
15760 + } while (retry--);
15761 +
15762 +}
15763 +
15764 +static void
15765 +osl_pcmcia_attr(void *osh, uint offset, char *buf, int size, bool write)
15766 +{
15767 +}
15768 +
15769 +void
15770 +osl_pcmcia_read_attr(void *osh, uint offset, void *buf, int size)
15771 +{
15772 + osl_pcmcia_attr(osh, offset, (char *) buf, size, FALSE);
15773 +}
15774 +
15775 +void
15776 +osl_pcmcia_write_attr(void *osh, uint offset, void *buf, int size)
15777 +{
15778 + osl_pcmcia_attr(osh, offset, (char *) buf, size, TRUE);
15779 +}
15780 +
15781 +
15782 +#ifdef BCMDBG_MEM
15783 +
15784 +void*
15785 +osl_debug_malloc(void *osh, uint size, int line, char* file)
15786 +{
15787 + bcm_mem_link_t *p;
15788 + char* basename;
15789 + os_handle_t *h = (os_handle_t *)osh;
15790 +
15791 + if (size == 0) {
15792 + return NULL;
15793 + }
15794 +
15795 + p = (bcm_mem_link_t*)osl_malloc(osh, sizeof(bcm_mem_link_t) + size);
15796 + if (p == NULL)
15797 + return p;
15798 +
15799 + p->size = size;
15800 + p->line = line;
15801 +
15802 + basename = strrchr(file, '/');
15803 + /* skip the '/' */
15804 + if (basename)
15805 + basename++;
15806 +
15807 + if (!basename)
15808 + basename = file;
15809 +
15810 + strncpy(p->file, basename, BCM_MEM_FILENAME_LEN);
15811 + p->file[BCM_MEM_FILENAME_LEN - 1] = '\0';
15812 +
15813 + /* link this block */
15814 + p->prev = NULL;
15815 + p->next = h->dbgmem_list;
15816 + if (p->next)
15817 + p->next->prev = p;
15818 + h->dbgmem_list = p;
15819 +
15820 + return p + 1;
15821 +}
15822 +
15823 +void
15824 +osl_debug_mfree(void *osh, void *addr, uint size, int line, char* file)
15825 +{
15826 + bcm_mem_link_t *p = (bcm_mem_link_t *)((int8*)addr - sizeof(bcm_mem_link_t));
15827 + os_handle_t *h = (os_handle_t *)osh;
15828 +
15829 + ASSERT((h && (h->magic == OS_HANDLE_MAGIC)));
15830 +
15831 + if (p->size == 0) {
15832 + printk("osl_debug_mfree: double free on addr 0x%x size %d at line %d file %s\n",
15833 + (uint)addr, size, line, file);
15834 + return;
15835 + }
15836 +
15837 + if (p->size != size) {
15838 + printk("osl_debug_mfree: dealloc size %d does not match alloc size %d on addr 0x%x at line %d file %s\n",
15839 + size, p->size, (uint)addr, line, file);
15840 + return;
15841 + }
15842 +
15843 + /* unlink this block */
15844 + if (p->prev)
15845 + p->prev->next = p->next;
15846 + if (p->next)
15847 + p->next->prev = p->prev;
15848 + if (h->dbgmem_list == p)
15849 + h->dbgmem_list = p->next;
15850 + p->next = p->prev = NULL;
15851 +
15852 + osl_mfree(osh, p, size + sizeof(bcm_mem_link_t));
15853 +}
15854 +
15855 +char*
15856 +osl_debug_memdump(void *osh, char *buf, uint sz)
15857 +{
15858 + bcm_mem_link_t *p;
15859 + char *obuf;
15860 + os_handle_t *h = (os_handle_t *)osh;
15861 +
15862 + ASSERT((h && (h->magic == OS_HANDLE_MAGIC)));
15863 + obuf = buf;
15864 +
15865 + buf += sprintf(buf, " Address\tSize\tFile:line\n");
15866 + for (p = h->dbgmem_list; p && ((buf - obuf) < (sz - 128)); p = p->next)
15867 + buf += sprintf(buf, "0x%08x\t%5d\t%s:%d\n",
15868 + (int)p + sizeof(bcm_mem_link_t), p->size, p->file, p->line);
15869 +
15870 + return (obuf);
15871 +}
15872 +
15873 +#endif /* BCMDBG_MEM */
15874 +
15875 +void*
15876 +osl_malloc(void *osh, uint size)
15877 +{
15878 + os_handle_t *h = (os_handle_t *)osh;
15879 + void *addr;
15880 +
15881 + ASSERT((h && (h->magic == OS_HANDLE_MAGIC)));
15882 + h->malloced += size;
15883 + addr = kmalloc(size, GFP_ATOMIC);
15884 + if (!addr)
15885 + h->failed++;
15886 + return (addr);
15887 +}
15888 +
15889 +void
15890 +osl_mfree(void *osh, void *addr, uint size)
15891 +{
15892 + os_handle_t *h = (os_handle_t *)osh;
15893 +
15894 + ASSERT((h && (h->magic == OS_HANDLE_MAGIC)));
15895 + h->malloced -= size;
15896 + kfree(addr);
15897 +}
15898 +
15899 +uint
15900 +osl_malloced(void *osh)
15901 +{
15902 + os_handle_t *h = (os_handle_t *)osh;
15903 +
15904 + ASSERT((h && (h->magic == OS_HANDLE_MAGIC)));
15905 + return (h->malloced);
15906 +}
15907 +
15908 +uint osl_malloc_failed(void *osh)
15909 +{
15910 + os_handle_t *h = (os_handle_t *)osh;
15911 +
15912 + ASSERT((h && (h->magic == OS_HANDLE_MAGIC)));
15913 + return (h->failed);
15914 +}
15915 +
15916 +void*
15917 +osl_dma_alloc_consistent(void *osh, uint size, ulong *pap)
15918 +{
15919 + struct pci_dev *dev;
15920 +
15921 + ASSERT((osh && (((os_handle_t *)osh)->magic == OS_HANDLE_MAGIC)));
15922 +
15923 + dev = ((os_handle_t *)osh)->pdev;
15924 + return (pci_alloc_consistent(dev, size, (dma_addr_t*)pap));
15925 +}
15926 +
15927 +void
15928 +osl_dma_free_consistent(void *osh, void *va, uint size, ulong pa)
15929 +{
15930 + struct pci_dev *dev;
15931 +
15932 + ASSERT((osh && (((os_handle_t *)osh)->magic == OS_HANDLE_MAGIC)));
15933 +
15934 + dev = ((os_handle_t *)osh)->pdev;
15935 + pci_free_consistent(dev, size, va, (dma_addr_t)pa);
15936 +}
15937 +
15938 +uint
15939 +osl_dma_map(void *osh, void *va, uint size, int direction)
15940 +{
15941 + int dir;
15942 + struct pci_dev *dev;
15943 +
15944 + ASSERT((osh && (((os_handle_t *)osh)->magic == OS_HANDLE_MAGIC)));
15945 +
15946 + dev = ((os_handle_t *)osh)->pdev;
15947 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
15948 + return (pci_map_single(dev, va, size, dir));
15949 +}
15950 +
15951 +void
15952 +osl_dma_unmap(void *osh, uint pa, uint size, int direction)
15953 +{
15954 + int dir;
15955 + struct pci_dev *dev;
15956 +
15957 + ASSERT((osh && (((os_handle_t *)osh)->magic == OS_HANDLE_MAGIC)));
15958 +
15959 + dev = ((os_handle_t *)osh)->pdev;
15960 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
15961 + pci_unmap_single(dev, (uint32)pa, size, dir);
15962 +}
15963 +
15964 +#if defined(BINOSL)
15965 +void
15966 +osl_assert(char *exp, char *file, int line)
15967 +{
15968 + char tempbuf[255];
15969 +
15970 + sprintf(tempbuf, "assertion \"%s\" failed: file \"%s\", line %d\n", exp, file, line);
15971 + panic(tempbuf);
15972 +}
15973 +#endif /* BCMDBG || BINOSL */
15974 +
15975 +/*
15976 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
15977 + */
15978 +#ifdef BINOSL
15979 +
15980 +int
15981 +osl_printf(const char *format, ...)
15982 +{
15983 + va_list args;
15984 + char buf[1024];
15985 + int len;
15986 +
15987 + /* sprintf into a local buffer because there *is* no "vprintk()".. */
15988 + va_start(args, format);
15989 + len = vsprintf(buf, format, args);
15990 + va_end(args);
15991 +
15992 + if (len > sizeof (buf)) {
15993 + printk("osl_printf: buffer overrun\n");
15994 + return (0);
15995 + }
15996 +
15997 + return (printk(buf));
15998 +}
15999 +
16000 +int
16001 +osl_sprintf(char *buf, const char *format, ...)
16002 +{
16003 + va_list args;
16004 + int rc;
16005 +
16006 + va_start(args, format);
16007 + rc = vsprintf(buf, format, args);
16008 + va_end(args);
16009 + return (rc);
16010 +}
16011 +
16012 +int
16013 +osl_strcmp(const char *s1, const char *s2)
16014 +{
16015 + return (strcmp(s1, s2));
16016 +}
16017 +
16018 +int
16019 +osl_strncmp(const char *s1, const char *s2, uint n)
16020 +{
16021 + return (strncmp(s1, s2, n));
16022 +}
16023 +
16024 +int
16025 +osl_strlen(char *s)
16026 +{
16027 + return (strlen(s));
16028 +}
16029 +
16030 +char*
16031 +osl_strcpy(char *d, const char *s)
16032 +{
16033 + return (strcpy(d, s));
16034 +}
16035 +
16036 +char*
16037 +osl_strncpy(char *d, const char *s, uint n)
16038 +{
16039 + return (strncpy(d, s, n));
16040 +}
16041 +
16042 +void
16043 +bcopy(const void *src, void *dst, int len)
16044 +{
16045 + memcpy(dst, src, len);
16046 +}
16047 +
16048 +int
16049 +bcmp(const void *b1, const void *b2, int len)
16050 +{
16051 + return (memcmp(b1, b2, len));
16052 +}
16053 +
16054 +void
16055 +bzero(void *b, int len)
16056 +{
16057 + memset(b, '\0', len);
16058 +}
16059 +
16060 +uint32
16061 +osl_readl(volatile uint32 *r)
16062 +{
16063 + return (readl(r));
16064 +}
16065 +
16066 +uint16
16067 +osl_readw(volatile uint16 *r)
16068 +{
16069 + return (readw(r));
16070 +}
16071 +
16072 +uint8
16073 +osl_readb(volatile uint8 *r)
16074 +{
16075 + return (readb(r));
16076 +}
16077 +
16078 +void
16079 +osl_writel(uint32 v, volatile uint32 *r)
16080 +{
16081 + writel(v, r);
16082 +}
16083 +
16084 +void
16085 +osl_writew(uint16 v, volatile uint16 *r)
16086 +{
16087 + writew(v, r);
16088 +}
16089 +
16090 +void
16091 +osl_writeb(uint8 v, volatile uint8 *r)
16092 +{
16093 + writeb(v, r);
16094 +}
16095 +
16096 +void *
16097 +osl_uncached(void *va)
16098 +{
16099 +#ifdef mips
16100 + return ((void*)KSEG1ADDR(va));
16101 +#else
16102 + return ((void*)va);
16103 +#endif
16104 +}
16105 +
16106 +uint
16107 +osl_getcycles(void)
16108 +{
16109 + uint cycles;
16110 +
16111 +#if defined(mips)
16112 + cycles = read_c0_count() * 2;
16113 +#elif defined(__i386__)
16114 + rdtscl(cycles);
16115 +#else
16116 + cycles = 0;
16117 +#endif
16118 + return cycles;
16119 +}
16120 +
16121 +void *
16122 +osl_reg_map(uint32 pa, uint size)
16123 +{
16124 + return (ioremap_nocache((unsigned long)pa, (unsigned long)size));
16125 +}
16126 +
16127 +void
16128 +osl_reg_unmap(void *va)
16129 +{
16130 + iounmap(va);
16131 +}
16132 +
16133 +int
16134 +osl_busprobe(uint32 *val, uint32 addr)
16135 +{
16136 +#ifdef mips
16137 + return get_dbe(*val, (uint32*)addr);
16138 +#else
16139 + *val = readl(addr);
16140 + return 0;
16141 +#endif
16142 +}
16143 +
16144 +void
16145 +osl_delay(uint usec)
16146 +{
16147 + udelay(usec);
16148 +}
16149 +
16150 +uchar*
16151 +osl_pktdata(void *drv, void *skb)
16152 +{
16153 + return (((struct sk_buff*)skb)->data);
16154 +}
16155 +
16156 +uint
16157 +osl_pktlen(void *drv, void *skb)
16158 +{
16159 + return (((struct sk_buff*)skb)->len);
16160 +}
16161 +
16162 +uint
16163 +osl_pktheadroom(void *drv, void *skb)
16164 +{
16165 + return (uint) skb_headroom((struct sk_buff *) skb);
16166 +}
16167 +
16168 +uint
16169 +osl_pkttailroom(void *drv, void *skb)
16170 +{
16171 + return (uint) skb_tailroom((struct sk_buff *) skb);
16172 +}
16173 +
16174 +void*
16175 +osl_pktnext(void *drv, void *skb)
16176 +{
16177 + return (((struct sk_buff*)skb)->next);
16178 +}
16179 +
16180 +void
16181 +osl_pktsetnext(void *skb, void *x)
16182 +{
16183 + ((struct sk_buff*)skb)->next = (struct sk_buff*)x;
16184 +}
16185 +
16186 +void
16187 +osl_pktsetlen(void *drv, void *skb, uint len)
16188 +{
16189 + __skb_trim((struct sk_buff*)skb, len);
16190 +}
16191 +
16192 +uchar*
16193 +osl_pktpush(void *drv, void *skb, int bytes)
16194 +{
16195 + return (skb_push((struct sk_buff*)skb, bytes));
16196 +}
16197 +
16198 +uchar*
16199 +osl_pktpull(void *drv, void *skb, int bytes)
16200 +{
16201 + return (skb_pull((struct sk_buff*)skb, bytes));
16202 +}
16203 +
16204 +void*
16205 +osl_pktdup(void *drv, void *skb)
16206 +{
16207 + return (skb_clone((struct sk_buff*)skb, GFP_ATOMIC));
16208 +}
16209 +
16210 +void*
16211 +osl_pktcookie(void *skb)
16212 +{
16213 + return ((void*)((struct sk_buff*)skb)->csum);
16214 +}
16215 +
16216 +void
16217 +osl_pktsetcookie(void *skb, void *x)
16218 +{
16219 + ((struct sk_buff*)skb)->csum = (uint)x;
16220 +}
16221 +
16222 +void*
16223 +osl_pktlink(void *skb)
16224 +{
16225 + return (((struct sk_buff*)skb)->prev);
16226 +}
16227 +
16228 +void
16229 +osl_pktsetlink(void *skb, void *x)
16230 +{
16231 + ((struct sk_buff*)skb)->prev = (struct sk_buff*)x;
16232 +}
16233 +
16234 +uint
16235 +osl_pktprio(void *skb)
16236 +{
16237 + return (((struct sk_buff*)skb)->priority);
16238 +}
16239 +
16240 +void
16241 +osl_pktsetprio(void *skb, uint x)
16242 +{
16243 + ((struct sk_buff*)skb)->priority = x;
16244 +}
16245 +
16246 +#endif /* BINOSL */
16247 diff -Nur linux-2.4.30/drivers/net/hnd/Makefile linux-2.4.30-brcm/drivers/net/hnd/Makefile
16248 --- linux-2.4.30/drivers/net/hnd/Makefile 1970-01-01 01:00:00.000000000 +0100
16249 +++ linux-2.4.30-brcm/drivers/net/hnd/Makefile 2005-05-25 18:54:08.000000000 +0200
16250 @@ -0,0 +1,19 @@
16251 +#
16252 +# Makefile for the BCM47xx specific kernel interface routines
16253 +# under Linux.
16254 +#
16255 +
16256 +EXTRA_CFLAGS += -I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
16257 +
16258 +O_TARGET := hnd.o
16259 +
16260 +HND_OBJS := bcmutils.o hnddma.o linux_osl.o sbutils.o bcmsrom.o
16261 +
16262 +export-objs := shared_ksyms.o
16263 +obj-y := shared_ksyms.o $(HND_OBJS)
16264 +obj-m := $(O_TARGET)
16265 +
16266 +include $(TOPDIR)/Rules.make
16267 +
16268 +shared_ksyms.c: shared_ksyms.sh $(HND_OBJS)
16269 + sh -e $< $(HND_OBJS) > $@
16270 diff -Nur linux-2.4.30/drivers/net/hnd/sbutils.c linux-2.4.30-brcm/drivers/net/hnd/sbutils.c
16271 --- linux-2.4.30/drivers/net/hnd/sbutils.c 1970-01-01 01:00:00.000000000 +0100
16272 +++ linux-2.4.30-brcm/drivers/net/hnd/sbutils.c 2005-05-22 23:01:41.000000000 +0200
16273 @@ -0,0 +1,2063 @@
16274 +/*
16275 + * Misc utility routines for accessing chip-specific features
16276 + * of the SiliconBackplane-based Broadcom chips.
16277 + *
16278 + * Copyright 2004, Broadcom Corporation
16279 + * All Rights Reserved.
16280 + *
16281 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
16282 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
16283 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
16284 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
16285 + * $Id$
16286 + */
16287 +
16288 +#include <typedefs.h>
16289 +#include <osl.h>
16290 +#include <bcmutils.h>
16291 +#include <bcmdevs.h>
16292 +#include <sbconfig.h>
16293 +#include <sbchipc.h>
16294 +#include <sbpci.h>
16295 +#include <pcicfg.h>
16296 +#include <sbpcmcia.h>
16297 +#include <sbextif.h>
16298 +#include <sbutils.h>
16299 +#include <bcmsrom.h>
16300 +
16301 +/* debug/trace */
16302 +#define SB_ERROR(args)
16303 +
16304 +
16305 +#define CLOCK_BASE_5350 12500000 /* Specific to 5350*/
16306 +
16307 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
16308 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
16309 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
16310 +
16311 +/* misc sb info needed by some of the routines */
16312 +typedef struct sb_info {
16313 + uint chip; /* chip number */
16314 + uint chiprev; /* chip revision */
16315 + uint chippkg; /* chip package option */
16316 + uint boardtype; /* board type */
16317 + uint boardvendor; /* board vendor id */
16318 + uint bustype; /* what bus type we are going through */
16319 +
16320 + void *osh; /* osl os handle */
16321 + void *sdh; /* bcmsdh handle */
16322 +
16323 + void *curmap; /* current regs va */
16324 + void *regs[SB_MAXCORES]; /* other regs va */
16325 +
16326 + uint curidx; /* current core index */
16327 + uint dev_coreid; /* the core provides driver functions */
16328 + uint pciidx; /* pci core index */
16329 + uint pcirev; /* pci core rev */
16330 +
16331 + uint pcmciaidx; /* pcmcia core index */
16332 + uint pcmciarev; /* pcmcia core rev */
16333 + bool memseg; /* flag to toggle MEM_SEG register */
16334 +
16335 + uint ccrev; /* chipc core rev */
16336 +
16337 + uint gpioidx; /* gpio control core index */
16338 + uint gpioid; /* gpio control coretype */
16339 +
16340 + uint numcores; /* # discovered cores */
16341 + uint coreid[SB_MAXCORES]; /* id of each core */
16342 +
16343 + void *intr_arg; /* interrupt callback function arg */
16344 + sb_intrsoff_t intrsoff_fn; /* function turns chip interrupts off */
16345 + sb_intrsrestore_t intrsrestore_fn; /* function restore chip interrupts */
16346 + sb_intrsenabled_t intrsenabled_fn; /* function to check if chip interrupts are enabled */
16347 +} sb_info_t;
16348 +
16349 +/* local prototypes */
16350 +static void* BCMINIT(sb_doattach)(sb_info_t *si, uint devid, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
16351 +static void BCMINIT(sb_scan)(sb_info_t *si);
16352 +static uint sb_corereg(void *sbh, uint coreidx, uint regoff, uint mask, uint val);
16353 +static uint _sb_coreidx(void *sbh);
16354 +static uint sb_findcoreidx(void *sbh, uint coreid, uint coreunit);
16355 +static uint BCMINIT(sb_pcidev2chip)(uint pcidev);
16356 +static uint BCMINIT(sb_chip2numcores)(uint chip);
16357 +
16358 +#define SB_INFO(sbh) (sb_info_t*)sbh
16359 +#define SET_SBREG(sbh, r, mask, val) W_SBREG((sbh), (r), ((R_SBREG((sbh), (r)) & ~(mask)) | (val)))
16360 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && ISALIGNED((x), SB_CORE_SIZE))
16361 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
16362 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
16363 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
16364 +#define BADIDX (SB_MAXCORES+1)
16365 +#define NOREV (SBIDH_RC_MASK + 1)
16366 +
16367 +#define R_SBREG(sbh, sbr) sb_read_sbreg((sbh), (sbr))
16368 +#define W_SBREG(sbh, sbr, v) sb_write_sbreg((sbh), (sbr), (v))
16369 +#define AND_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) & (v)))
16370 +#define OR_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) | (v)))
16371 +
16372 +/*
16373 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
16374 + * after core switching to avoid invalid register accesss inside ISR.
16375 + */
16376 +#define INTR_OFF(si, intr_val) \
16377 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
16378 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
16379 +#define INTR_RESTORE(si, intr_val) \
16380 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
16381 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
16382 +
16383 +/* power control defines */
16384 +#define LPOMINFREQ 25000 /* low power oscillator min */
16385 +#define LPOMAXFREQ 43000 /* low power oscillator max */
16386 +#define XTALMINFREQ 19800000 /* 20mhz - 1% */
16387 +#define XTALMAXFREQ 20200000 /* 20mhz + 1% */
16388 +#define PCIMINFREQ 25000000 /* 25mhz */
16389 +#define PCIMAXFREQ 34000000 /* 33mhz + fudge */
16390 +#define SCC_DEF_DIV 0 /* default slow clock divider */
16391 +
16392 +#define XTAL_ON_DELAY 1000 /* Xtal power on delay in us */
16393 +
16394 +#define SCC_LOW2FAST_LIMIT 5000 /* turn on fast clock time, in unit of ms */
16395 +
16396 +static uint32
16397 +sb_read_sbreg(void *sbh, volatile uint32 *sbr)
16398 +{
16399 + sb_info_t *si;
16400 + uint8 tmp;
16401 + uint32 val, intr_val = 0;
16402 +
16403 + si = SB_INFO(sbh);
16404 +
16405 + /*
16406 + * compact flash only has 11 bits address, while we needs 12 bits address.
16407 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
16408 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
16409 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
16410 + */
16411 + if(si->memseg) {
16412 + INTR_OFF(si, intr_val);
16413 + tmp = 1;
16414 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
16415 + (uintptr)sbr &= ~(1 << 11); /* mask out bit 11*/
16416 + }
16417 +
16418 + val = R_REG(sbr);
16419 +
16420 + if(si->memseg) {
16421 + tmp = 0;
16422 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
16423 + INTR_RESTORE(si, intr_val);
16424 + }
16425 +
16426 + return (val);
16427 +}
16428 +
16429 +static void
16430 +sb_write_sbreg(void *sbh, volatile uint32 *sbr, uint32 v)
16431 +{
16432 + sb_info_t *si;
16433 + uint8 tmp;
16434 + volatile uint32 dummy;
16435 + uint32 intr_val = 0;
16436 +
16437 + si = SB_INFO(sbh);
16438 +
16439 + /*
16440 + * compact flash only has 11 bits address, while we needs 12 bits address.
16441 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
16442 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
16443 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
16444 + */
16445 + if(si->memseg) {
16446 + INTR_OFF(si, intr_val);
16447 + tmp = 1;
16448 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
16449 + (uintptr)sbr &= ~(1 << 11); /* mask out bit 11 */
16450 + }
16451 +
16452 + if (BUSTYPE(si->bustype) == PCMCIA_BUS) {
16453 +#ifdef IL_BIGENDIAN
16454 + dummy = R_REG(sbr);
16455 + W_REG(((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
16456 + dummy = R_REG(sbr);
16457 + W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
16458 +#else
16459 + dummy = R_REG(sbr);
16460 + W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
16461 + dummy = R_REG(sbr);
16462 + W_REG(((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
16463 +#endif
16464 + } else
16465 + W_REG(sbr, v);
16466 +
16467 + if(si->memseg) {
16468 + tmp = 0;
16469 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
16470 + INTR_RESTORE(si, intr_val);
16471 + }
16472 +}
16473 +
16474 +/*
16475 + * Allocate a sb handle.
16476 + * devid - pci device id (used to determine chip#)
16477 + * osh - opaque OS handle
16478 + * regs - virtual address of initial core registers
16479 + * bustype - pci/pcmcia/sb/sdio/etc
16480 + * vars - pointer to a pointer area for "environment" variables
16481 + * varsz - pointer to int to return the size of the vars
16482 + */
16483 +void*
16484 +BCMINITFN(sb_attach)(uint devid, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz)
16485 +{
16486 + sb_info_t *si;
16487 +
16488 + /* alloc sb_info_t */
16489 + if ((si = MALLOC(osh, sizeof (sb_info_t))) == NULL) {
16490 + SB_ERROR(("sb_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
16491 + return (NULL);
16492 + }
16493 +
16494 + if (BCMINIT(sb_doattach)(si, devid, osh, regs, bustype, sdh, vars, varsz) == NULL) {
16495 + MFREE(osh, si, sizeof (sb_info_t));
16496 + return (NULL);
16497 + }
16498 + return si;
16499 +}
16500 +
16501 +/* Using sb_kattach depends on SB_BUS support, either implicit */
16502 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
16503 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
16504 +
16505 +/* global kernel resource */
16506 +static sb_info_t ksi;
16507 +
16508 +/* generic kernel variant of sb_attach() */
16509 +void*
16510 +BCMINITFN(sb_kattach)()
16511 +{
16512 + uint32 *regs;
16513 + char *unused;
16514 + int varsz;
16515 +
16516 + if (ksi.curmap == NULL) {
16517 + uint32 cid;
16518 +
16519 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
16520 + cid = R_REG((uint32 *)regs);
16521 + if (((cid & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
16522 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
16523 + ((cid & CID_REV_MASK) <= 0x00020000)) {
16524 + uint32 *scc, val;
16525 +
16526 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
16527 + val = R_REG(scc);
16528 + SB_ERROR((" initial scc = 0x%x\n", val));
16529 + val |= SCC_SS_XTAL;
16530 + W_REG(scc, val);
16531 + }
16532 +
16533 + if (BCMINIT(sb_doattach)(&ksi, BCM4710_DEVICE_ID, NULL, (void*)regs,
16534 + SB_BUS, NULL, &unused, &varsz) == NULL) {
16535 + return NULL;
16536 + }
16537 + }
16538 +
16539 + return &ksi;
16540 +}
16541 +#endif
16542 +
16543 +static void*
16544 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz)
16545 +{
16546 + uint origidx;
16547 + chipcregs_t *cc;
16548 + uint32 w;
16549 + int res;
16550 +
16551 + ASSERT(GOODREGS(regs));
16552 +
16553 + bzero((uchar*)si, sizeof (sb_info_t));
16554 +
16555 + si->pciidx = si->gpioidx = BADIDX;
16556 +
16557 + si->osh = osh;
16558 + si->curmap = regs;
16559 + si->sdh = sdh;
16560 +
16561 + /* check to see if we are a sb core mimic'ing a pci core */
16562 + if (bustype == PCI_BUS) {
16563 + if (OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof (uint32)) == 0xffffffff)
16564 + bustype = SB_BUS;
16565 + else
16566 + bustype = PCI_BUS;
16567 + }
16568 +
16569 + si->bustype = bustype;
16570 + if (si->bustype != BUSTYPE(si->bustype)) {
16571 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
16572 + si->bustype, BUSTYPE(si->bustype)));
16573 + return NULL;
16574 + }
16575 +
16576 + /* need to set memseg flag for CF card first before any sb registers access */
16577 + if (BUSTYPE(si->bustype) == PCMCIA_BUS)
16578 + si->memseg = TRUE;
16579 +
16580 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
16581 + if (BUSTYPE(si->bustype) == PCI_BUS)
16582 + sb_pwrctl_xtal((void*)si, XTAL|PLL, ON);
16583 +
16584 + /* initialize current core index value */
16585 + si->curidx = _sb_coreidx((void*)si);
16586 + if (si->curidx == BADIDX) {
16587 + return NULL;
16588 + }
16589 +
16590 + /* keep and reuse the initial register mapping */
16591 + origidx = si->curidx;
16592 + if (BUSTYPE(si->bustype) == SB_BUS)
16593 + si->regs[origidx] = regs;
16594 +
16595 + /* is core-0 a chipcommon core? */
16596 + si->numcores = 1;
16597 + cc = (chipcregs_t*) sb_setcoreidx((void*)si, 0);
16598 + if (sb_coreid((void*)si) != SB_CC)
16599 + cc = NULL;
16600 +
16601 + /* determine chip id and rev */
16602 + if (cc) {
16603 + /* chip common core found! */
16604 + si->chip = R_REG(&cc->chipid) & CID_ID_MASK;
16605 + si->chiprev = (R_REG(&cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
16606 + si->chippkg = (R_REG(&cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
16607 + } else {
16608 + /* The only pcmcia chip without a chipcommon core is a 4301 */
16609 + if (BUSTYPE(si->bustype) == PCMCIA_BUS)
16610 + devid = BCM4301_DEVICE_ID;
16611 +
16612 + /* no chip common core -- must convert device id to chip id */
16613 + if ((si->chip = BCMINIT(sb_pcidev2chip)(devid)) == 0) {
16614 + SB_ERROR(("sb_attach: unrecognized device id 0x%04x\n", devid));
16615 + return NULL;
16616 + }
16617 + }
16618 +
16619 + /* get chipcommon rev */
16620 + si->ccrev = cc ? sb_corerev((void*)si) : NOREV;
16621 +
16622 + /* determine numcores */
16623 + if (cc && ((si->ccrev == 4) || (si->ccrev >= 6)))
16624 + si->numcores = (R_REG(&cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
16625 + else
16626 + si->numcores = BCMINIT(sb_chip2numcores)(si->chip);
16627 +
16628 + /* return to original core */
16629 + sb_setcoreidx((void*)si, origidx);
16630 +
16631 + /* sanity checks */
16632 + ASSERT(si->chip);
16633 +
16634 + /* scan for cores */
16635 + BCMINIT(sb_scan)(si);
16636 +
16637 + /* srom_var_init() depends on sb_scan() info */
16638 + if ((res = srom_var_init(si, si->bustype, si->curmap, osh, vars, varsz))) {
16639 + SB_ERROR(("sb_attach: srom_var_init failed: bad srom\n"));
16640 + return (NULL);
16641 + }
16642 +
16643 + if (cc == NULL) {
16644 + /*
16645 + * The chip revision number is hardwired into all
16646 + * of the pci function config rev fields and is
16647 + * independent from the individual core revision numbers.
16648 + * For example, the "A0" silicon of each chip is chip rev 0.
16649 + * For PCMCIA we get it from the CIS instead.
16650 + */
16651 + if (BUSTYPE(si->bustype) == PCMCIA_BUS) {
16652 + ASSERT(vars);
16653 + si->chiprev = getintvar(*vars, "chiprev");
16654 + } else if (BUSTYPE(si->bustype) == PCI_BUS) {
16655 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_REV, sizeof (uint32));
16656 + si->chiprev = w & 0xff;
16657 + } else
16658 + si->chiprev = 0;
16659 + }
16660 +
16661 + if (BUSTYPE(si->bustype) == PCMCIA_BUS) {
16662 + w = getintvar(*vars, "regwindowsz");
16663 + si->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
16664 + }
16665 +
16666 + /* gpio control core is required */
16667 + if (!GOODIDX(si->gpioidx)) {
16668 + SB_ERROR(("sb_attach: gpio control core not found\n"));
16669 + return NULL;
16670 + }
16671 +
16672 + /* get boardtype and boardrev */
16673 + switch (BUSTYPE(si->bustype)) {
16674 + case PCI_BUS:
16675 + /* do a pci config read to get subsystem id and subvendor id */
16676 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_SVID, sizeof (uint32));
16677 + si->boardvendor = w & 0xffff;
16678 + si->boardtype = (w >> 16) & 0xffff;
16679 + break;
16680 +
16681 + case PCMCIA_BUS:
16682 + case SDIO_BUS:
16683 + si->boardvendor = getintvar(*vars, "manfid");
16684 + si->boardtype = getintvar(*vars, "prodid");
16685 + break;
16686 +
16687 + case SB_BUS:
16688 + si->boardvendor = VENDOR_BROADCOM;
16689 + si->boardtype = 0xffff;
16690 + break;
16691 + }
16692 +
16693 + if (si->boardtype == 0) {
16694 + SB_ERROR(("sb_attach: unknown board type\n"));
16695 + ASSERT(si->boardtype);
16696 + }
16697 +
16698 +
16699 + return ((void*)si);
16700 +}
16701 +
16702 +uint
16703 +sb_coreid(void *sbh)
16704 +{
16705 + sb_info_t *si;
16706 + sbconfig_t *sb;
16707 +
16708 + si = SB_INFO(sbh);
16709 + sb = REGS2SB(si->curmap);
16710 +
16711 + return ((R_SBREG(sbh, &(sb)->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
16712 +}
16713 +
16714 +uint
16715 +sb_coreidx(void *sbh)
16716 +{
16717 + sb_info_t *si;
16718 +
16719 + si = SB_INFO(sbh);
16720 + return (si->curidx);
16721 +}
16722 +
16723 +/* return current index of core */
16724 +static uint
16725 +_sb_coreidx(void *sbh)
16726 +{
16727 + sb_info_t *si;
16728 + sbconfig_t *sb;
16729 + uint32 sbaddr = 0;
16730 +
16731 + si = SB_INFO(sbh);
16732 + ASSERT(si);
16733 +
16734 + switch (BUSTYPE(si->bustype)) {
16735 + case SB_BUS:
16736 + sb = REGS2SB(si->curmap);
16737 + sbaddr = sb_base(R_SBREG(sbh, &sb->sbadmatch0));
16738 + break;
16739 +
16740 + case PCI_BUS:
16741 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32));
16742 + break;
16743 +
16744 + case PCMCIA_BUS: {
16745 + uint8 tmp = 0;
16746 +
16747 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
16748 + sbaddr = (uint)tmp << 12;
16749 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
16750 + sbaddr |= (uint)tmp << 16;
16751 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
16752 + sbaddr |= (uint)tmp << 24;
16753 + break;
16754 + }
16755 + default:
16756 + ASSERT(0);
16757 + }
16758 +
16759 + if (!GOODCOREADDR(sbaddr))
16760 + return BADIDX;
16761 +
16762 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
16763 +}
16764 +
16765 +uint
16766 +sb_corevendor(void *sbh)
16767 +{
16768 + sb_info_t *si;
16769 + sbconfig_t *sb;
16770 +
16771 + si = SB_INFO(sbh);
16772 + sb = REGS2SB(si->curmap);
16773 +
16774 + return ((R_SBREG(sbh, &(sb)->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
16775 +}
16776 +
16777 +uint
16778 +sb_corerev(void *sbh)
16779 +{
16780 + sb_info_t *si;
16781 + sbconfig_t *sb;
16782 +
16783 + si = SB_INFO(sbh);
16784 + sb = REGS2SB(si->curmap);
16785 +
16786 + return (R_SBREG(sbh, &(sb)->sbidhigh) & SBIDH_RC_MASK);
16787 +}
16788 +
16789 +void *
16790 +sb_osh(void *sbh)
16791 +{
16792 + sb_info_t *si;
16793 +
16794 + si = SB_INFO(sbh);
16795 + return si->osh;
16796 +}
16797 +
16798 +#define SBTML_ALLOW (SBTML_PE | SBTML_FGC | SBTML_FL_MASK)
16799 +
16800 +/* set/clear sbtmstatelow core-specific flags */
16801 +uint32
16802 +sb_coreflags(void *sbh, uint32 mask, uint32 val)
16803 +{
16804 + sb_info_t *si;
16805 + sbconfig_t *sb;
16806 + uint32 w;
16807 +
16808 + si = SB_INFO(sbh);
16809 + sb = REGS2SB(si->curmap);
16810 +
16811 + ASSERT((val & ~mask) == 0);
16812 + ASSERT((mask & ~SBTML_ALLOW) == 0);
16813 +
16814 + /* mask and set */
16815 + if (mask || val) {
16816 + w = (R_SBREG(sbh, &sb->sbtmstatelow) & ~mask) | val;
16817 + W_SBREG(sbh, &sb->sbtmstatelow, w);
16818 + }
16819 +
16820 + /* return the new value */
16821 + return (R_SBREG(sbh, &sb->sbtmstatelow) & SBTML_ALLOW);
16822 +}
16823 +
16824 +/* set/clear sbtmstatehigh core-specific flags */
16825 +uint32
16826 +sb_coreflagshi(void *sbh, uint32 mask, uint32 val)
16827 +{
16828 + sb_info_t *si;
16829 + sbconfig_t *sb;
16830 + uint32 w;
16831 +
16832 + si = SB_INFO(sbh);
16833 + sb = REGS2SB(si->curmap);
16834 +
16835 + ASSERT((val & ~mask) == 0);
16836 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
16837 +
16838 + /* mask and set */
16839 + if (mask || val) {
16840 + w = (R_SBREG(sbh, &sb->sbtmstatehigh) & ~mask) | val;
16841 + W_SBREG(sbh, &sb->sbtmstatehigh, w);
16842 + }
16843 +
16844 + /* return the new value */
16845 + return (R_SBREG(sbh, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
16846 +}
16847 +
16848 +bool
16849 +sb_iscoreup(void *sbh)
16850 +{
16851 + sb_info_t *si;
16852 + sbconfig_t *sb;
16853 +
16854 + si = SB_INFO(sbh);
16855 + sb = REGS2SB(si->curmap);
16856 +
16857 + return ((R_SBREG(sbh, &(sb)->sbtmstatelow) & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK);
16858 +}
16859 +
16860 +/*
16861 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
16862 + * switch back to the original core, and return the new value.
16863 + */
16864 +static uint
16865 +sb_corereg(void *sbh, uint coreidx, uint regoff, uint mask, uint val)
16866 +{
16867 + sb_info_t *si;
16868 + uint origidx;
16869 + uint32 *r;
16870 + uint w;
16871 + uint intr_val = 0;
16872 +
16873 + ASSERT(GOODIDX(coreidx));
16874 + ASSERT(regoff < SB_CORE_SIZE);
16875 + ASSERT((val & ~mask) == 0);
16876 +
16877 + si = SB_INFO(sbh);
16878 +
16879 + INTR_OFF(si, intr_val);
16880 +
16881 + /* save current core index */
16882 + origidx = sb_coreidx(sbh);
16883 +
16884 + /* switch core */
16885 + r = (uint32*) ((uchar*) sb_setcoreidx(sbh, coreidx) + regoff);
16886 +
16887 + /* mask and set */
16888 + if (mask || val) {
16889 + if (regoff >= SBCONFIGOFF) {
16890 + w = (R_SBREG(sbh, r) & ~mask) | val;
16891 + W_SBREG(sbh, r, w);
16892 + } else {
16893 + w = (R_REG(r) & ~mask) | val;
16894 + W_REG(r, w);
16895 + }
16896 + }
16897 +
16898 + /* readback */
16899 + if (regoff >= SBCONFIGOFF)
16900 + w = R_SBREG(sbh, r);
16901 + else
16902 + w = R_REG(r);
16903 +
16904 + /* restore core index */
16905 + if (origidx != coreidx)
16906 + sb_setcoreidx(sbh, origidx);
16907 +
16908 + INTR_RESTORE(si, intr_val);
16909 + return (w);
16910 +}
16911 +
16912 +/* scan the sb enumerated space to identify all cores */
16913 +static void
16914 +BCMINITFN(sb_scan)(sb_info_t *si)
16915 +{
16916 + void *sbh;
16917 + uint origidx;
16918 + uint i;
16919 +
16920 + sbh = (void*) si;
16921 +
16922 + /* numcores should already be set */
16923 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
16924 +
16925 + /* save current core index */
16926 + origidx = sb_coreidx(sbh);
16927 +
16928 + si->pciidx = si->pcmciaidx = si->gpioidx = BADIDX;
16929 + si->pcirev = si->pcmciarev = NOREV;
16930 +
16931 + for (i = 0; i < si->numcores; i++) {
16932 + sb_setcoreidx(sbh, i);
16933 + si->coreid[i] = sb_coreid(sbh);
16934 +
16935 + if (si->coreid[i] == SB_PCI) {
16936 + si->pciidx = i;
16937 + si->pcirev = sb_corerev(sbh);
16938 +
16939 + } else if (si->coreid[i] == SB_PCMCIA) {
16940 + si->pcmciaidx = i;
16941 + si->pcmciarev = sb_corerev(sbh);
16942 + }
16943 + }
16944 +
16945 + /*
16946 + * Find the gpio "controlling core" type and index.
16947 + * Precedence:
16948 + * - if there's a chip common core - use that
16949 + * - else if there's a pci core (rev >= 2) - use that
16950 + * - else there had better be an extif core (4710 only)
16951 + */
16952 + if (GOODIDX(sb_findcoreidx(sbh, SB_CC, 0))) {
16953 + si->gpioidx = sb_findcoreidx(sbh, SB_CC, 0);
16954 + si->gpioid = SB_CC;
16955 + } else if (GOODIDX(si->pciidx) && (si->pcirev >= 2)) {
16956 + si->gpioidx = si->pciidx;
16957 + si->gpioid = SB_PCI;
16958 + } else if (sb_findcoreidx(sbh, SB_EXTIF, 0)) {
16959 + si->gpioidx = sb_findcoreidx(sbh, SB_EXTIF, 0);
16960 + si->gpioid = SB_EXTIF;
16961 + } else
16962 + ASSERT(si->gpioidx != BADIDX);
16963 +
16964 + /* return to original core index */
16965 + sb_setcoreidx(sbh, origidx);
16966 +}
16967 +
16968 +/* may be called with core in reset */
16969 +void
16970 +sb_detach(void *sbh)
16971 +{
16972 + sb_info_t *si;
16973 + uint idx;
16974 +
16975 + si = SB_INFO(sbh);
16976 +
16977 + if (si == NULL)
16978 + return;
16979 +
16980 + if (BUSTYPE(si->bustype) == SB_BUS)
16981 + for (idx = 0; idx < SB_MAXCORES; idx++)
16982 + if (si->regs[idx]) {
16983 + REG_UNMAP(si->regs[idx]);
16984 + si->regs[idx] = NULL;
16985 + }
16986 +
16987 + MFREE(si->osh, si, sizeof (sb_info_t));
16988 +}
16989 +
16990 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
16991 +static uint
16992 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
16993 +{
16994 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
16995 + return (BCM4710_DEVICE_ID);
16996 + if ((pcidev >= BCM4610_DEVICE_ID) && (pcidev <= BCM4610_USB_ID))
16997 + return (BCM4610_DEVICE_ID);
16998 + if ((pcidev >= BCM4402_DEVICE_ID) && (pcidev <= BCM4402_V90_ID))
16999 + return (BCM4402_DEVICE_ID);
17000 + if (pcidev == BCM4401_ENET_ID)
17001 + return (BCM4402_DEVICE_ID);
17002 + if ((pcidev >= BCM4307_V90_ID) && (pcidev <= BCM4307_D11B_ID))
17003 + return (BCM4307_DEVICE_ID);
17004 + if (pcidev == BCM4301_DEVICE_ID)
17005 + return (BCM4301_DEVICE_ID);
17006 +
17007 + return (0);
17008 +}
17009 +
17010 +/* convert chip number to number of i/o cores */
17011 +static uint
17012 +BCMINITFN(sb_chip2numcores)(uint chip)
17013 +{
17014 + if (chip == 0x4710)
17015 + return (9);
17016 + if (chip == 0x4610)
17017 + return (9);
17018 + if (chip == 0x4402)
17019 + return (3);
17020 + if ((chip == 0x4307) || (chip == 0x4301))
17021 + return (5);
17022 + if (chip == 0x4310)
17023 + return (8);
17024 + if (chip == 0x4306) /* < 4306c0 */
17025 + return (6);
17026 + if (chip == 0x4704)
17027 + return (9);
17028 + if (chip == 0x5365)
17029 + return (7);
17030 +
17031 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
17032 + ASSERT(0);
17033 + return (1);
17034 +}
17035 +
17036 +/* return index of coreid or BADIDX if not found */
17037 +static uint
17038 +sb_findcoreidx(void *sbh, uint coreid, uint coreunit)
17039 +{
17040 + sb_info_t *si;
17041 + uint found;
17042 + uint i;
17043 +
17044 + si = SB_INFO(sbh);
17045 + found = 0;
17046 +
17047 + for (i = 0; i < si->numcores; i++)
17048 + if (si->coreid[i] == coreid) {
17049 + if (found == coreunit)
17050 + return (i);
17051 + found++;
17052 + }
17053 +
17054 + return (BADIDX);
17055 +}
17056 +
17057 +/*
17058 + * this function changes logical "focus" to the indiciated core,
17059 + * must be called with interrupt off.
17060 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
17061 + */
17062 +void*
17063 +sb_setcoreidx(void *sbh, uint coreidx)
17064 +{
17065 + sb_info_t *si;
17066 + uint32 sbaddr;
17067 + uint8 tmp;
17068 +
17069 + si = SB_INFO(sbh);
17070 +
17071 + if (coreidx >= si->numcores)
17072 + return (NULL);
17073 +
17074 + /*
17075 + * If the user has provided an interrupt mask enabled function,
17076 + * then assert interrupts are disabled before switching the core.
17077 + */
17078 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
17079 +
17080 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
17081 +
17082 + switch (BUSTYPE(si->bustype)) {
17083 + case SB_BUS:
17084 + /* map new one */
17085 + if (!si->regs[coreidx]) {
17086 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
17087 + ASSERT(GOODREGS(si->regs[coreidx]));
17088 + }
17089 + si->curmap = si->regs[coreidx];
17090 + break;
17091 +
17092 + case PCI_BUS:
17093 + /* point bar0 window */
17094 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
17095 + break;
17096 +
17097 + case PCMCIA_BUS:
17098 + tmp = (sbaddr >> 12) & 0x0f;
17099 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
17100 + tmp = (sbaddr >> 16) & 0xff;
17101 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
17102 + tmp = (sbaddr >> 24) & 0xff;
17103 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
17104 + break;
17105 + }
17106 +
17107 + si->curidx = coreidx;
17108 +
17109 + return (si->curmap);
17110 +}
17111 +
17112 +/*
17113 + * this function changes logical "focus" to the indiciated core,
17114 + * must be called with interrupt off.
17115 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
17116 + */
17117 +void*
17118 +sb_setcore(void *sbh, uint coreid, uint coreunit)
17119 +{
17120 + sb_info_t *si;
17121 + uint idx;
17122 +
17123 + si = SB_INFO(sbh);
17124 +
17125 + idx = sb_findcoreidx(sbh, coreid, coreunit);
17126 + if (!GOODIDX(idx))
17127 + return (NULL);
17128 +
17129 + return (sb_setcoreidx(sbh, idx));
17130 +}
17131 +
17132 +/* return chip number */
17133 +uint
17134 +BCMINITFN(sb_chip)(void *sbh)
17135 +{
17136 + sb_info_t *si;
17137 +
17138 + si = SB_INFO(sbh);
17139 + return (si->chip);
17140 +}
17141 +
17142 +/* return chip revision number */
17143 +uint
17144 +BCMINITFN(sb_chiprev)(void *sbh)
17145 +{
17146 + sb_info_t *si;
17147 +
17148 + si = SB_INFO(sbh);
17149 + return (si->chiprev);
17150 +}
17151 +
17152 +/* return chip common revision number */
17153 +uint
17154 +BCMINITFN(sb_chipcrev)(void *sbh)
17155 +{
17156 + sb_info_t *si;
17157 +
17158 + si = SB_INFO(sbh);
17159 + return (si->ccrev);
17160 +}
17161 +
17162 +/* return chip package option */
17163 +uint
17164 +BCMINITFN(sb_chippkg)(void *sbh)
17165 +{
17166 + sb_info_t *si;
17167 +
17168 + si = SB_INFO(sbh);
17169 + return (si->chippkg);
17170 +}
17171 +
17172 +/* return PCI core rev. */
17173 +uint
17174 +BCMINITFN(sb_pcirev)(void *sbh)
17175 +{
17176 + sb_info_t *si;
17177 +
17178 + si = SB_INFO(sbh);
17179 + return (si->pcirev);
17180 +}
17181 +
17182 +/* return PCMCIA core rev. */
17183 +uint
17184 +BCMINITFN(sb_pcmciarev)(void *sbh)
17185 +{
17186 + sb_info_t *si;
17187 +
17188 + si = SB_INFO(sbh);
17189 + return (si->pcmciarev);
17190 +}
17191 +
17192 +/* return board vendor id */
17193 +uint
17194 +BCMINITFN(sb_boardvendor)(void *sbh)
17195 +{
17196 + sb_info_t *si;
17197 +
17198 + si = SB_INFO(sbh);
17199 + return (si->boardvendor);
17200 +}
17201 +
17202 +/* return boardtype */
17203 +uint
17204 +BCMINITFN(sb_boardtype)(void *sbh)
17205 +{
17206 + sb_info_t *si;
17207 + char *var;
17208 +
17209 + si = SB_INFO(sbh);
17210 +
17211 + if (BUSTYPE(si->bustype) == SB_BUS && si->boardtype == 0xffff) {
17212 + /* boardtype format is a hex string */
17213 + si->boardtype = getintvar(NULL, "boardtype");
17214 +
17215 + /* backward compatibility for older boardtype string format */
17216 + if ((si->boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
17217 + if (!strcmp(var, "bcm94710dev"))
17218 + si->boardtype = BCM94710D_BOARD;
17219 + else if (!strcmp(var, "bcm94710ap"))
17220 + si->boardtype = BCM94710AP_BOARD;
17221 + else if (!strcmp(var, "bcm94310u"))
17222 + si->boardtype = BCM94310U_BOARD;
17223 + else if (!strcmp(var, "bu4711"))
17224 + si->boardtype = BU4711_BOARD;
17225 + else if (!strcmp(var, "bu4710"))
17226 + si->boardtype = BU4710_BOARD;
17227 + else if (!strcmp(var, "bcm94702mn"))
17228 + si->boardtype = BCM94702MN_BOARD;
17229 + else if (!strcmp(var, "bcm94710r1"))
17230 + si->boardtype = BCM94710R1_BOARD;
17231 + else if (!strcmp(var, "bcm94710r4"))
17232 + si->boardtype = BCM94710R4_BOARD;
17233 + else if (!strcmp(var, "bcm94702cpci"))
17234 + si->boardtype = BCM94702CPCI_BOARD;
17235 + else if (!strcmp(var, "bcm95380_rr"))
17236 + si->boardtype = BCM95380RR_BOARD;
17237 + }
17238 + }
17239 +
17240 + return (si->boardtype);
17241 +}
17242 +
17243 +/* return bus type of sdh device */
17244 +uint
17245 +sb_bus(void *sbh)
17246 +{
17247 + sb_info_t *si;
17248 +
17249 + si = SB_INFO(sbh);
17250 + return (si->bustype);
17251 +}
17252 +
17253 +/* return list of found cores */
17254 +uint
17255 +sb_corelist(void *sbh, uint coreid[])
17256 +{
17257 + sb_info_t *si;
17258 +
17259 + si = SB_INFO(sbh);
17260 +
17261 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof (uint)));
17262 + return (si->numcores);
17263 +}
17264 +
17265 +/* return current register mapping */
17266 +void *
17267 +sb_coreregs(void *sbh)
17268 +{
17269 + sb_info_t *si;
17270 +
17271 + si = SB_INFO(sbh);
17272 + ASSERT(GOODREGS(si->curmap));
17273 +
17274 + return (si->curmap);
17275 +}
17276 +
17277 +
17278 +/* do buffered registers update */
17279 +void
17280 +sb_commit(void *sbh)
17281 +{
17282 + sb_info_t *si;
17283 + uint origidx;
17284 + uint intr_val = 0;
17285 +
17286 + si = SB_INFO(sbh);
17287 +
17288 + origidx = si->curidx;
17289 + ASSERT(GOODIDX(origidx));
17290 +
17291 + INTR_OFF(si, intr_val);
17292 +
17293 + /* switch over to chipcommon core if there is one, else use pci */
17294 + if (si->ccrev != NOREV) {
17295 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
17296 +
17297 + /* do the buffer registers update */
17298 + W_REG(&ccregs->broadcastaddress, SB_COMMIT);
17299 + W_REG(&ccregs->broadcastdata, 0x0);
17300 + } else if (si->pciidx != BADIDX) {
17301 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
17302 +
17303 + /* do the buffer registers update */
17304 + W_REG(&pciregs->bcastaddr, SB_COMMIT);
17305 + W_REG(&pciregs->bcastdata, 0x0);
17306 + } else {
17307 + ASSERT((si->ccrev != NOREV) && (si->pciidx != BADIDX));
17308 + }
17309 +
17310 + /* restore core index */
17311 + sb_setcoreidx(sbh, origidx);
17312 + INTR_RESTORE(si, intr_val);
17313 +}
17314 +
17315 +/* reset and re-enable a core */
17316 +void
17317 +sb_core_reset(void *sbh, uint32 bits)
17318 +{
17319 + sb_info_t *si;
17320 + sbconfig_t *sb;
17321 + volatile uint32 dummy;
17322 +
17323 + si = SB_INFO(sbh);
17324 + ASSERT(GOODREGS(si->curmap));
17325 + sb = REGS2SB(si->curmap);
17326 +
17327 + /*
17328 + * Must do the disable sequence first to work for arbitrary current core state.
17329 + */
17330 + sb_core_disable(sbh, bits);
17331 +
17332 + /*
17333 + * Now do the initialization sequence.
17334 + */
17335 +
17336 + /* set reset while enabling the clock and forcing them on throughout the core */
17337 + W_SBREG(sbh, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits));
17338 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
17339 +
17340 + if (sb_coreid(sbh) == SB_ILINE100) {
17341 + bcm_mdelay(50);
17342 + } else {
17343 + OSL_DELAY(1);
17344 + }
17345 +
17346 + if (R_SBREG(sbh, &sb->sbtmstatehigh) & SBTMH_SERR) {
17347 + W_SBREG(sbh, &sb->sbtmstatehigh, 0);
17348 + }
17349 + if ((dummy = R_SBREG(sbh, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
17350 + AND_SBREG(sbh, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
17351 + }
17352 +
17353 + /* clear reset and allow it to propagate throughout the core */
17354 + W_SBREG(sbh, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
17355 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
17356 + OSL_DELAY(1);
17357 +
17358 + /* leave clock enabled */
17359 + W_SBREG(sbh, &sb->sbtmstatelow, (SBTML_CLK | bits));
17360 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
17361 + OSL_DELAY(1);
17362 +}
17363 +
17364 +void
17365 +sb_core_tofixup(void *sbh)
17366 +{
17367 + sb_info_t *si;
17368 + sbconfig_t *sb;
17369 +
17370 + si = SB_INFO(sbh);
17371 +
17372 + if ((si->pciidx == BADIDX) || (si->pcirev >= 5))
17373 + return;
17374 +
17375 + ASSERT(GOODREGS(si->curmap));
17376 + sb = REGS2SB(si->curmap);
17377 +
17378 + if (BUSTYPE(si->bustype) == SB_BUS) {
17379 + SET_SBREG(sbh, &sb->sbimconfiglow,
17380 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
17381 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
17382 + } else {
17383 + if (sb_coreid(sbh) == SB_PCI) {
17384 + SET_SBREG(sbh, &sb->sbimconfiglow,
17385 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
17386 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
17387 + } else {
17388 + SET_SBREG(sbh, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
17389 + }
17390 + }
17391 +
17392 + sb_commit(sbh);
17393 +}
17394 +
17395 +void
17396 +sb_core_disable(void *sbh, uint32 bits)
17397 +{
17398 + sb_info_t *si;
17399 + volatile uint32 dummy;
17400 + sbconfig_t *sb;
17401 +
17402 + si = SB_INFO(sbh);
17403 +
17404 + ASSERT(GOODREGS(si->curmap));
17405 + sb = REGS2SB(si->curmap);
17406 +
17407 + /* if core is already in reset, just return */
17408 + if (R_SBREG(sbh, &sb->sbtmstatelow) & SBTML_RESET)
17409 + return;
17410 +
17411 + /* if clocks are not enabled, put into reset and return */
17412 + if ((R_SBREG(sbh, &sb->sbtmstatelow) & SBTML_CLK) == 0)
17413 + goto disable;
17414 +
17415 + /* set the target reject bit and spin until busy is clear */
17416 + W_SBREG(sbh, &sb->sbtmstatelow, (SBTML_CLK | SBTML_REJ));
17417 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
17418 + OSL_DELAY(1);
17419 + SPINWAIT((R_SBREG(sbh, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
17420 +
17421 + if (R_SBREG(sbh, &sb->sbidlow) & SBIDL_INIT) {
17422 + OR_SBREG(sbh, &sb->sbimstate, SBIM_RJ);
17423 + dummy = R_SBREG(sbh, &sb->sbimstate);
17424 + OSL_DELAY(1);
17425 + SPINWAIT((R_SBREG(sbh, &sb->sbimstate) & SBIM_BY), 100000);
17426 + }
17427 +
17428 + /* set reset and reject while enabling the clocks */
17429 + W_SBREG(sbh, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET));
17430 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
17431 + OSL_DELAY(10);
17432 +
17433 + /* don't forget to clear the initiator reject bit */
17434 + if (R_SBREG(sbh, &sb->sbidlow) & SBIDL_INIT)
17435 + AND_SBREG(sbh, &sb->sbimstate, ~SBIM_RJ);
17436 +
17437 +disable:
17438 + /* leave reset and reject asserted */
17439 + W_SBREG(sbh, &sb->sbtmstatelow, (bits | SBTML_REJ | SBTML_RESET));
17440 + OSL_DELAY(1);
17441 +}
17442 +
17443 +void
17444 +sb_watchdog(void *sbh, uint ticks)
17445 +{
17446 + sb_info_t *si = SB_INFO(sbh);
17447 +
17448 + /* instant NMI */
17449 + switch (si->gpioid) {
17450 + case SB_CC:
17451 + sb_corereg(sbh, si->gpioidx, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
17452 + break;
17453 + case SB_EXTIF:
17454 + sb_corereg(sbh, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
17455 + break;
17456 + }
17457 +}
17458 +
17459 +/* initialize the pcmcia core */
17460 +void
17461 +sb_pcmcia_init(void *sbh)
17462 +{
17463 + sb_info_t *si;
17464 + uint8 cor;
17465 +
17466 + si = SB_INFO(sbh);
17467 +
17468 + /* enable d11 mac interrupts */
17469 + if (si->chip == BCM4301_DEVICE_ID) {
17470 + /* Have to use FCR2 in 4301 */
17471 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
17472 + cor |= COR_IRQEN | COR_FUNEN;
17473 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
17474 + } else {
17475 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
17476 + cor |= COR_IRQEN | COR_FUNEN;
17477 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
17478 + }
17479 +
17480 +}
17481 +
17482 +
17483 +/*
17484 + * Configure the pci core for pci client (NIC) action
17485 + * and get appropriate dma offset value.
17486 + * coremask is the bitvec of cores by index to be enabled.
17487 + */
17488 +void
17489 +sb_pci_setup(void *sbh, uint32 *dmaoffset, uint coremask)
17490 +{
17491 + sb_info_t *si;
17492 + sbconfig_t *sb;
17493 + sbpciregs_t *pciregs;
17494 + uint32 sbflag;
17495 + uint32 w;
17496 + uint idx;
17497 +
17498 + si = SB_INFO(sbh);
17499 +
17500 + if (dmaoffset)
17501 + *dmaoffset = 0;
17502 +
17503 + /* if not pci bus, we're done */
17504 + if (BUSTYPE(si->bustype) != PCI_BUS)
17505 + return;
17506 +
17507 + ASSERT(si->pciidx != BADIDX);
17508 +
17509 + /* get current core index */
17510 + idx = si->curidx;
17511 +
17512 + /* we interrupt on this backplane flag number */
17513 + ASSERT(GOODREGS(si->curmap));
17514 + sb = REGS2SB(si->curmap);
17515 + sbflag = R_SBREG(sbh, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
17516 +
17517 + /* switch over to pci core */
17518 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->pciidx);
17519 + sb = REGS2SB(pciregs);
17520 +
17521 + /*
17522 + * Enable sb->pci interrupts. Assume
17523 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
17524 + */
17525 + if (si->pcirev < 6) {
17526 + /* set sbintvec bit for our flag number */
17527 + OR_SBREG(sbh, &sb->sbintvec, (1 << sbflag));
17528 + } else {
17529 + /* pci config write to set this core bit in PCIIntMask */
17530 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
17531 + w |= (coremask << PCI_SBIM_SHIFT);
17532 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
17533 + }
17534 +
17535 + /* enable prefetch and bursts for dma big window */
17536 + OR_REG(&pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
17537 +
17538 + /* enable read multiple for dma big window */
17539 + if (si->pcirev >= 11)
17540 + OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
17541 +
17542 + if (si->pcirev < 5) {
17543 + SET_SBREG(sbh, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
17544 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
17545 + sb_commit(sbh);
17546 + }
17547 +
17548 + /* switch back to previous core */
17549 + sb_setcoreidx(sbh, idx);
17550 +
17551 + /* use large sb pci dma window */
17552 + if (dmaoffset)
17553 + *dmaoffset = SB_PCI_DMA;
17554 +}
17555 +
17556 +uint32
17557 +sb_base(uint32 admatch)
17558 +{
17559 + uint32 base;
17560 + uint type;
17561 +
17562 + type = admatch & SBAM_TYPE_MASK;
17563 + ASSERT(type < 3);
17564 +
17565 + base = 0;
17566 +
17567 + if (type == 0) {
17568 + base = admatch & SBAM_BASE0_MASK;
17569 + } else if (type == 1) {
17570 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
17571 + base = admatch & SBAM_BASE1_MASK;
17572 + } else if (type == 2) {
17573 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
17574 + base = admatch & SBAM_BASE2_MASK;
17575 + }
17576 +
17577 + return (base);
17578 +}
17579 +
17580 +uint32
17581 +sb_size(uint32 admatch)
17582 +{
17583 + uint32 size;
17584 + uint type;
17585 +
17586 + type = admatch & SBAM_TYPE_MASK;
17587 + ASSERT(type < 3);
17588 +
17589 + size = 0;
17590 +
17591 + if (type == 0) {
17592 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
17593 + } else if (type == 1) {
17594 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
17595 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
17596 + } else if (type == 2) {
17597 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
17598 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
17599 + }
17600 +
17601 + return (size);
17602 +}
17603 +
17604 +/* return the core-type instantiation # of the current core */
17605 +uint
17606 +sb_coreunit(void *sbh)
17607 +{
17608 + sb_info_t *si;
17609 + uint idx;
17610 + uint coreid;
17611 + uint coreunit;
17612 + uint i;
17613 +
17614 + si = SB_INFO(sbh);
17615 + coreunit = 0;
17616 +
17617 + idx = si->curidx;
17618 +
17619 + ASSERT(GOODREGS(si->curmap));
17620 + coreid = sb_coreid(sbh);
17621 +
17622 + /* count the cores of our type */
17623 + for (i = 0; i < idx; i++)
17624 + if (si->coreid[i] == coreid)
17625 + coreunit++;
17626 +
17627 + return (coreunit);
17628 +}
17629 +
17630 +static INLINE uint32
17631 +factor6(uint32 x)
17632 +{
17633 + switch (x) {
17634 + case CC_F6_2: return 2;
17635 + case CC_F6_3: return 3;
17636 + case CC_F6_4: return 4;
17637 + case CC_F6_5: return 5;
17638 + case CC_F6_6: return 6;
17639 + case CC_F6_7: return 7;
17640 + default: return 0;
17641 + }
17642 +}
17643 +
17644 +/* calculate the speed the SB would run at given a set of clockcontrol values */
17645 +uint32
17646 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
17647 +{
17648 + uint32 n1, n2, clock, m1, m2, m3, mc;
17649 +
17650 + n1 = n & CN_N1_MASK;
17651 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
17652 +
17653 + if (pll_type == PLL_TYPE6) {
17654 + if (m & CC_T6_MMASK)
17655 + return CC_T6_M1;
17656 + else
17657 + return CC_T6_M0;
17658 + } else if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE4)|| (pll_type == PLL_TYPE3)) {
17659 + n1 = factor6(n1);
17660 + n2 += CC_F5_BIAS;
17661 + } else if (pll_type == PLL_TYPE2) {
17662 + n1 += CC_T2_BIAS;
17663 + n2 += CC_T2_BIAS;
17664 + ASSERT((n1 >= 2) && (n1 <= 7));
17665 + ASSERT((n2 >= 5) && (n2 <= 23));
17666 + } else if (pll_type == PLL_TYPE5) {
17667 + return (100000000);
17668 + } else
17669 + ASSERT((pll_type >= PLL_TYPE1) && (pll_type <= PLL_TYPE4));
17670 +
17671 + /* Special case for 5350 */
17672 + if (pll_type == PLL_TYPE3)
17673 + clock = CLOCK_BASE_5350 * n1 * n2;
17674 + else
17675 + clock = CC_CLOCK_BASE * n1 * n2;
17676 +
17677 + if (clock == 0)
17678 + return 0;
17679 +
17680 + m1 = m & CC_M1_MASK;
17681 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
17682 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
17683 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
17684 +
17685 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE4) || (pll_type == PLL_TYPE3)) {
17686 + m1 = factor6(m1);
17687 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
17688 + m2 += CC_F5_BIAS;
17689 + else
17690 + m2 = factor6(m2);
17691 + m3 = factor6(m3);
17692 +
17693 + switch (mc) {
17694 + case CC_MC_BYPASS: return (clock);
17695 + case CC_MC_M1: return (clock / m1);
17696 + case CC_MC_M1M2: return (clock / (m1 * m2));
17697 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
17698 + case CC_MC_M1M3: return (clock / (m1 * m3));
17699 + default: return (0);
17700 + }
17701 + } else {
17702 + ASSERT(pll_type == PLL_TYPE2);
17703 +
17704 + m1 += CC_T2_BIAS;
17705 + m2 += CC_T2M2_BIAS;
17706 + m3 += CC_T2_BIAS;
17707 + ASSERT((m1 >= 2) && (m1 <= 7));
17708 + ASSERT((m2 >= 3) && (m2 <= 10));
17709 + ASSERT((m3 >= 2) && (m3 <= 7));
17710 +
17711 + if ((mc & CC_T2MC_M1BYP) == 0)
17712 + clock /= m1;
17713 + if ((mc & CC_T2MC_M2BYP) == 0)
17714 + clock /= m2;
17715 + if ((mc & CC_T2MC_M3BYP) == 0)
17716 + clock /= m3;
17717 +
17718 + return(clock);
17719 + }
17720 +}
17721 +
17722 +/* returns the current speed the SB is running at */
17723 +uint32
17724 +sb_clock(void *sbh)
17725 +{
17726 + sb_info_t *si;
17727 + extifregs_t *eir;
17728 + chipcregs_t *cc;
17729 + uint32 n, m;
17730 + uint idx;
17731 + uint32 pll_type, rate;
17732 + uint intr_val = 0;
17733 +
17734 + si = SB_INFO(sbh);
17735 + idx = si->curidx;
17736 + pll_type = PLL_TYPE1;
17737 +
17738 + INTR_OFF(si, intr_val);
17739 +
17740 + /* switch to extif or chipc core */
17741 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
17742 + n = R_REG(&eir->clockcontrol_n);
17743 + m = R_REG(&eir->clockcontrol_sb);
17744 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
17745 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
17746 + n = R_REG(&cc->clockcontrol_n);
17747 + if (pll_type == PLL_TYPE6)
17748 + m = R_REG(&cc->clockcontrol_mips);
17749 + else if (pll_type == PLL_TYPE3)
17750 + {
17751 + // Added by Chen-I for 5365
17752 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
17753 + m = R_REG(&cc->clockcontrol_sb);
17754 + else m = R_REG(&cc->clockcontrol_m2);
17755 + }
17756 + else
17757 + m = R_REG(&cc->clockcontrol_sb);
17758 + } else {
17759 + INTR_RESTORE(si, intr_val);
17760 + return 0;
17761 + }
17762 +
17763 + // Added by Chen-I for 5365
17764 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
17765 + {
17766 + rate = 100000000;
17767 + }
17768 + else
17769 + {
17770 + /* calculate rate */
17771 + rate = sb_clock_rate(pll_type, n, m);
17772 + if (pll_type == PLL_TYPE3) rate = rate / 2;
17773 + }
17774 +
17775 + /* switch back to previous core */
17776 + sb_setcoreidx(sbh, idx);
17777 +
17778 + INTR_RESTORE(si, intr_val);
17779 +
17780 + return rate;
17781 +}
17782 +
17783 +/* change logical "focus" to the gpio core for optimized access */
17784 +void*
17785 +sb_gpiosetcore(void *sbh)
17786 +{
17787 + sb_info_t *si;
17788 +
17789 + si = SB_INFO(sbh);
17790 +
17791 + return (sb_setcoreidx(sbh, si->gpioidx));
17792 +}
17793 +
17794 +/* mask&set gpiocontrol bits */
17795 +uint32
17796 +sb_gpiocontrol(void *sbh, uint32 mask, uint32 val)
17797 +{
17798 + sb_info_t *si;
17799 + uint regoff;
17800 +
17801 + si = SB_INFO(sbh);
17802 + regoff = 0;
17803 +
17804 + switch (si->gpioid) {
17805 + case SB_CC:
17806 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
17807 + break;
17808 +
17809 + case SB_PCI:
17810 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
17811 + break;
17812 +
17813 + case SB_EXTIF:
17814 + return (0);
17815 + }
17816 +
17817 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
17818 +}
17819 +
17820 +/* mask&set gpio output enable bits */
17821 +uint32
17822 +sb_gpioouten(void *sbh, uint32 mask, uint32 val)
17823 +{
17824 + sb_info_t *si;
17825 + uint regoff;
17826 +
17827 + si = SB_INFO(sbh);
17828 + regoff = 0;
17829 +
17830 + switch (si->gpioid) {
17831 + case SB_CC:
17832 + regoff = OFFSETOF(chipcregs_t, gpioouten);
17833 + break;
17834 +
17835 + case SB_PCI:
17836 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
17837 + break;
17838 +
17839 + case SB_EXTIF:
17840 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
17841 + break;
17842 + }
17843 +
17844 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
17845 +}
17846 +
17847 +/* mask&set gpio output bits */
17848 +uint32
17849 +sb_gpioout(void *sbh, uint32 mask, uint32 val)
17850 +{
17851 + sb_info_t *si;
17852 + uint regoff;
17853 +
17854 + si = SB_INFO(sbh);
17855 + regoff = 0;
17856 +
17857 + switch (si->gpioid) {
17858 + case SB_CC:
17859 + regoff = OFFSETOF(chipcregs_t, gpioout);
17860 + break;
17861 +
17862 + case SB_PCI:
17863 + regoff = OFFSETOF(sbpciregs_t, gpioout);
17864 + break;
17865 +
17866 + case SB_EXTIF:
17867 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
17868 + break;
17869 + }
17870 +
17871 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
17872 +}
17873 +
17874 +/* return the current gpioin register value */
17875 +uint32
17876 +sb_gpioin(void *sbh)
17877 +{
17878 + sb_info_t *si;
17879 + uint regoff;
17880 +
17881 + si = SB_INFO(sbh);
17882 + regoff = 0;
17883 +
17884 + switch (si->gpioid) {
17885 + case SB_CC:
17886 + regoff = OFFSETOF(chipcregs_t, gpioin);
17887 + break;
17888 +
17889 + case SB_PCI:
17890 + regoff = OFFSETOF(sbpciregs_t, gpioin);
17891 + break;
17892 +
17893 + case SB_EXTIF:
17894 + regoff = OFFSETOF(extifregs_t, gpioin);
17895 + break;
17896 + }
17897 +
17898 + return (sb_corereg(sbh, si->gpioidx, regoff, 0, 0));
17899 +}
17900 +
17901 +/* mask&set gpio interrupt polarity bits */
17902 +uint32
17903 +sb_gpiointpolarity(void *sbh, uint32 mask, uint32 val)
17904 +{
17905 + sb_info_t *si;
17906 + uint regoff;
17907 +
17908 + si = SB_INFO(sbh);
17909 + regoff = 0;
17910 +
17911 + switch (si->gpioid) {
17912 + case SB_CC:
17913 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
17914 + break;
17915 +
17916 + case SB_PCI:
17917 + /* pci gpio implementation does not support interrupt polarity */
17918 + ASSERT(0);
17919 + break;
17920 +
17921 + case SB_EXTIF:
17922 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
17923 + break;
17924 + }
17925 +
17926 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
17927 +}
17928 +
17929 +/* mask&set gpio interrupt mask bits */
17930 +uint32
17931 +sb_gpiointmask(void *sbh, uint32 mask, uint32 val)
17932 +{
17933 + sb_info_t *si;
17934 + uint regoff;
17935 +
17936 + si = SB_INFO(sbh);
17937 + regoff = 0;
17938 +
17939 + switch (si->gpioid) {
17940 + case SB_CC:
17941 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
17942 + break;
17943 +
17944 + case SB_PCI:
17945 + /* pci gpio implementation does not support interrupt mask */
17946 + ASSERT(0);
17947 + break;
17948 +
17949 + case SB_EXTIF:
17950 + regoff = OFFSETOF(extifregs_t, gpiointmask);
17951 + break;
17952 + }
17953 +
17954 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
17955 +}
17956 +
17957 +
17958 +/*
17959 + * Return the slow clock source.
17960 + * Three sources of SLOW CLOCK: LPO, Xtal, PCI
17961 + */
17962 +static uint
17963 +sb_slowclk_src(void *sbh)
17964 +{
17965 + sb_info_t *si;
17966 + chipcregs_t *cc;
17967 + uint32 v;
17968 +
17969 + si = SB_INFO(sbh);
17970 +
17971 + ASSERT(sb_coreid(sbh) == SB_CC);
17972 +
17973 + if (si->ccrev < 6) {
17974 + switch (BUSTYPE(si->bustype)) {
17975 + case PCMCIA_BUS: return (SCC_SS_XTAL);
17976 + case PCI_BUS:
17977 + v = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
17978 + if (v & PCI_CFG_GPIO_SCS)
17979 + return (SCC_SS_PCI);
17980 + else
17981 + return (SCC_SS_XTAL);
17982 + default: return (SCC_SS_XTAL);
17983 + }
17984 + } else if (si->ccrev < 10) {
17985 + cc = (chipcregs_t*) sb_setcoreidx(sbh, si->curidx);
17986 + v = R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK;
17987 + return (v);
17988 + } else {
17989 + return (SCC_SS_XTAL);
17990 + }
17991 +}
17992 +
17993 +/*
17994 + * Return the slowclock min or max frequency.
17995 + * Three sources of SLOW CLOCK:
17996 + * 1. On Chip LPO - 32khz or 160khz
17997 + * 2. On Chip Xtal OSC - 20mhz/4*(divider+1)
17998 + * 3. External PCI clock - 66mhz/4*(divider+1)
17999 + */
18000 +static uint
18001 +sb_slowclk_freq(void *sbh, bool max)
18002 +{
18003 + sb_info_t *si;
18004 + chipcregs_t *cc;
18005 + uint32 slowclk;
18006 + uint div;
18007 +
18008 + si = SB_INFO(sbh);
18009 +
18010 + ASSERT(sb_coreid(sbh) == SB_CC);
18011 +
18012 + cc = (chipcregs_t*) sb_setcoreidx(sbh, si->curidx);
18013 +
18014 + /* shouldn't be here unless we've established the chip has dynamic power control */
18015 + ASSERT(R_REG(&cc->capabilities) & CAP_PWR_CTL);
18016 +
18017 + slowclk = sb_slowclk_src(sbh);
18018 + if (si->ccrev < 6) {
18019 + if (slowclk == SCC_SS_PCI)
18020 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
18021 + else
18022 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
18023 + } else if (si->ccrev < 10) {
18024 + div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHF) + 1);
18025 + if (slowclk == SCC_SS_LPO)
18026 + return (max? LPOMAXFREQ : LPOMINFREQ);
18027 + else if (slowclk == SCC_SS_XTAL)
18028 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
18029 + else if (slowclk == SCC_SS_PCI)
18030 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
18031 + else
18032 + ASSERT(0);
18033 + } else {
18034 + /* Chipc rev 10 is InstaClock */
18035 + div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHF;
18036 + div = 4 * (div + 1);
18037 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
18038 + }
18039 + return (0);
18040 +}
18041 +
18042 +static void
18043 +sb_pwrctl_setdelay(void *sbh, void *chipcregs)
18044 +{
18045 + sb_info_t *si;
18046 + chipcregs_t * cc;
18047 + uint slowmaxfreq, pll_delay, slowclk;
18048 + uint pll_on_delay, fref_sel_delay;
18049 +
18050 + si = SB_INFO(sbh);
18051 + pll_delay = PLL_DELAY;
18052 +
18053 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
18054 + * since the xtal will also be powered down by dynamic power control logic.
18055 + */
18056 + slowclk = sb_slowclk_src(sbh);
18057 + if (slowclk != SCC_SS_XTAL)
18058 + pll_delay += XTAL_ON_DELAY;
18059 +
18060 + /* Starting with 4318 it is ILP that is used for the delays */
18061 + slowmaxfreq = sb_slowclk_freq(sbh, (si->ccrev >= 10) ? FALSE : TRUE);
18062 +
18063 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
18064 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
18065 +
18066 + cc = (chipcregs_t *)chipcregs;
18067 + W_REG(&cc->pll_on_delay, pll_on_delay);
18068 + W_REG(&cc->fref_sel_delay, fref_sel_delay);
18069 +}
18070 +
18071 +/* set or get slow clock divider */
18072 +int
18073 +sb_pwrctl_slowclk(void *sbh, bool set, uint *div)
18074 +{
18075 + sb_info_t *si;
18076 + uint origidx;
18077 + chipcregs_t *cc;
18078 + uint intr_val = 0;
18079 + uint err = 0;
18080 +
18081 + si = SB_INFO(sbh);
18082 +
18083 + /* chipcommon cores prior to rev6 don't support slowclkcontrol */
18084 + if (si->ccrev < 6)
18085 + return 1;
18086 +
18087 + /* chipcommon cores rev10 are a whole new ball game */
18088 + if (si->ccrev >= 10)
18089 + return 1;
18090 +
18091 + if (set && ((*div % 4) || (*div < 4)))
18092 + return 2;
18093 +
18094 + INTR_OFF(si, intr_val);
18095 + origidx = si->curidx;
18096 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
18097 + ASSERT(cc != NULL);
18098 +
18099 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL)) {
18100 + err = 3;
18101 + goto done;
18102 + }
18103 +
18104 + if (set) {
18105 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, ((*div / 4 - 1) << SCC_CD_SHF));
18106 + sb_pwrctl_setdelay(sbh, (void *)cc);
18107 + } else
18108 + *div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHF) + 1);
18109 +
18110 +done:
18111 + sb_setcoreidx(sbh, origidx);
18112 + INTR_RESTORE(si, intr_val);
18113 + return err;
18114 +}
18115 +
18116 +/* initialize power control delay registers */
18117 +void
18118 +sb_pwrctl_init(void *sbh)
18119 +{
18120 + sb_info_t *si;
18121 + uint origidx;
18122 + chipcregs_t *cc;
18123 +
18124 + si = SB_INFO(sbh);
18125 +
18126 + origidx = si->curidx;
18127 +
18128 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
18129 + return;
18130 +
18131 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
18132 + goto done;
18133 +
18134 + /* 4317pc does not work with SlowClock less than 5Mhz */
18135 + if (BUSTYPE(si->bustype) == PCMCIA_BUS) {
18136 + if ((si->ccrev >= 6) && (si->ccrev < 10))
18137 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, (SCC_DEF_DIV << SCC_CD_SHF));
18138 + }
18139 +
18140 + sb_pwrctl_setdelay(sbh, (void *)cc);
18141 +
18142 +done:
18143 + sb_setcoreidx(sbh, origidx);
18144 +}
18145 +
18146 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
18147 +uint16
18148 +sb_pwrctl_fast_pwrup_delay(void *sbh)
18149 +{
18150 + sb_info_t *si;
18151 + uint origidx;
18152 + chipcregs_t *cc;
18153 + uint slowminfreq;
18154 + uint16 fpdelay;
18155 + uint intr_val = 0;
18156 +
18157 + si = SB_INFO(sbh);
18158 + fpdelay = 0;
18159 + origidx = si->curidx;
18160 +
18161 + if (BUSTYPE(si->bustype) == SB_BUS)
18162 + goto done;
18163 +
18164 + INTR_OFF(si, intr_val);
18165 +
18166 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
18167 + goto done;
18168 +
18169 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
18170 + goto done;
18171 +
18172 + slowminfreq = sb_slowclk_freq(sbh, FALSE);
18173 + fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) + (slowminfreq - 1)) / slowminfreq;
18174 +
18175 +done:
18176 + sb_setcoreidx(sbh, origidx);
18177 + INTR_RESTORE(si, intr_val);
18178 + return (fpdelay);
18179 +}
18180 +
18181 +/* turn primary xtal and/or pll off/on */
18182 +int
18183 +sb_pwrctl_xtal(void *sbh, uint what, bool on)
18184 +{
18185 + sb_info_t *si;
18186 + uint32 in, out, outen;
18187 +
18188 + si = SB_INFO(sbh);
18189 +
18190 + switch (BUSTYPE(si->bustype)) {
18191 +
18192 +
18193 + case PCMCIA_BUS:
18194 + return (0);
18195 +
18196 +
18197 + case PCI_BUS:
18198 +
18199 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof (uint32));
18200 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
18201 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32));
18202 +
18203 + /*
18204 + * Avoid glitching the clock if GPRS is already using it.
18205 + * We can't actually read the state of the PLLPD so we infer it
18206 + * by the value of XTAL_PU which *is* readable via gpioin.
18207 + */
18208 + if (on && (in & PCI_CFG_GPIO_XTAL))
18209 + return (0);
18210 +
18211 + if (what & XTAL)
18212 + outen |= PCI_CFG_GPIO_XTAL;
18213 + if (what & PLL)
18214 + outen |= PCI_CFG_GPIO_PLL;
18215 +
18216 + if (on) {
18217 + /* turn primary xtal on */
18218 + if (what & XTAL) {
18219 + out |= PCI_CFG_GPIO_XTAL;
18220 + if (what & PLL)
18221 + out |= PCI_CFG_GPIO_PLL;
18222 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
18223 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
18224 + OSL_DELAY(XTAL_ON_DELAY);
18225 + }
18226 +
18227 + /* turn pll on */
18228 + if (what & PLL) {
18229 + out &= ~PCI_CFG_GPIO_PLL;
18230 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
18231 + OSL_DELAY(2000);
18232 + }
18233 + } else {
18234 + if (what & XTAL)
18235 + out &= ~PCI_CFG_GPIO_XTAL;
18236 + if (what & PLL)
18237 + out |= PCI_CFG_GPIO_PLL;
18238 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
18239 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
18240 + }
18241 +
18242 + default:
18243 + return (-1);
18244 + }
18245 +
18246 + return (0);
18247 +}
18248 +
18249 +/* set dynamic power control mode (forceslow, forcefast, dynamic) */
18250 +/* returns true if ignore pll off is set and false if it is not */
18251 +bool
18252 +sb_pwrctl_clk(void *sbh, uint mode)
18253 +{
18254 + sb_info_t *si;
18255 + uint origidx;
18256 + chipcregs_t *cc;
18257 + uint32 scc;
18258 + bool forcefastclk=FALSE;
18259 + uint intr_val = 0;
18260 +
18261 + si = SB_INFO(sbh);
18262 +
18263 + /* chipcommon cores prior to rev6 don't support slowclkcontrol */
18264 + if (si->ccrev < 6)
18265 + return (FALSE);
18266 +
18267 + /* chipcommon cores rev10 are a whole new ball game */
18268 + if (si->ccrev >= 10)
18269 + return (FALSE);
18270 +
18271 + INTR_OFF(si, intr_val);
18272 +
18273 + origidx = si->curidx;
18274 +
18275 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
18276 + ASSERT(cc != NULL);
18277 +
18278 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
18279 + goto done;
18280 +
18281 + switch (mode) {
18282 + case CLK_FAST: /* force fast (pll) clock */
18283 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
18284 + sb_pwrctl_xtal(sbh, XTAL, ON);
18285 +
18286 + SET_REG(&cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
18287 + break;
18288 +
18289 + case CLK_SLOW: /* force slow clock */
18290 + if ((BUSTYPE(si->bustype) == SDIO_BUS) || (BUSTYPE(si->bustype) == PCMCIA_BUS))
18291 + return (-1);
18292 +
18293 + if (si->ccrev >= 6)
18294 + OR_REG(&cc->slow_clk_ctl, SCC_FS);
18295 + break;
18296 +
18297 + case CLK_DYNAMIC: /* enable dynamic power control */
18298 + scc = R_REG(&cc->slow_clk_ctl);
18299 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
18300 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
18301 + scc |= SCC_XC;
18302 + W_REG(&cc->slow_clk_ctl, scc);
18303 +
18304 + /* for dynamic control, we have to release our xtal_pu "force on" */
18305 + if (scc & SCC_XC)
18306 + sb_pwrctl_xtal(sbh, XTAL, OFF);
18307 + break;
18308 + }
18309 +
18310 + /* Is the h/w forcing the use of the fast clk */
18311 + forcefastclk = (bool)((R_REG(&cc->slow_clk_ctl) & SCC_IP) == SCC_IP);
18312 +
18313 +done:
18314 + sb_setcoreidx(sbh, origidx);
18315 + INTR_RESTORE(si, intr_val);
18316 + return (forcefastclk);
18317 +}
18318 +
18319 +/* register driver interrupt disabling and restoring callback functions */
18320 +void
18321 +sb_register_intr_callback(void *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg)
18322 +{
18323 + sb_info_t *si;
18324 +
18325 + si = SB_INFO(sbh);
18326 + si->intr_arg = intr_arg;
18327 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
18328 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
18329 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
18330 + /* save current core id. when this function called, the current core
18331 + * must be the core which provides driver functions(il, et, wl, etc.)
18332 + */
18333 + si->dev_coreid = si->coreid[si->curidx];
18334 +}
18335 +
18336 +
18337 diff -Nur linux-2.4.30/drivers/net/hnd/shared_ksyms.sh linux-2.4.30-brcm/drivers/net/hnd/shared_ksyms.sh
18338 --- linux-2.4.30/drivers/net/hnd/shared_ksyms.sh 1970-01-01 01:00:00.000000000 +0100
18339 +++ linux-2.4.30-brcm/drivers/net/hnd/shared_ksyms.sh 2005-05-22 22:55:51.000000000 +0200
18340 @@ -0,0 +1,21 @@
18341 +#!/bin/sh
18342 +#
18343 +# Copyright 2004, Broadcom Corporation
18344 +# All Rights Reserved.
18345 +#
18346 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
18347 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
18348 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
18349 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
18350 +#
18351 +# $Id: shared_ksyms.sh,v 1.1 2005/03/16 13:50:00 wbx Exp $
18352 +#
18353 +
18354 +cat <<EOF
18355 +#include <linux/config.h>
18356 +#include <linux/module.h>
18357 +EOF
18358 +
18359 +for file in $* ; do
18360 + ${NM} $file | sed -ne 's/[0-9A-Fa-f]* [DT] \([^ ]*\)/extern void \1; EXPORT_SYMBOL(\1);/p'
18361 +done
18362 diff -Nur linux-2.4.30/drivers/net/Makefile linux-2.4.30-brcm/drivers/net/Makefile
18363 --- linux-2.4.30/drivers/net/Makefile 2005-01-19 15:09:56.000000000 +0100
18364 +++ linux-2.4.30-brcm/drivers/net/Makefile 2005-05-25 19:07:52.000000000 +0200
18365 @@ -3,6 +3,8 @@
18366 # Makefile for the Linux network (ethercard) device drivers.
18367 #
18368
18369 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
18370 +
18371 obj-y :=
18372 obj-m :=
18373 obj-n :=
18374 @@ -21,6 +23,8 @@
18375 list-multi := rcpci.o
18376 rcpci-objs := rcpci45.o rclanmtl.o
18377
18378 +subdir-m += diag
18379 +
18380 ifeq ($(CONFIG_TULIP),y)
18381 obj-y += tulip/tulip.o
18382 endif
18383 @@ -39,6 +43,9 @@
18384 obj-$(CONFIG_ISDN) += slhc.o
18385 endif
18386
18387 +subdir-$(CONFIG_HND) += hnd
18388 +subdir-$(CONFIG_ET) += et
18389 +subdir-$(CONFIG_WL) += wl
18390 subdir-$(CONFIG_NET_PCMCIA) += pcmcia
18391 subdir-$(CONFIG_NET_WIRELESS) += wireless
18392 subdir-$(CONFIG_TULIP) += tulip
18393 @@ -69,6 +76,16 @@
18394 obj-$(CONFIG_MYRI_SBUS) += myri_sbus.o
18395 obj-$(CONFIG_SUNGEM) += sungem.o
18396
18397 +ifeq ($(CONFIG_HND),y)
18398 + obj-y += hnd/hnd.o
18399 +endif
18400 +ifeq ($(CONFIG_ET),y)
18401 + obj-y += et/et.o
18402 +endif
18403 +ifeq ($(CONFIG_WL),y)
18404 + obj-y += wl/wl.o
18405 +endif
18406 +
18407 obj-$(CONFIG_MACE) += mace.o
18408 obj-$(CONFIG_BMAC) += bmac.o
18409 obj-$(CONFIG_GMAC) += gmac.o
18410 @@ -265,6 +282,7 @@
18411 endif
18412 endif
18413
18414 +
18415 include $(TOPDIR)/Rules.make
18416
18417 clean:
18418 diff -Nur linux-2.4.30/drivers/net/wireless/Config.in linux-2.4.30-brcm/drivers/net/wireless/Config.in
18419 --- linux-2.4.30/drivers/net/wireless/Config.in 2004-11-17 12:54:21.000000000 +0100
18420 +++ linux-2.4.30-brcm/drivers/net/wireless/Config.in 2005-05-22 22:55:52.000000000 +0200
18421 @@ -13,6 +13,7 @@
18422 fi
18423
18424 if [ "$CONFIG_PCI" = "y" ]; then
18425 + dep_tristate ' Proprietary Broadcom BCM43xx 802.11 Wireless support' CONFIG_WL
18426 dep_tristate ' Hermes in PLX9052 based PCI adaptor support (Netgear MA301 etc.) (EXPERIMENTAL)' CONFIG_PLX_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
18427 dep_tristate ' Hermes in TMD7160/NCP130 based PCI adaptor support (Pheecom WL-PCI etc.) (EXPERIMENTAL)' CONFIG_TMD_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
18428 dep_tristate ' Prism 2.5 PCI 802.11b adaptor support (EXPERIMENTAL)' CONFIG_PCI_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
18429 diff -Nur linux-2.4.30/drivers/net/wl/Makefile linux-2.4.30-brcm/drivers/net/wl/Makefile
18430 --- linux-2.4.30/drivers/net/wl/Makefile 1970-01-01 01:00:00.000000000 +0100
18431 +++ linux-2.4.30-brcm/drivers/net/wl/Makefile 2005-05-26 12:04:50.000000000 +0200
18432 @@ -0,0 +1,26 @@
18433 +#
18434 +# Makefile for the Broadcom wl driver
18435 +#
18436 +# Copyright 2004, Broadcom Corporation
18437 +# All Rights Reserved.
18438 +#
18439 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
18440 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
18441 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
18442 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
18443 +#
18444 +# $Id: Makefile,v 1.2 2005/03/29 03:32:18 mbm Exp $
18445 +
18446 +EXTRA_CFLAGS += -I$(TOPDIR)/arch/mips/bcm947xx/include
18447 +
18448 +O_TARGET := wl.o
18449 +
18450 +obj-y := apsta_aeskeywrap.o apsta_aes.o apsta_bcmwpa.o apsta_d11ucode.o
18451 +obj-y += apsta_hmac.o apsta_md5.o apsta_passhash.o apsta_prf.o apsta_rc4.o
18452 +obj-y += apsta_rijndael-alg-fst.o apsta_sha1.o apsta_tkhash.o apsta_wlc_led.o
18453 +obj-y += apsta_wlc_phy.o apsta_wlc_rate.o apsta_wlc_security.o
18454 +obj-y += apsta_wlc_sup.o apsta_wlc_wet.o apsta_wl_linux.o apsta_wlc.o
18455 +
18456 +obj-m := $(O_TARGET)
18457 +
18458 +include $(TOPDIR)/Rules.make
18459 diff -Nur linux-2.4.30/drivers/parport/Config.in linux-2.4.30-brcm/drivers/parport/Config.in
18460 --- linux-2.4.30/drivers/parport/Config.in 2004-02-18 14:36:31.000000000 +0100
18461 +++ linux-2.4.30-brcm/drivers/parport/Config.in 2005-05-22 22:55:52.000000000 +0200
18462 @@ -11,6 +11,7 @@
18463 tristate 'Parallel port support' CONFIG_PARPORT
18464 if [ "$CONFIG_PARPORT" != "n" ]; then
18465 dep_tristate ' PC-style hardware' CONFIG_PARPORT_PC $CONFIG_PARPORT
18466 + dep_tristate ' Asus WL500g parallel port' CONFIG_PARPORT_SPLINK $CONFIG_PARPORT
18467 if [ "$CONFIG_PARPORT_PC" != "n" -a "$CONFIG_SERIAL" != "n" ]; then
18468 if [ "$CONFIG_SERIAL" = "m" ]; then
18469 define_tristate CONFIG_PARPORT_PC_CML1 m
18470 diff -Nur linux-2.4.30/drivers/parport/Makefile linux-2.4.30-brcm/drivers/parport/Makefile
18471 --- linux-2.4.30/drivers/parport/Makefile 2004-08-08 01:26:05.000000000 +0200
18472 +++ linux-2.4.30-brcm/drivers/parport/Makefile 2005-05-22 22:55:52.000000000 +0200
18473 @@ -22,6 +22,7 @@
18474
18475 obj-$(CONFIG_PARPORT) += parport.o
18476 obj-$(CONFIG_PARPORT_PC) += parport_pc.o
18477 +obj-$(CONFIG_PARPORT_SPLINK) += parport_splink.o
18478 obj-$(CONFIG_PARPORT_PC_PCMCIA) += parport_cs.o
18479 obj-$(CONFIG_PARPORT_AMIGA) += parport_amiga.o
18480 obj-$(CONFIG_PARPORT_MFC3) += parport_mfc3.o
18481 diff -Nur linux-2.4.30/drivers/parport/parport_splink.c linux-2.4.30-brcm/drivers/parport/parport_splink.c
18482 --- linux-2.4.30/drivers/parport/parport_splink.c 1970-01-01 01:00:00.000000000 +0100
18483 +++ linux-2.4.30-brcm/drivers/parport/parport_splink.c 2005-05-22 22:55:52.000000000 +0200
18484 @@ -0,0 +1,345 @@
18485 +/* Low-level parallel port routines for the ASUS WL-500g built-in port
18486 + *
18487 + * Author: Nuno Grilo <nuno.grilo@netcabo.pt>
18488 + * Based on parport_pc source
18489 + */
18490 +
18491 +#include <linux/config.h>
18492 +#include <linux/module.h>
18493 +#include <linux/init.h>
18494 +#include <linux/ioport.h>
18495 +#include <linux/kernel.h>
18496 +#include <linux/slab.h>
18497 +#include <linux/parport.h>
18498 +#include <linux/parport_pc.h>
18499 +
18500 +#define SPLINK_ADDRESS 0xBF800010
18501 +
18502 +#undef DEBUG
18503 +
18504 +#ifdef DEBUG
18505 +#define DPRINTK printk
18506 +#else
18507 +#define DPRINTK(stuff...)
18508 +#endif
18509 +
18510 +
18511 +/* __parport_splink_frob_control differs from parport_splink_frob_control in that
18512 + * it doesn't do any extra masking. */
18513 +static __inline__ unsigned char __parport_splink_frob_control (struct parport *p,
18514 + unsigned char mask,
18515 + unsigned char val)
18516 +{
18517 + struct parport_pc_private *priv = p->physport->private_data;
18518 + unsigned char *io = (unsigned char *) p->base;
18519 + unsigned char ctr = priv->ctr;
18520 +#ifdef DEBUG_PARPORT
18521 + printk (KERN_DEBUG
18522 + "__parport_splink_frob_control(%02x,%02x): %02x -> %02x\n",
18523 + mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable);
18524 +#endif
18525 + ctr = (ctr & ~mask) ^ val;
18526 + ctr &= priv->ctr_writable; /* only write writable bits. */
18527 + *(io+2) = ctr;
18528 + priv->ctr = ctr; /* Update soft copy */
18529 + return ctr;
18530 +}
18531 +
18532 +
18533 +
18534 +static void parport_splink_data_forward (struct parport *p)
18535 +{
18536 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
18537 + __parport_splink_frob_control (p, 0x20, 0);
18538 +}
18539 +
18540 +static void parport_splink_data_reverse (struct parport *p)
18541 +{
18542 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
18543 + __parport_splink_frob_control (p, 0x20, 0x20);
18544 +}
18545 +
18546 +/*
18547 +static void parport_splink_interrupt(int irq, void *dev_id, struct pt_regs *regs)
18548 +{
18549 + DPRINTK(KERN_DEBUG "parport_splink: IRQ handler called\n");
18550 + parport_generic_irq(irq, (struct parport *) dev_id, regs);
18551 +}
18552 +*/
18553 +
18554 +static void parport_splink_enable_irq(struct parport *p)
18555 +{
18556 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_enable_irq called\n");
18557 + __parport_splink_frob_control (p, 0x10, 0x10);
18558 +}
18559 +
18560 +static void parport_splink_disable_irq(struct parport *p)
18561 +{
18562 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_disable_irq called\n");
18563 + __parport_splink_frob_control (p, 0x10, 0);
18564 +}
18565 +
18566 +static void parport_splink_init_state(struct pardevice *dev, struct parport_state *s)
18567 +{
18568 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_init_state called\n");
18569 + s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0);
18570 + if (dev->irq_func &&
18571 + dev->port->irq != PARPORT_IRQ_NONE)
18572 + /* Set ackIntEn */
18573 + s->u.pc.ctr |= 0x10;
18574 +}
18575 +
18576 +static void parport_splink_save_state(struct parport *p, struct parport_state *s)
18577 +{
18578 + const struct parport_pc_private *priv = p->physport->private_data;
18579 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_save_state called\n");
18580 + s->u.pc.ctr = priv->ctr;
18581 +}
18582 +
18583 +static void parport_splink_restore_state(struct parport *p, struct parport_state *s)
18584 +{
18585 + struct parport_pc_private *priv = p->physport->private_data;
18586 + unsigned char *io = (unsigned char *) p->base;
18587 + unsigned char ctr = s->u.pc.ctr;
18588 +
18589 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_restore_state called\n");
18590 + *(io+2) = ctr;
18591 + priv->ctr = ctr;
18592 +}
18593 +
18594 +static void parport_splink_setup_interrupt(void) {
18595 + return;
18596 +}
18597 +
18598 +static void parport_splink_write_data(struct parport *p, unsigned char d) {
18599 + DPRINTK(KERN_DEBUG "parport_splink: write data called\n");
18600 + unsigned char *io = (unsigned char *) p->base;
18601 + *io = d;
18602 +}
18603 +
18604 +static unsigned char parport_splink_read_data(struct parport *p) {
18605 + DPRINTK(KERN_DEBUG "parport_splink: read data called\n");
18606 + unsigned char *io = (unsigned char *) p->base;
18607 + return *io;
18608 +}
18609 +
18610 +static void parport_splink_write_control(struct parport *p, unsigned char d)
18611 +{
18612 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
18613 + PARPORT_CONTROL_AUTOFD |
18614 + PARPORT_CONTROL_INIT |
18615 + PARPORT_CONTROL_SELECT);
18616 +
18617 + DPRINTK(KERN_DEBUG "parport_splink: write control called\n");
18618 + /* Take this out when drivers have adapted to the newer interface. */
18619 + if (d & 0x20) {
18620 + printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n",
18621 + p->name, p->cad->name);
18622 + parport_splink_data_reverse (p);
18623 + }
18624 +
18625 + __parport_splink_frob_control (p, wm, d & wm);
18626 +}
18627 +
18628 +static unsigned char parport_splink_read_control(struct parport *p)
18629 +{
18630 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
18631 + PARPORT_CONTROL_AUTOFD |
18632 + PARPORT_CONTROL_INIT |
18633 + PARPORT_CONTROL_SELECT);
18634 + DPRINTK(KERN_DEBUG "parport_splink: read control called\n");
18635 + const struct parport_pc_private *priv = p->physport->private_data;
18636 + return priv->ctr & wm; /* Use soft copy */
18637 +}
18638 +
18639 +static unsigned char parport_splink_frob_control (struct parport *p, unsigned char mask,
18640 + unsigned char val)
18641 +{
18642 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
18643 + PARPORT_CONTROL_AUTOFD |
18644 + PARPORT_CONTROL_INIT |
18645 + PARPORT_CONTROL_SELECT);
18646 +
18647 + DPRINTK(KERN_DEBUG "parport_splink: frob control called\n");
18648 + /* Take this out when drivers have adapted to the newer interface. */
18649 + if (mask & 0x20) {
18650 + printk (KERN_DEBUG "%s (%s): use data_%s for this!\n",
18651 + p->name, p->cad->name,
18652 + (val & 0x20) ? "reverse" : "forward");
18653 + if (val & 0x20)
18654 + parport_splink_data_reverse (p);
18655 + else
18656 + parport_splink_data_forward (p);
18657 + }
18658 +
18659 + /* Restrict mask and val to control lines. */
18660 + mask &= wm;
18661 + val &= wm;
18662 +
18663 + return __parport_splink_frob_control (p, mask, val);
18664 +}
18665 +
18666 +static unsigned char parport_splink_read_status(struct parport *p)
18667 +{
18668 + DPRINTK(KERN_DEBUG "parport_splink: read status called\n");
18669 + unsigned char *io = (unsigned char *) p->base;
18670 + return *(io+1);
18671 +}
18672 +
18673 +static void parport_splink_inc_use_count(void)
18674 +{
18675 +#ifdef MODULE
18676 + MOD_INC_USE_COUNT;
18677 +#endif
18678 +}
18679 +
18680 +static void parport_splink_dec_use_count(void)
18681 +{
18682 +#ifdef MODULE
18683 + MOD_DEC_USE_COUNT;
18684 +#endif
18685 +}
18686 +
18687 +static struct parport_operations parport_splink_ops =
18688 +{
18689 + parport_splink_write_data,
18690 + parport_splink_read_data,
18691 +
18692 + parport_splink_write_control,
18693 + parport_splink_read_control,
18694 + parport_splink_frob_control,
18695 +
18696 + parport_splink_read_status,
18697 +
18698 + parport_splink_enable_irq,
18699 + parport_splink_disable_irq,
18700 +
18701 + parport_splink_data_forward,
18702 + parport_splink_data_reverse,
18703 +
18704 + parport_splink_init_state,
18705 + parport_splink_save_state,
18706 + parport_splink_restore_state,
18707 +
18708 + parport_splink_inc_use_count,
18709 + parport_splink_dec_use_count,
18710 +
18711 + parport_ieee1284_epp_write_data,
18712 + parport_ieee1284_epp_read_data,
18713 + parport_ieee1284_epp_write_addr,
18714 + parport_ieee1284_epp_read_addr,
18715 +
18716 + parport_ieee1284_ecp_write_data,
18717 + parport_ieee1284_ecp_read_data,
18718 + parport_ieee1284_ecp_write_addr,
18719 +
18720 + parport_ieee1284_write_compat,
18721 + parport_ieee1284_read_nibble,
18722 + parport_ieee1284_read_byte,
18723 +};
18724 +
18725 +/* --- Initialisation code -------------------------------- */
18726 +
18727 +static struct parport *parport_splink_probe_port (unsigned long int base)
18728 +{
18729 + struct parport_pc_private *priv;
18730 + struct parport_operations *ops;
18731 + struct parport *p;
18732 +
18733 + if (check_mem_region(base, 3)) {
18734 + printk (KERN_DEBUG "parport (0x%lx): iomem region not available\n", base);
18735 + return NULL;
18736 + }
18737 + priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
18738 + if (!priv) {
18739 + printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base);
18740 + return NULL;
18741 + }
18742 + ops = kmalloc (sizeof (struct parport_operations), GFP_KERNEL);
18743 + if (!ops) {
18744 + printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n",
18745 + base);
18746 + kfree (priv);
18747 + return NULL;
18748 + }
18749 + memcpy (ops, &parport_splink_ops, sizeof (struct parport_operations));
18750 + priv->ctr = 0xc;
18751 + priv->ctr_writable = 0xff;
18752 +
18753 + if (!(p = parport_register_port(base, PARPORT_IRQ_NONE,
18754 + PARPORT_DMA_NONE, ops))) {
18755 + printk (KERN_DEBUG "parport (0x%lx): registration failed!\n",
18756 + base);
18757 + kfree (priv);
18758 + kfree (ops);
18759 + return NULL;
18760 + }
18761 +
18762 + p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
18763 + p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
18764 + p->private_data = priv;
18765 +
18766 + parport_proc_register(p);
18767 + request_mem_region (p->base, 3, p->name);
18768 +
18769 + /* Done probing. Now put the port into a sensible start-up state. */
18770 + parport_splink_write_data(p, 0);
18771 + parport_splink_data_forward (p);
18772 +
18773 + /* Now that we've told the sharing engine about the port, and
18774 + found out its characteristics, let the high-level drivers
18775 + know about it. */
18776 + parport_announce_port (p);
18777 +
18778 + DPRINTK(KERN_DEBUG "parport (0x%lx): init ok!\n",
18779 + base);
18780 + return p;
18781 +}
18782 +
18783 +static void parport_splink_unregister_port(struct parport *p) {
18784 + struct parport_pc_private *priv = p->private_data;
18785 + struct parport_operations *ops = p->ops;
18786 +
18787 + if (p->irq != PARPORT_IRQ_NONE)
18788 + free_irq(p->irq, p);
18789 + release_mem_region(p->base, 3);
18790 + parport_proc_unregister(p);
18791 + kfree (priv);
18792 + parport_unregister_port(p);
18793 + kfree (ops);
18794 +}
18795 +
18796 +
18797 +int parport_splink_init(void)
18798 +{
18799 + int ret;
18800 +
18801 + DPRINTK(KERN_DEBUG "parport_splink init called\n");
18802 + parport_splink_setup_interrupt();
18803 + ret = !parport_splink_probe_port(SPLINK_ADDRESS);
18804 +
18805 + return ret;
18806 +}
18807 +
18808 +void parport_splink_cleanup(void) {
18809 + struct parport *p = parport_enumerate(), *tmp;
18810 + DPRINTK(KERN_DEBUG "parport_splink cleanup called\n");
18811 + if (p->size) {
18812 + if (p->modes & PARPORT_MODE_PCSPP) {
18813 + while(p) {
18814 + tmp = p->next;
18815 + parport_splink_unregister_port(p);
18816 + p = tmp;
18817 + }
18818 + }
18819 + }
18820 +}
18821 +
18822 +MODULE_AUTHOR("Nuno Grilo <nuno.grilo@netcabo.pt>");
18823 +MODULE_DESCRIPTION("Parport Driver for ASUS WL-500g router builtin Port");
18824 +MODULE_SUPPORTED_DEVICE("ASUS WL-500g builtin Parallel Port");
18825 +MODULE_LICENSE("GPL");
18826 +
18827 +module_init(parport_splink_init)
18828 +module_exit(parport_splink_cleanup)
18829 +
18830 diff -Nur linux-2.4.30/drivers/pcmcia/bcm4710_generic.c linux-2.4.30-brcm/drivers/pcmcia/bcm4710_generic.c
18831 --- linux-2.4.30/drivers/pcmcia/bcm4710_generic.c 1970-01-01 01:00:00.000000000 +0100
18832 +++ linux-2.4.30-brcm/drivers/pcmcia/bcm4710_generic.c 2005-05-22 22:55:52.000000000 +0200
18833 @@ -0,0 +1,912 @@
18834 +/*
18835 + *
18836 + * bcm47xx pcmcia driver
18837 + *
18838 + * Copyright 2004, Broadcom Corporation
18839 + * All Rights Reserved.
18840 + *
18841 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
18842 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
18843 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
18844 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
18845 + *
18846 + * Based on sa1100_generic.c from www.handhelds.org,
18847 + * and au1000_generic.c from oss.sgi.com.
18848 + *
18849 + * $Id: bcm4710_generic.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
18850 + */
18851 +#include <linux/module.h>
18852 +#include <linux/init.h>
18853 +#include <linux/config.h>
18854 +#include <linux/delay.h>
18855 +#include <linux/ioport.h>
18856 +#include <linux/kernel.h>
18857 +#include <linux/tqueue.h>
18858 +#include <linux/timer.h>
18859 +#include <linux/mm.h>
18860 +#include <linux/proc_fs.h>
18861 +#include <linux/version.h>
18862 +#include <linux/types.h>
18863 +#include <linux/vmalloc.h>
18864 +
18865 +#include <pcmcia/version.h>
18866 +#include <pcmcia/cs_types.h>
18867 +#include <pcmcia/cs.h>
18868 +#include <pcmcia/ss.h>
18869 +#include <pcmcia/bulkmem.h>
18870 +#include <pcmcia/cistpl.h>
18871 +#include <pcmcia/bus_ops.h>
18872 +#include "cs_internal.h"
18873 +
18874 +#include <asm/io.h>
18875 +#include <asm/irq.h>
18876 +#include <asm/system.h>
18877 +
18878 +#include <typedefs.h>
18879 +#include <bcm4710.h>
18880 +#include <sbextif.h>
18881 +
18882 +#include "bcm4710pcmcia.h"
18883 +
18884 +#ifdef PCMCIA_DEBUG
18885 +static int pc_debug = PCMCIA_DEBUG;
18886 +#endif
18887 +
18888 +MODULE_DESCRIPTION("Linux PCMCIA Card Services: bcm47xx Socket Controller");
18889 +
18890 +/* This structure maintains housekeeping state for each socket, such
18891 + * as the last known values of the card detect pins, or the Card Services
18892 + * callback value associated with the socket:
18893 + */
18894 +static struct bcm47xx_pcmcia_socket *pcmcia_socket;
18895 +static int socket_count;
18896 +
18897 +
18898 +/* Returned by the low-level PCMCIA interface: */
18899 +static struct pcmcia_low_level *pcmcia_low_level;
18900 +
18901 +/* Event poll timer structure */
18902 +static struct timer_list poll_timer;
18903 +
18904 +
18905 +/* Prototypes for routines which are used internally: */
18906 +
18907 +static int bcm47xx_pcmcia_driver_init(void);
18908 +static void bcm47xx_pcmcia_driver_shutdown(void);
18909 +static void bcm47xx_pcmcia_task_handler(void *data);
18910 +static void bcm47xx_pcmcia_poll_event(unsigned long data);
18911 +static void bcm47xx_pcmcia_interrupt(int irq, void *dev, struct pt_regs *regs);
18912 +static struct tq_struct bcm47xx_pcmcia_task;
18913 +
18914 +#ifdef CONFIG_PROC_FS
18915 +static int bcm47xx_pcmcia_proc_status(char *buf, char **start,
18916 + off_t pos, int count, int *eof, void *data);
18917 +#endif
18918 +
18919 +
18920 +/* Prototypes for operations which are exported to the
18921 + * in-kernel PCMCIA core:
18922 + */
18923 +
18924 +static int bcm47xx_pcmcia_init(unsigned int sock);
18925 +static int bcm47xx_pcmcia_suspend(unsigned int sock);
18926 +static int bcm47xx_pcmcia_register_callback(unsigned int sock,
18927 + void (*handler)(void *, unsigned int), void *info);
18928 +static int bcm47xx_pcmcia_inquire_socket(unsigned int sock, socket_cap_t *cap);
18929 +static int bcm47xx_pcmcia_get_status(unsigned int sock, u_int *value);
18930 +static int bcm47xx_pcmcia_get_socket(unsigned int sock, socket_state_t *state);
18931 +static int bcm47xx_pcmcia_set_socket(unsigned int sock, socket_state_t *state);
18932 +static int bcm47xx_pcmcia_get_io_map(unsigned int sock, struct pccard_io_map *io);
18933 +static int bcm47xx_pcmcia_set_io_map(unsigned int sock, struct pccard_io_map *io);
18934 +static int bcm47xx_pcmcia_get_mem_map(unsigned int sock, struct pccard_mem_map *mem);
18935 +static int bcm47xx_pcmcia_set_mem_map(unsigned int sock, struct pccard_mem_map *mem);
18936 +#ifdef CONFIG_PROC_FS
18937 +static void bcm47xx_pcmcia_proc_setup(unsigned int sock, struct proc_dir_entry *base);
18938 +#endif
18939 +
18940 +static struct pccard_operations bcm47xx_pcmcia_operations = {
18941 + bcm47xx_pcmcia_init,
18942 + bcm47xx_pcmcia_suspend,
18943 + bcm47xx_pcmcia_register_callback,
18944 + bcm47xx_pcmcia_inquire_socket,
18945 + bcm47xx_pcmcia_get_status,
18946 + bcm47xx_pcmcia_get_socket,
18947 + bcm47xx_pcmcia_set_socket,
18948 + bcm47xx_pcmcia_get_io_map,
18949 + bcm47xx_pcmcia_set_io_map,
18950 + bcm47xx_pcmcia_get_mem_map,
18951 + bcm47xx_pcmcia_set_mem_map,
18952 +#ifdef CONFIG_PROC_FS
18953 + bcm47xx_pcmcia_proc_setup
18954 +#endif
18955 +};
18956 +
18957 +
18958 +/*
18959 + * bcm47xx_pcmcia_driver_init()
18960 + *
18961 + * This routine performs a basic sanity check to ensure that this
18962 + * kernel has been built with the appropriate board-specific low-level
18963 + * PCMCIA support, performs low-level PCMCIA initialization, registers
18964 + * this socket driver with Card Services, and then spawns the daemon
18965 + * thread which is the real workhorse of the socket driver.
18966 + *
18967 + * Please see linux/Documentation/arm/SA1100/PCMCIA for more information
18968 + * on the low-level kernel interface.
18969 + *
18970 + * Returns: 0 on success, -1 on error
18971 + */
18972 +static int __init bcm47xx_pcmcia_driver_init(void)
18973 +{
18974 + servinfo_t info;
18975 + struct pcmcia_init pcmcia_init;
18976 + struct pcmcia_state state;
18977 + unsigned int i;
18978 + unsigned long tmp;
18979 +
18980 +
18981 + printk("\nBCM47XX PCMCIA (CS release %s)\n", CS_RELEASE);
18982 +
18983 + CardServices(GetCardServicesInfo, &info);
18984 +
18985 + if (info.Revision != CS_RELEASE_CODE) {
18986 + printk(KERN_ERR "Card Services release codes do not match\n");
18987 + return -1;
18988 + }
18989 +
18990 +#ifdef CONFIG_BCM4710
18991 + pcmcia_low_level=&bcm4710_pcmcia_ops;
18992 +#else
18993 +#error Unsupported Broadcom BCM47XX board.
18994 +#endif
18995 +
18996 + pcmcia_init.handler=bcm47xx_pcmcia_interrupt;
18997 +
18998 + if ((socket_count = pcmcia_low_level->init(&pcmcia_init)) < 0) {
18999 + printk(KERN_ERR "Unable to initialize PCMCIA service.\n");
19000 + return -EIO;
19001 + } else {
19002 + printk("\t%d PCMCIA sockets initialized.\n", socket_count);
19003 + }
19004 +
19005 + pcmcia_socket =
19006 + kmalloc(sizeof(struct bcm47xx_pcmcia_socket) * socket_count,
19007 + GFP_KERNEL);
19008 + memset(pcmcia_socket, 0,
19009 + sizeof(struct bcm47xx_pcmcia_socket) * socket_count);
19010 + if (!pcmcia_socket) {
19011 + printk(KERN_ERR "Card Services can't get memory \n");
19012 + return -1;
19013 + }
19014 +
19015 + for (i = 0; i < socket_count; i++) {
19016 + if (pcmcia_low_level->socket_state(i, &state) < 0) {
19017 + printk(KERN_ERR "Unable to get PCMCIA status\n");
19018 + return -EIO;
19019 + }
19020 + pcmcia_socket[i].k_state = state;
19021 + pcmcia_socket[i].cs_state.csc_mask = SS_DETECT;
19022 +
19023 + if (i == 0) {
19024 + pcmcia_socket[i].virt_io =
19025 + (unsigned long)ioremap_nocache(EXTIF_PCMCIA_IOBASE(BCM4710_EXTIF), 0x1000);
19026 + /* Substract ioport base which gets added by in/out */
19027 + pcmcia_socket[i].virt_io -= mips_io_port_base;
19028 + pcmcia_socket[i].phys_attr =
19029 + (unsigned long)EXTIF_PCMCIA_CFGBASE(BCM4710_EXTIF);
19030 + pcmcia_socket[i].phys_mem =
19031 + (unsigned long)EXTIF_PCMCIA_MEMBASE(BCM4710_EXTIF);
19032 + } else {
19033 + printk(KERN_ERR "bcm4710: socket 1 not supported\n");
19034 + return 1;
19035 + }
19036 + }
19037 +
19038 + /* Only advertise as many sockets as we can detect: */
19039 + if (register_ss_entry(socket_count, &bcm47xx_pcmcia_operations) < 0) {
19040 + printk(KERN_ERR "Unable to register socket service routine\n");
19041 + return -ENXIO;
19042 + }
19043 +
19044 + /* Start the event poll timer.
19045 + * It will reschedule by itself afterwards.
19046 + */
19047 + bcm47xx_pcmcia_poll_event(0);
19048 +
19049 + DEBUG(1, "bcm4710: initialization complete\n");
19050 + return 0;
19051 +
19052 +}
19053 +
19054 +module_init(bcm47xx_pcmcia_driver_init);
19055 +
19056 +
19057 +/*
19058 + * bcm47xx_pcmcia_driver_shutdown()
19059 + *
19060 + * Invokes the low-level kernel service to free IRQs associated with this
19061 + * socket controller and reset GPIO edge detection.
19062 + */
19063 +static void __exit bcm47xx_pcmcia_driver_shutdown(void)
19064 +{
19065 + int i;
19066 +
19067 + del_timer_sync(&poll_timer);
19068 + unregister_ss_entry(&bcm47xx_pcmcia_operations);
19069 + pcmcia_low_level->shutdown();
19070 + flush_scheduled_tasks();
19071 + for (i = 0; i < socket_count; i++) {
19072 + if (pcmcia_socket[i].virt_io)
19073 + iounmap((void *)pcmcia_socket[i].virt_io);
19074 + if (pcmcia_socket[i].phys_attr)
19075 + iounmap((void *)pcmcia_socket[i].phys_attr);
19076 + if (pcmcia_socket[i].phys_mem)
19077 + iounmap((void *)pcmcia_socket[i].phys_mem);
19078 + }
19079 + DEBUG(1, "bcm4710: shutdown complete\n");
19080 +}
19081 +
19082 +module_exit(bcm47xx_pcmcia_driver_shutdown);
19083 +
19084 +/*
19085 + * bcm47xx_pcmcia_init()
19086 + * We perform all of the interesting initialization tasks in
19087 + * bcm47xx_pcmcia_driver_init().
19088 + *
19089 + * Returns: 0
19090 + */
19091 +static int bcm47xx_pcmcia_init(unsigned int sock)
19092 +{
19093 + DEBUG(1, "%s(): initializing socket %u\n", __FUNCTION__, sock);
19094 +
19095 + return 0;
19096 +}
19097 +
19098 +/*
19099 + * bcm47xx_pcmcia_suspend()
19100 + *
19101 + * We don't currently perform any actions on a suspend.
19102 + *
19103 + * Returns: 0
19104 + */
19105 +static int bcm47xx_pcmcia_suspend(unsigned int sock)
19106 +{
19107 + DEBUG(1, "%s(): suspending socket %u\n", __FUNCTION__, sock);
19108 +
19109 + return 0;
19110 +}
19111 +
19112 +
19113 +/*
19114 + * bcm47xx_pcmcia_events()
19115 + *
19116 + * Helper routine to generate a Card Services event mask based on
19117 + * state information obtained from the kernel low-level PCMCIA layer
19118 + * in a recent (and previous) sampling. Updates `prev_state'.
19119 + *
19120 + * Returns: an event mask for the given socket state.
19121 + */
19122 +static inline unsigned
19123 +bcm47xx_pcmcia_events(struct pcmcia_state *state,
19124 + struct pcmcia_state *prev_state,
19125 + unsigned int mask, unsigned int flags)
19126 +{
19127 + unsigned int events=0;
19128 +
19129 + if (state->bvd1 != prev_state->bvd1) {
19130 +
19131 + DEBUG(3, "%s(): card BVD1 value %u\n", __FUNCTION__, state->bvd1);
19132 +
19133 + events |= mask & (flags & SS_IOCARD) ? SS_STSCHG : SS_BATDEAD;
19134 + }
19135 +
19136 + if (state->bvd2 != prev_state->bvd2) {
19137 +
19138 + DEBUG(3, "%s(): card BVD2 value %u\n", __FUNCTION__, state->bvd2);
19139 +
19140 + events |= mask & (flags & SS_IOCARD) ? 0 : SS_BATWARN;
19141 + }
19142 +
19143 + if (state->detect != prev_state->detect) {
19144 +
19145 + DEBUG(3, "%s(): card detect value %u\n", __FUNCTION__, state->detect);
19146 +
19147 + events |= mask & SS_DETECT;
19148 + }
19149 +
19150 +
19151 + if (state->ready != prev_state->ready) {
19152 +
19153 + DEBUG(3, "%s(): card ready value %u\n", __FUNCTION__, state->ready);
19154 +
19155 + events |= mask & ((flags & SS_IOCARD) ? 0 : SS_READY);
19156 + }
19157 +
19158 + if (events != 0) {
19159 + DEBUG(2, "events: %s%s%s%s%s\n",
19160 + (events & SS_DETECT) ? "DETECT " : "",
19161 + (events & SS_READY) ? "READY " : "",
19162 + (events & SS_BATDEAD) ? "BATDEAD " : "",
19163 + (events & SS_BATWARN) ? "BATWARN " : "",
19164 + (events & SS_STSCHG) ? "STSCHG " : "");
19165 + }
19166 +
19167 + *prev_state=*state;
19168 + return events;
19169 +}
19170 +
19171 +
19172 +/*
19173 + * bcm47xx_pcmcia_task_handler()
19174 + *
19175 + * Processes serviceable socket events using the "eventd" thread context.
19176 + *
19177 + * Event processing (specifically, the invocation of the Card Services event
19178 + * callback) occurs in this thread rather than in the actual interrupt
19179 + * handler due to the use of scheduling operations in the PCMCIA core.
19180 + */
19181 +static void bcm47xx_pcmcia_task_handler(void *data)
19182 +{
19183 + struct pcmcia_state state;
19184 + int i, events, irq_status;
19185 +
19186 + DEBUG(4, "%s(): entering PCMCIA monitoring thread\n", __FUNCTION__);
19187 +
19188 + for (i = 0; i < socket_count; i++) {
19189 + if ((irq_status = pcmcia_low_level->socket_state(i, &state)) < 0)
19190 + printk(KERN_ERR "Error in kernel low-level PCMCIA service.\n");
19191 +
19192 + events = bcm47xx_pcmcia_events(&state,
19193 + &pcmcia_socket[i].k_state,
19194 + pcmcia_socket[i].cs_state.csc_mask,
19195 + pcmcia_socket[i].cs_state.flags);
19196 +
19197 + if (pcmcia_socket[i].handler != NULL) {
19198 + pcmcia_socket[i].handler(pcmcia_socket[i].handler_info,
19199 + events);
19200 + }
19201 + }
19202 +}
19203 +
19204 +static struct tq_struct bcm47xx_pcmcia_task = {
19205 + routine: bcm47xx_pcmcia_task_handler
19206 +};
19207 +
19208 +
19209 +/*
19210 + * bcm47xx_pcmcia_poll_event()
19211 + *
19212 + * Let's poll for events in addition to IRQs since IRQ only is unreliable...
19213 + */
19214 +static void bcm47xx_pcmcia_poll_event(unsigned long dummy)
19215 +{
19216 + DEBUG(4, "%s(): polling for events\n", __FUNCTION__);
19217 +
19218 + poll_timer.function = bcm47xx_pcmcia_poll_event;
19219 + poll_timer.expires = jiffies + BCM47XX_PCMCIA_POLL_PERIOD;
19220 + add_timer(&poll_timer);
19221 + schedule_task(&bcm47xx_pcmcia_task);
19222 +}
19223 +
19224 +
19225 +/*
19226 + * bcm47xx_pcmcia_interrupt()
19227 + *
19228 + * Service routine for socket driver interrupts (requested by the
19229 + * low-level PCMCIA init() operation via bcm47xx_pcmcia_thread()).
19230 + *
19231 + * The actual interrupt-servicing work is performed by
19232 + * bcm47xx_pcmcia_task(), largely because the Card Services event-
19233 + * handling code performs scheduling operations which cannot be
19234 + * executed from within an interrupt context.
19235 + */
19236 +static void
19237 +bcm47xx_pcmcia_interrupt(int irq, void *dev, struct pt_regs *regs)
19238 +{
19239 + DEBUG(3, "%s(): servicing IRQ %d\n", __FUNCTION__, irq);
19240 + schedule_task(&bcm47xx_pcmcia_task);
19241 +}
19242 +
19243 +
19244 +/*
19245 + * bcm47xx_pcmcia_register_callback()
19246 + *
19247 + * Implements the register_callback() operation for the in-kernel
19248 + * PCMCIA service (formerly SS_RegisterCallback in Card Services). If
19249 + * the function pointer `handler' is not NULL, remember the callback
19250 + * location in the state for `sock', and increment the usage counter
19251 + * for the driver module. (The callback is invoked from the interrupt
19252 + * service routine, bcm47xx_pcmcia_interrupt(), to notify Card Services
19253 + * of interesting events.) Otherwise, clear the callback pointer in the
19254 + * socket state and decrement the module usage count.
19255 + *
19256 + * Returns: 0
19257 + */
19258 +static int
19259 +bcm47xx_pcmcia_register_callback(unsigned int sock,
19260 + void (*handler)(void *, unsigned int), void *info)
19261 +{
19262 + if (handler == NULL) {
19263 + pcmcia_socket[sock].handler = NULL;
19264 + MOD_DEC_USE_COUNT;
19265 + } else {
19266 + MOD_INC_USE_COUNT;
19267 + pcmcia_socket[sock].handler = handler;
19268 + pcmcia_socket[sock].handler_info = info;
19269 + }
19270 + return 0;
19271 +}
19272 +
19273 +
19274 +/*
19275 + * bcm47xx_pcmcia_inquire_socket()
19276 + *
19277 + * Implements the inquire_socket() operation for the in-kernel PCMCIA
19278 + * service (formerly SS_InquireSocket in Card Services). Of note is
19279 + * the setting of the SS_CAP_PAGE_REGS bit in the `features' field of
19280 + * `cap' to "trick" Card Services into tolerating large "I/O memory"
19281 + * addresses. Also set is SS_CAP_STATIC_MAP, which disables the memory
19282 + * resource database check. (Mapped memory is set up within the socket
19283 + * driver itself.)
19284 + *
19285 + * In conjunction with the STATIC_MAP capability is a new field,
19286 + * `io_offset', recommended by David Hinds. Rather than go through
19287 + * the SetIOMap interface (which is not quite suited for communicating
19288 + * window locations up from the socket driver), we just pass up
19289 + * an offset which is applied to client-requested base I/O addresses
19290 + * in alloc_io_space().
19291 + *
19292 + * Returns: 0 on success, -1 if no pin has been configured for `sock'
19293 + */
19294 +static int
19295 +bcm47xx_pcmcia_inquire_socket(unsigned int sock, socket_cap_t *cap)
19296 +{
19297 + struct pcmcia_irq_info irq_info;
19298 +
19299 + if (sock >= socket_count) {
19300 + printk(KERN_ERR "bcm47xx: socket %u not configured\n", sock);
19301 + return -1;
19302 + }
19303 +
19304 + /* SS_CAP_PAGE_REGS: used by setup_cis_mem() in cistpl.c to set the
19305 + * force_low argument to validate_mem() in rsrc_mgr.c -- since in
19306 + * general, the mapped * addresses of the PCMCIA memory regions
19307 + * will not be within 0xffff, setting force_low would be
19308 + * undesirable.
19309 + *
19310 + * SS_CAP_STATIC_MAP: don't bother with the (user-configured) memory
19311 + * resource database; we instead pass up physical address ranges
19312 + * and allow other parts of Card Services to deal with remapping.
19313 + *
19314 + * SS_CAP_PCCARD: we can deal with 16-bit PCMCIA & CF cards, but
19315 + * not 32-bit CardBus devices.
19316 + */
19317 + cap->features = (SS_CAP_PAGE_REGS | SS_CAP_STATIC_MAP | SS_CAP_PCCARD);
19318 +
19319 + irq_info.sock = sock;
19320 + irq_info.irq = -1;
19321 +
19322 + if (pcmcia_low_level->get_irq_info(&irq_info) < 0) {
19323 + printk(KERN_ERR "Error obtaining IRQ info socket %u\n", sock);
19324 + return -1;
19325 + }
19326 +
19327 + cap->irq_mask = 0;
19328 + cap->map_size = PAGE_SIZE;
19329 + cap->pci_irq = irq_info.irq;
19330 + cap->io_offset = pcmcia_socket[sock].virt_io;
19331 +
19332 + return 0;
19333 +}
19334 +
19335 +
19336 +/*
19337 + * bcm47xx_pcmcia_get_status()
19338 + *
19339 + * Implements the get_status() operation for the in-kernel PCMCIA
19340 + * service (formerly SS_GetStatus in Card Services). Essentially just
19341 + * fills in bits in `status' according to internal driver state or
19342 + * the value of the voltage detect chipselect register.
19343 + *
19344 + * As a debugging note, during card startup, the PCMCIA core issues
19345 + * three set_socket() commands in a row the first with RESET deasserted,
19346 + * the second with RESET asserted, and the last with RESET deasserted
19347 + * again. Following the third set_socket(), a get_status() command will
19348 + * be issued. The kernel is looking for the SS_READY flag (see
19349 + * setup_socket(), reset_socket(), and unreset_socket() in cs.c).
19350 + *
19351 + * Returns: 0
19352 + */
19353 +static int
19354 +bcm47xx_pcmcia_get_status(unsigned int sock, unsigned int *status)
19355 +{
19356 + struct pcmcia_state state;
19357 +
19358 +
19359 + if ((pcmcia_low_level->socket_state(sock, &state)) < 0) {
19360 + printk(KERN_ERR "Unable to get PCMCIA status from kernel.\n");
19361 + return -1;
19362 + }
19363 +
19364 + pcmcia_socket[sock].k_state = state;
19365 +
19366 + *status = state.detect ? SS_DETECT : 0;
19367 +
19368 + *status |= state.ready ? SS_READY : 0;
19369 +
19370 + /* The power status of individual sockets is not available
19371 + * explicitly from the hardware, so we just remember the state
19372 + * and regurgitate it upon request:
19373 + */
19374 + *status |= pcmcia_socket[sock].cs_state.Vcc ? SS_POWERON : 0;
19375 +
19376 + if (pcmcia_socket[sock].cs_state.flags & SS_IOCARD)
19377 + *status |= state.bvd1 ? SS_STSCHG : 0;
19378 + else {
19379 + if (state.bvd1 == 0)
19380 + *status |= SS_BATDEAD;
19381 + else if (state.bvd2 == 0)
19382 + *status |= SS_BATWARN;
19383 + }
19384 +
19385 + *status |= state.vs_3v ? SS_3VCARD : 0;
19386 +
19387 + *status |= state.vs_Xv ? SS_XVCARD : 0;
19388 +
19389 + DEBUG(2, "\tstatus: %s%s%s%s%s%s%s%s\n",
19390 + (*status&SS_DETECT)?"DETECT ":"",
19391 + (*status&SS_READY)?"READY ":"",
19392 + (*status&SS_BATDEAD)?"BATDEAD ":"",
19393 + (*status&SS_BATWARN)?"BATWARN ":"",
19394 + (*status&SS_POWERON)?"POWERON ":"",
19395 + (*status&SS_STSCHG)?"STSCHG ":"",
19396 + (*status&SS_3VCARD)?"3VCARD ":"",
19397 + (*status&SS_XVCARD)?"XVCARD ":"");
19398 +
19399 + return 0;
19400 +}
19401 +
19402 +
19403 +/*
19404 + * bcm47xx_pcmcia_get_socket()
19405 + *
19406 + * Implements the get_socket() operation for the in-kernel PCMCIA
19407 + * service (formerly SS_GetSocket in Card Services). Not a very
19408 + * exciting routine.
19409 + *
19410 + * Returns: 0
19411 + */
19412 +static int
19413 +bcm47xx_pcmcia_get_socket(unsigned int sock, socket_state_t *state)
19414 +{
19415 + DEBUG(2, "%s() for sock %u\n", __FUNCTION__, sock);
19416 +
19417 + /* This information was given to us in an earlier call to set_socket(),
19418 + * so we're just regurgitating it here:
19419 + */
19420 + *state = pcmcia_socket[sock].cs_state;
19421 + return 0;
19422 +}
19423 +
19424 +
19425 +/*
19426 + * bcm47xx_pcmcia_set_socket()
19427 + *
19428 + * Implements the set_socket() operation for the in-kernel PCMCIA
19429 + * service (formerly SS_SetSocket in Card Services). We more or
19430 + * less punt all of this work and let the kernel handle the details
19431 + * of power configuration, reset, &c. We also record the value of
19432 + * `state' in order to regurgitate it to the PCMCIA core later.
19433 + *
19434 + * Returns: 0
19435 + */
19436 +static int
19437 +bcm47xx_pcmcia_set_socket(unsigned int sock, socket_state_t *state)
19438 +{
19439 + struct pcmcia_configure configure;
19440 +
19441 + DEBUG(2, "\tmask: %s%s%s%s%s%s\n\tflags: %s%s%s%s%s%s\n"
19442 + "\tVcc %d Vpp %d irq %d\n",
19443 + (state->csc_mask == 0) ? "<NONE>" : "",
19444 + (state->csc_mask & SS_DETECT) ? "DETECT " : "",
19445 + (state->csc_mask & SS_READY) ? "READY " : "",
19446 + (state->csc_mask & SS_BATDEAD) ? "BATDEAD " : "",
19447 + (state->csc_mask & SS_BATWARN) ? "BATWARN " : "",
19448 + (state->csc_mask & SS_STSCHG) ? "STSCHG " : "",
19449 + (state->flags == 0) ? "<NONE>" : "",
19450 + (state->flags & SS_PWR_AUTO) ? "PWR_AUTO " : "",
19451 + (state->flags & SS_IOCARD) ? "IOCARD " : "",
19452 + (state->flags & SS_RESET) ? "RESET " : "",
19453 + (state->flags & SS_SPKR_ENA) ? "SPKR_ENA " : "",
19454 + (state->flags & SS_OUTPUT_ENA) ? "OUTPUT_ENA " : "",
19455 + state->Vcc, state->Vpp, state->io_irq);
19456 +
19457 + configure.sock = sock;
19458 + configure.vcc = state->Vcc;
19459 + configure.vpp = state->Vpp;
19460 + configure.output = (state->flags & SS_OUTPUT_ENA) ? 1 : 0;
19461 + configure.speaker = (state->flags & SS_SPKR_ENA) ? 1 : 0;
19462 + configure.reset = (state->flags & SS_RESET) ? 1 : 0;
19463 +
19464 + if (pcmcia_low_level->configure_socket(&configure) < 0) {
19465 + printk(KERN_ERR "Unable to configure socket %u\n", sock);
19466 + return -1;
19467 + }
19468 +
19469 + pcmcia_socket[sock].cs_state = *state;
19470 + return 0;
19471 +}
19472 +
19473 +
19474 +/*
19475 + * bcm47xx_pcmcia_get_io_map()
19476 + *
19477 + * Implements the get_io_map() operation for the in-kernel PCMCIA
19478 + * service (formerly SS_GetIOMap in Card Services). Just returns an
19479 + * I/O map descriptor which was assigned earlier by a set_io_map().
19480 + *
19481 + * Returns: 0 on success, -1 if the map index was out of range
19482 + */
19483 +static int
19484 +bcm47xx_pcmcia_get_io_map(unsigned int sock, struct pccard_io_map *map)
19485 +{
19486 + DEBUG(2, "bcm47xx_pcmcia_get_io_map: sock %d\n", sock);
19487 +
19488 + if (map->map >= MAX_IO_WIN) {
19489 + printk(KERN_ERR "%s(): map (%d) out of range\n",
19490 + __FUNCTION__, map->map);
19491 + return -1;
19492 + }
19493 +
19494 + *map = pcmcia_socket[sock].io_map[map->map];
19495 + return 0;
19496 +}
19497 +
19498 +
19499 +/*
19500 + * bcm47xx_pcmcia_set_io_map()
19501 + *
19502 + * Implements the set_io_map() operation for the in-kernel PCMCIA
19503 + * service (formerly SS_SetIOMap in Card Services). We configure
19504 + * the map speed as requested, but override the address ranges
19505 + * supplied by Card Services.
19506 + *
19507 + * Returns: 0 on success, -1 on error
19508 + */
19509 +int
19510 +bcm47xx_pcmcia_set_io_map(unsigned int sock, struct pccard_io_map *map)
19511 +{
19512 + unsigned int speed;
19513 + unsigned long start;
19514 +
19515 + DEBUG(2, "\tmap %u speed %u\n\tstart 0x%08lx stop 0x%08lx\n"
19516 + "\tflags: %s%s%s%s%s%s%s%s\n",
19517 + map->map, map->speed, map->start, map->stop,
19518 + (map->flags == 0) ? "<NONE>" : "",
19519 + (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
19520 + (map->flags & MAP_16BIT) ? "16BIT " : "",
19521 + (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
19522 + (map->flags & MAP_0WS) ? "0WS " : "",
19523 + (map->flags & MAP_WRPROT) ? "WRPROT " : "",
19524 + (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "",
19525 + (map->flags & MAP_PREFETCH) ? "PREFETCH " : "");
19526 +
19527 + if (map->map >= MAX_IO_WIN) {
19528 + printk(KERN_ERR "%s(): map (%d) out of range\n",
19529 + __FUNCTION__, map->map);
19530 + return -1;
19531 + }
19532 +
19533 + if (map->flags & MAP_ACTIVE) {
19534 + speed = (map->speed > 0) ? map->speed : BCM47XX_PCMCIA_IO_SPEED;
19535 + pcmcia_socket[sock].speed_io = speed;
19536 + }
19537 +
19538 + start = map->start;
19539 +
19540 + if (map->stop == 1) {
19541 + map->stop = PAGE_SIZE - 1;
19542 + }
19543 +
19544 + map->start = pcmcia_socket[sock].virt_io;
19545 + map->stop = map->start + (map->stop - start);
19546 + pcmcia_socket[sock].io_map[map->map] = *map;
19547 + DEBUG(2, "set_io_map %d start %x stop %x\n",
19548 + map->map, map->start, map->stop);
19549 + return 0;
19550 +}
19551 +
19552 +
19553 +/*
19554 + * bcm47xx_pcmcia_get_mem_map()
19555 + *
19556 + * Implements the get_mem_map() operation for the in-kernel PCMCIA
19557 + * service (formerly SS_GetMemMap in Card Services). Just returns a
19558 + * memory map descriptor which was assigned earlier by a
19559 + * set_mem_map() request.
19560 + *
19561 + * Returns: 0 on success, -1 if the map index was out of range
19562 + */
19563 +static int
19564 +bcm47xx_pcmcia_get_mem_map(unsigned int sock, struct pccard_mem_map *map)
19565 +{
19566 + DEBUG(2, "%s() for sock %u\n", __FUNCTION__, sock);
19567 +
19568 + if (map->map >= MAX_WIN) {
19569 + printk(KERN_ERR "%s(): map (%d) out of range\n",
19570 + __FUNCTION__, map->map);
19571 + return -1;
19572 + }
19573 +
19574 + *map = pcmcia_socket[sock].mem_map[map->map];
19575 + return 0;
19576 +}
19577 +
19578 +
19579 +/*
19580 + * bcm47xx_pcmcia_set_mem_map()
19581 + *
19582 + * Implements the set_mem_map() operation for the in-kernel PCMCIA
19583 + * service (formerly SS_SetMemMap in Card Services). We configure
19584 + * the map speed as requested, but override the address ranges
19585 + * supplied by Card Services.
19586 + *
19587 + * Returns: 0 on success, -1 on error
19588 + */
19589 +static int
19590 +bcm47xx_pcmcia_set_mem_map(unsigned int sock, struct pccard_mem_map *map)
19591 +{
19592 + unsigned int speed;
19593 + unsigned long start;
19594 + u_long flags;
19595 +
19596 + if (map->map >= MAX_WIN) {
19597 + printk(KERN_ERR "%s(): map (%d) out of range\n",
19598 + __FUNCTION__, map->map);
19599 + return -1;
19600 + }
19601 +
19602 + DEBUG(2, "\tmap %u speed %u\n\tsys_start %#lx\n"
19603 + "\tsys_stop %#lx\n\tcard_start %#x\n"
19604 + "\tflags: %s%s%s%s%s%s%s%s\n",
19605 + map->map, map->speed, map->sys_start, map->sys_stop,
19606 + map->card_start, (map->flags == 0) ? "<NONE>" : "",
19607 + (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
19608 + (map->flags & MAP_16BIT) ? "16BIT " : "",
19609 + (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
19610 + (map->flags & MAP_0WS) ? "0WS " : "",
19611 + (map->flags & MAP_WRPROT) ? "WRPROT " : "",
19612 + (map->flags & MAP_ATTRIB) ? "ATTRIB " : "",
19613 + (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "");
19614 +
19615 + if (map->flags & MAP_ACTIVE) {
19616 + /* When clients issue RequestMap, the access speed is not always
19617 + * properly configured:
19618 + */
19619 + speed = (map->speed > 0) ? map->speed : BCM47XX_PCMCIA_MEM_SPEED;
19620 +
19621 + /* TBD */
19622 + if (map->flags & MAP_ATTRIB) {
19623 + pcmcia_socket[sock].speed_attr = speed;
19624 + } else {
19625 + pcmcia_socket[sock].speed_mem = speed;
19626 + }
19627 + }
19628 +
19629 + save_flags(flags);
19630 + cli();
19631 + start = map->sys_start;
19632 +
19633 + if (map->sys_stop == 0)
19634 + map->sys_stop = PAGE_SIZE - 1;
19635 +
19636 + if (map->flags & MAP_ATTRIB) {
19637 + map->sys_start = pcmcia_socket[sock].phys_attr +
19638 + map->card_start;
19639 + } else {
19640 + map->sys_start = pcmcia_socket[sock].phys_mem +
19641 + map->card_start;
19642 + }
19643 +
19644 + map->sys_stop = map->sys_start + (map->sys_stop - start);
19645 + pcmcia_socket[sock].mem_map[map->map] = *map;
19646 + restore_flags(flags);
19647 + DEBUG(2, "set_mem_map %d start %x stop %x card_start %x\n",
19648 + map->map, map->sys_start, map->sys_stop,
19649 + map->card_start);
19650 + return 0;
19651 +}
19652 +
19653 +
19654 +#if defined(CONFIG_PROC_FS)
19655 +
19656 +/*
19657 + * bcm47xx_pcmcia_proc_setup()
19658 + *
19659 + * Implements the proc_setup() operation for the in-kernel PCMCIA
19660 + * service (formerly SS_ProcSetup in Card Services).
19661 + *
19662 + * Returns: 0 on success, -1 on error
19663 + */
19664 +static void
19665 +bcm47xx_pcmcia_proc_setup(unsigned int sock, struct proc_dir_entry *base)
19666 +{
19667 + struct proc_dir_entry *entry;
19668 +
19669 + if ((entry = create_proc_entry("status", 0, base)) == NULL) {
19670 + printk(KERN_ERR "Unable to install \"status\" procfs entry\n");
19671 + return;
19672 + }
19673 +
19674 + entry->read_proc = bcm47xx_pcmcia_proc_status;
19675 + entry->data = (void *)sock;
19676 +}
19677 +
19678 +
19679 +/*
19680 + * bcm47xx_pcmcia_proc_status()
19681 + *
19682 + * Implements the /proc/bus/pccard/??/status file.
19683 + *
19684 + * Returns: the number of characters added to the buffer
19685 + */
19686 +static int
19687 +bcm47xx_pcmcia_proc_status(char *buf, char **start, off_t pos,
19688 + int count, int *eof, void *data)
19689 +{
19690 + char *p = buf;
19691 + unsigned int sock = (unsigned int)data;
19692 +
19693 + p += sprintf(p, "k_flags : %s%s%s%s%s%s%s\n",
19694 + pcmcia_socket[sock].k_state.detect ? "detect " : "",
19695 + pcmcia_socket[sock].k_state.ready ? "ready " : "",
19696 + pcmcia_socket[sock].k_state.bvd1 ? "bvd1 " : "",
19697 + pcmcia_socket[sock].k_state.bvd2 ? "bvd2 " : "",
19698 + pcmcia_socket[sock].k_state.wrprot ? "wrprot " : "",
19699 + pcmcia_socket[sock].k_state.vs_3v ? "vs_3v " : "",
19700 + pcmcia_socket[sock].k_state.vs_Xv ? "vs_Xv " : "");
19701 +
19702 + p += sprintf(p, "status : %s%s%s%s%s%s%s%s%s\n",
19703 + pcmcia_socket[sock].k_state.detect ? "SS_DETECT " : "",
19704 + pcmcia_socket[sock].k_state.ready ? "SS_READY " : "",
19705 + pcmcia_socket[sock].cs_state.Vcc ? "SS_POWERON " : "",
19706 + pcmcia_socket[sock].cs_state.flags & SS_IOCARD ? "SS_IOCARD " : "",
19707 + (pcmcia_socket[sock].cs_state.flags & SS_IOCARD &&
19708 + pcmcia_socket[sock].k_state.bvd1) ? "SS_STSCHG " : "",
19709 + ((pcmcia_socket[sock].cs_state.flags & SS_IOCARD) == 0 &&
19710 + (pcmcia_socket[sock].k_state.bvd1 == 0)) ? "SS_BATDEAD " : "",
19711 + ((pcmcia_socket[sock].cs_state.flags & SS_IOCARD) == 0 &&
19712 + (pcmcia_socket[sock].k_state.bvd2 == 0)) ? "SS_BATWARN " : "",
19713 + pcmcia_socket[sock].k_state.vs_3v ? "SS_3VCARD " : "",
19714 + pcmcia_socket[sock].k_state.vs_Xv ? "SS_XVCARD " : "");
19715 +
19716 + p += sprintf(p, "mask : %s%s%s%s%s\n",
19717 + pcmcia_socket[sock].cs_state.csc_mask & SS_DETECT ? "SS_DETECT " : "",
19718 + pcmcia_socket[sock].cs_state.csc_mask & SS_READY ? "SS_READY " : "",
19719 + pcmcia_socket[sock].cs_state.csc_mask & SS_BATDEAD ? "SS_BATDEAD " : "",
19720 + pcmcia_socket[sock].cs_state.csc_mask & SS_BATWARN ? "SS_BATWARN " : "",
19721 + pcmcia_socket[sock].cs_state.csc_mask & SS_STSCHG ? "SS_STSCHG " : "");
19722 +
19723 + p += sprintf(p, "cs_flags : %s%s%s%s%s\n",
19724 + pcmcia_socket[sock].cs_state.flags & SS_PWR_AUTO ?
19725 + "SS_PWR_AUTO " : "",
19726 + pcmcia_socket[sock].cs_state.flags & SS_IOCARD ?
19727 + "SS_IOCARD " : "",
19728 + pcmcia_socket[sock].cs_state.flags & SS_RESET ?
19729 + "SS_RESET " : "",
19730 + pcmcia_socket[sock].cs_state.flags & SS_SPKR_ENA ?
19731 + "SS_SPKR_ENA " : "",
19732 + pcmcia_socket[sock].cs_state.flags & SS_OUTPUT_ENA ?
19733 + "SS_OUTPUT_ENA " : "");
19734 +
19735 + p += sprintf(p, "Vcc : %d\n", pcmcia_socket[sock].cs_state.Vcc);
19736 + p += sprintf(p, "Vpp : %d\n", pcmcia_socket[sock].cs_state.Vpp);
19737 + p += sprintf(p, "irq : %d\n", pcmcia_socket[sock].cs_state.io_irq);
19738 + p += sprintf(p, "I/O : %u\n", pcmcia_socket[sock].speed_io);
19739 + p += sprintf(p, "attribute: %u\n", pcmcia_socket[sock].speed_attr);
19740 + p += sprintf(p, "common : %u\n", pcmcia_socket[sock].speed_mem);
19741 + return p-buf;
19742 +}
19743 +
19744 +
19745 +#endif /* defined(CONFIG_PROC_FS) */
19746 diff -Nur linux-2.4.30/drivers/pcmcia/bcm4710_pcmcia.c linux-2.4.30-brcm/drivers/pcmcia/bcm4710_pcmcia.c
19747 --- linux-2.4.30/drivers/pcmcia/bcm4710_pcmcia.c 1970-01-01 01:00:00.000000000 +0100
19748 +++ linux-2.4.30-brcm/drivers/pcmcia/bcm4710_pcmcia.c 2005-05-22 22:55:52.000000000 +0200
19749 @@ -0,0 +1,266 @@
19750 +/*
19751 + * BCM4710 specific pcmcia routines.
19752 + *
19753 + * Copyright 2004, Broadcom Corporation
19754 + * All Rights Reserved.
19755 + *
19756 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
19757 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
19758 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
19759 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
19760 + *
19761 + * $Id: bcm4710_pcmcia.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
19762 + */
19763 +#include <linux/module.h>
19764 +#include <linux/init.h>
19765 +#include <linux/config.h>
19766 +#include <linux/delay.h>
19767 +#include <linux/ioport.h>
19768 +#include <linux/kernel.h>
19769 +#include <linux/tqueue.h>
19770 +#include <linux/timer.h>
19771 +#include <linux/mm.h>
19772 +#include <linux/proc_fs.h>
19773 +#include <linux/version.h>
19774 +#include <linux/types.h>
19775 +#include <linux/pci.h>
19776 +
19777 +#include <pcmcia/version.h>
19778 +#include <pcmcia/cs_types.h>
19779 +#include <pcmcia/cs.h>
19780 +#include <pcmcia/ss.h>
19781 +#include <pcmcia/bulkmem.h>
19782 +#include <pcmcia/cistpl.h>
19783 +#include <pcmcia/bus_ops.h>
19784 +#include "cs_internal.h"
19785 +
19786 +#include <asm/io.h>
19787 +#include <asm/irq.h>
19788 +#include <asm/system.h>
19789 +
19790 +
19791 +#include <typedefs.h>
19792 +#include <bcmdevs.h>
19793 +#include <bcm4710.h>
19794 +#include <sbconfig.h>
19795 +#include <sbextif.h>
19796 +
19797 +#include "bcm4710pcmcia.h"
19798 +
19799 +/* Use a static var for irq dev_id */
19800 +static int bcm47xx_pcmcia_dev_id;
19801 +
19802 +/* Do we think we have a card or not? */
19803 +static int bcm47xx_pcmcia_present = 0;
19804 +
19805 +
19806 +static void bcm4710_pcmcia_reset(void)
19807 +{
19808 + extifregs_t *eir;
19809 + unsigned long s;
19810 + uint32 out0, out1, outen;
19811 +
19812 +
19813 + eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
19814 +
19815 + save_and_cli(s);
19816 +
19817 + /* Use gpio7 to reset the pcmcia slot */
19818 + outen = readl(&eir->gpio[0].outen);
19819 + outen |= BCM47XX_PCMCIA_RESET;
19820 + out0 = readl(&eir->gpio[0].out);
19821 + out0 &= ~(BCM47XX_PCMCIA_RESET);
19822 + out1 = out0 | BCM47XX_PCMCIA_RESET;
19823 +
19824 + writel(out0, &eir->gpio[0].out);
19825 + writel(outen, &eir->gpio[0].outen);
19826 + mdelay(1);
19827 + writel(out1, &eir->gpio[0].out);
19828 + mdelay(1);
19829 + writel(out0, &eir->gpio[0].out);
19830 +
19831 + restore_flags(s);
19832 +}
19833 +
19834 +
19835 +static int bcm4710_pcmcia_init(struct pcmcia_init *init)
19836 +{
19837 + struct pci_dev *pdev;
19838 + extifregs_t *eir;
19839 + uint32 outen, intp, intm, tmp;
19840 + uint16 *attrsp;
19841 + int rc = 0, i;
19842 + extern unsigned long bcm4710_cpu_cycle;
19843 +
19844 +
19845 + if (!(pdev = pci_find_device(VENDOR_BROADCOM, SB_EXTIF, NULL))) {
19846 + printk(KERN_ERR "bcm4710_pcmcia: extif not found\n");
19847 + return -ENODEV;
19848 + }
19849 + eir = (extifregs_t *) ioremap_nocache(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
19850 +
19851 + /* Initialize the pcmcia i/f: 16bit no swap */
19852 + writel(CF_EM_PCMCIA | CF_DS | CF_EN, &eir->pcmcia_config);
19853 +
19854 +#ifdef notYet
19855 +
19856 + /* Set the timing for memory accesses */
19857 + tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
19858 + tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
19859 + tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
19860 + tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
19861 + writel(tmp, &eir->pcmcia_memwait); /* 0x01020a0c for a 100Mhz clock */
19862 +
19863 + /* Set the timing for I/O accesses */
19864 + tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
19865 + tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
19866 + tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
19867 + tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
19868 + writel(tmp, &eir->pcmcia_iowait); /* 0x01020a0c for a 100Mhz clock */
19869 +
19870 + /* Set the timing for attribute accesses */
19871 + tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
19872 + tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
19873 + tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
19874 + tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
19875 + writel(tmp, &eir->pcmcia_attrwait); /* 0x01020a0c for a 100Mhz clock */
19876 +
19877 +#endif
19878 + /* Make sure gpio0 and gpio5 are inputs */
19879 + outen = readl(&eir->gpio[0].outen);
19880 + outen &= ~(BCM47XX_PCMCIA_WP | BCM47XX_PCMCIA_STSCHG | BCM47XX_PCMCIA_RESET);
19881 + writel(outen, &eir->gpio[0].outen);
19882 +
19883 + /* Issue a reset to the pcmcia socket */
19884 + bcm4710_pcmcia_reset();
19885 +
19886 +#ifdef DO_BCM47XX_PCMCIA_INTERRUPTS
19887 + /* Setup gpio5 to be the STSCHG interrupt */
19888 + intp = readl(&eir->gpiointpolarity);
19889 + writel(intp | BCM47XX_PCMCIA_STSCHG, &eir->gpiointpolarity); /* Active low */
19890 + intm = readl(&eir->gpiointmask);
19891 + writel(intm | BCM47XX_PCMCIA_STSCHG, &eir->gpiointmask); /* Enable it */
19892 +#endif
19893 +
19894 + DEBUG(2, "bcm4710_pcmcia after reset:\n");
19895 + DEBUG(2, "\textstatus\t= 0x%08x:\n", readl(&eir->extstatus));
19896 + DEBUG(2, "\tpcmcia_config\t= 0x%08x:\n", readl(&eir->pcmcia_config));
19897 + DEBUG(2, "\tpcmcia_memwait\t= 0x%08x:\n", readl(&eir->pcmcia_memwait));
19898 + DEBUG(2, "\tpcmcia_attrwait\t= 0x%08x:\n", readl(&eir->pcmcia_attrwait));
19899 + DEBUG(2, "\tpcmcia_iowait\t= 0x%08x:\n", readl(&eir->pcmcia_iowait));
19900 + DEBUG(2, "\tgpioin\t\t= 0x%08x:\n", readl(&eir->gpioin));
19901 + DEBUG(2, "\tgpio_outen0\t= 0x%08x:\n", readl(&eir->gpio[0].outen));
19902 + DEBUG(2, "\tgpio_out0\t= 0x%08x:\n", readl(&eir->gpio[0].out));
19903 + DEBUG(2, "\tgpiointpolarity\t= 0x%08x:\n", readl(&eir->gpiointpolarity));
19904 + DEBUG(2, "\tgpiointmask\t= 0x%08x:\n", readl(&eir->gpiointmask));
19905 +
19906 +#ifdef DO_BCM47XX_PCMCIA_INTERRUPTS
19907 + /* Request pcmcia interrupt */
19908 + rc = request_irq(BCM47XX_PCMCIA_IRQ, init->handler, SA_INTERRUPT,
19909 + "PCMCIA Interrupt", &bcm47xx_pcmcia_dev_id);
19910 +#endif
19911 +
19912 + attrsp = (uint16 *)ioremap_nocache(EXTIF_PCMCIA_CFGBASE(BCM4710_EXTIF), 0x1000);
19913 + tmp = readw(&attrsp[0]);
19914 + DEBUG(2, "\tattr[0] = 0x%04x\n", tmp);
19915 + if ((tmp == 0x7fff) || (tmp == 0x7f00)) {
19916 + bcm47xx_pcmcia_present = 0;
19917 + } else {
19918 + bcm47xx_pcmcia_present = 1;
19919 + }
19920 +
19921 + /* There's only one socket */
19922 + return 1;
19923 +}
19924 +
19925 +static int bcm4710_pcmcia_shutdown(void)
19926 +{
19927 + extifregs_t *eir;
19928 + uint32 intm;
19929 +
19930 + eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
19931 +
19932 + /* Disable the pcmcia i/f */
19933 + writel(0, &eir->pcmcia_config);
19934 +
19935 + /* Reset gpio's */
19936 + intm = readl(&eir->gpiointmask);
19937 + writel(intm & ~BCM47XX_PCMCIA_STSCHG, &eir->gpiointmask); /* Disable it */
19938 +
19939 + free_irq(BCM47XX_PCMCIA_IRQ, &bcm47xx_pcmcia_dev_id);
19940 +
19941 + return 0;
19942 +}
19943 +
19944 +static int
19945 +bcm4710_pcmcia_socket_state(unsigned sock, struct pcmcia_state *state)
19946 +{
19947 + extifregs_t *eir;
19948 +
19949 + eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
19950 +
19951 +
19952 + if (sock != 0) {
19953 + printk(KERN_ERR "bcm4710 socket_state bad sock %d\n", sock);
19954 + return -1;
19955 + }
19956 +
19957 + if (bcm47xx_pcmcia_present) {
19958 + state->detect = 1;
19959 + state->ready = 1;
19960 + state->bvd1 = 1;
19961 + state->bvd2 = 1;
19962 + state->wrprot = (readl(&eir->gpioin) & BCM47XX_PCMCIA_WP) == BCM47XX_PCMCIA_WP;
19963 + state->vs_3v = 0;
19964 + state->vs_Xv = 0;
19965 + } else {
19966 + state->detect = 0;
19967 + state->ready = 0;
19968 + }
19969 +
19970 + return 1;
19971 +}
19972 +
19973 +
19974 +static int bcm4710_pcmcia_get_irq_info(struct pcmcia_irq_info *info)
19975 +{
19976 + if (info->sock >= BCM47XX_PCMCIA_MAX_SOCK) return -1;
19977 +
19978 + info->irq = BCM47XX_PCMCIA_IRQ;
19979 +
19980 + return 0;
19981 +}
19982 +
19983 +
19984 +static int
19985 +bcm4710_pcmcia_configure_socket(const struct pcmcia_configure *configure)
19986 +{
19987 + if (configure->sock >= BCM47XX_PCMCIA_MAX_SOCK) return -1;
19988 +
19989 +
19990 + DEBUG(2, "Vcc %dV Vpp %dV output %d speaker %d reset %d\n", configure->vcc,
19991 + configure->vpp, configure->output, configure->speaker, configure->reset);
19992 +
19993 + if ((configure->vcc != 50) || (configure->vpp != 50)) {
19994 + printk("%s: bad Vcc/Vpp (%d:%d)\n", __FUNCTION__, configure->vcc,
19995 + configure->vpp);
19996 + }
19997 +
19998 + if (configure->reset) {
19999 + /* Issue a reset to the pcmcia socket */
20000 + DEBUG(1, "%s: Reseting socket\n", __FUNCTION__);
20001 + bcm4710_pcmcia_reset();
20002 + }
20003 +
20004 +
20005 + return 0;
20006 +}
20007 +
20008 +struct pcmcia_low_level bcm4710_pcmcia_ops = {
20009 + bcm4710_pcmcia_init,
20010 + bcm4710_pcmcia_shutdown,
20011 + bcm4710_pcmcia_socket_state,
20012 + bcm4710_pcmcia_get_irq_info,
20013 + bcm4710_pcmcia_configure_socket
20014 +};
20015 +
20016 diff -Nur linux-2.4.30/drivers/pcmcia/bcm4710pcmcia.h linux-2.4.30-brcm/drivers/pcmcia/bcm4710pcmcia.h
20017 --- linux-2.4.30/drivers/pcmcia/bcm4710pcmcia.h 1970-01-01 01:00:00.000000000 +0100
20018 +++ linux-2.4.30-brcm/drivers/pcmcia/bcm4710pcmcia.h 2005-05-22 22:55:52.000000000 +0200
20019 @@ -0,0 +1,118 @@
20020 +/*
20021 + *
20022 + * bcm47xx pcmcia driver
20023 + *
20024 + * Copyright 2004, Broadcom Corporation
20025 + * All Rights Reserved.
20026 + *
20027 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
20028 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
20029 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
20030 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
20031 + *
20032 + * Based on sa1100.h and include/asm-arm/arch-sa1100/pcmica.h
20033 + * from www.handhelds.org,
20034 + * and au1000_generic.c from oss.sgi.com.
20035 + *
20036 + * $Id: bcm4710pcmcia.h,v 1.1 2005/03/16 13:50:00 wbx Exp $
20037 + */
20038 +
20039 +#if !defined(_BCM4710PCMCIA_H)
20040 +#define _BCM4710PCMCIA_H
20041 +
20042 +#include <pcmcia/cs_types.h>
20043 +#include <pcmcia/ss.h>
20044 +#include <pcmcia/bulkmem.h>
20045 +#include <pcmcia/cistpl.h>
20046 +#include "cs_internal.h"
20047 +
20048 +
20049 +/* The 47xx can only support one socket */
20050 +#define BCM47XX_PCMCIA_MAX_SOCK 1
20051 +
20052 +/* In the bcm947xx gpio's are used for some pcmcia functions */
20053 +#define BCM47XX_PCMCIA_WP 0x01 /* Bit 0 is WP input */
20054 +#define BCM47XX_PCMCIA_STSCHG 0x20 /* Bit 5 is STSCHG input/interrupt */
20055 +#define BCM47XX_PCMCIA_RESET 0x80 /* Bit 7 is RESET */
20056 +
20057 +#define BCM47XX_PCMCIA_IRQ 2
20058 +
20059 +/* The socket driver actually works nicely in interrupt-driven form,
20060 + * so the (relatively infrequent) polling is "just to be sure."
20061 + */
20062 +#define BCM47XX_PCMCIA_POLL_PERIOD (2 * HZ)
20063 +
20064 +#define BCM47XX_PCMCIA_IO_SPEED (255)
20065 +#define BCM47XX_PCMCIA_MEM_SPEED (300)
20066 +
20067 +
20068 +struct pcmcia_state {
20069 + unsigned detect: 1,
20070 + ready: 1,
20071 + bvd1: 1,
20072 + bvd2: 1,
20073 + wrprot: 1,
20074 + vs_3v: 1,
20075 + vs_Xv: 1;
20076 +};
20077 +
20078 +
20079 +struct pcmcia_configure {
20080 + unsigned sock: 8,
20081 + vcc: 8,
20082 + vpp: 8,
20083 + output: 1,
20084 + speaker: 1,
20085 + reset: 1;
20086 +};
20087 +
20088 +struct pcmcia_irq_info {
20089 + unsigned int sock;
20090 + unsigned int irq;
20091 +};
20092 +
20093 +/* This structure encapsulates per-socket state which we might need to
20094 + * use when responding to a Card Services query of some kind.
20095 + */
20096 +struct bcm47xx_pcmcia_socket {
20097 + socket_state_t cs_state;
20098 + struct pcmcia_state k_state;
20099 + unsigned int irq;
20100 + void (*handler)(void *, unsigned int);
20101 + void *handler_info;
20102 + pccard_io_map io_map[MAX_IO_WIN];
20103 + pccard_mem_map mem_map[MAX_WIN];
20104 + ioaddr_t virt_io, phys_attr, phys_mem;
20105 + unsigned short speed_io, speed_attr, speed_mem;
20106 +};
20107 +
20108 +struct pcmcia_init {
20109 + void (*handler)(int irq, void *dev, struct pt_regs *regs);
20110 +};
20111 +
20112 +struct pcmcia_low_level {
20113 + int (*init)(struct pcmcia_init *);
20114 + int (*shutdown)(void);
20115 + int (*socket_state)(unsigned sock, struct pcmcia_state *);
20116 + int (*get_irq_info)(struct pcmcia_irq_info *);
20117 + int (*configure_socket)(const struct pcmcia_configure *);
20118 +};
20119 +
20120 +extern struct pcmcia_low_level bcm47xx_pcmcia_ops;
20121 +
20122 +/* I/O pins replacing memory pins
20123 + * (PCMCIA System Architecture, 2nd ed., by Don Anderson, p.75)
20124 + *
20125 + * These signals change meaning when going from memory-only to
20126 + * memory-or-I/O interface:
20127 + */
20128 +#define iostschg bvd1
20129 +#define iospkr bvd2
20130 +
20131 +
20132 +/*
20133 + * Declaration for implementation specific low_level operations.
20134 + */
20135 +extern struct pcmcia_low_level bcm4710_pcmcia_ops;
20136 +
20137 +#endif /* !defined(_BCM4710PCMCIA_H) */
20138 diff -Nur linux-2.4.30/drivers/pcmcia/Makefile linux-2.4.30-brcm/drivers/pcmcia/Makefile
20139 --- linux-2.4.30/drivers/pcmcia/Makefile 2004-02-18 14:36:31.000000000 +0100
20140 +++ linux-2.4.30-brcm/drivers/pcmcia/Makefile 2005-05-22 22:55:52.000000000 +0200
20141 @@ -65,6 +65,10 @@
20142 au1000_ss-objs-$(CONFIG_PCMCIA_DB1X00) += au1000_db1x00.o
20143 au1000_ss-objs-$(CONFIG_PCMCIA_XXS1500) += au1000_xxs1500.o
20144
20145 +obj-$(CONFIG_PCMCIA_BCM4710) += bcm4710_ss.o
20146 +bcm4710_ss-objs := bcm4710_generic.o
20147 +bcm4710_ss-objs += bcm4710_pcmcia.o
20148 +
20149 obj-$(CONFIG_PCMCIA_SA1100) += sa1100_cs.o
20150 obj-$(CONFIG_PCMCIA_M8XX) += m8xx_pcmcia.o
20151 obj-$(CONFIG_PCMCIA_SIBYTE) += sibyte_generic.o
20152 @@ -102,5 +106,8 @@
20153 au1x00_ss.o: $(au1000_ss-objs-y)
20154 $(LD) -r -o $@ $(au1000_ss-objs-y)
20155
20156 +bcm4710_ss.o: $(bcm4710_ss-objs)
20157 + $(LD) -r -o $@ $(bcm4710_ss-objs)
20158 +
20159 yenta_socket.o: $(yenta_socket-objs)
20160 $(LD) $(LD_RFLAG) -r -o $@ $(yenta_socket-objs)
20161 diff -Nur linux-2.4.30/include/asm-mips/bootinfo.h linux-2.4.30-brcm/include/asm-mips/bootinfo.h
20162 --- linux-2.4.30/include/asm-mips/bootinfo.h 2004-02-18 14:36:32.000000000 +0100
20163 +++ linux-2.4.30-brcm/include/asm-mips/bootinfo.h 2005-05-22 22:55:53.000000000 +0200
20164 @@ -37,6 +37,7 @@
20165 #define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */
20166 #define MACH_GROUP_LASAT 21
20167 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
20168 +#define MACH_GROUP_BRCM 23 /* Broadcom */
20169
20170 /*
20171 * Valid machtype values for group unknown (low order halfword of mips_machtype)
20172 @@ -194,6 +195,15 @@
20173 #define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */
20174
20175 /*
20176 + * Valid machtypes for group Broadcom
20177 + */
20178 +#define MACH_BCM93725 0
20179 +#define MACH_BCM93725_VJ 1
20180 +#define MACH_BCM93730 2
20181 +#define MACH_BCM947XX 3
20182 +#define MACH_BCM933XX 4
20183 +
20184 +/*
20185 * Valid machtype for group TITAN
20186 */
20187 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
20188 diff -Nur linux-2.4.30/include/asm-mips/cpu.h linux-2.4.30-brcm/include/asm-mips/cpu.h
20189 --- linux-2.4.30/include/asm-mips/cpu.h 2005-01-19 15:10:11.000000000 +0100
20190 +++ linux-2.4.30-brcm/include/asm-mips/cpu.h 2005-05-22 22:55:53.000000000 +0200
20191 @@ -22,6 +22,11 @@
20192 spec.
20193 */
20194
20195 +#define PRID_COPT_MASK 0xff000000
20196 +#define PRID_COMP_MASK 0x00ff0000
20197 +#define PRID_IMP_MASK 0x0000ff00
20198 +#define PRID_REV_MASK 0x000000ff
20199 +
20200 #define PRID_COMP_LEGACY 0x000000
20201 #define PRID_COMP_MIPS 0x010000
20202 #define PRID_COMP_BROADCOM 0x020000
20203 @@ -58,6 +63,7 @@
20204 #define PRID_IMP_RM7000 0x2700
20205 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
20206 #define PRID_IMP_RM9000 0x3400
20207 +#define PRID_IMP_BCM4710 0x4000
20208 #define PRID_IMP_R5432 0x5400
20209 #define PRID_IMP_R5500 0x5500
20210 #define PRID_IMP_4KC 0x8000
20211 @@ -66,10 +72,16 @@
20212 #define PRID_IMP_4KEC 0x8400
20213 #define PRID_IMP_4KSC 0x8600
20214 #define PRID_IMP_25KF 0x8800
20215 +#define PRID_IMP_BCM3302 0x9000
20216 +#define PRID_IMP_BCM3303 0x9100
20217 #define PRID_IMP_24K 0x9300
20218
20219 #define PRID_IMP_UNKNOWN 0xff00
20220
20221 +#define BCM330X(id) \
20222 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
20223 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
20224 +
20225 /*
20226 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
20227 */
20228 @@ -174,7 +186,9 @@
20229 #define CPU_AU1550 57
20230 #define CPU_24K 58
20231 #define CPU_AU1200 59
20232 -#define CPU_LAST 59
20233 +#define CPU_BCM4710 60
20234 +#define CPU_BCM3302 61
20235 +#define CPU_LAST 61
20236
20237 /*
20238 * ISA Level encodings
20239 diff -Nur linux-2.4.30/include/asm-mips/r4kcache.h linux-2.4.30-brcm/include/asm-mips/r4kcache.h
20240 --- linux-2.4.30/include/asm-mips/r4kcache.h 2004-02-18 14:36:32.000000000 +0100
20241 +++ linux-2.4.30-brcm/include/asm-mips/r4kcache.h 2005-05-25 18:01:08.000000000 +0200
20242 @@ -567,4 +567,17 @@
20243 cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
20244 }
20245
20246 +extern inline void fill_icache_line(unsigned long addr)
20247 +{
20248 + __asm__ __volatile__(
20249 + ".set noreorder\n\t"
20250 + ".set mips3\n\t"
20251 + "cache %1, (%0)\n\t"
20252 + ".set mips0\n\t"
20253 + ".set reorder"
20254 + :
20255 + : "r" (addr),
20256 + "i" (Fill));
20257 +}
20258 +
20259 #endif /* __ASM_R4KCACHE_H */
20260 diff -Nur linux-2.4.30/include/asm-mips/serial.h linux-2.4.30-brcm/include/asm-mips/serial.h
20261 --- linux-2.4.30/include/asm-mips/serial.h 2005-01-19 15:10:12.000000000 +0100
20262 +++ linux-2.4.30-brcm/include/asm-mips/serial.h 2005-05-22 22:55:53.000000000 +0200
20263 @@ -223,6 +223,13 @@
20264 #define TXX927_SERIAL_PORT_DEFNS
20265 #endif
20266
20267 +#ifdef CONFIG_BCM947XX
20268 +/* reserve 4 ports to be configured at runtime */
20269 +#define BCM947XX_SERIAL_PORT_DEFNS { 0, }, { 0, }, { 0, }, { 0, },
20270 +#else
20271 +#define BCM947XX_SERIAL_PORT_DEFNS
20272 +#endif
20273 +
20274 #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
20275 #define STD_SERIAL_PORT_DEFNS \
20276 /* UART CLK PORT IRQ FLAGS */ \
20277 @@ -470,6 +477,7 @@
20278 #define SERIAL_PORT_DFNS \
20279 ATLAS_SERIAL_PORT_DEFNS \
20280 AU1000_SERIAL_PORT_DEFNS \
20281 + BCM947XX_SERIAL_PORT_DEFNS \
20282 COBALT_SERIAL_PORT_DEFNS \
20283 DDB5477_SERIAL_PORT_DEFNS \
20284 EV96100_SERIAL_PORT_DEFNS \
20285 diff -Nur linux-2.4.30/init/do_mounts.c linux-2.4.30-brcm/init/do_mounts.c
20286 --- linux-2.4.30/init/do_mounts.c 2003-11-28 19:26:21.000000000 +0100
20287 +++ linux-2.4.30-brcm/init/do_mounts.c 2005-05-22 22:55:53.000000000 +0200
20288 @@ -253,7 +253,13 @@
20289 { "ftlb", 0x2c08 },
20290 { "ftlc", 0x2c10 },
20291 { "ftld", 0x2c18 },
20292 +#if defined(CONFIG_MTD_BLOCK) || defined(CONFIG_MTD_BLOCK_RO)
20293 { "mtdblock", 0x1f00 },
20294 + { "mtdblock0",0x1f00 },
20295 + { "mtdblock1",0x1f01 },
20296 + { "mtdblock2",0x1f02 },
20297 + { "mtdblock3",0x1f03 },
20298 +#endif
20299 { "nb", 0x2b00 },
20300 { NULL, 0 }
20301 };
20302 diff -Nur linux-2.4.30/Makefile linux-2.4.30-brcm/Makefile
20303 --- linux-2.4.30/Makefile 2005-04-04 03:42:20.000000000 +0200
20304 +++ linux-2.4.30-brcm/Makefile 2005-05-22 22:55:53.000000000 +0200
20305 @@ -17,9 +17,9 @@
20306 FINDHPATH = $(HPATH)/asm $(HPATH)/linux $(HPATH)/scsi $(HPATH)/net $(HPATH)/math-emu
20307
20308 HOSTCC = gcc
20309 -HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer
20310 +HOSTCFLAGS = -Wall -Wstrict-prototypes -Os -fomit-frame-pointer
20311
20312 -CROSS_COMPILE =
20313 +CROSS_COMPILE=
20314
20315 #
20316 # Include the make variables (CC, etc...)
20317 @@ -91,8 +91,10 @@
20318
20319 CPPFLAGS := -D__KERNEL__ -I$(HPATH)
20320
20321 -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
20322 +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
20323 -fno-strict-aliasing -fno-common
20324 +
20325 +
20326 ifndef CONFIG_FRAME_POINTER
20327 CFLAGS += -fomit-frame-pointer
20328 endif
20329 @@ -354,7 +356,7 @@
20330 @rm -f .ver1
20331
20332 include/linux/version.h: ./Makefile
20333 - @expr length "$(KERNELRELEASE)" \<= $(uts_len) > /dev/null || \
20334 + @-expr length "$(KERNELRELEASE)" \<= $(uts_len) > /dev/null || \
20335 (echo KERNELRELEASE \"$(KERNELRELEASE)\" exceeds $(uts_len) characters >&2; false)
20336 @echo \#define UTS_RELEASE \"$(KERNELRELEASE)\" > .ver
20337 @echo \#define LINUX_VERSION_CODE `expr $(VERSION) \\* 65536 + $(PATCHLEVEL) \\* 256 + $(SUBLEVEL)` >> .ver
20338 @@ -500,7 +502,7 @@
20339 ifdef CONFIG_MODVERSIONS
20340 $(MAKE) update-modverfile
20341 endif
20342 - scripts/mkdep -- `find $(FINDHPATH) \( -name SCCS -o -name .svn \) -prune -o -follow -name \*.h ! -name modversions.h -print` > .hdepend
20343 + (find $(FINDHPATH) \( -name SCCS -o -name .svn \) -prune -o -follow -name \*.h ! -name modversions.h -print | xargs -r scripts/mkdep -- ) > .hdepend
20344 scripts/mkdep -- init/*.c > .depend
20345
20346 ifdef CONFIG_MODVERSIONS
20347 diff -Nur linux-2.4.30/Rules.make linux-2.4.30-brcm/Rules.make
20348 --- linux-2.4.30/Rules.make 2004-02-18 14:36:30.000000000 +0100
20349 +++ linux-2.4.30-brcm/Rules.make 2005-05-26 17:11:14.000000000 +0200
20350 @@ -176,7 +176,14 @@
20351 _modinst__: dummy
20352 ifneq "$(strip $(ALL_MOBJS))" ""
20353 mkdir -p $(MODLIB)/kernel/$(MOD_DESTDIR)
20354 - cp $(sort $(ALL_MOBJS)) $(MODLIB)/kernel/$(MOD_DESTDIR)
20355 + #@cp $(sort $(ALL_MOBJS)) $(MODLIB)/kernel/$(MOD_DESTDIR)
20356 + for f in $(ALL_MOBJS) ; do \
20357 + $(OBJCOPY) -R __ksymtab -R .comment -R .note -x \
20358 + `$(NM) $$f | cut -f3- -d' ' | sed -n \
20359 + -e 's/__module_parm_\(.*\)/-K \1/p' \
20360 + -e 's/__ks..tab_\(.*\)/-K \1/p'` \
20361 + $$f $(MODLIB)/kernel/$(MOD_DESTDIR)$(MOD_TARGET)$$f; \
20362 + done
20363 endif
20364
20365 .PHONY: modules_install
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