target/linux/lantiq/patches-2.6.32/120-falcon-i2c.patch

   1 --- a/drivers/i2c/busses/Makefile
   2 +++ b/drivers/i2c/busses/Makefile
   3 @@ -74,6 +74,7 @@
   4  obj-$(CONFIG_I2C_STUB)         += i2c-stub.o
   5  obj-$(CONFIG_SCx200_ACB)       += scx200_acb.o
   6  obj-$(CONFIG_SCx200_I2C)       += scx200_i2c.o
   7 +obj-$(CONFIG_I2C_FALCON)       += i2c-falcon.o
   8
   9  ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
  10  EXTRA_CFLAGS += -DDEBUG
  11 --- a/drivers/i2c/busses/Kconfig
  12 +++ b/drivers/i2c/busses/Kconfig
  13 @@ -278,6 +278,10 @@
  14
  15  comment "I2C system bus drivers (mostly embedded / system-on-chip)"
  16
  17 +config I2C_FALCON
  18 +       tristate "Falcon I2C interface"
  19 +#      depends on SOC_FALCON
  20 +
  21  config I2C_AT91
  22         tristate "Atmel AT91 I2C Two-Wire interface (TWI)"
  23         depends on ARCH_AT91 && EXPERIMENTAL && BROKEN
  24 --- /dev/null
  25 +++ b/drivers/i2c/busses/i2c-falcon.c
  26 @@ -0,0 +1,803 @@
  27 +/*
  28 + *   This program is free software; you can redistribute it and/or modify
  29 + *   it under the terms of the GNU General Public License as published by
  30 + *   the Free Software Foundation; either version 2 of the License, or
  31 + *   (at your option) any later version.
  32 + *
  33 + *   This program is distributed in the hope that it will be useful,
  34 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  35 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  36 + *   GNU General Public License for more details.
  37 + *
  38 + *   You should have received a copy of the GNU General Public License
  39 + *   along with this program; if not, write to the Free Software
  40 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  41 + */
  42 +
  43 +/* #define DEBUG */
  44 +
  45 +#include <linux/module.h>
  46 +#include <linux/ioport.h>
  47 +#include <linux/init.h>
  48 +#include <linux/platform_device.h>
  49 +#include <linux/i2c.h>
  50 +#include <linux/interrupt.h>
  51 +#include <linux/spinlock.h>
  52 +#include <linux/io.h>
  53 +#include <linux/clk.h>
  54 +#include <linux/err.h>
  55 +#include <linux/slab.h>
  56 +
  57 +/* CURRENT ISSUES:
  58 + * - no high speed support
  59 + * - rx issue with "address mode" & "tx end" interrupts
  60 + * - ten bit mode is not tested
  61 + */
  62 +
  63 +/* mapping for access macros */
  64 +#define reg_r32(reg)           __raw_readl(reg)
  65 +#define reg_w32(val, reg)      __raw_writel(val, reg)
  66 +#define reg_w32_mask(clear, set, reg)  \
  67 +                               reg_w32((reg_r32(reg) & ~(clear)) | (set), reg)
  68 +#define reg_r32_table(reg, idx) reg_r32(&((uint32_t *)&reg)[idx])
  69 +#define reg_w32_table(val, reg, idx) reg_w32(val, &((uint32_t *)&reg)[idx])
  70 +#define i2c    (priv->membase)
  71 +#include <falcon/i2c_reg.h>
  72 +
  73 +/* enable hacks to overcome current issue */
  74 +#define FALCON_FIX_ME
  75 +
  76 +#define FALCON_I2C_ADDR                        0x00
  77 +#define FALCON_I2C_READY_TIMEOUT       1000
  78 +#define FALCON_I2C_WAIT_TIMEOUT                10
  79 +
  80 +#define DRV_NAME "i2c-falcon"
  81 +
  82 +#if defined(DEBUG)
  83 +#define static /* no static functions for better debugging */
  84 +#endif
  85 +
  86 +#define FALCON_I2C_ARB_LOST    (1 << 0)
  87 +#define FALCON_I2C_NACK                (1 << 1)
  88 +#define FALCON_I2C_RX_UFL      (1 << 2)
  89 +#define FALCON_I2C_RX_OFL      (1 << 3)
  90 +#define FALCON_I2C_TX_UFL      (1 << 4)
  91 +#define FALCON_I2C_TX_OFL      (1 << 5)
  92 +#define FALCON_I2C_BURST_REQ   (1 << 6)
  93 +#define FALCON_I2C_RX          (1 << 7)
  94 +#define FALCON_I2C_TX_END      (1 << 8)
  95 +#define FALCON_I2C_ADDR_MATCH  (1 << 9) /* doesn't trigger */
  96 +
  97 +struct falcon_i2c {
  98 +       spinlock_t lock;
  99 +
 100 +       enum {
 101 +               FALCON_I2C_MODE_100     = 1,
 102 +               FALCON_I2C_MODE_400     = 2,
 103 +               FALCON_I2C_MODE_3400    = 3
 104 +       } mode;                         /* current speed mode */
 105 +
 106 +       int ten_bit;                    /* current address mode */
 107 +       unsigned long status;           /* bus events holder */
 108 +       struct clk *clk;                /* clock input for i2c hardware block */
 109 +       struct gpon_reg_i2c __iomem *membase;   /* base of mapped registers */
 110 +       int irq_lb, irq_b, irq_err, irq_p;      /* last burst, burst, error,
 111 +                                                  protocol IRQs */
 112 +       struct completion done;
 113 +       struct i2c_adapter adap;
 114 +       struct device *dev;
 115 +};
 116 +
 117 +#define FALCON_I2C_ERROR_MASK          (FALCON_I2C_NACK \
 118 +                                       | FALCON_I2C_ARB_LOST \
 119 +                                       | FALCON_I2C_RX_OFL \
 120 +                                       | FALCON_I2C_RX_UFL \
 121 +                                       | FALCON_I2C_TX_OFL \
 122 +                                       | FALCON_I2C_TX_UFL)
 123 +
 124 +#define FALCON_I2C_ERROR(priv)         (priv->status & FALCON_I2C_ERROR_MASK)
 125 +#define FALCON_I2C_ERROR_CLEAR(priv)   do { \
 126 +                                               priv->status &= \
 127 +                                               ~FALCON_I2C_ERROR_MASK; \
 128 +                                       } while (0)
 129 +
 130 +static void falcon_addr_configure(struct falcon_i2c *priv, int ten_bit)
 131 +{
 132 +       u32 ten_bit_mask = ten_bit ? I2C_ADDR_CFG_TBAM_10bit : 0;
 133 +
 134 +       /* configure address */
 135 +       i2c_w32(I2C_ADDR_CFG_SOPE_EN /* generate stop when no more data in the
 136 +                                       fifo */
 137 +               | I2C_ADDR_CFG_SONA_EN /* generate stop when NA received */
 138 +               | I2C_ADDR_CFG_MnS_EN /* we are master device */
 139 +               | ten_bit_mask
 140 +               | FALCON_I2C_ADDR, /* our address */
 141 +               addr_cfg);
 142 +}
 143 +
 144 +static irqreturn_t falcon_i2c_isr(int irq, void *dev_id)
 145 +{
 146 +       u32 i_raw, i_pro, i_err;
 147 +       struct falcon_i2c *priv = dev_id;
 148 +       unsigned long flags;
 149 +       unsigned int old_status;
 150 +
 151 +       spin_lock_irqsave(&priv->lock, flags);
 152 +
 153 +       old_status = (unsigned int)priv->status;
 154 +
 155 +       i_raw = i2c_r32(mis);
 156 +
 157 +       /* protocol interrupt */
 158 +       if (i_raw & I2C_RIS_I2C_P_INT_INTOCC) {
 159 +               i_pro = i2c_r32(p_irqss);
 160 +
 161 +               /* tx -> rx switch */
 162 +               if (i_pro & I2C_P_IRQSS_RX)
 163 +                       priv->status |= FALCON_I2C_RX;
 164 +
 165 +               /* tx end */
 166 +               if (i_pro & I2C_P_IRQSS_TX_END)
 167 +                       priv->status |= FALCON_I2C_TX_END;
 168 +
 169 +               /* not acknowledge */
 170 +               if (i_pro & I2C_P_IRQSS_NACK)
 171 +                       priv->status |= FALCON_I2C_NACK;
 172 +
 173 +               /* arbitration lost */
 174 +               if (i_pro & I2C_P_IRQSS_AL)
 175 +                       priv->status |= FALCON_I2C_ARB_LOST;
 176 +
 177 +               /* address match */
 178 +               if (i_pro & I2C_P_IRQSS_AM)
 179 +                       priv->status |= FALCON_I2C_ADDR_MATCH;
 180 +
 181 +               i2c_w32(i_pro, p_irqsc);
 182 +       }
 183 +
 184 +       /* error interrupt */
 185 +       if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) {
 186 +               i_err = i2c_r32(err_irqss);
 187 +
 188 +               /* tx fifo overflow */
 189 +               if (i_err & I2C_ERR_IRQSS_TXF_OFL)
 190 +                       priv->status |= FALCON_I2C_TX_OFL;
 191 +
 192 +               /* tx fifo underflow */
 193 +               if (i_err & I2C_ERR_IRQSS_TXF_UFL)
 194 +                       priv->status |= FALCON_I2C_TX_UFL;
 195 +
 196 +               /* rx fifo overflow */
 197 +               if (i_err & I2C_ERR_IRQSS_RXF_OFL)
 198 +                       priv->status |= FALCON_I2C_RX_OFL;
 199 +
 200 +               /* rx fifo underflow */
 201 +               if (i_err & I2C_ERR_IRQSS_RXF_UFL)
 202 +                       priv->status |= FALCON_I2C_RX_UFL;
 203 +
 204 +               i2c_w32(i_err, err_irqsc);
 205 +       }
 206 +
 207 +       /* burst request */
 208 +       if (i_raw & I2C_RIS_BREQ_INT_INTOCC) {
 209 +               i2c_w32_mask(I2C_IMSC_BREQ_INT_EN, 0, imsc);
 210 +               i2c_w32_mask(0, I2C_ICR_BREQ_INT_CLR, icr);
 211 +
 212 +               priv->status |= FALCON_I2C_BURST_REQ;
 213 +       }
 214 +
 215 +       /* last burst request */
 216 +       if (i_raw & I2C_RIS_LBREQ_INT_INTOCC) {
 217 +               i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN, 0, imsc);
 218 +               i2c_w32_mask(0, I2C_ICR_LBREQ_INT_CLR, icr);
 219 +
 220 +               priv->status |= FALCON_I2C_BURST_REQ;
 221 +       }
 222 +
 223 +       if (old_status != (unsigned int)priv->status)
 224 +               complete(&priv->done);
 225 +
 226 +       spin_unlock_irqrestore(&priv->lock, flags);
 227 +
 228 +       return IRQ_HANDLED;
 229 +}
 230 +
 231 +static int falcon_i2c_ready(struct falcon_i2c *priv)
 232 +{
 233 +       int timeout;
 234 +       u32 bus_stat;
 235 +       unsigned long flags;
 236 +       int ret;
 237 +
 238 +       for (timeout = 0; timeout < FALCON_I2C_READY_TIMEOUT; timeout++) {
 239 +               bus_stat = i2c_r32(bus_stat);
 240 +
 241 +               if (bus_stat & I2C_BUS_STAT_BS_SC) {
 242 +                       cpu_relax();
 243 +               } else {
 244 +                       spin_lock_irqsave(&priv->lock, flags);
 245 +
 246 +                       if (FALCON_I2C_ERROR(priv)) {
 247 +                               ret = priv->status;
 248 +
 249 +                               dev_dbg(priv->dev, "bus ready wait error 0x%08lx\n", priv->status);
 250 +
 251 +                               FALCON_I2C_ERROR_CLEAR(priv);
 252 +                       } else {
 253 +                               ret = 0;
 254 +                       }
 255 +
 256 +                       spin_unlock_irqrestore(&priv->lock, flags);
 257 +
 258 +                       return ret;
 259 +               }
 260 +       }
 261 +
 262 +       dev_dbg(priv->dev, "bus ready wait timeout\n");
 263 +
 264 +       return -ETIME;
 265 +}
 266 +
 267 +static int falcon_i2c_wait(struct falcon_i2c *priv, unsigned long status)
 268 +{
 269 +       int ret = 0;
 270 +       unsigned long flags;
 271 +       unsigned int timeout;
 272 +
 273 +       spin_lock_irqsave(&priv->lock, flags);
 274 +
 275 +       priv->status &= FALCON_I2C_BURST_REQ;
 276 +
 277 +       /* check if the event already occurred */
 278 +       if ((priv->status & status) == status) {
 279 +               priv->status &= ~status;
 280 +               spin_unlock_irqrestore(&priv->lock, flags);
 281 +
 282 +               return 0;
 283 +       }
 284 +
 285 +       spin_unlock_irqrestore(&priv->lock, flags);
 286 +
 287 +       /* unmask burst interrupts */
 288 +       i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc);
 289 +
 290 +       for (timeout = 0; timeout < FALCON_I2C_WAIT_TIMEOUT; timeout++) {
 291 +               /* wait for the data request */
 292 +               wait_for_completion_timeout(&priv->done, HZ / 10);
 293 +
 294 +               /* handle errors */
 295 +               spin_lock_irqsave(&priv->lock, flags);
 296 +
 297 +               if (FALCON_I2C_ERROR(priv)) {
 298 +                       dev_dbg(priv->dev, "wait error 0x%08lx (waiting for 0x%08lx)\n",
 299 +                           priv->status,
 300 +                           status);
 301 +
 302 +                       if (priv->status & FALCON_I2C_NACK)
 303 +                               ret = -ENXIO;
 304 +                       else
 305 +                               ret = -EREMOTEIO;
 306 +
 307 +                       FALCON_I2C_ERROR_CLEAR(priv);
 308 +               } else {
 309 +                       if ((priv->status & status) == status) {
 310 +                               priv->status &= ~status;
 311 +                               spin_unlock_irqrestore(&priv->lock, flags);
 312 +
 313 +                               return 0;
 314 +                       }
 315 +               }
 316 +
 317 +               spin_unlock_irqrestore(&priv->lock, flags);
 318 +
 319 +               if (ret)
 320 +                       return ret;
 321 +       }
 322 +
 323 +       dev_dbg(priv->dev, "wait timeout error 0x%08lx (waiting for 0x%08lx)\n",
 324 +           priv->status,
 325 +           status);
 326 +
 327 +       return -ETIME;
 328 +}
 329 +
 330 +static int falcon_i2c_tx(struct falcon_i2c *priv, int ten_bit, u16 addr,
 331 +                        u8 *buf, int len)
 332 +{
 333 +       int i;
 334 +       int ret;
 335 +
 336 +       dev_dbg(priv->dev, "%s\n", __func__);
 337 +
 338 +       /* tell fifo the number of bytes we are going to send */
 339 +       i2c_w32(len + (ten_bit ? 2 : 1), tps_ctrl);
 340 +
 341 +       /* wait for the data request */
 342 +       ret = falcon_i2c_wait(priv, FALCON_I2C_BURST_REQ);
 343 +       if (ret)
 344 +               return ret;
 345 +
 346 +       /* send slave address */
 347 +       if (ten_bit) {
 348 +               i2c_w32(0x78 | ((addr >> 7) & 0x7), txd);
 349 +               i2c_w32(0x78 | ((addr & 0x7f) << 1) | 0, txd);
 350 +       } else {
 351 +               i2c_w32((addr << 1) | 0, txd);
 352 +       }
 353 +
 354 +       /* fill fifo */
 355 +       for (i = 0; i < len; i++) {
 356 +               ret = falcon_i2c_wait(priv, FALCON_I2C_BURST_REQ);
 357 +               if (ret)
 358 +                       return ret;
 359 +
 360 +               i2c_w32(buf[i], txd);
 361 +       }
 362 +
 363 +       return falcon_i2c_wait(priv, FALCON_I2C_TX_END);
 364 +}
 365 +
 366 +static int falcon_i2c_rx(struct falcon_i2c *priv, int ten_bit, u16 addr,
 367 +                        u8 *buf, int len)
 368 +{
 369 +       int i;
 370 +       int ret;
 371 +
 372 +       dev_dbg(priv->dev, "%s\n", __func__);
 373 +
 374 +       /* we need to transmit address only */
 375 +       i2c_w32(ten_bit ? 2 : 1, tps_ctrl);
 376 +
 377 +       /* set maximum received packet size */
 378 +       i2c_w32(len, mrps_ctrl);
 379 +
 380 +       /* wait for the data request */
 381 +       ret = falcon_i2c_wait(priv, FALCON_I2C_BURST_REQ);
 382 +       if (ret)
 383 +               return ret;
 384 +
 385 +       /* write down the address */
 386 +       if (ten_bit) {
 387 +               i2c_w32(0x78 | ((addr >> 7) & 0x7), txd);
 388 +               i2c_w32(0x78 | ((addr & 0x7f) << 1) | 1, txd);
 389 +       } else {
 390 +               i2c_w32((addr << 1) | 1, txd);
 391 +       }
 392 +
 393 +       /* wait for the read request */
 394 +       ret = falcon_i2c_wait(priv, FALCON_I2C_TX_END
 395 +#ifndef FALCON_FIX_ME
 396 +                             | FALCON_I2C_ADDR_MATCH
 397 +#endif
 398 +                             | FALCON_I2C_RX);
 399 +
 400 +       if (ret)
 401 +               return ret;
 402 +
 403 +       /* read bytes */
 404 +       for (i = 0; i < len; i++) {
 405 +#ifdef FALCON_FIX_ME
 406 +               while (i2c_r32(rps_stat) == 0)
 407 +                       cpu_relax();
 408 +#else
 409 +               ret = falcon_i2c_wait(priv, FALCON_I2C_BURST_REQ);
 410 +
 411 +               if (ret)
 412 +                       return ret;
 413 +#endif
 414 +
 415 +               buf[i] = i2c_r32(rxd);
 416 +       }
 417 +
 418 +#ifndef FALCON_FIX_ME
 419 +       /* wait for transmission end */
 420 +       return falcon_i2c_wait(priv, FALCON_I2C_TX_END);
 421 +#else
 422 +       return 0;
 423 +#endif
 424 +}
 425 +
 426 +static int falcon_i2c_xfer_msg(struct falcon_i2c *priv, struct i2c_msg *msg)
 427 +{
 428 +       int ret;
 429 +       int ten_bit;
 430 +       unsigned long flags;
 431 +
 432 +       dev_dbg(priv->dev, "%s %u byte(s) %s 0x%02x\n",
 433 +               (msg->flags & I2C_M_RD) ? "read" : "write", msg->len,
 434 +               (msg->flags & I2C_M_RD) ? "from" : "to", msg->addr);
 435 +
 436 +       if (msg->flags & I2C_M_TEN)
 437 +               ten_bit = 1;
 438 +       else
 439 +               ten_bit = 0;
 440 +
 441 +       /* reconfigure bus if need to send message in different address mode */
 442 +       spin_lock_irqsave(&priv->lock, flags);
 443 +       if (ten_bit != priv->ten_bit) {
 444 +
 445 +               /* disable bus */
 446 +               i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
 447 +
 448 +               /* reconfigure address */
 449 +               falcon_addr_configure(priv, ten_bit);
 450 +
 451 +               /* enable bus */
 452 +               i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
 453 +
 454 +               priv->ten_bit = ten_bit;
 455 +       }
 456 +       spin_unlock_irqrestore(&priv->lock, flags);
 457 +
 458 +       /* read/write actual message */
 459 +       if (msg->flags & I2C_M_RD)
 460 +               ret = falcon_i2c_rx(priv, ten_bit, msg->addr, msg->buf,
 461 +                                   msg->len);
 462 +       else
 463 +               ret = falcon_i2c_tx(priv, ten_bit, msg->addr, msg->buf,
 464 +                                   msg->len);
 465 +
 466 +       if (ret)
 467 +               return ret;
 468 +
 469 +       return 0;
 470 +}
 471 +
 472 +static int falcon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
 473 +                          int num)
 474 +{
 475 +       int i;
 476 +       int ret;
 477 +       unsigned long flags;
 478 +       struct falcon_i2c *priv = i2c_get_adapdata(adap);
 479 +
 480 +       dev_dbg(priv->dev, "xfer %u messages\n", num);
 481 +
 482 +       /* transfer each message */
 483 +       for (i = 0; i < num; i++) {
 484 +#ifdef FALCON_FIX_ME
 485 +               /* disable bus */
 486 +               i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
 487 +               /* enable bus */
 488 +               i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
 489 +#endif
 490 +
 491 +               /* clear bus status */
 492 +               spin_lock_irqsave(&priv->lock, flags);
 493 +               priv->status = 0;
 494 +               spin_unlock_irqrestore(&priv->lock, flags);
 495 +
 496 +               /* wait for the bus to become ready */
 497 +               ret = falcon_i2c_ready(priv);
 498 +               if (ret)
 499 +                       return ret;
 500 +
 501 +               /* transfer message */
 502 +               ret = falcon_i2c_xfer_msg(priv, &msg[i]);
 503 +
 504 +               if (ret)
 505 +                       return ret;
 506 +
 507 +               /* check for unhandled errors */
 508 +               spin_lock_irqsave(&priv->lock, flags);
 509 +               if (FALCON_I2C_ERROR(priv))
 510 +                       ret = priv->status;
 511 +               spin_unlock_irqrestore(&priv->lock, flags);
 512 +
 513 +               if (ret) {
 514 +                       dev_warn(priv->dev, "message %u unhandled error 0x%x\n",
 515 +                               i, ret);
 516 +
 517 +                       return ret;
 518 +               }
 519 +       }
 520 +
 521 +       return 0;
 522 +}
 523 +
 524 +static u32 falcon_i2c_func(struct i2c_adapter *adap)
 525 +{
 526 +       return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
 527 +}
 528 +
 529 +static struct i2c_algorithm falcon_i2c_algorithm = {
 530 +       .master_xfer    = falcon_i2c_xfer,
 531 +       .functionality  = falcon_i2c_func,
 532 +};
 533 +
 534 +static int falcon_i2c_hw_init(struct i2c_adapter *adap)
 535 +{
 536 +       struct falcon_i2c *priv = i2c_get_adapdata(adap);
 537 +
 538 +       /* disable bus */
 539 +       i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
 540 +
 541 +       /* set normal operation clock divider */
 542 +       i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc);
 543 +
 544 +       /* set frequency */
 545 +       if (priv->mode == FALCON_I2C_MODE_100) {
 546 +               dev_dbg(priv->dev, "set standard mode (100 kHz)\n");
 547 +
 548 +               i2c_w32(0, fdiv_high_cfg);
 549 +
 550 +               i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET)
 551 +                       | (499 << I2C_FDIV_CFG_DEC_OFFSET),
 552 +                       fdiv_cfg);
 553 +       } else if (priv->mode == FALCON_I2C_MODE_400) {
 554 +               dev_dbg(priv->dev, "set fast mode (400 kHz)\n");
 555 +
 556 +               i2c_w32(0, fdiv_high_cfg);
 557 +
 558 +               i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET)
 559 +                       | (124 << I2C_FDIV_CFG_DEC_OFFSET),
 560 +                       fdiv_cfg);
 561 +       } else if (priv->mode == FALCON_I2C_MODE_3400) {
 562 +               dev_dbg(priv->dev, "set high mode (3.4 MHz)\n");
 563 +
 564 +               i2c_w32(0, fdiv_cfg);
 565 +
 566 +               /* TODO recalculate value for 100MHz input */
 567 +               i2c_w32((41 << I2C_FDIV_CFG_INC_OFFSET)
 568 +                       | (152 << I2C_FDIV_CFG_DEC_OFFSET),
 569 +                       fdiv_high_cfg);
 570 +       } else {
 571 +               dev_warn(priv->dev, "unknown mode\n");
 572 +
 573 +               return -ENODEV;
 574 +       }
 575 +
 576 +       /* configure fifo */
 577 +       i2c_w32(I2C_FIFO_CFG_TXFC /* tx fifo as flow controller */
 578 +               | I2C_FIFO_CFG_RXFC /* rx fifo as flow controller */
 579 +               | I2C_FIFO_CFG_TXFA_TXFA2 /* tx fifo 4-byte aligned */
 580 +               | I2C_FIFO_CFG_RXFA_RXFA2 /* rx fifo 4-byte aligned */
 581 +               | I2C_FIFO_CFG_TXBS_TXBS0 /* tx fifo burst size is 1 word */
 582 +               | I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */
 583 +               fifo_cfg);
 584 +
 585 +       /* configure address */
 586 +       falcon_addr_configure(priv, priv->ten_bit);
 587 +
 588 +       /* enable bus */
 589 +       i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
 590 +
 591 +       /* mask burst interrupts */
 592 +       i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc);
 593 +
 594 +       /* enable interrupts */
 595 +       i2c_w32(I2C_IMSC_LBREQ_INT_EN
 596 +               | I2C_IMSC_BREQ_INT_EN
 597 +               | I2C_IMSC_I2C_P_INT_EN
 598 +               | I2C_IMSC_I2C_ERR_INT_EN,
 599 +               imsc);
 600 +
 601 +       return 0;
 602 +}
 603 +
 604 +static int __devinit falcon_i2c_probe(struct platform_device *pdev)
 605 +{
 606 +       int ret = 0;
 607 +       struct falcon_i2c *priv;
 608 +       struct i2c_adapter *adap;
 609 +       struct resource *mmres, *ioarea,
 610 +                       *irqres_lb, *irqres_b, *irqres_err, *irqres_p;
 611 +       struct clk *clk;
 612 +
 613 +       dev_dbg(&pdev->dev, "probing\n");
 614 +
 615 +       mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 616 +       irqres_lb = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
 617 +                                                "i2c_lb");
 618 +       irqres_b = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_b");
 619 +       irqres_err = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
 620 +                                                 "i2c_err");
 621 +       irqres_p = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_p");
 622 +
 623 +       if (!mmres || !irqres_lb || !irqres_b || !irqres_err || !irqres_p) {
 624 +               dev_err(&pdev->dev, "no resources\n");
 625 +               return -ENODEV;
 626 +       }
 627 +
 628 +       clk = clk_get(&pdev->dev, "fpi");
 629 +       if (IS_ERR(clk)) {
 630 +               dev_err(&pdev->dev, "failed to get fpi clk\n");
 631 +               return -ENOENT;
 632 +       }
 633 +
 634 +       if (clk_get_rate(clk) != 100000000) {
 635 +               dev_err(&pdev->dev, "input clock is not 100MHz\n");
 636 +               return -ENOENT;
 637 +       }
 638 +
 639 +       /* allocate private data */
 640 +       priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 641 +       if (!priv) {
 642 +               dev_err(&pdev->dev, "can't allocate private data\n");
 643 +               return -ENOMEM;
 644 +       }
 645 +
 646 +       adap = &priv->adap;
 647 +       i2c_set_adapdata(adap, priv);
 648 +       adap->owner = THIS_MODULE;
 649 +       adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 650 +       strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name));
 651 +       adap->algo = &falcon_i2c_algorithm;
 652 +
 653 +       priv->ten_bit = 0;
 654 +       priv->mode = FALCON_I2C_MODE_100;
 655 +       priv->clk = clk;
 656 +       priv->dev = &pdev->dev;
 657 +
 658 +       spin_lock_init(&priv->lock);
 659 +
 660 +       ioarea = request_mem_region(mmres->start, resource_size(mmres),
 661 +                                        pdev->name);
 662 +
 663 +       if (ioarea == NULL) {
 664 +               dev_err(&pdev->dev, "I2C region already claimed\n");
 665 +               ret = -ENXIO;
 666 +               goto err_free_priv;
 667 +       }
 668 +
 669 +       /* map memory */
 670 +       priv->membase = ioremap_nocache(mmres->start & ~KSEG1,
 671 +               resource_size(mmres));
 672 +       if (priv->membase == NULL) {
 673 +               ret = -ENOMEM;
 674 +               goto err_release_region;
 675 +       }
 676 +
 677 +       priv->irq_lb = irqres_lb->start;
 678 +       ret = request_irq(priv->irq_lb, falcon_i2c_isr, IRQF_DISABLED,
 679 +                         irqres_lb->name, priv);
 680 +       if (ret) {
 681 +               dev_err(&pdev->dev, "can't get last burst IRQ %d\n", irqres_lb->start);
 682 +               ret = -ENODEV;
 683 +               goto err_unmap_mem;
 684 +       }
 685 +
 686 +       priv->irq_b = irqres_b->start;
 687 +       ret = request_irq(priv->irq_b, falcon_i2c_isr, IRQF_DISABLED,
 688 +                         irqres_b->name, priv);
 689 +       if (ret) {
 690 +               dev_err(&pdev->dev, "can't get burst IRQ %d\n", irqres_b->start);
 691 +               ret = -ENODEV;
 692 +               goto err_free_lb_irq;
 693 +       }
 694 +
 695 +       priv->irq_err = irqres_err->start;
 696 +       ret = request_irq(priv->irq_err, falcon_i2c_isr, IRQF_DISABLED,
 697 +                         irqres_err->name, priv);
 698 +       if (ret) {
 699 +               dev_err(&pdev->dev, "can't get error IRQ %d\n", irqres_err->start);
 700 +               ret = -ENODEV;
 701 +               goto err_free_b_irq;
 702 +       }
 703 +
 704 +       priv->irq_p = irqres_p->start;
 705 +       ret = request_irq(priv->irq_p, falcon_i2c_isr, IRQF_DISABLED,
 706 +                         irqres_p->name, priv);
 707 +       if (ret) {
 708 +               dev_err(&pdev->dev, "can't get protocol IRQ %d\n", irqres_p->start);
 709 +               ret = -ENODEV;
 710 +               goto err_free_err_irq;
 711 +       }
 712 +
 713 +       dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase);
 714 +       dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres_lb->start,
 715 +           irqres_b->start, irqres_err->start, irqres_p->start);
 716 +
 717 +       /* add our adapter to the i2c stack */
 718 +       ret = i2c_add_numbered_adapter(adap);
 719 +       if (ret) {
 720 +               dev_err(&pdev->dev, "can't register I2C adapter\n");
 721 +               goto err_free_p_irq;
 722 +       }
 723 +
 724 +       platform_set_drvdata(pdev, priv);
 725 +       i2c_set_adapdata(adap, priv);
 726 +
 727 +       /* print module version information */
 728 +       dev_dbg(&pdev->dev, "module id=%u revision=%u\n",
 729 +               (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET,
 730 +               (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET);
 731 +
 732 +       init_completion(&priv->done);
 733 +
 734 +       /* initialize HW */
 735 +       ret = falcon_i2c_hw_init(adap);
 736 +       if (ret) {
 737 +               dev_err(&pdev->dev, "can't configure adapter\n");
 738 +               goto err_remove_adapter;
 739 +       }
 740 +
 741 +       return 0;
 742 +
 743 +err_remove_adapter:
 744 +       i2c_del_adapter(adap);
 745 +       platform_set_drvdata(pdev, NULL);
 746 +
 747 +err_free_p_irq:
 748 +       free_irq(priv->irq_p, priv);
 749 +
 750 +err_free_err_irq:
 751 +       free_irq(priv->irq_err, priv);
 752 +
 753 +err_free_b_irq:
 754 +       free_irq(priv->irq_b, priv);
 755 +
 756 +err_free_lb_irq:
 757 +       free_irq(priv->irq_lb, priv);
 758 +
 759 +err_unmap_mem:
 760 +       iounmap(priv->membase);
 761 +
 762 +err_release_region:
 763 +       release_mem_region(mmres->start, resource_size(mmres));
 764 +
 765 +err_free_priv:
 766 +       kfree(priv);
 767 +
 768 +       return ret;
 769 +}
 770 +
 771 +static int __devexit falcon_i2c_remove(struct platform_device *pdev)
 772 +{
 773 +       struct falcon_i2c *priv = platform_get_drvdata(pdev);
 774 +       struct resource *mmres;
 775 +
 776 +       /* disable bus */
 777 +       i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
 778 +
 779 +       /* remove driver */
 780 +       platform_set_drvdata(pdev, NULL);
 781 +       i2c_del_adapter(&priv->adap);
 782 +
 783 +       free_irq(priv->irq_lb, priv);
 784 +       free_irq(priv->irq_b, priv);
 785 +       free_irq(priv->irq_err, priv);
 786 +       free_irq(priv->irq_p, priv);
 787 +
 788 +       kfree(priv);
 789 +
 790 +       mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 791 +       release_mem_region(mmres->start, resource_size(mmres));
 792 +
 793 +       dev_dbg(&pdev->dev, "removed\n");
 794 +
 795 +       return 0;
 796 +}
 797 +
 798 +static struct platform_driver falcon_i2c_driver = {
 799 +       .probe  = falcon_i2c_probe,
 800 +       .remove = __devexit_p(falcon_i2c_remove),
 801 +       .driver = {
 802 +               .name   = DRV_NAME,
 803 +               .owner  = THIS_MODULE,
 804 +       },
 805 +};
 806 +
 807 +static int __init falcon_i2c_init(void)
 808 +{
 809 +       int ret;
 810 +
 811 +       ret = platform_driver_register(&falcon_i2c_driver);
 812 +
 813 +       if (ret)
 814 +               printk(KERN_DEBUG DRV_NAME ": can't register platform driver");
 815 +
 816 +       return ret;
 817 +}
 818 +
 819 +static void __exit falcon_i2c_exit(void)
 820 +{
 821 +       platform_driver_unregister(&falcon_i2c_driver);
 822 +}
 823 +
 824 +module_init(falcon_i2c_init);
 825 +module_exit(falcon_i2c_exit);
 826 +
 827 +MODULE_DESCRIPTION("Lantiq FALC(tm) ON - I2C bus adapter");
 828 +MODULE_ALIAS("platform:i2c_falcon");
 829 +MODULE_LICENSE("GPL");