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ramips: default profile fix
[openwrt.git] / package / uboot-xburst / patches / 001-xburst.patch
1 this patch include the u-boot2009.11 change files
2
3 From: Xiangfu Liu <xiangfu@sharism.cc>
4
5
6 ---
7
8 Makefile | 10 +
9 common/env_common.c | 2
10 common/lcd.c | 45 ++++
11 common/main.c | 4
12 cpu/mips/Makefile | 4
13 cpu/mips/cache.S | 280 ++++++++++----------------
14 cpu/mips/config.mk | 6 -
15 cpu/mips/cpu.c | 75 +++++++
16 cpu/mips/start.S | 432 ++++++++++++++++++++++++++++++++--------
17 drivers/mtd/nand/nand_base.c | 88 ++++++++
18 examples/standalone/mips.lds | 2
19 include/asm-mips/addrspace.h | 2
20 include/asm-mips/global_data.h | 11 +
21 include/lcd.h | 56 +++++
22 lib_mips/board.c | 18 +-
23 lib_mips/bootm.c | 7 +
24 lib_mips/time.c | 4
25 20 files changed, 800 insertions(+), 333 deletions(-)
26
27
28 diff --git a/Makefile b/Makefile
29 index f06a97c..a318eb4 100644
30 --- a/Makefile
31 +++ b/Makefile
32 @@ -3439,6 +3439,22 @@ qemu_mips_config : unconfig
33 @$(MKCONFIG) -a qemu-mips mips mips qemu-mips
34
35 #########################################################################
36 +## MIPS32 Jz47XX
37 +#########################################################################
38 +qi_lb60_config : unconfig
39 + @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
40 + @echo "Compile NAND boot image for QI LB60"
41 + @$(MKCONFIG) -a qi_lb60 mips mips nanonote
42 + @echo "TEXT_BASE = 0x80100000" > $(obj)board/nanonote/config.tmp
43 + @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
44 +
45 +avt2_config : unconfig
46 + @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
47 + @echo "Compile NAND boot image for AVT2"
48 + @$(MKCONFIG) -a avt2 mips mips nanonote
49 + @echo "TEXT_BASE = 0x80100000" > $(obj)board/nanonote/config.tmp
50 + @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
51 +#########################################################################
52 ## MIPS64 5Kc
53 #########################################################################
54
55 diff --git a/common/env_common.c b/common/env_common.c
56 index 439a4a9..6cfe30b 100644
57 --- a/common/env_common.c
58 +++ b/common/env_common.c
59 @@ -134,7 +134,10 @@ uchar default_environment[] = {
60 "pcidelay=" MK_STR(CONFIG_PCI_BOOTDELAY) "\0"
61 #endif
62 -#ifdef CONFIG_EXTRA_ENV_SETTINGS
63 - CONFIG_EXTRA_ENV_SETTINGS
64 +#ifdef CONFIG_BOOTARGSFROMSD
65 + "bootargsfromsd=" CONFIG_BOOTARGSFROMSD "\0"
66 +#endif
67 +#ifdef CONFIG_BOOTCOMMANDFROMSD
68 + "bootcmdfromsd=" CONFIG_BOOTCOMMANDFROMSD "\0"
69 #endif
70 "\0"
71 };
72 diff --git a/common/lcd.c b/common/lcd.c
73 index 4e31618..ddd5aa8 100644
74 --- a/common/lcd.c
75 +++ b/common/lcd.c
76 @@ -64,7 +64,9 @@
77 #ifdef CONFIG_LCD_LOGO
78 # include <bmp_logo.h> /* Get logo data, width and height */
79 # if (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET)
80 -# error Default Color Map overlaps with Logo Color Map
81 +# ifndef CONFIG_JzRISC /* JzRISC core */
82 +# error Default Color Map overlaps with Logo Color Map
83 +# endif
84 # endif
85 #endif
86
87 @@ -249,6 +251,14 @@ static void lcd_drawchars (ushort x, ushort y, uchar *str, int count)
88 lcd_color_fg : lcd_color_bg;
89 bits <<= 1;
90 }
91 +#elif LCD_BPP == LCD_COLOR32
92 + uint *m = (uint *)d;
93 + for (c=0; c<32; ++c) {
94 + *m++ = (bits & 0x80) ?
95 + lcd_color_fg : lcd_color_bg;
96 + //d+=4;
97 + bits <<= 1;
98 + }
99 #endif
100 }
101 #if LCD_BPP == LCD_MONOCHROME
102 @@ -315,6 +325,9 @@ static void test_pattern (void)
103 }
104 #endif /* LCD_TEST_PATTERN */
105
106 +#ifdef CONFIG_JzRISC /* JzRISC core */
107 +extern int flush_cache_all(void);
108 +#endif
109
110 /************************************************************************/
111 /* ** GENERIC Initialization Routines */
112 @@ -381,6 +394,7 @@ static int lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
113 COLOR_MASK(lcd_getbgcolor()),
114 lcd_line_length*panel_info.vl_row);
115 #endif
116 +
117 /* Paint the logo and retrieve LCD base address */
118 debug ("[LCD] Drawing the logo...\n");
119 lcd_console_address = lcd_logo ();
120 @@ -458,6 +472,8 @@ static void lcd_setfgcolor (int color)
121 {
122 #ifdef CONFIG_ATMEL_LCD
123 lcd_color_fg = color;
124 +#elif LCD_BPP == LCD_COLOR32
125 + lcd_color_fg = color & 0xFFFFFFFF;
126 #else
127 lcd_color_fg = color & 0x0F;
128 #endif
129 @@ -469,6 +485,8 @@ static void lcd_setbgcolor (int color)
130 {
131 #ifdef CONFIG_ATMEL_LCD
132 lcd_color_bg = color;
133 +#elif LCD_BPP == LCD_COLOR32
134 + lcd_color_bg = color & 0xFFFFFFFF;
135 #else
136 lcd_color_bg = color & 0x0F;
137 #endif
138 @@ -507,6 +525,7 @@ void bitmap_plot (int x, int y)
139 uchar *bmap;
140 uchar *fb;
141 ushort *fb16;
142 + uint *fb32;
143 #if defined(CONFIG_PXA250)
144 struct pxafb_info *fbi = &panel_info.pxa;
145 #elif defined(CONFIG_MPC823)
146 @@ -567,13 +586,25 @@ void bitmap_plot (int x, int y)
147 }
148 }
149 else { /* true color mode */
150 - fb16 = (ushort *)(lcd_base + y * lcd_line_length + x);
151 - for (i=0; i<BMP_LOGO_HEIGHT; ++i) {
152 - for (j=0; j<BMP_LOGO_WIDTH; j++) {
153 - fb16[j] = bmp_logo_palette[(bmap[j])];
154 + if(NBITS(panel_info.vl_bpix) == 16){
155 + fb16 = (ushort *)(lcd_base + y * lcd_line_length + x);
156 + for (i=0; i<BMP_LOGO_HEIGHT; ++i) {
157 + for (j=0; j<BMP_LOGO_WIDTH; j++) {
158 + fb16[j] = bmp_logo_palette[(bmap[j])];
159 }
160 - bmap += BMP_LOGO_WIDTH;
161 - fb16 += panel_info.vl_col;
162 + bmap += BMP_LOGO_WIDTH;
163 + fb16 += panel_info.vl_col;
164 + }
165 + }
166 + else{
167 + fb32 = (uint *)(lcd_base + y * lcd_line_length + x);
168 + for (i=0; i<BMP_LOGO_HEIGHT; ++i) {
169 + for (j=0; j<BMP_LOGO_WIDTH; j++) {
170 + fb32[j] = bmp_logo_palette[(bmap[j])];
171 + }
172 + bmap += BMP_LOGO_WIDTH;
173 + fb32 += panel_info.vl_col;
174 + }
175 }
176 }
177
178 diff --git a/common/main.c b/common/main.c
179 index 10d8904..ff11ad7 100644
180 --- a/common/main.c
181 +++ b/common/main.c
182 @@ -372,7 +372,9 @@ void main_loop (void)
183 #if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
184 s = getenv ("bootdelay");
185 bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY;
186 -
187 + DECLARE_GLOBAL_DATA_PTR;
188 + if (gd->boot_option == 5)
189 + bootdelay = gd->boot_option;
190 debug ("### main_loop entered: bootdelay=%d\n\n", bootdelay);
191
192 # ifdef CONFIG_BOOT_RETRY_TIME
193 @@ -393,7 +395,9 @@ void main_loop (void)
194 }
195 else
196 #endif /* CONFIG_BOOTCOUNT_LIMIT */
197 - s = getenv ("bootcmd");
198 + s = gd->boot_option == 1 ?
199 + getenv ("bootcmdfromsd"):
200 + getenv ("bootcmd") ;
201
202 debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
203
204 diff --git a/cpu/mips/Makefile b/cpu/mips/Makefile
205 index 28a1cbb..5207bc5 100644
206 --- a/cpu/mips/Makefile
207 +++ b/cpu/mips/Makefile
208 @@ -33,6 +33,9 @@ SOBJS-$(CONFIG_INCA_IP) += incaip_wdt.o
209 COBJS-$(CONFIG_INCA_IP) += asc_serial.o incaip_clock.o
210 COBJS-$(CONFIG_PURPLE) += asc_serial.o
211 COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
212 +COBJS-$(CONFIG_JZSOC) += jz4740.o jz_serial.o jz_mmc.o jz4740_nand.o
213 +COBJS-$(CONFIG_NANONOTE) += nanonote_gpm940b0.o
214 +
215
216 SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
217 OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
218 diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
219 index ff4f11c..cb3baff 100644
220 --- a/cpu/mips/cache.S
221 +++ b/cpu/mips/cache.S
222 @@ -23,32 +23,19 @@
223 */
224
225 #include <config.h>
226 -#include <asm/asm.h>
227 +#include <version.h>
228 #include <asm/regdef.h>
229 #include <asm/mipsregs.h>
230 #include <asm/addrspace.h>
231 #include <asm/cacheops.h>
232
233 -#define RA t8
234 +#ifndef CONFIG_JzRISC
235
236 -/*
237 - * 16kB is the maximum size of instruction and data caches on MIPS 4K,
238 - * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
239 - *
240 - * Note that the above size is the maximum size of primary cache. U-Boot
241 - * doesn't have L2 cache support for now.
242 - */
243 -#define MIPS_MAX_CACHE_SIZE 0x10000
244 -
245 -#define INDEX_BASE CKSEG0
246 + /* 16KB is the maximum size of instruction and data caches on
247 + * MIPS 4K.
248 + */
249 +#define MIPS_MAX_CACHE_SIZE 0x4000
250
251 - .macro cache_op op addr
252 - .set push
253 - .set noreorder
254 - .set mips3
255 - cache \op, 0(\addr)
256 - .set pop
257 - .endm
258
259 /*
260 * cacheop macro to automate cache operations
261 @@ -119,79 +106,7 @@
262 #define icacheop(kva, n, cacheSize, cacheLineSize, op) \
263 icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
264
265 - .macro f_fill64 dst, offset, val
266 - LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
267 - LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
268 - LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
269 - LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
270 - LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
271 - LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
272 - LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
273 - LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
274 -#if LONGSIZE == 4
275 - LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
276 - LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
277 - LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
278 - LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
279 - LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
280 - LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
281 - LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
282 - LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
283 -#endif
284 - .endm
285 -
286 -/*
287 - * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
288 - */
289 -LEAF(mips_init_icache)
290 - blez a1, 9f
291 - mtc0 zero, CP0_TAGLO
292 - /* clear tag to invalidate */
293 - PTR_LI t0, INDEX_BASE
294 - PTR_ADDU t1, t0, a1
295 -1: cache_op Index_Store_Tag_I t0
296 - PTR_ADDU t0, a2
297 - bne t0, t1, 1b
298 - /* fill once, so data field parity is correct */
299 - PTR_LI t0, INDEX_BASE
300 -2: cache_op Fill t0
301 - PTR_ADDU t0, a2
302 - bne t0, t1, 2b
303 - /* invalidate again - prudent but not strictly neccessary */
304 - PTR_LI t0, INDEX_BASE
305 -1: cache_op Index_Store_Tag_I t0
306 - PTR_ADDU t0, a2
307 - bne t0, t1, 1b
308 -9: jr ra
309 - END(mips_init_icache)
310 -
311 /*
312 - * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
313 - */
314 -LEAF(mips_init_dcache)
315 - blez a1, 9f
316 - mtc0 zero, CP0_TAGLO
317 - /* clear all tags */
318 - PTR_LI t0, INDEX_BASE
319 - PTR_ADDU t1, t0, a1
320 -1: cache_op Index_Store_Tag_D t0
321 - PTR_ADDU t0, a2
322 - bne t0, t1, 1b
323 - /* load from each line (in cached space) */
324 - PTR_LI t0, INDEX_BASE
325 -2: LONG_L zero, 0(t0)
326 - PTR_ADDU t0, a2
327 - bne t0, t1, 2b
328 - /* clear all tags */
329 - PTR_LI t0, INDEX_BASE
330 -1: cache_op Index_Store_Tag_D t0
331 - PTR_ADDU t0, a2
332 - bne t0, t1, 1b
333 -9: jr ra
334 - END(mips_init_dcache)
335 -
336 -/*******************************************************************************
337 -*
338 * mips_cache_reset - low level initialisation of the primary caches
339 *
340 * This routine initialises the primary caches to ensure that they
341 @@ -204,112 +119,129 @@ LEAF(mips_init_dcache)
342 * a source of parity.
343 *
344 * RETURNS: N/A
345 -*
346 */
347 -NESTED(mips_cache_reset, 0, ra)
348 - move RA, ra
349 + .globl mips_cache_reset
350 + .ent mips_cache_reset
351 +mips_cache_reset:
352 +
353 li t2, CONFIG_SYS_ICACHE_SIZE
354 li t3, CONFIG_SYS_DCACHE_SIZE
355 li t4, CONFIG_SYS_CACHELINE_SIZE
356 move t5, t4
357
358 +
359 li v0, MIPS_MAX_CACHE_SIZE
360
361 - /*
362 - * Now clear that much memory starting from zero.
363 + /* Now clear that much memory starting from zero.
364 */
365 - PTR_LI a0, CKSEG1
366 - PTR_ADDU a1, a0, v0
367 -2: PTR_ADDIU a0, 64
368 - f_fill64 a0, -64, zero
369 - bne a0, a1, 2b
370 -
371 - /*
372 - * The caches are probably in an indeterminate state,
373 - * so we force good parity into them by doing an
374 - * invalidate, load/fill, invalidate for each line.
375 +
376 + li a0, KSEG1
377 + addu a1, a0, v0
378 +
379 +2: sw zero, 0(a0)
380 + sw zero, 4(a0)
381 + sw zero, 8(a0)
382 + sw zero, 12(a0)
383 + sw zero, 16(a0)
384 + sw zero, 20(a0)
385 + sw zero, 24(a0)
386 + sw zero, 28(a0)
387 + addu a0, 32
388 + bltu a0, a1, 2b
389 +
390 + /* Set invalid tag.
391 */
392
393 - /*
394 - * Assume bottom of RAM will generate good parity for the cache.
395 + mtc0 zero, CP0_TAGLO
396 +
397 + /*
398 + * The caches are probably in an indeterminate state,
399 + * so we force good parity into them by doing an
400 + * invalidate, load/fill, invalidate for each line.
401 + */
402 +
403 + /* Assume bottom of RAM will generate good parity for the cache.
404 */
405
406 - /*
407 - * Initialize the I-cache first,
408 + li a0, K0BASE
409 + move a2, t2 # icacheSize
410 + move a3, t4 # icacheLineSize
411 + move a1, a2
412 + icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill))
413 +
414 + /* To support Orion/R4600, we initialise the data cache in 3 passes.
415 */
416 - move a1, t2
417 - move a2, t4
418 - PTR_LA t7, mips_init_icache
419 - jalr t7
420
421 - /*
422 - * then initialize D-cache.
423 + /* 1: initialise dcache tags.
424 */
425 - move a1, t3
426 - move a2, t5
427 - PTR_LA t7, mips_init_dcache
428 - jalr t7
429
430 - jr RA
431 - END(mips_cache_reset)
432 + li a0, K0BASE
433 + move a2, t3 # dcacheSize
434 + move a3, t5 # dcacheLineSize
435 + move a1, a2
436 + icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
437
438 -/*******************************************************************************
439 -*
440 -* dcache_status - get cache status
441 -*
442 -* RETURNS: 0 - cache disabled; 1 - cache enabled
443 -*
444 -*/
445 -LEAF(dcache_status)
446 - mfc0 t0, CP0_CONFIG
447 - li t1, CONF_CM_UNCACHED
448 - andi t0, t0, CONF_CM_CMASK
449 - move v0, zero
450 - beq t0, t1, 2f
451 - li v0, 1
452 -2: jr ra
453 - END(dcache_status)
454 -
455 -/*******************************************************************************
456 -*
457 + /* 2: fill dcache.
458 + */
459 +
460 + li a0, K0BASE
461 + move a2, t3 # dcacheSize
462 + move a3, t5 # dcacheLineSize
463 + move a1, a2
464 + icacheopn(a0,a1,a2,a3,1lw,(dummy))
465 +
466 + /* 3: clear dcache tags.
467 + */
468 +
469 + li a0, K0BASE
470 + move a2, t3 # dcacheSize
471 + move a3, t5 # dcacheLineSize
472 + move a1, a2
473 + icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
474 +
475 + j ra
476 + .end mips_cache_reset
477 +
478 +
479 +/*
480 + * dcache_status - get cache status
481 + *
482 + * RETURNS: 0 - cache disabled; 1 - cache enabled
483 + */
484 + .globl dcache_status
485 + .ent dcache_status
486 +dcache_status:
487 +
488 + mfc0 v0, CP0_CONFIG
489 + andi v0, v0, 1
490 + j ra
491 +
492 + .end dcache_status
493 +
494 +/*
495 * dcache_disable - disable cache
496 *
497 * RETURNS: N/A
498 -*
499 */
500 -LEAF(dcache_disable)
501 + .globl dcache_disable
502 + .ent dcache_disable
503 +dcache_disable:
504 +
505 mfc0 t0, CP0_CONFIG
506 li t1, -8
507 and t0, t0, t1
508 ori t0, t0, CONF_CM_UNCACHED
509 - mtc0 t0, CP0_CONFIG
510 - jr ra
511 - END(dcache_disable)
512 + mtc0 t0, CP0_CONFIG
513 + j ra
514
515 -/*******************************************************************************
516 -*
517 -* dcache_enable - enable cache
518 -*
519 -* RETURNS: N/A
520 -*
521 -*/
522 -LEAF(dcache_enable)
523 - mfc0 t0, CP0_CONFIG
524 - ori t0, CONF_CM_CMASK
525 - xori t0, CONF_CM_CMASK
526 - ori t0, CONF_CM_CACHABLE_NONCOHERENT
527 - mtc0 t0, CP0_CONFIG
528 - jr ra
529 - END(dcache_enable)
530 -
531 -#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
532 -/*******************************************************************************
533 -*
534 -* mips_cache_lock - lock RAM area pointed to by a0 in cache.
535 -*
536 -* RETURNS: N/A
537 -*
538 -*/
539 + .end dcache_disable
540 +
541 +
542 +/*
543 + * mips_cache_lock - lock RAM area pointed to by a0 in cache.
544 + *
545 + * RETURNS: N/A
546 + */
547 #if defined(CONFIG_PURPLE)
548 # define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE/2)
549 #else
550 @@ -318,14 +250,14 @@ LEAF(dcache_enable)
551 .globl mips_cache_lock
552 .ent mips_cache_lock
553 mips_cache_lock:
554 - li a1, CKSEG0 - CACHE_LOCK_SIZE
555 + li a1, K0BASE - CACHE_LOCK_SIZE
556 addu a0, a1
557 li a2, CACHE_LOCK_SIZE
558 li a3, CONFIG_SYS_CACHELINE_SIZE
559 move a1, a2
560 icacheop(a0,a1,a2,a3,0x1d)
561
562 - jr ra
563 -
564 + j ra
565 .end mips_cache_lock
566 -#endif /* CONFIG_SYS_INIT_RAM_LOCK_MIPS */
567 +
568 +#endif /* CONFIG_JzRISC */
569 diff --git a/cpu/mips/config.mk b/cpu/mips/config.mk
570 index a173c54..8d27e52 100644
571 --- a/cpu/mips/config.mk
572 +++ b/cpu/mips/config.mk
573 @@ -25,15 +25,15 @@ MIPSFLAGS:=$(shell \
574 if [ "$v" -lt "14" ]; then \
575 echo "-mcpu=4kc"; \
576 else \
577 - echo "-march=4kc -mtune=4kc"; \
578 + echo "-march=4kc -mtune=r4600"; \
579 fi)
580
581 ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
582 ENDIANNESS = -EL
583 else
584 -ENDIANNESS = -EB
585 +#ENDIANNESS = -EB
586 endif
587
588 -MIPSFLAGS += $(ENDIANNESS)
589 +MIPSFLAGS += $(ENDIANNESS) -mabicalls -mips32 -O2
590
591 PLATFORM_CPPFLAGS += $(MIPSFLAGS)
592 diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c
593 index d5a1604..48e1cea 100644
594 --- a/cpu/mips/cpu.c
595 +++ b/cpu/mips/cpu.c
596 @@ -28,6 +28,12 @@
597 #include <asm/cacheops.h>
598 #include <asm/reboot.h>
599
600 +#ifdef CONFIG_JZ4740
601 +#include <asm/jz4740.h>
602 +#endif
603 +
604 +#if !defined (CONFIG_NAND_SPL) && !defined (CONFIG_MSC_SPL)
605 +
606 #define cache_op(op,addr) \
607 __asm__ __volatile__( \
608 " .set push \n" \
609 @@ -40,6 +46,19 @@
610
611 void __attribute__((weak)) _machine_restart(void)
612 {
613 +#ifdef CONFIG_JZ4740
614 + __wdt_select_extalclk();
615 + __wdt_select_clk_div64();
616 + __wdt_set_data(100);
617 + __wdt_set_count(0);
618 + __tcu_start_wdt_clock();
619 + __wdt_start();
620 + while(1);
621 +#endif
622 +#if defined(CONFIG_JzRISC)
623 + void (*f)(void) = (void *) 0xbfc00000;
624 + f();
625 +#endif
626 }
627
628 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
629 @@ -110,3 +129,59 @@ int cpu_eth_init(bd_t *bis)
630 #endif
631 return 0;
632 }
633 +
634 +#endif /* !CONFIG_NAND_SPL !CONFIG_MSC_SPL */
635 +
636 +#ifdef CONFIG_JzRISC
637 +void flush_icache_all(void)
638 +{
639 + u32 addr, t = 0;
640 +
641 + asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
642 + asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
643 +
644 + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE;
645 + addr += CONFIG_SYS_CACHELINE_SIZE) {
646 + asm volatile (
647 + ".set mips3\n\t"
648 + " cache %0, 0(%1)\n\t"
649 + ".set mips2\n\t"
650 + :
651 + : "I" (Index_Store_Tag_I), "r"(addr));
652 + }
653 +
654 + /* invalicate btb */
655 + asm volatile (
656 + ".set mips32\n\t"
657 + "mfc0 %0, $16, 7\n\t"
658 + "nop\n\t"
659 + "ori %0,2\n\t"
660 + "mtc0 %0, $16, 7\n\t"
661 + ".set mips2\n\t"
662 + :
663 + : "r" (t));
664 +}
665 +
666 +void flush_dcache_all(void)
667 +{
668 + u32 addr;
669 +
670 + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE;
671 + addr += CONFIG_SYS_CACHELINE_SIZE) {
672 + asm volatile (
673 + ".set mips3\n\t"
674 + " cache %0, 0(%1)\n\t"
675 + ".set mips2\n\t"
676 + :
677 + : "I" (Index_Writeback_Inv_D), "r"(addr));
678 + }
679 +
680 + asm volatile ("sync");
681 +}
682 +
683 +void flush_cache_all(void)
684 +{
685 + flush_dcache_all();
686 + flush_icache_all();
687 +}
688 +#endif /* CONFIG_JzRISC */
689 diff --git a/cpu/mips/start.S b/cpu/mips/start.S
690 index 57db589..fa6e352 100644
691 --- a/cpu/mips/start.S
692 +++ b/cpu/mips/start.S
693 @@ -23,32 +23,33 @@
694 */
695
696 #include <config.h>
697 +#include <version.h>
698 #include <asm/regdef.h>
699 #include <asm/mipsregs.h>
700 +#include <asm/addrspace.h>
701 +#include <asm/cacheops.h>
702
703 - /*
704 - * For the moment disable interrupts, mark the kernel mode and
705 - * set ST0_KX so that the CPU does not spit fire when using
706 - * 64-bit addresses.
707 - */
708 - .macro setup_c0_status set clr
709 - .set push
710 - mfc0 t0, CP0_STATUS
711 - or t0, ST0_CU0 | \set | 0x1f | \clr
712 - xor t0, 0x1f | \clr
713 - mtc0 t0, CP0_STATUS
714 - .set noreorder
715 - sll zero, 3 # ehb
716 - .set pop
717 - .endm
718 -
719 - .macro setup_c0_status_reset
720 -#ifdef CONFIG_64BIT
721 - setup_c0_status ST0_KX 0
722 -#else
723 - setup_c0_status 0 0
724 +#ifdef CONFIG_JZ4730
725 +#include <asm/jz4730.h>
726 +#endif
727 +
728 +#ifdef CONFIG_JZ4740
729 +#include <asm/jz4740.h>
730 +#endif
731 +
732 +#ifdef CONFIG_JZ4750
733 +#include <asm/jz4750.h>
734 +#endif
735 +
736 +#ifdef CONFIG_JZ4750D
737 +#include <asm/jz4750d.h>
738 +#endif
739 +
740 +#if defined(CONFIG_JZ4750) || defined(CONFIG_JZ4750D)
741 +#define JZ4750_NANDBOOT_CFG0 (0x55555500 | (CFG_NAND_BW8*0xff))
742 +#define JZ4750_NANDBOOT_CFG1 0x55555555
743 +#define JZ4750_NANDBOOT_CFG2 ((CFG_NAND_PAGE_SIZE==2048)&0xff0000) | ((CFG_NAND_PAGE_SIZE!=512)&0xff00) | ((CFG_NAND_ROW_CYCLE==3)&0xff)
744 #endif
745 - .endm
746
747 #define RVECENT(f,n) \
748 b f; nop
749 @@ -61,6 +62,28 @@
750 .globl _start
751 .text
752 _start:
753 +#if defined(CONFIG_JZ4740)
754 +#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_NAND_U_BOOT)
755 + .word JZ4740_NORBOOT_CFG /* fetched during NOR Boot */
756 +#else
757 +#if defined(CONFIG_NAND_SPL)
758 + .word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */
759 +#endif
760 +#endif
761 +#endif /* CONFIG_JZ4740 */
762 +#if defined(CONFIG_JZ4750) || defined(CONFIG_JZ4750D)
763 +#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_NAND_U_BOOT)
764 + .word JZ4750_NORBOOT_CFG /* fetched during NOR Boot */
765 +#else
766 +#if defined(CONFIG_NAND_SPL) && !defined(CONFIG_MSC_SPL)
767 + /* First three words fetched by CPU during NAND Boot */
768 + .word JZ4750_NANDBOOT_CFG0
769 + .word JZ4750_NANDBOOT_CFG1
770 + .word JZ4750_NANDBOOT_CFG2
771 +#endif
772 +#endif
773 +#endif /* CONFIG_JZ4750 || CONFIG_JZ4750D */
774 +#if !defined(CONFIG_JzRISC)
775 RVECENT(reset,0) /* U-boot entry point */
776 RVECENT(reset,1) /* software reboot */
777 #if defined(CONFIG_INCA_IP)
778 @@ -213,7 +236,7 @@ _start:
779 .word 0x00000000
780 .word 0x03e00008
781 .word 0x00000000
782 - .word 0x00000000
783 + .word 0x00000000
784 /* 0xbfc00428 */
785 .word 0xdc870000
786 .word 0xfca70000
787 @@ -224,74 +247,192 @@ _start:
788 .word 0x00000000
789 .word 0x03e00008
790 .word 0x00000000
791 - .word 0x00000000
792 + .word 0x00000000
793 #endif /* CONFIG_PURPLE */
794 .align 4
795 +#endif /* CONFIG_JzRISC */
796 +
797 reset:
798
799 +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
800 +
801 +#ifdef CONFIG_JZ4730
802 +
803 + /* Disable interrupts */
804 + la t0, INTC_IMR
805 + li t1, 0xffffffff
806 + sw t1, 0(t0)
807 +
808 + /*
809 + * Clear SCR.HGP
810 + */
811 + la t0, CPM_SCR
812 + lw t1, 0(t0)
813 + ori t1, 0x8
814 + xori t1, 0x8
815 + sw t1, 0(t0)
816 +
817 + /*
818 + * Set usb port0 as host
819 + */
820 + la t0, HARB_HAPOR
821 + lw t1, 0(t0)
822 + ori t1, HARB_HAPOR_UCHSEL
823 + sw t1, 0(t0)
824 +
825 + /*
826 + * Check reset status
827 + */
828 + la t0, CPM_RSTR
829 + lw t1, 0(t0)
830 + andi t1, 0x4
831 + bnez t1, resume_from_hibernate
832 + nop
833 +#endif /* CONFIG_JZ4730 */
834 +
835 +#ifndef CONFIG_NAND_SPL
836 /* Clear watch registers.
837 */
838 mtc0 zero, CP0_WATCHLO
839 mtc0 zero, CP0_WATCHHI
840 +#endif
841
842 - /* WP(Watch Pending), SW0/1 should be cleared. */
843 - mtc0 zero, CP0_CAUSE
844 + /* STATUS register */
845 +#ifdef CONFIG_JzRISC
846 + /*
847 + * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
848 + */
849 + li t0, 0x0040FC04
850 + mtc0 t0, CP0_STATUS
851 +#else
852 +#ifdef CONFIG_TB0229
853 + li k0, ST0_CU0
854 +#else
855 + mfc0 k0, CP0_STATUS
856 +#endif
857 + li k1, ~ST0_IE
858 + and k0, k1
859 + mtc0 k0, CP0_STATUS
860 +#endif
861
862 - setup_c0_status_reset
863 + /* CAUSE register */
864 +#ifdef CONFIG_JzRISC
865 + /* IV=1, use the specical interrupt vector (0x200) */
866 + li t1, 0x00800000
867 + mtc0 t1, CP0_CAUSE
868 +#else
869 + mtc0 zero, CP0_CAUSE
870 +#endif
871
872 +#ifndef CONFIG_JzRISC
873 /* Init Timer */
874 mtc0 zero, CP0_COUNT
875 mtc0 zero, CP0_COMPARE
876 +#endif
877
878 -#if !defined(CONFIG_SKIP_LOWLEVEL_INIT)
879 +#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
880 +
881 +#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_NAND_U_BOOT)
882 /* CONFIG0 register */
883 li t0, CONF_CM_UNCACHED
884 mtc0 t0, CP0_CONFIG
885 -#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
886 +#endif
887
888 - /* Initialize $gp.
889 + /* Initialize GOT pointer.
890 + */
891 + bal 1f
892 + nop
893 + .word _GLOBAL_OFFSET_TABLE_
894 + 1:
895 + move gp, ra
896 + lw t1, 0(ra)
897 + move gp, t1
898 +
899 +#ifdef CONFIG_INCA_IP
900 + /* Disable INCA-IP Watchdog.
901 */
902 - bal 1f
903 + la t9, disable_incaip_wdt
904 + jalr t9
905 nop
906 - .word _gp
907 -1:
908 - lw gp, 0(ra)
909 +#endif
910
911 -#if !defined(CONFIG_SKIP_LOWLEVEL_INIT)
912 +/* JzRISC will init external memory in board_init_f,
913 + which uses cache as stack and calls into C code. */
914 +#ifndef CONFIG_JzRISC
915 /* Initialize any external memory.
916 */
917 - la t9, lowlevel_init
918 - jalr t9
919 + la t9, lowlevel_init
920 + jalr t9
921 nop
922 +#endif
923
924 +#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_NAND_U_BOOT)
925 /* Initialize caches...
926 */
927 - la t9, mips_cache_reset
928 - jalr t9
929 +#ifdef CONFIG_JzRISC
930 + .set mips32
931 + mtc0 zero, CP0_TAGLO
932 + mtc0 zero, CP0_TAGHI
933 +
934 + li t0, K0BASE
935 + ori t1, t0, CONFIG_SYS_DCACHE_SIZE
936 +1:
937 + cache Index_Store_Tag_D, 0(t0)
938 + bne t0, t1, 1b
939 + addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE
940 +
941 + li t0, K0BASE
942 + ori t1, t0, CONFIG_SYS_ICACHE_SIZE
943 +2:
944 + cache Index_Store_Tag_I, 0(t0)
945 + bne t0, t1, 2b
946 + addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE
947 +
948 + /* Invalidate BTB */
949 + mfc0 t0, CP0_CONFIG, 7
950 + nop
951 + ori t0, 2
952 + mtc0 t0, CP0_CONFIG, 7
953 nop
954
955 + .set mips2
956 +#else
957 + la t9, mips_cache_reset
958 + jalr t9
959 + nop
960 +#endif
961 +
962 /* ... and enable them.
963 */
964 li t0, CONF_CM_CACHABLE_NONCOHERENT
965 mtc0 t0, CP0_CONFIG
966 -#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
967 + nop
968 +
969 +#endif /* !defined(CONFIG_NAND_SPL) && !defined(CONFIG_NAND_U_BOOT) */
970
971 /* Set up temporary stack.
972 */
973 -#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
974 +#ifndef CONFIG_JzRISC
975 li a0, CONFIG_SYS_INIT_SP_OFFSET
976 - la t9, mips_cache_lock
977 - jalr t9
978 + la t9, mips_cache_lock
979 + jalr t9
980 nop
981 #endif
982
983 +#ifdef CONFIG_NAND_SPL
984 + la sp, 0x80004000
985 + la t9, nand_boot
986 + j t9
987 + nop
988 +#else
989 li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
990 la sp, 0(t0)
991
992 la t9, board_init_f
993 - jr t9
994 + j t9
995 nop
996
997 +
998 /*
999 * void relocate_code (addr_sp, gd, addr_moni)
1000 *
1001 @@ -305,37 +446,28 @@ reset:
1002 .globl relocate_code
1003 .ent relocate_code
1004 relocate_code:
1005 - move sp, a0 /* Set new stack pointer */
1006 + move sp, a0 /* Set new stack pointer */
1007
1008 - li t0, CONFIG_SYS_MONITOR_BASE
1009 + li t0, TEXT_BASE
1010 la t3, in_ram
1011 lw t2, -12(t3) /* t2 <-- uboot_end_data */
1012 move t1, a2
1013 - move s2, a2 /* s2 <-- destination address */
1014
1015 /*
1016 - * Fix $gp:
1017 + * Fix GOT pointer:
1018 *
1019 - * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
1020 + * New GOT-PTR = (old GOT-PTR - TEXT_BASE) + Destination Address
1021 */
1022 move t6, gp
1023 - sub gp, CONFIG_SYS_MONITOR_BASE
1024 - add gp, a2 /* gp now adjusted */
1025 - sub s1, gp, t6 /* s1 <-- relocation offset */
1026 + sub gp, TEXT_BASE
1027 + add gp, a2 /* gp now adjusted */
1028 + sub t6, gp, t6 /* t6 <-- relocation offset */
1029
1030 /*
1031 * t0 = source address
1032 * t1 = target address
1033 * t2 = source end address
1034 */
1035 -
1036 - /*
1037 - * Save destination address and size for later usage in flush_cache()
1038 - */
1039 - move s0, a1 /* save gd in s0 */
1040 - move a0, t1 /* a0 <-- destination addr */
1041 - sub a1, t2, t0 /* a1 <-- size */
1042 -
1043 /* On the purple board we copy the code earlier in a special way
1044 * in order to solve flash problems
1045 */
1046 @@ -345,47 +477,61 @@ relocate_code:
1047 sw t3, 0(t1)
1048 addu t0, 4
1049 ble t0, t2, 1b
1050 - addu t1, 4 /* delay slot */
1051 + addu t1, 4 /* delay slot */
1052 #endif
1053
1054 /* If caches were enabled, we would have to flush them here.
1055 */
1056 -
1057 - /* a0 & a1 are already set up for flush_cache(start, size) */
1058 - la t9, flush_cache
1059 - jalr t9
1060 +#ifdef CONFIG_JzRISC
1061 + /* flush d-cache */
1062 + .set mips32
1063 + li t0, KSEG0
1064 + addi t1, t0, CONFIG_SYS_DCACHE_SIZE
1065 +2:
1066 + cache Index_Writeback_Inv_D, 0(t0)
1067 + bne t0, t1, 2b
1068 + addi t0, CONFIG_SYS_CACHELINE_SIZE
1069 +
1070 + sync
1071 +
1072 + /* flush i-cache */
1073 + li t0, KSEG0
1074 + addi t1, t0, CONFIG_SYS_ICACHE_SIZE
1075 +3:
1076 + cache Index_Invalidate_I, 0(t0)
1077 + bne t0, t1, 3b
1078 + addi t0, CONFIG_SYS_CACHELINE_SIZE
1079 +
1080 + /* Invalidate BTB */
1081 + mfc0 t0, CP0_CONFIG, 7
1082 + nop
1083 + ori t0, 2
1084 + mtc0 t0, CP0_CONFIG, 7
1085 nop
1086
1087 + .set mips0
1088 +#endif
1089 +
1090 /* Jump to where we've relocated ourselves.
1091 */
1092 - addi t0, s2, in_ram - _start
1093 - jr t0
1094 + addi t0, a2, in_ram - _start
1095 + j t0
1096 nop
1097
1098 - .word _gp
1099 - .word _GLOBAL_OFFSET_TABLE_
1100 .word uboot_end_data
1101 .word uboot_end
1102 .word num_got_entries
1103
1104 in_ram:
1105 - /*
1106 - * Now we want to update GOT.
1107 - *
1108 - * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
1109 - * generated by GNU ld. Skip these reserved entries from relocation.
1110 + /* Now we want to update GOT.
1111 */
1112 lw t3, -4(t0) /* t3 <-- num_got_entries */
1113 - lw t4, -16(t0) /* t4 <-- _GLOBAL_OFFSET_TABLE_ */
1114 - lw t5, -20(t0) /* t5 <-- _gp */
1115 - sub t4, t5 /* compute offset*/
1116 - add t4, t4, gp /* t4 now holds relocated _GLOBAL_OFFSET_TABLE_ */
1117 - addi t4, t4, 8 /* Skipping first two entries. */
1118 + addi t4, gp, 8 /* Skipping first two entries. */
1119 li t2, 2
1120 1:
1121 lw t1, 0(t4)
1122 beqz t1, 2f
1123 - add t1, s1
1124 + add t1, t6
1125 sw t1, 0(t4)
1126 2:
1127 addi t2, 1
1128 @@ -396,26 +542,134 @@ in_ram:
1129 */
1130 lw t1, -12(t0) /* t1 <-- uboot_end_data */
1131 lw t2, -8(t0) /* t2 <-- uboot_end */
1132 - add t1, s1 /* adjust pointers */
1133 - add t2, s1
1134 + add t1, t6 /* adjust pointers */
1135 + add t2, t6
1136
1137 sub t1, 4
1138 -1:
1139 - addi t1, 4
1140 +1: addi t1, 4
1141 bltl t1, t2, 1b
1142 sw zero, 0(t1) /* delay slot */
1143
1144 - move a0, s0 /* a0 <-- gd */
1145 + move a0, a1
1146 la t9, board_init_r
1147 - jr t9
1148 - move a1, s2 /* delay slot */
1149 + j t9
1150 + move a1, a2 /* delay slot */
1151
1152 .end relocate_code
1153
1154 +#endif /* CONFIG_NAND_SPL */
1155 +
1156 +#if !defined(CONFIG_JzRISC)
1157 /* Exception handlers.
1158 */
1159 romReserved:
1160 - b romReserved
1161 + b romReserved
1162
1163 romExcHandle:
1164 - b romExcHandle
1165 + b romExcHandle
1166 +#endif
1167 +
1168 +#ifdef CONFIG_JZ4730
1169 +
1170 +/* These are the runtime values, modify them according to your platform. */
1171 +#define PLCR1_VAL 0x1b000520
1172 +#define CFCR_VAL 0x0c526220
1173 +
1174 +#define DMCR_VAL0 0x042a3211
1175 +#define DMCR_VAL1 0x05aa3211 /*(DMCR_VAL0|EMC_DMCR_RFSH|EMC_DMCR_MRSET)*/
1176 +
1177 +#define RTCOR_VAL 0x10
1178 +#define RTCSR_VAL 0x83
1179 +
1180 + /*
1181 + * cpu was reset from hibernate mode
1182 + */
1183 +resume_from_hibernate:
1184 + /*
1185 + * Init PLL
1186 + */
1187 + la t0, 0xB0000000 /* CFCR */
1188 + li t1, CFCR_VAL
1189 + sw t1, 0(t0)
1190 +
1191 + la t0, 0xB0000010 /* PLCR1 */
1192 + li t1, PLCR1_VAL
1193 + sw t1, 0(t0)
1194 + nop;nop;nop;nop
1195 +
1196 + /* Init caches */
1197 + .set mips32
1198 + mtc0 zero, CP0_TAGLO
1199 + mtc0 zero, CP0_TAGHI
1200 +
1201 + li t0, K0BASE
1202 + ori t1, t0, CONFIG_SYS_DCACHE_SIZE
1203 +1:
1204 + cache Index_Store_Tag_D, 0(t0)
1205 + cache Index_Store_Tag_I, 0(t0)
1206 + bne t0, t1, 1b
1207 + addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE
1208 +
1209 + /*
1210 + * Init SDRAM
1211 + */
1212 + la t0, 0xB0010070 /* GPALR2 */
1213 + lw t1, 0(t0)
1214 + li t2, 0x3FFFFFFF
1215 + and t1, t2
1216 + li t2, 0x40000000
1217 + or t1, t2
1218 + sw t1, 0(t0)
1219 +
1220 + la t0, 0xB0010074 /* GPAUR2 */
1221 + lw t1, 0(t0)
1222 + li t2, 0xFFFF0000
1223 + and t1, t2
1224 + li t2, 0x00005555
1225 + or t1, t2
1226 + sw t1, 0(t0)
1227 +
1228 + la t0, 0xB3010000 /* EMC base address */
1229 +
1230 + li t1, DMCR_VAL0 /* DMCR */
1231 + sw t1, 0x80(t0)
1232 +
1233 + li t1, RTCOR_VAL
1234 + sh t1, 0x8c(t0) /* RTCOR */
1235 +
1236 + li t1, RTCSR_VAL
1237 + sh t1, 0x84(t0) /* RTCSR */
1238 +
1239 + /* precharge all chip-selects */
1240 + ori t1, t0, 0xa088
1241 + sb $0, 0(t1)
1242 + ori t1, t0, 0xb088
1243 + sb $0, 0(t1)
1244 +
1245 + /* delay about 200us */
1246 + li t1, 0x20000
1247 +1:
1248 + bnez t1, 1b
1249 + sub t1, 1
1250 +
1251 + la t1, DMCR_VAL1 /* DMCR */
1252 + sw t1, 0x80(t0)
1253 +
1254 + /* write sdram mode register for each chip-select */
1255 + ori t1, t0, 0xa088
1256 + sb $0, 0(t1)
1257 + ori t1, t0, 0xb088
1258 + sb $0, 0(t1)
1259 +
1260 + /*
1261 + * jump to resume entry point
1262 + */
1263 + la t0, CPM_SPR
1264 + lw t1, 0(t0)
1265 + li t0, 0x80000000
1266 + or t0, t1
1267 +
1268 + j t0
1269 + nop
1270 +
1271 +#endif /* CONFIG_JZ4730 */
1272 diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
1273 index 426bb95..6e5fbd3 100644
1274 --- a/drivers/mtd/nand/nand_base.c
1275 +++ b/drivers/mtd/nand/nand_base.c
1276 @@ -109,6 +109,22 @@ static struct nand_ecclayout nand_oob_16 = {
1277 . length = 8}}
1278 };
1279
1280 +#if defined(CONFIG_JZ4740)
1281 +static struct nand_ecclayout nand_oob_64 = {
1282 + .eccbytes = 36,
1283 + .eccpos = {
1284 + 6, 7, 8, 9, 10, 11, 12, 13,
1285 + 14, 15, 16, 17, 18, 19, 20, 21,
1286 + 22, 23, 24, 25, 26, 27, 28, 29,
1287 + 30, 31, 32, 33, 34, 35, 36, 37,
1288 + 38, 39, 40, 41},
1289 + .oobfree ={
1290 + {.offset = 2,
1291 + .length = 4},
1292 + {.offset = 42,
1293 + .length = 22}}
1294 +};
1295 +#else
1296 static struct nand_ecclayout nand_oob_64 = {
1297 .eccbytes = 24,
1298 .eccpos = {
1299 @@ -119,6 +135,7 @@ static struct nand_ecclayout nand_oob_64 = {
1300 {.offset = 2,
1301 .length = 38}}
1302 };
1303 +#endif
1304
1305 static struct nand_ecclayout nand_oob_128 = {
1306 .eccbytes = 48,
1307 @@ -1116,6 +1133,60 @@ static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1308 }
1309
1310 /**
1311 + * nand_read_page_hwecc_rs - [REPLACABLE] hardware rs ecc based page read function
1312 + * @mtd: mtd info structure
1313 + * @chip: nand chip info structure
1314 + * @buf: buffer to store read data
1315 + *
1316 + * Not for syndrome calculating ecc controllers which need a special oob layout
1317 + */
1318 +static int nand_read_page_hwecc_rs(struct mtd_info *mtd, struct nand_chip *chip,
1319 + uint8_t *buf)
1320 +{
1321 + int i, eccsize = chip->ecc.size;
1322 + int eccbytes = chip->ecc.bytes;
1323 + int eccsteps = chip->ecc.steps;
1324 + uint8_t *p = buf;
1325 + uint8_t *ecc_calc = chip->buffers->ecccalc;
1326 + uint8_t *ecc_code = chip->buffers->ecccode;
1327 + uint32_t *eccpos = chip->ecc.layout->eccpos;
1328 + uint32_t page;
1329 + uint8_t flag = 0;
1330 +
1331 + page = (buf[3]<<24) + (buf[2]<<16) + (buf[1]<<8) + buf[0];
1332 +
1333 + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1334 + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1335 +
1336 + for (i = 0; i < chip->ecc.total; i++) {
1337 + ecc_code[i] = chip->oob_poi[CONFIG_SYS_NAND_ECC_POS + i];
1338 + if (ecc_code[i] != 0xff)
1339 + flag = 1;
1340 + }
1341 +
1342 + eccsteps = chip->ecc.steps;
1343 + p = buf;
1344 +
1345 + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, 0x00, -1);
1346 + for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1347 + int stat;
1348 + if (flag) {
1349 + chip->ecc.hwctl(mtd, NAND_ECC_READ);
1350 + chip->read_buf(mtd, p, eccsize);
1351 + stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1352 + if (stat < 0)
1353 + mtd->ecc_stats.failed++;
1354 + else
1355 + mtd->ecc_stats.corrected += stat;
1356 + }
1357 + else {
1358 + chip->ecc.hwctl(mtd, NAND_ECC_READ);
1359 + chip->read_buf(mtd, p, eccsize);
1360 + }
1361 + }
1362 + return 0;
1363 +}
1364 +/**
1365 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1366 * @mtd: mtd info structure
1367 * @chip: nand chip info structure
1368 @@ -1271,9 +1342,17 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1369 bufpoi, page);
1370 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1371 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1372 - else
1373 + else {
1374 +#if defined(CONFIG_JZ4740)
1375 + bufpoi[0] = (uint8_t)page;
1376 + bufpoi[1] = (uint8_t)(page >> 8);
1377 + bufpoi[2] = (uint8_t)(page >> 16);
1378 + bufpoi[3] = (uint8_t)(page >> 24);
1379 +#endif
1380 +
1381 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1382 page);
1383 + }
1384 if (ret < 0)
1385 break;
1386
1387 @@ -2791,8 +2870,13 @@ int nand_scan_tail(struct mtd_info *mtd)
1388
1389 case NAND_ECC_HW:
1390 /* Use standard hwecc read page function ? */
1391 - if (!chip->ecc.read_page)
1392 + if (!chip->ecc.read_page) {
1393 +#if defined(CONFIG_JZ4740)
1394 + chip->ecc.read_page = nand_read_page_hwecc_rs;
1395 +#else
1396 chip->ecc.read_page = nand_read_page_hwecc;
1397 +#endif
1398 + }
1399 if (!chip->ecc.write_page)
1400 chip->ecc.write_page = nand_write_page_hwecc;
1401 if (!chip->ecc.read_oob)
1402 diff --git a/examples/standalone/mips.lds b/examples/standalone/mips.lds
1403 index 717b201..d4a45f8 100644
1404 --- a/examples/standalone/mips.lds
1405 +++ b/examples/standalone/mips.lds
1406 @@ -23,8 +23,8 @@
1407
1408 /*
1409 OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
1410 -*/
1411 OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
1412 +*/
1413 OUTPUT_ARCH(mips)
1414 SECTIONS
1415 {
1416 diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
1417 index 3a1e6d6..2ee6920 100644
1418 --- a/include/asm-mips/addrspace.h
1419 +++ b/include/asm-mips/addrspace.h
1420 @@ -131,7 +131,7 @@
1421 * Returns the uncached address of a sdram address
1422 */
1423 #ifndef __ASSEMBLY__
1424 -#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229)
1425 +#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229) || defined(CONFIG_JzRISC)
1426 /* We use a 36 bit physical address map here and
1427 cannot access physical memory directly from core */
1428 #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
1429 diff --git a/include/asm-mips/global_data.h b/include/asm-mips/global_data.h
1430 index b2c4891..23f597e 100644
1431 --- a/include/asm-mips/global_data.h
1432 +++ b/include/asm-mips/global_data.h
1433 @@ -39,6 +39,17 @@
1434 typedef struct global_data {
1435 bd_t *bd;
1436 unsigned long flags;
1437 +#if defined(CONFIG_JZSOC)
1438 + /* There are other clocks in the Jz47xx or Jz5730*/
1439 + unsigned long cpu_clk; /* CPU core clock */
1440 + unsigned long sys_clk; /* System bus clock */
1441 + unsigned long per_clk; /* Peripheral bus clock */
1442 + unsigned long mem_clk; /* Memory bus clock */
1443 + unsigned long dev_clk; /* Device clock */
1444 + unsigned long fb_base; /* base address of framebuffer */
1445 + unsigned long boot_option; /* 1: boot from sd
1446 + * 5: boot delay for 5 secs*/
1447 +#endif
1448 unsigned long baudrate;
1449 unsigned long have_console; /* serial_init() was called */
1450 phys_size_t ram_size; /* RAM size */
1451 diff --git a/include/lcd.h b/include/lcd.h
1452 index 1f85daa..997e246 100644
1453 --- a/include/lcd.h
1454 +++ b/include/lcd.h
1455 @@ -181,8 +181,44 @@ typedef struct vidinfo {
1456 u_long mmio; /* Memory mapped registers */
1457 } vidinfo_t;
1458
1459 -#else
1460 +#elif defined(CONFIG_JZSOC)
1461 +/*
1462 + * LCD controller stucture for JZSOC: JZ4730 JZ4740
1463 + */
1464 +struct jz_fb_dma_descriptor {
1465 + u_long fdadr; /* Frame descriptor address register */
1466 + u_long fsadr; /* Frame source address register */
1467 + u_long fidr; /* Frame ID register */
1468 + u_long ldcmd; /* Command register */
1469 +};
1470
1471 +/*
1472 + * Jz LCD info
1473 + */
1474 +struct jz_fb_info {
1475 +
1476 + u_long fdadr0; /* physical address of frame/palette descriptor */
1477 + u_long fdadr1; /* physical address of frame descriptor */
1478 +
1479 + /* DMA descriptors */
1480 + struct jz_fb_dma_descriptor * dmadesc_fblow;
1481 + struct jz_fb_dma_descriptor * dmadesc_fbhigh;
1482 + struct jz_fb_dma_descriptor * dmadesc_palette;
1483 + u_long screen; /* address of frame buffer */
1484 + u_long palette; /* address of palette memory */
1485 + u_int palette_size;
1486 +};
1487 +typedef struct vidinfo {
1488 + ushort vl_col; /* Number of columns (i.e. 640) */
1489 + ushort vl_row; /* Number of rows (i.e. 480) */
1490 + u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
1491 +
1492 + struct jz_fb_info jz_fb;
1493 +} vidinfo_t;
1494 +
1495 +extern vidinfo_t panel_info;
1496 +
1497 +#else
1498 typedef struct vidinfo {
1499 ushort vl_col; /* Number of columns (i.e. 160) */
1500 ushort vl_row; /* Number of rows (i.e. 100) */
1501 @@ -194,7 +230,7 @@ typedef struct vidinfo {
1502 void *priv; /* Pointer to driver-specific data */
1503 } vidinfo_t;
1504
1505 -#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 or CONFIG_ATMEL_LCD */
1506 +#endif /* CONFIG_MPC823, CONFIG_PXA250, CONFIG_MCC200 or CONFIG_JZ4740 */
1507
1508 extern vidinfo_t panel_info;
1509
1510 @@ -234,6 +270,7 @@ void lcd_show_board_info(void);
1511 #define LCD_COLOR4 2
1512 #define LCD_COLOR8 3
1513 #define LCD_COLOR16 4
1514 +#define LCD_COLOR32 5
1515
1516 /*----------------------------------------------------------------------*/
1517 #if defined(CONFIG_LCD_INFO_BELOW_LOGO)
1518 @@ -285,13 +322,22 @@ void lcd_show_board_info(void);
1519 # define CONSOLE_COLOR_GREY 14
1520 # define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */
1521
1522 -#else
1523 +#elif LCD_BPP == LCD_COLOR16
1524
1525 /*
1526 * 16bpp color definitions
1527 */
1528 # define CONSOLE_COLOR_BLACK 0x0000
1529 -# define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */
1530 +# define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */
1531 +
1532 +#elif LCD_BPP == LCD_COLOR32
1533 +/*
1534 + * 18,24,32 bpp color definitions
1535 + */
1536 +# define CONSOLE_COLOR_BLACK 0x00000000
1537 +# define CONSOLE_COLOR_WHITE 0xffffffff /* Must remain last / highest */
1538 +
1539 +#else
1540
1541 #endif /* color definitions */
1542
1543 @@ -322,7 +368,7 @@ void lcd_show_board_info(void);
1544 #if LCD_BPP == LCD_MONOCHROME
1545 # define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \
1546 (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7)
1547 -#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16)
1548 +#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) || (LCD_BPP == LCD_COLOR32)
1549 # define COLOR_MASK(c) (c)
1550 #else
1551 # error Unsupported LCD BPP.
1552 diff --git a/lib_mips/board.c b/lib_mips/board.c
1553 index b2d113e..87cb12d 100644
1554 --- a/lib_mips/board.c
1555 +++ b/lib_mips/board.c
1556 @@ -49,6 +49,10 @@ DECLARE_GLOBAL_DATA_PTR;
1557
1558 #undef DEBUG
1559
1560 +#if defined(CONFIG_JZSOC)
1561 +extern int jz_board_init(void);
1562 +#endif
1563 +
1564 extern int timer_init(void);
1565
1566 extern int incaip_set_cpuclk(void);
1567 @@ -78,7 +82,6 @@ int __board_early_init_f(void)
1568 }
1569 int board_early_init_f(void) __attribute__((weak, alias("__board_early_init_f")));
1570
1571 -
1572 static int init_func_ram (void)
1573 {
1574 #ifdef CONFIG_BOARD_TYPES
1575 @@ -98,7 +101,6 @@ static int init_func_ram (void)
1576
1577 static int display_banner(void)
1578 {
1579 -
1580 printf ("\n\n%s\n\n", version_string);
1581 return (0);
1582 }
1583 @@ -147,6 +149,9 @@ static int init_baudrate (void)
1584 typedef int (init_fnc_t) (void);
1585
1586 init_fnc_t *init_sequence[] = {
1587 +#if defined(CONFIG_JZSOC)
1588 + jz_board_init, /* init gpio/clocks/dram etc. */
1589 +#endif
1590 board_early_init_f,
1591 timer_init,
1592 env_init, /* initialize environment */
1593 @@ -162,7 +167,6 @@ init_fnc_t *init_sequence[] = {
1594 NULL,
1595 };
1596
1597 -
1598 void board_init_f(ulong bootflag)
1599 {
1600 gd_t gd_data, *id;
1601 @@ -202,6 +206,12 @@ void board_init_f(ulong bootflag)
1602 addr &= ~(4096 - 1);
1603 debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
1604
1605 +#ifdef CONFIG_LCD
1606 + /* reserve memory for LCD display (always full pages) */
1607 + addr = lcd_setmem (addr);
1608 + gd->fb_base = addr;
1609 +#endif /* CONFIG_LCD */
1610 +
1611 /* Reserve memory for U-Boot code, data & bss
1612 * round down to next 16 kB limit
1613 */
1614 @@ -349,9 +359,9 @@ void board_init_r (gd_t *id, ulong dest_addr)
1615 size = flash_init();
1616 display_flash_config (size);
1617 bd->bi_flashsize = size;
1618 + bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
1619 #endif
1620
1621 - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
1622 #if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
1623 bd->bi_flashoffset = monitor_flash_len; /* reserved area for U-Boot */
1624 #else
1625 diff --git a/lib_mips/bootm.c b/lib_mips/bootm.c
1626 index 54af24c..64bcad9 100644
1627 --- a/lib_mips/bootm.c
1628 +++ b/lib_mips/bootm.c
1629 @@ -46,7 +46,9 @@ static void linux_env_set (char * env_name, char * env_val);
1630 int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
1631 {
1632 void (*theKernel) (int, char **, char **, int *);
1633 - char *commandline = getenv ("bootargs");
1634 + char *commandline = gd->boot_option == 1 ?
1635 + getenv ("bootargsfromsd") :
1636 + getenv ("bootargs");
1637 char env_buf[12];
1638 char *cp;
1639
1640 @@ -98,6 +100,9 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
1641 }
1642
1643 /* we assume that the kernel is in place */
1644 + if (gd->boot_option == 1)
1645 + printf ("\n *** Booting from mircoSD ***\n");
1646 +
1647 printf ("\nStarting kernel ...\n\n");
1648
1649 theKernel (linux_argc, linux_argv, linux_env, 0);
1650 diff --git a/lib_mips/time.c b/lib_mips/time.c
1651 index 07e356d..4654bf4 100644
1652 --- a/lib_mips/time.c
1653 +++ b/lib_mips/time.c
1654 @@ -24,6 +24,8 @@
1655 #include <common.h>
1656 #include <asm/mipsregs.h>
1657
1658 +#ifndef CONFIG_JzRISC
1659 +
1660 static unsigned long timestamp;
1661
1662 /* how many counter cycles in a jiffy */
1663 @@ -96,3 +98,5 @@ ulong get_tbclk(void)
1664 {
1665 return CONFIG_SYS_HZ;
1666 }
1667 +
1668 +#endif /* !CONFIG_JzRISC */
1669
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