[kernel] 2.6.31: update generic config
[openwrt.git] / package / broadcom-wl / src / driver / sbhnddma.h
1 /*
2 * Generic Broadcom Home Networking Division (HND) DMA engine HW interface
3 * This supports the following chips: BCM42xx, 44xx, 47xx .
4 *
5 * Copyright 2007, Broadcom Corporation
6 * All Rights Reserved.
7 *
8 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12 *
13 */
14
15 #ifndef _sbhnddma_h_
16 #define _sbhnddma_h_
17
18 /* DMA structure:
19 * support two DMA engines: 32 bits address or 64 bit addressing
20 * basic DMA register set is per channel(transmit or receive)
21 * a pair of channels is defined for convenience
22 */
23
24
25 /* 32 bits addressing */
26
27 /* dma registers per channel(xmt or rcv) */
28 typedef volatile struct {
29 uint32 control; /* enable, et al */
30 uint32 addr; /* descriptor ring base address (4K aligned) */
31 uint32 ptr; /* last descriptor posted to chip */
32 uint32 status; /* current active descriptor, et al */
33 } dma32regs_t;
34
35 typedef volatile struct {
36 dma32regs_t xmt; /* dma tx channel */
37 dma32regs_t rcv; /* dma rx channel */
38 } dma32regp_t;
39
40 typedef volatile struct { /* diag access */
41 uint32 fifoaddr; /* diag address */
42 uint32 fifodatalow; /* low 32bits of data */
43 uint32 fifodatahigh; /* high 32bits of data */
44 uint32 pad; /* reserved */
45 } dma32diag_t;
46
47 /*
48 * DMA Descriptor
49 * Descriptors are only read by the hardware, never written back.
50 */
51 typedef volatile struct {
52 uint32 ctrl; /* misc control bits & bufcount */
53 uint32 addr; /* data buffer address */
54 } dma32dd_t;
55
56 /*
57 * Each descriptor ring must be 4096byte aligned, and fit within a single 4096byte page.
58 */
59 #define D32MAXRINGSZ 4096
60 #define D32RINGALIGN 4096
61 #define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t))
62
63 /* transmit channel control */
64 #define XC_XE ((uint32)1 << 0) /* transmit enable */
65 #define XC_SE ((uint32)1 << 1) /* transmit suspend request */
66 #define XC_LE ((uint32)1 << 2) /* loopback enable */
67 #define XC_FL ((uint32)1 << 4) /* flush request */
68 #define XC_AE ((uint32)3 << 16) /* address extension bits */
69 #define XC_AE_SHIFT 16
70
71 /* transmit descriptor table pointer */
72 #define XP_LD_MASK 0xfff /* last valid descriptor */
73
74 /* transmit channel status */
75 #define XS_CD_MASK 0x0fff /* current descriptor pointer */
76 #define XS_XS_MASK 0xf000 /* transmit state */
77 #define XS_XS_SHIFT 12
78 #define XS_XS_DISABLED 0x0000 /* disabled */
79 #define XS_XS_ACTIVE 0x1000 /* active */
80 #define XS_XS_IDLE 0x2000 /* idle wait */
81 #define XS_XS_STOPPED 0x3000 /* stopped */
82 #define XS_XS_SUSP 0x4000 /* suspend pending */
83 #define XS_XE_MASK 0xf0000 /* transmit errors */
84 #define XS_XE_SHIFT 16
85 #define XS_XE_NOERR 0x00000 /* no error */
86 #define XS_XE_DPE 0x10000 /* descriptor protocol error */
87 #define XS_XE_DFU 0x20000 /* data fifo underrun */
88 #define XS_XE_BEBR 0x30000 /* bus error on buffer read */
89 #define XS_XE_BEDA 0x40000 /* bus error on descriptor access */
90 #define XS_AD_MASK 0xfff00000 /* active descriptor */
91 #define XS_AD_SHIFT 20
92
93 /* receive channel control */
94 #define RC_RE ((uint32)1 << 0) /* receive enable */
95 #define RC_RO_MASK 0xfe /* receive frame offset */
96 #define RC_RO_SHIFT 1
97 #define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */
98 #define RC_AE ((uint32)3 << 16) /* address extension bits */
99 #define RC_AE_SHIFT 16
100
101 /* receive descriptor table pointer */
102 #define RP_LD_MASK 0xfff /* last valid descriptor */
103
104 /* receive channel status */
105 #define RS_CD_MASK 0x0fff /* current descriptor pointer */
106 #define RS_RS_MASK 0xf000 /* receive state */
107 #define RS_RS_SHIFT 12
108 #define RS_RS_DISABLED 0x0000 /* disabled */
109 #define RS_RS_ACTIVE 0x1000 /* active */
110 #define RS_RS_IDLE 0x2000 /* idle wait */
111 #define RS_RS_STOPPED 0x3000 /* reserved */
112 #define RS_RE_MASK 0xf0000 /* receive errors */
113 #define RS_RE_SHIFT 16
114 #define RS_RE_NOERR 0x00000 /* no error */
115 #define RS_RE_DPE 0x10000 /* descriptor protocol error */
116 #define RS_RE_DFO 0x20000 /* data fifo overflow */
117 #define RS_RE_BEBW 0x30000 /* bus error on buffer write */
118 #define RS_RE_BEDA 0x40000 /* bus error on descriptor access */
119 #define RS_AD_MASK 0xfff00000 /* active descriptor */
120 #define RS_AD_SHIFT 20
121
122 /* fifoaddr */
123 #define FA_OFF_MASK 0xffff /* offset */
124 #define FA_SEL_MASK 0xf0000 /* select */
125 #define FA_SEL_SHIFT 16
126 #define FA_SEL_XDD 0x00000 /* transmit dma data */
127 #define FA_SEL_XDP 0x10000 /* transmit dma pointers */
128 #define FA_SEL_RDD 0x40000 /* receive dma data */
129 #define FA_SEL_RDP 0x50000 /* receive dma pointers */
130 #define FA_SEL_XFD 0x80000 /* transmit fifo data */
131 #define FA_SEL_XFP 0x90000 /* transmit fifo pointers */
132 #define FA_SEL_RFD 0xc0000 /* receive fifo data */
133 #define FA_SEL_RFP 0xd0000 /* receive fifo pointers */
134 #define FA_SEL_RSD 0xe0000 /* receive frame status data */
135 #define FA_SEL_RSP 0xf0000 /* receive frame status pointers */
136
137 /* descriptor control flags */
138 #define CTRL_BC_MASK 0x1fff /* buffer byte count */
139 #define CTRL_AE ((uint32)3 << 16) /* address extension bits */
140 #define CTRL_AE_SHIFT 16
141 #define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */
142 #define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */
143 #define CTRL_EOF ((uint32)1 << 30) /* end of frame */
144 #define CTRL_SOF ((uint32)1 << 31) /* start of frame */
145
146 /* control flags in the range [27:20] are core-specific and not defined here */
147 #define CTRL_CORE_MASK 0x0ff00000
148
149 /* 64 bits addressing */
150
151 /* dma registers per channel(xmt or rcv) */
152 typedef volatile struct {
153 uint32 control; /* enable, et al */
154 uint32 ptr; /* last descriptor posted to chip */
155 uint32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */
156 uint32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */
157 uint32 status0; /* current descriptor, xmt state */
158 uint32 status1; /* active descriptor, xmt error */
159 } dma64regs_t;
160
161 typedef volatile struct {
162 dma64regs_t tx; /* dma64 tx channel */
163 dma64regs_t rx; /* dma64 rx channel */
164 } dma64regp_t;
165
166 typedef volatile struct { /* diag access */
167 uint32 fifoaddr; /* diag address */
168 uint32 fifodatalow; /* low 32bits of data */
169 uint32 fifodatahigh; /* high 32bits of data */
170 uint32 pad; /* reserved */
171 } dma64diag_t;
172
173 /*
174 * DMA Descriptor
175 * Descriptors are only read by the hardware, never written back.
176 */
177 typedef volatile struct {
178 uint32 ctrl1; /* misc control bits & bufcount */
179 uint32 ctrl2; /* buffer count and address extension */
180 uint32 addrlow; /* memory address of the date buffer, bits 31:0 */
181 uint32 addrhigh; /* memory address of the date buffer, bits 63:32 */
182 } dma64dd_t;
183
184 /*
185 * Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical addresss.
186 */
187 #define D64MAXRINGSZ 8192
188 #define D64RINGALIGN 8192
189 #define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t))
190
191 /* transmit channel control */
192 #define D64_XC_XE 0x00000001 /* transmit enable */
193 #define D64_XC_SE 0x00000002 /* transmit suspend request */
194 #define D64_XC_LE 0x00000004 /* loopback enable */
195 #define D64_XC_FL 0x00000010 /* flush request */
196 #define D64_XC_AE 0x00030000 /* address extension bits */
197 #define D64_XC_AE_SHIFT 16
198
199 /* transmit descriptor table pointer */
200 #define D64_XP_LD_MASK 0x00000fff /* last valid descriptor */
201
202 /* transmit channel status */
203 #define D64_XS0_CD_MASK 0x00001fff /* current descriptor pointer */
204 #define D64_XS0_XS_MASK 0xf0000000 /* transmit state */
205 #define D64_XS0_XS_SHIFT 28
206 #define D64_XS0_XS_DISABLED 0x00000000 /* disabled */
207 #define D64_XS0_XS_ACTIVE 0x10000000 /* active */
208 #define D64_XS0_XS_IDLE 0x20000000 /* idle wait */
209 #define D64_XS0_XS_STOPPED 0x30000000 /* stopped */
210 #define D64_XS0_XS_SUSP 0x40000000 /* suspend pending */
211
212 #define D64_XS1_AD_MASK 0x0001ffff /* active descriptor */
213 #define D64_XS1_XE_MASK 0xf0000000 /* transmit errors */
214 #define D64_XS1_XE_SHIFT 28
215 #define D64_XS1_XE_NOERR 0x00000000 /* no error */
216 #define D64_XS1_XE_DPE 0x10000000 /* descriptor protocol error */
217 #define D64_XS1_XE_DFU 0x20000000 /* data fifo underrun */
218 #define D64_XS1_XE_DTE 0x30000000 /* data transfer error */
219 #define D64_XS1_XE_DESRE 0x40000000 /* descriptor read error */
220 #define D64_XS1_XE_COREE 0x50000000 /* core error */
221
222 /* receive channel control */
223 #define D64_RC_RE 0x00000001 /* receive enable */
224 #define D64_RC_RO_MASK 0x000000fe /* receive frame offset */
225 #define D64_RC_RO_SHIFT 1
226 #define D64_RC_FM 0x00000100 /* direct fifo receive (pio) mode */
227 #define D64_RC_AE 0x00030000 /* address extension bits */
228 #define D64_RC_AE_SHIFT 16
229
230 /* receive descriptor table pointer */
231 #define D64_RP_LD_MASK 0x00000fff /* last valid descriptor */
232
233 /* receive channel status */
234 #define D64_RS0_CD_MASK 0x00001fff /* current descriptor pointer */
235 #define D64_RS0_RS_MASK 0xf0000000 /* receive state */
236 #define D64_RS0_RS_SHIFT 28
237 #define D64_RS0_RS_DISABLED 0x00000000 /* disabled */
238 #define D64_RS0_RS_ACTIVE 0x10000000 /* active */
239 #define D64_RS0_RS_IDLE 0x20000000 /* idle wait */
240 #define D64_RS0_RS_STOPPED 0x30000000 /* stopped */
241 #define D64_RS0_RS_SUSP 0x40000000 /* suspend pending */
242
243 #define D64_RS1_AD_MASK 0x0001ffff /* active descriptor */
244 #define D64_RS1_RE_MASK 0xf0000000 /* receive errors */
245 #define D64_RS1_RE_SHIFT 28
246 #define D64_RS1_RE_NOERR 0x00000000 /* no error */
247 #define D64_RS1_RE_DPO 0x10000000 /* descriptor protocol error */
248 #define D64_RS1_RE_DFU 0x20000000 /* data fifo overflow */
249 #define D64_RS1_RE_DTE 0x30000000 /* data transfer error */
250 #define D64_RS1_RE_DESRE 0x40000000 /* descriptor read error */
251 #define D64_RS1_RE_COREE 0x50000000 /* core error */
252
253 /* fifoaddr */
254 #define D64_FA_OFF_MASK 0xffff /* offset */
255 #define D64_FA_SEL_MASK 0xf0000 /* select */
256 #define D64_FA_SEL_SHIFT 16
257 #define D64_FA_SEL_XDD 0x00000 /* transmit dma data */
258 #define D64_FA_SEL_XDP 0x10000 /* transmit dma pointers */
259 #define D64_FA_SEL_RDD 0x40000 /* receive dma data */
260 #define D64_FA_SEL_RDP 0x50000 /* receive dma pointers */
261 #define D64_FA_SEL_XFD 0x80000 /* transmit fifo data */
262 #define D64_FA_SEL_XFP 0x90000 /* transmit fifo pointers */
263 #define D64_FA_SEL_RFD 0xc0000 /* receive fifo data */
264 #define D64_FA_SEL_RFP 0xd0000 /* receive fifo pointers */
265 #define D64_FA_SEL_RSD 0xe0000 /* receive frame status data */
266 #define D64_FA_SEL_RSP 0xf0000 /* receive frame status pointers */
267
268 /* descriptor control flags 1 */
269 #define D64_CTRL1_EOT ((uint32)1 << 28) /* end of descriptor table */
270 #define D64_CTRL1_IOC ((uint32)1 << 29) /* interrupt on completion */
271 #define D64_CTRL1_EOF ((uint32)1 << 30) /* end of frame */
272 #define D64_CTRL1_SOF ((uint32)1 << 31) /* start of frame */
273
274 /* descriptor control flags 2 */
275 #define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count mask */
276 #define D64_CTRL2_AE 0x00030000 /* address extension bits */
277 #define D64_CTRL2_AE_SHIFT 16
278
279 /* control flags in the range [27:20] are core-specific and not defined here */
280 #define D64_CTRL_CORE_MASK 0x0ff00000
281
282
283 #endif /* _sbhnddma_h_ */
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