package/rt2x00/src/rt73usb.h

   1 /*
   2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt73usb
  23         Abstract: Data structures and registers for the rt73usb module.
  24         Supported chipsets: rt2571W & rt2671.
  25  */
  26
  27 #ifndef RT73USB_H
  28 #define RT73USB_H
  29
  30 /*
  31  * RF chip defines.
  32  */
  33 #define RF5226                          0x0001
  34 #define RF2528                          0x0002
  35 #define RF5225                          0x0003
  36 #define RF2527                          0x0004
  37
  38 /*
  39  * Signal information.
  40  */
  41 #define MAX_RX_SSI                      -1
  42 #define MAX_RX_NOISE                    -110
  43 #define DEFAULT_RSSI_OFFSET             120
  44
  45 /*
  46  * Register layout information.
  47  */
  48 #define CSR_REG_BASE                    0x3000
  49 #define CSR_REG_SIZE                    0x04b0
  50 #define EEPROM_BASE                     0x0000
  51 #define EEPROM_SIZE                     0x0100
  52 #define BBP_SIZE                        0x0080
  53
  54 /*
  55  * USB registers.
  56  */
  57
  58 /*
  59  * MCU_LEDCS: LED control for MCU Mailbox.
  60  */
  61 #define MCU_LEDCS_LED_MODE              FIELD16(0x001f)
  62 #define MCU_LEDCS_RADIO_STATUS          FIELD16(0x0020)
  63 #define MCU_LEDCS_LINK_BG_STATUS        FIELD16(0x0040)
  64 #define MCU_LEDCS_LINK_A_STATUS         FIELD16(0x0080)
  65 #define MCU_LEDCS_POLARITY_GPIO_0       FIELD16(0x0100)
  66 #define MCU_LEDCS_POLARITY_GPIO_1       FIELD16(0x0200)
  67 #define MCU_LEDCS_POLARITY_GPIO_2       FIELD16(0x0400)
  68 #define MCU_LEDCS_POLARITY_GPIO_3       FIELD16(0x0800)
  69 #define MCU_LEDCS_POLARITY_GPIO_4       FIELD16(0x1000)
  70 #define MCU_LEDCS_POLARITY_ACT          FIELD16(0x2000)
  71 #define MCU_LEDCS_POLARITY_READY_BG     FIELD16(0x4000)
  72 #define MCU_LEDCS_POLARITY_READY_A      FIELD16(0x8000)
  73
  74 /*
  75  * 8051 firmware image.
  76  */
  77 #define FIRMWARE_RT2571                 "rt73.bin"
  78 #define FIRMWARE_IMAGE_BASE             0x0800
  79
  80 /*
  81  * Security key table memory.
  82  * 16 entries 32-byte for shared key table
  83  * 64 entries 32-byte for pairwise key table
  84  * 64 entries 8-byte for pairwise ta key table
  85  */
  86 #define SHARED_KEY_TABLE_BASE           0x1000
  87 #define PAIRWISE_KEY_TABLE_BASE         0x1200
  88 #define PAIRWISE_TA_TABLE_BASE          0x1a00
  89
  90 struct hw_key_entry {
  91         u8 key[16];
  92         u8 tx_mic[8];
  93         u8 rx_mic[8];
  94 } __attribute__ ((packed));
  95
  96 struct hw_pairwise_ta_entry {
  97         u8 address[6];
  98         u8 reserved[2];
  99 } __attribute__ ((packed));
 100
 101 /*
 102  * Since NULL frame won't be that long (256 byte),
 103  * We steal 16 tail bytes to save debugging settings.
 104  */
 105 #define HW_DEBUG_SETTING_BASE           0x2bf0
 106
 107 /*
 108  * On-chip BEACON frame space.
 109  */
 110 #define HW_BEACON_BASE0                 0x2400
 111 #define HW_BEACON_BASE1                 0x2500
 112 #define HW_BEACON_BASE2                 0x2600
 113 #define HW_BEACON_BASE3                 0x2700
 114
 115 /*
 116  * MAC Control/Status Registers(CSR).
 117  * Some values are set in TU, whereas 1 TU == 1024 us.
 118  */
 119
 120 /*
 121  * MAC_CSR0: ASIC revision number.
 122  */
 123 #define MAC_CSR0                        0x3000
 124
 125 /*
 126  * MAC_CSR1: System control register.
 127  * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
 128  * BBP_RESET: Hardware reset BBP.
 129  * HOST_READY: Host is ready after initialization, 1: ready.
 130  */
 131 #define MAC_CSR1                        0x3004
 132 #define MAC_CSR1_SOFT_RESET             FIELD32(0x00000001)
 133 #define MAC_CSR1_BBP_RESET              FIELD32(0x00000002)
 134 #define MAC_CSR1_HOST_READY             FIELD32(0x00000004)
 135
 136 /*
 137  * MAC_CSR2: STA MAC register 0.
 138  */
 139 #define MAC_CSR2                        0x3008
 140 #define MAC_CSR2_BYTE0                  FIELD32(0x000000ff)
 141 #define MAC_CSR2_BYTE1                  FIELD32(0x0000ff00)
 142 #define MAC_CSR2_BYTE2                  FIELD32(0x00ff0000)
 143 #define MAC_CSR2_BYTE3                  FIELD32(0xff000000)
 144
 145 /*
 146  * MAC_CSR3: STA MAC register 1.
 147  */
 148 #define MAC_CSR3                        0x300c
 149 #define MAC_CSR3_BYTE4                  FIELD32(0x000000ff)
 150 #define MAC_CSR3_BYTE5                  FIELD32(0x0000ff00)
 151 #define MAC_CSR3_UNICAST_TO_ME_MASK     FIELD32(0x00ff0000)
 152
 153 /*
 154  * MAC_CSR4: BSSID register 0.
 155  */
 156 #define MAC_CSR4                        0x3010
 157 #define MAC_CSR4_BYTE0                  FIELD32(0x000000ff)
 158 #define MAC_CSR4_BYTE1                  FIELD32(0x0000ff00)
 159 #define MAC_CSR4_BYTE2                  FIELD32(0x00ff0000)
 160 #define MAC_CSR4_BYTE3                  FIELD32(0xff000000)
 161
 162 /*
 163  * MAC_CSR5: BSSID register 1.
 164  * BSS_ID_MASK: 3: one BSSID, 0: 4 BSSID, 2 or 1: 2 BSSID.
 165  */
 166 #define MAC_CSR5                        0x3014
 167 #define MAC_CSR5_BYTE4                  FIELD32(0x000000ff)
 168 #define MAC_CSR5_BYTE5                  FIELD32(0x0000ff00)
 169 #define MAC_CSR5_BSS_ID_MASK            FIELD32(0x00ff0000)
 170
 171 /*
 172  * MAC_CSR6: Maximum frame length register.
 173  */
 174 #define MAC_CSR6                        0x3018
 175 #define MAC_CSR6_MAX_FRAME_UNIT         FIELD32(0x000007ff)
 176
 177 /*
 178  * MAC_CSR7: Reserved
 179  */
 180 #define MAC_CSR7                        0x301c
 181
 182 /*
 183  * MAC_CSR8: SIFS/EIFS register.
 184  * All units are in US.
 185  */
 186 #define MAC_CSR8                        0x3020
 187 #define MAC_CSR8_SIFS                   FIELD32(0x000000ff)
 188 #define MAC_CSR8_SIFS_AFTER_RX_OFDM     FIELD32(0x0000ff00)
 189 #define MAC_CSR8_EIFS                   FIELD32(0xffff0000)
 190
 191 /*
 192  * MAC_CSR9: Back-Off control register.
 193  * SLOT_TIME: Slot time, default is 20us for 802.11BG.
 194  * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
 195  * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
 196  * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
 197  */
 198 #define MAC_CSR9                        0x3024
 199 #define MAC_CSR9_SLOT_TIME              FIELD32(0x000000ff)
 200 #define MAC_CSR9_CWMIN                  FIELD32(0x00000f00)
 201 #define MAC_CSR9_CWMAX                  FIELD32(0x0000f000)
 202 #define MAC_CSR9_CW_SELECT              FIELD32(0x00010000)
 203
 204 /*
 205  * MAC_CSR10: Power state configuration.
 206  */
 207 #define MAC_CSR10                       0x3028
 208
 209 /*
 210  * MAC_CSR11: Power saving transition time register.
 211  * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
 212  * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
 213  * WAKEUP_LATENCY: In unit of TU.
 214  */
 215 #define MAC_CSR11                       0x302c
 216 #define MAC_CSR11_DELAY_AFTER_TBCN      FIELD32(0x000000ff)
 217 #define MAC_CSR11_TBCN_BEFORE_WAKEUP    FIELD32(0x00007f00)
 218 #define MAC_CSR11_AUTOWAKE              FIELD32(0x00008000)
 219 #define MAC_CSR11_WAKEUP_LATENCY        FIELD32(0x000f0000)
 220
 221 /*
 222  * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
 223  * CURRENT_STATE: 0:sleep, 1:awake.
 224  * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
 225  * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
 226  */
 227 #define MAC_CSR12                       0x3030
 228 #define MAC_CSR12_CURRENT_STATE         FIELD32(0x00000001)
 229 #define MAC_CSR12_PUT_TO_SLEEP          FIELD32(0x00000002)
 230 #define MAC_CSR12_FORCE_WAKEUP          FIELD32(0x00000004)
 231 #define MAC_CSR12_BBP_CURRENT_STATE     FIELD32(0x00000008)
 232
 233 /*
 234  * MAC_CSR13: GPIO.
 235  */
 236 #define MAC_CSR13                       0x3034
 237
 238 /*
 239  * MAC_CSR14: LED control register.
 240  * ON_PERIOD: On period, default 70ms.
 241  * OFF_PERIOD: Off period, default 30ms.
 242  * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
 243  * SW_LED: s/w LED, 1: ON, 0: OFF.
 244  * HW_LED_POLARITY: 0: active low, 1: active high.
 245  */
 246 #define MAC_CSR14                       0x3038
 247 #define MAC_CSR14_ON_PERIOD             FIELD32(0x000000ff)
 248 #define MAC_CSR14_OFF_PERIOD            FIELD32(0x0000ff00)
 249 #define MAC_CSR14_HW_LED                FIELD32(0x00010000)
 250 #define MAC_CSR14_SW_LED                FIELD32(0x00020000)
 251 #define MAC_CSR14_HW_LED_POLARITY       FIELD32(0x00040000)
 252 #define MAC_CSR14_SW_LED2               FIELD32(0x00080000)
 253
 254 /*
 255  * MAC_CSR15: NAV control.
 256  */
 257 #define MAC_CSR15                       0x303c
 258
 259 /*
 260  * TXRX control registers.
 261  * Some values are set in TU, whereas 1 TU == 1024 us.
 262  */
 263
 264 /*
 265  * TXRX_CSR0: TX/RX configuration register.
 266  * TSF_OFFSET: Default is 24.
 267  * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
 268  * DISABLE_RX: Disable Rx engine.
 269  * DROP_CRC: Drop CRC error.
 270  * DROP_PHYSICAL: Drop physical error.
 271  * DROP_CONTROL: Drop control frame.
 272  * DROP_NOT_TO_ME: Drop not to me unicast frame.
 273  * DROP_TO_DS: Drop fram ToDs bit is true.
 274  * DROP_VERSION_ERROR: Drop version error frame.
 275  * DROP_MULTICAST: Drop multicast frames.
 276  * DROP_BORADCAST: Drop broadcast frames.
 277  * ROP_ACK_CTS: Drop received ACK and CTS.
 278  */
 279 #define TXRX_CSR0                       0x3040
 280 #define TXRX_CSR0_RX_ACK_TIMEOUT        FIELD32(0x000001ff)
 281 #define TXRX_CSR0_TSF_OFFSET            FIELD32(0x00007e00)
 282 #define TXRX_CSR0_AUTO_TX_SEQ           FIELD32(0x00008000)
 283 #define TXRX_CSR0_DISABLE_RX            FIELD32(0x00010000)
 284 #define TXRX_CSR0_DROP_CRC              FIELD32(0x00020000)
 285 #define TXRX_CSR0_DROP_PHYSICAL         FIELD32(0x00040000)
 286 #define TXRX_CSR0_DROP_CONTROL          FIELD32(0x00080000)
 287 #define TXRX_CSR0_DROP_NOT_TO_ME        FIELD32(0x00100000)
 288 #define TXRX_CSR0_DROP_TO_DS            FIELD32(0x00200000)
 289 #define TXRX_CSR0_DROP_VERSION_ERROR    FIELD32(0x00400000)
 290 #define TXRX_CSR0_DROP_MULTICAST        FIELD32(0x00800000)
 291 #define TXRX_CSR0_DROP_BORADCAST        FIELD32(0x01000000)
 292 #define TXRX_CSR0_DROP_ACK_CTS          FIELD32(0x02000000)
 293 #define TXRX_CSR0_TX_WITHOUT_WAITING    FIELD32(0x04000000)
 294
 295 /*
 296  * TXRX_CSR1
 297  */
 298 #define TXRX_CSR1                       0x3044
 299
 300 /*
 301  * TXRX_CSR2
 302  */
 303 #define TXRX_CSR2                       0x3048
 304
 305 /*
 306  * TXRX_CSR3
 307  */
 308 #define TXRX_CSR3                       0x304c
 309
 310 /*
 311  * TXRX_CSR4: Auto-Responder/Tx-retry register.
 312  * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
 313  * OFDM_TX_RATE_DOWN: 1:enable.
 314  * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
 315  * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
 316  */
 317 #define TXRX_CSR4                       0x3050
 318 #define TXRX_CSR4_TX_ACK_TIMEOUT        FIELD32(0x000000ff)
 319 #define TXRX_CSR4_CNTL_ACK_POLICY       FIELD32(0x00000700)
 320 #define TXRX_CSR4_ACK_CTS_PSM           FIELD32(0x00010000)
 321 #define TXRX_CSR4_AUTORESPOND_ENABLE    FIELD32(0x00020000)
 322 #define TXRX_CSR4_AUTORESPOND_PREAMBLE  FIELD32(0x00040000)
 323 #define TXRX_CSR4_OFDM_TX_RATE_DOWN     FIELD32(0x00080000)
 324 #define TXRX_CSR4_OFDM_TX_RATE_STEP     FIELD32(0x00300000)
 325 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK  FIELD32(0x00400000)
 326 #define TXRX_CSR4_LONG_RETRY_LIMIT      FIELD32(0x0f000000)
 327 #define TXRX_CSR4_SHORT_RETRY_LIMIT     FIELD32(0xf0000000)
 328
 329 /*
 330  * TXRX_CSR5
 331  */
 332 #define TXRX_CSR5                       0x3054
 333
 334 /*
 335  * ACK/CTS payload consumed time registers.
 336  */
 337 #define TXRX_CSR6                       0x3058
 338 #define TXRX_CSR7                       0x305c
 339 #define TXRX_CSR8                       0x3060
 340
 341 /*
 342  * TXRX_CSR9: Synchronization control register.
 343  * BEACON_INTERVAL: In unit of 1/16 TU.
 344  * TSF_TICKING: Enable TSF auto counting.
 345  * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
 346  * BEACON_GEN: Enable beacon generator.
 347  */
 348 #define TXRX_CSR9                       0x3064
 349 #define TXRX_CSR9_BEACON_INTERVAL       FIELD32(0x0000ffff)
 350 #define TXRX_CSR9_TSF_TICKING           FIELD32(0x00010000)
 351 #define TXRX_CSR9_TSF_SYNC              FIELD32(0x00060000)
 352 #define TXRX_CSR9_TBTT_ENABLE           FIELD32(0x00080000)
 353 #define TXRX_CSR9_BEACON_GEN            FIELD32(0x00100000)
 354 #define TXRX_CSR9_TIMESTAMP_COMPENSATE  FIELD32(0xff000000)
 355
 356 /*
 357  * TXRX_CSR10: BEACON alignment.
 358  */
 359 #define TXRX_CSR10                      0x3068
 360
 361 /*
 362  * TXRX_CSR11: AES mask.
 363  */
 364 #define TXRX_CSR11                      0x306c
 365
 366 /*
 367  * TXRX_CSR12: TSF low 32.
 368  */
 369 #define TXRX_CSR12                      0x3070
 370 #define TXRX_CSR12_LOW_TSFTIMER         FIELD32(0xffffffff)
 371
 372 /*
 373  * TXRX_CSR13: TSF high 32.
 374  */
 375 #define TXRX_CSR13                      0x3074
 376 #define TXRX_CSR13_HIGH_TSFTIMER        FIELD32(0xffffffff)
 377
 378 /*
 379  * TXRX_CSR14: TBTT timer.
 380  */
 381 #define TXRX_CSR14                      0x3078
 382
 383 /*
 384  * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
 385  */
 386 #define TXRX_CSR15                      0x307c
 387
 388 /*
 389  * PHY control registers.
 390  * Some values are set in TU, whereas 1 TU == 1024 us.
 391  */
 392
 393 /*
 394  * PHY_CSR0: RF/PS control.
 395  */
 396 #define PHY_CSR0                        0x3080
 397 #define PHY_CSR0_PA_PE_BG               FIELD32(0x00010000)
 398 #define PHY_CSR0_PA_PE_A                FIELD32(0x00020000)
 399
 400 /*
 401  * PHY_CSR1
 402  */
 403 #define PHY_CSR1                        0x3084
 404 #define PHY_CSR1_RF_RPI                 FIELD32(0x00010000)
 405
 406
 407 /*
 408  * PHY_CSR2: Pre-TX BBP control.
 409  */
 410 #define PHY_CSR2                        0x3088
 411
 412 /*
 413  * PHY_CSR3: BBP serial control register.
 414  * VALUE: Register value to program into BBP.
 415  * REG_NUM: Selected BBP register.
 416  * READ_CONTROL: 0: Write BBP, 1: Read BBP.
 417  * BUSY: 1: ASIC is busy execute BBP programming.
 418  */
 419 #define PHY_CSR3                        0x308c
 420 #define PHY_CSR3_VALUE                  FIELD32(0x000000ff)
 421 #define PHY_CSR3_REGNUM                 FIELD32(0x00007f00)
 422 #define PHY_CSR3_READ_CONTROL           FIELD32(0x00008000)
 423 #define PHY_CSR3_BUSY                   FIELD32(0x00010000)
 424
 425 /*
 426  * PHY_CSR4: RF serial control register
 427  * VALUE: Register value (include register id) serial out to RF/IF chip.
 428  * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
 429  * IF_SELECT: 1: select IF to program, 0: select RF to program.
 430  * PLL_LD: RF PLL_LD status.
 431  * BUSY: 1: ASIC is busy execute RF programming.
 432  */
 433 #define PHY_CSR4                        0x3090
 434 #define PHY_CSR4_VALUE                  FIELD32(0x00ffffff)
 435 #define PHY_CSR4_NUMBER_OF_BITS         FIELD32(0x1f000000)
 436 #define PHY_CSR4_IF_SELECT              FIELD32(0x20000000)
 437 #define PHY_CSR4_PLL_LD                 FIELD32(0x40000000)
 438 #define PHY_CSR4_BUSY                   FIELD32(0x80000000)
 439
 440 /*
 441  * PHY_CSR5: RX to TX signal switch timing control.
 442  */
 443 #define PHY_CSR5                        0x3094
 444
 445 /*
 446  * PHY_CSR6: TX to RX signal timing control.
 447  */
 448 #define PHY_CSR6                        0x3098
 449
 450 /*
 451  * PHY_CSR7: TX DAC switching timing control.
 452  */
 453 #define PHY_CSR7                        0x309c
 454
 455 /*
 456  * Security control register.
 457  */
 458
 459 /*
 460  * SEC_CSR0: Shared key table control.
 461  */
 462 #define SEC_CSR0                        0x30a0
 463
 464 /*
 465  * SEC_CSR1: Shared key table security mode register.
 466  */
 467 #define SEC_CSR1                        0x30a4
 468 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG   FIELD32(0x00000007)
 469 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG   FIELD32(0x00000070)
 470 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG   FIELD32(0x00000700)
 471 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG   FIELD32(0x00007000)
 472 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG   FIELD32(0x00070000)
 473 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG   FIELD32(0x00700000)
 474 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG   FIELD32(0x07000000)
 475 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG   FIELD32(0x70000000)
 476
 477 /*
 478  * Pairwise key table valid bitmap registers.
 479  * SEC_CSR2: pairwise key table valid bitmap 0.
 480  * SEC_CSR3: pairwise key table valid bitmap 1.
 481  */
 482 #define SEC_CSR2                        0x30a8
 483 #define SEC_CSR3                        0x30ac
 484
 485 /*
 486  * SEC_CSR4: Pairwise key table lookup control.
 487  */
 488 #define SEC_CSR4                        0x30b0
 489
 490 /*
 491  * SEC_CSR5: shared key table security mode register.
 492  */
 493 #define SEC_CSR5                        0x30b4
 494 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG   FIELD32(0x00000007)
 495 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG   FIELD32(0x00000070)
 496 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG   FIELD32(0x00000700)
 497 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG   FIELD32(0x00007000)
 498 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG   FIELD32(0x00070000)
 499 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG   FIELD32(0x00700000)
 500 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG   FIELD32(0x07000000)
 501 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG   FIELD32(0x70000000)
 502
 503 /*
 504  * STA control registers.
 505  */
 506
 507 /*
 508  * STA_CSR0: RX PLCP error count & RX FCS error count.
 509  */
 510 #define STA_CSR0                        0x30c0
 511 #define STA_CSR0_FCS_ERROR              FIELD32(0x0000ffff)
 512 #define STA_CSR0_PLCP_ERROR             FIELD32(0xffff0000)
 513
 514 /*
 515  * STA_CSR1: RX False CCA count & RX LONG frame count.
 516  */
 517 #define STA_CSR1                        0x30c4
 518 #define STA_CSR1_PHYSICAL_ERROR         FIELD32(0x0000ffff)
 519 #define STA_CSR1_FALSE_CCA_ERROR        FIELD32(0xffff0000)
 520
 521 /*
 522  * STA_CSR2: TX Beacon count and RX FIFO overflow count.
 523  */
 524 #define STA_CSR2                        0x30c8
 525 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
 526 #define STA_CSR2_RX_OVERFLOW_COUNT      FIELD32(0xffff0000)
 527
 528 /*
 529  * STA_CSR3: TX Beacon count.
 530  */
 531 #define STA_CSR3                        0x30cc
 532 #define STA_CSR3_TX_BEACON_COUNT        FIELD32(0x0000ffff)
 533
 534 /*
 535  * STA_CSR4: TX Retry count.
 536  */
 537 #define STA_CSR4                        0x30d0
 538 #define STA_CSR4_TX_NO_RETRY_COUNT      FIELD32(0x0000ffff)
 539 #define STA_CSR4_TX_ONE_RETRY_COUNT     FIELD32(0xffff0000)
 540
 541 /*
 542  * STA_CSR5: TX Retry count.
 543  */
 544 #define STA_CSR5                        0x30d4
 545 #define STA_CSR4_TX_MULTI_RETRY_COUNT   FIELD32(0x0000ffff)
 546 #define STA_CSR4_TX_RETRY_FAIL_COUNT    FIELD32(0xffff0000)
 547
 548 /*
 549  * QOS control registers.
 550  */
 551
 552 /*
 553  * QOS_CSR1: TXOP holder MAC address register.
 554  */
 555 #define QOS_CSR1                        0x30e4
 556 #define QOS_CSR1_BYTE4                  FIELD32(0x000000ff)
 557 #define QOS_CSR1_BYTE5                  FIELD32(0x0000ff00)
 558
 559 /*
 560  * QOS_CSR2: TXOP holder timeout register.
 561  */
 562 #define QOS_CSR2                        0x30e8
 563
 564 /*
 565  * RX QOS-CFPOLL MAC address register.
 566  * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
 567  * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
 568  */
 569 #define QOS_CSR3                        0x30ec
 570 #define QOS_CSR4                        0x30f0
 571
 572 /*
 573  * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
 574  */
 575 #define QOS_CSR5                        0x30f4
 576
 577 /*
 578  * WMM Scheduler Register
 579  */
 580
 581 /*
 582  * AIFSN_CSR: AIFSN for each EDCA AC.
 583  * AIFSN0: For AC_BK.
 584  * AIFSN1: For AC_BE.
 585  * AIFSN2: For AC_VI.
 586  * AIFSN3: For AC_VO.
 587  */
 588 #define AIFSN_CSR                       0x0400
 589 #define AIFSN_CSR_AIFSN0                FIELD32(0x0000000f)
 590 #define AIFSN_CSR_AIFSN1                FIELD32(0x000000f0)
 591 #define AIFSN_CSR_AIFSN2                FIELD32(0x00000f00)
 592 #define AIFSN_CSR_AIFSN3                FIELD32(0x0000f000)
 593
 594 /*
 595  * CWMIN_CSR: CWmin for each EDCA AC.
 596  * CWMIN0: For AC_BK.
 597  * CWMIN1: For AC_BE.
 598  * CWMIN2: For AC_VI.
 599  * CWMIN3: For AC_VO.
 600  */
 601 #define CWMIN_CSR                       0x0404
 602 #define CWMIN_CSR_CWMIN0                FIELD32(0x0000000f)
 603 #define CWMIN_CSR_CWMIN1                FIELD32(0x000000f0)
 604 #define CWMIN_CSR_CWMIN2                FIELD32(0x00000f00)
 605 #define CWMIN_CSR_CWMIN3                FIELD32(0x0000f000)
 606
 607 /*
 608  * CWMAX_CSR: CWmax for each EDCA AC.
 609  * CWMAX0: For AC_BK.
 610  * CWMAX1: For AC_BE.
 611  * CWMAX2: For AC_VI.
 612  * CWMAX3: For AC_VO.
 613  */
 614 #define CWMAX_CSR                       0x0408
 615 #define CWMAX_CSR_CWMAX0                FIELD32(0x0000000f)
 616 #define CWMAX_CSR_CWMAX1                FIELD32(0x000000f0)
 617 #define CWMAX_CSR_CWMAX2                FIELD32(0x00000f00)
 618 #define CWMAX_CSR_CWMAX3                FIELD32(0x0000f000)
 619
 620 /*
 621  * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
 622  * AC0_TX_OP: For AC_BK, in unit of 32us.
 623  * AC1_TX_OP: For AC_BE, in unit of 32us.
 624  */
 625 #define AC_TXOP_CSR0                    0x040c
 626 #define AC_TXOP_CSR0_AC0_TX_OP          FIELD32(0x0000ffff)
 627 #define AC_TXOP_CSR0_AC1_TX_OP          FIELD32(0xffff0000)
 628
 629 /*
 630  * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
 631  * AC2_TX_OP: For AC_VI, in unit of 32us.
 632  * AC3_TX_OP: For AC_VO, in unit of 32us.
 633  */
 634 #define AC_TXOP_CSR1                    0x0410
 635 #define AC_TXOP_CSR1_AC2_TX_OP          FIELD32(0x0000ffff)
 636 #define AC_TXOP_CSR1_AC3_TX_OP          FIELD32(0xffff0000)
 637
 638 /*
 639  * RF registers
 640  */
 641 #define RF3_TXPOWER                     FIELD32(0x00003e00)
 642 #define RF4_FREQ_OFFSET                 FIELD32(0x0003f000)
 643
 644 /*
 645  * EEPROM content.
 646  * The wordsize of the EEPROM is 16 bits.
 647  */
 648
 649 /*
 650  * HW MAC address.
 651  */
 652 #define EEPROM_MAC_ADDR_0               0x0002
 653 #define EEPROM_MAC_ADDR_BYTE0           FIELD16(0x00ff)
 654 #define EEPROM_MAC_ADDR_BYTE1           FIELD16(0xff00)
 655 #define EEPROM_MAC_ADDR1                0x0003
 656 #define EEPROM_MAC_ADDR_BYTE2           FIELD16(0x00ff)
 657 #define EEPROM_MAC_ADDR_BYTE3           FIELD16(0xff00)
 658 #define EEPROM_MAC_ADDR_2               0x0004
 659 #define EEPROM_MAC_ADDR_BYTE4           FIELD16(0x00ff)
 660 #define EEPROM_MAC_ADDR_BYTE5           FIELD16(0xff00)
 661
 662 /*
 663  * EEPROM antenna.
 664  * ANTENNA_NUM: Number of antenna's.
 665  * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
 666  * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
 667  * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
 668  * DYN_TXAGC: Dynamic TX AGC control.
 669  * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
 670  * RF_TYPE: Rf_type of this adapter.
 671  */
 672 #define EEPROM_ANTENNA                  0x0010
 673 #define EEPROM_ANTENNA_NUM              FIELD16(0x0003)
 674 #define EEPROM_ANTENNA_TX_DEFAULT       FIELD16(0x000c)
 675 #define EEPROM_ANTENNA_RX_DEFAULT       FIELD16(0x0030)
 676 #define EEPROM_ANTENNA_FRAME_TYPE       FIELD16(0x0040)
 677 #define EEPROM_ANTENNA_DYN_TXAGC        FIELD16(0x0200)
 678 #define EEPROM_ANTENNA_HARDWARE_RADIO   FIELD16(0x0400)
 679 #define EEPROM_ANTENNA_RF_TYPE          FIELD16(0xf800)
 680
 681 /*
 682  * EEPROM NIC config.
 683  * EXTERNAL_LNA: External LNA.
 684  */
 685 #define EEPROM_NIC                      0x0011
 686 #define EEPROM_NIC_EXTERNAL_LNA         FIELD16(0x0010)
 687
 688 /*
 689  * EEPROM geography.
 690  * GEO_A: Default geographical setting for 5GHz band
 691  * GEO: Default geographical setting.
 692  */
 693 #define EEPROM_GEOGRAPHY                0x0012
 694 #define EEPROM_GEOGRAPHY_GEO_A          FIELD16(0x00ff)
 695 #define EEPROM_GEOGRAPHY_GEO            FIELD16(0xff00)
 696
 697 /*
 698  * EEPROM BBP.
 699  */
 700 #define EEPROM_BBP_START                0x0013
 701 #define EEPROM_BBP_SIZE                 16
 702 #define EEPROM_BBP_VALUE                FIELD16(0x00ff)
 703 #define EEPROM_BBP_REG_ID               FIELD16(0xff00)
 704
 705 /*
 706  * EEPROM TXPOWER 802.11G
 707  */
 708 #define EEPROM_TXPOWER_G_START          0x0023
 709 #define EEPROM_TXPOWER_G_SIZE           7
 710 #define EEPROM_TXPOWER_G_1              FIELD16(0x00ff)
 711 #define EEPROM_TXPOWER_G_2              FIELD16(0xff00)
 712
 713 /*
 714  * EEPROM Frequency
 715  */
 716 #define EEPROM_FREQ                     0x002f
 717 #define EEPROM_FREQ_OFFSET              FIELD16(0x00ff)
 718 #define EEPROM_FREQ_SEQ_MASK            FIELD16(0xff00)
 719 #define EEPROM_FREQ_SEQ                 FIELD16(0x0300)
 720
 721 /*
 722  * EEPROM LED.
 723  * POLARITY_RDY_G: Polarity RDY_G setting.
 724  * POLARITY_RDY_A: Polarity RDY_A setting.
 725  * POLARITY_ACT: Polarity ACT setting.
 726  * POLARITY_GPIO_0: Polarity GPIO0 setting.
 727  * POLARITY_GPIO_1: Polarity GPIO1 setting.
 728  * POLARITY_GPIO_2: Polarity GPIO2 setting.
 729  * POLARITY_GPIO_3: Polarity GPIO3 setting.
 730  * POLARITY_GPIO_4: Polarity GPIO4 setting.
 731  * LED_MODE: Led mode.
 732  */
 733 #define EEPROM_LED                      0x0030
 734 #define EEPROM_LED_POLARITY_RDY_G       FIELD16(0x0001)
 735 #define EEPROM_LED_POLARITY_RDY_A       FIELD16(0x0002)
 736 #define EEPROM_LED_POLARITY_ACT         FIELD16(0x0004)
 737 #define EEPROM_LED_POLARITY_GPIO_0      FIELD16(0x0008)
 738 #define EEPROM_LED_POLARITY_GPIO_1      FIELD16(0x0010)
 739 #define EEPROM_LED_POLARITY_GPIO_2      FIELD16(0x0020)
 740 #define EEPROM_LED_POLARITY_GPIO_3      FIELD16(0x0040)
 741 #define EEPROM_LED_POLARITY_GPIO_4      FIELD16(0x0080)
 742 #define EEPROM_LED_LED_MODE             FIELD16(0x1f00)
 743
 744 /*
 745  * EEPROM TXPOWER 802.11A
 746  */
 747 #define EEPROM_TXPOWER_A_START          0x0031
 748 #define EEPROM_TXPOWER_A_SIZE           12
 749 #define EEPROM_TXPOWER_A_1              FIELD16(0x00ff)
 750 #define EEPROM_TXPOWER_A_2              FIELD16(0xff00)
 751
 752 /*
 753  * EEPROM RSSI offset 802.11BG
 754  */
 755 #define EEPROM_RSSI_OFFSET_BG           0x004d
 756 #define EEPROM_RSSI_OFFSET_BG_1         FIELD16(0x00ff)
 757 #define EEPROM_RSSI_OFFSET_BG_2         FIELD16(0xff00)
 758
 759 /*
 760  * EEPROM RSSI offset 802.11A
 761  */
 762 #define EEPROM_RSSI_OFFSET_A            0x004e
 763 #define EEPROM_RSSI_OFFSET_A_1          FIELD16(0x00ff)
 764 #define EEPROM_RSSI_OFFSET_A_2          FIELD16(0xff00)
 765
 766 /*
 767  * BBP content.
 768  * The wordsize of the BBP is 8 bits.
 769  */
 770
 771 /*
 772  * BBP_R2
 773  */
 774 #define BBP_R2_BG_MODE                  FIELD8(0x20)
 775
 776 /*
 777  * BBP_R3
 778  */
 779 #define BBP_R3_SMART_MODE               FIELD8(0x01)
 780
 781 /*
 782  * BBP_R4: RX antenna control
 783  * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
 784  */
 785 #define BBP_R4_RX_ANTENNA               FIELD8(0x03)
 786 #define BBP_R4_RX_FRAME_END             FIELD8(0x10)
 787 #define BBP_R4_RX_BG_MODE               FIELD8(0x20)
 788
 789 /*
 790  * BBP_R77
 791  */
 792 #define BBP_R77_PAIR                    FIELD8(0x03)
 793
 794 /*
 795  * DMA descriptor defines.
 796  */
 797 #define TXD_DESC_SIZE                   ( 6 * sizeof(struct data_desc) )
 798 #define RXD_DESC_SIZE                   ( 6 * sizeof(struct data_desc) )
 799
 800 /*
 801  * TX descriptor format for TX, PRIO and Beacon Ring.
 802  */
 803
 804 /*
 805  * Word0
 806  * BURST: Next frame belongs to same "burst" event.
 807  * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
 808  * KEY_TABLE: Use per-client pairwise KEY table.
 809  * KEY_INDEX:
 810  * Key index (0~31) to the pairwise KEY table.
 811  * 0~3 to shared KEY table 0 (BSS0).
 812  * 4~7 to shared KEY table 1 (BSS1).
 813  * 8~11 to shared KEY table 2 (BSS2).
 814  * 12~15 to shared KEY table 3 (BSS3).
 815  * BURST2: For backward compatibility, set to same value as BURST.
 816  */
 817 #define TXD_W0_BURST                    FIELD32(0x00000001)
 818 #define TXD_W0_VALID                    FIELD32(0x00000002)
 819 #define TXD_W0_MORE_FRAG                FIELD32(0x00000004)
 820 #define TXD_W0_ACK                      FIELD32(0x00000008)
 821 #define TXD_W0_TIMESTAMP                FIELD32(0x00000010)
 822 #define TXD_W0_OFDM                     FIELD32(0x00000020)
 823 #define TXD_W0_IFS                      FIELD32(0x00000040)
 824 #define TXD_W0_RETRY_MODE               FIELD32(0x00000080)
 825 #define TXD_W0_TKIP_MIC                 FIELD32(0x00000100)
 826 #define TXD_W0_KEY_TABLE                FIELD32(0x00000200)
 827 #define TXD_W0_KEY_INDEX                FIELD32(0x0000fc00)
 828 #define TXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
 829 #define TXD_W0_BURST2                   FIELD32(0x10000000)
 830 #define TXD_W0_CIPHER_ALG               FIELD32(0xe0000000)
 831
 832 /*
 833  * Word1
 834  * HOST_Q_ID: EDCA/HCCA queue ID.
 835  * HW_SEQUENCE: MAC overwrites the frame sequence number.
 836  * BUFFER_COUNT: Number of buffers in this TXD.
 837  */
 838 #define TXD_W1_HOST_Q_ID                FIELD32(0x0000000f)
 839 #define TXD_W1_AIFSN                    FIELD32(0x000000f0)
 840 #define TXD_W1_CWMIN                    FIELD32(0x00000f00)
 841 #define TXD_W1_CWMAX                    FIELD32(0x0000f000)
 842 #define TXD_W1_IV_OFFSET                FIELD32(0x003f0000)
 843 #define TXD_W1_HW_SEQUENCE              FIELD32(0x10000000)
 844 #define TXD_W1_BUFFER_COUNT             FIELD32(0xe0000000)
 845
 846 /*
 847  * Word2: PLCP information
 848  */
 849 #define TXD_W2_PLCP_SIGNAL              FIELD32(0x000000ff)
 850 #define TXD_W2_PLCP_SERVICE             FIELD32(0x0000ff00)
 851 #define TXD_W2_PLCP_LENGTH_LOW          FIELD32(0x00ff0000)
 852 #define TXD_W2_PLCP_LENGTH_HIGH         FIELD32(0xff000000)
 853
 854 /*
 855  * Word3
 856  */
 857 #define TXD_W3_IV                       FIELD32(0xffffffff)
 858
 859 /*
 860  * Word4
 861  */
 862 #define TXD_W4_EIV                      FIELD32(0xffffffff)
 863
 864 /*
 865  * Word5
 866  * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
 867  * PACKET_ID: Driver assigned packet ID to categorize TXResult in interrupt.
 868  * WAITING_DMA_DONE_INT: TXD been filled with data
 869  * and waiting for TxDoneISR housekeeping.
 870  */
 871 #define TXD_W5_FRAME_OFFSET             FIELD32(0x000000ff)
 872 #define TXD_W5_PACKET_ID                FIELD32(0x0000ff00)
 873 #define TXD_W5_TX_POWER                 FIELD32(0x00ff0000)
 874 #define TXD_W5_WAITING_DMA_DONE_INT     FIELD32(0x01000000)
 875
 876 /*
 877  * RX descriptor format for RX Ring.
 878  */
 879
 880 /*
 881  * Word0
 882  * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
 883  * KEY_INDEX: Decryption key actually used.
 884  */
 885 #define RXD_W0_OWNER_NIC                FIELD32(0x00000001)
 886 #define RXD_W0_DROP                     FIELD32(0x00000002)
 887 #define RXD_W0_UNICAST_TO_ME            FIELD32(0x00000004)
 888 #define RXD_W0_MULTICAST                FIELD32(0x00000008)
 889 #define RXD_W0_BROADCAST                FIELD32(0x00000010)
 890 #define RXD_W0_MY_BSS                   FIELD32(0x00000020)
 891 #define RXD_W0_CRC                      FIELD32(0x00000040)
 892 #define RXD_W0_OFDM                     FIELD32(0x00000080)
 893 #define RXD_W0_CIPHER_ERROR             FIELD32(0x00000300)
 894 #define RXD_W0_KEY_INDEX                FIELD32(0x0000fc00)
 895 #define RXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
 896 #define RXD_W0_CIPHER_ALG               FIELD32(0xe0000000)
 897
 898 /*
 899  * WORD1
 900  * SIGNAL: RX raw data rate reported by BBP.
 901  * RSSI: RSSI reported by BBP.
 902  */
 903 #define RXD_W1_SIGNAL                   FIELD32(0x000000ff)
 904 #define RXD_W1_RSSI_AGC                 FIELD32(0x00001f00)
 905 #define RXD_W1_RSSI_LNA                 FIELD32(0x00006000)
 906 #define RXD_W1_FRAME_OFFSET             FIELD32(0x7f000000)
 907
 908 /*
 909  * Word2
 910  * IV: Received IV of originally encrypted.
 911  */
 912 #define RXD_W2_IV                       FIELD32(0xffffffff)
 913
 914 /*
 915  * Word3
 916  * EIV: Received EIV of originally encrypted.
 917  */
 918 #define RXD_W3_EIV                      FIELD32(0xffffffff)
 919
 920 /*
 921  * Word4
 922  */
 923 #define RXD_W4_RESERVED                 FIELD32(0xffffffff)
 924
 925 /*
 926  * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
 927  * and passed to the HOST driver.
 928  * The following fields are for DMA block and HOST usage only.
 929  * Can't be touched by ASIC MAC block.
 930  */
 931
 932 /*
 933  * Word5
 934  */
 935 #define RXD_W5_RESERVED                 FIELD32(0xffffffff)
 936
 937 /*
 938  * Macro's for converting txpower from EEPROM to dscape value
 939  * and from dscape value to register value.
 940  */
 941 #define MIN_TXPOWER     0
 942 #define MAX_TXPOWER     31
 943 #define DEFAULT_TXPOWER 24
 944
 945 #define TXPOWER_FROM_DEV(__txpower)             \
 946 ({                                              \
 947         ((__txpower) > MAX_TXPOWER) ?           \
 948                 DEFAULT_TXPOWER : (__txpower);  \
 949 })
 950
 951 #define TXPOWER_TO_DEV(__txpower)                       \
 952 ({                                                      \
 953         ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER :    \
 954         (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER :   \
 955         (__txpower));                                   \
 956 })
 957
 958 #endif /* RT73USB_H */