package/uboot-lantiq/files/drivers/net/ifx_etop.c

   1 /*
   2  * Lantiq CPE device ethernet driver.
   3  * Supposed to work on Twinpass/Danube.
   4  *
   5  * Based on INCA-IP driver:
   6  * (C) Copyright 2003-2004
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * (C) Copyright 2010
  10  * Thomas Langer, Ralph Hempel
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 #include <common.h>
  32
  33 #include <malloc.h>
  34 #include <net.h>
  35 #include <miiphy.h>
  36 #include <asm/types.h>
  37 #include <asm/io.h>
  38 #include <asm/addrspace.h>
  39 #include <config.h>
  40
  41 #include "ifx_etop.h"
  42
  43 #if defined(CONFIG_AR9)
  44 #define TX_CHAN_NO   1
  45 #define RX_CHAN_NO   0
  46 #else
  47 #define TX_CHAN_NO   7
  48 #define RX_CHAN_NO   6
  49 #endif
  50
  51 #define NUM_RX_DESC     PKTBUFSRX
  52 #define NUM_TX_DESC     8
  53 #define TOUT_LOOP       100
  54
  55 typedef struct
  56 {
  57         union
  58         {
  59                 struct
  60                 {
  61                         volatile u32 OWN        :1;
  62                         volatile u32 C          :1;
  63                         volatile u32 Sop        :1;
  64                         volatile u32 Eop        :1;
  65                         volatile u32 reserved   :3;
  66                         volatile u32 Byteoffset :2;
  67                         volatile u32 reserve    :7;
  68                         volatile u32 DataLen    :16;
  69                 }field;
  70
  71                 volatile u32 word;
  72         }status;
  73
  74         volatile u32 DataPtr;
  75 } dma_rx_descriptor_t;
  76
  77 typedef struct
  78 {
  79         union
  80         {
  81                 struct
  82                 {
  83                         volatile u32 OWN        :1;
  84                         volatile u32 C          :1;
  85                         volatile u32 Sop        :1;
  86                         volatile u32 Eop        :1;
  87                         volatile u32 Byteoffset :5;
  88                         volatile u32 reserved   :7;
  89                         volatile u32 DataLen    :16;
  90                 }field;
  91
  92                 volatile u32 word;
  93         }status;
  94
  95         volatile u32 DataPtr;
  96 } dma_tx_descriptor_t;
  97
  98 static volatile dma_rx_descriptor_t rx_des_ring[NUM_RX_DESC] __attribute__ ((aligned(8)));
  99 static volatile dma_tx_descriptor_t tx_des_ring[NUM_TX_DESC] __attribute__ ((aligned(8)));
 100 static int tx_num, rx_num;
 101
 102 static volatile IfxDMA_t *pDma = (IfxDMA_t *)CKSEG1ADDR(DANUBE_DMA_BASE);
 103
 104 static int lq_eth_init(struct eth_device *dev, bd_t * bis);
 105 static int lq_eth_send(struct eth_device *dev, volatile void *packet,int length);
 106 static int lq_eth_recv(struct eth_device *dev);
 107 static void lq_eth_halt(struct eth_device *dev);
 108 static void lq_eth_init_chip(void);
 109 static void lq_eth_init_dma(void);
 110
 111 static int lq_eth_miiphy_read(char *devname, u8 phyAddr, u8 regAddr, u16 * retVal)
 112 {
 113         u32 timeout = 50000;
 114         u32 phy, reg;
 115
 116         if ((phyAddr > 0x1F) || (regAddr > 0x1F) || (retVal == NULL))
 117                 return -1;
 118
 119         phy = (phyAddr & 0x1F) << 21;
 120         reg = (regAddr & 0x1F) << 16;
 121
 122         *ETOP_MDIO_ACC = 0xC0000000 | phy | reg;
 123         while ((timeout--) && (*ETOP_MDIO_ACC & 0x80000000))
 124                 udelay(10);
 125
 126         if (timeout==0) {
 127                 *retVal = 0;
 128                 return -1;
 129         }
 130         *retVal = *ETOP_MDIO_ACC & 0xFFFF;
 131         return 0;
 132 }
 133
 134 static int lq_eth_miiphy_write(char *devname, u8 phyAddr, u8 regAddr, u16 data)
 135 {
 136         u32 timeout = 50000;
 137         u32 phy, reg;
 138
 139         if ((phyAddr > 0x1F) || (regAddr > 0x1F))
 140                 return -1;
 141
 142         phy = (phyAddr & 0x1F) << 21;
 143         reg = (regAddr & 0x1F) << 16;
 144
 145         *ETOP_MDIO_ACC = 0x80000000 | phy | reg | data;
 146         while ((timeout--) && (*ETOP_MDIO_ACC & 0x80000000))
 147                 udelay(10);
 148
 149         if (timeout==0)
 150                 return -1;
 151         return 0;
 152 }
 153
 154
 155 int lq_eth_initialize(bd_t * bis)
 156 {
 157         struct eth_device *dev;
 158
 159         debug("Entered lq_eth_initialize()\n");
 160
 161         if (!(dev = malloc (sizeof *dev))) {
 162                 printf("Failed to allocate memory\n");
 163                 return -1;
 164         }
 165         memset(dev, 0, sizeof(*dev));
 166
 167         sprintf(dev->name, "lq_cpe_eth");
 168         dev->init = lq_eth_init;
 169         dev->halt = lq_eth_halt;
 170         dev->send = lq_eth_send;
 171         dev->recv = lq_eth_recv;
 172
 173         eth_register(dev);
 174
 175 #if defined (CONFIG_MII) || defined(CONFIG_CMD_MII)
 176         /* register mii command access routines */
 177         miiphy_register(dev->name,
 178                         lq_eth_miiphy_read, lq_eth_miiphy_write);
 179 #endif
 180
 181         lq_eth_init_dma();
 182         lq_eth_init_chip();
 183
 184         return 0;
 185 }
 186
 187 static int lq_eth_init(struct eth_device *dev, bd_t * bis)
 188 {
 189         int i;
 190         uchar *enetaddr = dev->enetaddr;
 191
 192         debug("lq_eth_init %x:%x:%x:%x:%x:%x\n",
 193                 enetaddr[0], enetaddr[1], enetaddr[2], enetaddr[3], enetaddr[4], enetaddr[5]);
 194
 195         *ENET_MAC_DA0 = (enetaddr[0]<<24) + (enetaddr[1]<<16) + (enetaddr[2]<< 8) + enetaddr[3];
 196         *ENET_MAC_DA1 = (enetaddr[4]<<24) + (enetaddr[5]<<16);
 197         *ENETS_CFG |= 1<<28;    /* enable filter for unicast packets */
 198
 199         tx_num=0;
 200         rx_num=0;
 201
 202         for(i=0;i < NUM_RX_DESC; i++) {
 203                 dma_rx_descriptor_t * rx_desc = (dma_rx_descriptor_t *)CKSEG1ADDR(&rx_des_ring[i]);
 204                 rx_desc->status.word=0;
 205                 rx_desc->status.field.OWN=1;
 206                 rx_desc->status.field.DataLen=PKTSIZE_ALIGN;   /* 1536  */
 207                 rx_desc->DataPtr=(u32)CKSEG1ADDR(NetRxPackets[i]);
 208                 NetRxPackets[i][0] = 0xAA;
 209         }
 210
 211         /* Reset DMA */
 212         dma_writel(dma_cs, RX_CHAN_NO);
 213         dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/
 214         dma_writel(dma_cpoll, 0x80000040);
 215         /*set descriptor base*/
 216         dma_writel(dma_cdba, (u32)rx_des_ring);
 217         dma_writel(dma_cdlen, NUM_RX_DESC);
 218         dma_writel(dma_cie, 0);
 219         dma_writel(dma_cctrl, 0x30000);
 220
 221         for(i=0;i < NUM_TX_DESC; i++) {
 222                 dma_tx_descriptor_t * tx_desc = (dma_tx_descriptor_t *)CKSEG1ADDR(&tx_des_ring[i]);
 223                 memset(tx_desc, 0, sizeof(tx_des_ring[0]));
 224         }
 225
 226         dma_writel(dma_cs, TX_CHAN_NO);
 227         dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/
 228         dma_writel(dma_cpoll, 0x80000040);
 229         dma_writel(dma_cdba, (u32)tx_des_ring);
 230         dma_writel(dma_cdlen, NUM_TX_DESC);
 231         dma_writel(dma_cie, 0);
 232         dma_writel(dma_cctrl, 0x30100);
 233
 234         /* turn on DMA rx & tx channel
 235         */
 236         dma_writel(dma_cs, RX_CHAN_NO);
 237         dma_writel(dma_cctrl, dma_readl(dma_cctrl) | 1); /*reset and turn on the channel*/
 238
 239         return 0;
 240 }
 241
 242 static void lq_eth_halt(struct eth_device *dev)
 243 {
 244         int i;
 245
 246         debug("lq_eth_halt()\n");
 247
 248         for(i=0;i<8;i++) {
 249                 dma_writel(dma_cs, i);
 250                 dma_writel(dma_cctrl, dma_readl(dma_cctrl) & ~1);/*stop the dma channel*/
 251         }
 252 }
 253
 254 #ifdef DEBUG
 255 static void lq_dump(const u8 *data, const u32 length)
 256 {
 257         u32 i;
 258         debug("\n");
 259         for(i=0;i<length;i++) {
 260                 debug("%02x ", data[i]);
 261         }
 262         debug("\n");
 263 }
 264 #endif
 265
 266 static int lq_eth_send(struct eth_device *dev, volatile void *packet, int length)
 267 {
 268         int i;
 269         int res = -1;
 270         volatile dma_tx_descriptor_t * tx_desc = (dma_tx_descriptor_t *)CKSEG1ADDR(&tx_des_ring[tx_num]);
 271
 272         if (length <= 0) {
 273                 printf ("%s: bad packet size: %d\n", dev->name, length);
 274                 goto Done;
 275         }
 276
 277         for(i=0; tx_desc->status.field.OWN==1; i++) {
 278                 if (i>=TOUT_LOOP) {
 279                         printf("NO Tx Descriptor...");
 280                         goto Done;
 281                 }
 282         }
 283
 284         tx_desc->status.field.Sop=1;
 285         tx_desc->status.field.Eop=1;
 286         tx_desc->status.field.C=0;
 287         tx_desc->DataPtr = (u32)CKSEG1ADDR(packet);
 288         if (length<60)
 289                 tx_desc->status.field.DataLen = 60;
 290         else
 291                 tx_desc->status.field.DataLen = (u32)length;
 292
 293         flush_cache((u32)packet, tx_desc->status.field.DataLen);
 294         asm("SYNC");
 295         tx_desc->status.field.OWN=1;
 296
 297         res=length;
 298         tx_num++;
 299         if (tx_num==NUM_TX_DESC) tx_num=0;
 300
 301 #ifdef DEBUG
 302         lq_dump(tx_desc->DataPtr, tx_desc->status.field.DataLen);
 303 #endif
 304
 305         dma_writel(dma_cs, TX_CHAN_NO);
 306         if (!(dma_readl(dma_cctrl) & 1)) {
 307                 dma_writel(dma_cctrl, dma_readl(dma_cctrl) | 1);
 308         }
 309
 310 Done:
 311         return res;
 312 }
 313
 314 static int lq_eth_recv(struct eth_device *dev)
 315 {
 316         int length  = 0;
 317         volatile dma_rx_descriptor_t * rx_desc;
 318
 319         rx_desc = (dma_rx_descriptor_t *)CKSEG1ADDR(&rx_des_ring[rx_num]);
 320
 321         if ((rx_desc->status.field.C == 0) || (rx_desc->status.field.OWN == 1)) {
 322                 return 0;
 323         }
 324         debug("rx");
 325 #ifdef DEBUG
 326         lq_dump(rx_desc->DataPtr, rx_desc->status.field.DataLen);
 327 #endif
 328         length = rx_desc->status.field.DataLen;
 329         if (length > 4) {
 330                 invalidate_dcache_range((u32)CKSEG0ADDR(rx_desc->DataPtr), (u32) CKSEG0ADDR(rx_desc->DataPtr) + length);
 331                 NetReceive(NetRxPackets[rx_num], length);
 332         } else {
 333                 printf("ERROR: Invalid rx packet length.\n");
 334         }
 335
 336         rx_desc->status.field.Sop=0;
 337         rx_desc->status.field.Eop=0;
 338         rx_desc->status.field.C=0;
 339         rx_desc->status.field.DataLen=PKTSIZE_ALIGN;
 340         rx_desc->status.field.OWN=1;
 341
 342         rx_num++;
 343         if (rx_num == NUM_RX_DESC)
 344                 rx_num=0;
 345
 346         return length;
 347 }
 348
 349 static void lq_eth_init_chip(void)
 350 {
 351         *ETOP_MDIO_CFG &= ~0x6;
 352         *ENET_MAC_CFG = 0x187;
 353
 354         // turn on port0, set to rmii and turn off port1.
 355 #ifdef CONFIG_RMII
 356         *ETOP_CFG = (*ETOP_CFG & 0xFFFFFFFC) | 0x0000000A;
 357 #else
 358         *ETOP_CFG = (*ETOP_CFG & 0xFFFFFFFC) | 0x00000008;
 359 #endif
 360
 361         *ETOP_IG_PLEN_CTRL = 0x004005EE; // set packetlen.
 362         *ENET_MAC_CFG |= 1<<11; /*enable the crc*/
 363         return;
 364 }
 365
 366 static void lq_eth_init_dma(void)
 367 {
 368         /* Reset DMA */
 369         dma_writel(dma_ctrl, dma_readl(dma_ctrl) | 1);
 370         dma_writel(dma_irnen, 0);/*disable all the interrupts first*/
 371
 372         /* Clear Interrupt Status Register */
 373         dma_writel(dma_irncr, 0xfffff);
 374         /*disable all the dma interrupts*/
 375         dma_writel(dma_irnen, 0);
 376         /*disable channel 0 and channel 1 interrupts*/
 377
 378         dma_writel(dma_cs, RX_CHAN_NO);
 379         dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/
 380         dma_writel(dma_cpoll, 0x80000040);
 381         /*set descriptor base*/
 382         dma_writel(dma_cdba, (u32)rx_des_ring);
 383         dma_writel(dma_cdlen, NUM_RX_DESC);
 384         dma_writel(dma_cie, 0);
 385         dma_writel(dma_cctrl, 0x30000);
 386
 387         dma_writel(dma_cs, TX_CHAN_NO);
 388         dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/
 389         dma_writel(dma_cpoll, 0x80000040);
 390         dma_writel(dma_cdba, (u32)tx_des_ring);
 391         dma_writel(dma_cdlen, NUM_TX_DESC);
 392         dma_writel(dma_cie, 0);
 393         dma_writel(dma_cctrl, 0x30100);
 394         /*enable the poll function and set the poll counter*/
 395         //dma_writel(DMA_CPOLL=DANUBE_DMA_POLL_EN | (DANUBE_DMA_POLL_COUNT<<4);
 396         /*set port properties, enable endian conversion for switch*/
 397         dma_writel(dma_ps, 0);
 398         dma_writel(dma_pctrl, dma_readl(dma_pctrl) | (0xf<<8));/*enable 32 bit endian conversion*/
 399
 400         return;
 401 }