target/linux/pxa/patches/001-pm.patch

   1 diff -NurbwB linux-2.6.17/arch/arm/mach-pxa/pm.c linux-2.6.17-patched/arch/arm/mach-pxa/pm.c
   2 --- linux-2.6.17/arch/arm/mach-pxa/pm.c 2006-06-17 18:49:35.000000000 -0700
   3 +++ linux-2.6.17-patched/arch/arm/mach-pxa/pm.c 2006-09-11 10:58:41.000000000 -0700
   4 @@ -10,35 +10,50 @@
   5   * This program is free software; you can redistribute it and/or
   6   * modify it under the terms of the GNU General Public License.
   7   */
   8 +
   9  #include <linux/config.h>
  10  #include <linux/init.h>
  11 -#include <linux/module.h>
  12 -#include <linux/suspend.h>
  13 +#include <linux/pm.h>
  14 +#include <linux/slab.h>
  15 +#include <linux/sched.h>
  16 +#include <linux/interrupt.h>
  17 +#include <linux/sysctl.h>
  18  #include <linux/errno.h>
  19 -#include <linux/time.h>
  20
  21  #include <asm/hardware.h>
  22  #include <asm/memory.h>
  23  #include <asm/system.h>
  24 -#include <asm/arch/pm.h>
  25 +#include <asm/leds.h>
  26 +#include <asm/uaccess.h>
  27  #include <asm/arch/pxa-regs.h>
  28  #include <asm/arch/lubbock.h>
  29  #include <asm/mach/time.h>
  30
  31 +/**/
  32 +#include <linux/module.h>
  33 +/**/
  34 +//kirti
  35 +#include <linux/delay.h>
  36 +//kirti~
  37
  38  /*
  39   * Debug macros
  40   */
  41 -#undef DEBUG
  42 +#define DEBUG
  43 +
  44 +extern void pxa_cpu_suspend(void);
  45 +extern void pxa_cpu_resume(void);
  46 +
  47 +int pm_pwronoff;
  48 +/*Angelia Additions */
  49 +int pm_pedr=0;
  50 +EXPORT_SYMBOL(pm_pwronoff);
  51 +EXPORT_SYMBOL(pm_pedr);
  52 +
  53
  54  #define SAVE(x)                sleep_save[SLEEP_SAVE_##x] = x
  55  #define RESTORE(x)     x = sleep_save[SLEEP_SAVE_##x]
  56
  57 -#define RESTORE_GPLEVEL(n) do { \
  58 -       GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
  59 -       GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
  60 -} while (0)
  61 -
  62  /*
  63   * List of global PXA peripheral registers to preserve.
  64   * More ones like CP and general purpose register values are preserved
  65 @@ -46,97 +61,405 @@
  66   */
  67  enum { SLEEP_SAVE_START = 0,
  68
  69 -       SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3,
  70 -       SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3,
  71 -       SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3,
  72 -       SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3,
  73 -       SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
  74 -
  75 -       SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
  76 -       SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
  77 -       SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
  78 -       SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U,
  79 +       SLEEP_SAVE_OSCR, SLEEP_SAVE_OIER,
  80 +       SLEEP_SAVE_OSMR0, SLEEP_SAVE_OSMR1, SLEEP_SAVE_OSMR2, SLEEP_SAVE_OSMR3,
  81
  82 -       SLEEP_SAVE_PSTR,
  83 +       SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2,
  84 +       SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2,
  85 +       SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2,
  86 +       SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR2_L,
  87 +       SLEEP_SAVE_GAFR0_U, SLEEP_SAVE_GAFR1_U, SLEEP_SAVE_GAFR2_U,
  88 +
  89 +       SLEEP_SAVE_FFIER, SLEEP_SAVE_FFLCR, SLEEP_SAVE_FFMCR,
  90 +       SLEEP_SAVE_FFSPR, SLEEP_SAVE_FFISR,
  91 +       SLEEP_SAVE_FFDLL, SLEEP_SAVE_FFDLH,SLEEP_SAVE_FFFCR,
  92 +
  93 +       SLEEP_SAVE_STIER, SLEEP_SAVE_STLCR, SLEEP_SAVE_STMCR,
  94 +       SLEEP_SAVE_STSPR, SLEEP_SAVE_STISR,
  95 +       SLEEP_SAVE_STDLL, SLEEP_SAVE_STDLH,
  96 +
  97 +       SLEEP_SAVE_BTIER, SLEEP_SAVE_BTLCR, SLEEP_SAVE_BTMCR,
  98 +       SLEEP_SAVE_BTSPR, SLEEP_SAVE_BTISR,
  99 +       SLEEP_SAVE_BTDLL, SLEEP_SAVE_BTDLH,
 100
 101         SLEEP_SAVE_ICMR,
 102         SLEEP_SAVE_CKEN,
 103
 104 -#ifdef CONFIG_PXA27x
 105 -       SLEEP_SAVE_MDREFR,
 106 -       SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
 107 -       SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
 108 -#endif
 109 +       SLEEP_SAVE_LCCR0, SLEEP_SAVE_LCCR1, SLEEP_SAVE_LCCR2,SLEEP_SAVE_LCCR3,
 110 +       SLEEP_SAVE_TMEDCR, SLEEP_SAVE_FDADR0, SLEEP_SAVE_FSADR0,SLEEP_SAVE_FIDR0,SLEEP_SAVE_FDADR1,
 111 +       SLEEP_SAVE_LDCMD0,
 112 +
 113 +       SLEEP_SAVE_NSSCR0,SLEEP_SAVE_NSSCR1,SLEEP_SAVE_NSSSR,SLEEP_SAVE_NSSITR,SLEEP_SAVE_NSSDR,
 114 +       SLEEP_SAVE_NSSTO,SLEEP_SAVE_NSSPSP,
 115
 116 -       SLEEP_SAVE_CKSUM,
 117
 118 +       SLEEP_SAVE_CKSUM,
 119         SLEEP_SAVE_SIZE
 120  };
 121
 122 +/**/
 123 +#define UART_DTR       1
 124 +#define UART_RTS       2
 125 +
 126 +/**/
 127
 128 -int pxa_pm_enter(suspend_state_t state)
 129 +int pm_do_suspend(void)
 130  {
 131         unsigned long sleep_save[SLEEP_SAVE_SIZE];
 132         unsigned long checksum = 0;
 133 -       struct timespec delta, rtc;
 134         int i;
 135 +       int valbefore,valafter,valafter1;
 136 +       int gpsr0,gpsr1,gpsr2;
 137         extern void pxa_cpu_pm_enter(suspend_state_t state);
 138
 139 -#ifdef CONFIG_IWMMXT
 140 -       /* force any iWMMXt context to ram **/
 141 -       iwmmxt_task_disable(NULL);
 142 -#endif
 143 +       // YoKu 16Feb06 GPIO Changed ----->
 144 +
 145 +       PGSR2 |= GPIO_bit(78);
 146 +/*     if(GPLR2 & GPIO_bit(78))                // LCD Reset Pin
 147 +               PGSR2 |= GPIO_bit(78);
 148 +       else
 149 +               PGSR2 &= ~GPIO_bit(78);         */
 150 +       GPDR0 &= ~GPIO_bit(0);
 151 +       GPDR0 &= ~GPIO_bit(1);
 152 +       GPDR0 &= ~GPIO_bit(3); //Tushar: 20 apr GPIO3 configured as input
 153 +       GPDR0 &= ~GPIO_bit(2);
 154 +//     GPDR0 &= ~GPIO_bit(5);
 155 +//     GPDR0 &= ~GPIO_bit(6);
 156 +//     GPDR0 &= ~GPIO_bit(7);
 157 +//     GPDR0 &= ~GPIO_bit(8);
 158 +
 159 +
 160 +// KeyCol pin Status in sleep mode
 161 +       PGSR0 &= ~GPIO_bit(9);         //19
 162 +        PGSR0 &= ~GPIO_bit(10);        //20
 163 +        PGSR0 &= ~GPIO_bit(11);        //21
 164 +        PGSR0 &= ~GPIO_bit(12);        //22
 165 +        PGSR0 &= ~GPIO_bit(13);        //23
 166 +        PGSR0 &= ~GPIO_bit(14);        //24
 167 +
 168 +       printk("KER_PM: Setting up wakeup sources 26May06\n");
 169 +
 170 +       // KeyPad
 171 +       //printk("KER_PM: Uncommented key pad wakeup sources\n");
 172 +       PWER |= GPIO_bit(5);            //11
 173 +       PWER |= GPIO_bit(6);            //12
 174 +       PWER |= GPIO_bit(7);            //13
 175 +       PWER |= GPIO_bit(8);            //14
 176 +       PFER |= GPIO_bit(5);            //11
 177 +       PFER |= GPIO_bit(6);            //12
 178 +       PFER |= GPIO_bit(7);            //13
 179 +       PFER |= GPIO_bit(8);            //14
 180 +       PRER |= GPIO_bit(5);            //11
 181 +       PRER |= GPIO_bit(6);            //12
 182 +       PRER |= GPIO_bit(7);            //13
 183 +       PRER |= GPIO_bit(8);            //14
 184 +
 185 +       // USB
 186 +       PWER |= GPIO_bit(3);            //6
 187 +       PFER |= GPIO_bit(3);            //6
 188 +       PRER |= GPIO_bit(3);            //6
 189 +
 190 +       // PMU
 191 +       PWER |= GPIO_bit(2);            //4
 192 +       PFER |= GPIO_bit(2);            //4
 193 +       PRER |= GPIO_bit(2);            //4
 194 +
 195 +       // Anup : GSM RI
 196 +        PWER |= GPIO_bit(0);           //0
 197 +        PFER |= GPIO_bit(0);           //0
 198 +        PRER |= GPIO_bit(0);           //0
 199 +       // anup prashant : for gsm reset problem 19 may 2006
 200 +       //GPDR0 |= GPIO_bit(18);        YoKu Commented this line, GPIO18 should be i/p pin to avoid GSM Reset pulse
 201 +       PGSR0 |= GPIO_bit(18);          // GSM reset pin
 202 +       PGSR0 |= GPIO_bit(0);           //
 203 +       PGSR1 |= GPIO_bit(38);          // commneted .18 apr
 204 +       //  <----- YoKu
 205 +
 206 +       // YoKu ----->
 207 +       // When exiting from sleep mode, 10us Low pulse comes on GSM Reset and Pwr pin
 208 +       // to avoid this configure GPIO 18,80 as input pins before going to sleep mode
 209 +        GPDR0 &= ~GPIO_bit(18);
 210 +        //GPDR2 &= ~GPIO_bit(80);
 211 +        // <----- YoKu
 212 +
 213 +       //kirti for RTC
 214 +        PWER |= PWER_RTC;
 215 +       //kirti cli();
 216 +       local_irq_disable();
 217 +       //kirti clf();
 218 +       local_fiq_disable();
 219 +       leds_event(led_stop);
 220 +
 221 +       /* Put Current time into RCNR */
 222 +       RCNR = xtime.tv_sec;
 223
 224 -       /* preserve current time */
 225 -       rtc.tv_sec = RCNR;
 226 -       rtc.tv_nsec = 0;
 227 -       save_time_delta(&delta, &rtc);
 228 +       printk("11May2006 KERR: pgsr0=0x%08x pgsr1=0x%08x pgsr2= 0x%08x\n",PGSR0,PGSR1,PGSR2);
 229 +       printk("KER_PM_DELAY: SSCR Going to Sleep at RCNR =%d\n\n\n\n\n\n",RCNR);
 230 +
 231 +       /*
 232 +        * Temporary solution.  This won't be necessary once
 233 +        * we move pxa support into the serial driver
 234 +        * Save the FF UART
 235 +        */
 236 +
 237 +       // Anup : commented for power saving mode problem
 238 +       printk("\nPM: Why doesnt it prnt?? 26May06\n");
 239 +       printk("\nPM : GSM Sleep Mode enabled");
 240 +
 241 +
 242 +       FFMCR &= ~UART_RTS;
 243 +       udelay(2000);
 244 +       udelay(2000);
 245 +       FFMCR &= ~UART_DTR ;
 246 +       udelay(2000);
 247 +
 248 +       udelay(2000);
 249 +       // rupali
 250 +       // Anup : Do not check here
 251 +/*     if(!pm_pwronoff)
 252 +       {
 253 +               printk("\nPM : Modem Control Register = %x " , FFMCR);
 254 +               while( FFMSR & 0x00000020)
 255 +               {
 256 +                       printk("\nPM : FFFSR = %x " , FFMSR);
 257 +               }
 258 +       }               */
 259 +       udelay(2000);
 260 +
 261 +//Tushar: 19 apr
 262 +//     NSSCR0 &= 0xFFFFFF7F;
 263 +//     printk("\nPM: NSSCR0 = %x" ,NSSCR0 );
 264 +
 265 +       SAVE(FFIER);
 266 +       SAVE(FFLCR);
 267 +       SAVE(FFMCR);
 268 +       SAVE(FFSPR);
 269 +       SAVE(FFISR);
 270 +       FFLCR |= 0x80;
 271 +       SAVE(FFDLL);
 272 +       SAVE(FFDLH);
 273 +       SAVE(FFFCR);
 274 +       FFLCR &= 0xef;
 275 +
 276 +       SAVE(STIER);
 277 +       SAVE(STLCR);
 278 +       SAVE(STMCR);
 279 +       SAVE(STSPR);
 280 +       SAVE(STISR);
 281 +       STLCR |= 0x80;
 282 +       SAVE(STDLL);
 283 +       SAVE(STDLH);
 284 +       STLCR &= 0xef;
 285 +
 286 +       SAVE(BTIER);
 287 +       SAVE(BTLCR);
 288 +       SAVE(BTMCR);
 289 +       SAVE(BTSPR);
 290 +       SAVE(BTISR);
 291 +       BTLCR |= 0x80;
 292 +       SAVE(BTDLL);
 293 +       SAVE(BTDLH);
 294 +       BTLCR &= 0xef;
 295 +
 296 +       /* save vital registers */
 297 +       SAVE(OSCR);
 298 +       SAVE(OSMR0);
 299 +       SAVE(OSMR1);
 300 +       SAVE(OSMR2);
 301 +       SAVE(OSMR3);
 302 +       SAVE(OIER);
 303
 304 -       SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2);
 305         SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2);
 306         SAVE(GRER0); SAVE(GRER1); SAVE(GRER2);
 307         SAVE(GFER0); SAVE(GFER1); SAVE(GFER2);
 308 -       SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
 309 -
 310         SAVE(GAFR0_L); SAVE(GAFR0_U);
 311         SAVE(GAFR1_L); SAVE(GAFR1_U);
 312         SAVE(GAFR2_L); SAVE(GAFR2_U);
 313
 314 -#ifdef CONFIG_PXA27x
 315 -       SAVE(MDREFR);
 316 -       SAVE(GPLR3); SAVE(GPDR3); SAVE(GRER3); SAVE(GFER3); SAVE(PGSR3);
 317 -       SAVE(GAFR3_L); SAVE(GAFR3_U);
 318 -       SAVE(PWER); SAVE(PCFR); SAVE(PRER);
 319 -       SAVE(PFER); SAVE(PKWR);
 320 -#endif
 321 +       // YoKu 23Feb06 Added To save LCD Registers, updated by kirti 24Feb06 ----->
 322 +       SAVE(LCCR0); SAVE(LCCR1); SAVE(LCCR2); SAVE(LCCR3);
 323 +       SAVE(FDADR0);
 324 +       SAVE(FDADR1);
 325 +       LCSR = 0xffffffff;      /* Clear LCD Status Register */
 326 +
 327 +//     LCCR0 &= ~LCCR0_LDM;    /* Enable LCD Disable Done Interrupt */
 328 +//     LCCR0 |= LCCR0_DIS;     /* Disable LCD Controller */
 329 +
 330 +       SAVE(LDCMD0);
 331 +       // <----- YoKu
 332 +
 333 +//     LCCR0 &= ~LCCR0_LDM;    /* Enable LCD Disable Done Interrupt */
 334 +//      LCCR0 |= LCCR0_DIS;     /* Disable LCD Controller */
 335 +
 336
 337         SAVE(ICMR);
 338         ICMR = 0;
 339
 340         SAVE(CKEN);
 341 -       SAVE(PSTR);
 342 +       CKEN = 0;
 343 +
 344 +       // Anup : For Wifi power saving mode 2 May 2006
 345 +        SAVE(NSSCR0);SAVE(NSSCR1);SAVE(NSSSR);SAVE(NSSITR);SAVE(NSSDR);SAVE(NSSTO);
 346 +        SAVE(NSSPSP);
 347 +        printk("\nMY favourite mode in life.......sleep.....\n");
 348 +
 349
 350         /* Note: wake up source are set up in each machine specific files */
 351
 352 +       /*Changes to keep the right sim selected */
 353 +       gpsr0 = GPLR0;
 354 +       gpsr1 = GPLR1;
 355 +       gpsr2 = GPLR2;
 356 +
 357 +       /*Sim 1 selected */
 358 +       // YoKu GPIOs Changed ----->
 359 +       if( (GPLR0 & GPIO_bit(21)) && !(GPLR0 & GPIO_bit(22)) ) // 62,63
 360 +       {
 361 +               PGSR0 |= GPIO_bit(21) ;         //62
 362 +               PGSR0 &= ~GPIO_bit(22) ;        //63
 363 +       }
 364 +       else if (!(GPLR0 & GPIO_bit(21)) && (GPLR0 & GPIO_bit(22)) ) // 62,63
 365 +       {
 366 +               PGSR0 |= GPIO_bit(22) ;         //63
 367 +               PGSR0 &= ~GPIO_bit(21) ;        //62
 368 +       } /* sim 2*/
 369 +       // <----- YoKu
 370 +
 371         /* clear GPIO transition detect  bits */
 372         GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
 373 -#ifdef CONFIG_PXA27x
 374 -       GEDR3 = GEDR3;
 375 -#endif
 376
 377         /* Clear sleep reset status */
 378         RCSR = RCSR_SMR;
 379
 380 +       /* set resume return address */
 381 +       PSPR = virt_to_phys(pxa_cpu_resume);
 382 +
 383         /* before sleeping, calculate and save a checksum */
 384         for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
 385                 checksum += sleep_save[i];
 386         sleep_save[SLEEP_SAVE_CKSUM] = checksum;
 387
 388 -       /* *** go zzz *** */
 389 -       pxa_cpu_pm_enter(state);
 390 +        PGSR0 |= GPIO_bit(15);   //sidd for wake from Sleep 15, YoKu Comented ?? GPIO15 was ChipSelect
 391 +       PGSR2 |= GPIO_bit(80);   //sidd for GSM Engine 69, YoKu GPIO Changed    Anup :commented
 392 +
 393 +       PGSR1 &= ~GPIO_bit(33); //Tushar: BT Codec Power Down
 394 +
 395 +       PGSR0 &= ~GPIO_bit(23); //Tushar: BGW200 Regulator OFF
 396 +
 397 +//     GPDR1 |= GPIO_bit(49); //Tushar: LCD Serial Data in changed to O/P
 398 +
 399 +//     PGSR1 &= ~GPIO_bit(48);//Tushar: LCD Serial Pins
 400 +
 401 +//     PGSR1 &= ~GPIO_bit(49);
 402 +
 403 +//     PGSR1 &= ~GPIO_bit(50);
 404 +
 405 +//     PGSR1 |= GPIO_bit(51);
 406 +
 407 +//     PGSR1 &= 0x03FFFFFF;//Tushar: 24apr LCD datalines
 408 +//     PGSR2 &= 0xFFFFFC00;
 409 +
 410 +       PGSR0 &= ~GPIO_bit(24); //Tushar: Mux Control Signals
 411 +
 412 +       PGSR0 &= ~GPIO_bit(25);
 413 +
 414 +       PGSR0 &= ~GPIO_bit(26);
 415 +
 416 +       PGSR0 &= ~GPIO_bit(27);
 417 +
 418 + //       GPDR0 |= GPIO_bit(17); //Tushar: unused GPIOs 19apr
 419 +   //     GPCR0 |= GPIO_bit(17);
 420 +        PGSR0 &= ~GPIO_bit(17);
 421 +
 422 +//     GPDR1 |= GPIO_bit(56); //Tushar: unused GPIOs 19apr
 423 +  //      GPCR1 |= GPIO_bit(56);
 424 +        PGSR1 &= ~GPIO_bit(56);
 425 +
 426 +//     GPDR2 |= GPIO_bit(79);//Tushar: unused GPIOs 19apr
 427 +//     GPCR2 |= GPIO_bit(79);
 428 +       PGSR2 &= ~GPIO_bit(79);
 429 +
 430 +//     GPDR1 |= 0x03F00000;//Tushar: unused GPIOs 19apr
 431 +//     GPCR1 |= 0x03F00000;
 432 +       PGSR1 &= 0xFC0FFFFF;
 433 +
 434 +
 435 +       GPDR0 |= GPIO_bit(19);//Tushar: SIM Present Inputs configured as outputs
 436 +       GPDR0 |= GPIO_bit(20);
 437 +       PGSR0 &= ~GPIO_bit(19);
 438 +       PGSR0 &= ~GPIO_bit(20);
 439 +
 440 +
 441 +//Tushar: 25apr FFRTS FFDTR & FFTXD
 442 +
 443 +       PGSR1 |= GPIO_bit(39);
 444 +       PGSR1 |= GPIO_bit(40);
 445 +       PGSR1 |= GPIO_bit(41);
 446 +/*
 447 +       PGSR2 &= GPIO_bit(81); //Tushar: 24apr NSSP pins
 448 +       PGSR2 &= GPIO_bit(82);
 449 +       PGSR2 &= GPIO_bit(83);
 450 +
 451 +       PGSR2 |= GPIO_bit(74);
 452 +       PGSR2 |= GPIO_bit(75);
 453 +       PGSR2 |= GPIO_bit(76);
 454 +       PGSR2 |= GPIO_bit(77);
 455 +*/
 456 +       if(pm_pwronoff)
 457 +       {
 458 +               /* We are here bcos of pressing of on off switch
 459 +                  We wake up now only on pwr switch */
 460 +               printk("Anup: Before sleeping \n");
 461 +               pm_pwronoff = 0;
 462 +               PGSR0 &= ~GPIO_bit(23);         //7  YoKu GPIO Changed
 463 +               //PGSR2 &= ~GPIO_bit(64);       //64 YoKu Commented in PWG500 64,7 was WifiReg, IN PWG600 it is 23
 464 +
 465 +               PGSR2 &= ~GPIO_bit(80);         //69 YoKu GPIO Changed  Anup : commnented
 466 +               PWER = 0x0004;                  // YoKu Changed from 0x10 to 0x04 (i.e GPIO 4 -> 2)
 467 +               PFER = 0x0004;
 468 +               PRER = 0x0004;
 469 +
 470 +// YoKu ---->
 471 +// 11May2006 To reduce Power Off current from 7mA to 4mA
 472 +               GPDR0 |= GPIO_bit(16);  // BTReset o/p Low
 473 +               PGSR0 &= ~GPIO_bit(16);
 474 +
 475 +               GPDR1 |= GPIO_bit(33);  // nMEC/nPDI o/p Low
 476 +                PGSR1 &= ~GPIO_bit(33);
 477 +
 478 +               GPDR1 |= GPIO_bit(45);  // BTRTS o/p High
 479 +                PGSR1 |= GPIO_bit(45);
 480 +
 481 +
 482 +               GPDR1 |= GPIO_bit(43);  // BTTXD o/p High
 483 +                PGSR1 |= GPIO_bit(43);
 484 +
 485 +               GPDR1 &= ~GPIO_bit(42); // BTRXD i/p
 486 +               GPDR1 &= ~GPIO_bit(44); // BTCTS i/p
 487 +// <---- YoKu
 488 +
 489 +               PSPR = virt_to_phys(pxa_cpu_resume);    // YoKu 29July05 to Resume from where u left, Original PSPR = 0
 490 +       }
 491 +
 492 +       valbefore = GPLR0 & (GPIO_bit(21) | GPIO_bit(22)) ; // 62,63 YoKu GPIO Changed
 493 +
 494 +       //printk("Anup: Before sleeping gpsr0=0x%08x gpsr1=0x%08x gpsr2= 0x%08x\n",gpsr0,gpsr1,gpsr2);
 495 +       //kirti pxa_cpu_suspend();
 496 +       //printk("KER_PM: Going to sleep zzzzzzzzz\n");
 497 +
 498 +//     OSCC |= OSCC_OON; //Tushar: 18 apr. enable 32.768KHz Oscillator
 499 +
 500 +//     PCFR |= PCFR_OPDE; //Tushar: 18 apr. disable 3.6864MHz oscillator
 501 +
 502 +       pxa_cpu_pm_enter(PM_SUSPEND_MEM);
 503
 504         cpu_init();
 505
 506 +       //kirti~
 507 +       /**/
 508 +       //FFMCR |=  UART_DTR ;
 509 +       /**/
 510 +
 511         /* after sleeping, validate the checksum */
 512         checksum = 0;
 513         for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
 514 @@ -141,39 +464,63 @@
 515         checksum = 0;
 516         for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
 517                 checksum += sleep_save[i];
 518 -
 519         /* if invalid, display message and wait for a hardware reset */
 520 -       if (checksum != sleep_save[SLEEP_SAVE_CKSUM]) {
 521 +       if (checksum != sleep_save[SLEEP_SAVE_CKSUM])
 522 +       {
 523  #ifdef CONFIG_ARCH_LUBBOCK
 524                 LUB_HEXLED = 0xbadbadc5;
 525  #endif
 526                 while (1)
 527 -                       pxa_cpu_pm_enter(state);
 528 +               {
 529 +                       printk("\n\n\nKERN_PM: CRC Error!!! after wakeup\n\n\n"); // YoKu 25May06
 530 +
 531         }
 532
 533 +       }
 534 +       valafter = GPLR0 & (GPIO_bit(21) | GPIO_bit(22)) ;      //62,63 YoKu GPIO Changed
 535 +       pm_pedr = PEDR ;
 536 +
 537         /* ensure not to come back here if it wasn't intended */
 538         PSPR = 0;
 539
 540 +       /*printk("YoKu: gafr0_L=0x%08x gafr0_U=0x%08x\n",GAFR0_L,GAFR0_U);
 541 +       printk(" gafr1_L= 0x%08x gafr1_U= 0x%08x\n",GAFR1_L,GAFR1_U);
 542 +       printk(" gafr2_L= 0x%08x gafr2_U= 0x%08x\n",GAFR2_L,GAFR2_U);   */
 543         /* restore registers */
 544 -       RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2);
 545         RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
 546 +       RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
 547 +       RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
 548         RESTORE(GAFR0_L); RESTORE(GAFR0_U);
 549         RESTORE(GAFR1_L); RESTORE(GAFR1_U);
 550         RESTORE(GAFR2_L); RESTORE(GAFR2_U);
 551 -       RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
 552 -       RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
 553 -       RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
 554
 555 -#ifdef CONFIG_PXA27x
 556 -       RESTORE(MDREFR);
 557 -       RESTORE_GPLEVEL(3); RESTORE(GPDR3);
 558 -       RESTORE(GAFR3_L); RESTORE(GAFR3_U);
 559 -       RESTORE(GRER3); RESTORE(GFER3); RESTORE(PGSR3);
 560 -       RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
 561 -       RESTORE(PFER); RESTORE(PKWR);
 562 -#endif
 563
 564 -       PSSR = PSSR_RDH | PSSR_PH;
 565 +       // Anup : For Wifi power saving mode 2 May 2006
 566 +        RESTORE(NSSCR0);RESTORE(NSSCR1);RESTORE(NSSSR);RESTORE(NSSITR);RESTORE(NSSDR);RESTORE(NSSTO);
 567 +        RESTORE(NSSPSP);
 568 +
 569 +       // PSSR = PSSR_PH;
 570 +       GPSR0 = gpsr0;
 571 +       GPSR1 = gpsr1;
 572 +       GPSR2 = gpsr2;
 573 +
 574 +       // Anup : check values of these registers
 575 +//      printk("YoKu: gpsr0=0x%08x gpsr1=0x%08x gpsr2= 0x%08x\n",gpsr0,gpsr1,gpsr2);
 576 +       //sidd
 577 +
 578 +       GPCR0 |= ~gpsr0;
 579 +       GPCR1 |= ~gpsr1;
 580 +       GPCR2 |= ~gpsr2;
 581 +
 582 +
 583 +       PSSR = ~PSSR_PH;
 584 +
 585 +       RESTORE(OSMR0);
 586 +       RESTORE(OSMR1);
 587 +       RESTORE(OSMR2);
 588 +       RESTORE(OSMR3);
 589 +       RESTORE(OSCR);
 590 +       RESTORE(OIER);
 591
 592         RESTORE(CKEN);
 593
 594 @@ -181,62 +528,181 @@
 595         ICCR = 1;
 596         RESTORE(ICMR);
 597
 598 -       RESTORE(PSTR);
 599 +       /*
 600 +        * Temporary solution.  This won't be necessary once
 601 +        * we move pxa support into the serial driver.
 602 +        * Restore the FF UART.
 603 +        */
 604 +       RESTORE(BTMCR);
 605 +       RESTORE(BTSPR);
 606 +       RESTORE(BTLCR);
 607 +       BTLCR |= 0x80;
 608 +       RESTORE(BTDLH);
 609 +       RESTORE(BTDLL);
 610 +       RESTORE(BTLCR);
 611 +       RESTORE(BTISR);
 612 +       BTFCR = 0xc7;
 613 +       RESTORE(BTIER);
 614 +
 615 +       RESTORE(STMCR);
 616 +       RESTORE(STSPR);
 617 +       RESTORE(STLCR);
 618 +       STLCR |= 0x80;
 619 +       RESTORE(STDLH);
 620 +       RESTORE(STDLL);
 621 +       RESTORE(STLCR);
 622 +       RESTORE(STISR);
 623 +       STFCR = 0xc7;
 624 +       RESTORE(STIER);
 625 +
 626 +       RESTORE(FFMCR);
 627 +       RESTORE(FFSPR);
 628 +       RESTORE(FFLCR);
 629 +       FFLCR |= 0x80;
 630 +       RESTORE(FFDLH);
 631 +       RESTORE(FFDLL);
 632 +       RESTORE(FFLCR);
 633 +       RESTORE(FFISR);
 634 +       RESTORE(FFFCR);
 635 +       FFFCR = 0xc7;
 636 +       RESTORE(FFIER);
 637 +
 638 +        // YoKu 23Feb06 Added To save LCD Registers, updated by kirti 24Feb06 ----->
 639 +        RESTORE(LCCR3); RESTORE(LCCR2); RESTORE(LCCR1);
 640 +       LCCR0=RESTORE(LCCR0) & ~LCCR0_ENB;
 641 +        RESTORE(FDADR0); RESTORE(FDADR1);
 642 +       LCCR0 |= LCCR0_ENB;
 643 +
 644 +        // <----- YoKu
 645
 646         /* restore current time */
 647 -       rtc.tv_sec = RCNR;
 648 -       restore_time_delta(&delta, &rtc);
 649 +       xtime.tv_sec = RCNR;
 650 +
 651 +       valafter1 = GPLR0 & (GPIO_bit(21) | GPIO_bit(22)) ;     //62,63 YoKu GPIO Changed
 652 +
 653 +//     SSCR0 &=0xFFFFFFFF;
 654 +//     printk("\nPM : val of SSCR0 = %x " , SSCR0);
 655 +
 656 +       printk("KER_PM: Resumed at RCNR = %d RTSR= %x\n",RCNR,RTSR);
 657 +
 658 +       printk("YoKu: pgsr0=0x%08x pgsr1=0x%08x pgsr2= 0x%08x\n",PGSR0,PGSR1,PGSR2);
 659 +
 660 +       OSMR0 = 0;              /* set initial match at 0 */
 661 +       OSSR = 0xf;             /* clear status on all timers */
 662 +       OIER |= OIER_E0;        /* enable match on timer 0 to cause interrupts */
 663 +       OSCR = 0;               /* initialize free-running timer, force first match */
 664 +
 665 +       leds_event(led_start);
 666 +       //kirti sti();
 667 +       // call i2c reset here---->
 668 +       ICR = ICR_UR;
 669 +       ISR = 0x7FF; //I2C_ISR_INIT;
 670 +       ICR &= ~ICR_UR;
 671 +
 672 +       ISAR = 0x32;//i2c->slave_addr;
 673 +
 674 +       /* set control register values */
 675 +       ICR = (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE);//I2C_ICR_INIT;
 676 +
 677 +       /* enable unit */
 678 +       ICR |= ICR_IUE;
 679 +       udelay(100);
 680 +       //<-----
 681 +
 682 +       local_irq_enable();
 683
 684 -#ifdef DEBUG
 685 -       printk(KERN_DEBUG "*** made it back from resume\n");
 686 -#endif
 687
 688         return 0;
 689  }
 690
 691 -EXPORT_SYMBOL_GPL(pxa_pm_enter);
 692 -
 693  unsigned long sleep_phys_sp(void *sp)
 694  {
 695         return virt_to_phys(sp);
 696  }
 697
 698 +#ifdef CONFIG_SYSCTL
 699  /*
 700 - * Called after processes are frozen, but before we shut down devices.
 701 + * ARGH!  ACPI people defined CTL_ACPI in linux/acpi.h rather than
 702 + * linux/sysctl.h.
 703 + *
 704 + * This means our interface here won't survive long - it needs a new
 705 + * interface.  Quick hack to get this working - use sysctl id 9999.
 706   */
 707 -int pxa_pm_prepare(suspend_state_t state)
 708 -{
 709 -       extern int pxa_cpu_pm_prepare(suspend_state_t state);
 710 +#warning ACPI broke the kernel, this interface needs to be fixed up.
 711 +#define CTL_ACPI 9999
 712 +#define ACPI_S1_SLP_TYP 19
 713
 714 -       return pxa_cpu_pm_prepare(state);
 715 +/*
 716 + * Send us to sleep.
 717 + */
 718 +static int sysctl_pm_do_suspend(ctl_table *ctl, int write, struct file *filp,
 719 +               void *buffer, size_t *lenp)
 720 +{
 721 +       int retval=0;
 722 +       unsigned i , clock ;
 723 +       if (write)
 724 +       {
 725 +               char buf[16], *p;
 726 +               unsigned int sleepsec;
 727 +               int len,left = *lenp;
 728 +
 729 +               len = left;
 730 +               if (left > sizeof(buf))
 731 +                       left = sizeof(buf);
 732 +               if (!copy_from_user(buf, buffer, left))
 733 +               {
 734 +                       buf[sizeof(buf) - 1] = '\0';
 735 +                       sleepsec = simple_strtoul(buf, &p, 0);
 736 +                       printk("\nSleeping %d Pwronoff=%x RCNR=%d\n",sleepsec,pm_pwronoff,RCNR);
 737 +                       printk("\nPWER %x PFER=%x PRER=%x\n",PWER,PFER,PRER);
 738 +                       RTAR = xtime.tv_sec + sleepsec;
 739 +                       printk("\nRTAR=%d \n",RTAR);
 740 +               }
 741 +       }
 742 +       retval = pm_do_suspend();
 743 +       clock = get_memclk_frequency_10khz();
 744 +       return retval;
 745  }
 746 -
 747 -EXPORT_SYMBOL_GPL(pxa_pm_prepare);
 748
 749  /*
 750 - * Called after devices are re-setup, but before processes are thawed.
 751 +static struct ctl_table pm_table[] =
 752 +{
 753 +       {ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, (proc_handler *)&sysctl_pm_do_suspend},
 754 +       {0}
 755 +};
 756   */
 757 -int pxa_pm_finish(suspend_state_t state)
 758 +static struct ctl_table pm_table[] =
 759  {
 760 -       return 0;
 761 +       {
 762 +       ctl_name:       ACPI_S1_SLP_TYP,
 763 +       procname:       "suspend",
 764 +       mode:           0600,
 765 +       proc_handler:   (proc_handler *)&sysctl_pm_do_suspend,
 766 +       },
 767 +       {
 768 +       ctl_name: 0
 769  }
 770 +};
 771
 772 -EXPORT_SYMBOL_GPL(pxa_pm_finish);
 773 +static struct ctl_table pm_dir_table[] =
 774 +{
 775 +       {CTL_ACPI, "pm", NULL, 0, 0555, pm_table},
 776 +       {0}
 777 +};
 778
 779  /*
 780 - * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
 781 + * Initialize power interface
 782   */
 783 -static struct pm_ops pxa_pm_ops = {
 784 -       .pm_disk_mode   = PM_DISK_FIRMWARE,
 785 -       .prepare        = pxa_pm_prepare,
 786 -       .enter          = pxa_pm_enter,
 787 -       .finish         = pxa_pm_finish,
 788 -};
 789 -
 790 -static int __init pxa_pm_init(void)
 791 +static int __init pm_init(void)
 792  {
 793 -       pm_set_ops(&pxa_pm_ops);
 794 +       register_sysctl_table(pm_dir_table, 1);
 795 +        /*Adi: Adjust for clock value to RTC
 796 +        RTTR = RTC clk - 1*/
 797 +        RTTR = 32913;
 798 +
 799         return 0;
 800  }
 801
 802 -device_initcall(pxa_pm_init);
 803 +__initcall(pm_init);
 804 +
 805 +#endif
 806 diff -NurbwB linux-2.6.17/arch/arm/mach-pxa/sleep.S linux-2.6.17-patched/arch/arm/mach-pxa/sleep.S
 807 --- linux-2.6.17/arch/arm/mach-pxa/sleep.S      2006-06-17 18:49:35.000000000 -0700
 808 +++ linux-2.6.17-patched/arch/arm/mach-pxa/sleep.S      2006-09-11 13:07:05.000000000 -0700
 809 @@ -79,7 +79,7 @@
 810         ldr     r5, [r4]
 811
 812         @ enable SDRAM self-refresh mode
 813 -       orr     r5, r5, #MDREFR_SLFRSH
 814 +       orr     r5, r5, #(MDREFR_SLFRSH | MDREFR_APD)
 815
 816  #ifdef CONFIG_PXA27x
 817         @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
 818 diff -NurbwB linux-2.6.17/include/asm-arm/arch-pxa/pxa-regs.h linux-2.6.17-patched/include/asm-arm/arch-pxa/pxa-regs.h
 819 --- linux-2.6.17/include/asm-arm/arch-pxa/pxa-regs.h    2006-06-17 18:49:35.000000000 -0700
 820 +++ linux-2.6.17-patched/include/asm-arm/arch-pxa/pxa-regs.h    2006-09-11 11:04:36.000000000 -0700
 821 @@ -1748,6 +1748,15 @@
 822  #define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL))
 823  #define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL))
 824
 825 +#define NSSCR0          __REG(0x41400000)  /* SSP Port 1 Control Register 0 */
 826 +#define NSSCR1          __REG(0x41400004)  /* SSP Port 1 Control Register 1 */
 827 +#define NSSSR           __REG(0x41400008)  /* SSP Port 1 Status Register */
 828 +#define NSSITR          __REG(0x4140000C)  /* SSP Port 1 Interrupt Test Register */
 829 +#define NSSDR           __REG(0x41400010)  /* (Write / Read) SSP Port 1 Data Write Register/SSP Data Read Register */
 830 +#define NSSTO           __REG(0x41400028)  /* SSP Port 1 Time Out Register */
 831 +#define NSSPSP          __REG(0x4140002C)  /* SSP Port 1 Programmable Serial Port Register */
 832 +
 833 +
 834  /*
 835   * MultiMediaCard (MMC) controller
 836   */
 837 diff -NurbwB linux-2.6.17/kernel/power/main.c linux-2.6.17-patched/kernel/power/main.c
 838 --- linux-2.6.17/kernel/power/main.c    2006-06-17 18:49:35.000000000 -0700
 839 +++ linux-2.6.17-patched/kernel/power/main.c    2006-09-11 12:59:20.000000000 -0700
 840 @@ -66,10 +66,12 @@
 841                 goto Enable_cpu;
 842         }
 843
 844 +       /*
 845         if (freeze_processes()) {
 846                 error = -EAGAIN;
 847                 goto Thaw;
 848         }
 849 +       */
 850
 851         if ((free_pages = nr_free_pages()) < FREE_PAGE_NUMBER) {
 852                 pr_debug("PM: free some memory\n");
 853 @@ -110,12 +112,15 @@
 854
 855         local_irq_save(flags);
 856
 857 +       /*
 858         if ((error = device_power_down(PMSG_SUSPEND))) {
 859                 printk(KERN_ERR "Some devices failed to power down\n");
 860                 goto Done;
 861         }
 862 +       */
 863 +
 864         error = pm_ops->enter(state);
 865 -       device_power_up();
 866 +       //device_power_up();
 867   Done:
 868         local_irq_restore(flags);
 869         return error;