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omap24xx: Add 2.6.36 support
[openwrt.git] / target / linux / brcm63xx / patches-2.6.35 / 240-spi.patch
1 --- a/arch/mips/bcm63xx/cpu.c
2 +++ b/arch/mips/bcm63xx/cpu.c
3 @@ -56,6 +56,7 @@ static const unsigned long bcm96338_regs
4
5 static const int bcm96338_irqs[] = {
6 [IRQ_TIMER] = BCM_6338_TIMER_IRQ,
7 + [IRQ_SPI] = BCM_6338_SPI_IRQ,
8 [IRQ_UART0] = BCM_6338_UART0_IRQ,
9 [IRQ_DSL] = BCM_6338_DSL_IRQ,
10 [IRQ_ENET0] = BCM_6338_ENET0_IRQ,
11 @@ -130,6 +131,7 @@ static const unsigned long bcm96348_regs
12
13 static const int bcm96348_irqs[] = {
14 [IRQ_TIMER] = BCM_6348_TIMER_IRQ,
15 + [IRQ_SPI] = BCM_6348_SPI_IRQ,
16 [IRQ_UART0] = BCM_6348_UART0_IRQ,
17 [IRQ_DSL] = BCM_6348_DSL_IRQ,
18 [IRQ_ENET0] = BCM_6348_ENET0_IRQ,
19 @@ -173,6 +175,7 @@ static const unsigned long bcm96358_regs
20
21 static const int bcm96358_irqs[] = {
22 [IRQ_TIMER] = BCM_6358_TIMER_IRQ,
23 + [IRQ_SPI] = BCM_6358_SPI_IRQ,
24 [IRQ_UART0] = BCM_6358_UART0_IRQ,
25 [IRQ_UART1] = BCM_6358_UART1_IRQ,
26 [IRQ_DSL] = BCM_6358_DSL_IRQ,
27 --- /dev/null
28 +++ b/arch/mips/bcm63xx/dev-spi.c
29 @@ -0,0 +1,60 @@
30 +/*
31 + * This file is subject to the terms and conditions of the GNU General Public
32 + * License. See the file "COPYING" in the main directory of this archive
33 + * for more details.
34 + *
35 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
36 + */
37 +
38 +#include <linux/init.h>
39 +#include <linux/kernel.h>
40 +#include <linux/platform_device.h>
41 +
42 +#include <bcm63xx_cpu.h>
43 +#include <bcm63xx_dev_spi.h>
44 +#include <bcm63xx_regs.h>
45 +
46 +static struct resource spi_resources[] = {
47 + {
48 + .start = -1, /* filled at runtime */
49 + .end = -1, /* filled at runtime */
50 + .flags = IORESOURCE_MEM,
51 + },
52 + {
53 + .start = -1, /* filled at runtime */
54 + .flags = IORESOURCE_IRQ,
55 + },
56 +};
57 +
58 +static struct bcm63xx_spi_pdata spi_pdata = {
59 + .bus_num = 0,
60 + .num_chipselect = 4,
61 + .speed_hz = 50000000, /* Fclk */
62 +};
63 +
64 +static struct platform_device bcm63xx_spi_device = {
65 + .name = "bcm63xx-spi",
66 + .id = 0,
67 + .num_resources = ARRAY_SIZE(spi_resources),
68 + .resource = spi_resources,
69 + .dev = {
70 + .platform_data = &spi_pdata,
71 + },
72 +};
73 +
74 +int __init bcm63xx_spi_register(void)
75 +{
76 + spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
77 + spi_resources[0].end = spi_resources[0].start;
78 + spi_resources[0].end += RSET_SPI_SIZE - 1;
79 + spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
80 +
81 + /* Fill in platform data */
82 + if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
83 + spi_pdata.fifo_size = SPI_BCM_6338_SPI_MSG_DATA_SIZE;
84 +
85 + if (BCMCPU_IS_6358())
86 + spi_pdata.fifo_size = SPI_BCM_6358_SPI_MSG_DATA_SIZE;
87 +
88 + return platform_device_register(&bcm63xx_spi_device);
89 +}
90 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
91 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
92 @@ -109,6 +109,7 @@ enum bcm63xx_regs_set {
93 #define RSET_WDT_SIZE 12
94 #define RSET_ENET_SIZE 2048
95 #define RSET_ENETDMA_SIZE 2048
96 +#define RSET_SPI_SIZE 256
97 #define RSET_UART_SIZE 24
98 #define RSET_UDC_SIZE 256
99 #define RSET_OHCI_SIZE 256
100 @@ -214,7 +215,7 @@ enum bcm63xx_regs_set {
101 #define BCM_6358_UART0_BASE (0xfffe0100)
102 #define BCM_6358_UART1_BASE (0xfffe0120)
103 #define BCM_6358_GPIO_BASE (0xfffe0080)
104 -#define BCM_6358_SPI_BASE (0xdeadbeef)
105 +#define BCM_6358_SPI_BASE (0xfffe0800)
106 #define BCM_6358_UDC0_BASE (0xfffe0400)
107 #define BCM_6358_OHCI0_BASE (0xfffe1400)
108 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
109 @@ -441,6 +442,7 @@ static inline unsigned long bcm63xx_regs
110 */
111 enum bcm63xx_irq {
112 IRQ_TIMER = 0,
113 + IRQ_SPI,
114 IRQ_UART0,
115 IRQ_UART1,
116 IRQ_DSL,
117 @@ -507,6 +509,7 @@ enum bcm63xx_irq {
118 * 6348 irqs
119 */
120 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
121 +#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
122 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
123 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
124 #define BCM_6348_UDC0_IRQ (IRQ_INTERNAL_BASE + 6)
125 @@ -531,6 +534,7 @@ enum bcm63xx_irq {
126 * 6358 irqs
127 */
128 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
129 +#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
130 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
131 #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
132 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
133 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
134 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
135 @@ -769,4 +769,116 @@
136 #define DMIPSPLLCFG_N2_SHIFT 29
137 #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
138
139 +/*************************************************************************
140 + * _REG relative to RSET_SPI
141 + *************************************************************************/
142 +
143 +/* BCM 6338 SPI core */
144 +#define SPI_BCM_6338_SPI_CMD 0x00 /* 16-bits register */
145 +#define SPI_BCM_6338_SPI_INT_STATUS 0x02
146 +#define SPI_BCM_6338_SPI_MASK_INT_ST 0x03
147 +#define SPI_BCM_6338_SPI_INT_MASK 0x04
148 +#define SPI_BCM_6338_SPI_ST 0x05
149 +#define SPI_BCM_6338_SPI_CLK_CFG 0x06
150 +#define SPI_BCM_6338_SPI_FILL_BYTE 0x07
151 +#define SPI_BCM_6338_SPI_MSG_TAIL 0x09
152 +#define SPI_BCM_6338_SPI_RX_TAIL 0x0b
153 +#define SPI_BCM_6338_SPI_MSG_CTL 0x40
154 +#define SPI_BCM_6338_SPI_MSG_DATA 0x41
155 +#define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f
156 +#define SPI_BCM_6338_SPI_RX_DATA 0x80
157 +#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
158 +
159 +/* BCM 6348 SPI core */
160 +#define SPI_BCM_6348_SPI_MASK_INT_ST 0x00
161 +#define SPI_BCM_6348_SPI_INT_STATUS 0x01
162 +#define SPI_BCM_6348_SPI_CMD 0x02 /* 16-bits register */
163 +#define SPI_BCM_6348_SPI_FILL_BYTE 0x04
164 +#define SPI_BCM_6348_SPI_CLK_CFG 0x05
165 +#define SPI_BCM_6348_SPI_ST 0x06
166 +#define SPI_BCM_6348_SPI_INT_MASK 0x07
167 +#define SPI_BCM_6348_SPI_RX_TAIL 0x08
168 +#define SPI_BCM_6348_SPI_MSG_TAIL 0x10
169 +#define SPI_BCM_6348_SPI_MSG_DATA 0x40
170 +#define SPI_BCM_6348_SPI_MSG_CTL 0x42
171 +#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
172 +#define SPI_BCM_6348_SPI_RX_DATA 0x80
173 +#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
174 +
175 +/* BCM 6358 SPI core */
176 +#define SPI_BCM_6358_MSG_CTL 0x00 /* 16-bits register */
177 +
178 +#define SPI_BCM_6358_SPI_MSG_DATA 0x02
179 +#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
180 +
181 +#define SPI_BCM_6358_SPI_RX_DATA 0x400
182 +#define SPI_BCM_6358_SPI_RX_DATA_SIZE 0x220
183 +
184 +#define SPI_BCM_6358_SPI_CMD 0x700 /* 16-bits register */
185 +
186 +#define SPI_BCM_6358_SPI_INT_STATUS 0x702
187 +#define SPI_BCM_6358_SPI_MASK_INT_ST 0x703
188 +
189 +#define SPI_BCM_6358_SPI_INT_MASK 0x704
190 +
191 +#define SPI_BCM_6358_SPI_STATUS 0x705
192 +
193 +#define SPI_BCM_6358_SPI_CLK_CFG 0x706
194 +
195 +#define SPI_BCM_6358_SPI_FILL_BYTE 0x707
196 +#define SPI_BCM_6358_SPI_MSG_TAIL 0x709
197 +#define SPI_BCM_6358_SPI_RX_TAIL 0x70B
198 +
199 +/* Shared SPI definitions */
200 +
201 +/* Message configuration */
202 +#define SPI_FD_RW 0x00
203 +#define SPI_HD_W 0x01
204 +#define SPI_HD_R 0x02
205 +#define SPI_BYTE_CNT_SHIFT 0
206 +#define SPI_MSG_TYPE_SHIFT 14
207 +
208 +/* Command */
209 +#define SPI_CMD_NOOP 0x01
210 +#define SPI_CMD_SOFT_RESET 0x02
211 +#define SPI_CMD_HARD_RESET 0x04
212 +#define SPI_CMD_START_IMMEDIATE 0x08
213 +#define SPI_CMD_COMMAND_SHIFT 0
214 +#define SPI_CMD_COMMAND_MASK 0x000f
215 +#define SPI_CMD_DEVICE_ID_SHIFT 4
216 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
217 +#define SPI_CMD_ONE_BYTE_SHIFT 11
218 +#define SPI_CMD_ONE_WIRE_SHIFT 12
219 +#define SPI_DEV_ID_0 0
220 +#define SPI_DEV_ID_1 1
221 +#define SPI_DEV_ID_2 2
222 +#define SPI_DEV_ID_3 3
223 +
224 +/* Interrupt mask */
225 +#define SPI_INTR_CMD_DONE 0x01
226 +#define SPI_INTR_RX_OVERFLOW 0x02
227 +#define SPI_INTR_TX_UNDERFLOW 0x04
228 +#define SPI_INTR_TX_OVERFLOW 0x08
229 +#define SPI_INTR_RX_UNDERFLOW 0x10
230 +#define SPI_INTR_CLEAR_ALL 0x1f
231 +
232 +/* Status */
233 +#define SPI_RX_EMPTY 0x02
234 +#define SPI_CMD_BUSY 0x04
235 +#define SPI_SERIAL_BUSY 0x08
236 +
237 +/* Clock configuration */
238 +#define SPI_CLK_20MHZ 0x00
239 +#define SPI_CLK_0_391MHZ 0x01
240 +#define SPI_CLK_0_781MHZ 0x02 /* default */
241 +#define SPI_CLK_1_563MHZ 0x03
242 +#define SPI_CLK_3_125MHZ 0x04
243 +#define SPI_CLK_6_250MHZ 0x05
244 +#define SPI_CLK_12_50MHZ 0x06
245 +#define SPI_CLK_25MHZ 0x07
246 +#define SPI_CLK_MASK 0x07
247 +#define SPI_SSOFFTIME_MASK 0x38
248 +#define SPI_SSOFFTIME_SHIFT 3
249 +#define SPI_BYTE_SWAP 0x80
250 +
251 #endif /* BCM63XX_REGS_H_ */
252 --- /dev/null
253 +++ b/drivers/spi/bcm63xx_spi.c
254 @@ -0,0 +1,628 @@
255 +/*
256 + * Broadcom BCM63xx SPI controller support
257 + *
258 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
259 + *
260 + * This program is free software; you can redistribute it and/or
261 + * modify it under the terms of the GNU General Public License
262 + * as published by the Free Software Foundation; either version 2
263 + * of the License, or (at your option) any later version.
264 + *
265 + * This program is distributed in the hope that it will be useful,
266 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
267 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
268 + * GNU General Public License for more details.
269 + *
270 + * You should have received a copy of the GNU General Public License
271 + * along with this program; if not, write to the
272 + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
273 + */
274 +
275 +#include <linux/kernel.h>
276 +#include <linux/init.h>
277 +#include <linux/clk.h>
278 +#include <linux/module.h>
279 +#include <linux/platform_device.h>
280 +#include <linux/delay.h>
281 +#include <linux/interrupt.h>
282 +#include <linux/spi/spi.h>
283 +#include <linux/spi/spi_bitbang.h>
284 +#include <linux/gpio.h>
285 +#include <linux/completion.h>
286 +#include <linux/err.h>
287 +
288 +#include <bcm63xx_io.h>
289 +#include <bcm63xx_regs.h>
290 +#include <bcm63xx_dev_spi.h>
291 +
292 +#define PFX KBUILD_MODNAME
293 +#define DRV_VER "0.1.2"
294 +
295 +enum bcm63xx_regs_spi {
296 + SPI_CMD,
297 + SPI_INT_STATUS,
298 + SPI_INT_MASK_ST,
299 + SPI_INT_MASK,
300 + SPI_ST,
301 + SPI_CLK_CFG,
302 + SPI_FILL_BYTE,
303 + SPI_MSG_TAIL,
304 + SPI_RX_TAIL,
305 + SPI_MSG_CTL,
306 + SPI_MSG_DATA,
307 + SPI_RX_DATA,
308 +};
309 +
310 +/*
311 + * register offsets
312 + */
313 +static const unsigned long bcm96338_regs_spi[] = {
314 + [SPI_CMD] = SPI_BCM_6338_SPI_CMD,
315 + [SPI_INT_STATUS] = SPI_BCM_6338_SPI_INT_STATUS,
316 + [SPI_INT_MASK_ST] = SPI_BCM_6338_SPI_MASK_INT_ST,
317 + [SPI_INT_MASK] = SPI_BCM_6338_SPI_INT_MASK,
318 + [SPI_ST] = SPI_BCM_6338_SPI_ST,
319 + [SPI_CLK_CFG] = SPI_BCM_6338_SPI_CLK_CFG,
320 + [SPI_FILL_BYTE] = SPI_BCM_6338_SPI_FILL_BYTE,
321 + [SPI_MSG_TAIL] = SPI_BCM_6338_SPI_MSG_TAIL,
322 + [SPI_RX_TAIL] = SPI_BCM_6338_SPI_RX_TAIL,
323 + [SPI_MSG_CTL] = SPI_BCM_6338_SPI_MSG_CTL,
324 + [SPI_MSG_DATA] = SPI_BCM_6338_SPI_MSG_DATA,
325 + [SPI_RX_DATA] = SPI_BCM_6338_SPI_RX_DATA,
326 +};
327 +
328 +static const unsigned long bcm96348_regs_spi[] = {
329 + [SPI_CMD] = SPI_BCM_6348_SPI_CMD,
330 + [SPI_INT_STATUS] = SPI_BCM_6348_SPI_INT_STATUS,
331 + [SPI_INT_MASK_ST] = SPI_BCM_6348_SPI_MASK_INT_ST,
332 + [SPI_INT_MASK] = SPI_BCM_6348_SPI_INT_MASK,
333 + [SPI_ST] = SPI_BCM_6348_SPI_ST,
334 + [SPI_CLK_CFG] = SPI_BCM_6348_SPI_CLK_CFG,
335 + [SPI_FILL_BYTE] = SPI_BCM_6348_SPI_FILL_BYTE,
336 + [SPI_MSG_TAIL] = SPI_BCM_6348_SPI_MSG_TAIL,
337 + [SPI_RX_TAIL] = SPI_BCM_6348_SPI_RX_TAIL,
338 + [SPI_MSG_CTL] = SPI_BCM_6348_SPI_MSG_CTL,
339 + [SPI_MSG_DATA] = SPI_BCM_6348_SPI_MSG_DATA,
340 + [SPI_RX_DATA] = SPI_BCM_6348_SPI_RX_DATA,
341 +};
342 +
343 +static const unsigned long bcm96358_regs_spi[] = {
344 + [SPI_CMD] = SPI_BCM_6358_SPI_CMD,
345 + [SPI_INT_STATUS] = SPI_BCM_6358_SPI_INT_STATUS,
346 + [SPI_INT_MASK_ST] = SPI_BCM_6358_SPI_MASK_INT_ST,
347 + [SPI_INT_MASK] = SPI_BCM_6358_SPI_INT_MASK,
348 + [SPI_ST] = SPI_BCM_6358_SPI_STATUS,
349 + [SPI_CLK_CFG] = SPI_BCM_6358_SPI_CLK_CFG,
350 + [SPI_FILL_BYTE] = SPI_BCM_6358_SPI_FILL_BYTE,
351 + [SPI_MSG_TAIL] = SPI_BCM_6358_SPI_MSG_TAIL,
352 + [SPI_RX_TAIL] = SPI_BCM_6358_SPI_RX_TAIL,
353 + [SPI_MSG_CTL] = SPI_BCM_6358_MSG_CTL,
354 + [SPI_MSG_DATA] = SPI_BCM_6358_SPI_MSG_DATA,
355 + [SPI_RX_DATA] = SPI_BCM_6358_SPI_RX_DATA,
356 +};
357 +
358 +
359 +#ifdef BCMCPU_RUNTIME_DETECT
360 +static const unsigned long *bcm63xx_regs_spi;
361 +
362 +static __init void bcm63xx_spi_regs_init(void)
363 +{
364 + if (BCMCPU_IS_6338())
365 + bcm63xx_regs_spi = bcm96338_regs_spi;
366 + if (BCMCPU_IS_6348())
367 + bcm63xx_regs_spi = bcm96348_regs_spi;
368 + if (BCMCPU_IS_6358())
369 + bcm63xx_regs_spi = bcm96358_regs_spi;
370 +}
371 +#else
372 +static __init void bcm63xx_spi_regs_init(void) { }
373 +#endif
374 +
375 +static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
376 +{
377 +#ifdef BCMCPU_RUNTIME_DETECT
378 + return bcm63xx_regs_spi[reg];
379 +#else
380 +#ifdef CONFIG_BCM63XX_CPU_6338
381 +switch (reg) {
382 + case SPI_CMD:
383 + return SPI_BCM_6338_SPI_CMD;
384 + case SPI_INT_STATUS:
385 + return SPI_BCM_6338_SPI_INT_STATUS;
386 + case SPI_INT_MASK_ST:
387 + return SPI_BCM_6338_SPI_MASK_INT_ST;
388 + case SPI_INT_MASK:
389 + return SPI_BCM_6338_SPI_INT_MASK;
390 + case SPI_ST:
391 + return SPI_BCM_6338_SPI_ST;
392 + case SPI_CLK_CFG:
393 + return SPI_BCM_6338_SPI_CLK_CFG;
394 + case SPI_FILL_BYTE:
395 + return SPI_BCM_6338_SPI_FILL_BYTE;
396 + case SPI_MSG_TAIL:
397 + return SPI_BCM_6338_SPI_MSG_TAIL;
398 + case SPI_RX_TAIL:
399 + return SPI_BCM_6338_SPI_RX_TAIL;
400 + case SPI_MSG_CTL:
401 + return SPI_BCM_6338_SPI_MSG_CTL;
402 + case SPI_MSG_DATA:
403 + return SPI_BCM_6338_SPI_MSG_DATA;
404 + case SPI_RX_DATA:
405 + return SPI_BCM_6338_SPI_RX_DATA;
406 +}
407 +#endif
408 +#ifdef CONFIG_BCM63XX_CPU_6348
409 +switch (reg) {
410 + case SPI_CMD:
411 + return SPI_BCM_6348_SPI_CMD;
412 + case SPI_INT_MASK_ST:
413 + return SPI_BCM_6348_SPI_MASK_INT_ST;
414 + case SPI_INT_MASK:
415 + return SPI_BCM_6348_SPI_INT_MASK;
416 + case SPI_INT_STATUS:
417 + return SPI_BCM_6348_SPI_INT_STATUS;
418 + case SPI_ST:
419 + return SPI_BCM_6348_SPI_ST;
420 + case SPI_CLK_CFG:
421 + return SPI_BCM_6348_SPI_CLK_CFG;
422 + case SPI_FILL_BYTE:
423 + return SPI_BCM_6348_SPI_FILL_BYTE;
424 + case SPI_MSG_TAIL:
425 + return SPI_BCM_6348_SPI_MSG_TAIL;
426 + case SPI_RX_TAIL:
427 + return SPI_BCM_6348_SPI_RX_TAIL;
428 + case SPI_MSG_CTL:
429 + return SPI_BCM_6348_SPI_MSG_CTL;
430 + case SPI_MSG_DATA:
431 + return SPI_BCM_6348_SPI_MSG_DATA;
432 + case SPI_RX_DATA:
433 + return SPI_BCM_6348_SPI_RX_DATA;
434 +}
435 +#endif
436 +#ifdef CONFIG_BCM63XX_CPU_6358
437 +switch (reg) {
438 + case SPI_CMD:
439 + return SPI_BCM_6358_SPI_CMD;
440 + case SPI_INT_STATUS:
441 + return SPI_BCM_6358_SPI_INT_STATUS;
442 + case SPI_INT_MASK_ST:
443 + return SPI_BCM_6358_SPI_MASK_INT_ST;
444 + case SPI_INT_MASK:
445 + return SPI_BCM_6358_SPI_INT_MASK;
446 + case SPI_ST:
447 + return SPI_BCM_6358_SPI_STATUS;
448 + case SPI_CLK_CFG:
449 + return SPI_BCM_6358_SPI_CLK_CFG;
450 + case SPI_FILL_BYTE:
451 + return SPI_BCM_6358_SPI_FILL_BYTE;
452 + case SPI_MSG_TAIL:
453 + return SPI_BCM_6358_SPI_MSG_TAIL;
454 + case SPI_RX_TAIL:
455 + return SPI_BCM_6358_SPI_RX_TAIL;
456 + case SPI_MSG_CTL:
457 + return SPI_BCM_6358_MSG_CTL;
458 + case SPI_MSG_DATA:
459 + return SPI_BCM_6358_SPI_MSG_DATA;
460 + case SPI_RX_DATA:
461 + return SPI_BCM_6358_SPI_RX_DATA;
462 +}
463 +#endif
464 +#endif
465 + return 0;
466 +}
467 +
468 +/*
469 + * helpers for the SPI register sets
470 + */
471 +#define bcm_spi_readb(b,o) bcm_readb((b) + bcm63xx_spireg(o))
472 +#define bcm_spi_readw(b,o) bcm_readw((b) + bcm63xx_spireg(o))
473 +#define bcm_spi_writeb(v,b,o) bcm_writeb((v), (b) + bcm63xx_spireg(o))
474 +#define bcm_spi_writew(v,b,o) bcm_writew((v), (b) + bcm63xx_spireg(o))
475 +
476 +struct bcm63xx_spi {
477 + /* bitbang has to be first */
478 + struct spi_bitbang bitbang;
479 + struct completion done;
480 +
481 + void __iomem *regs;
482 + int irq;
483 +
484 + /* Platform data */
485 + u32 speed_hz;
486 + unsigned fifo_size;
487 +
488 + /* Data buffers */
489 + const unsigned char *tx_ptr;
490 + unsigned char *rx_ptr;
491 + int remaining_bytes;
492 +
493 + struct clk *clk;
494 + struct resource *ioarea;
495 + struct platform_device *pdev;
496 +};
497 +
498 +static void bcm63xx_spi_chipselect(struct spi_device *spi, int is_on)
499 +{
500 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
501 + u16 val;
502 +
503 + val = bcm_spi_readw(bs->regs, SPI_CMD);
504 + if (is_on == BITBANG_CS_INACTIVE)
505 + val |= SPI_CMD_NOOP;
506 + else if (is_on == BITBANG_CS_ACTIVE)
507 + val |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
508 +
509 + bcm_spi_writew(val, bs->regs, SPI_CMD);
510 +}
511 +
512 +static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
513 + struct spi_transfer *t)
514 +{
515 + u8 bits_per_word;
516 + u8 clk_cfg;
517 + u32 hz;
518 + unsigned int div;
519 +
520 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
521 +
522 + bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
523 + hz = (t) ? t->speed_hz : spi->max_speed_hz;
524 + if (bits_per_word != 8) {
525 + dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
526 + __func__, bits_per_word);
527 + return -EINVAL;
528 + }
529 +
530 + if (spi->chip_select > spi->master->num_chipselect) {
531 + dev_err(&spi->dev, "%s, unsupported slave %d\n",
532 + __func__, spi->chip_select);
533 + return -EINVAL;
534 + }
535 +
536 + /* Check clock setting */
537 + div = (bs->speed_hz / hz);
538 + switch (div) {
539 + case 2:
540 + clk_cfg = SPI_CLK_25MHZ;
541 + break;
542 + case 4:
543 + clk_cfg = SPI_CLK_12_50MHZ;
544 + break;
545 + case 8:
546 + clk_cfg = SPI_CLK_6_250MHZ;
547 + break;
548 + case 16:
549 + clk_cfg = SPI_CLK_3_125MHZ;
550 + break;
551 + case 32:
552 + clk_cfg = SPI_CLK_1_563MHZ;
553 + break;
554 + case 128:
555 + clk_cfg = SPI_CLK_0_781MHZ;
556 + break;
557 + case 64:
558 + default:
559 + /* Set to slowest mode for compatibility */
560 + clk_cfg = SPI_CLK_0_781MHZ;
561 + break;
562 + }
563 +
564 + bcm_spi_writeb(clk_cfg, bs->regs, SPI_CLK_CFG);
565 + dev_dbg(&spi->dev, "Setting clock register to %d (hz %d, cmd %02x)\n",
566 + div, hz, clk_cfg);
567 +
568 + return 0;
569 +}
570 +
571 +/* the spi->mode bits understood by this driver: */
572 +#define MODEBITS (SPI_CPOL | SPI_CPHA)
573 +
574 +static int bcm63xx_spi_setup(struct spi_device *spi)
575 +{
576 + struct spi_bitbang *bitbang;
577 + struct bcm63xx_spi *bs;
578 + int retval;
579 +
580 + bs = spi_master_get_devdata(spi->master);
581 + bitbang = &bs->bitbang;
582 +
583 + if (!spi->bits_per_word)
584 + spi->bits_per_word = 8;
585 +
586 + if (spi->mode & ~MODEBITS) {
587 + dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
588 + __func__, spi->mode & ~MODEBITS);
589 + return -EINVAL;
590 + }
591 +
592 + retval = bcm63xx_spi_setup_transfer(spi, NULL);
593 + if (retval < 0) {
594 + dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
595 + spi->mode & ~MODEBITS);
596 + return retval;
597 + }
598 +
599 + dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
600 + __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
601 +
602 + return 0;
603 +}
604 +
605 +/* Fill the TX FIFO with as many bytes as possible */
606 +static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
607 +{
608 + u8 tail;
609 +
610 + /* Fill the Tx FIFO with as many bytes as possible */
611 + tail = bcm_spi_readb(bs->regs, SPI_MSG_TAIL);
612 + while ((tail < bs->fifo_size) && (bs->remaining_bytes > 0)) {
613 + if (bs->tx_ptr)
614 + bcm_spi_writeb(*bs->tx_ptr++, bs->regs, SPI_MSG_DATA);
615 + else
616 + bcm_spi_writeb(0, bs->regs, SPI_MSG_DATA);
617 + bs->remaining_bytes--;
618 + tail = bcm_spi_readb(bs->regs, SPI_MSG_TAIL);
619 + }
620 +}
621 +
622 +static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
623 +{
624 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
625 + u8 msg_ctl;
626 + u16 cmd;
627 +
628 + dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
629 + t->tx_buf, t->rx_buf, t->len);
630 +
631 + /* Transmitter is inhibited */
632 + bs->tx_ptr = t->tx_buf;
633 + bs->rx_ptr = t->rx_buf;
634 + bs->remaining_bytes = t->len;
635 + init_completion(&bs->done);
636 +
637 + bcm63xx_spi_fill_tx_fifo(bs);
638 +
639 + /* Enable the command done interrupt which
640 + * we use to determine completion of a command */
641 + bcm_spi_writeb(SPI_INTR_CMD_DONE, bs->regs, SPI_INT_MASK);
642 +
643 + /* Fill in the Message control register */
644 + msg_ctl = bcm_spi_readb(bs->regs, SPI_MSG_CTL);
645 + msg_ctl |= (t->len << SPI_BYTE_CNT_SHIFT);
646 + msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
647 + bcm_spi_writeb(msg_ctl, bs->regs, SPI_MSG_CTL);
648 +
649 + /* Issue the transfer */
650 + cmd = bcm_spi_readw(bs->regs, SPI_CMD);
651 + cmd |= SPI_CMD_START_IMMEDIATE;
652 + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
653 + bcm_spi_writew(cmd, bs->regs, SPI_CMD);
654 +
655 + wait_for_completion(&bs->done);
656 +
657 + /* Disable the CMD_DONE interrupt */
658 + bcm_spi_writeb(~(SPI_INTR_CMD_DONE), bs->regs, SPI_INT_MASK);
659 +
660 + return t->len - bs->remaining_bytes;
661 +}
662 +
663 +/* This driver supports single master mode only. Hence
664 + * CMD_DONE is the only interrupt we care about
665 + */
666 +static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
667 +{
668 + struct spi_master *master = (struct spi_master *)dev_id;
669 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
670 + u8 intr;
671 + u16 cmd;
672 +
673 + /* Read interupts and clear them immediately */
674 + intr = bcm_spi_readb(bs->regs, SPI_INT_STATUS);
675 + bcm_spi_writeb(SPI_INTR_CLEAR_ALL, bs->regs, SPI_INT_MASK);
676 +
677 + /* A tansfer completed */
678 + if (intr & SPI_INTR_CMD_DONE) {
679 + u8 rx_empty;
680 +
681 + rx_empty = bcm_spi_readb(bs->regs, SPI_ST);
682 + /* Read out all the data */
683 + while ((rx_empty & SPI_RX_EMPTY) == 0) {
684 + u8 data;
685 +
686 + data = bcm_spi_readb(bs->regs, SPI_RX_DATA);
687 + if (bs->rx_ptr)
688 + *bs->rx_ptr++ = data;
689 +
690 + rx_empty = bcm_spi_readb(bs->regs, SPI_RX_EMPTY);
691 + }
692 +
693 + /* See if there is more data to send */
694 + if (bs->remaining_bytes > 0) {
695 + bcm63xx_spi_fill_tx_fifo(bs);
696 +
697 + /* Start the transfer */
698 + cmd = bcm_spi_readw(bs->regs, SPI_CMD);
699 + cmd |= SPI_CMD_START_IMMEDIATE;
700 + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
701 + bcm_spi_writew(cmd, bs->regs, SPI_CMD);
702 + } else
703 + complete(&bs->done);
704 + }
705 +
706 + return IRQ_HANDLED;
707 +}
708 +
709 +
710 +static int __init bcm63xx_spi_probe(struct platform_device *pdev)
711 +{
712 + struct resource *r;
713 + struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
714 + int irq;
715 + struct spi_master *master;
716 + struct clk *clk;
717 + struct bcm63xx_spi *bs;
718 + int ret;
719 +
720 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
721 + if (!r) {
722 + ret = -ENXIO;
723 + goto out;
724 + }
725 +
726 + irq = platform_get_irq(pdev, 0);
727 + if (irq < 0) {
728 + ret = -ENXIO;
729 + goto out;
730 + }
731 +
732 + bcm63xx_spi_regs_init();
733 +
734 + clk = clk_get(&pdev->dev, "spi");
735 + if (IS_ERR(clk)) {
736 + dev_err(&pdev->dev, "No clock for device\n");
737 + ret = -ENODEV;
738 + goto out;
739 + }
740 +
741 + master = spi_alloc_master(&pdev->dev, sizeof(struct bcm63xx_spi));
742 + if (!master) {
743 + ret = -ENOMEM;
744 + goto out_free;
745 + }
746 +
747 + bs = spi_master_get_devdata(master);
748 + bs->bitbang.master = spi_master_get(master);
749 + bs->bitbang.chipselect = bcm63xx_spi_chipselect;
750 + bs->bitbang.setup_transfer = bcm63xx_spi_setup_transfer;
751 + bs->bitbang.txrx_bufs = bcm63xx_txrx_bufs;
752 + bs->bitbang.master->setup = bcm63xx_spi_setup;
753 + init_completion(&bs->done);
754 +
755 + platform_set_drvdata(pdev, master);
756 + bs->pdev = pdev;
757 +
758 + if (!request_mem_region(r->start,
759 + r->end - r->start, PFX)) {
760 + ret = -ENXIO;
761 + goto out_free;
762 + }
763 +
764 + bs->regs = ioremap_nocache(r->start, r->end - r->start);
765 + if (!bs->regs) {
766 + printk(KERN_ERR PFX " unable to ioremap regs\n");
767 + ret = -ENOMEM;
768 + goto out_free;
769 + }
770 + bs->irq = irq;
771 + bs->clk = clk;
772 + bs->fifo_size = pdata->fifo_size;
773 +
774 + ret = request_irq(irq, bcm63xx_spi_interrupt, 0,
775 + pdev->name, master);
776 + if (ret) {
777 + printk(KERN_ERR PFX " unable to request irq\n");
778 + goto out_unmap;
779 + }
780 +
781 + master->bus_num = pdata->bus_num;
782 + master->num_chipselect = pdata->num_chipselect;
783 + bs->speed_hz = pdata->speed_hz;
784 +
785 + /* Initialize hardware */
786 + clk_enable(bs->clk);
787 + bcm_spi_writeb(SPI_INTR_CLEAR_ALL, bs->regs, SPI_INT_MASK);
788 +
789 + dev_info(&pdev->dev, " at 0x%08x (irq %d, FIFOs size %d) v%s\n",
790 + r->start, irq, bs->fifo_size, DRV_VER);
791 +
792 + ret = spi_bitbang_start(&bs->bitbang);
793 + if (ret) {
794 + dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
795 + goto out_reset_hw;
796 + }
797 +
798 + return ret;
799 +
800 +out_reset_hw:
801 + clk_disable(clk);
802 + free_irq(irq, master);
803 +out_unmap:
804 + iounmap(bs->regs);
805 +out_free:
806 + clk_put(clk);
807 + spi_master_put(master);
808 +out:
809 + return ret;
810 +}
811 +
812 +static int __exit bcm63xx_spi_remove(struct platform_device *pdev)
813 +{
814 + struct spi_master *master = platform_get_drvdata(pdev);
815 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
816 +
817 + spi_bitbang_stop(&bs->bitbang);
818 + clk_disable(bs->clk);
819 + clk_put(bs->clk);
820 + free_irq(bs->irq, master);
821 + iounmap(bs->regs);
822 + platform_set_drvdata(pdev, 0);
823 + spi_master_put(bs->bitbang.master);
824 +
825 + return 0;
826 +}
827 +
828 +#ifdef CONFIG_PM
829 +static int bcm63xx_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
830 +{
831 + struct spi_master *master = platform_get_drvdata(pdev);
832 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
833 +
834 + clk_disable(bs->clk);
835 +
836 + return 0;
837 +}
838 +
839 +static int bcm63xx_spi_resume(struct platform_device *pdev)
840 +{
841 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
842 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
843 +
844 + clk_enable(bs->clk);
845 +
846 + return 0;
847 +}
848 +#else
849 +#define bcm63xx_spi_suspend NULL
850 +#define bcm63xx_spi_resume NULL
851 +#endif
852 +
853 +static struct platform_driver bcm63xx_spi_driver = {
854 + .driver = {
855 + .name = "bcm63xx-spi",
856 + .owner = THIS_MODULE,
857 + },
858 + .probe = bcm63xx_spi_probe,
859 + .remove = bcm63xx_spi_remove,
860 + .suspend = bcm63xx_spi_suspend,
861 + .resume = bcm63xx_spi_resume,
862 +};
863 +
864 +
865 +static int __init bcm63xx_spi_init(void)
866 +{
867 + return platform_driver_register(&bcm63xx_spi_driver);
868 +}
869 +
870 +static void __exit bcm63xx_spi_exit(void)
871 +{
872 + platform_driver_unregister(&bcm63xx_spi_driver);
873 +}
874 +
875 +module_init(bcm63xx_spi_init);
876 +module_exit(bcm63xx_spi_exit);
877 +
878 +MODULE_ALIAS("platform:bcm63xx_spi");
879 +MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
880 +MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
881 +MODULE_LICENSE("GPL");
882 +MODULE_VERSION(DRV_VER);
883 --- a/drivers/spi/Kconfig
884 +++ b/drivers/spi/Kconfig
885 @@ -60,6 +60,13 @@ config SPI_ATMEL
886 This selects a driver for the Atmel SPI Controller, present on
887 many AT32 (AVR32) and AT91 (ARM) chips.
888
889 +config SPI_BCM63XX
890 + tristate "Broadcom BCM63xx SPI controller"
891 + depends on BCM63XX
892 + select SPI_BITBANG
893 + help
894 + This is the SPI controller master driver for Broadcom BCM63xx SoC.
895 +
896 config SPI_BFIN
897 tristate "SPI controller driver for ADI Blackfin5xx"
898 depends on BLACKFIN
899 --- a/drivers/spi/Makefile
900 +++ b/drivers/spi/Makefile
901 @@ -48,6 +48,7 @@ obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.
902 obj-$(CONFIG_SPI_SH_MSIOF) += spi_sh_msiof.o
903 obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o
904 obj-$(CONFIG_SPI_NUC900) += spi_nuc900.o
905 +obj-$(CONFIG_SPI_BCM63XX) += bcm63xx_spi.o
906
907 # special build for s3c24xx spi driver with fiq support
908 spi_s3c24xx_hw-y := spi_s3c24xx.o
909 --- /dev/null
910 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
911 @@ -0,0 +1,15 @@
912 +#ifndef BCM63XX_DEV_SPI_H
913 +#define BCM63XX_DEV_SPI_H
914 +
915 +#include <linux/types.h>
916 +
917 +int __init bcm63xx_spi_register(void);
918 +
919 +struct bcm63xx_spi_pdata {
920 + unsigned int fifo_size;
921 + int bus_num;
922 + int num_chipselect;
923 + u32 speed_hz;
924 +};
925 +
926 +#endif /* BCM63XX_DEV_SPI_H */
927 --- a/arch/mips/bcm63xx/Makefile
928 +++ b/arch/mips/bcm63xx/Makefile
929 @@ -1,6 +1,6 @@
930 obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
931 dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o \
932 - dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o
933 + dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o dev-spi.o
934 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
935
936 obj-y += boards/
937 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
938 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
939 @@ -31,6 +31,7 @@
940 #include <bcm63xx_dev_usb_ohci.h>
941 #include <bcm63xx_dev_usb_ehci.h>
942 #include <bcm63xx_dev_usb_udc.h>
943 +#include <bcm63xx_dev_spi.h>
944 #include <board_bcm963xx.h>
945
946 #define PFX "board_bcm963xx: "
947 @@ -1557,6 +1558,9 @@ int __init board_register_devices(void)
948 if (board.has_udc0)
949 bcm63xx_udc_register();
950
951 + if (!BCMCPU_IS_6345())
952 + bcm63xx_spi_register();
953 +
954 /* read base address of boot chip select (0) */
955 if (BCMCPU_IS_6345())
956 val = 0x1fc00000;
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