projects / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
omap24xx: Add 2.6.36 support
[openwrt.git] / target / linux / omap24xx / patches-2.6.36 / 200-omap-platform.patch
1 ---
2 arch/arm/include/asm/setup.h | 12
3 arch/arm/plat-omap/Kconfig | 24
4 arch/arm/plat-omap/Makefile | 2
5 arch/arm/plat-omap/bootreason.c | 79 ++
6 arch/arm/plat-omap/common.c | 70 ++
7 arch/arm/plat-omap/component-version.c | 64 ++
8 arch/arm/plat-omap/include/mach/blizzard.h | 12
9 arch/arm/plat-omap/include/mach/board-ams-delta.h | 76 ++
10 arch/arm/plat-omap/include/mach/board-sx1.h | 52 +
11 arch/arm/plat-omap/include/mach/board-voiceblue.h | 19
12 arch/arm/plat-omap/include/mach/board.h | 169 +++++
13 arch/arm/plat-omap/include/mach/cbus.h | 31 +
14 arch/arm/plat-omap/include/mach/clkdev.h | 13
15 arch/arm/plat-omap/include/mach/clkdev_omap.h | 41 +
16 arch/arm/plat-omap/include/mach/clock.h | 168 +++++
17 arch/arm/plat-omap/include/mach/clockdomain.h | 111 +++
18 arch/arm/plat-omap/include/mach/common.h | 83 ++
19 arch/arm/plat-omap/include/mach/control.h | 325 ++++++++++
20 arch/arm/plat-omap/include/mach/cpu.h | 516 +++++++++++++++++
21 arch/arm/plat-omap/include/mach/display.h | 575 +++++++++++++++++++
22 arch/arm/plat-omap/include/mach/dma.h | 640 +++++++++++++++++++++
23 arch/arm/plat-omap/include/mach/dmtimer.h | 84 ++
24 arch/arm/plat-omap/include/mach/dsp_common.h | 40 +
25 arch/arm/plat-omap/include/mach/fpga.h | 197 ++++++
26 arch/arm/plat-omap/include/mach/gpio-switch.h | 54 +
27 arch/arm/plat-omap/include/mach/gpio.h | 129 ++++
28 arch/arm/plat-omap/include/mach/gpmc-smc91x.h | 42 +
29 arch/arm/plat-omap/include/mach/gpmc.h | 115 +++
30 arch/arm/plat-omap/include/mach/hardware.h | 290 +++++++++
31 arch/arm/plat-omap/include/mach/hwa742.h | 8
32 arch/arm/plat-omap/include/mach/i2c.h | 39 +
33 arch/arm/plat-omap/include/mach/io.h | 287 +++++++++
34 arch/arm/plat-omap/include/mach/iommu.h | 168 +++++
35 arch/arm/plat-omap/include/mach/iommu2.h | 96 +++
36 arch/arm/plat-omap/include/mach/iovmm.h | 94 +++
37 arch/arm/plat-omap/include/mach/irda.h | 33 +
38 arch/arm/plat-omap/include/mach/irqs.h | 506 ++++++++++++++++
39 arch/arm/plat-omap/include/mach/keypad.h | 45 +
40 arch/arm/plat-omap/include/mach/lcd_mipid.h | 29
41 arch/arm/plat-omap/include/mach/led.h | 24
42 arch/arm/plat-omap/include/mach/mailbox.h | 111 +++
43 arch/arm/plat-omap/include/mach/mcbsp.h | 462 +++++++++++++++
44 arch/arm/plat-omap/include/mach/mcspi.h | 15
45 arch/arm/plat-omap/include/mach/memory.h | 103 +++
46 arch/arm/plat-omap/include/mach/menelaus.h | 49 +
47 arch/arm/plat-omap/include/mach/mmc.h | 157 +++++
48 arch/arm/plat-omap/include/mach/mux.h | 662 ++++++++++++++++++++++
49 arch/arm/plat-omap/include/mach/nand.h | 24
50 arch/arm/plat-omap/include/mach/omap-alsa.h | 123 ++++
51 arch/arm/plat-omap/include/mach/omap-pm.h | 301 ++++++++++
52 arch/arm/plat-omap/include/mach/omap1510.h | 50 +
53 arch/arm/plat-omap/include/mach/omap16xx.h | 202 ++++++
54 arch/arm/plat-omap/include/mach/omap24xx.h | 89 ++
55 arch/arm/plat-omap/include/mach/omap34xx.h | 86 ++
56 arch/arm/plat-omap/include/mach/omap44xx.h | 48 +
57 arch/arm/plat-omap/include/mach/omap730.h | 102 +++
58 arch/arm/plat-omap/include/mach/omap7xx.h | 104 +++
59 arch/arm/plat-omap/include/mach/omap850.h | 102 +++
60 arch/arm/plat-omap/include/mach/omap_device.h | 143 ++++
61 arch/arm/plat-omap/include/mach/omap_hwmod.h | 467 +++++++++++++++
62 arch/arm/plat-omap/include/mach/onenand.h | 43 +
63 arch/arm/plat-omap/include/mach/param.h | 8
64 arch/arm/plat-omap/include/mach/powerdomain.h | 187 ++++++
65 arch/arm/plat-omap/include/mach/prcm.h | 39 +
66 arch/arm/plat-omap/include/mach/sdrc.h | 158 +++++
67 arch/arm/plat-omap/include/mach/serial.h | 65 ++
68 arch/arm/plat-omap/include/mach/smp.h | 53 +
69 arch/arm/plat-omap/include/mach/sram.h | 78 ++
70 arch/arm/plat-omap/include/mach/system.h | 51 +
71 arch/arm/plat-omap/include/mach/tc.h | 106 +++
72 arch/arm/plat-omap/include/mach/timer-gp.h | 17
73 arch/arm/plat-omap/include/mach/timex.h | 41 +
74 arch/arm/plat-omap/include/mach/uncompress.h | 88 ++
75 arch/arm/plat-omap/include/mach/usb.h | 162 +++++
76 arch/arm/plat-omap/include/mach/vram.h | 62 ++
77 arch/arm/plat-omap/include/mach/vrfb.h | 50 +
78 arch/arm/plat-omap/include/plat/cbus.h | 31 +
79 77 files changed, 10001 insertions(+)
80
81 --- /dev/null
82 +++ linux-2.6.36-rc4/arch/arm/plat-omap/bootreason.c
83 @@ -0,0 +1,79 @@
84 +/*
85 + * linux/arch/arm/plat-omap/bootreason.c
86 + *
87 + * OMAP Bootreason passing
88 + *
89 + * Copyright (c) 2004 Nokia
90 + *
91 + * Written by David Weinehall <david.weinehall@nokia.com>
92 + *
93 + * This program is free software; you can redistribute it and/or modify it
94 + * under the terms of the GNU General Public License as published by the
95 + * Free Software Foundation; either version 2 of the License, or (at your
96 + * option) any later version.
97 + *
98 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
99 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
100 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
101 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
102 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
103 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
104 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
105 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
106 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
107 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
108 + *
109 + * You should have received a copy of the GNU General Public License along
110 + * with this program; if not, write to the Free Software Foundation, Inc.,
111 + * 675 Mass Ave, Cambridge, MA 02139, USA.
112 + */
113 +#include <linux/proc_fs.h>
114 +#include <linux/errno.h>
115 +#include <plat/board.h>
116 +
117 +static char boot_reason[16];
118 +
119 +static int omap_bootreason_read_proc(char *page, char **start, off_t off,
120 + int count, int *eof, void *data)
121 +{
122 + int len = 0;
123 +
124 + len += sprintf(page + len, "%s\n", boot_reason);
125 +
126 + *start = page + off;
127 +
128 + if (len > off)
129 + len -= off;
130 + else
131 + len = 0;
132 +
133 + return len < count ? len : count;
134 +}
135 +
136 +static int __init bootreason_init(void)
137 +{
138 + const struct omap_boot_reason_config *cfg;
139 + int reason_valid = 0;
140 +
141 + cfg = omap_get_config(OMAP_TAG_BOOT_REASON, struct omap_boot_reason_config);
142 + if (cfg != NULL) {
143 + strncpy(boot_reason, cfg->reason_str, sizeof(cfg->reason_str));
144 + boot_reason[sizeof(cfg->reason_str)] = 0;
145 + reason_valid = 1;
146 + } else {
147 + /* Read the boot reason from the OMAP registers */
148 + }
149 +
150 + if (!reason_valid)
151 + return -ENOENT;
152 +
153 + printk(KERN_INFO "Bootup reason: %s\n", boot_reason);
154 +
155 + if (!create_proc_read_entry("bootreason", S_IRUGO, NULL,
156 + omap_bootreason_read_proc, NULL))
157 + return -ENOMEM;
158 +
159 + return 0;
160 +}
161 +
162 +late_initcall(bootreason_init);
163 --- linux-2.6.36-rc4.orig/arch/arm/plat-omap/common.c
164 +++ linux-2.6.36-rc4/arch/arm/plat-omap/common.c
165 @@ -49,11 +49,81 @@
166 struct omap_board_config_kernel *omap_board_config;
167 int omap_board_config_size;
168
169 +unsigned char omap_bootloader_tag[1024];
170 +int omap_bootloader_tag_len;
171 +
172 +/* used by omap-smp.c and board-4430sdp.c */
173 +void __iomem *gic_cpu_base_addr;
174 +
175 +#ifdef CONFIG_OMAP_BOOT_TAG
176 +
177 +static int __init parse_tag_omap(const struct tag *tag)
178 +{
179 + u32 size = tag->hdr.size - (sizeof(tag->hdr) >> 2);
180 +
181 + size <<= 2;
182 + if (size > sizeof(omap_bootloader_tag))
183 + return -1;
184 +
185 + memcpy(omap_bootloader_tag, tag->u.omap.data, size);
186 + omap_bootloader_tag_len = size;
187 +
188 + return 0;
189 +}
190 +
191 +__tagtable(ATAG_BOARD, parse_tag_omap);
192 +
193 +#endif
194 +
195 static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
196 {
197 struct omap_board_config_kernel *kinfo = NULL;
198 int i;
199
200 +#ifdef CONFIG_OMAP_BOOT_TAG
201 + struct omap_board_config_entry *info = NULL;
202 +
203 + if (omap_bootloader_tag_len > 4)
204 + info = (struct omap_board_config_entry *) omap_bootloader_tag;
205 + while (info != NULL) {
206 + u8 *next;
207 +
208 + if (info->tag == tag) {
209 + if (skip == 0)
210 + break;
211 + skip--;
212 + }
213 +
214 + if ((info->len & 0x03) != 0) {
215 + /* We bail out to avoid an alignment fault */
216 + printk(KERN_ERR "OMAP peripheral config: Length (%d) not word-aligned (tag %04x)\n",
217 + info->len, info->tag);
218 + return NULL;
219 + }
220 + next = (u8 *) info + sizeof(*info) + info->len;
221 + if (next >= omap_bootloader_tag + omap_bootloader_tag_len)
222 + info = NULL;
223 + else
224 + info = (struct omap_board_config_entry *) next;
225 + }
226 + if (info != NULL) {
227 + /* Check the length as a lame attempt to check for
228 + * binary inconsistency. */
229 + if (len != NO_LENGTH_CHECK) {
230 + /* Word-align len */
231 + if (len & 0x03)
232 + len = (len + 3) & ~0x03;
233 + if (info->len != len) {
234 + printk(KERN_ERR "OMAP peripheral config: Length mismatch with tag %x (want %d, got %d)\n",
235 + tag, len, info->len);
236 + return NULL;
237 + }
238 + }
239 + if (len_out != NULL)
240 + *len_out = info->len;
241 + return info->data;
242 + }
243 +#endif
244 /* Try to find the config from the board-specific structures
245 * in the kernel. */
246 for (i = 0; i < omap_board_config_size; i++) {
247 --- /dev/null
248 +++ linux-2.6.36-rc4/arch/arm/plat-omap/component-version.c
249 @@ -0,0 +1,64 @@
250 +/*
251 + * linux/arch/arm/plat-omap/component-version.c
252 + *
253 + * Copyright (C) 2005 Nokia Corporation
254 + * Written by Juha Yrjölä <juha.yrjola@nokia.com>
255 + *
256 + * This program is free software; you can redistribute it and/or modify
257 + * it under the terms of the GNU General Public License version 2 as
258 + * published by the Free Software Foundation.
259 + */
260 +
261 +#include <linux/init.h>
262 +#include <linux/module.h>
263 +#include <linux/err.h>
264 +#include <linux/proc_fs.h>
265 +#include <plat/board.h>
266 +
267 +static int component_version_read_proc(char *page, char **start, off_t off,
268 + int count, int *eof, void *data)
269 +{
270 + int len, i;
271 + const struct omap_version_config *ver;
272 + char *p;
273 +
274 + i = 0;
275 + p = page;
276 + while ((ver = omap_get_nr_config(OMAP_TAG_VERSION_STR,
277 + struct omap_version_config, i)) != NULL) {
278 + p += sprintf(p, "%-12s%s\n", ver->component, ver->version);
279 + i++;
280 + }
281 +
282 + len = (p - page) - off;
283 + if (len < 0)
284 + len = 0;
285 +
286 + *eof = (len <= count) ? 1 : 0;
287 + *start = page + off;
288 +
289 + return len;
290 +}
291 +
292 +static int __init component_version_init(void)
293 +{
294 + if (omap_get_config(OMAP_TAG_VERSION_STR, struct omap_version_config) == NULL)
295 + return -ENODEV;
296 + if (!create_proc_read_entry("component_version", S_IRUGO, NULL,
297 + component_version_read_proc, NULL))
298 + return -ENOMEM;
299 +
300 + return 0;
301 +}
302 +
303 +static void __exit component_version_exit(void)
304 +{
305 + remove_proc_entry("component_version", NULL);
306 +}
307 +
308 +late_initcall(component_version_init);
309 +module_exit(component_version_exit);
310 +
311 +MODULE_AUTHOR("Juha Yrjölä <juha.yrjola@nokia.com>");
312 +MODULE_DESCRIPTION("Component version driver");
313 +MODULE_LICENSE("GPL");
314 --- /dev/null
315 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/blizzard.h
316 @@ -0,0 +1,12 @@
317 +#ifndef _BLIZZARD_H
318 +#define _BLIZZARD_H
319 +
320 +struct blizzard_platform_data {
321 + void (*power_up)(struct device *dev);
322 + void (*power_down)(struct device *dev);
323 + unsigned long (*get_clock_rate)(struct device *dev);
324 +
325 + unsigned te_connected : 1;
326 +};
327 +
328 +#endif
329 --- /dev/null
330 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/board-ams-delta.h
331 @@ -0,0 +1,76 @@
332 +/*
333 + * arch/arm/plat-omap/include/mach/board-ams-delta.h
334 + *
335 + * Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
336 + *
337 + * This program is free software; you can redistribute it and/or modify it
338 + * under the terms of the GNU General Public License as published by the
339 + * Free Software Foundation; either version 2 of the License, or (at your
340 + * option) any later version.
341 + *
342 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
343 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
344 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
345 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
346 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
347 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
348 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
349 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
350 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
351 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
352 + *
353 + * You should have received a copy of the GNU General Public License along
354 + * with this program; if not, write to the Free Software Foundation, Inc.,
355 + * 675 Mass Ave, Cambridge, MA 02139, USA.
356 + */
357 +#ifndef __ASM_ARCH_OMAP_AMS_DELTA_H
358 +#define __ASM_ARCH_OMAP_AMS_DELTA_H
359 +
360 +#if defined (CONFIG_MACH_AMS_DELTA)
361 +
362 +#define AMS_DELTA_LATCH1_PHYS 0x01000000
363 +#define AMS_DELTA_LATCH1_VIRT 0xEA000000
364 +#define AMS_DELTA_MODEM_PHYS 0x04000000
365 +#define AMS_DELTA_MODEM_VIRT 0xEB000000
366 +#define AMS_DELTA_LATCH2_PHYS 0x08000000
367 +#define AMS_DELTA_LATCH2_VIRT 0xEC000000
368 +
369 +#define AMS_DELTA_LATCH1_LED_CAMERA 0x01
370 +#define AMS_DELTA_LATCH1_LED_ADVERT 0x02
371 +#define AMS_DELTA_LATCH1_LED_EMAIL 0x04
372 +#define AMS_DELTA_LATCH1_LED_HANDSFREE 0x08
373 +#define AMS_DELTA_LATCH1_LED_VOICEMAIL 0x10
374 +#define AMS_DELTA_LATCH1_LED_VOICE 0x20
375 +
376 +#define AMS_DELTA_LATCH2_LCD_VBLEN 0x0001
377 +#define AMS_DELTA_LATCH2_LCD_NDISP 0x0002
378 +#define AMS_DELTA_LATCH2_NAND_NCE 0x0004
379 +#define AMS_DELTA_LATCH2_NAND_NRE 0x0008
380 +#define AMS_DELTA_LATCH2_NAND_NWP 0x0010
381 +#define AMS_DELTA_LATCH2_NAND_NWE 0x0020
382 +#define AMS_DELTA_LATCH2_NAND_ALE 0x0040
383 +#define AMS_DELTA_LATCH2_NAND_CLE 0x0080
384 +#define AMD_DELTA_LATCH2_KEYBRD_PWR 0x0100
385 +#define AMD_DELTA_LATCH2_KEYBRD_DATA 0x0200
386 +#define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400
387 +#define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800
388 +#define AMS_DELTA_LATCH2_MODEM_NRESET 0x1000
389 +#define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000
390 +
391 +#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0
392 +#define AMS_DELTA_GPIO_PIN_KEYBRD_CLK 1
393 +#define AMS_DELTA_GPIO_PIN_MODEM_IRQ 2
394 +#define AMS_DELTA_GPIO_PIN_HOOK_SWITCH 4
395 +#define AMS_DELTA_GPIO_PIN_SCARD_NOFF 6
396 +#define AMS_DELTA_GPIO_PIN_SCARD_IO 7
397 +#define AMS_DELTA_GPIO_PIN_CONFIG 11
398 +#define AMS_DELTA_GPIO_PIN_NAND_RB 12
399 +
400 +#ifndef __ASSEMBLY__
401 +void ams_delta_latch1_write(u8 mask, u8 value);
402 +void ams_delta_latch2_write(u16 mask, u16 value);
403 +#endif
404 +
405 +#endif /* CONFIG_MACH_AMS_DELTA */
406 +
407 +#endif /* __ASM_ARCH_OMAP_AMS_DELTA_H */
408 --- /dev/null
409 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/board.h
410 @@ -0,0 +1,169 @@
411 +/*
412 + * arch/arm/plat-omap/include/mach/board.h
413 + *
414 + * Information structures for board-specific data
415 + *
416 + * Copyright (C) 2004 Nokia Corporation
417 + * Written by Juha Yrjölä <juha.yrjola@nokia.com>
418 + */
419 +
420 +#ifndef _OMAP_BOARD_H
421 +#define _OMAP_BOARD_H
422 +
423 +#include <linux/types.h>
424 +
425 +#include <plat/gpio-switch.h>
426 +
427 +/*
428 + * OMAP35x EVM revision
429 + * Run time detection of EVM revision is done by reading Ethernet
430 + * PHY ID -
431 + * GEN_1 = 0x01150000
432 + * GEN_2 = 0x92200000
433 + */
434 +enum {
435 + OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */
436 + OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */
437 +};
438 +
439 +/* Different peripheral ids */
440 +#define OMAP_TAG_CLOCK 0x4f01
441 +#define OMAP_TAG_LCD 0x4f05
442 +#define OMAP_TAG_GPIO_SWITCH 0x4f06
443 +#define OMAP_TAG_FBMEM 0x4f08
444 +#define OMAP_TAG_STI_CONSOLE 0x4f09
445 +#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
446 +
447 +#define OMAP_TAG_BOOT_REASON 0x4f80
448 +#define OMAP_TAG_FLASH_PART 0x4f81
449 +#define OMAP_TAG_VERSION_STR 0x4f82
450 +
451 +struct omap_clock_config {
452 + /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
453 + u8 system_clock_type;
454 +};
455 +
456 +struct omap_serial_console_config {
457 + u8 console_uart;
458 + u32 console_speed;
459 +};
460 +
461 +struct omap_sti_console_config {
462 + unsigned enable:1;
463 + u8 channel;
464 +};
465 +
466 +struct omap_camera_sensor_config {
467 + u16 reset_gpio;
468 + int (*power_on)(void * data);
469 + int (*power_off)(void * data);
470 +};
471 +
472 +struct omap_usb_config {
473 + /* Configure drivers according to the connectors on your board:
474 + * - "A" connector (rectagular)
475 + * ... for host/OHCI use, set "register_host".
476 + * - "B" connector (squarish) or "Mini-B"
477 + * ... for device/gadget use, set "register_dev".
478 + * - "Mini-AB" connector (very similar to Mini-B)
479 + * ... for OTG use as device OR host, initialize "otg"
480 + */
481 + unsigned register_host:1;
482 + unsigned register_dev:1;
483 + u8 otg; /* port number, 1-based: usb1 == 2 */
484 +
485 + u8 hmc_mode;
486 +
487 + /* implicitly true if otg: host supports remote wakeup? */
488 + u8 rwc;
489 +
490 + /* signaling pins used to talk to transceiver on usbN:
491 + * 0 == usbN unused
492 + * 2 == usb0-only, using internal transceiver
493 + * 3 == 3 wire bidirectional
494 + * 4 == 4 wire bidirectional
495 + * 6 == 6 wire unidirectional (or TLL)
496 + */
497 + u8 pins[3];
498 +};
499 +
500 +struct omap_lcd_config {
501 + char panel_name[16];
502 + char ctrl_name[16];
503 + s16 nreset_gpio;
504 + u8 data_lines;
505 +};
506 +
507 +struct device;
508 +struct fb_info;
509 +struct omap_backlight_config {
510 + int default_intensity;
511 + int (*set_power)(struct device *dev, int state);
512 + int (*check_fb)(struct fb_info *fb);
513 +};
514 +
515 +struct omap_fbmem_config {
516 + u32 start;
517 + u32 size;
518 +};
519 +
520 +struct omap_pwm_led_platform_data {
521 + const char *name;
522 + int intensity_timer;
523 + int blink_timer;
524 + void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
525 +};
526 +
527 +struct omap_uart_config {
528 + /* Bit field of UARTs present; bit 0 --> UART1 */
529 + unsigned int enabled_uarts;
530 +};
531 +
532 +
533 +struct omap_flash_part_config {
534 + char part_table[0];
535 +};
536 +
537 +struct omap_boot_reason_config {
538 + char reason_str[12];
539 +};
540 +
541 +struct omap_version_config {
542 + char component[12];
543 + char version[12];
544 +};
545 +
546 +struct omap_board_config_entry {
547 + u16 tag;
548 + u16 len;
549 + u8 data[0];
550 +};
551 +
552 +struct omap_board_config_kernel {
553 + u16 tag;
554 + const void *data;
555 +};
556 +
557 +extern const void *__omap_get_config(u16 tag, size_t len, int nr);
558 +
559 +#define omap_get_config(tag, type) \
560 + ((const type *) __omap_get_config((tag), sizeof(type), 0))
561 +#define omap_get_nr_config(tag, type, nr) \
562 + ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
563 +
564 +extern const void *omap_get_var_config(u16 tag, size_t *len);
565 +
566 +extern struct omap_board_config_kernel *omap_board_config;
567 +extern int omap_board_config_size;
568 +
569 +
570 +/* for TI reference platforms sharing the same debug card */
571 +extern int debug_card_init(u32 addr, unsigned gpio);
572 +
573 +/* OMAP3EVM revision */
574 +#if defined(CONFIG_MACH_OMAP3EVM)
575 +u8 get_omap3_evm_rev(void);
576 +#else
577 +#define get_omap3_evm_rev() (-EINVAL)
578 +#endif
579 +#endif
580 --- /dev/null
581 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/board-sx1.h
582 @@ -0,0 +1,52 @@
583 +/*
584 + * Siemens SX1 board definitions
585 + *
586 + * Copyright: Vovan888 at gmail com
587 + *
588 + * This package is free software; you can redistribute it and/or modify
589 + * it under the terms of the GNU General Public License version 2 as
590 + * published by the Free Software Foundation.
591 + *
592 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
593 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
594 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
595 + */
596 +
597 +#ifndef __ASM_ARCH_SX1_I2C_CHIPS_H
598 +#define __ASM_ARCH_SX1_I2C_CHIPS_H
599 +
600 +#define SOFIA_MAX_LIGHT_VAL 0x2B
601 +
602 +#define SOFIA_I2C_ADDR 0x32
603 +/* Sofia reg 3 bits masks */
604 +#define SOFIA_POWER1_REG 0x03
605 +
606 +#define SOFIA_USB_POWER 0x01
607 +#define SOFIA_MMC_POWER 0x04
608 +#define SOFIA_BLUETOOTH_POWER 0x08
609 +#define SOFIA_MMILIGHT_POWER 0x20
610 +
611 +#define SOFIA_POWER2_REG 0x04
612 +#define SOFIA_BACKLIGHT_REG 0x06
613 +#define SOFIA_KEYLIGHT_REG 0x07
614 +#define SOFIA_DIMMING_REG 0x09
615 +
616 +
617 +/* Function Prototypes for SX1 devices control on I2C bus */
618 +
619 +int sx1_setbacklight(u8 backlight);
620 +int sx1_getbacklight(u8 *backlight);
621 +int sx1_setkeylight(u8 keylight);
622 +int sx1_getkeylight(u8 *keylight);
623 +
624 +int sx1_setmmipower(u8 onoff);
625 +int sx1_setusbpower(u8 onoff);
626 +int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value);
627 +int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value);
628 +
629 +/* MMC prototypes */
630 +
631 +extern void sx1_mmc_init(void);
632 +extern void sx1_mmc_slot_cover_handler(void *arg, int state);
633 +
634 +#endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */
635 --- /dev/null
636 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/board-voiceblue.h
637 @@ -0,0 +1,19 @@
638 +/*
639 + * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
640 + *
641 + * Hardware definitions for OMAP5910 based VoiceBlue board.
642 + *
643 + * This program is free software; you can redistribute it and/or modify
644 + * it under the terms of the GNU General Public License version 2 as
645 + * published by the Free Software Foundation.
646 + */
647 +
648 +#ifndef __ASM_ARCH_VOICEBLUE_H
649 +#define __ASM_ARCH_VOICEBLUE_H
650 +
651 +extern void voiceblue_wdt_enable(void);
652 +extern void voiceblue_wdt_disable(void);
653 +extern void voiceblue_wdt_ping(void);
654 +
655 +#endif /* __ASM_ARCH_VOICEBLUE_H */
656 +
657 --- /dev/null
658 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/cbus.h
659 @@ -0,0 +1,31 @@
660 +/*
661 + * cbus.h - CBUS platform_data definition
662 + *
663 + * Copyright (C) 2004 - 2009 Nokia Corporation
664 + *
665 + * Written by Felipe Balbi <felipe.balbi@nokia.com>
666 + *
667 + * This file is subject to the terms and conditions of the GNU General
668 + * Public License. See the file "COPYING" in the main directory of this
669 + * archive for more details.
670 + *
671 + * This program is distributed in the hope that it will be useful,
672 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
673 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
674 + * GNU General Public License for more details.
675 + *
676 + * You should have received a copy of the GNU General Public License
677 + * along with this program; if not, write to the Free Software
678 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
679 + */
680 +
681 +#ifndef __PLAT_CBUS_H
682 +#define __PLAT_CBUS_H
683 +
684 +struct cbus_host_platform_data {
685 + int dat_gpio;
686 + int clk_gpio;
687 + int sel_gpio;
688 +};
689 +
690 +#endif /* __PLAT_CBUS_H */
691 --- /dev/null
692 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/clkdev.h
693 @@ -0,0 +1,13 @@
694 +#ifndef __MACH_CLKDEV_H
695 +#define __MACH_CLKDEV_H
696 +
697 +static inline int __clk_get(struct clk *clk)
698 +{
699 + return 1;
700 +}
701 +
702 +static inline void __clk_put(struct clk *clk)
703 +{
704 +}
705 +
706 +#endif
707 --- /dev/null
708 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/clkdev_omap.h
709 @@ -0,0 +1,41 @@
710 +/*
711 + * clkdev <-> OMAP integration
712 + *
713 + * Russell King <linux@arm.linux.org.uk>
714 + *
715 + */
716 +
717 +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
718 +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
719 +
720 +#include <asm/clkdev.h>
721 +
722 +struct omap_clk {
723 + u16 cpu;
724 + struct clk_lookup lk;
725 +};
726 +
727 +#define CLK(dev, con, ck, cp) \
728 + { \
729 + .cpu = cp, \
730 + .lk = { \
731 + .dev_id = dev, \
732 + .con_id = con, \
733 + .clk = ck, \
734 + }, \
735 + }
736 +
737 +
738 +#define CK_310 (1 << 0)
739 +#define CK_7XX (1 << 1)
740 +#define CK_1510 (1 << 2)
741 +#define CK_16XX (1 << 3)
742 +#define CK_243X (1 << 4)
743 +#define CK_242X (1 << 5)
744 +#define CK_343X (1 << 6)
745 +#define CK_3430ES1 (1 << 7)
746 +#define CK_3430ES2 (1 << 8)
747 +#define CK_443X (1 << 9)
748 +
749 +#endif
750 +
751 --- /dev/null
752 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/clockdomain.h
753 @@ -0,0 +1,111 @@
754 +/*
755 + * arch/arm/plat-omap/include/mach/clockdomain.h
756 + *
757 + * OMAP2/3 clockdomain framework functions
758 + *
759 + * Copyright (C) 2008 Texas Instruments, Inc.
760 + * Copyright (C) 2008 Nokia Corporation
761 + *
762 + * Written by Paul Walmsley
763 + *
764 + * This program is free software; you can redistribute it and/or modify
765 + * it under the terms of the GNU General Public License version 2 as
766 + * published by the Free Software Foundation.
767 + */
768 +
769 +#ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
770 +#define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
771 +
772 +#include <plat/powerdomain.h>
773 +#include <plat/clock.h>
774 +#include <plat/cpu.h>
775 +
776 +/* Clockdomain capability flags */
777 +#define CLKDM_CAN_FORCE_SLEEP (1 << 0)
778 +#define CLKDM_CAN_FORCE_WAKEUP (1 << 1)
779 +#define CLKDM_CAN_ENABLE_AUTO (1 << 2)
780 +#define CLKDM_CAN_DISABLE_AUTO (1 << 3)
781 +
782 +#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
783 +#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
784 +#define CLKDM_CAN_HWSUP_SWSUP (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP)
785 +
786 +/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
787 +#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
788 +#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
789 +
790 +/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
791 +#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0
792 +#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1
793 +#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2
794 +#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3
795 +
796 +/*
797 + * struct clkdm_pwrdm_autodep - a powerdomain that should have wkdeps
798 + * and sleepdeps added when a powerdomain should stay active in hwsup mode;
799 + * and conversely, removed when the powerdomain should be allowed to go
800 + * inactive in hwsup mode.
801 + */
802 +struct clkdm_pwrdm_autodep {
803 +
804 + union {
805 + /* Name of the powerdomain to add a wkdep/sleepdep on */
806 + const char *name;
807 +
808 + /* Powerdomain pointer (looked up at clkdm_init() time) */
809 + struct powerdomain *ptr;
810 + } pwrdm;
811 +
812 + /* OMAP chip types that this clockdomain dep is valid on */
813 + const struct omap_chip_id omap_chip;
814 +
815 +};
816 +
817 +struct clockdomain {
818 +
819 + /* Clockdomain name */
820 + const char *name;
821 +
822 + union {
823 + /* Powerdomain enclosing this clockdomain */
824 + const char *name;
825 +
826 + /* Powerdomain pointer assigned at clkdm_register() */
827 + struct powerdomain *ptr;
828 + } pwrdm;
829 +
830 + /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */
831 + const u16 clktrctrl_mask;
832 +
833 + /* Clockdomain capability flags */
834 + const u8 flags;
835 +
836 + /* OMAP chip types that this clockdomain is valid on */
837 + const struct omap_chip_id omap_chip;
838 +
839 + /* Usecount tracking */
840 + atomic_t usecount;
841 +
842 + struct list_head node;
843 +
844 +};
845 +
846 +void clkdm_init(struct clockdomain **clkdms, struct clkdm_pwrdm_autodep *autodeps);
847 +int clkdm_register(struct clockdomain *clkdm);
848 +int clkdm_unregister(struct clockdomain *clkdm);
849 +struct clockdomain *clkdm_lookup(const char *name);
850 +
851 +int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
852 + void *user);
853 +struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
854 +
855 +void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
856 +void omap2_clkdm_deny_idle(struct clockdomain *clkdm);
857 +
858 +int omap2_clkdm_wakeup(struct clockdomain *clkdm);
859 +int omap2_clkdm_sleep(struct clockdomain *clkdm);
860 +
861 +int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
862 +int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
863 +
864 +#endif
865 --- /dev/null
866 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/clock.h
867 @@ -0,0 +1,168 @@
868 +/*
869 + * arch/arm/plat-omap/include/mach/clock.h
870 + *
871 + * Copyright (C) 2004 - 2005 Nokia corporation
872 + * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
873 + * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
874 + *
875 + * This program is free software; you can redistribute it and/or modify
876 + * it under the terms of the GNU General Public License version 2 as
877 + * published by the Free Software Foundation.
878 + */
879 +
880 +#ifndef __ARCH_ARM_OMAP_CLOCK_H
881 +#define __ARCH_ARM_OMAP_CLOCK_H
882 +
883 +#include <linux/list.h>
884 +
885 +struct module;
886 +struct clk;
887 +struct clockdomain;
888 +
889 +struct clkops {
890 + int (*enable)(struct clk *);
891 + void (*disable)(struct clk *);
892 + void (*find_idlest)(struct clk *, void __iomem **, u8 *);
893 + void (*find_companion)(struct clk *, void __iomem **, u8 *);
894 +};
895 +
896 +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
897 + defined(CONFIG_ARCH_OMAP4)
898 +
899 +struct clksel_rate {
900 + u32 val;
901 + u8 div;
902 + u8 flags;
903 +};
904 +
905 +struct clksel {
906 + struct clk *parent;
907 + const struct clksel_rate *rates;
908 +};
909 +
910 +struct dpll_data {
911 + void __iomem *mult_div1_reg;
912 + u32 mult_mask;
913 + u32 div1_mask;
914 + struct clk *clk_bypass;
915 + struct clk *clk_ref;
916 + void __iomem *control_reg;
917 + u32 enable_mask;
918 + unsigned int rate_tolerance;
919 + unsigned long last_rounded_rate;
920 + u16 last_rounded_m;
921 + u8 last_rounded_n;
922 + u8 min_divider;
923 + u8 max_divider;
924 + u32 max_tolerance;
925 + u16 max_multiplier;
926 +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
927 + u8 modes;
928 + void __iomem *autoidle_reg;
929 + void __iomem *idlest_reg;
930 + u32 autoidle_mask;
931 + u32 freqsel_mask;
932 + u32 idlest_mask;
933 + u8 auto_recal_bit;
934 + u8 recal_en_bit;
935 + u8 recal_st_bit;
936 +# endif
937 +};
938 +
939 +#endif
940 +
941 +struct clk {
942 + struct list_head node;
943 + const struct clkops *ops;
944 + const char *name;
945 + int id;
946 + struct clk *parent;
947 + struct list_head children;
948 + struct list_head sibling; /* node for children */
949 + unsigned long rate;
950 + __u32 flags;
951 + void __iomem *enable_reg;
952 + unsigned long (*recalc)(struct clk *);
953 + int (*set_rate)(struct clk *, unsigned long);
954 + long (*round_rate)(struct clk *, unsigned long);
955 + void (*init)(struct clk *);
956 + __u8 enable_bit;
957 + __s8 usecount;
958 +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
959 + defined(CONFIG_ARCH_OMAP4)
960 + u8 fixed_div;
961 + void __iomem *clksel_reg;
962 + u32 clksel_mask;
963 + const struct clksel *clksel;
964 + struct dpll_data *dpll_data;
965 + const char *clkdm_name;
966 + struct clockdomain *clkdm;
967 +#else
968 + __u8 rate_offset;
969 + __u8 src_offset;
970 +#endif
971 +#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
972 + struct dentry *dent; /* For visible tree hierarchy */
973 +#endif
974 +};
975 +
976 +struct cpufreq_frequency_table;
977 +
978 +struct clk_functions {
979 + int (*clk_enable)(struct clk *clk);
980 + void (*clk_disable)(struct clk *clk);
981 + long (*clk_round_rate)(struct clk *clk, unsigned long rate);
982 + int (*clk_set_rate)(struct clk *clk, unsigned long rate);
983 + int (*clk_set_parent)(struct clk *clk, struct clk *parent);
984 + void (*clk_allow_idle)(struct clk *clk);
985 + void (*clk_deny_idle)(struct clk *clk);
986 + void (*clk_disable_unused)(struct clk *clk);
987 +#ifdef CONFIG_CPU_FREQ
988 + void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
989 +#endif
990 +};
991 +
992 +extern unsigned int mpurate;
993 +
994 +extern int clk_init(struct clk_functions *custom_clocks);
995 +extern void clk_preinit(struct clk *clk);
996 +extern int clk_register(struct clk *clk);
997 +extern void clk_reparent(struct clk *child, struct clk *parent);
998 +extern void clk_unregister(struct clk *clk);
999 +extern void propagate_rate(struct clk *clk);
1000 +extern void recalculate_root_clocks(void);
1001 +extern unsigned long followparent_recalc(struct clk *clk);
1002 +extern void clk_enable_init_clocks(void);
1003 +#ifdef CONFIG_CPU_FREQ
1004 +extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
1005 +#endif
1006 +
1007 +extern const struct clkops clkops_null;
1008 +
1009 +/* Clock flags */
1010 +/* bit 0 is free */
1011 +#define RATE_FIXED (1 << 1) /* Fixed clock rate */
1012 +/* bits 2-4 are free */
1013 +#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */
1014 +#define CLOCK_IDLE_CONTROL (1 << 7)
1015 +#define CLOCK_NO_IDLE_PARENT (1 << 8)
1016 +#define DELAYED_APP (1 << 9) /* Delay application of clock */
1017 +#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
1018 +#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
1019 +#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
1020 +#define CLOCK_IN_OMAP4430 (1 << 13)
1021 +#define ALWAYS_ENABLED (1 << 14)
1022 +/* bits 13-31 are currently free */
1023 +
1024 +/* Clksel_rate flags */
1025 +#define DEFAULT_RATE (1 << 0)
1026 +#define RATE_IN_242X (1 << 1)
1027 +#define RATE_IN_243X (1 << 2)
1028 +#define RATE_IN_343X (1 << 3) /* rates common to all 343X */
1029 +#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
1030 +#define RATE_IN_4430 (1 << 5)
1031 +
1032 +#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
1033 +
1034 +
1035 +#endif
1036 --- /dev/null
1037 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/common.h
1038 @@ -0,0 +1,83 @@
1039 +/*
1040 + * arch/arm/plat-omap/include/mach/common.h
1041 + *
1042 + * Header for code common to all OMAP machines.
1043 + *
1044 + * This program is free software; you can redistribute it and/or modify it
1045 + * under the terms of the GNU General Public License as published by the
1046 + * Free Software Foundation; either version 2 of the License, or (at your
1047 + * option) any later version.
1048 + *
1049 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1050 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1051 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1052 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1053 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1054 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1055 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1056 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1057 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1058 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1059 + *
1060 + * You should have received a copy of the GNU General Public License along
1061 + * with this program; if not, write to the Free Software Foundation, Inc.,
1062 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1063 + */
1064 +
1065 +#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
1066 +#define __ARCH_ARM_MACH_OMAP_COMMON_H
1067 +
1068 +#include <plat/i2c.h>
1069 +
1070 +struct sys_timer;
1071 +
1072 +/* used by omap-smp.c and board-4430sdp.c */
1073 +extern void __iomem *gic_cpu_base_addr;
1074 +
1075 +extern void omap_map_common_io(void);
1076 +extern struct sys_timer omap_timer;
1077 +
1078 +/* IO bases for various OMAP processors */
1079 +struct omap_globals {
1080 + u32 class; /* OMAP class to detect */
1081 + void __iomem *tap; /* Control module ID code */
1082 + void __iomem *sdrc; /* SDRAM Controller */
1083 + void __iomem *sms; /* SDRAM Memory Scheduler */
1084 + void __iomem *ctrl; /* System Control Module */
1085 + void __iomem *prm; /* Power and Reset Management */
1086 + void __iomem *cm; /* Clock Management */
1087 + void __iomem *cm2;
1088 +};
1089 +
1090 +void omap2_set_globals_242x(void);
1091 +void omap2_set_globals_243x(void);
1092 +void omap2_set_globals_343x(void);
1093 +void omap2_set_globals_443x(void);
1094 +
1095 +/* These get called from omap2_set_globals_xxxx(), do not call these */
1096 +void omap2_set_globals_tap(struct omap_globals *);
1097 +void omap2_set_globals_sdrc(struct omap_globals *);
1098 +void omap2_set_globals_control(struct omap_globals *);
1099 +void omap2_set_globals_prcm(struct omap_globals *);
1100 +
1101 +/**
1102 + * omap_test_timeout - busy-loop, testing a condition
1103 + * @cond: condition to test until it evaluates to true
1104 + * @timeout: maximum number of microseconds in the timeout
1105 + * @index: loop index (integer)
1106 + *
1107 + * Loop waiting for @cond to become true or until at least @timeout
1108 + * microseconds have passed. To use, define some integer @index in the
1109 + * calling code. After running, if @index == @timeout, then the loop has
1110 + * timed out.
1111 + */
1112 +#define omap_test_timeout(cond, timeout, index) \
1113 +({ \
1114 + for (index = 0; index < timeout; index++) { \
1115 + if (cond) \
1116 + break; \
1117 + udelay(1); \
1118 + } \
1119 +})
1120 +
1121 +#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
1122 --- /dev/null
1123 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/control.h
1124 @@ -0,0 +1,325 @@
1125 +/*
1126 + * arch/arm/plat-omap/include/mach/control.h
1127 + *
1128 + * OMAP2/3/4 System Control Module definitions
1129 + *
1130 + * Copyright (C) 2007-2009 Texas Instruments, Inc.
1131 + * Copyright (C) 2007-2008 Nokia Corporation
1132 + *
1133 + * Written by Paul Walmsley
1134 + *
1135 + * This program is free software; you can redistribute it and/or modify
1136 + * it under the terms of the GNU General Public License as published by
1137 + * the Free Software Foundation.
1138 + */
1139 +
1140 +#ifndef __ASM_ARCH_CONTROL_H
1141 +#define __ASM_ARCH_CONTROL_H
1142 +
1143 +#include <mach/io.h>
1144 +
1145 +#ifndef __ASSEMBLY__
1146 +#define OMAP242X_CTRL_REGADDR(reg) \
1147 + OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
1148 +#define OMAP243X_CTRL_REGADDR(reg) \
1149 + OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
1150 +#define OMAP343X_CTRL_REGADDR(reg) \
1151 + OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
1152 +#else
1153 +#define OMAP242X_CTRL_REGADDR(reg) \
1154 + OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
1155 +#define OMAP243X_CTRL_REGADDR(reg) \
1156 + OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
1157 +#define OMAP343X_CTRL_REGADDR(reg) \
1158 + OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
1159 +#endif /* __ASSEMBLY__ */
1160 +
1161 +/*
1162 + * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
1163 + * OMAP24XX and OMAP34XX.
1164 + */
1165 +
1166 +/* Control submodule offsets */
1167 +
1168 +#define OMAP2_CONTROL_INTERFACE 0x000
1169 +#define OMAP2_CONTROL_PADCONFS 0x030
1170 +#define OMAP2_CONTROL_GENERAL 0x270
1171 +#define OMAP343X_CONTROL_MEM_WKUP 0x600
1172 +#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
1173 +#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
1174 +
1175 +/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
1176 +
1177 +#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
1178 +
1179 +/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
1180 +#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004)
1181 +#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020)
1182 +#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024)
1183 +#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028)
1184 +#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c)
1185 +#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030)
1186 +#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034)
1187 +#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040)
1188 +#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090)
1189 +#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094)
1190 +#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098)
1191 +#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c)
1192 +
1193 +/* 242x-only CONTROL_GENERAL register offsets */
1194 +#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */
1195 +#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068)
1196 +
1197 +/* 243x-only CONTROL_GENERAL register offsets */
1198 +/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
1199 +#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078)
1200 +#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c)
1201 +#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
1202 +#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
1203 +#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
1204 +#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230)
1205 +
1206 +/* 24xx-only CONTROL_GENERAL register offsets */
1207 +#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
1208 +#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008)
1209 +#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044)
1210 +#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048)
1211 +#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c)
1212 +#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050)
1213 +#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060)
1214 +#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
1215 +#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
1216 +#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
1217 +#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074)
1218 +#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
1219 +#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
1220 +#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)
1221 +#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
1222 +#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
1223 +#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
1224 +#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
1225 +#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
1226 +#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
1227 +#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
1228 +#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
1229 +#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
1230 +#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
1231 +#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
1232 +#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
1233 +#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
1234 +#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
1235 +#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
1236 +#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
1237 +#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
1238 +
1239 +#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
1240 +
1241 +/* 34xx-only CONTROL_GENERAL register offsets */
1242 +#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
1243 +#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
1244 +#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c)
1245 +#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068)
1246 +#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c)
1247 +#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070)
1248 +#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074)
1249 +#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078)
1250 +#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
1251 +#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
1252 +#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0)
1253 +#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8)
1254 +#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac)
1255 +#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0)
1256 +#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4)
1257 +#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8)
1258 +#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc)
1259 +#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0)
1260 +#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4)
1261 +#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8)
1262 +#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc)
1263 +#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0)
1264 +#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4)
1265 +#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8)
1266 +#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec)
1267 +#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0)
1268 +#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4)
1269 +#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8)
1270 +#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
1271 +#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
1272 +#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
1273 +#define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \
1274 + + ((i) >> 1) * 4 + (!(i) & 1) * 2)
1275 +#define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4)
1276 +#define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8)
1277 +#define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0)
1278 +#define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4)
1279 +#define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8)
1280 +#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
1281 +#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0)
1282 +#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4)
1283 +#define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8)
1284 +#define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0)
1285 +#define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4)
1286 +
1287 +
1288 +/* 34xx PADCONF register offsets */
1289 +#define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
1290 + (i)*2)
1291 +#define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0)
1292 +#define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1)
1293 +#define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2)
1294 +#define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3)
1295 +#define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4)
1296 +#define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5)
1297 +#define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6)
1298 +#define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7)
1299 +#define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8)
1300 +#define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9)
1301 +#define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10)
1302 +#define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11)
1303 +#define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12)
1304 +#define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13)
1305 +#define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14)
1306 +#define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15)
1307 +#define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16)
1308 +#define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17)
1309 +
1310 +/* 34xx GENERAL_WKUP regist offsets */
1311 +#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
1312 + 0x008 + (i))
1313 +#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
1314 +#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
1315 +#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
1316 +#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
1317 +#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
1318 +
1319 +/* 34xx D2D idle-related pins, handled by PM core */
1320 +#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
1321 +#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
1322 +
1323 +/*
1324 + * REVISIT: This list of registers is not comprehensive - there are more
1325 + * that should be added.
1326 + */
1327 +
1328 +/*
1329 + * Control module register bit defines - these should eventually go into
1330 + * their own regbits file. Some of these will be complicated, depending
1331 + * on the device type (general-purpose, emulator, test, secure, bad, other)
1332 + * and the security mode (secure, non-secure, don't care)
1333 + */
1334 +/* CONTROL_DEVCONF0 bits */
1335 +#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */
1336 +#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
1337 +#define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
1338 +#define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
1339 +
1340 +/* CONTROL_DEVCONF1 bits */
1341 +#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31)
1342 +#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */
1343 +#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
1344 +#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
1345 +#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */
1346 +
1347 +/* CONTROL_STATUS bits */
1348 +#define OMAP2_DEVICETYPE_MASK (0x7 << 8)
1349 +#define OMAP2_SYSBOOT_5_MASK (1 << 5)
1350 +#define OMAP2_SYSBOOT_4_MASK (1 << 4)
1351 +#define OMAP2_SYSBOOT_3_MASK (1 << 3)
1352 +#define OMAP2_SYSBOOT_2_MASK (1 << 2)
1353 +#define OMAP2_SYSBOOT_1_MASK (1 << 1)
1354 +#define OMAP2_SYSBOOT_0_MASK (1 << 0)
1355 +
1356 +/* CONTROL_PBIAS_LITE bits */
1357 +#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15)
1358 +#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11)
1359 +#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10)
1360 +#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9)
1361 +#define OMAP343X_PBIASLITEVMODE1 (1 << 8)
1362 +#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7)
1363 +#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3)
1364 +#define OMAP2_PBIASSPEEDCTRL0 (1 << 2)
1365 +#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
1366 +#define OMAP2_PBIASLITEVMODE0 (1 << 0)
1367 +
1368 +/* CONTROL_PROG_IO1 bits */
1369 +#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
1370 +
1371 +/* CONTROL_IVA2_BOOTMOD bits */
1372 +#define OMAP3_IVA2_BOOTMOD_SHIFT 0
1373 +#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
1374 +#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0)
1375 +
1376 +/* CONTROL_PADCONF_X bits */
1377 +#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
1378 +#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
1379 +
1380 +#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860)
1381 +#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
1382 +#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
1383 +
1384 +/*
1385 + * CONTROL OMAP STATUS register to identify OMAP3 features
1386 + */
1387 +#define OMAP3_CONTROL_OMAP_STATUS 0x044c
1388 +
1389 +#define OMAP3_SGX_SHIFT 13
1390 +#define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT)
1391 +#define FEAT_SGX_FULL 0
1392 +#define FEAT_SGX_HALF 1
1393 +#define FEAT_SGX_NONE 2
1394 +
1395 +#define OMAP3_IVA_SHIFT 12
1396 +#define OMAP3_IVA_MASK (1 << OMAP3_SGX_SHIFT)
1397 +#define FEAT_IVA 0
1398 +#define FEAT_IVA_NONE 1
1399 +
1400 +#define OMAP3_L2CACHE_SHIFT 10
1401 +#define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT)
1402 +#define FEAT_L2CACHE_NONE 0
1403 +#define FEAT_L2CACHE_64KB 1
1404 +#define FEAT_L2CACHE_128KB 2
1405 +#define FEAT_L2CACHE_256KB 3
1406 +
1407 +#define OMAP3_ISP_SHIFT 5
1408 +#define OMAP3_ISP_MASK (1<< OMAP3_ISP_SHIFT)
1409 +#define FEAT_ISP 0
1410 +#define FEAT_ISP_NONE 1
1411 +
1412 +#define OMAP3_NEON_SHIFT 4
1413 +#define OMAP3_NEON_MASK (1<< OMAP3_NEON_SHIFT)
1414 +#define FEAT_NEON 0
1415 +#define FEAT_NEON_NONE 1
1416 +
1417 +
1418 +#ifndef __ASSEMBLY__
1419 +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
1420 + defined(CONFIG_ARCH_OMAP4)
1421 +extern void __iomem *omap_ctrl_base_get(void);
1422 +extern u8 omap_ctrl_readb(u16 offset);
1423 +extern u16 omap_ctrl_readw(u16 offset);
1424 +extern u32 omap_ctrl_readl(u16 offset);
1425 +extern void omap_ctrl_writeb(u8 val, u16 offset);
1426 +extern void omap_ctrl_writew(u16 val, u16 offset);
1427 +extern void omap_ctrl_writel(u32 val, u16 offset);
1428 +
1429 +extern void omap3_save_scratchpad_contents(void);
1430 +extern void omap3_clear_scratchpad_contents(void);
1431 +extern u32 *get_restore_pointer(void);
1432 +extern u32 *get_es3_restore_pointer(void);
1433 +extern u32 omap3_arm_context[128];
1434 +extern void omap3_control_save_context(void);
1435 +extern void omap3_control_restore_context(void);
1436 +
1437 +#else
1438 +#define omap_ctrl_base_get() 0
1439 +#define omap_ctrl_readb(x) 0
1440 +#define omap_ctrl_readw(x) 0
1441 +#define omap_ctrl_readl(x) 0
1442 +#define omap_ctrl_writeb(x, y) WARN_ON(1)
1443 +#define omap_ctrl_writew(x, y) WARN_ON(1)
1444 +#define omap_ctrl_writel(x, y) WARN_ON(1)
1445 +#endif
1446 +#endif /* __ASSEMBLY__ */
1447 +
1448 +#endif /* __ASM_ARCH_CONTROL_H */
1449 +
1450 --- /dev/null
1451 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/cpu.h
1452 @@ -0,0 +1,516 @@
1453 +/*
1454 + * arch/arm/plat-omap/include/mach/cpu.h
1455 + *
1456 + * OMAP cpu type detection
1457 + *
1458 + * Copyright (C) 2004, 2008 Nokia Corporation
1459 + *
1460 + * Copyright (C) 2009 Texas Instruments.
1461 + *
1462 + * Written by Tony Lindgren <tony.lindgren@nokia.com>
1463 + *
1464 + * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
1465 + *
1466 + * This program is free software; you can redistribute it and/or modify
1467 + * it under the terms of the GNU General Public License as published by
1468 + * the Free Software Foundation; either version 2 of the License, or
1469 + * (at your option) any later version.
1470 + *
1471 + * This program is distributed in the hope that it will be useful,
1472 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1473 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1474 + * GNU General Public License for more details.
1475 + *
1476 + * You should have received a copy of the GNU General Public License
1477 + * along with this program; if not, write to the Free Software
1478 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1479 + *
1480 + */
1481 +
1482 +#ifndef __ASM_ARCH_OMAP_CPU_H
1483 +#define __ASM_ARCH_OMAP_CPU_H
1484 +
1485 +#include <linux/bitops.h>
1486 +
1487 +/*
1488 + * Omap device type i.e. EMU/HS/TST/GP/BAD
1489 + */
1490 +#define OMAP2_DEVICE_TYPE_TEST 0
1491 +#define OMAP2_DEVICE_TYPE_EMU 1
1492 +#define OMAP2_DEVICE_TYPE_SEC 2
1493 +#define OMAP2_DEVICE_TYPE_GP 3
1494 +#define OMAP2_DEVICE_TYPE_BAD 4
1495 +
1496 +int omap_type(void);
1497 +
1498 +struct omap_chip_id {
1499 + u8 oc;
1500 + u8 type;
1501 +};
1502 +
1503 +#define OMAP_CHIP_INIT(x) { .oc = x }
1504 +
1505 +/*
1506 + * omap_rev bits:
1507 + * CPU id bits (0730, 1510, 1710, 2422...) [31:16]
1508 + * CPU revision (See _REV_ defined in cpu.h) [15:08]
1509 + * CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00]
1510 + */
1511 +unsigned int omap_rev(void);
1512 +
1513 +/*
1514 + * Define CPU revision bits
1515 + *
1516 + * Verbose meaning of the revision bits may be different for a silicon
1517 + * family. This difference can be handled separately.
1518 + */
1519 +#define OMAP_REVBITS_00 0x00
1520 +#define OMAP_REVBITS_10 0x10
1521 +#define OMAP_REVBITS_20 0x20
1522 +#define OMAP_REVBITS_30 0x30
1523 +#define OMAP_REVBITS_40 0x40
1524 +
1525 +/*
1526 + * Get the CPU revision for OMAP devices
1527 + */
1528 +#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff)
1529 +
1530 +/*
1531 + * Test if multicore OMAP support is needed
1532 + */
1533 +#undef MULTI_OMAP1
1534 +#undef MULTI_OMAP2
1535 +#undef OMAP_NAME
1536 +
1537 +#ifdef CONFIG_ARCH_OMAP730
1538 +# ifdef OMAP_NAME
1539 +# undef MULTI_OMAP1
1540 +# define MULTI_OMAP1
1541 +# else
1542 +# define OMAP_NAME omap730
1543 +# endif
1544 +#endif
1545 +#ifdef CONFIG_ARCH_OMAP850
1546 +# ifdef OMAP_NAME
1547 +# undef MULTI_OMAP1
1548 +# define MULTI_OMAP1
1549 +# else
1550 +# define OMAP_NAME omap850
1551 +# endif
1552 +#endif
1553 +#ifdef CONFIG_ARCH_OMAP15XX
1554 +# ifdef OMAP_NAME
1555 +# undef MULTI_OMAP1
1556 +# define MULTI_OMAP1
1557 +# else
1558 +# define OMAP_NAME omap1510
1559 +# endif
1560 +#endif
1561 +#ifdef CONFIG_ARCH_OMAP16XX
1562 +# ifdef OMAP_NAME
1563 +# undef MULTI_OMAP1
1564 +# define MULTI_OMAP1
1565 +# else
1566 +# define OMAP_NAME omap16xx
1567 +# endif
1568 +#endif
1569 +#if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX))
1570 +# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
1571 +# error "OMAP1 and OMAP2 can't be selected at the same time"
1572 +# endif
1573 +#endif
1574 +#ifdef CONFIG_ARCH_OMAP2420
1575 +# ifdef OMAP_NAME
1576 +# undef MULTI_OMAP2
1577 +# define MULTI_OMAP2
1578 +# else
1579 +# define OMAP_NAME omap2420
1580 +# endif
1581 +#endif
1582 +#ifdef CONFIG_ARCH_OMAP2430
1583 +# ifdef OMAP_NAME
1584 +# undef MULTI_OMAP2
1585 +# define MULTI_OMAP2
1586 +# else
1587 +# define OMAP_NAME omap2430
1588 +# endif
1589 +#endif
1590 +#ifdef CONFIG_ARCH_OMAP3430
1591 +# ifdef OMAP_NAME
1592 +# undef MULTI_OMAP2
1593 +# define MULTI_OMAP2
1594 +# else
1595 +# define OMAP_NAME omap3430
1596 +# endif
1597 +#endif
1598 +
1599 +/*
1600 + * Macros to group OMAP into cpu classes.
1601 + * These can be used in most places.
1602 + * cpu_is_omap7xx(): True for OMAP730, OMAP850
1603 + * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310
1604 + * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710
1605 + * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
1606 + * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423
1607 + * cpu_is_omap243x(): True for OMAP2430
1608 + * cpu_is_omap343x(): True for OMAP3430
1609 + */
1610 +#define GET_OMAP_CLASS (omap_rev() & 0xff)
1611 +
1612 +#define IS_OMAP_CLASS(class, id) \
1613 +static inline int is_omap ##class (void) \
1614 +{ \
1615 + return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
1616 +}
1617 +
1618 +#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
1619 +
1620 +#define IS_OMAP_SUBCLASS(subclass, id) \
1621 +static inline int is_omap ##subclass (void) \
1622 +{ \
1623 + return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
1624 +}
1625 +
1626 +IS_OMAP_CLASS(7xx, 0x07)
1627 +IS_OMAP_CLASS(15xx, 0x15)
1628 +IS_OMAP_CLASS(16xx, 0x16)
1629 +IS_OMAP_CLASS(24xx, 0x24)
1630 +IS_OMAP_CLASS(34xx, 0x34)
1631 +IS_OMAP_CLASS(44xx, 0x44)
1632 +
1633 +IS_OMAP_SUBCLASS(242x, 0x242)
1634 +IS_OMAP_SUBCLASS(243x, 0x243)
1635 +IS_OMAP_SUBCLASS(343x, 0x343)
1636 +IS_OMAP_SUBCLASS(363x, 0x363)
1637 +IS_OMAP_SUBCLASS(443x, 0x443)
1638 +
1639 +#define cpu_is_omap7xx() 0
1640 +#define cpu_is_omap15xx() 0
1641 +#define cpu_is_omap16xx() 0
1642 +#define cpu_is_omap24xx() 0
1643 +#define cpu_is_omap242x() 0
1644 +#define cpu_is_omap243x() 0
1645 +#define cpu_is_omap34xx() 0
1646 +#define cpu_is_omap343x() 0
1647 +#define cpu_is_omap44xx() 0
1648 +#define cpu_is_omap443x() 0
1649 +
1650 +#if defined(MULTI_OMAP1)
1651 +# if defined(CONFIG_ARCH_OMAP730)
1652 +# undef cpu_is_omap7xx
1653 +# define cpu_is_omap7xx() is_omap7xx()
1654 +# endif
1655 +# if defined(CONFIG_ARCH_OMAP850)
1656 +# undef cpu_is_omap7xx
1657 +# define cpu_is_omap7xx() is_omap7xx()
1658 +# endif
1659 +# if defined(CONFIG_ARCH_OMAP15XX)
1660 +# undef cpu_is_omap15xx
1661 +# define cpu_is_omap15xx() is_omap15xx()
1662 +# endif
1663 +# if defined(CONFIG_ARCH_OMAP16XX)
1664 +# undef cpu_is_omap16xx
1665 +# define cpu_is_omap16xx() is_omap16xx()
1666 +# endif
1667 +#else
1668 +# if defined(CONFIG_ARCH_OMAP730)
1669 +# undef cpu_is_omap7xx
1670 +# define cpu_is_omap7xx() 1
1671 +# endif
1672 +# if defined(CONFIG_ARCH_OMAP850)
1673 +# undef cpu_is_omap7xx
1674 +# define cpu_is_omap7xx() 1
1675 +# endif
1676 +# if defined(CONFIG_ARCH_OMAP15XX)
1677 +# undef cpu_is_omap15xx
1678 +# define cpu_is_omap15xx() 1
1679 +# endif
1680 +# if defined(CONFIG_ARCH_OMAP16XX)
1681 +# undef cpu_is_omap16xx
1682 +# define cpu_is_omap16xx() 1
1683 +# endif
1684 +#endif
1685 +
1686 +#if defined(MULTI_OMAP2)
1687 +# if defined(CONFIG_ARCH_OMAP24XX)
1688 +# undef cpu_is_omap24xx
1689 +# undef cpu_is_omap242x
1690 +# undef cpu_is_omap243x
1691 +# define cpu_is_omap24xx() is_omap24xx()
1692 +# define cpu_is_omap242x() is_omap242x()
1693 +# define cpu_is_omap243x() is_omap243x()
1694 +# endif
1695 +# if defined(CONFIG_ARCH_OMAP34XX)
1696 +# undef cpu_is_omap34xx
1697 +# undef cpu_is_omap343x
1698 +# define cpu_is_omap34xx() is_omap34xx()
1699 +# define cpu_is_omap343x() is_omap343x()
1700 +# endif
1701 +#else
1702 +# if defined(CONFIG_ARCH_OMAP24XX)
1703 +# undef cpu_is_omap24xx
1704 +# define cpu_is_omap24xx() 1
1705 +# endif
1706 +# if defined(CONFIG_ARCH_OMAP2420)
1707 +# undef cpu_is_omap242x
1708 +# define cpu_is_omap242x() 1
1709 +# endif
1710 +# if defined(CONFIG_ARCH_OMAP2430)
1711 +# undef cpu_is_omap243x
1712 +# define cpu_is_omap243x() 1
1713 +# endif
1714 +# if defined(CONFIG_ARCH_OMAP34XX)
1715 +# undef cpu_is_omap34xx
1716 +# define cpu_is_omap34xx() 1
1717 +# endif
1718 +# if defined(CONFIG_ARCH_OMAP3430)
1719 +# undef cpu_is_omap343x
1720 +# define cpu_is_omap343x() 1
1721 +# endif
1722 +#endif
1723 +
1724 +/*
1725 + * Macros to detect individual cpu types.
1726 + * These are only rarely needed.
1727 + * cpu_is_omap330(): True for OMAP330
1728 + * cpu_is_omap730(): True for OMAP730
1729 + * cpu_is_omap850(): True for OMAP850
1730 + * cpu_is_omap1510(): True for OMAP1510
1731 + * cpu_is_omap1610(): True for OMAP1610
1732 + * cpu_is_omap1611(): True for OMAP1611
1733 + * cpu_is_omap5912(): True for OMAP5912
1734 + * cpu_is_omap1621(): True for OMAP1621
1735 + * cpu_is_omap1710(): True for OMAP1710
1736 + * cpu_is_omap2420(): True for OMAP2420
1737 + * cpu_is_omap2422(): True for OMAP2422
1738 + * cpu_is_omap2423(): True for OMAP2423
1739 + * cpu_is_omap2430(): True for OMAP2430
1740 + * cpu_is_omap3430(): True for OMAP3430
1741 + * cpu_is_omap3505(): True for OMAP3505
1742 + * cpu_is_omap3517(): True for OMAP3517
1743 + */
1744 +#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff)
1745 +
1746 +#define IS_OMAP_TYPE(type, id) \
1747 +static inline int is_omap ##type (void) \
1748 +{ \
1749 + return (GET_OMAP_TYPE == (id)) ? 1 : 0; \
1750 +}
1751 +
1752 +IS_OMAP_TYPE(310, 0x0310)
1753 +IS_OMAP_TYPE(730, 0x0730)
1754 +IS_OMAP_TYPE(850, 0x0850)
1755 +IS_OMAP_TYPE(1510, 0x1510)
1756 +IS_OMAP_TYPE(1610, 0x1610)
1757 +IS_OMAP_TYPE(1611, 0x1611)
1758 +IS_OMAP_TYPE(5912, 0x1611)
1759 +IS_OMAP_TYPE(1621, 0x1621)
1760 +IS_OMAP_TYPE(1710, 0x1710)
1761 +IS_OMAP_TYPE(2420, 0x2420)
1762 +IS_OMAP_TYPE(2422, 0x2422)
1763 +IS_OMAP_TYPE(2423, 0x2423)
1764 +IS_OMAP_TYPE(2430, 0x2430)
1765 +IS_OMAP_TYPE(3430, 0x3430)
1766 +IS_OMAP_TYPE(3505, 0x3505)
1767 +IS_OMAP_TYPE(3517, 0x3517)
1768 +
1769 +#define cpu_is_omap310() 0
1770 +#define cpu_is_omap730() 0
1771 +#define cpu_is_omap850() 0
1772 +#define cpu_is_omap1510() 0
1773 +#define cpu_is_omap1610() 0
1774 +#define cpu_is_omap5912() 0
1775 +#define cpu_is_omap1611() 0
1776 +#define cpu_is_omap1621() 0
1777 +#define cpu_is_omap1710() 0
1778 +#define cpu_is_omap2420() 0
1779 +#define cpu_is_omap2422() 0
1780 +#define cpu_is_omap2423() 0
1781 +#define cpu_is_omap2430() 0
1782 +#define cpu_is_omap3503() 0
1783 +#define cpu_is_omap3515() 0
1784 +#define cpu_is_omap3525() 0
1785 +#define cpu_is_omap3530() 0
1786 +#define cpu_is_omap3505() 0
1787 +#define cpu_is_omap3517() 0
1788 +#define cpu_is_omap3430() 0
1789 +#define cpu_is_omap3630() 0
1790 +
1791 +/*
1792 + * Whether we have MULTI_OMAP1 or not, we still need to distinguish
1793 + * between 730 vs 850, 330 vs. 1510 and 1611B/5912 vs. 1710.
1794 + */
1795 +
1796 +#if defined(CONFIG_ARCH_OMAP730)
1797 +# undef cpu_is_omap730
1798 +# define cpu_is_omap730() is_omap730()
1799 +#endif
1800 +
1801 +#if defined(CONFIG_ARCH_OMAP850)
1802 +# undef cpu_is_omap850
1803 +# define cpu_is_omap850() is_omap850()
1804 +#endif
1805 +
1806 +#if defined(CONFIG_ARCH_OMAP15XX)
1807 +# undef cpu_is_omap310
1808 +# undef cpu_is_omap1510
1809 +# define cpu_is_omap310() is_omap310()
1810 +# define cpu_is_omap1510() is_omap1510()
1811 +#endif
1812 +
1813 +#if defined(CONFIG_ARCH_OMAP16XX)
1814 +# undef cpu_is_omap1610
1815 +# undef cpu_is_omap1611
1816 +# undef cpu_is_omap5912
1817 +# undef cpu_is_omap1621
1818 +# undef cpu_is_omap1710
1819 +# define cpu_is_omap1610() is_omap1610()
1820 +# define cpu_is_omap1611() is_omap1611()
1821 +# define cpu_is_omap5912() is_omap5912()
1822 +# define cpu_is_omap1621() is_omap1621()
1823 +# define cpu_is_omap1710() is_omap1710()
1824 +#endif
1825 +
1826 +#if defined(CONFIG_ARCH_OMAP24XX)
1827 +# undef cpu_is_omap2420
1828 +# undef cpu_is_omap2422
1829 +# undef cpu_is_omap2423
1830 +# undef cpu_is_omap2430
1831 +# define cpu_is_omap2420() is_omap2420()
1832 +# define cpu_is_omap2422() is_omap2422()
1833 +# define cpu_is_omap2423() is_omap2423()
1834 +# define cpu_is_omap2430() is_omap2430()
1835 +#endif
1836 +
1837 +#if defined(CONFIG_ARCH_OMAP34XX)
1838 +# undef cpu_is_omap3430
1839 +# undef cpu_is_omap3503
1840 +# undef cpu_is_omap3515
1841 +# undef cpu_is_omap3525
1842 +# undef cpu_is_omap3530
1843 +# undef cpu_is_omap3505
1844 +# undef cpu_is_omap3517
1845 +# define cpu_is_omap3430() is_omap3430()
1846 +# define cpu_is_omap3503() (cpu_is_omap3430() && \
1847 + (!omap3_has_iva()) && \
1848 + (!omap3_has_sgx()))
1849 +# define cpu_is_omap3515() (cpu_is_omap3430() && \
1850 + (!omap3_has_iva()) && \
1851 + (omap3_has_sgx()))
1852 +# define cpu_is_omap3525() (cpu_is_omap3430() && \
1853 + (!omap3_has_sgx()) && \
1854 + (omap3_has_iva()))
1855 +# define cpu_is_omap3530() (cpu_is_omap3430())
1856 +# define cpu_is_omap3505() is_omap3505()
1857 +# define cpu_is_omap3517() is_omap3517()
1858 +# undef cpu_is_omap3630
1859 +# define cpu_is_omap3630() is_omap363x()
1860 +#endif
1861 +
1862 +# if defined(CONFIG_ARCH_OMAP4)
1863 +# undef cpu_is_omap44xx
1864 +# undef cpu_is_omap443x
1865 +# define cpu_is_omap44xx() is_omap44xx()
1866 +# define cpu_is_omap443x() is_omap443x()
1867 +# endif
1868 +
1869 +/* Macros to detect if we have OMAP1 or OMAP2 */
1870 +#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \
1871 + cpu_is_omap16xx())
1872 +#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
1873 + cpu_is_omap44xx())
1874 +
1875 +/* Various silicon revisions for omap2 */
1876 +#define OMAP242X_CLASS 0x24200024
1877 +#define OMAP2420_REV_ES1_0 0x24200024
1878 +#define OMAP2420_REV_ES2_0 0x24201024
1879 +
1880 +#define OMAP243X_CLASS 0x24300024
1881 +#define OMAP2430_REV_ES1_0 0x24300024
1882 +
1883 +#define OMAP343X_CLASS 0x34300034
1884 +#define OMAP3430_REV_ES1_0 0x34300034
1885 +#define OMAP3430_REV_ES2_0 0x34301034
1886 +#define OMAP3430_REV_ES2_1 0x34302034
1887 +#define OMAP3430_REV_ES3_0 0x34303034
1888 +#define OMAP3430_REV_ES3_1 0x34304034
1889 +
1890 +#define OMAP3630_REV_ES1_0 0x36300034
1891 +
1892 +#define OMAP35XX_CLASS 0x35000034
1893 +#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
1894 +#define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8))
1895 +#define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
1896 +#define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
1897 +#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
1898 +#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
1899 +
1900 +#define OMAP443X_CLASS 0x44300044
1901 +#define OMAP4430_REV_ES1_0 0x44300044
1902 +
1903 +/*
1904 + * omap_chip bits
1905 + *
1906 + * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
1907 + * valid on all chips of that type. CHIP_IS_OMAP3430ES{1,2} indicates
1908 + * something that is only valid on that particular ES revision.
1909 + *
1910 + * These bits may be ORed together to indicate structures that are
1911 + * available on multiple chip types.
1912 + *
1913 + * To test whether a particular structure matches the current OMAP chip type,
1914 + * use omap_chip_is().
1915 + *
1916 + */
1917 +#define CHIP_IS_OMAP2420 (1 << 0)
1918 +#define CHIP_IS_OMAP2430 (1 << 1)
1919 +#define CHIP_IS_OMAP3430 (1 << 2)
1920 +#define CHIP_IS_OMAP3430ES1 (1 << 3)
1921 +#define CHIP_IS_OMAP3430ES2 (1 << 4)
1922 +#define CHIP_IS_OMAP3430ES3_0 (1 << 5)
1923 +#define CHIP_IS_OMAP3430ES3_1 (1 << 6)
1924 +#define CHIP_IS_OMAP3630ES1 (1 << 7)
1925 +
1926 +#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
1927 +
1928 +/*
1929 + * "GE" here represents "greater than or equal to" in terms of ES
1930 + * levels. So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430
1931 + * chips at ES2 and beyond, but not, for example, any OMAP lines after
1932 + * OMAP3.
1933 + */
1934 +#define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \
1935 + CHIP_IS_OMAP3430ES3_0 | \
1936 + CHIP_IS_OMAP3430ES3_1 | \
1937 + CHIP_IS_OMAP3630ES1)
1938 +#define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \
1939 + CHIP_IS_OMAP3630ES1)
1940 +
1941 +
1942 +int omap_chip_is(struct omap_chip_id oci);
1943 +void omap2_check_revision(void);
1944 +
1945 +/*
1946 + * Runtime detection of OMAP3 features
1947 + */
1948 +extern u32 omap3_features;
1949 +
1950 +#define OMAP3_HAS_L2CACHE BIT(0)
1951 +#define OMAP3_HAS_IVA BIT(1)
1952 +#define OMAP3_HAS_SGX BIT(2)
1953 +#define OMAP3_HAS_NEON BIT(3)
1954 +#define OMAP3_HAS_ISP BIT(4)
1955 +
1956 +#define OMAP3_HAS_FEATURE(feat,flag) \
1957 +static inline unsigned int omap3_has_ ##feat(void) \
1958 +{ \
1959 + return (omap3_features & OMAP3_HAS_ ##flag); \
1960 +} \
1961 +
1962 +OMAP3_HAS_FEATURE(l2cache, L2CACHE)
1963 +OMAP3_HAS_FEATURE(sgx, SGX)
1964 +OMAP3_HAS_FEATURE(iva, IVA)
1965 +OMAP3_HAS_FEATURE(neon, NEON)
1966 +OMAP3_HAS_FEATURE(isp, ISP)
1967 +
1968 +#endif
1969 --- /dev/null
1970 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/display.h
1971 @@ -0,0 +1,575 @@
1972 +/*
1973 + * linux/include/asm-arm/arch-omap/display.h
1974 + *
1975 + * Copyright (C) 2008 Nokia Corporation
1976 + * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
1977 + *
1978 + * This program is free software; you can redistribute it and/or modify it
1979 + * under the terms of the GNU General Public License version 2 as published by
1980 + * the Free Software Foundation.
1981 + *
1982 + * This program is distributed in the hope that it will be useful, but WITHOUT
1983 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1984 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1985 + * more details.
1986 + *
1987 + * You should have received a copy of the GNU General Public License along with
1988 + * this program. If not, see <http://www.gnu.org/licenses/>.
1989 + */
1990 +
1991 +#ifndef __ASM_ARCH_OMAP_DISPLAY_H
1992 +#define __ASM_ARCH_OMAP_DISPLAY_H
1993 +
1994 +#include <linux/list.h>
1995 +#include <linux/kobject.h>
1996 +#include <linux/device.h>
1997 +#include <asm/atomic.h>
1998 +
1999 +#define DISPC_IRQ_FRAMEDONE (1 << 0)
2000 +#define DISPC_IRQ_VSYNC (1 << 1)
2001 +#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
2002 +#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
2003 +#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
2004 +#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
2005 +#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
2006 +#define DISPC_IRQ_GFX_END_WIN (1 << 7)
2007 +#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
2008 +#define DISPC_IRQ_OCP_ERR (1 << 9)
2009 +#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
2010 +#define DISPC_IRQ_VID1_END_WIN (1 << 11)
2011 +#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
2012 +#define DISPC_IRQ_VID2_END_WIN (1 << 13)
2013 +#define DISPC_IRQ_SYNC_LOST (1 << 14)
2014 +#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
2015 +#define DISPC_IRQ_WAKEUP (1 << 16)
2016 +
2017 +struct omap_dss_device;
2018 +struct omap_overlay_manager;
2019 +
2020 +enum omap_display_type {
2021 + OMAP_DISPLAY_TYPE_NONE = 0,
2022 + OMAP_DISPLAY_TYPE_DPI = 1 << 0,
2023 + OMAP_DISPLAY_TYPE_DBI = 1 << 1,
2024 + OMAP_DISPLAY_TYPE_SDI = 1 << 2,
2025 + OMAP_DISPLAY_TYPE_DSI = 1 << 3,
2026 + OMAP_DISPLAY_TYPE_VENC = 1 << 4,
2027 +};
2028 +
2029 +enum omap_plane {
2030 + OMAP_DSS_GFX = 0,
2031 + OMAP_DSS_VIDEO1 = 1,
2032 + OMAP_DSS_VIDEO2 = 2
2033 +};
2034 +
2035 +enum omap_channel {
2036 + OMAP_DSS_CHANNEL_LCD = 0,
2037 + OMAP_DSS_CHANNEL_DIGIT = 1,
2038 +};
2039 +
2040 +enum omap_color_mode {
2041 + OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
2042 + OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
2043 + OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
2044 + OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
2045 + OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
2046 + OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
2047 + OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
2048 + OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
2049 + OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
2050 + OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
2051 + OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
2052 + OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
2053 + OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
2054 + OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
2055 +
2056 + OMAP_DSS_COLOR_GFX_OMAP2 =
2057 + OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
2058 + OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
2059 + OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
2060 + OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
2061 +
2062 + OMAP_DSS_COLOR_VID_OMAP2 =
2063 + OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
2064 + OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
2065 + OMAP_DSS_COLOR_UYVY,
2066 +
2067 + OMAP_DSS_COLOR_GFX_OMAP3 =
2068 + OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
2069 + OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
2070 + OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
2071 + OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
2072 + OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
2073 + OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
2074 +
2075 + OMAP_DSS_COLOR_VID1_OMAP3 =
2076 + OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
2077 + OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
2078 + OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
2079 +
2080 + OMAP_DSS_COLOR_VID2_OMAP3 =
2081 + OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
2082 + OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
2083 + OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
2084 + OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
2085 + OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
2086 +};
2087 +
2088 +enum omap_lcd_display_type {
2089 + OMAP_DSS_LCD_DISPLAY_STN,
2090 + OMAP_DSS_LCD_DISPLAY_TFT,
2091 +};
2092 +
2093 +enum omap_dss_load_mode {
2094 + OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
2095 + OMAP_DSS_LOAD_CLUT_ONLY = 1,
2096 + OMAP_DSS_LOAD_FRAME_ONLY = 2,
2097 + OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
2098 +};
2099 +
2100 +enum omap_dss_trans_key_type {
2101 + OMAP_DSS_COLOR_KEY_GFX_DST = 0,
2102 + OMAP_DSS_COLOR_KEY_VID_SRC = 1,
2103 +};
2104 +
2105 +enum omap_rfbi_te_mode {
2106 + OMAP_DSS_RFBI_TE_MODE_1 = 1,
2107 + OMAP_DSS_RFBI_TE_MODE_2 = 2,
2108 +};
2109 +
2110 +enum omap_panel_config {
2111 + OMAP_DSS_LCD_IVS = 1<<0,
2112 + OMAP_DSS_LCD_IHS = 1<<1,
2113 + OMAP_DSS_LCD_IPC = 1<<2,
2114 + OMAP_DSS_LCD_IEO = 1<<3,
2115 + OMAP_DSS_LCD_RF = 1<<4,
2116 + OMAP_DSS_LCD_ONOFF = 1<<5,
2117 +
2118 + OMAP_DSS_LCD_TFT = 1<<20,
2119 +};
2120 +
2121 +enum omap_dss_venc_type {
2122 + OMAP_DSS_VENC_TYPE_COMPOSITE,
2123 + OMAP_DSS_VENC_TYPE_SVIDEO,
2124 +};
2125 +
2126 +enum omap_display_caps {
2127 + OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
2128 + OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
2129 +};
2130 +
2131 +enum omap_dss_update_mode {
2132 + OMAP_DSS_UPDATE_DISABLED = 0,
2133 + OMAP_DSS_UPDATE_AUTO,
2134 + OMAP_DSS_UPDATE_MANUAL,
2135 +};
2136 +
2137 +enum omap_dss_display_state {
2138 + OMAP_DSS_DISPLAY_DISABLED = 0,
2139 + OMAP_DSS_DISPLAY_ACTIVE,
2140 + OMAP_DSS_DISPLAY_SUSPENDED,
2141 +};
2142 +
2143 +/* XXX perhaps this should be removed */
2144 +enum omap_dss_overlay_managers {
2145 + OMAP_DSS_OVL_MGR_LCD,
2146 + OMAP_DSS_OVL_MGR_TV,
2147 +};
2148 +
2149 +enum omap_dss_rotation_type {
2150 + OMAP_DSS_ROT_DMA = 0,
2151 + OMAP_DSS_ROT_VRFB = 1,
2152 +};
2153 +
2154 +/* clockwise rotation angle */
2155 +enum omap_dss_rotation_angle {
2156 + OMAP_DSS_ROT_0 = 0,
2157 + OMAP_DSS_ROT_90 = 1,
2158 + OMAP_DSS_ROT_180 = 2,
2159 + OMAP_DSS_ROT_270 = 3,
2160 +};
2161 +
2162 +enum omap_overlay_caps {
2163 + OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
2164 + OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
2165 +};
2166 +
2167 +enum omap_overlay_manager_caps {
2168 + OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
2169 +};
2170 +
2171 +/* RFBI */
2172 +
2173 +struct rfbi_timings {
2174 + int cs_on_time;
2175 + int cs_off_time;
2176 + int we_on_time;
2177 + int we_off_time;
2178 + int re_on_time;
2179 + int re_off_time;
2180 + int we_cycle_time;
2181 + int re_cycle_time;
2182 + int cs_pulse_width;
2183 + int access_time;
2184 +
2185 + int clk_div;
2186 +
2187 + u32 tim[5]; /* set by rfbi_convert_timings() */
2188 +
2189 + int converted;
2190 +};
2191 +
2192 +void omap_rfbi_write_command(const void *buf, u32 len);
2193 +void omap_rfbi_read_data(void *buf, u32 len);
2194 +void omap_rfbi_write_data(const void *buf, u32 len);
2195 +void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
2196 + u16 x, u16 y,
2197 + u16 w, u16 h);
2198 +int omap_rfbi_enable_te(bool enable, unsigned line);
2199 +int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
2200 + unsigned hs_pulse_time, unsigned vs_pulse_time,
2201 + int hs_pol_inv, int vs_pol_inv, int extif_div);
2202 +
2203 +/* DSI */
2204 +void dsi_bus_lock(void);
2205 +void dsi_bus_unlock(void);
2206 +int dsi_vc_dcs_write(int channel, u8 *data, int len);
2207 +int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
2208 +int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
2209 +int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
2210 +int dsi_vc_send_null(int channel);
2211 +int dsi_vc_send_bta_sync(int channel);
2212 +
2213 +/* Board specific data */
2214 +struct omap_dss_board_info {
2215 + int (*get_last_off_on_transaction_id)(struct device *dev);
2216 + int num_devices;
2217 + struct omap_dss_device **devices;
2218 + struct omap_dss_device *default_device;
2219 +};
2220 +
2221 +struct omap_video_timings {
2222 + /* Unit: pixels */
2223 + u16 x_res;
2224 + /* Unit: pixels */
2225 + u16 y_res;
2226 + /* Unit: KHz */
2227 + u32 pixel_clock;
2228 + /* Unit: pixel clocks */
2229 + u16 hsw; /* Horizontal synchronization pulse width */
2230 + /* Unit: pixel clocks */
2231 + u16 hfp; /* Horizontal front porch */
2232 + /* Unit: pixel clocks */
2233 + u16 hbp; /* Horizontal back porch */
2234 + /* Unit: line clocks */
2235 + u16 vsw; /* Vertical synchronization pulse width */
2236 + /* Unit: line clocks */
2237 + u16 vfp; /* Vertical front porch */
2238 + /* Unit: line clocks */
2239 + u16 vbp; /* Vertical back porch */
2240 +};
2241 +
2242 +#ifdef CONFIG_OMAP2_DSS_VENC
2243 +/* Hardcoded timings for tv modes. Venc only uses these to
2244 + * identify the mode, and does not actually use the configs
2245 + * itself. However, the configs should be something that
2246 + * a normal monitor can also show */
2247 +const extern struct omap_video_timings omap_dss_pal_timings;
2248 +const extern struct omap_video_timings omap_dss_ntsc_timings;
2249 +#endif
2250 +
2251 +struct omap_overlay_info {
2252 + bool enabled;
2253 +
2254 + u32 paddr;
2255 + void __iomem *vaddr;
2256 + u16 screen_width;
2257 + u16 width;
2258 + u16 height;
2259 + enum omap_color_mode color_mode;
2260 + u8 rotation;
2261 + enum omap_dss_rotation_type rotation_type;
2262 + bool mirror;
2263 +
2264 + u16 pos_x;
2265 + u16 pos_y;
2266 + u16 out_width; /* if 0, out_width == width */
2267 + u16 out_height; /* if 0, out_height == height */
2268 + u8 global_alpha;
2269 +};
2270 +
2271 +struct omap_overlay {
2272 + struct kobject kobj;
2273 + struct list_head list;
2274 +
2275 + /* static fields */
2276 + const char *name;
2277 + int id;
2278 + enum omap_color_mode supported_modes;
2279 + enum omap_overlay_caps caps;
2280 +
2281 + /* dynamic fields */
2282 + struct omap_overlay_manager *manager;
2283 + struct omap_overlay_info info;
2284 +
2285 + /* if true, info has been changed, but not applied() yet */
2286 + bool info_dirty;
2287 +
2288 + int (*set_manager)(struct omap_overlay *ovl,
2289 + struct omap_overlay_manager *mgr);
2290 + int (*unset_manager)(struct omap_overlay *ovl);
2291 +
2292 + int (*set_overlay_info)(struct omap_overlay *ovl,
2293 + struct omap_overlay_info *info);
2294 + void (*get_overlay_info)(struct omap_overlay *ovl,
2295 + struct omap_overlay_info *info);
2296 +
2297 + int (*wait_for_go)(struct omap_overlay *ovl);
2298 +};
2299 +
2300 +struct omap_overlay_manager_info {
2301 + u32 default_color;
2302 +
2303 + enum omap_dss_trans_key_type trans_key_type;
2304 + u32 trans_key;
2305 + bool trans_enabled;
2306 +
2307 + bool alpha_enabled;
2308 +};
2309 +
2310 +struct omap_overlay_manager {
2311 + struct kobject kobj;
2312 + struct list_head list;
2313 +
2314 + /* static fields */
2315 + const char *name;
2316 + int id;
2317 + enum omap_overlay_manager_caps caps;
2318 + int num_overlays;
2319 + struct omap_overlay **overlays;
2320 + enum omap_display_type supported_displays;
2321 +
2322 + /* dynamic fields */
2323 + struct omap_dss_device *device;
2324 + struct omap_overlay_manager_info info;
2325 +
2326 + bool device_changed;
2327 + /* if true, info has been changed but not applied() yet */
2328 + bool info_dirty;
2329 +
2330 + int (*set_device)(struct omap_overlay_manager *mgr,
2331 + struct omap_dss_device *dssdev);
2332 + int (*unset_device)(struct omap_overlay_manager *mgr);
2333 +
2334 + int (*set_manager_info)(struct omap_overlay_manager *mgr,
2335 + struct omap_overlay_manager_info *info);
2336 + void (*get_manager_info)(struct omap_overlay_manager *mgr,
2337 + struct omap_overlay_manager_info *info);
2338 +
2339 + int (*apply)(struct omap_overlay_manager *mgr);
2340 + int (*wait_for_go)(struct omap_overlay_manager *mgr);
2341 +};
2342 +
2343 +struct omap_dss_device {
2344 + struct device dev;
2345 +
2346 + enum omap_display_type type;
2347 +
2348 + union {
2349 + struct {
2350 + u8 data_lines;
2351 + } dpi;
2352 +
2353 + struct {
2354 + u8 channel;
2355 + u8 data_lines;
2356 + } rfbi;
2357 +
2358 + struct {
2359 + u8 datapairs;
2360 + } sdi;
2361 +
2362 + struct {
2363 + u8 clk_lane;
2364 + u8 clk_pol;
2365 + u8 data1_lane;
2366 + u8 data1_pol;
2367 + u8 data2_lane;
2368 + u8 data2_pol;
2369 +
2370 + struct {
2371 + u16 regn;
2372 + u16 regm;
2373 + u16 regm3;
2374 + u16 regm4;
2375 +
2376 + u16 lp_clk_div;
2377 +
2378 + u16 lck_div;
2379 + u16 pck_div;
2380 + } div;
2381 +
2382 + bool ext_te;
2383 + u8 ext_te_gpio;
2384 + } dsi;
2385 +
2386 + struct {
2387 + enum omap_dss_venc_type type;
2388 + bool invert_polarity;
2389 + } venc;
2390 + } phy;
2391 +
2392 + struct {
2393 + struct omap_video_timings timings;
2394 +
2395 + int acbi; /* ac-bias pin transitions per interrupt */
2396 + /* Unit: line clocks */
2397 + int acb; /* ac-bias pin frequency */
2398 +
2399 + enum omap_panel_config config;
2400 +
2401 + u8 recommended_bpp;
2402 +
2403 + struct omap_dss_device *ctrl;
2404 + } panel;
2405 +
2406 + struct {
2407 + u8 pixel_size;
2408 + struct rfbi_timings rfbi_timings;
2409 + struct omap_dss_device *panel;
2410 + } ctrl;
2411 +
2412 + int reset_gpio;
2413 +
2414 + int max_backlight_level;
2415 +
2416 + const char *name;
2417 +
2418 + /* used to match device to driver */
2419 + const char *driver_name;
2420 +
2421 + void *data;
2422 +
2423 + struct omap_dss_driver *driver;
2424 +
2425 + /* helper variable for driver suspend/resume */
2426 + bool activate_after_resume;
2427 +
2428 + enum omap_display_caps caps;
2429 +
2430 + struct omap_overlay_manager *manager;
2431 +
2432 + enum omap_dss_display_state state;
2433 +
2434 + int (*enable)(struct omap_dss_device *dssdev);
2435 + void (*disable)(struct omap_dss_device *dssdev);
2436 +
2437 + int (*suspend)(struct omap_dss_device *dssdev);
2438 + int (*resume)(struct omap_dss_device *dssdev);
2439 +
2440 + void (*get_resolution)(struct omap_dss_device *dssdev,
2441 + u16 *xres, u16 *yres);
2442 + int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
2443 +
2444 + int (*check_timings)(struct omap_dss_device *dssdev,
2445 + struct omap_video_timings *timings);
2446 + void (*set_timings)(struct omap_dss_device *dssdev,
2447 + struct omap_video_timings *timings);
2448 + void (*get_timings)(struct omap_dss_device *dssdev,
2449 + struct omap_video_timings *timings);
2450 + int (*update)(struct omap_dss_device *dssdev,
2451 + u16 x, u16 y, u16 w, u16 h);
2452 + int (*sync)(struct omap_dss_device *dssdev);
2453 + int (*wait_vsync)(struct omap_dss_device *dssdev);
2454 +
2455 + int (*set_update_mode)(struct omap_dss_device *dssdev,
2456 + enum omap_dss_update_mode);
2457 + enum omap_dss_update_mode (*get_update_mode)
2458 + (struct omap_dss_device *dssdev);
2459 +
2460 + int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
2461 + int (*get_te)(struct omap_dss_device *dssdev);
2462 +
2463 + u8 (*get_rotate)(struct omap_dss_device *dssdev);
2464 + int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
2465 +
2466 + bool (*get_mirror)(struct omap_dss_device *dssdev);
2467 + int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
2468 +
2469 + int (*run_test)(struct omap_dss_device *dssdev, int test);
2470 + int (*memory_read)(struct omap_dss_device *dssdev,
2471 + void *buf, size_t size,
2472 + u16 x, u16 y, u16 w, u16 h);
2473 +
2474 + int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
2475 + u32 (*get_wss)(struct omap_dss_device *dssdev);
2476 +
2477 + /* platform specific */
2478 + int (*platform_enable)(struct omap_dss_device *dssdev);
2479 + void (*platform_disable)(struct omap_dss_device *dssdev);
2480 + int (*set_backlight)(struct omap_dss_device *dssdev, int level);
2481 + int (*get_backlight)(struct omap_dss_device *dssdev);
2482 +};
2483 +
2484 +struct omap_dss_driver {
2485 + struct device_driver driver;
2486 +
2487 + int (*probe)(struct omap_dss_device *);
2488 + void (*remove)(struct omap_dss_device *);
2489 +
2490 + int (*enable)(struct omap_dss_device *display);
2491 + void (*disable)(struct omap_dss_device *display);
2492 + int (*suspend)(struct omap_dss_device *display);
2493 + int (*resume)(struct omap_dss_device *display);
2494 + int (*run_test)(struct omap_dss_device *display, int test);
2495 +
2496 + void (*setup_update)(struct omap_dss_device *dssdev,
2497 + u16 x, u16 y, u16 w, u16 h);
2498 +
2499 + int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
2500 + int (*wait_for_te)(struct omap_dss_device *dssdev);
2501 +
2502 + u8 (*get_rotate)(struct omap_dss_device *dssdev);
2503 + int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
2504 +
2505 + bool (*get_mirror)(struct omap_dss_device *dssdev);
2506 + int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
2507 +
2508 + int (*memory_read)(struct omap_dss_device *dssdev,
2509 + void *buf, size_t size,
2510 + u16 x, u16 y, u16 w, u16 h);
2511 +};
2512 +
2513 +int omap_dss_register_driver(struct omap_dss_driver *);
2514 +void omap_dss_unregister_driver(struct omap_dss_driver *);
2515 +
2516 +int omap_dss_register_device(struct omap_dss_device *);
2517 +void omap_dss_unregister_device(struct omap_dss_device *);
2518 +
2519 +void omap_dss_get_device(struct omap_dss_device *dssdev);
2520 +void omap_dss_put_device(struct omap_dss_device *dssdev);
2521 +#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
2522 +struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
2523 +struct omap_dss_device *omap_dss_find_device(void *data,
2524 + int (*match)(struct omap_dss_device *dssdev, void *data));
2525 +
2526 +int omap_dss_start_device(struct omap_dss_device *dssdev);
2527 +void omap_dss_stop_device(struct omap_dss_device *dssdev);
2528 +
2529 +int omap_dss_get_num_overlay_managers(void);
2530 +struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
2531 +
2532 +int omap_dss_get_num_overlays(void);
2533 +struct omap_overlay *omap_dss_get_overlay(int num);
2534 +
2535 +typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
2536 +int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
2537 +int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
2538 +
2539 +int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
2540 +int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
2541 + unsigned long timeout);
2542 +
2543 +#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
2544 +#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
2545 +
2546 +#endif
2547 --- /dev/null
2548 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/dma.h
2549 @@ -0,0 +1,640 @@
2550 +/*
2551 + * arch/arm/plat-omap/include/mach/dma.h
2552 + *
2553 + * Copyright (C) 2003 Nokia Corporation
2554 + * Author: Juha Yrjölä <juha.yrjola@nokia.com>
2555 + *
2556 + * This program is free software; you can redistribute it and/or modify
2557 + * it under the terms of the GNU General Public License as published by
2558 + * the Free Software Foundation; either version 2 of the License, or
2559 + * (at your option) any later version.
2560 + *
2561 + * This program is distributed in the hope that it will be useful,
2562 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2563 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2564 + * GNU General Public License for more details.
2565 + *
2566 + * You should have received a copy of the GNU General Public License
2567 + * along with this program; if not, write to the Free Software
2568 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2569 + */
2570 +#ifndef __ASM_ARCH_DMA_H
2571 +#define __ASM_ARCH_DMA_H
2572 +
2573 +/* Hardware registers for omap1 */
2574 +#define OMAP1_DMA_BASE (0xfffed800)
2575 +
2576 +#define OMAP1_DMA_GCR 0x400
2577 +#define OMAP1_DMA_GSCR 0x404
2578 +#define OMAP1_DMA_GRST 0x408
2579 +#define OMAP1_DMA_HW_ID 0x442
2580 +#define OMAP1_DMA_PCH2_ID 0x444
2581 +#define OMAP1_DMA_PCH0_ID 0x446
2582 +#define OMAP1_DMA_PCH1_ID 0x448
2583 +#define OMAP1_DMA_PCHG_ID 0x44a
2584 +#define OMAP1_DMA_PCHD_ID 0x44c
2585 +#define OMAP1_DMA_CAPS_0_U 0x44e
2586 +#define OMAP1_DMA_CAPS_0_L 0x450
2587 +#define OMAP1_DMA_CAPS_1_U 0x452
2588 +#define OMAP1_DMA_CAPS_1_L 0x454
2589 +#define OMAP1_DMA_CAPS_2 0x456
2590 +#define OMAP1_DMA_CAPS_3 0x458
2591 +#define OMAP1_DMA_CAPS_4 0x45a
2592 +#define OMAP1_DMA_PCH2_SR 0x460
2593 +#define OMAP1_DMA_PCH0_SR 0x480
2594 +#define OMAP1_DMA_PCH1_SR 0x482
2595 +#define OMAP1_DMA_PCHD_SR 0x4c0
2596 +
2597 +/* Hardware registers for omap2 and omap3 */
2598 +#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000)
2599 +#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000)
2600 +#define OMAP44XX_DMA4_BASE (L4_44XX_BASE + 0x56000)
2601 +
2602 +#define OMAP_DMA4_REVISION 0x00
2603 +#define OMAP_DMA4_GCR 0x78
2604 +#define OMAP_DMA4_IRQSTATUS_L0 0x08
2605 +#define OMAP_DMA4_IRQSTATUS_L1 0x0c
2606 +#define OMAP_DMA4_IRQSTATUS_L2 0x10
2607 +#define OMAP_DMA4_IRQSTATUS_L3 0x14
2608 +#define OMAP_DMA4_IRQENABLE_L0 0x18
2609 +#define OMAP_DMA4_IRQENABLE_L1 0x1c
2610 +#define OMAP_DMA4_IRQENABLE_L2 0x20
2611 +#define OMAP_DMA4_IRQENABLE_L3 0x24
2612 +#define OMAP_DMA4_SYSSTATUS 0x28
2613 +#define OMAP_DMA4_OCP_SYSCONFIG 0x2c
2614 +#define OMAP_DMA4_CAPS_0 0x64
2615 +#define OMAP_DMA4_CAPS_2 0x6c
2616 +#define OMAP_DMA4_CAPS_3 0x70
2617 +#define OMAP_DMA4_CAPS_4 0x74
2618 +
2619 +#define OMAP1_LOGICAL_DMA_CH_COUNT 17
2620 +#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
2621 +
2622 +/* Common channel specific registers for omap1 */
2623 +#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00)
2624 +#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00)
2625 +#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02)
2626 +#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04)
2627 +#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06)
2628 +#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10)
2629 +#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12)
2630 +#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14)
2631 +#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16)
2632 +#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */
2633 +#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18)
2634 +#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a)
2635 +#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c)
2636 +#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e)
2637 +#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28)
2638 +
2639 +/* Common channel specific registers for omap2 */
2640 +#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80)
2641 +#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80)
2642 +#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84)
2643 +#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88)
2644 +#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c)
2645 +#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90)
2646 +#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94)
2647 +#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98)
2648 +#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4)
2649 +#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8)
2650 +#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac)
2651 +#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0)
2652 +#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4)
2653 +#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8)
2654 +
2655 +/* Channel specific registers only on omap1 */
2656 +#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08)
2657 +#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a)
2658 +#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c)
2659 +#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e)
2660 +#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20)
2661 +#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22)
2662 +#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24)
2663 +#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */
2664 +#define OMAP1_DMA_CCEN(n) 0
2665 +#define OMAP1_DMA_CCFN(n) 0
2666 +
2667 +/* Channel specific registers only on omap2 */
2668 +#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c)
2669 +#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0)
2670 +#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc)
2671 +#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
2672 +#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)
2673 +
2674 +/* Additional registers available on OMAP4 */
2675 +#define OMAP_DMA4_CDP(n) (0x60 * (n) + 0xd0)
2676 +#define OMAP_DMA4_CNDP(n) (0x60 * (n) + 0xd4)
2677 +#define OMAP_DMA4_CCDN(n) (0x60 * (n) + 0xd8)
2678 +
2679 +/* Dummy defines to keep multi-omap compiles happy */
2680 +#define OMAP1_DMA_REVISION 0
2681 +#define OMAP1_DMA_IRQSTATUS_L0 0
2682 +#define OMAP1_DMA_IRQENABLE_L0 0
2683 +#define OMAP1_DMA_OCP_SYSCONFIG 0
2684 +#define OMAP_DMA4_HW_ID 0
2685 +#define OMAP_DMA4_CAPS_0_L 0
2686 +#define OMAP_DMA4_CAPS_0_U 0
2687 +#define OMAP_DMA4_CAPS_1_L 0
2688 +#define OMAP_DMA4_CAPS_1_U 0
2689 +#define OMAP_DMA4_GSCR 0
2690 +#define OMAP_DMA4_CPC(n) 0
2691 +
2692 +#define OMAP_DMA4_LCH_CTRL(n) 0
2693 +#define OMAP_DMA4_COLOR_L(n) 0
2694 +#define OMAP_DMA4_COLOR_U(n) 0
2695 +#define OMAP_DMA4_CCR2(n) 0
2696 +#define OMAP1_DMA_CSSA(n) 0
2697 +#define OMAP1_DMA_CDSA(n) 0
2698 +#define OMAP_DMA4_CSSA_L(n) 0
2699 +#define OMAP_DMA4_CSSA_U(n) 0
2700 +#define OMAP_DMA4_CDSA_L(n) 0
2701 +#define OMAP_DMA4_CDSA_U(n) 0
2702 +#define OMAP1_DMA_COLOR(n) 0
2703 +
2704 +/*----------------------------------------------------------------------------*/
2705 +
2706 +/* DMA channels for omap1 */
2707 +#define OMAP_DMA_NO_DEVICE 0
2708 +#define OMAP_DMA_MCSI1_TX 1
2709 +#define OMAP_DMA_MCSI1_RX 2
2710 +#define OMAP_DMA_I2C_RX 3
2711 +#define OMAP_DMA_I2C_TX 4
2712 +#define OMAP_DMA_EXT_NDMA_REQ 5
2713 +#define OMAP_DMA_EXT_NDMA_REQ2 6
2714 +#define OMAP_DMA_UWIRE_TX 7
2715 +#define OMAP_DMA_MCBSP1_TX 8
2716 +#define OMAP_DMA_MCBSP1_RX 9
2717 +#define OMAP_DMA_MCBSP3_TX 10
2718 +#define OMAP_DMA_MCBSP3_RX 11
2719 +#define OMAP_DMA_UART1_TX 12
2720 +#define OMAP_DMA_UART1_RX 13
2721 +#define OMAP_DMA_UART2_TX 14
2722 +#define OMAP_DMA_UART2_RX 15
2723 +#define OMAP_DMA_MCBSP2_TX 16
2724 +#define OMAP_DMA_MCBSP2_RX 17
2725 +#define OMAP_DMA_UART3_TX 18
2726 +#define OMAP_DMA_UART3_RX 19
2727 +#define OMAP_DMA_CAMERA_IF_RX 20
2728 +#define OMAP_DMA_MMC_TX 21
2729 +#define OMAP_DMA_MMC_RX 22
2730 +#define OMAP_DMA_NAND 23
2731 +#define OMAP_DMA_IRQ_LCD_LINE 24
2732 +#define OMAP_DMA_MEMORY_STICK 25
2733 +#define OMAP_DMA_USB_W2FC_RX0 26
2734 +#define OMAP_DMA_USB_W2FC_RX1 27
2735 +#define OMAP_DMA_USB_W2FC_RX2 28
2736 +#define OMAP_DMA_USB_W2FC_TX0 29
2737 +#define OMAP_DMA_USB_W2FC_TX1 30
2738 +#define OMAP_DMA_USB_W2FC_TX2 31
2739 +
2740 +/* These are only for 1610 */
2741 +#define OMAP_DMA_CRYPTO_DES_IN 32
2742 +#define OMAP_DMA_SPI_TX 33
2743 +#define OMAP_DMA_SPI_RX 34
2744 +#define OMAP_DMA_CRYPTO_HASH 35
2745 +#define OMAP_DMA_CCP_ATTN 36
2746 +#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
2747 +#define OMAP_DMA_CMT_APE_TX_CHAN_0 38
2748 +#define OMAP_DMA_CMT_APE_RV_CHAN_0 39
2749 +#define OMAP_DMA_CMT_APE_TX_CHAN_1 40
2750 +#define OMAP_DMA_CMT_APE_RV_CHAN_1 41
2751 +#define OMAP_DMA_CMT_APE_TX_CHAN_2 42
2752 +#define OMAP_DMA_CMT_APE_RV_CHAN_2 43
2753 +#define OMAP_DMA_CMT_APE_TX_CHAN_3 44
2754 +#define OMAP_DMA_CMT_APE_RV_CHAN_3 45
2755 +#define OMAP_DMA_CMT_APE_TX_CHAN_4 46
2756 +#define OMAP_DMA_CMT_APE_RV_CHAN_4 47
2757 +#define OMAP_DMA_CMT_APE_TX_CHAN_5 48
2758 +#define OMAP_DMA_CMT_APE_RV_CHAN_5 49
2759 +#define OMAP_DMA_CMT_APE_TX_CHAN_6 50
2760 +#define OMAP_DMA_CMT_APE_RV_CHAN_6 51
2761 +#define OMAP_DMA_CMT_APE_TX_CHAN_7 52
2762 +#define OMAP_DMA_CMT_APE_RV_CHAN_7 53
2763 +#define OMAP_DMA_MMC2_TX 54
2764 +#define OMAP_DMA_MMC2_RX 55
2765 +#define OMAP_DMA_CRYPTO_DES_OUT 56
2766 +
2767 +/* DMA channels for 24xx */
2768 +#define OMAP24XX_DMA_NO_DEVICE 0
2769 +#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */
2770 +#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */
2771 +#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */
2772 +#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
2773 +#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
2774 +#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
2775 +#define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */
2776 +#define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */
2777 +#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */
2778 +#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
2779 +#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
2780 +#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
2781 +#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
2782 +#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
2783 +#define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */
2784 +#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */
2785 +#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */
2786 +#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */
2787 +#define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */
2788 +#define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */
2789 +#define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
2790 +#define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */
2791 +#define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */
2792 +#define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */
2793 +#define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */
2794 +#define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */
2795 +#define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */
2796 +#define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */
2797 +#define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */
2798 +#define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
2799 +#define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
2800 +#define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */
2801 +#define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */
2802 +#define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */
2803 +#define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */
2804 +#define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */
2805 +#define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */
2806 +#define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
2807 +#define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
2808 +#define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */
2809 +#define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */
2810 +#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */
2811 +#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */
2812 +#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
2813 +#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
2814 +#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
2815 +#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
2816 +#define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */
2817 +#define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */
2818 +#define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */
2819 +#define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */
2820 +#define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
2821 +#define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
2822 +#define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
2823 +#define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
2824 +#define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
2825 +#define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
2826 +#define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
2827 +#define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
2828 +#define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
2829 +#define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
2830 +#define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
2831 +#define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
2832 +#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */
2833 +#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */
2834 +#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */
2835 +#define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */
2836 +#define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */
2837 +#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */
2838 +#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */
2839 +#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */
2840 +#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */
2841 +#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */
2842 +#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */
2843 +#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */
2844 +#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */
2845 +#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */
2846 +#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */
2847 +#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */
2848 +#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */
2849 +#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
2850 +#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */
2851 +#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */
2852 +#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */
2853 +#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */
2854 +#define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */
2855 +#define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */
2856 +#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */
2857 +#define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
2858 +#define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
2859 +#define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */
2860 +#define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */
2861 +#define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */
2862 +#define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */
2863 +#define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */
2864 +#define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */
2865 +#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
2866 +#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
2867 +
2868 +/* DMA request lines for 44xx */
2869 +#define OMAP44XX_DMA_DSS_DISPC_REQ 6 /* S_DMA_5 */
2870 +#define OMAP44XX_DMA_SYS_REQ2 7 /* S_DMA_6 */
2871 +#define OMAP44XX_DMA_ISS_REQ1 9 /* S_DMA_8 */
2872 +#define OMAP44XX_DMA_ISS_REQ2 10 /* S_DMA_9 */
2873 +#define OMAP44XX_DMA_ISS_REQ3 12 /* S_DMA_11 */
2874 +#define OMAP44XX_DMA_ISS_REQ4 13 /* S_DMA_12 */
2875 +#define OMAP44XX_DMA_DSS_RFBI_REQ 14 /* S_DMA_13 */
2876 +#define OMAP44XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
2877 +#define OMAP44XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
2878 +#define OMAP44XX_DMA_MCBSP2_TX 17 /* S_DMA_16 */
2879 +#define OMAP44XX_DMA_MCBSP2_RX 18 /* S_DMA_17 */
2880 +#define OMAP44XX_DMA_MCBSP3_TX 19 /* S_DMA_18 */
2881 +#define OMAP44XX_DMA_MCBSP3_RX 20 /* S_DMA_19 */
2882 +#define OMAP44XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
2883 +#define OMAP44XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
2884 +#define OMAP44XX_DMA_I2C3_TX 25 /* S_DMA_24 */
2885 +#define OMAP44XX_DMA_I2C3_RX 26 /* S_DMA_25 */
2886 +#define OMAP44XX_DMA_I2C1_TX 27 /* S_DMA_26 */
2887 +#define OMAP44XX_DMA_I2C1_RX 28 /* S_DMA_27 */
2888 +#define OMAP44XX_DMA_I2C2_TX 29 /* S_DMA_28 */
2889 +#define OMAP44XX_DMA_I2C2_RX 30 /* S_DMA_29 */
2890 +#define OMAP44XX_DMA_MCBSP4_TX 31 /* S_DMA_30 */
2891 +#define OMAP44XX_DMA_MCBSP4_RX 32 /* S_DMA_31 */
2892 +#define OMAP44XX_DMA_MCBSP1_TX 33 /* S_DMA_32 */
2893 +#define OMAP44XX_DMA_MCBSP1_RX 34 /* S_DMA_33 */
2894 +#define OMAP44XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
2895 +#define OMAP44XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
2896 +#define OMAP44XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
2897 +#define OMAP44XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
2898 +#define OMAP44XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
2899 +#define OMAP44XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
2900 +#define OMAP44XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
2901 +#define OMAP44XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
2902 +#define OMAP44XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
2903 +#define OMAP44XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
2904 +#define OMAP44XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
2905 +#define OMAP44XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
2906 +#define OMAP44XX_DMA_MMC2_TX 47 /* S_DMA_46 */
2907 +#define OMAP44XX_DMA_MMC2_RX 48 /* S_DMA_47 */
2908 +#define OMAP44XX_DMA_UART1_TX 49 /* S_DMA_48 */
2909 +#define OMAP44XX_DMA_UART1_RX 50 /* S_DMA_49 */
2910 +#define OMAP44XX_DMA_UART2_TX 51 /* S_DMA_50 */
2911 +#define OMAP44XX_DMA_UART2_RX 52 /* S_DMA_51 */
2912 +#define OMAP44XX_DMA_UART3_TX 53 /* S_DMA_52 */
2913 +#define OMAP44XX_DMA_UART3_RX 54 /* S_DMA_53 */
2914 +#define OMAP44XX_DMA_UART4_TX 55 /* S_DMA_54 */
2915 +#define OMAP44XX_DMA_UART4_RX 56 /* S_DMA_55 */
2916 +#define OMAP44XX_DMA_MMC4_TX 57 /* S_DMA_56 */
2917 +#define OMAP44XX_DMA_MMC4_RX 58 /* S_DMA_57 */
2918 +#define OMAP44XX_DMA_MMC5_TX 59 /* S_DMA_58 */
2919 +#define OMAP44XX_DMA_MMC5_RX 60 /* S_DMA_59 */
2920 +#define OMAP44XX_DMA_MMC1_TX 61 /* S_DMA_60 */
2921 +#define OMAP44XX_DMA_MMC1_RX 62 /* S_DMA_61 */
2922 +#define OMAP44XX_DMA_SYS_REQ3 64 /* S_DMA_63 */
2923 +#define OMAP44XX_DMA_MCPDM_UP 65 /* S_DMA_64 */
2924 +#define OMAP44XX_DMA_MCPDM_DL 66 /* S_DMA_65 */
2925 +#define OMAP44XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
2926 +#define OMAP44XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
2927 +#define OMAP44XX_DMA_DSS_DSI1_REQ0 72 /* S_DMA_71 */
2928 +#define OMAP44XX_DMA_DSS_DSI1_REQ1 73 /* S_DMA_72 */
2929 +#define OMAP44XX_DMA_DSS_DSI1_REQ2 74 /* S_DMA_73 */
2930 +#define OMAP44XX_DMA_DSS_DSI1_REQ3 75 /* S_DMA_74 */
2931 +#define OMAP44XX_DMA_DSS_HDMI_REQ 76 /* S_DMA_75 */
2932 +#define OMAP44XX_DMA_MMC3_TX 77 /* S_DMA_76 */
2933 +#define OMAP44XX_DMA_MMC3_RX 78 /* S_DMA_77 */
2934 +#define OMAP44XX_DMA_USIM_TX 79 /* S_DMA_78 */
2935 +#define OMAP44XX_DMA_USIM_RX 80 /* S_DMA_79 */
2936 +#define OMAP44XX_DMA_DSS_DSI2_REQ0 81 /* S_DMA_80 */
2937 +#define OMAP44XX_DMA_DSS_DSI2_REQ1 82 /* S_DMA_81 */
2938 +#define OMAP44XX_DMA_DSS_DSI2_REQ2 83 /* S_DMA_82 */
2939 +#define OMAP44XX_DMA_DSS_DSI2_REQ3 84 /* S_DMA_83 */
2940 +#define OMAP44XX_DMA_ABE_REQ0 101 /* S_DMA_100 */
2941 +#define OMAP44XX_DMA_ABE_REQ1 102 /* S_DMA_101 */
2942 +#define OMAP44XX_DMA_ABE_REQ2 103 /* S_DMA_102 */
2943 +#define OMAP44XX_DMA_ABE_REQ3 104 /* S_DMA_103 */
2944 +#define OMAP44XX_DMA_ABE_REQ4 105 /* S_DMA_104 */
2945 +#define OMAP44XX_DMA_ABE_REQ5 106 /* S_DMA_105 */
2946 +#define OMAP44XX_DMA_ABE_REQ6 107 /* S_DMA_106 */
2947 +#define OMAP44XX_DMA_ABE_REQ7 108 /* S_DMA_107 */
2948 +#define OMAP44XX_DMA_I2C4_TX 124 /* S_DMA_123 */
2949 +#define OMAP44XX_DMA_I2C4_RX 125 /* S_DMA_124 */
2950 +
2951 +/*----------------------------------------------------------------------------*/
2952 +
2953 +#define OMAP1_DMA_TOUT_IRQ (1 << 0)
2954 +#define OMAP_DMA_DROP_IRQ (1 << 1)
2955 +#define OMAP_DMA_HALF_IRQ (1 << 2)
2956 +#define OMAP_DMA_FRAME_IRQ (1 << 3)
2957 +#define OMAP_DMA_LAST_IRQ (1 << 4)
2958 +#define OMAP_DMA_BLOCK_IRQ (1 << 5)
2959 +#define OMAP1_DMA_SYNC_IRQ (1 << 6)
2960 +#define OMAP2_DMA_PKT_IRQ (1 << 7)
2961 +#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
2962 +#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
2963 +#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
2964 +#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
2965 +
2966 +#define OMAP_DMA_CCR_EN (1 << 7)
2967 +
2968 +#define OMAP_DMA_DATA_TYPE_S8 0x00
2969 +#define OMAP_DMA_DATA_TYPE_S16 0x01
2970 +#define OMAP_DMA_DATA_TYPE_S32 0x02
2971 +
2972 +#define OMAP_DMA_SYNC_ELEMENT 0x00
2973 +#define OMAP_DMA_SYNC_FRAME 0x01
2974 +#define OMAP_DMA_SYNC_BLOCK 0x02
2975 +#define OMAP_DMA_SYNC_PACKET 0x03
2976 +
2977 +#define OMAP_DMA_SRC_SYNC 0x01
2978 +#define OMAP_DMA_DST_SYNC 0x00
2979 +
2980 +#define OMAP_DMA_PORT_EMIFF 0x00
2981 +#define OMAP_DMA_PORT_EMIFS 0x01
2982 +#define OMAP_DMA_PORT_OCP_T1 0x02
2983 +#define OMAP_DMA_PORT_TIPB 0x03
2984 +#define OMAP_DMA_PORT_OCP_T2 0x04
2985 +#define OMAP_DMA_PORT_MPUI 0x05
2986 +
2987 +#define OMAP_DMA_AMODE_CONSTANT 0x00
2988 +#define OMAP_DMA_AMODE_POST_INC 0x01
2989 +#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
2990 +#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
2991 +
2992 +#define DMA_DEFAULT_FIFO_DEPTH 0x10
2993 +#define DMA_DEFAULT_ARB_RATE 0x01
2994 +/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
2995 +#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
2996 +#define DMA_THREAD_RESERVE_ONET (0x01 << 12)
2997 +#define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
2998 +#define DMA_THREAD_RESERVE_THREET (0x03 << 12)
2999 +#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
3000 +#define DMA_THREAD_FIFO_75 (0x01 << 14)
3001 +#define DMA_THREAD_FIFO_25 (0x02 << 14)
3002 +#define DMA_THREAD_FIFO_50 (0x03 << 14)
3003 +
3004 +/* DMA4_OCP_SYSCONFIG bits */
3005 +#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12)
3006 +#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
3007 +#define DMA_SYSCONFIG_EMUFREE (1 << 5)
3008 +#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3)
3009 +#define DMA_SYSCONFIG_SOFTRESET (1 << 2)
3010 +#define DMA_SYSCONFIG_AUTOIDLE (1 << 0)
3011 +
3012 +#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12)
3013 +#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3)
3014 +
3015 +#define DMA_IDLEMODE_SMARTIDLE 0x2
3016 +#define DMA_IDLEMODE_NO_IDLE 0x1
3017 +#define DMA_IDLEMODE_FORCE_IDLE 0x0
3018 +
3019 +/* Chaining modes*/
3020 +#ifndef CONFIG_ARCH_OMAP1
3021 +#define OMAP_DMA_STATIC_CHAIN 0x1
3022 +#define OMAP_DMA_DYNAMIC_CHAIN 0x2
3023 +#define OMAP_DMA_CHAIN_ACTIVE 0x1
3024 +#define OMAP_DMA_CHAIN_INACTIVE 0x0
3025 +#endif
3026 +
3027 +#define DMA_CH_PRIO_HIGH 0x1
3028 +#define DMA_CH_PRIO_LOW 0x0 /* Def */
3029 +
3030 +enum omap_dma_burst_mode {
3031 + OMAP_DMA_DATA_BURST_DIS = 0,
3032 + OMAP_DMA_DATA_BURST_4,
3033 + OMAP_DMA_DATA_BURST_8,
3034 + OMAP_DMA_DATA_BURST_16,
3035 +};
3036 +
3037 +enum end_type {
3038 + OMAP_DMA_LITTLE_ENDIAN = 0,
3039 + OMAP_DMA_BIG_ENDIAN
3040 +};
3041 +
3042 +enum omap_dma_color_mode {
3043 + OMAP_DMA_COLOR_DIS = 0,
3044 + OMAP_DMA_CONSTANT_FILL,
3045 + OMAP_DMA_TRANSPARENT_COPY
3046 +};
3047 +
3048 +enum omap_dma_write_mode {
3049 + OMAP_DMA_WRITE_NON_POSTED = 0,
3050 + OMAP_DMA_WRITE_POSTED,
3051 + OMAP_DMA_WRITE_LAST_NON_POSTED
3052 +};
3053 +
3054 +enum omap_dma_channel_mode {
3055 + OMAP_DMA_LCH_2D = 0,
3056 + OMAP_DMA_LCH_G,
3057 + OMAP_DMA_LCH_P,
3058 + OMAP_DMA_LCH_PD
3059 +};
3060 +
3061 +struct omap_dma_channel_params {
3062 + int data_type; /* data type 8,16,32 */
3063 + int elem_count; /* number of elements in a frame */
3064 + int frame_count; /* number of frames in a element */
3065 +
3066 + int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
3067 + int src_amode; /* constant, post increment, indexed,
3068 + double indexed */
3069 + unsigned long src_start; /* source address : physical */
3070 + int src_ei; /* source element index */
3071 + int src_fi; /* source frame index */
3072 +
3073 + int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
3074 + int dst_amode; /* constant, post increment, indexed,
3075 + double indexed */
3076 + unsigned long dst_start; /* source address : physical */
3077 + int dst_ei; /* source element index */
3078 + int dst_fi; /* source frame index */
3079 +
3080 + int trigger; /* trigger attached if the channel is
3081 + synchronized */
3082 + int sync_mode; /* sycn on element, frame , block or packet */
3083 + int src_or_dst_synch; /* source synch(1) or destination synch(0) */
3084 +
3085 + int ie; /* interrupt enabled */
3086 +
3087 + unsigned char read_prio;/* read priority */
3088 + unsigned char write_prio;/* write priority */
3089 +
3090 +#ifndef CONFIG_ARCH_OMAP1
3091 + enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
3092 +#endif
3093 +};
3094 +
3095 +
3096 +extern void omap_set_dma_priority(int lch, int dst_port, int priority);
3097 +extern int omap_request_dma(int dev_id, const char *dev_name,
3098 + void (*callback)(int lch, u16 ch_status, void *data),
3099 + void *data, int *dma_ch);
3100 +extern void omap_enable_dma_irq(int ch, u16 irq_bits);
3101 +extern void omap_disable_dma_irq(int ch, u16 irq_bits);
3102 +extern void omap_free_dma(int ch);
3103 +extern void omap_start_dma(int lch);
3104 +extern void omap_stop_dma(int lch);
3105 +extern void omap_set_dma_transfer_params(int lch, int data_type,
3106 + int elem_count, int frame_count,
3107 + int sync_mode,
3108 + int dma_trigger, int src_or_dst_synch);
3109 +extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
3110 + u32 color);
3111 +extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
3112 +extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
3113 +
3114 +extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
3115 + unsigned long src_start,
3116 + int src_ei, int src_fi);
3117 +extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
3118 +extern void omap_set_dma_src_data_pack(int lch, int enable);
3119 +extern void omap_set_dma_src_burst_mode(int lch,
3120 + enum omap_dma_burst_mode burst_mode);
3121 +
3122 +extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
3123 + unsigned long dest_start,
3124 + int dst_ei, int dst_fi);
3125 +extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
3126 +extern void omap_set_dma_dest_data_pack(int lch, int enable);
3127 +extern void omap_set_dma_dest_burst_mode(int lch,
3128 + enum omap_dma_burst_mode burst_mode);
3129 +
3130 +extern void omap_set_dma_params(int lch,
3131 + struct omap_dma_channel_params *params);
3132 +
3133 +extern void omap_dma_link_lch(int lch_head, int lch_queue);
3134 +extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
3135 +
3136 +extern int omap_set_dma_callback(int lch,
3137 + void (*callback)(int lch, u16 ch_status, void *data),
3138 + void *data);
3139 +extern dma_addr_t omap_get_dma_src_pos(int lch);
3140 +extern dma_addr_t omap_get_dma_dst_pos(int lch);
3141 +extern void omap_clear_dma(int lch);
3142 +extern int omap_get_dma_active_status(int lch);
3143 +extern int omap_dma_running(void);
3144 +extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
3145 + int tparams);
3146 +extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
3147 + unsigned char write_prio);
3148 +extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
3149 +extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
3150 +extern int omap_get_dma_index(int lch, int *ei, int *fi);
3151 +
3152 +void omap_dma_global_context_save(void);
3153 +void omap_dma_global_context_restore(void);
3154 +
3155 +extern void omap_dma_disable_irq(int lch);
3156 +
3157 +/* Chaining APIs */
3158 +#ifndef CONFIG_ARCH_OMAP1
3159 +extern int omap_request_dma_chain(int dev_id, const char *dev_name,
3160 + void (*callback) (int lch, u16 ch_status,
3161 + void *data),
3162 + int *chain_id, int no_of_chans,
3163 + int chain_mode,
3164 + struct omap_dma_channel_params params);
3165 +extern int omap_free_dma_chain(int chain_id);
3166 +extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
3167 + int dest_start, int elem_count,
3168 + int frame_count, void *callbk_data);
3169 +extern int omap_start_dma_chain_transfers(int chain_id);
3170 +extern int omap_stop_dma_chain_transfers(int chain_id);
3171 +extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
3172 +extern int omap_get_dma_chain_dst_pos(int chain_id);
3173 +extern int omap_get_dma_chain_src_pos(int chain_id);
3174 +
3175 +extern int omap_modify_dma_chain_params(int chain_id,
3176 + struct omap_dma_channel_params params);
3177 +extern int omap_dma_chain_status(int chain_id);
3178 +#endif
3179 +
3180 +#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
3181 +#include <mach/lcd_dma.h>
3182 +#else
3183 +static inline int omap_lcd_dma_running(void)
3184 +{
3185 + return 0;
3186 +}
3187 +#endif
3188 +
3189 +#endif /* __ASM_ARCH_DMA_H */
3190 --- /dev/null
3191 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/dmtimer.h
3192 @@ -0,0 +1,84 @@
3193 +/*
3194 + * arch/arm/plat-omap/include/mach/dmtimer.h
3195 + *
3196 + * OMAP Dual-Mode Timers
3197 + *
3198 + * Copyright (C) 2005 Nokia Corporation
3199 + * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
3200 + * PWM and clock framwork support by Timo Teras.
3201 + *
3202 + * This program is free software; you can redistribute it and/or modify it
3203 + * under the terms of the GNU General Public License as published by the
3204 + * Free Software Foundation; either version 2 of the License, or (at your
3205 + * option) any later version.
3206 + *
3207 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3208 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3209 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3210 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3211 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3212 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3213 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3214 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3215 + *
3216 + * You should have received a copy of the GNU General Public License along
3217 + * with this program; if not, write to the Free Software Foundation, Inc.,
3218 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3219 + */
3220 +
3221 +#ifndef __ASM_ARCH_DMTIMER_H
3222 +#define __ASM_ARCH_DMTIMER_H
3223 +
3224 +/* clock sources */
3225 +#define OMAP_TIMER_SRC_SYS_CLK 0x00
3226 +#define OMAP_TIMER_SRC_32_KHZ 0x01
3227 +#define OMAP_TIMER_SRC_EXT_CLK 0x02
3228 +
3229 +/* timer interrupt enable bits */
3230 +#define OMAP_TIMER_INT_CAPTURE (1 << 2)
3231 +#define OMAP_TIMER_INT_OVERFLOW (1 << 1)
3232 +#define OMAP_TIMER_INT_MATCH (1 << 0)
3233 +
3234 +/* trigger types */
3235 +#define OMAP_TIMER_TRIGGER_NONE 0x00
3236 +#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
3237 +#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
3238 +
3239 +struct omap_dm_timer;
3240 +struct clk;
3241 +
3242 +int omap_dm_timer_init(void);
3243 +
3244 +struct omap_dm_timer *omap_dm_timer_request(void);
3245 +struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
3246 +void omap_dm_timer_free(struct omap_dm_timer *timer);
3247 +void omap_dm_timer_enable(struct omap_dm_timer *timer);
3248 +void omap_dm_timer_disable(struct omap_dm_timer *timer);
3249 +
3250 +int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
3251 +
3252 +u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
3253 +struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
3254 +
3255 +void omap_dm_timer_trigger(struct omap_dm_timer *timer);
3256 +void omap_dm_timer_start(struct omap_dm_timer *timer);
3257 +void omap_dm_timer_stop(struct omap_dm_timer *timer);
3258 +
3259 +int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
3260 +void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
3261 +void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
3262 +void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
3263 +void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
3264 +void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
3265 +
3266 +void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
3267 +
3268 +unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
3269 +void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
3270 +unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
3271 +void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
3272 +
3273 +int omap_dm_timers_active(void);
3274 +
3275 +
3276 +#endif /* __ASM_ARCH_DMTIMER_H */
3277 --- /dev/null
3278 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/dsp_common.h
3279 @@ -0,0 +1,40 @@
3280 +/*
3281 + * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
3282 + *
3283 + * Copyright (C) 2004-2006 Nokia Corporation. All rights reserved.
3284 + *
3285 + * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
3286 + *
3287 + * This program is free software; you can redistribute it and/or
3288 + * modify it under the terms of the GNU General Public License
3289 + * version 2 as published by the Free Software Foundation.
3290 + *
3291 + * This program is distributed in the hope that it will be useful, but
3292 + * WITHOUT ANY WARRANTY; without even the implied warranty of
3293 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
3294 + * General Public License for more details.
3295 + *
3296 + * You should have received a copy of the GNU General Public License
3297 + * along with this program; if not, write to the Free Software
3298 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
3299 + * 02110-1301 USA
3300 + *
3301 + */
3302 +
3303 +#ifndef ASM_ARCH_DSP_COMMON_H
3304 +#define ASM_ARCH_DSP_COMMON_H
3305 +
3306 +#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_OMAP_MMU_FWK)
3307 +extern void omap_dsp_request_mpui(void);
3308 +extern void omap_dsp_release_mpui(void);
3309 +extern int omap_dsp_request_mem(void);
3310 +extern int omap_dsp_release_mem(void);
3311 +#else
3312 +static inline int omap_dsp_request_mem(void)
3313 +{
3314 + return 0;
3315 +}
3316 +#define omap_dsp_release_mem() do {} while (0)
3317 +#endif
3318 +
3319 +#endif /* ASM_ARCH_DSP_COMMON_H */
3320 --- /dev/null
3321 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/fpga.h
3322 @@ -0,0 +1,197 @@
3323 +/*
3324 + * arch/arm/plat-omap/include/mach/fpga.h
3325 + *
3326 + * Interrupt handler for OMAP-1510 FPGA
3327 + *
3328 + * Copyright (C) 2001 RidgeRun, Inc.
3329 + * Author: Greg Lonnon <glonnon@ridgerun.com>
3330 + *
3331 + * Copyright (C) 2002 MontaVista Software, Inc.
3332 + *
3333 + * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
3334 + * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
3335 + *
3336 + * This program is free software; you can redistribute it and/or modify
3337 + * it under the terms of the GNU General Public License version 2 as
3338 + * published by the Free Software Foundation.
3339 + */
3340 +
3341 +#ifndef __ASM_ARCH_OMAP_FPGA_H
3342 +#define __ASM_ARCH_OMAP_FPGA_H
3343 +
3344 +#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
3345 +extern void omap1510_fpga_init_irq(void);
3346 +#else
3347 +#define omap1510_fpga_init_irq() (0)
3348 +#endif
3349 +
3350 +#define fpga_read(reg) __raw_readb(reg)
3351 +#define fpga_write(val, reg) __raw_writeb(val, reg)
3352 +
3353 +/*
3354 + * ---------------------------------------------------------------------------
3355 + * H2/P2 Debug board FPGA
3356 + * ---------------------------------------------------------------------------
3357 + */
3358 +/* maps in the FPGA registers and the ETHR registers */
3359 +#define H2P2_DBG_FPGA_BASE IOMEM(0xE8000000) /* VA */
3360 +#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
3361 +#define H2P2_DBG_FPGA_START 0x04000000 /* PA */
3362 +
3363 +#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
3364 +#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
3365 +#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */
3366 +#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */
3367 +#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */
3368 +#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */
3369 +#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
3370 +#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
3371 +
3372 +/* NOTE: most boards don't have a static mapping for the FPGA ... */
3373 +struct h2p2_dbg_fpga {
3374 + /* offset 0x00 */
3375 + u16 smc91x[8];
3376 + /* offset 0x10 */
3377 + u16 fpga_rev;
3378 + u16 board_rev;
3379 + u16 gpio_outputs;
3380 + u16 leds;
3381 + /* offset 0x18 */
3382 + u16 misc_inputs;
3383 + u16 lan_status;
3384 + u16 lan_reset;
3385 + u16 reserved0;
3386 + /* offset 0x20 */
3387 + u16 ps2_data;
3388 + u16 ps2_ctrl;
3389 + /* plus also 4 rs232 ports ... */
3390 +};
3391 +
3392 +/* LEDs definition on debug board (16 LEDs, all physically green) */
3393 +#define H2P2_DBG_FPGA_LED_GREEN (1 << 15)
3394 +#define H2P2_DBG_FPGA_LED_AMBER (1 << 14)
3395 +#define H2P2_DBG_FPGA_LED_RED (1 << 13)
3396 +#define H2P2_DBG_FPGA_LED_BLUE (1 << 12)
3397 +/* cpu0 load-meter LEDs */
3398 +#define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ...
3399 +#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11
3400 +#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
3401 +
3402 +#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0)
3403 +#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1)
3404 +
3405 +/*
3406 + * ---------------------------------------------------------------------------
3407 + * OMAP-1510 FPGA
3408 + * ---------------------------------------------------------------------------
3409 + */
3410 +#define OMAP1510_FPGA_BASE IOMEM(0xE8000000) /* VA */
3411 +#define OMAP1510_FPGA_SIZE SZ_4K
3412 +#define OMAP1510_FPGA_START 0x08000000 /* PA */
3413 +
3414 +/* Revision */
3415 +#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
3416 +#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1)
3417 +
3418 +#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2)
3419 +#define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3)
3420 +#define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4)
3421 +#define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5)
3422 +
3423 +/* Interrupt status */
3424 +#define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6)
3425 +#define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7)
3426 +
3427 +/* Interrupt mask */
3428 +#define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8)
3429 +#define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9)
3430 +
3431 +/* Reset registers */
3432 +#define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa)
3433 +#define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb)
3434 +
3435 +#define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc)
3436 +#define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe)
3437 +#define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf)
3438 +#define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14)
3439 +#define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15)
3440 +#define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16)
3441 +#define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18)
3442 +#define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100)
3443 +#define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101)
3444 +#define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102)
3445 +
3446 +#define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204)
3447 +
3448 +#define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205)
3449 +#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206)
3450 +#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207)
3451 +#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208)
3452 +#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209)
3453 +#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a)
3454 +#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b)
3455 +#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c)
3456 +#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d)
3457 +#define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e)
3458 +#define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210)
3459 +
3460 +#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300)
3461 +
3462 +/*
3463 + * Power up Giga UART driver, turn on HID clock.
3464 + * Turn off BT power, since we're not using it and it
3465 + * draws power.
3466 + */
3467 +#define OMAP1510_FPGA_RESET_VALUE 0x42
3468 +
3469 +#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7)
3470 +#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6)
3471 +#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5)
3472 +#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4)
3473 +#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3)
3474 +#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2)
3475 +#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1)
3476 +#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0)
3477 +
3478 +/*
3479 + * Innovator/OMAP1510 FPGA HID register bit definitions
3480 + */
3481 +#define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */
3482 +#define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */
3483 +#define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */
3484 +#define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */
3485 +#define OMAP1510_FPGA_HID_MISO (1<<4) /* input */
3486 +#define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */
3487 +#define OMAP1510_FPGA_HID_rsrvd (1<<6)
3488 +#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
3489 +
3490 +/* The FPGA IRQ is cascaded through GPIO_13 */
3491 +#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
3492 +
3493 +/* IRQ Numbers for interrupts muxed through the FPGA */
3494 +#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0)
3495 +#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1)
3496 +#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2)
3497 +#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3)
3498 +#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4)
3499 +#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5)
3500 +#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6)
3501 +#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7)
3502 +#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8)
3503 +#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9)
3504 +#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10)
3505 +#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11)
3506 +#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12)
3507 +#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13)
3508 +#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14)
3509 +#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15)
3510 +#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16)
3511 +#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17)
3512 +#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18)
3513 +#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19)
3514 +#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20)
3515 +#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21)
3516 +#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22)
3517 +#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23)
3518 +
3519 +#endif
3520 --- /dev/null
3521 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/gpio.h
3522 @@ -0,0 +1,129 @@
3523 +/*
3524 + * arch/arm/plat-omap/include/mach/gpio.h
3525 + *
3526 + * OMAP GPIO handling defines and functions
3527 + *
3528 + * Copyright (C) 2003-2005 Nokia Corporation
3529 + *
3530 + * Written by Juha Yrjölä <juha.yrjola@nokia.com>
3531 + *
3532 + * This program is free software; you can redistribute it and/or modify
3533 + * it under the terms of the GNU General Public License as published by
3534 + * the Free Software Foundation; either version 2 of the License, or
3535 + * (at your option) any later version.
3536 + *
3537 + * This program is distributed in the hope that it will be useful,
3538 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3539 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3540 + * GNU General Public License for more details.
3541 + *
3542 + * You should have received a copy of the GNU General Public License
3543 + * along with this program; if not, write to the Free Software
3544 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3545 + *
3546 + */
3547 +
3548 +#ifndef __ASM_ARCH_OMAP_GPIO_H
3549 +#define __ASM_ARCH_OMAP_GPIO_H
3550 +
3551 +#include <linux/io.h>
3552 +#include <mach/irqs.h>
3553 +
3554 +#define OMAP1_MPUIO_BASE 0xfffb5000
3555 +
3556 +#if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850))
3557 +
3558 +#define OMAP_MPUIO_INPUT_LATCH 0x00
3559 +#define OMAP_MPUIO_OUTPUT 0x02
3560 +#define OMAP_MPUIO_IO_CNTL 0x04
3561 +#define OMAP_MPUIO_KBR_LATCH 0x08
3562 +#define OMAP_MPUIO_KBC 0x0a
3563 +#define OMAP_MPUIO_GPIO_EVENT_MODE 0x0c
3564 +#define OMAP_MPUIO_GPIO_INT_EDGE 0x0e
3565 +#define OMAP_MPUIO_KBD_INT 0x10
3566 +#define OMAP_MPUIO_GPIO_INT 0x12
3567 +#define OMAP_MPUIO_KBD_MASKIT 0x14
3568 +#define OMAP_MPUIO_GPIO_MASKIT 0x16
3569 +#define OMAP_MPUIO_GPIO_DEBOUNCING 0x18
3570 +#define OMAP_MPUIO_LATCH 0x1a
3571 +#else
3572 +#define OMAP_MPUIO_INPUT_LATCH 0x00
3573 +#define OMAP_MPUIO_OUTPUT 0x04
3574 +#define OMAP_MPUIO_IO_CNTL 0x08
3575 +#define OMAP_MPUIO_KBR_LATCH 0x10
3576 +#define OMAP_MPUIO_KBC 0x14
3577 +#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
3578 +#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
3579 +#define OMAP_MPUIO_KBD_INT 0x20
3580 +#define OMAP_MPUIO_GPIO_INT 0x24
3581 +#define OMAP_MPUIO_KBD_MASKIT 0x28
3582 +#define OMAP_MPUIO_GPIO_MASKIT 0x2c
3583 +#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
3584 +#define OMAP_MPUIO_LATCH 0x34
3585 +#endif
3586 +
3587 +#define OMAP34XX_NR_GPIOS 6
3588 +
3589 +#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
3590 +#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
3591 +
3592 +#define OMAP_GPIO_IRQ(nr) (OMAP_GPIO_IS_MPUIO(nr) ? \
3593 + IH_MPUIO_BASE + ((nr) & 0x0f) : \
3594 + IH_GPIO_BASE + (nr))
3595 +
3596 +extern int omap_gpio_init(void); /* Call from board init only */
3597 +extern void omap2_gpio_prepare_for_retention(void);
3598 +extern void omap2_gpio_resume_after_retention(void);
3599 +extern void omap_set_gpio_debounce(int gpio, int enable);
3600 +extern void omap_set_gpio_debounce_time(int gpio, int enable);
3601 +extern void omap_gpio_save_context(void);
3602 +extern void omap_gpio_restore_context(void);
3603 +/*-------------------------------------------------------------------------*/
3604 +
3605 +/* Wrappers for "new style" GPIO calls, using the new infrastructure
3606 + * which lets us plug in FPGA, I2C, and other implementations.
3607 + * *
3608 + * The original OMAP-specfic calls should eventually be removed.
3609 + */
3610 +
3611 +#include <linux/errno.h>
3612 +#include <asm-generic/gpio.h>
3613 +
3614 +static inline int gpio_get_value(unsigned gpio)
3615 +{
3616 + return __gpio_get_value(gpio);
3617 +}
3618 +
3619 +static inline void gpio_set_value(unsigned gpio, int value)
3620 +{
3621 + __gpio_set_value(gpio, value);
3622 +}
3623 +
3624 +static inline int gpio_cansleep(unsigned gpio)
3625 +{
3626 + return __gpio_cansleep(gpio);
3627 +}
3628 +
3629 +static inline int gpio_to_irq(unsigned gpio)
3630 +{
3631 + return __gpio_to_irq(gpio);
3632 +}
3633 +
3634 +static inline int irq_to_gpio(unsigned irq)
3635 +{
3636 + int tmp;
3637 +
3638 + /* omap1 SOC mpuio */
3639 + if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16)))
3640 + return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES;
3641 +
3642 + /* SOC gpio */
3643 + tmp = irq - IH_GPIO_BASE;
3644 + if (tmp < OMAP_MAX_GPIO_LINES)
3645 + return tmp;
3646 +
3647 + /* we don't supply reverse mappings for non-SOC gpios */
3648 + return -EIO;
3649 +}
3650 +
3651 +#endif
3652 --- /dev/null
3653 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/gpio-switch.h
3654 @@ -0,0 +1,54 @@
3655 +/*
3656 + * GPIO switch definitions
3657 + *
3658 + * Copyright (C) 2006 Nokia Corporation
3659 + *
3660 + * This program is free software; you can redistribute it and/or modify
3661 + * it under the terms of the GNU General Public License version 2 as
3662 + * published by the Free Software Foundation.
3663 + */
3664 +
3665 +#ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H
3666 +#define __ASM_ARCH_OMAP_GPIO_SWITCH_H
3667 +
3668 +#include <linux/types.h>
3669 +
3670 +/* Cover:
3671 + * high -> closed
3672 + * low -> open
3673 + * Connection:
3674 + * high -> connected
3675 + * low -> disconnected
3676 + * Activity:
3677 + * high -> active
3678 + * low -> inactive
3679 + *
3680 + */
3681 +#define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000
3682 +#define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001
3683 +#define OMAP_GPIO_SWITCH_TYPE_ACTIVITY 0x0002
3684 +#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001
3685 +#define OMAP_GPIO_SWITCH_FLAG_OUTPUT 0x0002
3686 +
3687 +struct omap_gpio_switch {
3688 + const char *name;
3689 + s16 gpio;
3690 + unsigned flags:4;
3691 + unsigned type:4;
3692 +
3693 + /* Time in ms to debounce when transitioning from
3694 + * inactive state to active state. */
3695 + u16 debounce_rising;
3696 + /* Same for transition from active to inactive state. */
3697 + u16 debounce_falling;
3698 +
3699 + /* notify board-specific code about state changes */
3700 + void (* notify)(void *data, int state);
3701 + void *notify_data;
3702 +};
3703 +
3704 +/* Call at init time only */
3705 +extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl,
3706 + int count);
3707 +
3708 +#endif
3709 --- /dev/null
3710 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/gpmc.h
3711 @@ -0,0 +1,115 @@
3712 +/*
3713 + * General-Purpose Memory Controller for OMAP2
3714 + *
3715 + * Copyright (C) 2005-2006 Nokia Corporation
3716 + *
3717 + * This program is free software; you can redistribute it and/or modify
3718 + * it under the terms of the GNU General Public License version 2 as
3719 + * published by the Free Software Foundation.
3720 + */
3721 +
3722 +#ifndef __OMAP2_GPMC_H
3723 +#define __OMAP2_GPMC_H
3724 +
3725 +/* Maximum Number of Chip Selects */
3726 +#define GPMC_CS_NUM 8
3727 +
3728 +#define GPMC_CS_CONFIG1 0x00
3729 +#define GPMC_CS_CONFIG2 0x04
3730 +#define GPMC_CS_CONFIG3 0x08
3731 +#define GPMC_CS_CONFIG4 0x0c
3732 +#define GPMC_CS_CONFIG5 0x10
3733 +#define GPMC_CS_CONFIG6 0x14
3734 +#define GPMC_CS_CONFIG7 0x18
3735 +#define GPMC_CS_NAND_COMMAND 0x1c
3736 +#define GPMC_CS_NAND_ADDRESS 0x20
3737 +#define GPMC_CS_NAND_DATA 0x24
3738 +
3739 +#define GPMC_CONFIG 0x50
3740 +#define GPMC_STATUS 0x54
3741 +
3742 +#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
3743 +#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
3744 +#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
3745 +#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
3746 +#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
3747 +#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
3748 +#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
3749 +#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
3750 +#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
3751 +#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
3752 +#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
3753 +#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
3754 +#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
3755 +#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
3756 +#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
3757 +#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
3758 +#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
3759 +#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(2)
3760 +#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
3761 +#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
3762 +#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
3763 +#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
3764 +#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
3765 +#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
3766 +#define GPMC_CONFIG7_CSVALID (1 << 6)
3767 +
3768 +/*
3769 + * Note that all values in this struct are in nanoseconds, while
3770 + * the register values are in gpmc_fck cycles.
3771 + */
3772 +struct gpmc_timings {
3773 + /* Minimum clock period for synchronous mode */
3774 + u16 sync_clk;
3775 +
3776 + /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
3777 + u16 cs_on; /* Assertion time */
3778 + u16 cs_rd_off; /* Read deassertion time */
3779 + u16 cs_wr_off; /* Write deassertion time */
3780 +
3781 + /* ADV signal timings corresponding to GPMC_CONFIG3 */
3782 + u16 adv_on; /* Assertion time */
3783 + u16 adv_rd_off; /* Read deassertion time */
3784 + u16 adv_wr_off; /* Write deassertion time */
3785 +
3786 + /* WE signals timings corresponding to GPMC_CONFIG4 */
3787 + u16 we_on; /* WE assertion time */
3788 + u16 we_off; /* WE deassertion time */
3789 +
3790 + /* OE signals timings corresponding to GPMC_CONFIG4 */
3791 + u16 oe_on; /* OE assertion time */
3792 + u16 oe_off; /* OE deassertion time */
3793 +
3794 + /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
3795 + u16 page_burst_access; /* Multiple access word delay */
3796 + u16 access; /* Start-cycle to first data valid delay */
3797 + u16 rd_cycle; /* Total read cycle time */
3798 + u16 wr_cycle; /* Total write cycle time */
3799 +
3800 + /* The following are only on OMAP3430 */
3801 + u16 wr_access; /* WRACCESSTIME */
3802 + u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
3803 +};
3804 +
3805 +extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
3806 +extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
3807 +extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
3808 +extern unsigned long gpmc_get_fclk_period(void);
3809 +
3810 +extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
3811 +extern u32 gpmc_cs_read_reg(int cs, int idx);
3812 +extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
3813 +extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
3814 +extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
3815 +extern void gpmc_cs_free(int cs);
3816 +extern int gpmc_cs_set_reserved(int cs, int reserved);
3817 +extern int gpmc_cs_reserved(int cs);
3818 +extern int gpmc_prefetch_enable(int cs, int dma_mode,
3819 + unsigned int u32_count, int is_write);
3820 +extern void gpmc_prefetch_reset(void);
3821 +extern int gpmc_prefetch_status(void);
3822 +extern void omap3_gpmc_save_context(void);
3823 +extern void omap3_gpmc_restore_context(void);
3824 +extern void __init gpmc_init(void);
3825 +
3826 +#endif
3827 --- /dev/null
3828 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/gpmc-smc91x.h
3829 @@ -0,0 +1,42 @@
3830 +/*
3831 + * arch/arm/plat-omap/include/mach/gpmc-smc91x.h
3832 + *
3833 + * Copyright (C) 2009 Nokia Corporation
3834 + *
3835 + * This program is free software; you can redistribute it and/or modify
3836 + * it under the terms of the GNU General Public License version 2 as
3837 + * published by the Free Software Foundation.
3838 + */
3839 +
3840 +#ifndef __ASM_ARCH_OMAP_GPMC_SMC91X_H__
3841 +
3842 +#define GPMC_TIMINGS_SMC91C96 (1 << 4)
3843 +#define GPMC_MUX_ADD_DATA (1 << 5) /* GPMC_CONFIG1_MUXADDDATA */
3844 +#define GPMC_READ_MON (1 << 6) /* GPMC_CONFIG1_WAIT_READ_MON */
3845 +#define GPMC_WRITE_MON (1 << 7) /* GPMC_CONFIG1_WAIT_WRITE_MON */
3846 +
3847 +struct omap_smc91x_platform_data {
3848 + int cs;
3849 + int gpio_irq;
3850 + int gpio_pwrdwn;
3851 + int gpio_reset;
3852 + int wait_pin; /* Optional GPMC_CONFIG1_WAITPINSELECT */
3853 + u32 flags;
3854 + int (*retime)(void);
3855 +};
3856 +
3857 +#if defined(CONFIG_SMC91X) || \
3858 + defined(CONFIG_SMC91X_MODULE)
3859 +
3860 +extern void gpmc_smc91x_init(struct omap_smc91x_platform_data *d);
3861 +
3862 +#else
3863 +
3864 +#define board_smc91x_data NULL
3865 +
3866 +static inline void gpmc_smc91x_init(struct omap_smc91x_platform_data *d)
3867 +{
3868 +}
3869 +
3870 +#endif
3871 +#endif
3872 --- /dev/null
3873 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/hardware.h
3874 @@ -0,0 +1,290 @@
3875 +/*
3876 + * arch/arm/plat-omap/include/mach/hardware.h
3877 + *
3878 + * Hardware definitions for TI OMAP processors and boards
3879 + *
3880 + * NOTE: Please put device driver specific defines into a separate header
3881 + * file for each driver.
3882 + *
3883 + * Copyright (C) 2001 RidgeRun, Inc.
3884 + * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
3885 + *
3886 + * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
3887 + * and Dirk Behme <dirk.behme@de.bosch.com>
3888 + *
3889 + * This program is free software; you can redistribute it and/or modify it
3890 + * under the terms of the GNU General Public License as published by the
3891 + * Free Software Foundation; either version 2 of the License, or (at your
3892 + * option) any later version.
3893 + *
3894 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3895 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3896 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3897 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3898 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3899 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3900 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3901 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3902 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3903 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3904 + *
3905 + * You should have received a copy of the GNU General Public License along
3906 + * with this program; if not, write to the Free Software Foundation, Inc.,
3907 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3908 + */
3909 +
3910 +#ifndef __ASM_ARCH_OMAP_HARDWARE_H
3911 +#define __ASM_ARCH_OMAP_HARDWARE_H
3912 +
3913 +#include <asm/sizes.h>
3914 +#ifndef __ASSEMBLER__
3915 +#include <asm/types.h>
3916 +#include <plat/cpu.h>
3917 +#endif
3918 +#include <plat/serial.h>
3919 +
3920 +/*
3921 + * ---------------------------------------------------------------------------
3922 + * Common definitions for all OMAP processors
3923 + * NOTE: Put all processor or board specific parts to the special header
3924 + * files.
3925 + * ---------------------------------------------------------------------------
3926 + */
3927 +
3928 +/*
3929 + * ----------------------------------------------------------------------------
3930 + * Timers
3931 + * ----------------------------------------------------------------------------
3932 + */
3933 +#define OMAP_MPU_TIMER1_BASE (0xfffec500)
3934 +#define OMAP_MPU_TIMER2_BASE (0xfffec600)
3935 +#define OMAP_MPU_TIMER3_BASE (0xfffec700)
3936 +#define MPU_TIMER_FREE (1 << 6)
3937 +#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
3938 +#define MPU_TIMER_AR (1 << 1)
3939 +#define MPU_TIMER_ST (1 << 0)
3940 +
3941 +/*
3942 + * ----------------------------------------------------------------------------
3943 + * Clocks
3944 + * ----------------------------------------------------------------------------
3945 + */
3946 +#define CLKGEN_REG_BASE (0xfffece00)
3947 +#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
3948 +#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
3949 +#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
3950 +#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
3951 +#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
3952 +#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
3953 +#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
3954 +#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
3955 +
3956 +#define CK_RATEF 1
3957 +#define CK_IDLEF 2
3958 +#define CK_ENABLEF 4
3959 +#define CK_SELECTF 8
3960 +#define SETARM_IDLE_SHIFT
3961 +
3962 +/* DPLL control registers */
3963 +#define DPLL_CTL (0xfffecf00)
3964 +
3965 +/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
3966 +#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
3967 +#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
3968 +#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
3969 +#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
3970 +#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
3971 +
3972 +/*
3973 + * ---------------------------------------------------------------------------
3974 + * UPLD
3975 + * ---------------------------------------------------------------------------
3976 + */
3977 +#define ULPD_REG_BASE (0xfffe0800)
3978 +#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
3979 +#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
3980 +#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
3981 +# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
3982 +# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
3983 +#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
3984 +# define SOFT_UDC_REQ (1 << 4)
3985 +# define SOFT_USB_CLK_REQ (1 << 3)
3986 +# define SOFT_DPLL_REQ (1 << 0)
3987 +#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
3988 +#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
3989 +#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
3990 +#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
3991 +#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
3992 +# define DIS_MMC2_DPLL_REQ (1 << 11)
3993 +# define DIS_MMC1_DPLL_REQ (1 << 10)
3994 +# define DIS_UART3_DPLL_REQ (1 << 9)
3995 +# define DIS_UART2_DPLL_REQ (1 << 8)
3996 +# define DIS_UART1_DPLL_REQ (1 << 7)
3997 +# define DIS_USB_HOST_DPLL_REQ (1 << 6)
3998 +#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
3999 +#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
4000 +
4001 +/*
4002 + * ---------------------------------------------------------------------------
4003 + * Watchdog timer
4004 + * ---------------------------------------------------------------------------
4005 + */
4006 +
4007 +/* Watchdog timer within the OMAP3.2 gigacell */
4008 +#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
4009 +#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
4010 +#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
4011 +#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
4012 +#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
4013 +
4014 +/*
4015 + * ---------------------------------------------------------------------------
4016 + * Interrupts
4017 + * ---------------------------------------------------------------------------
4018 + */
4019 +#ifdef CONFIG_ARCH_OMAP1
4020 +
4021 +/*
4022 + * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
4023 + * or something similar.. -- PFM.
4024 + */
4025 +
4026 +#define OMAP_IH1_BASE 0xfffecb00
4027 +#define OMAP_IH2_BASE 0xfffe0000
4028 +
4029 +#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
4030 +#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
4031 +#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
4032 +#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
4033 +#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
4034 +#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
4035 +#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
4036 +
4037 +#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
4038 +#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
4039 +#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
4040 +#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
4041 +#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
4042 +#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
4043 +#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
4044 +
4045 +#define IRQ_ITR_REG_OFFSET 0x00
4046 +#define IRQ_MIR_REG_OFFSET 0x04
4047 +#define IRQ_SIR_IRQ_REG_OFFSET 0x10
4048 +#define IRQ_SIR_FIQ_REG_OFFSET 0x14
4049 +#define IRQ_CONTROL_REG_OFFSET 0x18
4050 +#define IRQ_ISR_REG_OFFSET 0x9c
4051 +#define IRQ_ILR0_REG_OFFSET 0x1c
4052 +#define IRQ_GMR_REG_OFFSET 0xa0
4053 +
4054 +#endif
4055 +
4056 +/*
4057 + * ----------------------------------------------------------------------------
4058 + * System control registers
4059 + * ----------------------------------------------------------------------------
4060 + */
4061 +#define MOD_CONF_CTRL_0 0xfffe1080
4062 +#define MOD_CONF_CTRL_1 0xfffe1110
4063 +
4064 +/*
4065 + * ----------------------------------------------------------------------------
4066 + * Pin multiplexing registers
4067 + * ----------------------------------------------------------------------------
4068 + */
4069 +#define FUNC_MUX_CTRL_0 0xfffe1000
4070 +#define FUNC_MUX_CTRL_1 0xfffe1004
4071 +#define FUNC_MUX_CTRL_2 0xfffe1008
4072 +#define COMP_MODE_CTRL_0 0xfffe100c
4073 +#define FUNC_MUX_CTRL_3 0xfffe1010
4074 +#define FUNC_MUX_CTRL_4 0xfffe1014
4075 +#define FUNC_MUX_CTRL_5 0xfffe1018
4076 +#define FUNC_MUX_CTRL_6 0xfffe101C
4077 +#define FUNC_MUX_CTRL_7 0xfffe1020
4078 +#define FUNC_MUX_CTRL_8 0xfffe1024
4079 +#define FUNC_MUX_CTRL_9 0xfffe1028
4080 +#define FUNC_MUX_CTRL_A 0xfffe102C
4081 +#define FUNC_MUX_CTRL_B 0xfffe1030
4082 +#define FUNC_MUX_CTRL_C 0xfffe1034
4083 +#define FUNC_MUX_CTRL_D 0xfffe1038
4084 +#define PULL_DWN_CTRL_0 0xfffe1040
4085 +#define PULL_DWN_CTRL_1 0xfffe1044
4086 +#define PULL_DWN_CTRL_2 0xfffe1048
4087 +#define PULL_DWN_CTRL_3 0xfffe104c
4088 +#define PULL_DWN_CTRL_4 0xfffe10ac
4089 +
4090 +/* OMAP-1610 specific multiplexing registers */
4091 +#define FUNC_MUX_CTRL_E 0xfffe1090
4092 +#define FUNC_MUX_CTRL_F 0xfffe1094
4093 +#define FUNC_MUX_CTRL_10 0xfffe1098
4094 +#define FUNC_MUX_CTRL_11 0xfffe109c
4095 +#define FUNC_MUX_CTRL_12 0xfffe10a0
4096 +#define PU_PD_SEL_0 0xfffe10b4
4097 +#define PU_PD_SEL_1 0xfffe10b8
4098 +#define PU_PD_SEL_2 0xfffe10bc
4099 +#define PU_PD_SEL_3 0xfffe10c0
4100 +#define PU_PD_SEL_4 0xfffe10c4
4101 +
4102 +/* Timer32K for 1610 and 1710*/
4103 +#define OMAP_TIMER32K_BASE 0xFFFBC400
4104 +
4105 +/*
4106 + * ---------------------------------------------------------------------------
4107 + * TIPB bus interface
4108 + * ---------------------------------------------------------------------------
4109 + */
4110 +#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
4111 +#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
4112 +#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
4113 +#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
4114 +
4115 +/*
4116 + * ----------------------------------------------------------------------------
4117 + * MPUI interface
4118 + * ----------------------------------------------------------------------------
4119 + */
4120 +#define MPUI_BASE (0xfffec900)
4121 +#define MPUI_CTRL (MPUI_BASE + 0x0)
4122 +#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
4123 +#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
4124 +#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
4125 +#define MPUI_STATUS_REG (MPUI_BASE + 0x10)
4126 +#define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
4127 +#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
4128 +#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
4129 +
4130 +/*
4131 + * ----------------------------------------------------------------------------
4132 + * LED Pulse Generator
4133 + * ----------------------------------------------------------------------------
4134 + */
4135 +#define OMAP_LPG1_BASE 0xfffbd000
4136 +#define OMAP_LPG2_BASE 0xfffbd800
4137 +#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
4138 +#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
4139 +#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
4140 +#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
4141 +
4142 +/*
4143 + * ----------------------------------------------------------------------------
4144 + * Pulse-Width Light
4145 + * ----------------------------------------------------------------------------
4146 + */
4147 +#define OMAP_PWL_BASE 0xfffb5800
4148 +#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)
4149 +#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)
4150 +
4151 +/*
4152 + * ---------------------------------------------------------------------------
4153 + * Processor specific defines
4154 + * ---------------------------------------------------------------------------
4155 + */
4156 +
4157 +#include <plat/omap7xx.h>
4158 +#include <plat/omap1510.h>
4159 +#include <plat/omap16xx.h>
4160 +#include <plat/omap24xx.h>
4161 +#include <plat/omap34xx.h>
4162 +#include <plat/omap44xx.h>
4163 +
4164 +#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
4165 --- /dev/null
4166 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/hwa742.h
4167 @@ -0,0 +1,8 @@
4168 +#ifndef _HWA742_H
4169 +#define _HWA742_H
4170 +
4171 +struct hwa742_platform_data {
4172 + unsigned te_connected:1;
4173 +};
4174 +
4175 +#endif
4176 --- /dev/null
4177 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/i2c.h
4178 @@ -0,0 +1,39 @@
4179 +/*
4180 + * Helper module for board specific I2C bus registration
4181 + *
4182 + * Copyright (C) 2009 Nokia Corporation.
4183 + *
4184 + * This program is free software; you can redistribute it and/or
4185 + * modify it under the terms of the GNU General Public License
4186 + * version 2 as published by the Free Software Foundation.
4187 + *
4188 + * This program is distributed in the hope that it will be useful, but
4189 + * WITHOUT ANY WARRANTY; without even the implied warranty of
4190 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
4191 + * General Public License for more details.
4192 + *
4193 + * You should have received a copy of the GNU General Public License
4194 + * along with this program; if not, write to the Free Software
4195 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
4196 + * 02110-1301 USA
4197 + *
4198 + */
4199 +
4200 +#include <linux/i2c.h>
4201 +
4202 +#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
4203 +extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
4204 + struct i2c_board_info const *info,
4205 + unsigned len);
4206 +#else
4207 +static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
4208 + struct i2c_board_info const *info,
4209 + unsigned len)
4210 +{
4211 + return 0;
4212 +}
4213 +#endif
4214 +
4215 +int omap_plat_register_i2c_bus(int bus_id, u32 clkrate,
4216 + struct i2c_board_info const *info,
4217 + unsigned len);
4218 --- /dev/null
4219 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/io.h
4220 @@ -0,0 +1,287 @@
4221 +/*
4222 + * arch/arm/plat-omap/include/mach/io.h
4223 + *
4224 + * IO definitions for TI OMAP processors and boards
4225 + *
4226 + * Copied from arch/arm/mach-sa1100/include/mach/io.h
4227 + * Copyright (C) 1997-1999 Russell King
4228 + *
4229 + * Copyright (C) 2009 Texas Instruments
4230 + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
4231 + *
4232 + * This program is free software; you can redistribute it and/or modify it
4233 + * under the terms of the GNU General Public License as published by the
4234 + * Free Software Foundation; either version 2 of the License, or (at your
4235 + * option) any later version.
4236 + *
4237 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4238 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4239 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4240 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4241 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4242 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4243 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4244 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4245 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4246 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4247 + *
4248 + * You should have received a copy of the GNU General Public License along
4249 + * with this program; if not, write to the Free Software Foundation, Inc.,
4250 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4251 + *
4252 + * Modifications:
4253 + * 06-12-1997 RMK Created.
4254 + * 07-04-1999 RMK Major cleanup
4255 + */
4256 +
4257 +#ifndef __ASM_ARM_ARCH_IO_H
4258 +#define __ASM_ARM_ARCH_IO_H
4259 +
4260 +#include <mach/hardware.h>
4261 +
4262 +#define IO_SPACE_LIMIT 0xffffffff
4263 +
4264 +/*
4265 + * We don't actually have real ISA nor PCI buses, but there is so many
4266 + * drivers out there that might just work if we fake them...
4267 + */
4268 +#define __io(a) __typesafe_io(a)
4269 +#define __mem_pci(a) (a)
4270 +
4271 +/*
4272 + * ----------------------------------------------------------------------------
4273 + * I/O mapping
4274 + * ----------------------------------------------------------------------------
4275 + */
4276 +
4277 +#ifdef __ASSEMBLER__
4278 +#define IOMEM(x) (x)
4279 +#else
4280 +#define IOMEM(x) ((void __force __iomem *)(x))
4281 +#endif
4282 +
4283 +#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
4284 +#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
4285 +
4286 +#define OMAP2_L3_IO_OFFSET 0x90000000
4287 +#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
4288 +
4289 +
4290 +#define OMAP2_L4_IO_OFFSET 0xb2000000
4291 +#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
4292 +
4293 +#define OMAP4_L3_IO_OFFSET 0xb4000000
4294 +#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
4295 +
4296 +#define OMAP4_L3_PER_IO_OFFSET 0xb1100000
4297 +#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
4298 +
4299 +#define OMAP4_GPMC_IO_OFFSET 0xa9000000
4300 +#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
4301 +
4302 +#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
4303 +#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
4304 +
4305 +/*
4306 + * ----------------------------------------------------------------------------
4307 + * Omap1 specific IO mapping
4308 + * ----------------------------------------------------------------------------
4309 + */
4310 +
4311 +#define OMAP1_IO_PHYS 0xFFFB0000
4312 +#define OMAP1_IO_SIZE 0x40000
4313 +#define OMAP1_IO_VIRT (OMAP1_IO_PHYS - OMAP1_IO_OFFSET)
4314 +
4315 +/*
4316 + * ----------------------------------------------------------------------------
4317 + * Omap2 specific IO mapping
4318 + * ----------------------------------------------------------------------------
4319 + */
4320 +
4321 +/* We map both L3 and L4 on OMAP2 */
4322 +#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
4323 +#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
4324 +#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
4325 +#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
4326 +#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
4327 +#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
4328 +
4329 +#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
4330 +#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
4331 +#define L4_WK_243X_SIZE SZ_1M
4332 +#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE
4333 +#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
4334 + /* 0x6e000000 --> 0xfe000000 */
4335 +#define OMAP243X_GPMC_SIZE SZ_1M
4336 +#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
4337 + /* 0x6D000000 --> 0xfd000000 */
4338 +#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
4339 +#define OMAP243X_SDRC_SIZE SZ_1M
4340 +#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
4341 + /* 0x6c000000 --> 0xfc000000 */
4342 +#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
4343 +#define OMAP243X_SMS_SIZE SZ_1M
4344 +
4345 +/* DSP */
4346 +#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
4347 +#define DSP_MEM_24XX_VIRT 0xe0000000
4348 +#define DSP_MEM_24XX_SIZE 0x28000
4349 +#define DSP_IPI_24XX_PHYS OMAP2420_DSP_IPI_BASE /* 0x59000000 */
4350 +#define DSP_IPI_24XX_VIRT 0xe1000000
4351 +#define DSP_IPI_24XX_SIZE SZ_4K
4352 +#define DSP_MMU_24XX_PHYS OMAP2420_DSP_MMU_BASE /* 0x5a000000 */
4353 +#define DSP_MMU_24XX_VIRT 0xe2000000
4354 +#define DSP_MMU_24XX_SIZE SZ_4K
4355 +
4356 +/*
4357 + * ----------------------------------------------------------------------------
4358 + * Omap3 specific IO mapping
4359 + * ----------------------------------------------------------------------------
4360 + */
4361 +
4362 +/* We map both L3 and L4 on OMAP3 */
4363 +#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */
4364 +#define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
4365 +#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
4366 +
4367 +#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */
4368 +#define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
4369 +#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
4370 +
4371 +/*
4372 + * Need to look at the Size 4M for L4.
4373 + * VPOM3430 was not working for Int controller
4374 + */
4375 +
4376 +#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 --> 0xfa300000 */
4377 +#define L4_WK_34XX_VIRT (L4_WK_34XX_PHYS + OMAP2_L4_IO_OFFSET)
4378 +#define L4_WK_34XX_SIZE SZ_1M
4379 +
4380 +#define L4_PER_34XX_PHYS L4_PER_34XX_BASE
4381 + /* 0x49000000 --> 0xfb000000 */
4382 +#define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
4383 +#define L4_PER_34XX_SIZE SZ_1M
4384 +
4385 +#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE
4386 + /* 0x54000000 --> 0xfe800000 */
4387 +#define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
4388 +#define L4_EMU_34XX_SIZE SZ_8M
4389 +
4390 +#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE
4391 + /* 0x6e000000 --> 0xfe000000 */
4392 +#define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
4393 +#define OMAP34XX_GPMC_SIZE SZ_1M
4394 +
4395 +#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE
4396 + /* 0x6c000000 --> 0xfc000000 */
4397 +#define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
4398 +#define OMAP343X_SMS_SIZE SZ_1M
4399 +
4400 +#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE
4401 + /* 0x6D000000 --> 0xfd000000 */
4402 +#define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
4403 +#define OMAP343X_SDRC_SIZE SZ_1M
4404 +
4405 +/* DSP */
4406 +#define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */
4407 +#define DSP_MEM_34XX_VIRT 0xe0000000
4408 +#define DSP_MEM_34XX_SIZE 0x28000
4409 +#define DSP_IPI_34XX_PHYS OMAP34XX_DSP_IPI_BASE /* 0x59000000 */
4410 +#define DSP_IPI_34XX_VIRT 0xe1000000
4411 +#define DSP_IPI_34XX_SIZE SZ_4K
4412 +#define DSP_MMU_34XX_PHYS OMAP34XX_DSP_MMU_BASE /* 0x5a000000 */
4413 +#define DSP_MMU_34XX_VIRT 0xe2000000
4414 +#define DSP_MMU_34XX_SIZE SZ_4K
4415 +
4416 +/*
4417 + * ----------------------------------------------------------------------------
4418 + * Omap4 specific IO mapping
4419 + * ----------------------------------------------------------------------------
4420 + */
4421 +
4422 +/* We map both L3 and L4 on OMAP4 */
4423 +#define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */
4424 +#define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
4425 +#define L3_44XX_SIZE SZ_1M
4426 +
4427 +#define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */
4428 +#define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4429 +#define L4_44XX_SIZE SZ_4M
4430 +
4431 +
4432 +#define L4_WK_44XX_PHYS L4_WK_44XX_BASE /* 0x4a300000 --> 0xfc300000 */
4433 +#define L4_WK_44XX_VIRT (L4_WK_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4434 +#define L4_WK_44XX_SIZE SZ_1M
4435 +
4436 +#define L4_PER_44XX_PHYS L4_PER_44XX_BASE
4437 + /* 0x48000000 --> 0xfa000000 */
4438 +#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4439 +#define L4_PER_44XX_SIZE SZ_4M
4440 +
4441 +#define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE
4442 + /* 0x49000000 --> 0xfb000000 */
4443 +#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4444 +#define L4_ABE_44XX_SIZE SZ_1M
4445 +
4446 +#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
4447 + /* 0x54000000 --> 0xfe800000 */
4448 +#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
4449 +#define L4_EMU_44XX_SIZE SZ_8M
4450 +
4451 +#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE
4452 + /* 0x50000000 --> 0xf9000000 */
4453 +#define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
4454 +#define OMAP44XX_GPMC_SIZE SZ_1M
4455 +
4456 +
4457 +#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE
4458 + /* 0x4c000000 --> 0xfd100000 */
4459 +#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
4460 +#define OMAP44XX_EMIF1_SIZE SZ_1M
4461 +
4462 +#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
4463 + /* 0x4d000000 --> 0xfd200000 */
4464 +#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
4465 +#define OMAP44XX_EMIF2_SIZE SZ_1M
4466 +
4467 +#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
4468 + /* 0x4e000000 --> 0xfd300000 */
4469 +#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
4470 +#define OMAP44XX_DMM_SIZE SZ_1M
4471 +/*
4472 + * ----------------------------------------------------------------------------
4473 + * Omap specific register access
4474 + * ----------------------------------------------------------------------------
4475 + */
4476 +
4477 +#ifndef __ASSEMBLER__
4478 +
4479 +/*
4480 + * NOTE: Please use ioremap + __raw_read/write where possible instead of these
4481 + */
4482 +
4483 +extern u8 omap_readb(u32 pa);
4484 +extern u16 omap_readw(u32 pa);
4485 +extern u32 omap_readl(u32 pa);
4486 +extern void omap_writeb(u8 v, u32 pa);
4487 +extern void omap_writew(u16 v, u32 pa);
4488 +extern void omap_writel(u32 v, u32 pa);
4489 +
4490 +struct omap_sdrc_params;
4491 +
4492 +extern void omap1_map_common_io(void);
4493 +extern void omap1_init_common_hw(void);
4494 +
4495 +extern void omap2_map_common_io(void);
4496 +extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
4497 + struct omap_sdrc_params *sdrc_cs1);
4498 +
4499 +#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
4500 +#define __arch_iounmap(v) omap_iounmap(v)
4501 +
4502 +void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
4503 +void omap_iounmap(volatile void __iomem *addr);
4504 +
4505 +#endif
4506 +
4507 +#endif
4508 --- /dev/null
4509 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/iommu2.h
4510 @@ -0,0 +1,96 @@
4511 +/*
4512 + * omap iommu: omap2 architecture specific definitions
4513 + *
4514 + * Copyright (C) 2008-2009 Nokia Corporation
4515 + *
4516 + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
4517 + *
4518 + * This program is free software; you can redistribute it and/or modify
4519 + * it under the terms of the GNU General Public License version 2 as
4520 + * published by the Free Software Foundation.
4521 + */
4522 +
4523 +#ifndef __MACH_IOMMU2_H
4524 +#define __MACH_IOMMU2_H
4525 +
4526 +#include <linux/io.h>
4527 +
4528 +/*
4529 + * MMU Register offsets
4530 + */
4531 +#define MMU_REVISION 0x00
4532 +#define MMU_SYSCONFIG 0x10
4533 +#define MMU_SYSSTATUS 0x14
4534 +#define MMU_IRQSTATUS 0x18
4535 +#define MMU_IRQENABLE 0x1c
4536 +#define MMU_WALKING_ST 0x40
4537 +#define MMU_CNTL 0x44
4538 +#define MMU_FAULT_AD 0x48
4539 +#define MMU_TTB 0x4c
4540 +#define MMU_LOCK 0x50
4541 +#define MMU_LD_TLB 0x54
4542 +#define MMU_CAM 0x58
4543 +#define MMU_RAM 0x5c
4544 +#define MMU_GFLUSH 0x60
4545 +#define MMU_FLUSH_ENTRY 0x64
4546 +#define MMU_READ_CAM 0x68
4547 +#define MMU_READ_RAM 0x6c
4548 +#define MMU_EMU_FAULT_AD 0x70
4549 +
4550 +#define MMU_REG_SIZE 256
4551 +
4552 +/*
4553 + * MMU Register bit definitions
4554 + */
4555 +#define MMU_LOCK_BASE_SHIFT 10
4556 +#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
4557 +#define MMU_LOCK_BASE(x) \
4558 + ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
4559 +
4560 +#define MMU_LOCK_VICT_SHIFT 4
4561 +#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
4562 +#define MMU_LOCK_VICT(x) \
4563 + ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
4564 +
4565 +#define MMU_CAM_VATAG_SHIFT 12
4566 +#define MMU_CAM_VATAG_MASK \
4567 + ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
4568 +#define MMU_CAM_P (1 << 3)
4569 +#define MMU_CAM_V (1 << 2)
4570 +#define MMU_CAM_PGSZ_MASK 3
4571 +#define MMU_CAM_PGSZ_1M (0 << 0)
4572 +#define MMU_CAM_PGSZ_64K (1 << 0)
4573 +#define MMU_CAM_PGSZ_4K (2 << 0)
4574 +#define MMU_CAM_PGSZ_16M (3 << 0)
4575 +
4576 +#define MMU_RAM_PADDR_SHIFT 12
4577 +#define MMU_RAM_PADDR_MASK \
4578 + ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
4579 +#define MMU_RAM_ENDIAN_SHIFT 9
4580 +#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT)
4581 +#define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT)
4582 +#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
4583 +#define MMU_RAM_ELSZ_SHIFT 7
4584 +#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
4585 +#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
4586 +#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
4587 +#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
4588 +#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
4589 +#define MMU_RAM_MIXED_SHIFT 6
4590 +#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT)
4591 +#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
4592 +
4593 +/*
4594 + * register accessors
4595 + */
4596 +static inline u32 iommu_read_reg(struct iommu *obj, size_t offs)
4597 +{
4598 + return __raw_readl(obj->regbase + offs);
4599 +}
4600 +
4601 +static inline void iommu_write_reg(struct iommu *obj, u32 val, size_t offs)
4602 +{
4603 + __raw_writel(val, obj->regbase + offs);
4604 +}
4605 +
4606 +#endif /* __MACH_IOMMU2_H */
4607 --- /dev/null
4608 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/iommu.h
4609 @@ -0,0 +1,168 @@
4610 +/*
4611 + * omap iommu: main structures
4612 + *
4613 + * Copyright (C) 2008-2009 Nokia Corporation
4614 + *
4615 + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
4616 + *
4617 + * This program is free software; you can redistribute it and/or modify
4618 + * it under the terms of the GNU General Public License version 2 as
4619 + * published by the Free Software Foundation.
4620 + */
4621 +
4622 +#ifndef __MACH_IOMMU_H
4623 +#define __MACH_IOMMU_H
4624 +
4625 +struct iotlb_entry {
4626 + u32 da;
4627 + u32 pa;
4628 + u32 pgsz, prsvd, valid;
4629 + union {
4630 + u16 ap;
4631 + struct {
4632 + u32 endian, elsz, mixed;
4633 + };
4634 + };
4635 +};
4636 +
4637 +struct iommu {
4638 + const char *name;
4639 + struct module *owner;
4640 + struct clk *clk;
4641 + void __iomem *regbase;
4642 + struct device *dev;
4643 +
4644 + unsigned int refcount;
4645 + struct mutex iommu_lock; /* global for this whole object */
4646 +
4647 + /*
4648 + * We don't change iopgd for a situation like pgd for a task,
4649 + * but share it globally for each iommu.
4650 + */
4651 + u32 *iopgd;
4652 + spinlock_t page_table_lock; /* protect iopgd */
4653 +
4654 + int nr_tlb_entries;
4655 +
4656 + struct list_head mmap;
4657 + struct mutex mmap_lock; /* protect mmap */
4658 +
4659 + int (*isr)(struct iommu *obj);
4660 +
4661 + void *ctx; /* iommu context: registres saved area */
4662 +};
4663 +
4664 +struct cr_regs {
4665 + union {
4666 + struct {
4667 + u16 cam_l;
4668 + u16 cam_h;
4669 + };
4670 + u32 cam;
4671 + };
4672 + union {
4673 + struct {
4674 + u16 ram_l;
4675 + u16 ram_h;
4676 + };
4677 + u32 ram;
4678 + };
4679 +};
4680 +
4681 +struct iotlb_lock {
4682 + short base;
4683 + short vict;
4684 +};
4685 +
4686 +/* architecture specific functions */
4687 +struct iommu_functions {
4688 + unsigned long version;
4689 +
4690 + int (*enable)(struct iommu *obj);
4691 + void (*disable)(struct iommu *obj);
4692 + u32 (*fault_isr)(struct iommu *obj, u32 *ra);
4693 +
4694 + void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
4695 + void (*tlb_load_cr)(struct iommu *obj, struct cr_regs *cr);
4696 +
4697 + struct cr_regs *(*alloc_cr)(struct iommu *obj, struct iotlb_entry *e);
4698 + int (*cr_valid)(struct cr_regs *cr);
4699 + u32 (*cr_to_virt)(struct cr_regs *cr);
4700 + void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
4701 + ssize_t (*dump_cr)(struct iommu *obj, struct cr_regs *cr, char *buf);
4702 +
4703 + u32 (*get_pte_attr)(struct iotlb_entry *e);
4704 +
4705 + void (*save_ctx)(struct iommu *obj);
4706 + void (*restore_ctx)(struct iommu *obj);
4707 + ssize_t (*dump_ctx)(struct iommu *obj, char *buf, ssize_t len);
4708 +};
4709 +
4710 +struct iommu_platform_data {
4711 + const char *name;
4712 + const char *clk_name;
4713 + const int nr_tlb_entries;
4714 +};
4715 +
4716 +#if defined(CONFIG_ARCH_OMAP1)
4717 +#error "iommu for this processor not implemented yet"
4718 +#else
4719 +#include <plat/iommu2.h>
4720 +#endif
4721 +
4722 +/*
4723 + * utilities for super page(16MB, 1MB, 64KB and 4KB)
4724 + */
4725 +
4726 +#define iopgsz_max(bytes) \
4727 + (((bytes) >= SZ_16M) ? SZ_16M : \
4728 + ((bytes) >= SZ_1M) ? SZ_1M : \
4729 + ((bytes) >= SZ_64K) ? SZ_64K : \
4730 + ((bytes) >= SZ_4K) ? SZ_4K : 0)
4731 +
4732 +#define bytes_to_iopgsz(bytes) \
4733 + (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
4734 + ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
4735 + ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
4736 + ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
4737 +
4738 +#define iopgsz_to_bytes(iopgsz) \
4739 + (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
4740 + ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
4741 + ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
4742 + ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
4743 +
4744 +#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
4745 +
4746 +/*
4747 + * global functions
4748 + */
4749 +extern u32 iommu_arch_version(void);
4750 +
4751 +extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
4752 +extern u32 iotlb_cr_to_virt(struct cr_regs *cr);
4753 +
4754 +extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e);
4755 +extern void flush_iotlb_page(struct iommu *obj, u32 da);
4756 +extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
4757 +extern void flush_iotlb_all(struct iommu *obj);
4758 +
4759 +extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
4760 +extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
4761 +
4762 +extern struct iommu *iommu_get(const char *name);
4763 +extern void iommu_put(struct iommu *obj);
4764 +
4765 +extern void iommu_save_ctx(struct iommu *obj);
4766 +extern void iommu_restore_ctx(struct iommu *obj);
4767 +
4768 +extern int install_iommu_arch(const struct iommu_functions *ops);
4769 +extern void uninstall_iommu_arch(const struct iommu_functions *ops);
4770 +
4771 +extern int foreach_iommu_device(void *data,
4772 + int (*fn)(struct device *, void *));
4773 +
4774 +extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len);
4775 +extern size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t len);
4776 +
4777 +#endif /* __MACH_IOMMU_H */
4778 --- /dev/null
4779 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/iovmm.h
4780 @@ -0,0 +1,94 @@
4781 +/*
4782 + * omap iommu: simple virtual address space management
4783 + *
4784 + * Copyright (C) 2008-2009 Nokia Corporation
4785 + *
4786 + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
4787 + *
4788 + * This program is free software; you can redistribute it and/or modify
4789 + * it under the terms of the GNU General Public License version 2 as
4790 + * published by the Free Software Foundation.
4791 + */
4792 +
4793 +#ifndef __IOMMU_MMAP_H
4794 +#define __IOMMU_MMAP_H
4795 +
4796 +struct iovm_struct {
4797 + struct iommu *iommu; /* iommu object which this belongs to */
4798 + u32 da_start; /* area definition */
4799 + u32 da_end;
4800 + u32 flags; /* IOVMF_: see below */
4801 + struct list_head list; /* linked in ascending order */
4802 + const struct sg_table *sgt; /* keep 'page' <-> 'da' mapping */
4803 + void *va; /* mpu side mapped address */
4804 +};
4805 +
4806 +/*
4807 + * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma)
4808 + *
4809 + * lower 16 bit is used for h/w and upper 16 bit is for s/w.
4810 + */
4811 +#define IOVMF_SW_SHIFT 16
4812 +#define IOVMF_HW_SIZE (1 << IOVMF_SW_SHIFT)
4813 +#define IOVMF_HW_MASK (IOVMF_HW_SIZE - 1)
4814 +#define IOVMF_SW_MASK (~IOVMF_HW_MASK)UL
4815 +
4816 +/*
4817 + * iovma: h/w flags derived from cam and ram attribute
4818 + */
4819 +#define IOVMF_CAM_MASK (~((1 << 10) - 1))
4820 +#define IOVMF_RAM_MASK (~IOVMF_CAM_MASK)
4821 +
4822 +#define IOVMF_PGSZ_MASK (3 << 0)
4823 +#define IOVMF_PGSZ_1M MMU_CAM_PGSZ_1M
4824 +#define IOVMF_PGSZ_64K MMU_CAM_PGSZ_64K
4825 +#define IOVMF_PGSZ_4K MMU_CAM_PGSZ_4K
4826 +#define IOVMF_PGSZ_16M MMU_CAM_PGSZ_16M
4827 +
4828 +#define IOVMF_ENDIAN_MASK (1 << 9)
4829 +#define IOVMF_ENDIAN_BIG MMU_RAM_ENDIAN_BIG
4830 +#define IOVMF_ENDIAN_LITTLE MMU_RAM_ENDIAN_LITTLE
4831 +
4832 +#define IOVMF_ELSZ_MASK (3 << 7)
4833 +#define IOVMF_ELSZ_8 MMU_RAM_ELSZ_8
4834 +#define IOVMF_ELSZ_16 MMU_RAM_ELSZ_16
4835 +#define IOVMF_ELSZ_32 MMU_RAM_ELSZ_32
4836 +#define IOVMF_ELSZ_NONE MMU_RAM_ELSZ_NONE
4837 +
4838 +#define IOVMF_MIXED_MASK (1 << 6)
4839 +#define IOVMF_MIXED MMU_RAM_MIXED
4840 +
4841 +/*
4842 + * iovma: s/w flags, used for mapping and umapping internally.
4843 + */
4844 +#define IOVMF_MMIO (1 << IOVMF_SW_SHIFT)
4845 +#define IOVMF_ALLOC (2 << IOVMF_SW_SHIFT)
4846 +#define IOVMF_ALLOC_MASK (3 << IOVMF_SW_SHIFT)
4847 +
4848 +/* "superpages" is supported just with physically linear pages */
4849 +#define IOVMF_DISCONT (1 << (2 + IOVMF_SW_SHIFT))
4850 +#define IOVMF_LINEAR (2 << (2 + IOVMF_SW_SHIFT))
4851 +#define IOVMF_LINEAR_MASK (3 << (2 + IOVMF_SW_SHIFT))
4852 +
4853 +#define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT))
4854 +#define IOVMF_DA_ANON (2 << (4 + IOVMF_SW_SHIFT))
4855 +#define IOVMF_DA_MASK (3 << (4 + IOVMF_SW_SHIFT))
4856 +
4857 +
4858 +extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da);
4859 +extern u32 iommu_vmap(struct iommu *obj, u32 da,
4860 + const struct sg_table *sgt, u32 flags);
4861 +extern struct sg_table *iommu_vunmap(struct iommu *obj, u32 da);
4862 +extern u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes,
4863 + u32 flags);
4864 +extern void iommu_vfree(struct iommu *obj, const u32 da);
4865 +extern u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes,
4866 + u32 flags);
4867 +extern void iommu_kunmap(struct iommu *obj, u32 da);
4868 +extern u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes,
4869 + u32 flags);
4870 +extern void iommu_kfree(struct iommu *obj, u32 da);
4871 +
4872 +extern void *da_to_va(struct iommu *obj, u32 da);
4873 +
4874 +#endif /* __IOMMU_MMAP_H */
4875 --- /dev/null
4876 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/irda.h
4877 @@ -0,0 +1,33 @@
4878 +/*
4879 + * arch/arm/plat-omap/include/mach/irda.h
4880 + *
4881 + * Copyright (C) 2005-2006 Komal Shah <komal_shah802003@yahoo.com>
4882 + *
4883 + * This program is free software; you can redistribute it and/or modify
4884 + * it under the terms of the GNU General Public License version 2 as
4885 + * published by the Free Software Foundation.
4886 + */
4887 +#ifndef ASMARM_ARCH_IRDA_H
4888 +#define ASMARM_ARCH_IRDA_H
4889 +
4890 +/* board specific transceiver capabilities */
4891 +
4892 +#define IR_SEL 1 /* Selects IrDA */
4893 +#define IR_SIRMODE 2
4894 +#define IR_FIRMODE 4
4895 +#define IR_MIRMODE 8
4896 +
4897 +struct omap_irda_config {
4898 + int transceiver_cap;
4899 + int (*transceiver_mode)(struct device *dev, int mode);
4900 + int (*select_irda)(struct device *dev, int state);
4901 + int rx_channel;
4902 + int tx_channel;
4903 + unsigned long dest_start;
4904 + unsigned long src_start;
4905 + int tx_trigger;
4906 + int rx_trigger;
4907 + int mode;
4908 +};
4909 +
4910 +#endif
4911 --- /dev/null
4912 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/irqs.h
4913 @@ -0,0 +1,506 @@
4914 +/*
4915 + * arch/arm/plat-omap/include/mach/irqs.h
4916 + *
4917 + * Copyright (C) Greg Lonnon 2001
4918 + * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
4919 + *
4920 + * Copyright (C) 2009 Texas Instruments
4921 + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
4922 + *
4923 + * This program is free software; you can redistribute it and/or modify
4924 + * it under the terms of the GNU General Public License as published by
4925 + * the Free Software Foundation; either version 2 of the License, or
4926 + * (at your option) any later version.
4927 + *
4928 + * This program is distributed in the hope that it will be useful,
4929 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4930 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4931 + * GNU General Public License for more details.
4932 + *
4933 + * You should have received a copy of the GNU General Public License
4934 + * along with this program; if not, write to the Free Software
4935 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4936 + *
4937 + * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
4938 + * are different.
4939 + */
4940 +
4941 +#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
4942 +#define __ASM_ARCH_OMAP15XX_IRQS_H
4943 +
4944 +/*
4945 + * IRQ numbers for interrupt handler 1
4946 + *
4947 + * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
4948 + *
4949 + */
4950 +#define INT_CAMERA 1
4951 +#define INT_FIQ 3
4952 +#define INT_RTDX 6
4953 +#define INT_DSP_MMU_ABORT 7
4954 +#define INT_HOST 8
4955 +#define INT_ABORT 9
4956 +#define INT_BRIDGE_PRIV 13
4957 +#define INT_GPIO_BANK1 14
4958 +#define INT_UART3 15
4959 +#define INT_TIMER3 16
4960 +#define INT_DMA_CH0_6 19
4961 +#define INT_DMA_CH1_7 20
4962 +#define INT_DMA_CH2_8 21
4963 +#define INT_DMA_CH3 22
4964 +#define INT_DMA_CH4 23
4965 +#define INT_DMA_CH5 24
4966 +#define INT_DMA_LCD 25
4967 +#define INT_TIMER1 26
4968 +#define INT_WD_TIMER 27
4969 +#define INT_BRIDGE_PUB 28
4970 +#define INT_TIMER2 30
4971 +#define INT_LCD_CTRL 31
4972 +
4973 +/*
4974 + * OMAP-1510 specific IRQ numbers for interrupt handler 1
4975 + */
4976 +#define INT_1510_IH2_IRQ 0
4977 +#define INT_1510_RES2 2
4978 +#define INT_1510_SPI_TX 4
4979 +#define INT_1510_SPI_RX 5
4980 +#define INT_1510_DSP_MAILBOX1 10
4981 +#define INT_1510_DSP_MAILBOX2 11
4982 +#define INT_1510_RES12 12
4983 +#define INT_1510_LB_MMU 17
4984 +#define INT_1510_RES18 18
4985 +#define INT_1510_LOCAL_BUS 29
4986 +
4987 +/*
4988 + * OMAP-1610 specific IRQ numbers for interrupt handler 1
4989 + */
4990 +#define INT_1610_IH2_IRQ 0
4991 +#define INT_1610_IH2_FIQ 2
4992 +#define INT_1610_McBSP2_TX 4
4993 +#define INT_1610_McBSP2_RX 5
4994 +#define INT_1610_DSP_MAILBOX1 10
4995 +#define INT_1610_DSP_MAILBOX2 11
4996 +#define INT_1610_LCD_LINE 12
4997 +#define INT_1610_GPTIMER1 17
4998 +#define INT_1610_GPTIMER2 18
4999 +#define INT_1610_SSR_FIFO_0 29
5000 +
5001 +/*
5002 + * OMAP-7xx specific IRQ numbers for interrupt handler 1
5003 + */
5004 +#define INT_7XX_IH2_FIQ 0
5005 +#define INT_7XX_IH2_IRQ 1
5006 +#define INT_7XX_USB_NON_ISO 2
5007 +#define INT_7XX_USB_ISO 3
5008 +#define INT_7XX_ICR 4
5009 +#define INT_7XX_EAC 5
5010 +#define INT_7XX_GPIO_BANK1 6
5011 +#define INT_7XX_GPIO_BANK2 7
5012 +#define INT_7XX_GPIO_BANK3 8
5013 +#define INT_7XX_McBSP2TX 10
5014 +#define INT_7XX_McBSP2RX 11
5015 +#define INT_7XX_McBSP2RX_OVF 12
5016 +#define INT_7XX_LCD_LINE 14
5017 +#define INT_7XX_GSM_PROTECT 15
5018 +#define INT_7XX_TIMER3 16
5019 +#define INT_7XX_GPIO_BANK5 17
5020 +#define INT_7XX_GPIO_BANK6 18
5021 +#define INT_7XX_SPGIO_WR 29
5022 +
5023 +/*
5024 + * IRQ numbers for interrupt handler 2
5025 + *
5026 + * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
5027 + */
5028 +#define IH2_BASE 32
5029 +
5030 +#define INT_KEYBOARD (1 + IH2_BASE)
5031 +#define INT_uWireTX (2 + IH2_BASE)
5032 +#define INT_uWireRX (3 + IH2_BASE)
5033 +#define INT_I2C (4 + IH2_BASE)
5034 +#define INT_MPUIO (5 + IH2_BASE)
5035 +#define INT_USB_HHC_1 (6 + IH2_BASE)
5036 +#define INT_McBSP3TX (10 + IH2_BASE)
5037 +#define INT_McBSP3RX (11 + IH2_BASE)
5038 +#define INT_McBSP1TX (12 + IH2_BASE)
5039 +#define INT_McBSP1RX (13 + IH2_BASE)
5040 +#define INT_UART1 (14 + IH2_BASE)
5041 +#define INT_UART2 (15 + IH2_BASE)
5042 +#define INT_BT_MCSI1TX (16 + IH2_BASE)
5043 +#define INT_BT_MCSI1RX (17 + IH2_BASE)
5044 +#define INT_SOSSI_MATCH (19 + IH2_BASE)
5045 +#define INT_USB_W2FC (20 + IH2_BASE)
5046 +#define INT_1WIRE (21 + IH2_BASE)
5047 +#define INT_OS_TIMER (22 + IH2_BASE)
5048 +#define INT_MMC (23 + IH2_BASE)
5049 +#define INT_GAUGE_32K (24 + IH2_BASE)
5050 +#define INT_RTC_TIMER (25 + IH2_BASE)
5051 +#define INT_RTC_ALARM (26 + IH2_BASE)
5052 +#define INT_MEM_STICK (27 + IH2_BASE)
5053 +
5054 +/*
5055 + * OMAP-1510 specific IRQ numbers for interrupt handler 2
5056 + */
5057 +#define INT_1510_DSP_MMU (28 + IH2_BASE)
5058 +#define INT_1510_COM_SPI_RO (31 + IH2_BASE)
5059 +
5060 +/*
5061 + * OMAP-1610 specific IRQ numbers for interrupt handler 2
5062 + */
5063 +#define INT_1610_FAC (0 + IH2_BASE)
5064 +#define INT_1610_USB_HHC_2 (7 + IH2_BASE)
5065 +#define INT_1610_USB_OTG (8 + IH2_BASE)
5066 +#define INT_1610_SoSSI (9 + IH2_BASE)
5067 +#define INT_1610_SoSSI_MATCH (19 + IH2_BASE)
5068 +#define INT_1610_DSP_MMU (28 + IH2_BASE)
5069 +#define INT_1610_McBSP2RX_OF (31 + IH2_BASE)
5070 +#define INT_1610_STI (32 + IH2_BASE)
5071 +#define INT_1610_STI_WAKEUP (33 + IH2_BASE)
5072 +#define INT_1610_GPTIMER3 (34 + IH2_BASE)
5073 +#define INT_1610_GPTIMER4 (35 + IH2_BASE)
5074 +#define INT_1610_GPTIMER5 (36 + IH2_BASE)
5075 +#define INT_1610_GPTIMER6 (37 + IH2_BASE)
5076 +#define INT_1610_GPTIMER7 (38 + IH2_BASE)
5077 +#define INT_1610_GPTIMER8 (39 + IH2_BASE)
5078 +#define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
5079 +#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
5080 +#define INT_1610_MMC2 (42 + IH2_BASE)
5081 +#define INT_1610_CF (43 + IH2_BASE)
5082 +#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
5083 +#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
5084 +#define INT_1610_SPI (49 + IH2_BASE)
5085 +#define INT_1610_DMA_CH6 (53 + IH2_BASE)
5086 +#define INT_1610_DMA_CH7 (54 + IH2_BASE)
5087 +#define INT_1610_DMA_CH8 (55 + IH2_BASE)
5088 +#define INT_1610_DMA_CH9 (56 + IH2_BASE)
5089 +#define INT_1610_DMA_CH10 (57 + IH2_BASE)
5090 +#define INT_1610_DMA_CH11 (58 + IH2_BASE)
5091 +#define INT_1610_DMA_CH12 (59 + IH2_BASE)
5092 +#define INT_1610_DMA_CH13 (60 + IH2_BASE)
5093 +#define INT_1610_DMA_CH14 (61 + IH2_BASE)
5094 +#define INT_1610_DMA_CH15 (62 + IH2_BASE)
5095 +#define INT_1610_NAND (63 + IH2_BASE)
5096 +#define INT_1610_SHA1MD5 (91 + IH2_BASE)
5097 +
5098 +/*
5099 + * OMAP-7xx specific IRQ numbers for interrupt handler 2
5100 + */
5101 +#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
5102 +#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
5103 +#define INT_7XX_CFCD (2 + IH2_BASE)
5104 +#define INT_7XX_CFIREQ (3 + IH2_BASE)
5105 +#define INT_7XX_I2C (4 + IH2_BASE)
5106 +#define INT_7XX_PCC (5 + IH2_BASE)
5107 +#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
5108 +#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
5109 +#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
5110 +#define INT_7XX_VLYNQ (9 + IH2_BASE)
5111 +#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
5112 +#define INT_7XX_McBSP1TX (11 + IH2_BASE)
5113 +#define INT_7XX_McBSP1RX (12 + IH2_BASE)
5114 +#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
5115 +#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
5116 +#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
5117 +#define INT_7XX_MCSI (16 + IH2_BASE)
5118 +#define INT_7XX_uWireTX (17 + IH2_BASE)
5119 +#define INT_7XX_uWireRX (18 + IH2_BASE)
5120 +#define INT_7XX_SMC_CD (19 + IH2_BASE)
5121 +#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
5122 +#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
5123 +#define INT_7XX_TIMER32K (22 + IH2_BASE)
5124 +#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
5125 +#define INT_7XX_UPLD (24 + IH2_BASE)
5126 +#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
5127 +#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
5128 +#define INT_7XX_USB_GENI (29 + IH2_BASE)
5129 +#define INT_7XX_USB_OTG (30 + IH2_BASE)
5130 +#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
5131 +#define INT_7XX_RNG (32 + IH2_BASE)
5132 +#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
5133 +#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
5134 +#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
5135 +#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
5136 +#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
5137 +#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
5138 +#define INT_7XX_MPUIO (39 + IH2_BASE)
5139 +#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
5140 +#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
5141 +#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
5142 +#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
5143 +#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
5144 +#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
5145 +#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
5146 +#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
5147 +#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
5148 +#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
5149 +#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
5150 +#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
5151 +#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
5152 +#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
5153 +#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
5154 +#define INT_7XX_NAND (63 + IH2_BASE)
5155 +
5156 +#define INT_24XX_SYS_NIRQ 7
5157 +#define INT_24XX_SDMA_IRQ0 12
5158 +#define INT_24XX_SDMA_IRQ1 13
5159 +#define INT_24XX_SDMA_IRQ2 14
5160 +#define INT_24XX_SDMA_IRQ3 15
5161 +#define INT_24XX_CAM_IRQ 24
5162 +#define INT_24XX_DSS_IRQ 25
5163 +#define INT_24XX_MAIL_U0_MPU 26
5164 +#define INT_24XX_DSP_UMA 27
5165 +#define INT_24XX_DSP_MMU 28
5166 +#define INT_24XX_GPIO_BANK1 29
5167 +#define INT_24XX_GPIO_BANK2 30
5168 +#define INT_24XX_GPIO_BANK3 31
5169 +#define INT_24XX_GPIO_BANK4 32
5170 +#define INT_24XX_GPIO_BANK5 33
5171 +#define INT_24XX_MAIL_U3_MPU 34
5172 +#define INT_24XX_GPTIMER1 37
5173 +#define INT_24XX_GPTIMER2 38
5174 +#define INT_24XX_GPTIMER3 39
5175 +#define INT_24XX_GPTIMER4 40
5176 +#define INT_24XX_GPTIMER5 41
5177 +#define INT_24XX_GPTIMER6 42
5178 +#define INT_24XX_GPTIMER7 43
5179 +#define INT_24XX_GPTIMER8 44
5180 +#define INT_24XX_GPTIMER9 45
5181 +#define INT_24XX_GPTIMER10 46
5182 +#define INT_24XX_GPTIMER11 47
5183 +#define INT_24XX_GPTIMER12 48
5184 +#define INT_24XX_SHA1MD5 51
5185 +#define INT_24XX_MCBSP4_IRQ_TX 54
5186 +#define INT_24XX_MCBSP4_IRQ_RX 55
5187 +#define INT_24XX_I2C1_IRQ 56
5188 +#define INT_24XX_I2C2_IRQ 57
5189 +#define INT_24XX_HDQ_IRQ 58
5190 +#define INT_24XX_MCBSP1_IRQ_TX 59
5191 +#define INT_24XX_MCBSP1_IRQ_RX 60
5192 +#define INT_24XX_MCBSP2_IRQ_TX 62
5193 +#define INT_24XX_MCBSP2_IRQ_RX 63
5194 +#define INT_24XX_SPI1_IRQ 65
5195 +#define INT_24XX_SPI2_IRQ 66
5196 +#define INT_24XX_UART1_IRQ 72
5197 +#define INT_24XX_UART2_IRQ 73
5198 +#define INT_24XX_UART3_IRQ 74
5199 +#define INT_24XX_USB_IRQ_GEN 75
5200 +#define INT_24XX_USB_IRQ_NISO 76
5201 +#define INT_24XX_USB_IRQ_ISO 77
5202 +#define INT_24XX_USB_IRQ_HGEN 78
5203 +#define INT_24XX_USB_IRQ_HSOF 79
5204 +#define INT_24XX_USB_IRQ_OTG 80
5205 +#define INT_24XX_MCBSP5_IRQ_TX 81
5206 +#define INT_24XX_MCBSP5_IRQ_RX 82
5207 +#define INT_24XX_MMC_IRQ 83
5208 +#define INT_24XX_MMC2_IRQ 86
5209 +#define INT_24XX_MCBSP3_IRQ_TX 89
5210 +#define INT_24XX_MCBSP3_IRQ_RX 90
5211 +#define INT_24XX_SPI3_IRQ 91
5212 +
5213 +#define INT_243X_MCBSP2_IRQ 16
5214 +#define INT_243X_MCBSP3_IRQ 17
5215 +#define INT_243X_MCBSP4_IRQ 18
5216 +#define INT_243X_MCBSP5_IRQ 19
5217 +#define INT_243X_MCBSP1_IRQ 64
5218 +#define INT_243X_HS_USB_MC 92
5219 +#define INT_243X_HS_USB_DMA 93
5220 +#define INT_243X_CARKIT_IRQ 94
5221 +
5222 +#define INT_34XX_BENCH_MPU_EMUL 3
5223 +#define INT_34XX_ST_MCBSP2_IRQ 4
5224 +#define INT_34XX_ST_MCBSP3_IRQ 5
5225 +#define INT_34XX_SSM_ABORT_IRQ 6
5226 +#define INT_34XX_SYS_NIRQ 7
5227 +#define INT_34XX_D2D_FW_IRQ 8
5228 +#define INT_34XX_PRCM_MPU_IRQ 11
5229 +#define INT_34XX_MCBSP1_IRQ 16
5230 +#define INT_34XX_MCBSP2_IRQ 17
5231 +#define INT_34XX_MCBSP3_IRQ 22
5232 +#define INT_34XX_MCBSP4_IRQ 23
5233 +#define INT_34XX_CAM_IRQ 24
5234 +#define INT_34XX_MCBSP5_IRQ 27
5235 +#define INT_34XX_GPIO_BANK1 29
5236 +#define INT_34XX_GPIO_BANK2 30
5237 +#define INT_34XX_GPIO_BANK3 31
5238 +#define INT_34XX_GPIO_BANK4 32
5239 +#define INT_34XX_GPIO_BANK5 33
5240 +#define INT_34XX_GPIO_BANK6 34
5241 +#define INT_34XX_USIM_IRQ 35
5242 +#define INT_34XX_WDT3_IRQ 36
5243 +#define INT_34XX_SPI4_IRQ 48
5244 +#define INT_34XX_SHA1MD52_IRQ 49
5245 +#define INT_34XX_FPKA_READY_IRQ 50
5246 +#define INT_34XX_SHA1MD51_IRQ 51
5247 +#define INT_34XX_RNG_IRQ 52
5248 +#define INT_34XX_I2C3_IRQ 61
5249 +#define INT_34XX_FPKA_ERROR_IRQ 64
5250 +#define INT_34XX_PBIAS_IRQ 75
5251 +#define INT_34XX_OHCI_IRQ 76
5252 +#define INT_34XX_EHCI_IRQ 77
5253 +#define INT_34XX_TLL_IRQ 78
5254 +#define INT_34XX_PARTHASH_IRQ 79
5255 +#define INT_34XX_MMC3_IRQ 94
5256 +#define INT_34XX_GPT12_IRQ 95
5257 +
5258 +#define INT_34XX_BENCH_MPU_EMUL 3
5259 +
5260 +
5261 +#define IRQ_GIC_START 32
5262 +#define INT_44XX_LOCALTIMER_IRQ 29
5263 +#define INT_44XX_LOCALWDT_IRQ 30
5264 +
5265 +#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START)
5266 +#define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START)
5267 +#define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START)
5268 +#define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START)
5269 +#define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START)
5270 +#define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START)
5271 +#define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START)
5272 +#define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START)
5273 +#define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START)
5274 +#define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START)
5275 +#define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START)
5276 +#define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START)
5277 +#define INT_44XX_DSP_MMU (28 + IRQ_GIC_START)
5278 +#define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START)
5279 +#define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START)
5280 +#define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START)
5281 +#define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START)
5282 +#define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START)
5283 +#define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START)
5284 +#define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START)
5285 +#define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START)
5286 +#define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START)
5287 +#define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START)
5288 +#define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START)
5289 +#define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START)
5290 +#define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START)
5291 +#define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START)
5292 +#define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START)
5293 +#define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START)
5294 +#define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START)
5295 +#define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START)
5296 +#define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START)
5297 +#define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START)
5298 +#define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START)
5299 +#define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START)
5300 +#define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START)
5301 +#define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START)
5302 +#define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START)
5303 +#define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START)
5304 +#define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START)
5305 +#define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START)
5306 +#define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START)
5307 +#define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START)
5308 +#define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START)
5309 +#define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START)
5310 +#define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START)
5311 +#define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START)
5312 +#define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START)
5313 +#define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START)
5314 +#define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START)
5315 +#define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START)
5316 +
5317 +#define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START)
5318 +#define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START)
5319 +#define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START)
5320 +#define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START)
5321 +#define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START)
5322 +#define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START)
5323 +#define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START)
5324 +
5325 +#define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START)
5326 +#define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START)
5327 +#define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START)
5328 +#define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START)
5329 +#define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START)
5330 +#define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START)
5331 +#define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START)
5332 +#define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START)
5333 +#define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START)
5334 +#define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START)
5335 +#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START)
5336 +#define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START)
5337 +#define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START)
5338 +#define INT_44XX_MMC5_IRQ (59 + IRQ_GIC_START)
5339 +#define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START)
5340 +#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START)
5341 +#define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START)
5342 +#define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START)
5343 +#define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START)
5344 +#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START)
5345 +#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START)
5346 +#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START)
5347 +#define INT_44XX_MMC4_IRQ (96 + IRQ_GIC_START)
5348 +
5349 +
5350 +/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
5351 + * 16 MPUIO lines */
5352 +#define OMAP_MAX_GPIO_LINES 192
5353 +#define IH_GPIO_BASE (128 + IH2_BASE)
5354 +#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
5355 +#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
5356 +
5357 +/* External FPGA handles interrupts on Innovator boards */
5358 +#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
5359 +#ifdef CONFIG_MACH_OMAP_INNOVATOR
5360 +#define OMAP_FPGA_NR_IRQS 24
5361 +#else
5362 +#define OMAP_FPGA_NR_IRQS 0
5363 +#endif
5364 +#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
5365 +
5366 +/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
5367 +#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END)
5368 +#ifdef CONFIG_TWL4030_CORE
5369 +#define TWL4030_BASE_NR_IRQS 8
5370 +#define TWL4030_PWR_NR_IRQS 8
5371 +#else
5372 +#define TWL4030_BASE_NR_IRQS 0
5373 +#define TWL4030_PWR_NR_IRQS 0
5374 +#endif
5375 +#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
5376 +#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END
5377 +#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
5378 +
5379 +/* External TWL4030 gpio interrupts are optional */
5380 +#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END
5381 +#ifdef CONFIG_GPIO_TWL4030
5382 +#define TWL4030_GPIO_NR_IRQS 18
5383 +#else
5384 +#define TWL4030_GPIO_NR_IRQS 0
5385 +#endif
5386 +#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
5387 +
5388 +#define TWL6030_IRQ_BASE (OMAP_FPGA_IRQ_END)
5389 +#ifdef CONFIG_TWL4030_CORE
5390 +#define TWL6030_BASE_NR_IRQS 20
5391 +#else
5392 +#define TWL6030_BASE_NR_IRQS 0
5393 +#endif
5394 +#define TWL6030_IRQ_END (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)
5395 +
5396 +/* Total number of interrupts depends on the enabled blocks above */
5397 +#if (TWL4030_GPIO_IRQ_END > TWL6030_IRQ_END)
5398 +#define TWL_IRQ_END TWL4030_GPIO_IRQ_END
5399 +#else
5400 +#define TWL_IRQ_END TWL6030_IRQ_END
5401 +#endif
5402 +
5403 +#define NR_IRQS TWL_IRQ_END
5404 +
5405 +#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
5406 +
5407 +#define INTCPS_NR_MIR_REGS 3
5408 +#define INTCPS_NR_IRQS 96
5409 +
5410 +#ifndef __ASSEMBLY__
5411 +extern void omap_init_irq(void);
5412 +extern int omap_irq_pending(void);
5413 +void omap_intc_save_context(void);
5414 +void omap_intc_restore_context(void);
5415 +#endif
5416 +
5417 +#include <mach/hardware.h>
5418 +
5419 +#endif
5420 --- /dev/null
5421 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/keypad.h
5422 @@ -0,0 +1,45 @@
5423 +/*
5424 + * arch/arm/plat-omap/include/mach/keypad.h
5425 + *
5426 + * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
5427 + *
5428 + * This program is free software; you can redistribute it and/or modify
5429 + * it under the terms of the GNU General Public License version 2 as
5430 + * published by the Free Software Foundation.
5431 + */
5432 +#ifndef ASMARM_ARCH_KEYPAD_H
5433 +#define ASMARM_ARCH_KEYPAD_H
5434 +
5435 +#warning: Please update the board to use matrix_keypad.h instead
5436 +
5437 +struct omap_kp_platform_data {
5438 + int rows;
5439 + int cols;
5440 + int *keymap;
5441 + unsigned int keymapsize;
5442 + unsigned int rep:1;
5443 + unsigned long delay;
5444 + unsigned int dbounce:1;
5445 + /* specific to OMAP242x*/
5446 + unsigned int *row_gpios;
5447 + unsigned int *col_gpios;
5448 +};
5449 +
5450 +/* Group (0..3) -- when multiple keys are pressed, only the
5451 + * keys pressed in the same group are considered as pressed. This is
5452 + * in order to workaround certain crappy HW designs that produce ghost
5453 + * keypresses. */
5454 +#define GROUP_0 (0 << 16)
5455 +#define GROUP_1 (1 << 16)
5456 +#define GROUP_2 (2 << 16)
5457 +#define GROUP_3 (3 << 16)
5458 +#define GROUP_MASK GROUP_3
5459 +
5460 +#define KEY_PERSISTENT 0x00800000
5461 +#define KEYNUM_MASK 0x00EFFFFF
5462 +#define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val))
5463 +#define PERSISTENT_KEY(col, row) (((col) << 28) | ((row) << 24) | \
5464 + KEY_PERSISTENT)
5465 +
5466 +#endif
5467 +
5468 --- /dev/null
5469 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/lcd_mipid.h
5470 @@ -0,0 +1,29 @@
5471 +#ifndef __LCD_MIPID_H
5472 +#define __LCD_MIPID_H
5473 +
5474 +enum mipid_test_num {
5475 + MIPID_TEST_RGB_LINES,
5476 +};
5477 +
5478 +enum mipid_test_result {
5479 + MIPID_TEST_SUCCESS,
5480 + MIPID_TEST_INVALID,
5481 + MIPID_TEST_FAILED,
5482 +};
5483 +
5484 +#ifdef __KERNEL__
5485 +
5486 +struct mipid_platform_data {
5487 + int nreset_gpio;
5488 + int data_lines;
5489 +
5490 + void (*shutdown)(struct mipid_platform_data *pdata);
5491 + void (*set_bklight_level)(struct mipid_platform_data *pdata,
5492 + int level);
5493 + int (*get_bklight_level)(struct mipid_platform_data *pdata);
5494 + int (*get_bklight_max)(struct mipid_platform_data *pdata);
5495 +};
5496 +
5497 +#endif
5498 +
5499 +#endif
5500 --- /dev/null
5501 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/led.h
5502 @@ -0,0 +1,24 @@
5503 +/*
5504 + * arch/arm/plat-omap/include/mach/led.h
5505 + *
5506 + * Copyright (C) 2006 Samsung Electronics
5507 + * Kyungmin Park <kyungmin.park@samsung.com>
5508 + *
5509 + * This program is free software; you can redistribute it and/or modify
5510 + * it under the terms of the GNU General Public License version 2 as
5511 + * published by the Free Software Foundation.
5512 + */
5513 +#ifndef ASMARM_ARCH_LED_H
5514 +#define ASMARM_ARCH_LED_H
5515 +
5516 +struct omap_led_config {
5517 + struct led_classdev cdev;
5518 + s16 gpio;
5519 +};
5520 +
5521 +struct omap_led_platform_data {
5522 + s16 nr_leds;
5523 + struct omap_led_config *leds;
5524 +};
5525 +
5526 +#endif
5527 --- /dev/null
5528 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/mailbox.h
5529 @@ -0,0 +1,111 @@
5530 +/* mailbox.h */
5531 +
5532 +#ifndef MAILBOX_H
5533 +#define MAILBOX_H
5534 +
5535 +#include <linux/wait.h>
5536 +#include <linux/workqueue.h>
5537 +#include <linux/blkdev.h>
5538 +#include <linux/interrupt.h>
5539 +
5540 +typedef u32 mbox_msg_t;
5541 +struct omap_mbox;
5542 +
5543 +typedef int __bitwise omap_mbox_irq_t;
5544 +#define IRQ_TX ((__force omap_mbox_irq_t) 1)
5545 +#define IRQ_RX ((__force omap_mbox_irq_t) 2)
5546 +
5547 +typedef int __bitwise omap_mbox_type_t;
5548 +#define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1)
5549 +#define OMAP_MBOX_TYPE2 ((__force omap_mbox_type_t) 2)
5550 +
5551 +struct omap_mbox_ops {
5552 + omap_mbox_type_t type;
5553 + int (*startup)(struct omap_mbox *mbox);
5554 + void (*shutdown)(struct omap_mbox *mbox);
5555 + /* fifo */
5556 + mbox_msg_t (*fifo_read)(struct omap_mbox *mbox);
5557 + void (*fifo_write)(struct omap_mbox *mbox, mbox_msg_t msg);
5558 + int (*fifo_empty)(struct omap_mbox *mbox);
5559 + int (*fifo_full)(struct omap_mbox *mbox);
5560 + /* irq */
5561 + void (*enable_irq)(struct omap_mbox *mbox,
5562 + omap_mbox_irq_t irq);
5563 + void (*disable_irq)(struct omap_mbox *mbox,
5564 + omap_mbox_irq_t irq);
5565 + void (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
5566 + int (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
5567 + /* ctx */
5568 + void (*save_ctx)(struct omap_mbox *mbox);
5569 + void (*restore_ctx)(struct omap_mbox *mbox);
5570 +};
5571 +
5572 +struct omap_mbox_queue {
5573 + spinlock_t lock;
5574 + struct request_queue *queue;
5575 + struct work_struct work;
5576 + struct tasklet_struct tasklet;
5577 + int (*callback)(void *);
5578 + struct omap_mbox *mbox;
5579 +};
5580 +
5581 +struct omap_mbox {
5582 + char *name;
5583 + unsigned int irq;
5584 +
5585 + struct omap_mbox_queue *txq, *rxq;
5586 +
5587 + struct omap_mbox_ops *ops;
5588 +
5589 + mbox_msg_t seq_snd, seq_rcv;
5590 +
5591 + struct device *dev;
5592 +
5593 + struct omap_mbox *next;
5594 + void *priv;
5595 +
5596 + void (*err_notify)(void);
5597 +};
5598 +
5599 +int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
5600 +void omap_mbox_init_seq(struct omap_mbox *);
5601 +
5602 +struct omap_mbox *omap_mbox_get(const char *);
5603 +void omap_mbox_put(struct omap_mbox *);
5604 +
5605 +int omap_mbox_register(struct device *parent, struct omap_mbox *);
5606 +int omap_mbox_unregister(struct omap_mbox *);
5607 +
5608 +static inline void omap_mbox_save_ctx(struct omap_mbox *mbox)
5609 +{
5610 + if (!mbox->ops->save_ctx) {
5611 + dev_err(mbox->dev, "%s:\tno save\n", __func__);
5612 + return;
5613 + }
5614 +
5615 + mbox->ops->save_ctx(mbox);
5616 +}
5617 +
5618 +static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox)
5619 +{
5620 + if (!mbox->ops->restore_ctx) {
5621 + dev_err(mbox->dev, "%s:\tno restore\n", __func__);
5622 + return;
5623 + }
5624 +
5625 + mbox->ops->restore_ctx(mbox);
5626 +}
5627 +
5628 +static inline void omap_mbox_enable_irq(struct omap_mbox *mbox,
5629 + omap_mbox_irq_t irq)
5630 +{
5631 + mbox->ops->enable_irq(mbox, irq);
5632 +}
5633 +
5634 +static inline void omap_mbox_disable_irq(struct omap_mbox *mbox,
5635 + omap_mbox_irq_t irq)
5636 +{
5637 + mbox->ops->disable_irq(mbox, irq);
5638 +}
5639 +
5640 +#endif /* MAILBOX_H */
5641 --- /dev/null
5642 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/mcbsp.h
5643 @@ -0,0 +1,462 @@
5644 +/*
5645 + * arch/arm/plat-omap/include/mach/mcbsp.h
5646 + *
5647 + * Defines for Multi-Channel Buffered Serial Port
5648 + *
5649 + * Copyright (C) 2002 RidgeRun, Inc.
5650 + * Author: Steve Johnson
5651 + *
5652 + * This program is free software; you can redistribute it and/or modify
5653 + * it under the terms of the GNU General Public License as published by
5654 + * the Free Software Foundation; either version 2 of the License, or
5655 + * (at your option) any later version.
5656 + *
5657 + * This program is distributed in the hope that it will be useful,
5658 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5659 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5660 + * GNU General Public License for more details.
5661 + *
5662 + * You should have received a copy of the GNU General Public License
5663 + * along with this program; if not, write to the Free Software
5664 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5665 + *
5666 + */
5667 +#ifndef __ASM_ARCH_OMAP_MCBSP_H
5668 +#define __ASM_ARCH_OMAP_MCBSP_H
5669 +
5670 +#include <linux/completion.h>
5671 +#include <linux/spinlock.h>
5672 +
5673 +#include <mach/hardware.h>
5674 +#include <plat/clock.h>
5675 +
5676 +#define OMAP7XX_MCBSP1_BASE 0xfffb1000
5677 +#define OMAP7XX_MCBSP2_BASE 0xfffb1800
5678 +
5679 +#define OMAP1510_MCBSP1_BASE 0xe1011800
5680 +#define OMAP1510_MCBSP2_BASE 0xfffb1000
5681 +#define OMAP1510_MCBSP3_BASE 0xe1017000
5682 +
5683 +#define OMAP1610_MCBSP1_BASE 0xe1011800
5684 +#define OMAP1610_MCBSP2_BASE 0xfffb1000
5685 +#define OMAP1610_MCBSP3_BASE 0xe1017000
5686 +
5687 +#define OMAP24XX_MCBSP1_BASE 0x48074000
5688 +#define OMAP24XX_MCBSP2_BASE 0x48076000
5689 +#define OMAP2430_MCBSP3_BASE 0x4808c000
5690 +#define OMAP2430_MCBSP4_BASE 0x4808e000
5691 +#define OMAP2430_MCBSP5_BASE 0x48096000
5692 +
5693 +#define OMAP34XX_MCBSP1_BASE 0x48074000
5694 +#define OMAP34XX_MCBSP2_BASE 0x49022000
5695 +#define OMAP34XX_MCBSP3_BASE 0x49024000
5696 +#define OMAP34XX_MCBSP4_BASE 0x49026000
5697 +#define OMAP34XX_MCBSP5_BASE 0x48096000
5698 +
5699 +#define OMAP44XX_MCBSP1_BASE 0x49022000
5700 +#define OMAP44XX_MCBSP2_BASE 0x49024000
5701 +#define OMAP44XX_MCBSP3_BASE 0x49026000
5702 +#define OMAP44XX_MCBSP4_BASE 0x48074000
5703 +
5704 +#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
5705 +
5706 +#define OMAP_MCBSP_REG_DRR2 0x00
5707 +#define OMAP_MCBSP_REG_DRR1 0x02
5708 +#define OMAP_MCBSP_REG_DXR2 0x04
5709 +#define OMAP_MCBSP_REG_DXR1 0x06
5710 +#define OMAP_MCBSP_REG_SPCR2 0x08
5711 +#define OMAP_MCBSP_REG_SPCR1 0x0a
5712 +#define OMAP_MCBSP_REG_RCR2 0x0c
5713 +#define OMAP_MCBSP_REG_RCR1 0x0e
5714 +#define OMAP_MCBSP_REG_XCR2 0x10
5715 +#define OMAP_MCBSP_REG_XCR1 0x12
5716 +#define OMAP_MCBSP_REG_SRGR2 0x14
5717 +#define OMAP_MCBSP_REG_SRGR1 0x16
5718 +#define OMAP_MCBSP_REG_MCR2 0x18
5719 +#define OMAP_MCBSP_REG_MCR1 0x1a
5720 +#define OMAP_MCBSP_REG_RCERA 0x1c
5721 +#define OMAP_MCBSP_REG_RCERB 0x1e
5722 +#define OMAP_MCBSP_REG_XCERA 0x20
5723 +#define OMAP_MCBSP_REG_XCERB 0x22
5724 +#define OMAP_MCBSP_REG_PCR0 0x24
5725 +#define OMAP_MCBSP_REG_RCERC 0x26
5726 +#define OMAP_MCBSP_REG_RCERD 0x28
5727 +#define OMAP_MCBSP_REG_XCERC 0x2A
5728 +#define OMAP_MCBSP_REG_XCERD 0x2C
5729 +#define OMAP_MCBSP_REG_RCERE 0x2E
5730 +#define OMAP_MCBSP_REG_RCERF 0x30
5731 +#define OMAP_MCBSP_REG_XCERE 0x32
5732 +#define OMAP_MCBSP_REG_XCERF 0x34
5733 +#define OMAP_MCBSP_REG_RCERG 0x36
5734 +#define OMAP_MCBSP_REG_RCERH 0x38
5735 +#define OMAP_MCBSP_REG_XCERG 0x3A
5736 +#define OMAP_MCBSP_REG_XCERH 0x3C
5737 +
5738 +/* Dummy defines, these are not available on omap1 */
5739 +#define OMAP_MCBSP_REG_XCCR 0x00
5740 +#define OMAP_MCBSP_REG_RCCR 0x00
5741 +
5742 +#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
5743 +#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
5744 +
5745 +#define AUDIO_MCBSP OMAP_MCBSP1
5746 +#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
5747 +#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
5748 +
5749 +#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
5750 + defined(CONFIG_ARCH_OMAP4)
5751 +
5752 +#define OMAP_MCBSP_REG_DRR2 0x00
5753 +#define OMAP_MCBSP_REG_DRR1 0x04
5754 +#define OMAP_MCBSP_REG_DXR2 0x08
5755 +#define OMAP_MCBSP_REG_DXR1 0x0C
5756 +#define OMAP_MCBSP_REG_DRR 0x00
5757 +#define OMAP_MCBSP_REG_DXR 0x08
5758 +#define OMAP_MCBSP_REG_SPCR2 0x10
5759 +#define OMAP_MCBSP_REG_SPCR1 0x14
5760 +#define OMAP_MCBSP_REG_RCR2 0x18
5761 +#define OMAP_MCBSP_REG_RCR1 0x1C
5762 +#define OMAP_MCBSP_REG_XCR2 0x20
5763 +#define OMAP_MCBSP_REG_XCR1 0x24
5764 +#define OMAP_MCBSP_REG_SRGR2 0x28
5765 +#define OMAP_MCBSP_REG_SRGR1 0x2C
5766 +#define OMAP_MCBSP_REG_MCR2 0x30
5767 +#define OMAP_MCBSP_REG_MCR1 0x34
5768 +#define OMAP_MCBSP_REG_RCERA 0x38
5769 +#define OMAP_MCBSP_REG_RCERB 0x3C
5770 +#define OMAP_MCBSP_REG_XCERA 0x40
5771 +#define OMAP_MCBSP_REG_XCERB 0x44
5772 +#define OMAP_MCBSP_REG_PCR0 0x48
5773 +#define OMAP_MCBSP_REG_RCERC 0x4C
5774 +#define OMAP_MCBSP_REG_RCERD 0x50
5775 +#define OMAP_MCBSP_REG_XCERC 0x54
5776 +#define OMAP_MCBSP_REG_XCERD 0x58
5777 +#define OMAP_MCBSP_REG_RCERE 0x5C
5778 +#define OMAP_MCBSP_REG_RCERF 0x60
5779 +#define OMAP_MCBSP_REG_XCERE 0x64
5780 +#define OMAP_MCBSP_REG_XCERF 0x68
5781 +#define OMAP_MCBSP_REG_RCERG 0x6C
5782 +#define OMAP_MCBSP_REG_RCERH 0x70
5783 +#define OMAP_MCBSP_REG_XCERG 0x74
5784 +#define OMAP_MCBSP_REG_XCERH 0x78
5785 +#define OMAP_MCBSP_REG_SYSCON 0x8C
5786 +#define OMAP_MCBSP_REG_THRSH2 0x90
5787 +#define OMAP_MCBSP_REG_THRSH1 0x94
5788 +#define OMAP_MCBSP_REG_IRQST 0xA0
5789 +#define OMAP_MCBSP_REG_IRQEN 0xA4
5790 +#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
5791 +#define OMAP_MCBSP_REG_XCCR 0xAC
5792 +#define OMAP_MCBSP_REG_RCCR 0xB0
5793 +
5794 +#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
5795 +#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
5796 +
5797 +#define AUDIO_MCBSP OMAP_MCBSP2
5798 +#define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX
5799 +#define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX
5800 +
5801 +#endif
5802 +
5803 +/************************** McBSP SPCR1 bit definitions ***********************/
5804 +#define RRST 0x0001
5805 +#define RRDY 0x0002
5806 +#define RFULL 0x0004
5807 +#define RSYNC_ERR 0x0008
5808 +#define RINTM(value) ((value)<<4) /* bits 4:5 */
5809 +#define ABIS 0x0040
5810 +#define DXENA 0x0080
5811 +#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
5812 +#define RJUST(value) ((value)<<13) /* bits 13:14 */
5813 +#define ALB 0x8000
5814 +#define DLB 0x8000
5815 +
5816 +/************************** McBSP SPCR2 bit definitions ***********************/
5817 +#define XRST 0x0001
5818 +#define XRDY 0x0002
5819 +#define XEMPTY 0x0004
5820 +#define XSYNC_ERR 0x0008
5821 +#define XINTM(value) ((value)<<4) /* bits 4:5 */
5822 +#define GRST 0x0040
5823 +#define FRST 0x0080
5824 +#define SOFT 0x0100
5825 +#define FREE 0x0200
5826 +
5827 +/************************** McBSP PCR bit definitions *************************/
5828 +#define CLKRP 0x0001
5829 +#define CLKXP 0x0002
5830 +#define FSRP 0x0004
5831 +#define FSXP 0x0008
5832 +#define DR_STAT 0x0010
5833 +#define DX_STAT 0x0020
5834 +#define CLKS_STAT 0x0040
5835 +#define SCLKME 0x0080
5836 +#define CLKRM 0x0100
5837 +#define CLKXM 0x0200
5838 +#define FSRM 0x0400
5839 +#define FSXM 0x0800
5840 +#define RIOEN 0x1000
5841 +#define XIOEN 0x2000
5842 +#define IDLE_EN 0x4000
5843 +
5844 +/************************** McBSP RCR1 bit definitions ************************/
5845 +#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
5846 +#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
5847 +
5848 +/************************** McBSP XCR1 bit definitions ************************/
5849 +#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
5850 +#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
5851 +
5852 +/*************************** McBSP RCR2 bit definitions ***********************/
5853 +#define RDATDLY(value) (value) /* Bits 0:1 */
5854 +#define RFIG 0x0004
5855 +#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
5856 +#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
5857 +#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
5858 +#define RPHASE 0x8000
5859 +
5860 +/*************************** McBSP XCR2 bit definitions ***********************/
5861 +#define XDATDLY(value) (value) /* Bits 0:1 */
5862 +#define XFIG 0x0004
5863 +#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
5864 +#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
5865 +#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
5866 +#define XPHASE 0x8000
5867 +
5868 +/************************* McBSP SRGR1 bit definitions ************************/
5869 +#define CLKGDV(value) (value) /* Bits 0:7 */
5870 +#define FWID(value) ((value)<<8) /* Bits 8:15 */
5871 +
5872 +/************************* McBSP SRGR2 bit definitions ************************/
5873 +#define FPER(value) (value) /* Bits 0:11 */
5874 +#define FSGM 0x1000
5875 +#define CLKSM 0x2000
5876 +#define CLKSP 0x4000
5877 +#define GSYNC 0x8000
5878 +
5879 +/************************* McBSP MCR1 bit definitions *************************/
5880 +#define RMCM 0x0001
5881 +#define RCBLK(value) ((value)<<2) /* Bits 2:4 */
5882 +#define RPABLK(value) ((value)<<5) /* Bits 5:6 */
5883 +#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
5884 +
5885 +/************************* McBSP MCR2 bit definitions *************************/
5886 +#define XMCM(value) (value) /* Bits 0:1 */
5887 +#define XCBLK(value) ((value)<<2) /* Bits 2:4 */
5888 +#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
5889 +#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
5890 +
5891 +/*********************** McBSP XCCR bit definitions *************************/
5892 +#define EXTCLKGATE 0x8000
5893 +#define PPCONNECT 0x4000
5894 +#define DXENDLY(value) ((value)<<12) /* Bits 12:13 */
5895 +#define XFULL_CYCLE 0x0800
5896 +#define DILB 0x0020
5897 +#define XDMAEN 0x0008
5898 +#define XDISABLE 0x0001
5899 +
5900 +/********************** McBSP RCCR bit definitions *************************/
5901 +#define RFULL_CYCLE 0x0800
5902 +#define RDMAEN 0x0008
5903 +#define RDISABLE 0x0001
5904 +
5905 +/********************** McBSP SYSCONFIG bit definitions ********************/
5906 +#define CLOCKACTIVITY(value) ((value)<<8)
5907 +#define SIDLEMODE(value) ((value)<<3)
5908 +#define ENAWAKEUP 0x0004
5909 +#define SOFTRST 0x0002
5910 +
5911 +/********************** McBSP DMA operating modes **************************/
5912 +#define MCBSP_DMA_MODE_ELEMENT 0
5913 +#define MCBSP_DMA_MODE_THRESHOLD 1
5914 +#define MCBSP_DMA_MODE_FRAME 2
5915 +
5916 +/********************** McBSP WAKEUPEN bit definitions *********************/
5917 +#define XEMPTYEOFEN 0x4000
5918 +#define XRDYEN 0x0400
5919 +#define XEOFEN 0x0200
5920 +#define XFSXEN 0x0100
5921 +#define XSYNCERREN 0x0080
5922 +#define RRDYEN 0x0008
5923 +#define REOFEN 0x0004
5924 +#define RFSREN 0x0002
5925 +#define RSYNCERREN 0x0001
5926 +
5927 +/* we don't do multichannel for now */
5928 +struct omap_mcbsp_reg_cfg {
5929 + u16 spcr2;
5930 + u16 spcr1;
5931 + u16 rcr2;
5932 + u16 rcr1;
5933 + u16 xcr2;
5934 + u16 xcr1;
5935 + u16 srgr2;
5936 + u16 srgr1;
5937 + u16 mcr2;
5938 + u16 mcr1;
5939 + u16 pcr0;
5940 + u16 rcerc;
5941 + u16 rcerd;
5942 + u16 xcerc;
5943 + u16 xcerd;
5944 + u16 rcere;
5945 + u16 rcerf;
5946 + u16 xcere;
5947 + u16 xcerf;
5948 + u16 rcerg;
5949 + u16 rcerh;
5950 + u16 xcerg;
5951 + u16 xcerh;
5952 + u16 xccr;
5953 + u16 rccr;
5954 +};
5955 +
5956 +typedef enum {
5957 + OMAP_MCBSP1 = 0,
5958 + OMAP_MCBSP2,
5959 + OMAP_MCBSP3,
5960 + OMAP_MCBSP4,
5961 + OMAP_MCBSP5
5962 +} omap_mcbsp_id;
5963 +
5964 +typedef int __bitwise omap_mcbsp_io_type_t;
5965 +#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
5966 +#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
5967 +
5968 +typedef enum {
5969 + OMAP_MCBSP_WORD_8 = 0,
5970 + OMAP_MCBSP_WORD_12,
5971 + OMAP_MCBSP_WORD_16,
5972 + OMAP_MCBSP_WORD_20,
5973 + OMAP_MCBSP_WORD_24,
5974 + OMAP_MCBSP_WORD_32,
5975 +} omap_mcbsp_word_length;
5976 +
5977 +typedef enum {
5978 + OMAP_MCBSP_CLK_RISING = 0,
5979 + OMAP_MCBSP_CLK_FALLING,
5980 +} omap_mcbsp_clk_polarity;
5981 +
5982 +typedef enum {
5983 + OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
5984 + OMAP_MCBSP_FS_ACTIVE_LOW,
5985 +} omap_mcbsp_fs_polarity;
5986 +
5987 +typedef enum {
5988 + OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
5989 + OMAP_MCBSP_CLK_STP_MODE_DELAY,
5990 +} omap_mcbsp_clk_stp_mode;
5991 +
5992 +
5993 +/******* SPI specific mode **********/
5994 +typedef enum {
5995 + OMAP_MCBSP_SPI_MASTER = 0,
5996 + OMAP_MCBSP_SPI_SLAVE,
5997 +} omap_mcbsp_spi_mode;
5998 +
5999 +struct omap_mcbsp_spi_cfg {
6000 + omap_mcbsp_spi_mode spi_mode;
6001 + omap_mcbsp_clk_polarity rx_clock_polarity;
6002 + omap_mcbsp_clk_polarity tx_clock_polarity;
6003 + omap_mcbsp_fs_polarity fsx_polarity;
6004 + u8 clk_div;
6005 + omap_mcbsp_clk_stp_mode clk_stp_mode;
6006 + omap_mcbsp_word_length word_length;
6007 +};
6008 +
6009 +/* Platform specific configuration */
6010 +struct omap_mcbsp_ops {
6011 + void (*request)(unsigned int);
6012 + void (*free)(unsigned int);
6013 +};
6014 +
6015 +struct omap_mcbsp_platform_data {
6016 + unsigned long phys_base;
6017 + u8 dma_rx_sync, dma_tx_sync;
6018 + u16 rx_irq, tx_irq;
6019 + struct omap_mcbsp_ops *ops;
6020 +#ifdef CONFIG_ARCH_OMAP34XX
6021 + u16 buffer_size;
6022 +#endif
6023 +};
6024 +
6025 +struct omap_mcbsp {
6026 + struct device *dev;
6027 + unsigned long phys_base;
6028 + void __iomem *io_base;
6029 + u8 id;
6030 + u8 free;
6031 + omap_mcbsp_word_length rx_word_length;
6032 + omap_mcbsp_word_length tx_word_length;
6033 +
6034 + omap_mcbsp_io_type_t io_type; /* IRQ or poll */
6035 + /* IRQ based TX/RX */
6036 + int rx_irq;
6037 + int tx_irq;
6038 +
6039 + /* DMA stuff */
6040 + u8 dma_rx_sync;
6041 + short dma_rx_lch;
6042 + u8 dma_tx_sync;
6043 + short dma_tx_lch;
6044 +
6045 + /* Completion queues */
6046 + struct completion tx_irq_completion;
6047 + struct completion rx_irq_completion;
6048 + struct completion tx_dma_completion;
6049 + struct completion rx_dma_completion;
6050 +
6051 + /* Protect the field .free, while checking if the mcbsp is in use */
6052 + spinlock_t lock;
6053 + struct omap_mcbsp_platform_data *pdata;
6054 + struct clk *iclk;
6055 + struct clk *fclk;
6056 +#ifdef CONFIG_ARCH_OMAP34XX
6057 + int dma_op_mode;
6058 + u16 max_tx_thres;
6059 + u16 max_rx_thres;
6060 +#endif
6061 +};
6062 +extern struct omap_mcbsp **mcbsp_ptr;
6063 +extern int omap_mcbsp_count;
6064 +
6065 +int omap_mcbsp_init(void);
6066 +void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
6067 + int size);
6068 +void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
6069 +#ifdef CONFIG_ARCH_OMAP34XX
6070 +void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
6071 +void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
6072 +u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
6073 +u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
6074 +int omap_mcbsp_get_dma_op_mode(unsigned int id);
6075 +#else
6076 +static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
6077 +{ }
6078 +static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
6079 +{ }
6080 +static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
6081 +static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
6082 +static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
6083 +#endif
6084 +int omap_mcbsp_request(unsigned int id);
6085 +void omap_mcbsp_free(unsigned int id);
6086 +void omap_mcbsp_start(unsigned int id, int tx, int rx);
6087 +void omap_mcbsp_stop(unsigned int id, int tx, int rx);
6088 +void omap_mcbsp_xmit_word(unsigned int id, u32 word);
6089 +u32 omap_mcbsp_recv_word(unsigned int id);
6090 +
6091 +int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
6092 +int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
6093 +int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
6094 +int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
6095 +
6096 +
6097 +/* SPI specific API */
6098 +void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
6099 +
6100 +/* Polled read/write functions */
6101 +int omap_mcbsp_pollread(unsigned int id, u16 * buf);
6102 +int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
6103 +int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
6104 +
6105 +#endif
6106 --- /dev/null
6107 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/mcspi.h
6108 @@ -0,0 +1,15 @@
6109 +#ifndef _OMAP2_MCSPI_H
6110 +#define _OMAP2_MCSPI_H
6111 +
6112 +struct omap2_mcspi_platform_config {
6113 + unsigned short num_cs;
6114 +};
6115 +
6116 +struct omap2_mcspi_device_config {
6117 + unsigned turbo_mode:1;
6118 +
6119 + /* Do we want one channel enabled at the same time? */
6120 + unsigned single_channel:1;
6121 +};
6122 +
6123 +#endif
6124 --- /dev/null
6125 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/memory.h
6126 @@ -0,0 +1,103 @@
6127 +/*
6128 + * arch/arm/plat-omap/include/mach/memory.h
6129 + *
6130 + * Memory map for OMAP-1510 and 1610
6131 + *
6132 + * Copyright (C) 2000 RidgeRun, Inc.
6133 + * Author: Greg Lonnon <glonnon@ridgerun.com>
6134 + *
6135 + * This file was derived from arch/arm/mach-intergrator/include/mach/memory.h
6136 + * Copyright (C) 1999 ARM Limited
6137 + *
6138 + * This program is free software; you can redistribute it and/or modify it
6139 + * under the terms of the GNU General Public License as published by the
6140 + * Free Software Foundation; either version 2 of the License, or (at your
6141 + * option) any later version.
6142 + *
6143 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6144 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6145 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6146 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6147 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6148 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6149 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6150 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6151 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6152 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6153 + *
6154 + * You should have received a copy of the GNU General Public License along
6155 + * with this program; if not, write to the Free Software Foundation, Inc.,
6156 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6157 + */
6158 +
6159 +#ifndef __ASM_ARCH_MEMORY_H
6160 +#define __ASM_ARCH_MEMORY_H
6161 +
6162 +/*
6163 + * Physical DRAM offset.
6164 + */
6165 +#if defined(CONFIG_ARCH_OMAP1)
6166 +#define PHYS_OFFSET UL(0x10000000)
6167 +#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
6168 + defined(CONFIG_ARCH_OMAP4)
6169 +#define PHYS_OFFSET UL(0x80000000)
6170 +#endif
6171 +
6172 +/*
6173 + * Bus address is physical address, except for OMAP-1510 Local Bus.
6174 + * OMAP-1510 bus address is translated into a Local Bus address if the
6175 + * OMAP bus type is lbus. We do the address translation based on the
6176 + * device overriding the defaults used in the dma-mapping API.
6177 + * Note that the is_lbus_device() test is not very efficient on 1510
6178 + * because of the strncmp().
6179 + */
6180 +#ifdef CONFIG_ARCH_OMAP15XX
6181 +
6182 +/*
6183 + * OMAP-1510 Local Bus address offset
6184 + */
6185 +#define OMAP1510_LB_OFFSET UL(0x30000000)
6186 +
6187 +#define virt_to_lbus(x) ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
6188 +#define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
6189 +#define is_lbus_device(dev) (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0))
6190 +
6191 +#define __arch_page_to_dma(dev, page) \
6192 + ({ dma_addr_t __dma = page_to_phys(page); \
6193 + if (is_lbus_device(dev)) \
6194 + __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \
6195 + __dma; })
6196 +
6197 +#define __arch_dma_to_page(dev, addr) \
6198 + ({ dma_addr_t __dma = addr; \
6199 + if (is_lbus_device(dev)) \
6200 + __dma += PHYS_OFFSET - OMAP1510_LB_OFFSET; \
6201 + phys_to_page(__dma); \
6202 + })
6203 +
6204 +#define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \
6205 + lbus_to_virt(addr) : \
6206 + __phys_to_virt(addr)); })
6207 +
6208 +#define __arch_virt_to_dma(dev, addr) ({ unsigned long __addr = (unsigned long)(addr); \
6209 + (dma_addr_t) (is_lbus_device(dev) ? \
6210 + virt_to_lbus(__addr) : \
6211 + __virt_to_phys(__addr)); })
6212 +
6213 +#endif /* CONFIG_ARCH_OMAP15XX */
6214 +
6215 +/* Override the ARM default */
6216 +#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
6217 +
6218 +#if (CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE == 0)
6219 +#undef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
6220 +#define CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE 2
6221 +#endif
6222 +
6223 +#define CONSISTENT_DMA_SIZE \
6224 + (((CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE + 1) & ~1) * 1024 * 1024)
6225 +
6226 +#endif
6227 +
6228 +#endif
6229 +
6230 --- /dev/null
6231 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/menelaus.h
6232 @@ -0,0 +1,49 @@
6233 +/*
6234 + * arch/arm/plat-omap/include/mach/menelaus.h
6235 + *
6236 + * Functions to access Menelaus power management chip
6237 + */
6238 +
6239 +#ifndef __ASM_ARCH_MENELAUS_H
6240 +#define __ASM_ARCH_MENELAUS_H
6241 +
6242 +struct device;
6243 +
6244 +struct menelaus_platform_data {
6245 + int (* late_init)(struct device *dev);
6246 +};
6247 +
6248 +extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask),
6249 + void *data);
6250 +extern void menelaus_unregister_mmc_callback(void);
6251 +extern int menelaus_set_mmc_opendrain(int slot, int enable);
6252 +extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on);
6253 +
6254 +extern int menelaus_set_vmem(unsigned int mV);
6255 +extern int menelaus_set_vio(unsigned int mV);
6256 +extern int menelaus_set_vmmc(unsigned int mV);
6257 +extern int menelaus_set_vaux(unsigned int mV);
6258 +extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
6259 +extern int menelaus_set_slot_sel(int enable);
6260 +extern int menelaus_get_slot_pin_states(void);
6261 +extern int menelaus_set_vcore_sw(unsigned int mV);
6262 +extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
6263 +
6264 +#define EN_VPLL_SLEEP (1 << 7)
6265 +#define EN_VMMC_SLEEP (1 << 6)
6266 +#define EN_VAUX_SLEEP (1 << 5)
6267 +#define EN_VIO_SLEEP (1 << 4)
6268 +#define EN_VMEM_SLEEP (1 << 3)
6269 +#define EN_DC3_SLEEP (1 << 2)
6270 +#define EN_DC2_SLEEP (1 << 1)
6271 +#define EN_VC_SLEEP (1 << 0)
6272 +
6273 +extern int menelaus_set_regulator_sleep(int enable, u32 val);
6274 +
6275 +#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS)
6276 +#define omap_has_menelaus() 1
6277 +#else
6278 +#define omap_has_menelaus() 0
6279 +#endif
6280 +
6281 +#endif
6282 --- /dev/null
6283 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/mmc.h
6284 @@ -0,0 +1,157 @@
6285 +/*
6286 + * MMC definitions for OMAP2
6287 + *
6288 + * Copyright (C) 2006 Nokia Corporation
6289 + *
6290 + * This program is free software; you can redistribute it and/or modify
6291 + * it under the terms of the GNU General Public License version 2 as
6292 + * published by the Free Software Foundation.
6293 + */
6294 +
6295 +#ifndef __OMAP2_MMC_H
6296 +#define __OMAP2_MMC_H
6297 +
6298 +#include <linux/types.h>
6299 +#include <linux/device.h>
6300 +#include <linux/mmc/host.h>
6301 +
6302 +#include <plat/board.h>
6303 +
6304 +#define OMAP15XX_NR_MMC 1
6305 +#define OMAP16XX_NR_MMC 2
6306 +#define OMAP1_MMC_SIZE 0x080
6307 +#define OMAP1_MMC1_BASE 0xfffb7800
6308 +#define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */
6309 +
6310 +#define OMAP24XX_NR_MMC 2
6311 +#define OMAP34XX_NR_MMC 3
6312 +#define OMAP44XX_NR_MMC 5
6313 +#define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE
6314 +#define OMAP3_HSMMC_SIZE 0x200
6315 +#define OMAP4_HSMMC_SIZE 0x1000
6316 +#define OMAP2_MMC1_BASE 0x4809c000
6317 +#define OMAP2_MMC2_BASE 0x480b4000
6318 +#define OMAP3_MMC3_BASE 0x480ad000
6319 +#define OMAP4_MMC4_BASE 0x480d1000
6320 +#define OMAP4_MMC5_BASE 0x480d5000
6321 +#define OMAP4_MMC_REG_OFFSET 0x100
6322 +#define HSMMC5 (1 << 4)
6323 +#define HSMMC4 (1 << 3)
6324 +#define HSMMC3 (1 << 2)
6325 +#define HSMMC2 (1 << 1)
6326 +#define HSMMC1 (1 << 0)
6327 +
6328 +#define OMAP_MMC_MAX_SLOTS 2
6329 +
6330 +struct omap_mmc_platform_data {
6331 + /* back-link to device */
6332 + struct device *dev;
6333 +
6334 + /* number of slots per controller */
6335 + unsigned nr_slots:2;
6336 +
6337 + /* set if your board has components or wiring that limits the
6338 + * maximum frequency on the MMC bus */
6339 + unsigned int max_freq;
6340 +
6341 + /* switch the bus to a new slot */
6342 + int (* switch_slot)(struct device *dev, int slot);
6343 + /* initialize board-specific MMC functionality, can be NULL if
6344 + * not supported */
6345 + int (* init)(struct device *dev);
6346 + void (* cleanup)(struct device *dev);
6347 + void (* shutdown)(struct device *dev);
6348 +
6349 + /* To handle board related suspend/resume functionality for MMC */
6350 + int (*suspend)(struct device *dev, int slot);
6351 + int (*resume)(struct device *dev, int slot);
6352 +
6353 + /* Return context loss count due to PM states changing */
6354 + int (*get_context_loss_count)(struct device *dev);
6355 +
6356 + u64 dma_mask;
6357 +
6358 + struct omap_mmc_slot_data {
6359 +
6360 + /* 4 wire signaling is optional, and is used for SD/SDIO/HSMMC;
6361 + * 8 wire signaling is also optional, and is used with HSMMC
6362 + */
6363 + u8 wires;
6364 +
6365 + /*
6366 + * nomux means "standard" muxing is wrong on this board, and
6367 + * that board-specific code handled it before common init logic.
6368 + */
6369 + unsigned nomux:1;
6370 +
6371 + /* switch pin can be for card detect (default) or card cover */
6372 + unsigned cover:1;
6373 +
6374 + /* use the internal clock */
6375 + unsigned internal_clock:1;
6376 +
6377 + /* nonremovable e.g. eMMC */
6378 + unsigned nonremovable:1;
6379 +
6380 + /* Try to sleep or power off when possible */
6381 + unsigned power_saving:1;
6382 +
6383 + int switch_pin; /* gpio (card detect) */
6384 + int gpio_wp; /* gpio (write protect) */
6385 +
6386 + int (* set_bus_mode)(struct device *dev, int slot, int bus_mode);
6387 + int (* set_power)(struct device *dev, int slot, int power_on, int vdd);
6388 + int (* get_ro)(struct device *dev, int slot);
6389 + int (*set_sleep)(struct device *dev, int slot, int sleep,
6390 + int vdd, int cardsleep);
6391 +
6392 + /* return MMC cover switch state, can be NULL if not supported.
6393 + *
6394 + * possible return values:
6395 + * 0 - closed
6396 + * 1 - open
6397 + */
6398 + int (* get_cover_state)(struct device *dev, int slot);
6399 +
6400 + const char *name;
6401 + u32 ocr_mask;
6402 +
6403 + /* Card detection IRQs */
6404 + int card_detect_irq;
6405 + int (* card_detect)(int irq);
6406 +
6407 + unsigned int ban_openended:1;
6408 +
6409 + } slots[OMAP_MMC_MAX_SLOTS];
6410 +};
6411 +
6412 +/* called from board-specific card detection service routine */
6413 +extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed);
6414 +
6415 +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
6416 + defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
6417 +void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
6418 + int nr_controllers);
6419 +void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
6420 + int nr_controllers);
6421 +int omap_mmc_add(const char *name, int id, unsigned long base,
6422 + unsigned long size, unsigned int irq,
6423 + struct omap_mmc_platform_data *data);
6424 +#else
6425 +static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
6426 + int nr_controllers)
6427 +{
6428 +}
6429 +static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
6430 + int nr_controllers)
6431 +{
6432 +}
6433 +static inline int omap_mmc_add(const char *name, int id, unsigned long base,
6434 + unsigned long size, unsigned int irq,
6435 + struct omap_mmc_platform_data *data)
6436 +{
6437 + return 0;
6438 +}
6439 +
6440 +#endif
6441 +#endif
6442 --- /dev/null
6443 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/mux.h
6444 @@ -0,0 +1,662 @@
6445 +/*
6446 + * arch/arm/plat-omap/include/mach/mux.h
6447 + *
6448 + * Table of the Omap register configurations for the FUNC_MUX and
6449 + * PULL_DWN combinations.
6450 + *
6451 + * Copyright (C) 2004 - 2008 Texas Instruments Inc.
6452 + * Copyright (C) 2003 - 2008 Nokia Corporation
6453 + *
6454 + * Written by Tony Lindgren
6455 + *
6456 + * This program is free software; you can redistribute it and/or modify
6457 + * it under the terms of the GNU General Public License as published by
6458 + * the Free Software Foundation; either version 2 of the License, or
6459 + * (at your option) any later version.
6460 + *
6461 + * This program is distributed in the hope that it will be useful,
6462 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6463 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6464 + * GNU General Public License for more details.
6465 + *
6466 + * You should have received a copy of the GNU General Public License
6467 + * along with this program; if not, write to the Free Software
6468 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6469 + *
6470 + * NOTE: Please use the following naming style for new pin entries.
6471 + * For example, W8_1610_MMC2_DAT0, where:
6472 + * - W8 = ball
6473 + * - 1610 = 1510 or 1610, none if common for both 1510 and 1610
6474 + * - MMC2_DAT0 = function
6475 + */
6476 +
6477 +#ifndef __ASM_ARCH_MUX_H
6478 +#define __ASM_ARCH_MUX_H
6479 +
6480 +#define PU_PD_SEL_NA 0 /* No pu_pd reg available */
6481 +#define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
6482 +
6483 +#ifdef CONFIG_OMAP_MUX_DEBUG
6484 +#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
6485 + .mux_reg = FUNC_MUX_CTRL_##reg, \
6486 + .mask_offset = mode_offset, \
6487 + .mask = mode,
6488 +
6489 +#define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \
6490 + .pull_reg = PULL_DWN_CTRL_##reg, \
6491 + .pull_bit = bit, \
6492 + .pull_val = status,
6493 +
6494 +#define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \
6495 + .pu_pd_reg = PU_PD_SEL_##reg, \
6496 + .pu_pd_val = status,
6497 +
6498 +#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
6499 + .mux_reg = OMAP7XX_IO_CONF_##reg, \
6500 + .mask_offset = mode_offset, \
6501 + .mask = mode,
6502 +
6503 +#define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \
6504 + .pull_reg = OMAP7XX_IO_CONF_##reg, \
6505 + .pull_bit = bit, \
6506 + .pull_val = status,
6507 +
6508 +#else
6509 +
6510 +#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
6511 + .mask_offset = mode_offset, \
6512 + .mask = mode,
6513 +
6514 +#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \
6515 + .pull_bit = bit, \
6516 + .pull_val = status,
6517 +
6518 +#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
6519 + .pu_pd_val = status,
6520 +
6521 +#define MUX_REG_7XX(reg, mode_offset, mode) \
6522 + .mux_reg = OMAP7XX_IO_CONF_##reg, \
6523 + .mask_offset = mode_offset, \
6524 + .mask = mode,
6525 +
6526 +#define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \
6527 + .pull_bit = bit, \
6528 + .pull_val = status,
6529 +
6530 +#endif /* CONFIG_OMAP_MUX_DEBUG */
6531 +
6532 +#define MUX_CFG(desc, mux_reg, mode_offset, mode, \
6533 + pull_reg, pull_bit, pull_status, \
6534 + pu_pd_reg, pu_pd_status, debug_status) \
6535 +{ \
6536 + .name = desc, \
6537 + .debug = debug_status, \
6538 + MUX_REG(mux_reg, mode_offset, mode) \
6539 + PULL_REG(pull_reg, pull_bit, pull_status) \
6540 + PU_PD_REG(pu_pd_reg, pu_pd_status) \
6541 +},
6542 +
6543 +
6544 +/*
6545 + * OMAP730/850 has a slightly different config for the pin mux.
6546 + * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
6547 + * not the FUNC_MUX_CTRL_x regs from hardware.h
6548 + * - for pull-up/down, only has one enable bit which is is in the same register
6549 + * as mux config
6550 + */
6551 +#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \
6552 + pull_bit, pull_status, debug_status)\
6553 +{ \
6554 + .name = desc, \
6555 + .debug = debug_status, \
6556 + MUX_REG_7XX(mux_reg, mode_offset, mode) \
6557 + PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
6558 + PU_PD_REG(NA, 0) \
6559 +},
6560 +
6561 +#define MUX_CFG_24XX(desc, reg_offset, mode, \
6562 + pull_en, pull_mode, dbg) \
6563 +{ \
6564 + .name = desc, \
6565 + .debug = dbg, \
6566 + .mux_reg = reg_offset, \
6567 + .mask = mode, \
6568 + .pull_val = pull_en, \
6569 + .pu_pd_val = pull_mode, \
6570 +},
6571 +
6572 +/* 24xx/34xx mux bit defines */
6573 +#define OMAP2_PULL_ENA (1 << 3)
6574 +#define OMAP2_PULL_UP (1 << 4)
6575 +#define OMAP2_ALTELECTRICALSEL (1 << 5)
6576 +
6577 +struct pin_config {
6578 + char *name;
6579 + const unsigned int mux_reg;
6580 + unsigned char debug;
6581 +
6582 +#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
6583 + const unsigned char mask_offset;
6584 + const unsigned char mask;
6585 +
6586 + const char *pull_name;
6587 + const unsigned int pull_reg;
6588 + const unsigned char pull_val;
6589 + const unsigned char pull_bit;
6590 +
6591 + const char *pu_pd_name;
6592 + const unsigned int pu_pd_reg;
6593 + const unsigned char pu_pd_val;
6594 +#endif
6595 +
6596 +#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
6597 + const char *mux_reg_name;
6598 +#endif
6599 +
6600 +};
6601 +
6602 +enum omap7xx_index {
6603 + /* OMAP 730 keyboard */
6604 + E2_7XX_KBR0,
6605 + J7_7XX_KBR1,
6606 + E1_7XX_KBR2,
6607 + F3_7XX_KBR3,
6608 + D2_7XX_KBR4,
6609 + C2_7XX_KBC0,
6610 + D3_7XX_KBC1,
6611 + E4_7XX_KBC2,
6612 + F4_7XX_KBC3,
6613 + E3_7XX_KBC4,
6614 +
6615 + /* USB */
6616 + AA17_7XX_USB_DM,
6617 + W16_7XX_USB_PU_EN,
6618 + W17_7XX_USB_VBUSI,
6619 + W18_7XX_USB_DMCK_OUT,
6620 + W19_7XX_USB_DCRST,
6621 +
6622 + /* MMC */
6623 + MMC_7XX_CMD,
6624 + MMC_7XX_CLK,
6625 + MMC_7XX_DAT0,
6626 +
6627 + /* I2C */
6628 + I2C_7XX_SCL,
6629 + I2C_7XX_SDA,
6630 +};
6631 +
6632 +enum omap1xxx_index {
6633 + /* UART1 (BT_UART_GATING)*/
6634 + UART1_TX = 0,
6635 + UART1_RTS,
6636 +
6637 + /* UART2 (COM_UART_GATING)*/
6638 + UART2_TX,
6639 + UART2_RX,
6640 + UART2_CTS,
6641 + UART2_RTS,
6642 +
6643 + /* UART3 (GIGA_UART_GATING) */
6644 + UART3_TX,
6645 + UART3_RX,
6646 + UART3_CTS,
6647 + UART3_RTS,
6648 + UART3_CLKREQ,
6649 + UART3_BCLK, /* 12MHz clock out */
6650 + Y15_1610_UART3_RTS,
6651 +
6652 + /* PWT & PWL */
6653 + PWT,
6654 + PWL,
6655 +
6656 + /* USB master generic */
6657 + R18_USB_VBUS,
6658 + R18_1510_USB_GPIO0,
6659 + W4_USB_PUEN,
6660 + W4_USB_CLKO,
6661 + W4_USB_HIGHZ,
6662 + W4_GPIO58,
6663 +
6664 + /* USB1 master */
6665 + USB1_SUSP,
6666 + USB1_SEO,
6667 + W13_1610_USB1_SE0,
6668 + USB1_TXEN,
6669 + USB1_TXD,
6670 + USB1_VP,
6671 + USB1_VM,
6672 + USB1_RCV,
6673 + USB1_SPEED,
6674 + R13_1610_USB1_SPEED,
6675 + R13_1710_USB1_SE0,
6676 +
6677 + /* USB2 master */
6678 + USB2_SUSP,
6679 + USB2_VP,
6680 + USB2_TXEN,
6681 + USB2_VM,
6682 + USB2_RCV,
6683 + USB2_SEO,
6684 + USB2_TXD,
6685 +
6686 + /* OMAP-1510 GPIO */
6687 + R18_1510_GPIO0,
6688 + R19_1510_GPIO1,
6689 + M14_1510_GPIO2,
6690 +
6691 + /* OMAP1610 GPIO */
6692 + P18_1610_GPIO3,
6693 + Y15_1610_GPIO17,
6694 +
6695 + /* OMAP-1710 GPIO */
6696 + R18_1710_GPIO0,
6697 + V2_1710_GPIO10,
6698 + N21_1710_GPIO14,
6699 + W15_1710_GPIO40,
6700 +
6701 + /* MPUIO */
6702 + MPUIO2,
6703 + N15_1610_MPUIO2,
6704 + MPUIO4,
6705 + MPUIO5,
6706 + T20_1610_MPUIO5,
6707 + W11_1610_MPUIO6,
6708 + V10_1610_MPUIO7,
6709 + W11_1610_MPUIO9,
6710 + V10_1610_MPUIO10,
6711 + W10_1610_MPUIO11,
6712 + E20_1610_MPUIO13,
6713 + U20_1610_MPUIO14,
6714 + E19_1610_MPUIO15,
6715 +
6716 + /* MCBSP2 */
6717 + MCBSP2_CLKR,
6718 + MCBSP2_CLKX,
6719 + MCBSP2_DR,
6720 + MCBSP2_DX,
6721 + MCBSP2_FSR,
6722 + MCBSP2_FSX,
6723 +
6724 + /* MCBSP3 */
6725 + MCBSP3_CLKX,
6726 +
6727 + /* Misc ballouts */
6728 + BALLOUT_V8_ARMIO3,
6729 + N20_HDQ,
6730 +
6731 + /* OMAP-1610 MMC2 */
6732 + W8_1610_MMC2_DAT0,
6733 + V8_1610_MMC2_DAT1,
6734 + W15_1610_MMC2_DAT2,
6735 + R10_1610_MMC2_DAT3,
6736 + Y10_1610_MMC2_CLK,
6737 + Y8_1610_MMC2_CMD,
6738 + V9_1610_MMC2_CMDDIR,
6739 + V5_1610_MMC2_DATDIR0,
6740 + W19_1610_MMC2_DATDIR1,
6741 + R18_1610_MMC2_CLKIN,
6742 +
6743 + /* OMAP-1610 External Trace Interface */
6744 + M19_1610_ETM_PSTAT0,
6745 + L15_1610_ETM_PSTAT1,
6746 + L18_1610_ETM_PSTAT2,
6747 + L19_1610_ETM_D0,
6748 + J19_1610_ETM_D6,
6749 + J18_1610_ETM_D7,
6750 +
6751 + /* OMAP16XX GPIO */
6752 + P20_1610_GPIO4,
6753 + V9_1610_GPIO7,
6754 + W8_1610_GPIO9,
6755 + N20_1610_GPIO11,
6756 + N19_1610_GPIO13,
6757 + P10_1610_GPIO22,
6758 + V5_1610_GPIO24,
6759 + AA20_1610_GPIO_41,
6760 + W19_1610_GPIO48,
6761 + M7_1610_GPIO62,
6762 + V14_16XX_GPIO37,
6763 + R9_16XX_GPIO18,
6764 + L14_16XX_GPIO49,
6765 +
6766 + /* OMAP-1610 uWire */
6767 + V19_1610_UWIRE_SCLK,
6768 + U18_1610_UWIRE_SDI,
6769 + W21_1610_UWIRE_SDO,
6770 + N14_1610_UWIRE_CS0,
6771 + P15_1610_UWIRE_CS3,
6772 + N15_1610_UWIRE_CS1,
6773 +
6774 + /* OMAP-1610 SPI */
6775 + U19_1610_SPIF_SCK,
6776 + U18_1610_SPIF_DIN,
6777 + P20_1610_SPIF_DIN,
6778 + W21_1610_SPIF_DOUT,
6779 + R18_1610_SPIF_DOUT,
6780 + N14_1610_SPIF_CS0,
6781 + N15_1610_SPIF_CS1,
6782 + T19_1610_SPIF_CS2,
6783 + P15_1610_SPIF_CS3,
6784 +
6785 + /* OMAP-1610 Flash */
6786 + L3_1610_FLASH_CS2B_OE,
6787 + M8_1610_FLASH_CS2B_WE,
6788 +
6789 + /* First MMC */
6790 + MMC_CMD,
6791 + MMC_DAT1,
6792 + MMC_DAT2,
6793 + MMC_DAT0,
6794 + MMC_CLK,
6795 + MMC_DAT3,
6796 +
6797 + /* OMAP-1710 MMC CMDDIR and DATDIR0 */
6798 + M15_1710_MMC_CLKI,
6799 + P19_1710_MMC_CMDDIR,
6800 + P20_1710_MMC_DATDIR0,
6801 +
6802 + /* OMAP-1610 USB0 alternate pin configuration */
6803 + W9_USB0_TXEN,
6804 + AA9_USB0_VP,
6805 + Y5_USB0_RCV,
6806 + R9_USB0_VM,
6807 + V6_USB0_TXD,
6808 + W5_USB0_SE0,
6809 + V9_USB0_SPEED,
6810 + V9_USB0_SUSP,
6811 +
6812 + /* USB2 */
6813 + W9_USB2_TXEN,
6814 + AA9_USB2_VP,
6815 + Y5_USB2_RCV,
6816 + R9_USB2_VM,
6817 + V6_USB2_TXD,
6818 + W5_USB2_SE0,
6819 +
6820 + /* 16XX UART */
6821 + R13_1610_UART1_TX,
6822 + V14_16XX_UART1_RX,
6823 + R14_1610_UART1_CTS,
6824 + AA15_1610_UART1_RTS,
6825 + R9_16XX_UART2_RX,
6826 + L14_16XX_UART3_RX,
6827 +
6828 + /* I2C OMAP-1610 */
6829 + I2C_SCL,
6830 + I2C_SDA,
6831 +
6832 + /* Keypad */
6833 + F18_1610_KBC0,
6834 + D20_1610_KBC1,
6835 + D19_1610_KBC2,
6836 + E18_1610_KBC3,
6837 + C21_1610_KBC4,
6838 + G18_1610_KBR0,
6839 + F19_1610_KBR1,
6840 + H14_1610_KBR2,
6841 + E20_1610_KBR3,
6842 + E19_1610_KBR4,
6843 + N19_1610_KBR5,
6844 +
6845 + /* Power management */
6846 + T20_1610_LOW_PWR,
6847 +
6848 + /* MCLK Settings */
6849 + V5_1710_MCLK_ON,
6850 + V5_1710_MCLK_OFF,
6851 + R10_1610_MCLK_ON,
6852 + R10_1610_MCLK_OFF,
6853 +
6854 + /* CompactFlash controller */
6855 + P11_1610_CF_CD2,
6856 + R11_1610_CF_IOIS16,
6857 + V10_1610_CF_IREQ,
6858 + W10_1610_CF_RESET,
6859 + W11_1610_CF_CD1,
6860 +
6861 + /* parallel camera */
6862 + J15_1610_CAM_LCLK,
6863 + J18_1610_CAM_D7,
6864 + J19_1610_CAM_D6,
6865 + J14_1610_CAM_D5,
6866 + K18_1610_CAM_D4,
6867 + K19_1610_CAM_D3,
6868 + K15_1610_CAM_D2,
6869 + K14_1610_CAM_D1,
6870 + L19_1610_CAM_D0,
6871 + L18_1610_CAM_VS,
6872 + L15_1610_CAM_HS,
6873 + M19_1610_CAM_RSTZ,
6874 + Y15_1610_CAM_OUTCLK,
6875 +
6876 + /* serial camera */
6877 + H19_1610_CAM_EXCLK,
6878 + Y12_1610_CCP_CLKP,
6879 + W13_1610_CCP_CLKM,
6880 + W14_1610_CCP_DATAP,
6881 + Y14_1610_CCP_DATAM,
6882 +
6883 +};
6884 +
6885 +enum omap24xx_index {
6886 + /* 24xx I2C */
6887 + M19_24XX_I2C1_SCL,
6888 + L15_24XX_I2C1_SDA,
6889 + J15_24XX_I2C2_SCL,
6890 + H19_24XX_I2C2_SDA,
6891 +
6892 + /* 24xx Menelaus interrupt */
6893 + W19_24XX_SYS_NIRQ,
6894 +
6895 + /* 24xx clock */
6896 + W14_24XX_SYS_CLKOUT,
6897 +
6898 + /* 24xx GPMC chipselects, wait pin monitoring */
6899 + E2_GPMC_NCS2,
6900 + L2_GPMC_NCS7,
6901 + L3_GPMC_WAIT0,
6902 + N7_GPMC_WAIT1,
6903 + M1_GPMC_WAIT2,
6904 + P1_GPMC_WAIT3,
6905 +
6906 + /* 242X McBSP */
6907 + Y15_24XX_MCBSP2_CLKX,
6908 + R14_24XX_MCBSP2_FSX,
6909 + W15_24XX_MCBSP2_DR,
6910 + V15_24XX_MCBSP2_DX,
6911 +
6912 + /* 24xx GPIO */
6913 + M21_242X_GPIO11,
6914 + P21_242X_GPIO12,
6915 + AA10_242X_GPIO13,
6916 + AA6_242X_GPIO14,
6917 + AA4_242X_GPIO15,
6918 + Y11_242X_GPIO16,
6919 + AA12_242X_GPIO17,
6920 + AA8_242X_GPIO58,
6921 + Y20_24XX_GPIO60,
6922 + W4__24XX_GPIO74,
6923 + N15_24XX_GPIO85,
6924 + M15_24XX_GPIO92,
6925 + P20_24XX_GPIO93,
6926 + P18_24XX_GPIO95,
6927 + M18_24XX_GPIO96,
6928 + L14_24XX_GPIO97,
6929 + J15_24XX_GPIO99,
6930 + V14_24XX_GPIO117,
6931 + P14_24XX_GPIO125,
6932 +
6933 + /* 242x DBG GPIO */
6934 + V4_242X_GPIO49,
6935 + W2_242X_GPIO50,
6936 + U4_242X_GPIO51,
6937 + V3_242X_GPIO52,
6938 + V2_242X_GPIO53,
6939 + V6_242X_GPIO53,
6940 + T4_242X_GPIO54,
6941 + Y4_242X_GPIO54,
6942 + T3_242X_GPIO55,
6943 + U2_242X_GPIO56,
6944 +
6945 + /* 24xx external DMA requests */
6946 + AA10_242X_DMAREQ0,
6947 + AA6_242X_DMAREQ1,
6948 + E4_242X_DMAREQ2,
6949 + G4_242X_DMAREQ3,
6950 + D3_242X_DMAREQ4,
6951 + E3_242X_DMAREQ5,
6952 +
6953 + /* UART3 */
6954 + K15_24XX_UART3_TX,
6955 + K14_24XX_UART3_RX,
6956 +
6957 + /* MMC/SDIO */
6958 + G19_24XX_MMC_CLKO,
6959 + H18_24XX_MMC_CMD,
6960 + F20_24XX_MMC_DAT0,
6961 + H14_24XX_MMC_DAT1,
6962 + E19_24XX_MMC_DAT2,
6963 + D19_24XX_MMC_DAT3,
6964 + F19_24XX_MMC_DAT_DIR0,
6965 + E20_24XX_MMC_DAT_DIR1,
6966 + F18_24XX_MMC_DAT_DIR2,
6967 + E18_24XX_MMC_DAT_DIR3,
6968 + G18_24XX_MMC_CMD_DIR,
6969 + H15_24XX_MMC_CLKI,
6970 +
6971 + /* Full speed USB */
6972 + J20_24XX_USB0_PUEN,
6973 + J19_24XX_USB0_VP,
6974 + K20_24XX_USB0_VM,
6975 + J18_24XX_USB0_RCV,
6976 + K19_24XX_USB0_TXEN,
6977 + J14_24XX_USB0_SE0,
6978 + K18_24XX_USB0_DAT,
6979 +
6980 + N14_24XX_USB1_SE0,
6981 + W12_24XX_USB1_SE0,
6982 + P15_24XX_USB1_DAT,
6983 + R13_24XX_USB1_DAT,
6984 + W20_24XX_USB1_TXEN,
6985 + P13_24XX_USB1_TXEN,
6986 + V19_24XX_USB1_RCV,
6987 + V12_24XX_USB1_RCV,
6988 +
6989 + AA10_24XX_USB2_SE0,
6990 + Y11_24XX_USB2_DAT,
6991 + AA12_24XX_USB2_TXEN,
6992 + AA6_24XX_USB2_RCV,
6993 + AA4_24XX_USB2_TLLSE0,
6994 +
6995 + /* Keypad GPIO*/
6996 + T19_24XX_KBR0,
6997 + R19_24XX_KBR1,
6998 + V18_24XX_KBR2,
6999 + M21_24XX_KBR3,
7000 + E5__24XX_KBR4,
7001 + M18_24XX_KBR5,
7002 + R20_24XX_KBC0,
7003 + M14_24XX_KBC1,
7004 + H19_24XX_KBC2,
7005 + V17_24XX_KBC3,
7006 + P21_24XX_KBC4,
7007 + L14_24XX_KBC5,
7008 + N19_24XX_KBC6,
7009 +
7010 + /* 24xx Menelaus Keypad GPIO */
7011 + B3__24XX_KBR5,
7012 + AA4_24XX_KBC2,
7013 + B13_24XX_KBC6,
7014 +
7015 + /* 2430 USB */
7016 + AD9_2430_USB0_PUEN,
7017 + Y11_2430_USB0_VP,
7018 + AD7_2430_USB0_VM,
7019 + AE7_2430_USB0_RCV,
7020 + AD4_2430_USB0_TXEN,
7021 + AF9_2430_USB0_SE0,
7022 + AE6_2430_USB0_DAT,
7023 + AD24_2430_USB1_SE0,
7024 + AB24_2430_USB1_RCV,
7025 + Y25_2430_USB1_TXEN,
7026 + AA26_2430_USB1_DAT,
7027 +
7028 + /* 2430 HS-USB */
7029 + AD9_2430_USB0HS_DATA3,
7030 + Y11_2430_USB0HS_DATA4,
7031 + AD7_2430_USB0HS_DATA5,
7032 + AE7_2430_USB0HS_DATA6,
7033 + AD4_2430_USB0HS_DATA2,
7034 + AF9_2430_USB0HS_DATA0,
7035 + AE6_2430_USB0HS_DATA1,
7036 + AE8_2430_USB0HS_CLK,
7037 + AD8_2430_USB0HS_DIR,
7038 + AE5_2430_USB0HS_STP,
7039 + AE9_2430_USB0HS_NXT,
7040 + AC7_2430_USB0HS_DATA7,
7041 +
7042 + /* 2430 McBSP */
7043 + AD6_2430_MCBSP_CLKS,
7044 +
7045 + AB2_2430_MCBSP1_CLKR,
7046 + AD5_2430_MCBSP1_FSR,
7047 + AA1_2430_MCBSP1_DX,
7048 + AF3_2430_MCBSP1_DR,
7049 + AB3_2430_MCBSP1_FSX,
7050 + Y9_2430_MCBSP1_CLKX,
7051 +
7052 + AC10_2430_MCBSP2_FSX,
7053 + AD16_2430_MCBSP2_CLX,
7054 + AE13_2430_MCBSP2_DX,
7055 + AD13_2430_MCBSP2_DR,
7056 + AC10_2430_MCBSP2_FSX_OFF,
7057 + AD16_2430_MCBSP2_CLX_OFF,
7058 + AE13_2430_MCBSP2_DX_OFF,
7059 + AD13_2430_MCBSP2_DR_OFF,
7060 +
7061 + AC9_2430_MCBSP3_CLKX,
7062 + AE4_2430_MCBSP3_FSX,
7063 + AE2_2430_MCBSP3_DR,
7064 + AF4_2430_MCBSP3_DX,
7065 +
7066 + N3_2430_MCBSP4_CLKX,
7067 + AD23_2430_MCBSP4_DR,
7068 + AB25_2430_MCBSP4_DX,
7069 + AC25_2430_MCBSP4_FSX,
7070 +
7071 + AE16_2430_MCBSP5_CLKX,
7072 + AF12_2430_MCBSP5_FSX,
7073 + K7_2430_MCBSP5_DX,
7074 + M1_2430_MCBSP5_DR,
7075 +
7076 + /* 2430 McSPI*/
7077 + Y18_2430_MCSPI1_CLK,
7078 + AD15_2430_MCSPI1_SIMO,
7079 + AE17_2430_MCSPI1_SOMI,
7080 + U1_2430_MCSPI1_CS0,
7081 +
7082 + /* Touchscreen GPIO */
7083 + AF19_2430_GPIO_85,
7084 +
7085 +};
7086 +
7087 +struct omap_mux_cfg {
7088 + struct pin_config *pins;
7089 + unsigned long size;
7090 + int (*cfg_reg)(const struct pin_config *cfg);
7091 +};
7092 +
7093 +#ifdef CONFIG_OMAP_MUX
7094 +/* setup pin muxing in Linux */
7095 +extern int omap1_mux_init(void);
7096 +extern int omap_mux_register(struct omap_mux_cfg *);
7097 +extern int omap_cfg_reg(unsigned long reg_cfg);
7098 +#else
7099 +/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
7100 +static inline int omap1_mux_init(void) { return 0; }
7101 +static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
7102 +#endif
7103 +
7104 +extern int omap2_mux_init(void);
7105 +
7106 +#endif
7107 --- /dev/null
7108 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/nand.h
7109 @@ -0,0 +1,24 @@
7110 +/*
7111 + * arch/arm/plat-omap/include/mach/nand.h
7112 + *
7113 + * Copyright (C) 2006 Micron Technology Inc.
7114 + *
7115 + * This program is free software; you can redistribute it and/or modify
7116 + * it under the terms of the GNU General Public License version 2 as
7117 + * published by the Free Software Foundation.
7118 + */
7119 +
7120 +#include <linux/mtd/partitions.h>
7121 +
7122 +struct omap_nand_platform_data {
7123 + unsigned int options;
7124 + int cs;
7125 + int gpio_irq;
7126 + struct mtd_partition *parts;
7127 + int nr_parts;
7128 + int (*nand_setup)(void __iomem *);
7129 + int (*dev_ready)(struct omap_nand_platform_data *);
7130 + int dma_channel;
7131 + void __iomem *gpmc_cs_baseaddr;
7132 + void __iomem *gpmc_baseaddr;
7133 +};
7134 --- /dev/null
7135 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap1510.h
7136 @@ -0,0 +1,50 @@
7137 +/* arch/arm/plat-omap/include/mach/omap1510.h
7138 + *
7139 + * Hardware definitions for TI OMAP1510 processor.
7140 + *
7141 + * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7142 + *
7143 + * This program is free software; you can redistribute it and/or modify it
7144 + * under the terms of the GNU General Public License as published by the
7145 + * Free Software Foundation; either version 2 of the License, or (at your
7146 + * option) any later version.
7147 + *
7148 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7149 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7150 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7151 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7152 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7153 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7154 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7155 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7156 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7157 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7158 + *
7159 + * You should have received a copy of the GNU General Public License along
7160 + * with this program; if not, write to the Free Software Foundation, Inc.,
7161 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7162 + */
7163 +
7164 +#ifndef __ASM_ARCH_OMAP15XX_H
7165 +#define __ASM_ARCH_OMAP15XX_H
7166 +
7167 +/*
7168 + * ----------------------------------------------------------------------------
7169 + * Base addresses
7170 + * ----------------------------------------------------------------------------
7171 + */
7172 +
7173 +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7174 +
7175 +#define OMAP1510_DSP_BASE 0xE0000000
7176 +#define OMAP1510_DSP_SIZE 0x28000
7177 +#define OMAP1510_DSP_START 0xE0000000
7178 +
7179 +#define OMAP1510_DSPREG_BASE 0xE1000000
7180 +#define OMAP1510_DSPREG_SIZE SZ_128K
7181 +#define OMAP1510_DSPREG_START 0xE1000000
7182 +
7183 +#define OMAP1510_DSP_MMU_BASE (0xfffed200)
7184 +
7185 +#endif /* __ASM_ARCH_OMAP15XX_H */
7186 +
7187 --- /dev/null
7188 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap16xx.h
7189 @@ -0,0 +1,202 @@
7190 +/* arch/arm/plat-omap/include/mach/omap16xx.h
7191 + *
7192 + * Hardware definitions for TI OMAP1610/5912/1710 processors.
7193 + *
7194 + * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7195 + *
7196 + * This program is free software; you can redistribute it and/or modify it
7197 + * under the terms of the GNU General Public License as published by the
7198 + * Free Software Foundation; either version 2 of the License, or (at your
7199 + * option) any later version.
7200 + *
7201 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7202 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7203 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7204 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7205 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7206 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7207 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7208 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7209 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7210 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7211 + *
7212 + * You should have received a copy of the GNU General Public License along
7213 + * with this program; if not, write to the Free Software Foundation, Inc.,
7214 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7215 + */
7216 +
7217 +#ifndef __ASM_ARCH_OMAP16XX_H
7218 +#define __ASM_ARCH_OMAP16XX_H
7219 +
7220 +/*
7221 + * ----------------------------------------------------------------------------
7222 + * Base addresses
7223 + * ----------------------------------------------------------------------------
7224 + */
7225 +
7226 +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7227 +
7228 +#define OMAP16XX_DSP_BASE 0xE0000000
7229 +#define OMAP16XX_DSP_SIZE 0x28000
7230 +#define OMAP16XX_DSP_START 0xE0000000
7231 +
7232 +#define OMAP16XX_DSPREG_BASE 0xE1000000
7233 +#define OMAP16XX_DSPREG_SIZE SZ_128K
7234 +#define OMAP16XX_DSPREG_START 0xE1000000
7235 +
7236 +#define OMAP16XX_SEC_BASE 0xFFFE4000
7237 +#define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000)
7238 +#define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800)
7239 +#define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000)
7240 +
7241 +/*
7242 + * ---------------------------------------------------------------------------
7243 + * Interrupts
7244 + * ---------------------------------------------------------------------------
7245 + */
7246 +#define OMAP_IH2_0_BASE (0xfffe0000)
7247 +#define OMAP_IH2_1_BASE (0xfffe0100)
7248 +#define OMAP_IH2_2_BASE (0xfffe0200)
7249 +#define OMAP_IH2_3_BASE (0xfffe0300)
7250 +
7251 +#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
7252 +#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04)
7253 +#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10)
7254 +#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
7255 +#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18)
7256 +#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c)
7257 +#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c)
7258 +
7259 +#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
7260 +#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04)
7261 +#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10)
7262 +#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
7263 +#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18)
7264 +#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c)
7265 +#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c)
7266 +
7267 +#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
7268 +#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04)
7269 +#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10)
7270 +#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
7271 +#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18)
7272 +#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c)
7273 +#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c)
7274 +
7275 +#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
7276 +#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04)
7277 +#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10)
7278 +#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
7279 +#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18)
7280 +#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c)
7281 +#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c)
7282 +
7283 +/*
7284 + * ----------------------------------------------------------------------------
7285 + * Clocks
7286 + * ----------------------------------------------------------------------------
7287 + */
7288 +#define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
7289 +
7290 +/*
7291 + * ----------------------------------------------------------------------------
7292 + * Pin configuration registers
7293 + * ----------------------------------------------------------------------------
7294 + */
7295 +#define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8)
7296 +#define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9)
7297 +#define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10)
7298 +#define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11)
7299 +#define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13)
7300 +
7301 +/*
7302 + * ----------------------------------------------------------------------------
7303 + * System control registers
7304 + * ----------------------------------------------------------------------------
7305 + */
7306 +#define OMAP1610_RESET_CONTROL 0xfffe1140
7307 +
7308 +/*
7309 + * ---------------------------------------------------------------------------
7310 + * TIPB bus interface
7311 + * ---------------------------------------------------------------------------
7312 + */
7313 +#define TIPB_SWITCH_BASE (0xfffbc800)
7314 +#define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160)
7315 +
7316 +/* UART3 Registers Mapping through MPU bus */
7317 +#define UART3_RHR (OMAP_UART3_BASE + 0)
7318 +#define UART3_THR (OMAP_UART3_BASE + 0)
7319 +#define UART3_DLL (OMAP_UART3_BASE + 0)
7320 +#define UART3_IER (OMAP_UART3_BASE + 4)
7321 +#define UART3_DLH (OMAP_UART3_BASE + 4)
7322 +#define UART3_IIR (OMAP_UART3_BASE + 8)
7323 +#define UART3_FCR (OMAP_UART3_BASE + 8)
7324 +#define UART3_EFR (OMAP_UART3_BASE + 8)
7325 +#define UART3_LCR (OMAP_UART3_BASE + 0x0C)
7326 +#define UART3_MCR (OMAP_UART3_BASE + 0x10)
7327 +#define UART3_XON1_ADDR1 (OMAP_UART3_BASE + 0x10)
7328 +#define UART3_XON2_ADDR2 (OMAP_UART3_BASE + 0x14)
7329 +#define UART3_LSR (OMAP_UART3_BASE + 0x14)
7330 +#define UART3_TCR (OMAP_UART3_BASE + 0x18)
7331 +#define UART3_MSR (OMAP_UART3_BASE + 0x18)
7332 +#define UART3_XOFF1 (OMAP_UART3_BASE + 0x18)
7333 +#define UART3_XOFF2 (OMAP_UART3_BASE + 0x1C)
7334 +#define UART3_SPR (OMAP_UART3_BASE + 0x1C)
7335 +#define UART3_TLR (OMAP_UART3_BASE + 0x1C)
7336 +#define UART3_MDR1 (OMAP_UART3_BASE + 0x20)
7337 +#define UART3_MDR2 (OMAP_UART3_BASE + 0x24)
7338 +#define UART3_SFLSR (OMAP_UART3_BASE + 0x28)
7339 +#define UART3_TXFLL (OMAP_UART3_BASE + 0x28)
7340 +#define UART3_RESUME (OMAP_UART3_BASE + 0x2C)
7341 +#define UART3_TXFLH (OMAP_UART3_BASE + 0x2C)
7342 +#define UART3_SFREGL (OMAP_UART3_BASE + 0x30)
7343 +#define UART3_RXFLL (OMAP_UART3_BASE + 0x30)
7344 +#define UART3_SFREGH (OMAP_UART3_BASE + 0x34)
7345 +#define UART3_RXFLH (OMAP_UART3_BASE + 0x34)
7346 +#define UART3_BLR (OMAP_UART3_BASE + 0x38)
7347 +#define UART3_ACREG (OMAP_UART3_BASE + 0x3C)
7348 +#define UART3_DIV16 (OMAP_UART3_BASE + 0x3C)
7349 +#define UART3_SCR (OMAP_UART3_BASE + 0x40)
7350 +#define UART3_SSR (OMAP_UART3_BASE + 0x44)
7351 +#define UART3_EBLR (OMAP_UART3_BASE + 0x48)
7352 +#define UART3_OSC_12M_SEL (OMAP_UART3_BASE + 0x4C)
7353 +#define UART3_MVR (OMAP_UART3_BASE + 0x50)
7354 +
7355 +/*
7356 + * ---------------------------------------------------------------------------
7357 + * Watchdog timer
7358 + * ---------------------------------------------------------------------------
7359 + */
7360 +
7361 +/* 32-bit Watchdog timer in OMAP 16XX */
7362 +#define OMAP_16XX_WATCHDOG_BASE (0xfffeb000)
7363 +#define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00)
7364 +#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
7365 +#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
7366 +#define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24)
7367 +#define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28)
7368 +#define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c)
7369 +#define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30)
7370 +#define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34)
7371 +#define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48)
7372 +
7373 +#define WCLR_PRE_SHIFT 5
7374 +#define WCLR_PTV_SHIFT 2
7375 +
7376 +#define WWPS_W_PEND_WSPR (1 << 4)
7377 +#define WWPS_W_PEND_WTGR (1 << 3)
7378 +#define WWPS_W_PEND_WLDR (1 << 2)
7379 +#define WWPS_W_PEND_WCRR (1 << 1)
7380 +#define WWPS_W_PEND_WCLR (1 << 0)
7381 +
7382 +#define WSPR_ENABLE_0 (0x0000bbbb)
7383 +#define WSPR_ENABLE_1 (0x00004444)
7384 +#define WSPR_DISABLE_0 (0x0000aaaa)
7385 +#define WSPR_DISABLE_1 (0x00005555)
7386 +
7387 +#define OMAP16XX_DSP_MMU_BASE (0xfffed200)
7388 +#define OMAP16XX_MAILBOX_BASE (0xfffcf000)
7389 +
7390 +#endif /* __ASM_ARCH_OMAP16XX_H */
7391 +
7392 --- /dev/null
7393 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap24xx.h
7394 @@ -0,0 +1,89 @@
7395 +/*
7396 + * arch/arm/plat-omap/include/mach/omap24xx.h
7397 + *
7398 + * This file contains the processor specific definitions
7399 + * of the TI OMAP24XX.
7400 + *
7401 + * Copyright (C) 2007 Texas Instruments.
7402 + * Copyright (C) 2007 Nokia Corporation.
7403 + *
7404 + * This program is free software; you can redistribute it and/or modify
7405 + * it under the terms of the GNU General Public License as published by
7406 + * the Free Software Foundation; either version 2 of the License, or
7407 + * (at your option) any later version.
7408 + *
7409 + * This program is distributed in the hope that it will be useful,
7410 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7411 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7412 + * GNU General Public License for more details.
7413 + *
7414 + * You should have received a copy of the GNU General Public License
7415 + * along with this program; if not, write to the Free Software
7416 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7417 + *
7418 + */
7419 +
7420 +#ifndef __ASM_ARCH_OMAP24XX_H
7421 +#define __ASM_ARCH_OMAP24XX_H
7422 +
7423 +/*
7424 + * Please place only base defines here and put the rest in device
7425 + * specific headers. Note also that some of these defines are needed
7426 + * for omap1 to compile without adding ifdefs.
7427 + */
7428 +
7429 +#define L4_24XX_BASE 0x48000000
7430 +#define L4_WK_243X_BASE 0x49000000
7431 +#define L3_24XX_BASE 0x68000000
7432 +
7433 +/* interrupt controller */
7434 +#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
7435 +#define OMAP24XX_IVA_INTC_BASE 0x40000000
7436 +
7437 +#define OMAP2420_CTRL_BASE L4_24XX_BASE
7438 +#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
7439 +#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
7440 +#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
7441 +#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
7442 +#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
7443 +#define OMAP2420_SMS_BASE 0x68008000
7444 +#define OMAP2420_GPMC_BASE 0x6800a000
7445 +
7446 +#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
7447 +#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
7448 +#define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000)
7449 +#define OMAP2430_PRM_BASE OMAP2430_CM_BASE
7450 +
7451 +#define OMAP243X_SMS_BASE 0x6C000000
7452 +#define OMAP243X_SDRC_BASE 0x6D000000
7453 +#define OMAP243X_GPMC_BASE 0x6E000000
7454 +#define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000)
7455 +#define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE
7456 +#define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000)
7457 +
7458 +/* DSP SS */
7459 +#define OMAP2420_DSP_BASE 0x58000000
7460 +#define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0)
7461 +#define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000)
7462 +#define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000)
7463 +
7464 +#define OMAP243X_DSP_BASE 0x5C000000
7465 +#define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0)
7466 +#define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000)
7467 +
7468 +/* Mailbox */
7469 +#define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000)
7470 +
7471 +/* Camera */
7472 +#define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000)
7473 +
7474 +/* Security */
7475 +#define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000)
7476 +#define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000)
7477 +#define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000)
7478 +#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000)
7479 +#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000)
7480 +#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000)
7481 +
7482 +#endif /* __ASM_ARCH_OMAP24XX_H */
7483 +
7484 --- /dev/null
7485 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap34xx.h
7486 @@ -0,0 +1,86 @@
7487 +/*
7488 + * arch/arm/plat-omap/include/mach/omap34xx.h
7489 + *
7490 + * This file contains the processor specific definitions of the TI OMAP34XX.
7491 + *
7492 + * Copyright (C) 2007 Texas Instruments.
7493 + * Copyright (C) 2007 Nokia Corporation.
7494 + *
7495 + * This program is free software; you can redistribute it and/or modify
7496 + * it under the terms of the GNU General Public License as published by
7497 + * the Free Software Foundation; either version 2 of the License, or
7498 + * (at your option) any later version.
7499 + *
7500 + * This program is distributed in the hope that it will be useful,
7501 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7502 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7503 + * GNU General Public License for more details.
7504 + *
7505 + * You should have received a copy of the GNU General Public License
7506 + * along with this program; if not, write to the Free Software
7507 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7508 + */
7509 +
7510 +#ifndef __ASM_ARCH_OMAP34XX_H
7511 +#define __ASM_ARCH_OMAP34XX_H
7512 +
7513 +/*
7514 + * Please place only base defines here and put the rest in device
7515 + * specific headers.
7516 + */
7517 +
7518 +#define L4_34XX_BASE 0x48000000
7519 +#define L4_WK_34XX_BASE 0x48300000
7520 +#define L4_PER_34XX_BASE 0x49000000
7521 +#define L4_EMU_34XX_BASE 0x54000000
7522 +#define L3_34XX_BASE 0x68000000
7523 +
7524 +#define OMAP3430_32KSYNCT_BASE 0x48320000
7525 +#define OMAP3430_CM_BASE 0x48004800
7526 +#define OMAP3430_PRM_BASE 0x48306800
7527 +#define OMAP343X_SMS_BASE 0x6C000000
7528 +#define OMAP343X_SDRC_BASE 0x6D000000
7529 +#define OMAP34XX_GPMC_BASE 0x6E000000
7530 +#define OMAP343X_SCM_BASE 0x48002000
7531 +#define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE
7532 +
7533 +#define OMAP34XX_IC_BASE 0x48200000
7534 +
7535 +#define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000)
7536 +#define OMAP3430_ISP_CBUFF_BASE (OMAP3430_ISP_BASE + 0x0100)
7537 +#define OMAP3430_ISP_CCP2_BASE (OMAP3430_ISP_BASE + 0x0400)
7538 +#define OMAP3430_ISP_CCDC_BASE (OMAP3430_ISP_BASE + 0x0600)
7539 +#define OMAP3430_ISP_HIST_BASE (OMAP3430_ISP_BASE + 0x0A00)
7540 +#define OMAP3430_ISP_H3A_BASE (OMAP3430_ISP_BASE + 0x0C00)
7541 +#define OMAP3430_ISP_PREV_BASE (OMAP3430_ISP_BASE + 0x0E00)
7542 +#define OMAP3430_ISP_RESZ_BASE (OMAP3430_ISP_BASE + 0x1000)
7543 +#define OMAP3430_ISP_SBL_BASE (OMAP3430_ISP_BASE + 0x1200)
7544 +#define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400)
7545 +#define OMAP3430_ISP_CSI2A_BASE (OMAP3430_ISP_BASE + 0x1800)
7546 +#define OMAP3430_ISP_CSI2PHY_BASE (OMAP3430_ISP_BASE + 0x1970)
7547 +
7548 +#define OMAP3430_ISP_END (OMAP3430_ISP_BASE + 0x06F)
7549 +#define OMAP3430_ISP_CBUFF_END (OMAP3430_ISP_CBUFF_BASE + 0x077)
7550 +#define OMAP3430_ISP_CCP2_END (OMAP3430_ISP_CCP2_BASE + 0x1EF)
7551 +#define OMAP3430_ISP_CCDC_END (OMAP3430_ISP_CCDC_BASE + 0x0A7)
7552 +#define OMAP3430_ISP_HIST_END (OMAP3430_ISP_HIST_BASE + 0x047)
7553 +#define OMAP3430_ISP_H3A_END (OMAP3430_ISP_H3A_BASE + 0x05F)
7554 +#define OMAP3430_ISP_PREV_END (OMAP3430_ISP_PREV_BASE + 0x09F)
7555 +#define OMAP3430_ISP_RESZ_END (OMAP3430_ISP_RESZ_BASE + 0x0AB)
7556 +#define OMAP3430_ISP_SBL_END (OMAP3430_ISP_SBL_BASE + 0x0FB)
7557 +#define OMAP3430_ISP_MMU_END (OMAP3430_ISP_MMU_BASE + 0x06F)
7558 +#define OMAP3430_ISP_CSI2A_END (OMAP3430_ISP_CSI2A_BASE + 0x16F)
7559 +#define OMAP3430_ISP_CSI2PHY_END (OMAP3430_ISP_CSI2PHY_BASE + 0x007)
7560 +
7561 +#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
7562 +#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
7563 +#define OMAP34XX_UHH_CONFIG_BASE (L4_34XX_BASE + 0x64000)
7564 +#define OMAP34XX_OHCI_BASE (L4_34XX_BASE + 0x64400)
7565 +#define OMAP34XX_EHCI_BASE (L4_34XX_BASE + 0x64800)
7566 +#define OMAP34XX_SR1_BASE 0x480C9000
7567 +#define OMAP34XX_SR2_BASE 0x480CB000
7568 +
7569 +#define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000)
7570 +
7571 +#endif /* __ASM_ARCH_OMAP34XX_H */
7572 +
7573 --- /dev/null
7574 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap44xx.h
7575 @@ -0,0 +1,48 @@
7576 +/*:
7577 + * Address mappings and base address for OMAP4 interconnects
7578 + * and peripherals.
7579 + *
7580 + * Copyright (C) 2009 Texas Instruments
7581 + *
7582 + * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
7583 + *
7584 + * This program is free software; you can redistribute it and/or modify
7585 + * it under the terms of the GNU General Public License version 2 as
7586 + * published by the Free Software Foundation.
7587 + */
7588 +#ifndef __ASM_ARCH_OMAP44XX_H
7589 +#define __ASM_ARCH_OMAP44XX_H
7590 +
7591 +/*
7592 + * Please place only base defines here and put the rest in device
7593 + * specific headers.
7594 + */
7595 +#define L4_44XX_BASE 0x4a000000
7596 +#define L4_WK_44XX_BASE 0x4a300000
7597 +#define L4_PER_44XX_BASE 0x48000000
7598 +#define L4_EMU_44XX_BASE 0x54000000
7599 +#define L3_44XX_BASE 0x44000000
7600 +#define OMAP44XX_EMIF1_BASE 0x4c000000
7601 +#define OMAP44XX_EMIF2_BASE 0x4d000000
7602 +#define OMAP44XX_DMM_BASE 0x4e000000
7603 +#define OMAP4430_32KSYNCT_BASE 0x4a304000
7604 +#define OMAP4430_CM1_BASE 0x4a004000
7605 +#define OMAP4430_CM_BASE OMAP4430_CM1_BASE
7606 +#define OMAP4430_CM2_BASE 0x4a008000
7607 +#define OMAP4430_PRM_BASE 0x4a306000
7608 +#define OMAP44XX_GPMC_BASE 0x50000000
7609 +#define OMAP443X_SCM_BASE 0x4a002000
7610 +#define OMAP443X_CTRL_BASE OMAP443X_SCM_BASE
7611 +#define OMAP44XX_IC_BASE 0x48200000
7612 +#define OMAP44XX_IVA_INTC_BASE 0x40000000
7613 +#define IRQ_SIR_IRQ 0x0040
7614 +#define OMAP44XX_GIC_DIST_BASE 0x48241000
7615 +#define OMAP44XX_GIC_CPU_BASE 0x48240100
7616 +#define OMAP44XX_SCU_BASE 0x48240000
7617 +#define OMAP44XX_LOCAL_TWD_BASE 0x48240600
7618 +#define OMAP44XX_WKUPGEN_BASE 0x48281000
7619 +
7620 +#define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000)
7621 +
7622 +#endif /* __ASM_ARCH_OMAP44XX_H */
7623 +
7624 --- /dev/null
7625 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap730.h
7626 @@ -0,0 +1,102 @@
7627 +/* arch/arm/plat-omap/include/mach/omap730.h
7628 + *
7629 + * Hardware definitions for TI OMAP730 processor.
7630 + *
7631 + * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7632 + *
7633 + * This program is free software; you can redistribute it and/or modify it
7634 + * under the terms of the GNU General Public License as published by the
7635 + * Free Software Foundation; either version 2 of the License, or (at your
7636 + * option) any later version.
7637 + *
7638 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7639 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7640 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7641 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7642 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7643 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7644 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7645 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7646 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7647 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7648 + *
7649 + * You should have received a copy of the GNU General Public License along
7650 + * with this program; if not, write to the Free Software Foundation, Inc.,
7651 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7652 + */
7653 +
7654 +#ifndef __ASM_ARCH_OMAP730_H
7655 +#define __ASM_ARCH_OMAP730_H
7656 +
7657 +/*
7658 + * ----------------------------------------------------------------------------
7659 + * Base addresses
7660 + * ----------------------------------------------------------------------------
7661 + */
7662 +
7663 +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7664 +
7665 +#define OMAP730_DSP_BASE 0xE0000000
7666 +#define OMAP730_DSP_SIZE 0x50000
7667 +#define OMAP730_DSP_START 0xE0000000
7668 +
7669 +#define OMAP730_DSPREG_BASE 0xE1000000
7670 +#define OMAP730_DSPREG_SIZE SZ_128K
7671 +#define OMAP730_DSPREG_START 0xE1000000
7672 +
7673 +/*
7674 + * ----------------------------------------------------------------------------
7675 + * OMAP730 specific configuration registers
7676 + * ----------------------------------------------------------------------------
7677 + */
7678 +#define OMAP730_CONFIG_BASE 0xfffe1000
7679 +#define OMAP730_IO_CONF_0 0xfffe1070
7680 +#define OMAP730_IO_CONF_1 0xfffe1074
7681 +#define OMAP730_IO_CONF_2 0xfffe1078
7682 +#define OMAP730_IO_CONF_3 0xfffe107c
7683 +#define OMAP730_IO_CONF_4 0xfffe1080
7684 +#define OMAP730_IO_CONF_5 0xfffe1084
7685 +#define OMAP730_IO_CONF_6 0xfffe1088
7686 +#define OMAP730_IO_CONF_7 0xfffe108c
7687 +#define OMAP730_IO_CONF_8 0xfffe1090
7688 +#define OMAP730_IO_CONF_9 0xfffe1094
7689 +#define OMAP730_IO_CONF_10 0xfffe1098
7690 +#define OMAP730_IO_CONF_11 0xfffe109c
7691 +#define OMAP730_IO_CONF_12 0xfffe10a0
7692 +#define OMAP730_IO_CONF_13 0xfffe10a4
7693 +
7694 +#define OMAP730_MODE_1 0xfffe1010
7695 +#define OMAP730_MODE_2 0xfffe1014
7696 +
7697 +/* CSMI specials: in terms of base + offset */
7698 +#define OMAP730_MODE2_OFFSET 0x14
7699 +
7700 +/*
7701 + * ----------------------------------------------------------------------------
7702 + * OMAP730 traffic controller configuration registers
7703 + * ----------------------------------------------------------------------------
7704 + */
7705 +#define OMAP730_FLASH_CFG_0 0xfffecc10
7706 +#define OMAP730_FLASH_ACFG_0 0xfffecc50
7707 +#define OMAP730_FLASH_CFG_1 0xfffecc14
7708 +#define OMAP730_FLASH_ACFG_1 0xfffecc54
7709 +
7710 +/*
7711 + * ----------------------------------------------------------------------------
7712 + * OMAP730 DSP control registers
7713 + * ----------------------------------------------------------------------------
7714 + */
7715 +#define OMAP730_ICR_BASE 0xfffbb800
7716 +#define OMAP730_DSP_M_CTL 0xfffbb804
7717 +#define OMAP730_DSP_MMU_BASE 0xfffed200
7718 +
7719 +/*
7720 + * ----------------------------------------------------------------------------
7721 + * OMAP730 PCC_UPLD configuration registers
7722 + * ----------------------------------------------------------------------------
7723 + */
7724 +#define OMAP730_PCC_UPLD_CTRL_BASE (0xfffe0900)
7725 +#define OMAP730_PCC_UPLD_CTRL (OMAP730_PCC_UPLD_CTRL_BASE + 0x00)
7726 +
7727 +#endif /* __ASM_ARCH_OMAP730_H */
7728 +
7729 --- /dev/null
7730 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap7xx.h
7731 @@ -0,0 +1,104 @@
7732 +/* arch/arm/plat-omap/include/mach/omap7xx.h
7733 + *
7734 + * Hardware definitions for TI OMAP7XX processor.
7735 + *
7736 + * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7737 + * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net>
7738 + * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com>
7739 + *
7740 + * This program is free software; you can redistribute it and/or modify it
7741 + * under the terms of the GNU General Public License as published by the
7742 + * Free Software Foundation; either version 2 of the License, or (at your
7743 + * option) any later version.
7744 + *
7745 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7746 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7747 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7748 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7749 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7750 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7751 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7752 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7753 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7754 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7755 + *
7756 + * You should have received a copy of the GNU General Public License along
7757 + * with this program; if not, write to the Free Software Foundation, Inc.,
7758 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7759 + */
7760 +
7761 +#ifndef __ASM_ARCH_OMAP7XX_H
7762 +#define __ASM_ARCH_OMAP7XX_H
7763 +
7764 +/*
7765 + * ----------------------------------------------------------------------------
7766 + * Base addresses
7767 + * ----------------------------------------------------------------------------
7768 + */
7769 +
7770 +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7771 +
7772 +#define OMAP7XX_DSP_BASE 0xE0000000
7773 +#define OMAP7XX_DSP_SIZE 0x50000
7774 +#define OMAP7XX_DSP_START 0xE0000000
7775 +
7776 +#define OMAP7XX_DSPREG_BASE 0xE1000000
7777 +#define OMAP7XX_DSPREG_SIZE SZ_128K
7778 +#define OMAP7XX_DSPREG_START 0xE1000000
7779 +
7780 +/*
7781 + * ----------------------------------------------------------------------------
7782 + * OMAP7XX specific configuration registers
7783 + * ----------------------------------------------------------------------------
7784 + */
7785 +#define OMAP7XX_CONFIG_BASE 0xfffe1000
7786 +#define OMAP7XX_IO_CONF_0 0xfffe1070
7787 +#define OMAP7XX_IO_CONF_1 0xfffe1074
7788 +#define OMAP7XX_IO_CONF_2 0xfffe1078
7789 +#define OMAP7XX_IO_CONF_3 0xfffe107c
7790 +#define OMAP7XX_IO_CONF_4 0xfffe1080
7791 +#define OMAP7XX_IO_CONF_5 0xfffe1084
7792 +#define OMAP7XX_IO_CONF_6 0xfffe1088
7793 +#define OMAP7XX_IO_CONF_7 0xfffe108c
7794 +#define OMAP7XX_IO_CONF_8 0xfffe1090
7795 +#define OMAP7XX_IO_CONF_9 0xfffe1094
7796 +#define OMAP7XX_IO_CONF_10 0xfffe1098
7797 +#define OMAP7XX_IO_CONF_11 0xfffe109c
7798 +#define OMAP7XX_IO_CONF_12 0xfffe10a0
7799 +#define OMAP7XX_IO_CONF_13 0xfffe10a4
7800 +
7801 +#define OMAP7XX_MODE_1 0xfffe1010
7802 +#define OMAP7XX_MODE_2 0xfffe1014
7803 +
7804 +/* CSMI specials: in terms of base + offset */
7805 +#define OMAP7XX_MODE2_OFFSET 0x14
7806 +
7807 +/*
7808 + * ----------------------------------------------------------------------------
7809 + * OMAP7XX traffic controller configuration registers
7810 + * ----------------------------------------------------------------------------
7811 + */
7812 +#define OMAP7XX_FLASH_CFG_0 0xfffecc10
7813 +#define OMAP7XX_FLASH_ACFG_0 0xfffecc50
7814 +#define OMAP7XX_FLASH_CFG_1 0xfffecc14
7815 +#define OMAP7XX_FLASH_ACFG_1 0xfffecc54
7816 +
7817 +/*
7818 + * ----------------------------------------------------------------------------
7819 + * OMAP7XX DSP control registers
7820 + * ----------------------------------------------------------------------------
7821 + */
7822 +#define OMAP7XX_ICR_BASE 0xfffbb800
7823 +#define OMAP7XX_DSP_M_CTL 0xfffbb804
7824 +#define OMAP7XX_DSP_MMU_BASE 0xfffed200
7825 +
7826 +/*
7827 + * ----------------------------------------------------------------------------
7828 + * OMAP7XX PCC_UPLD configuration registers
7829 + * ----------------------------------------------------------------------------
7830 + */
7831 +#define OMAP7XX_PCC_UPLD_CTRL_BASE (0xfffe0900)
7832 +#define OMAP7XX_PCC_UPLD_CTRL (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00)
7833 +
7834 +#endif /* __ASM_ARCH_OMAP7XX_H */
7835 +
7836 --- /dev/null
7837 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap850.h
7838 @@ -0,0 +1,102 @@
7839 +/* arch/arm/plat-omap/include/mach/omap850.h
7840 + *
7841 + * Hardware definitions for TI OMAP850 processor.
7842 + *
7843 + * Derived from omap730.h by Zebediah C. McClure <zmc@lurian.net>
7844 + *
7845 + * This program is free software; you can redistribute it and/or modify it
7846 + * under the terms of the GNU General Public License as published by the
7847 + * Free Software Foundation; either version 2 of the License, or (at your
7848 + * option) any later version.
7849 + *
7850 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7851 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7852 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7853 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7854 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7855 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7856 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7857 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7858 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7859 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7860 + *
7861 + * You should have received a copy of the GNU General Public License along
7862 + * with this program; if not, write to the Free Software Foundation, Inc.,
7863 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7864 + */
7865 +
7866 +#ifndef __ASM_ARCH_OMAP850_H
7867 +#define __ASM_ARCH_OMAP850_H
7868 +
7869 +/*
7870 + * ----------------------------------------------------------------------------
7871 + * Base addresses
7872 + * ----------------------------------------------------------------------------
7873 + */
7874 +
7875 +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7876 +
7877 +#define OMAP850_DSP_BASE 0xE0000000
7878 +#define OMAP850_DSP_SIZE 0x50000
7879 +#define OMAP850_DSP_START 0xE0000000
7880 +
7881 +#define OMAP850_DSPREG_BASE 0xE1000000
7882 +#define OMAP850_DSPREG_SIZE SZ_128K
7883 +#define OMAP850_DSPREG_START 0xE1000000
7884 +
7885 +/*
7886 + * ----------------------------------------------------------------------------
7887 + * OMAP850 specific configuration registers
7888 + * ----------------------------------------------------------------------------
7889 + */
7890 +#define OMAP850_CONFIG_BASE 0xfffe1000
7891 +#define OMAP850_IO_CONF_0 0xfffe1070
7892 +#define OMAP850_IO_CONF_1 0xfffe1074
7893 +#define OMAP850_IO_CONF_2 0xfffe1078
7894 +#define OMAP850_IO_CONF_3 0xfffe107c
7895 +#define OMAP850_IO_CONF_4 0xfffe1080
7896 +#define OMAP850_IO_CONF_5 0xfffe1084
7897 +#define OMAP850_IO_CONF_6 0xfffe1088
7898 +#define OMAP850_IO_CONF_7 0xfffe108c
7899 +#define OMAP850_IO_CONF_8 0xfffe1090
7900 +#define OMAP850_IO_CONF_9 0xfffe1094
7901 +#define OMAP850_IO_CONF_10 0xfffe1098
7902 +#define OMAP850_IO_CONF_11 0xfffe109c
7903 +#define OMAP850_IO_CONF_12 0xfffe10a0
7904 +#define OMAP850_IO_CONF_13 0xfffe10a4
7905 +
7906 +#define OMAP850_MODE_1 0xfffe1010
7907 +#define OMAP850_MODE_2 0xfffe1014
7908 +
7909 +/* CSMI specials: in terms of base + offset */
7910 +#define OMAP850_MODE2_OFFSET 0x14
7911 +
7912 +/*
7913 + * ----------------------------------------------------------------------------
7914 + * OMAP850 traffic controller configuration registers
7915 + * ----------------------------------------------------------------------------
7916 + */
7917 +#define OMAP850_FLASH_CFG_0 0xfffecc10
7918 +#define OMAP850_FLASH_ACFG_0 0xfffecc50
7919 +#define OMAP850_FLASH_CFG_1 0xfffecc14
7920 +#define OMAP850_FLASH_ACFG_1 0xfffecc54
7921 +
7922 +/*
7923 + * ----------------------------------------------------------------------------
7924 + * OMAP850 DSP control registers
7925 + * ----------------------------------------------------------------------------
7926 + */
7927 +#define OMAP850_ICR_BASE 0xfffbb800
7928 +#define OMAP850_DSP_M_CTL 0xfffbb804
7929 +#define OMAP850_DSP_MMU_BASE 0xfffed200
7930 +
7931 +/*
7932 + * ----------------------------------------------------------------------------
7933 + * OMAP850 PCC_UPLD configuration registers
7934 + * ----------------------------------------------------------------------------
7935 + */
7936 +#define OMAP850_PCC_UPLD_CTRL_BASE (0xfffe0900)
7937 +#define OMAP850_PCC_UPLD_CTRL (OMAP850_PCC_UPLD_CTRL_BASE + 0x00)
7938 +
7939 +#endif /* __ASM_ARCH_OMAP850_H */
7940 +
7941 --- /dev/null
7942 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap-alsa.h
7943 @@ -0,0 +1,123 @@
7944 +/*
7945 + * arch/arm/plat-omap/include/mach/omap-alsa.h
7946 + *
7947 + * Alsa Driver for AIC23 and TSC2101 codecs on OMAP platform boards.
7948 + *
7949 + * Copyright (C) 2006 Mika Laitio <lamikr@cc.jyu.fi>
7950 + *
7951 + * Copyright (C) 2005 Instituto Nokia de Tecnologia - INdT - Manaus Brazil
7952 + * Written by Daniel Petrini, David Cohen, Anderson Briglia
7953 + * {daniel.petrini, david.cohen, anderson.briglia}@indt.org.br
7954 + *
7955 + * This program is free software; you can redistribute it and/or modify it
7956 + * under the terms of the GNU General Public License as published by the
7957 + * Free Software Foundation; either version 2 of the License, or (at your
7958 + * option) any later version.
7959 + *
7960 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7961 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7962 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7963 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7964 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7965 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7966 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7967 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7968 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7969 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7970 + *
7971 + * You should have received a copy of the GNU General Public License along
7972 + * with this program; if not, write to the Free Software Foundation, Inc.,
7973 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7974 + *
7975 + * History
7976 + * -------
7977 + *
7978 + * 2005/07/25 INdT-10LE Kernel Team - Alsa driver for omap osk,
7979 + * original version based in sa1100 driver
7980 + * and omap oss driver.
7981 + */
7982 +
7983 +#ifndef __OMAP_ALSA_H
7984 +#define __OMAP_ALSA_H
7985 +
7986 +#include <plat/dma.h>
7987 +#include <sound/core.h>
7988 +#include <sound/pcm.h>
7989 +#include <plat/mcbsp.h>
7990 +#include <linux/platform_device.h>
7991 +
7992 +#define DMA_BUF_SIZE (1024 * 8)
7993 +
7994 +/*
7995 + * Buffer management for alsa and dma
7996 + */
7997 +struct audio_stream {
7998 + char *id; /* identification string */
7999 + int stream_id; /* numeric identification */
8000 + int dma_dev; /* dma number of that device */
8001 + int *lch; /* Chain of channels this stream is linked to */
8002 + char started; /* to store if the chain was started or not */
8003 + int dma_q_head; /* DMA Channel Q Head */
8004 + int dma_q_tail; /* DMA Channel Q Tail */
8005 + char dma_q_count; /* DMA Channel Q Count */
8006 + int active:1; /* we are using this stream for transfer now */
8007 + int period; /* current transfer period */
8008 + int periods; /* current count of periods registerd in the DMA engine */
8009 + spinlock_t dma_lock; /* for locking in DMA operations */
8010 + struct snd_pcm_substream *stream; /* the pcm stream */
8011 + unsigned linked:1; /* dma channels linked */
8012 + int offset; /* store start position of the last period in the alsa buffer */
8013 + int (*hw_start)(void); /* interface to start HW interface, e.g. McBSP */
8014 + int (*hw_stop)(void); /* interface to stop HW interface, e.g. McBSP */
8015 +};
8016 +
8017 +/*
8018 + * Alsa card structure for aic23
8019 + */
8020 +struct snd_card_omap_codec {
8021 + struct snd_card *card;
8022 + struct snd_pcm *pcm;
8023 + long samplerate;
8024 + struct audio_stream s[2]; /* playback & capture */
8025 +};
8026 +
8027 +/* Codec specific information and function pointers.
8028 + * Codec (omap-alsa-aic23.c and omap-alsa-tsc2101.c)
8029 + * are responsible for defining the function pointers.
8030 + */
8031 +struct omap_alsa_codec_config {
8032 + char *name;
8033 + struct omap_mcbsp_reg_cfg *mcbsp_regs_alsa;
8034 + struct snd_pcm_hw_constraint_list *hw_constraints_rates;
8035 + struct snd_pcm_hardware *snd_omap_alsa_playback;
8036 + struct snd_pcm_hardware *snd_omap_alsa_capture;
8037 + void (*codec_configure_dev)(void);
8038 + void (*codec_set_samplerate)(long);
8039 + void (*codec_clock_setup)(void);
8040 + int (*codec_clock_on)(void);
8041 + int (*codec_clock_off)(void);
8042 + int (*get_default_samplerate)(void);
8043 +};
8044 +
8045 +/*********** Mixer function prototypes *************************/
8046 +int snd_omap_mixer(struct snd_card_omap_codec *);
8047 +void snd_omap_init_mixer(void);
8048 +
8049 +#ifdef CONFIG_PM
8050 +void snd_omap_suspend_mixer(void);
8051 +void snd_omap_resume_mixer(void);
8052 +#endif
8053 +
8054 +int snd_omap_alsa_post_probe(struct platform_device *pdev, struct omap_alsa_codec_config *config);
8055 +int snd_omap_alsa_remove(struct platform_device *pdev);
8056 +#ifdef CONFIG_PM
8057 +int snd_omap_alsa_suspend(struct platform_device *pdev, pm_message_t state);
8058 +int snd_omap_alsa_resume(struct platform_device *pdev);
8059 +#else
8060 +#define snd_omap_alsa_suspend NULL
8061 +#define snd_omap_alsa_resume NULL
8062 +#endif
8063 +
8064 +void callback_omap_alsa_sound_dma(void *);
8065 +
8066 +#endif
8067 --- /dev/null
8068 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap_device.h
8069 @@ -0,0 +1,143 @@
8070 +/*
8071 + * omap_device headers
8072 + *
8073 + * Copyright (C) 2009 Nokia Corporation
8074 + * Paul Walmsley
8075 + *
8076 + * Developed in collaboration with (alphabetical order): Benoit
8077 + * Cousson, Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram
8078 + * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard
8079 + * Woodruff
8080 + *
8081 + * This program is free software; you can redistribute it and/or modify
8082 + * it under the terms of the GNU General Public License version 2 as
8083 + * published by the Free Software Foundation.
8084 + *
8085 + * Eventually this type of functionality should either be
8086 + * a) implemented via arch-specific pointers in platform_device
8087 + * or
8088 + * b) implemented as a proper omap_bus/omap_device in Linux, no more
8089 + * platform_device
8090 + *
8091 + * omap_device differs from omap_hwmod in that it includes external
8092 + * (e.g., board- and system-level) integration details. omap_hwmod
8093 + * stores hardware data that is invariant for a given OMAP chip.
8094 + *
8095 + * To do:
8096 + * - GPIO integration
8097 + * - regulator integration
8098 + *
8099 + */
8100 +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
8101 +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
8102 +
8103 +#include <linux/kernel.h>
8104 +#include <linux/platform_device.h>
8105 +
8106 +#include <plat/omap_hwmod.h>
8107 +
8108 +/* omap_device._state values */
8109 +#define OMAP_DEVICE_STATE_UNKNOWN 0
8110 +#define OMAP_DEVICE_STATE_ENABLED 1
8111 +#define OMAP_DEVICE_STATE_IDLE 2
8112 +#define OMAP_DEVICE_STATE_SHUTDOWN 3
8113 +
8114 +/**
8115 + * struct omap_device - omap_device wrapper for platform_devices
8116 + * @pdev: platform_device
8117 + * @hwmods: (one .. many per omap_device)
8118 + * @hwmods_cnt: ARRAY_SIZE() of @hwmods
8119 + * @pm_lats: ptr to an omap_device_pm_latency table
8120 + * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats
8121 + * @pm_lat_level: array index of the last odpl entry executed - -1 if never
8122 + * @dev_wakeup_lat: dev wakeup latency in nanoseconds
8123 + * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
8124 + * @_state: one of OMAP_DEVICE_STATE_* (see above)
8125 + * @flags: device flags
8126 + *
8127 + * Integrates omap_hwmod data into Linux platform_device.
8128 + *
8129 + * Field names beginning with underscores are for the internal use of
8130 + * the omap_device code.
8131 + *
8132 + */
8133 +struct omap_device {
8134 + struct platform_device pdev;
8135 + struct omap_hwmod **hwmods;
8136 + struct omap_device_pm_latency *pm_lats;
8137 + u32 dev_wakeup_lat;
8138 + u32 _dev_wakeup_lat_limit;
8139 + u8 pm_lats_cnt;
8140 + s8 pm_lat_level;
8141 + u8 hwmods_cnt;
8142 + u8 _state;
8143 +};
8144 +
8145 +/* Device driver interface (call via platform_data fn ptrs) */
8146 +
8147 +int omap_device_enable(struct platform_device *pdev);
8148 +int omap_device_idle(struct platform_device *pdev);
8149 +int omap_device_shutdown(struct platform_device *pdev);
8150 +
8151 +/* Core code interface */
8152 +
8153 +int omap_device_count_resources(struct omap_device *od);
8154 +int omap_device_fill_resources(struct omap_device *od, struct resource *res);
8155 +
8156 +struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
8157 + struct omap_hwmod *oh, void *pdata,
8158 + int pdata_len,
8159 + struct omap_device_pm_latency *pm_lats,
8160 + int pm_lats_cnt);
8161 +
8162 +struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
8163 + struct omap_hwmod **oh, int oh_cnt,
8164 + void *pdata, int pdata_len,
8165 + struct omap_device_pm_latency *pm_lats,
8166 + int pm_lats_cnt);
8167 +
8168 +int omap_device_register(struct omap_device *od);
8169 +
8170 +/* OMAP PM interface */
8171 +int omap_device_align_pm_lat(struct platform_device *pdev,
8172 + u32 new_wakeup_lat_limit);
8173 +struct powerdomain *omap_device_get_pwrdm(struct omap_device *od);
8174 +
8175 +/* Other */
8176 +
8177 +int omap_device_idle_hwmods(struct omap_device *od);
8178 +int omap_device_enable_hwmods(struct omap_device *od);
8179 +
8180 +int omap_device_disable_clocks(struct omap_device *od);
8181 +int omap_device_enable_clocks(struct omap_device *od);
8182 +
8183 +
8184 +/*
8185 + * Entries should be kept in latency order ascending
8186 + *
8187 + * deact_lat is the maximum number of microseconds required to complete
8188 + * deactivate_func() at the device's slowest OPP.
8189 + *
8190 + * act_lat is the maximum number of microseconds required to complete
8191 + * activate_func() at the device's slowest OPP.
8192 + *
8193 + * This will result in some suboptimal power management decisions at fast
8194 + * OPPs, but avoids having to recompute all device power management decisions
8195 + * if the system shifts from a fast OPP to a slow OPP (in order to meet
8196 + * latency requirements).
8197 + *
8198 + * XXX should deactivate_func/activate_func() take platform_device pointers
8199 + * rather than omap_device pointers?
8200 + */
8201 +struct omap_device_pm_latency {
8202 + u32 deactivate_lat;
8203 + int (*deactivate_func)(struct omap_device *od);
8204 + u32 activate_lat;
8205 + int (*activate_func)(struct omap_device *od);
8206 +};
8207 +
8208 +
8209 +/* Get omap_device pointer from platform_device pointer */
8210 +#define to_omap_device(x) container_of((x), struct omap_device, pdev)
8211 +
8212 +#endif
8213 --- /dev/null
8214 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap_hwmod.h
8215 @@ -0,0 +1,467 @@
8216 +/*
8217 + * omap_hwmod macros, structures
8218 + *
8219 + * Copyright (C) 2009 Nokia Corporation
8220 + * Paul Walmsley
8221 + *
8222 + * Created in collaboration with (alphabetical order): Benoit Cousson,
8223 + * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
8224 + * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
8225 + *
8226 + * This program is free software; you can redistribute it and/or modify
8227 + * it under the terms of the GNU General Public License version 2 as
8228 + * published by the Free Software Foundation.
8229 + *
8230 + * These headers and macros are used to define OMAP on-chip module
8231 + * data and their integration with other OMAP modules and Linux.
8232 + *
8233 + * References:
8234 + * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
8235 + * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
8236 + * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
8237 + * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
8238 + * - Open Core Protocol Specification 2.2
8239 + *
8240 + * To do:
8241 + * - add interconnect error log structures
8242 + * - add pinmuxing
8243 + * - init_conn_id_bit (CONNID_BIT_VECTOR)
8244 + * - implement default hwmod SMS/SDRC flags?
8245 + *
8246 + */
8247 +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
8248 +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
8249 +
8250 +#include <linux/kernel.h>
8251 +#include <linux/ioport.h>
8252 +
8253 +#include <plat/cpu.h>
8254 +
8255 +struct omap_device;
8256 +
8257 +/* OCP SYSCONFIG bit shifts/masks */
8258 +#define SYSC_MIDLEMODE_SHIFT 12
8259 +#define SYSC_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT)
8260 +#define SYSC_CLOCKACTIVITY_SHIFT 8
8261 +#define SYSC_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT)
8262 +#define SYSC_SIDLEMODE_SHIFT 3
8263 +#define SYSC_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT)
8264 +#define SYSC_ENAWAKEUP_SHIFT 2
8265 +#define SYSC_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT)
8266 +#define SYSC_SOFTRESET_SHIFT 1
8267 +#define SYSC_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT)
8268 +#define SYSC_AUTOIDLE_SHIFT 0
8269 +#define SYSC_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT)
8270 +
8271 +/* OCP SYSSTATUS bit shifts/masks */
8272 +#define SYSS_RESETDONE_SHIFT 0
8273 +#define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT)
8274 +
8275 +/* Master standby/slave idle mode flags */
8276 +#define HWMOD_IDLEMODE_FORCE (1 << 0)
8277 +#define HWMOD_IDLEMODE_NO (1 << 1)
8278 +#define HWMOD_IDLEMODE_SMART (1 << 2)
8279 +
8280 +
8281 +/**
8282 + * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
8283 + * @name: name of the IRQ channel (module local name)
8284 + * @irq_ch: IRQ channel ID
8285 + *
8286 + * @name should be something short, e.g., "tx" or "rx". It is for use
8287 + * by platform_get_resource_byname(). It is defined locally to the
8288 + * hwmod.
8289 + */
8290 +struct omap_hwmod_irq_info {
8291 + const char *name;
8292 + u16 irq;
8293 +};
8294 +
8295 +/**
8296 + * struct omap_hwmod_dma_info - DMA channels used by the hwmod
8297 + * @name: name of the DMA channel (module local name)
8298 + * @dma_ch: DMA channel ID
8299 + *
8300 + * @name should be something short, e.g., "tx" or "rx". It is for use
8301 + * by platform_get_resource_byname(). It is defined locally to the
8302 + * hwmod.
8303 + */
8304 +struct omap_hwmod_dma_info {
8305 + const char *name;
8306 + u16 dma_ch;
8307 +};
8308 +
8309 +/**
8310 + * struct omap_hwmod_opt_clk - optional clocks used by this hwmod
8311 + * @role: "sys", "32k", "tv", etc -- for use in clk_get()
8312 + * @clkdev_dev_id: opt clock: clkdev dev_id string
8313 + * @clkdev_con_id: opt clock: clkdev con_id string
8314 + * @_clk: pointer to the struct clk (filled in at runtime)
8315 + *
8316 + * The module's interface clock and main functional clock should not
8317 + * be added as optional clocks.
8318 + */
8319 +struct omap_hwmod_opt_clk {
8320 + const char *role;
8321 + const char *clkdev_dev_id;
8322 + const char *clkdev_con_id;
8323 + struct clk *_clk;
8324 +};
8325 +
8326 +
8327 +/* omap_hwmod_omap2_firewall.flags bits */
8328 +#define OMAP_FIREWALL_L3 (1 << 0)
8329 +#define OMAP_FIREWALL_L4 (1 << 1)
8330 +
8331 +/**
8332 + * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data
8333 + * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_*
8334 + * @l4_fw_region: L4 firewall region ID
8335 + * @l4_prot_group: L4 protection group ID
8336 + * @flags: (see omap_hwmod_omap2_firewall.flags macros above)
8337 + */
8338 +struct omap_hwmod_omap2_firewall {
8339 + u8 l3_perm_bit;
8340 + u8 l4_fw_region;
8341 + u8 l4_prot_group;
8342 + u8 flags;
8343 +};
8344 +
8345 +
8346 +/*
8347 + * omap_hwmod_addr_space.flags bits
8348 + *
8349 + * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init.
8350 + * ADDR_TYPE_RT: Address space contains module register target data.
8351 + */
8352 +#define ADDR_MAP_ON_INIT (1 << 0)
8353 +#define ADDR_TYPE_RT (1 << 1)
8354 +
8355 +/**
8356 + * struct omap_hwmod_addr_space - MPU address space handled by the hwmod
8357 + * @pa_start: starting physical address
8358 + * @pa_end: ending physical address
8359 + * @flags: (see omap_hwmod_addr_space.flags macros above)
8360 + *
8361 + * Address space doesn't necessarily follow physical interconnect
8362 + * structure. GPMC is one example.
8363 + */
8364 +struct omap_hwmod_addr_space {
8365 + u32 pa_start;
8366 + u32 pa_end;
8367 + u8 flags;
8368 +};
8369 +
8370 +
8371 +/*
8372 + * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this
8373 + * interface to interact with the hwmod. Used to add sleep dependencies
8374 + * when the module is enabled or disabled.
8375 + */
8376 +#define OCP_USER_MPU (1 << 0)
8377 +#define OCP_USER_SDMA (1 << 1)
8378 +
8379 +/* omap_hwmod_ocp_if.flags bits */
8380 +#define OCPIF_HAS_IDLEST (1 << 0)
8381 +#define OCPIF_SWSUP_IDLE (1 << 1)
8382 +#define OCPIF_CAN_BURST (1 << 2)
8383 +
8384 +/**
8385 + * struct omap_hwmod_ocp_if - OCP interface data
8386 + * @master: struct omap_hwmod that initiates OCP transactions on this link
8387 + * @slave: struct omap_hwmod that responds to OCP transactions on this link
8388 + * @addr: address space associated with this link
8389 + * @clkdev_dev_id: interface clock: clkdev dev_id string
8390 + * @clkdev_con_id: interface clock: clkdev con_id string
8391 + * @_clk: pointer to the interface struct clk (filled in at runtime)
8392 + * @fw: interface firewall data
8393 + * @addr_cnt: ARRAY_SIZE(@addr)
8394 + * @width: OCP data width
8395 + * @thread_cnt: number of threads
8396 + * @max_burst_len: maximum burst length in @width sized words (0 if unlimited)
8397 + * @user: initiators using this interface (see OCP_USER_* macros above)
8398 + * @flags: OCP interface flags (see OCPIF_* macros above)
8399 + *
8400 + * It may also be useful to add a tag_cnt field for OCP2.x devices.
8401 + *
8402 + * Parameter names beginning with an underscore are managed internally by
8403 + * the omap_hwmod code and should not be set during initialization.
8404 + */
8405 +struct omap_hwmod_ocp_if {
8406 + struct omap_hwmod *master;
8407 + struct omap_hwmod *slave;
8408 + struct omap_hwmod_addr_space *addr;
8409 + const char *clkdev_dev_id;
8410 + const char *clkdev_con_id;
8411 + struct clk *_clk;
8412 + union {
8413 + struct omap_hwmod_omap2_firewall omap2;
8414 + } fw;
8415 + u8 addr_cnt;
8416 + u8 width;
8417 + u8 thread_cnt;
8418 + u8 max_burst_len;
8419 + u8 user;
8420 + u8 flags;
8421 +};
8422 +
8423 +
8424 +/* Macros for use in struct omap_hwmod_sysconfig */
8425 +
8426 +/* Flags for use in omap_hwmod_sysconfig.idlemodes */
8427 +#define MASTER_STANDBY_SHIFT 2
8428 +#define SLAVE_IDLE_SHIFT 0
8429 +#define SIDLE_FORCE (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT)
8430 +#define SIDLE_NO (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT)
8431 +#define SIDLE_SMART (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT)
8432 +#define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
8433 +#define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
8434 +#define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
8435 +
8436 +/* omap_hwmod_sysconfig.sysc_flags capability flags */
8437 +#define SYSC_HAS_AUTOIDLE (1 << 0)
8438 +#define SYSC_HAS_SOFTRESET (1 << 1)
8439 +#define SYSC_HAS_ENAWAKEUP (1 << 2)
8440 +#define SYSC_HAS_EMUFREE (1 << 3)
8441 +#define SYSC_HAS_CLOCKACTIVITY (1 << 4)
8442 +#define SYSC_HAS_SIDLEMODE (1 << 5)
8443 +#define SYSC_HAS_MIDLEMODE (1 << 6)
8444 +#define SYSS_MISSING (1 << 7)
8445 +
8446 +/* omap_hwmod_sysconfig.clockact flags */
8447 +#define CLOCKACT_TEST_BOTH 0x0
8448 +#define CLOCKACT_TEST_MAIN 0x1
8449 +#define CLOCKACT_TEST_ICLK 0x2
8450 +#define CLOCKACT_TEST_NONE 0x3
8451 +
8452 +/**
8453 + * struct omap_hwmod_sysconfig - hwmod OCP_SYSCONFIG/OCP_SYSSTATUS data
8454 + * @rev_offs: IP block revision register offset (from module base addr)
8455 + * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
8456 + * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
8457 + * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
8458 + * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
8459 + * @clockact: the default value of the module CLOCKACTIVITY bits
8460 + *
8461 + * @clockact describes to the module which clocks are likely to be
8462 + * disabled when the PRCM issues its idle request to the module. Some
8463 + * modules have separate clockdomains for the interface clock and main
8464 + * functional clock, and can check whether they should acknowledge the
8465 + * idle request based on the internal module functionality that has
8466 + * been associated with the clocks marked in @clockact. This field is
8467 + * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below)
8468 + *
8469 + */
8470 +struct omap_hwmod_sysconfig {
8471 + u16 rev_offs;
8472 + u16 sysc_offs;
8473 + u16 syss_offs;
8474 + u8 idlemodes;
8475 + u8 sysc_flags;
8476 + u8 clockact;
8477 +};
8478 +
8479 +/**
8480 + * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data
8481 + * @module_offs: PRCM submodule offset from the start of the PRM/CM
8482 + * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3)
8483 + * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs
8484 + * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3)
8485 + * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit
8486 + * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit
8487 + *
8488 + * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST,
8489 + * WKEN, GRPSEL registers. In an ideal world, no extra information
8490 + * would be needed for IDLEST information, but alas, there are some
8491 + * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit
8492 + * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST)
8493 + */
8494 +struct omap_hwmod_omap2_prcm {
8495 + s16 module_offs;
8496 + u8 prcm_reg_id;
8497 + u8 module_bit;
8498 + u8 idlest_reg_id;
8499 + u8 idlest_idle_bit;
8500 + u8 idlest_stdby_bit;
8501 +};
8502 +
8503 +
8504 +/**
8505 + * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
8506 + * @module_offs: PRCM submodule offset from the start of the PRM/CM1/CM2
8507 + * @device_offs: device register offset from @module_offs
8508 + * @submodule_wkdep_bit: bit shift of the WKDEP range
8509 + */
8510 +struct omap_hwmod_omap4_prcm {
8511 + u32 module_offs;
8512 + u16 device_offs;
8513 + u8 submodule_wkdep_bit;
8514 +};
8515 +
8516 +
8517 +/*
8518 + * omap_hwmod.flags definitions
8519 + *
8520 + * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
8521 + * of idle, rather than relying on module smart-idle
8522 + * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
8523 + * of standby, rather than relying on module smart-standby
8524 + * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
8525 + * SDRAM controller, etc.
8526 + * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
8527 + * controller, etc.
8528 + * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
8529 + * when module is enabled, rather than the default, which is to
8530 + * enable autoidle
8531 + * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
8532 + */
8533 +#define HWMOD_SWSUP_SIDLE (1 << 0)
8534 +#define HWMOD_SWSUP_MSTANDBY (1 << 1)
8535 +#define HWMOD_INIT_NO_RESET (1 << 2)
8536 +#define HWMOD_INIT_NO_IDLE (1 << 3)
8537 +#define HWMOD_NO_OCP_AUTOIDLE (1 << 4)
8538 +#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5)
8539 +
8540 +/*
8541 + * omap_hwmod._int_flags definitions
8542 + * These are for internal use only and are managed by the omap_hwmod code.
8543 + *
8544 + * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
8545 + * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
8546 + * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
8547 + */
8548 +#define _HWMOD_NO_MPU_PORT (1 << 0)
8549 +#define _HWMOD_WAKEUP_ENABLED (1 << 1)
8550 +#define _HWMOD_SYSCONFIG_LOADED (1 << 2)
8551 +
8552 +/*
8553 + * omap_hwmod._state definitions
8554 + *
8555 + * INITIALIZED: reset (optionally), initialized, enabled, disabled
8556 + * (optionally)
8557 + *
8558 + *
8559 + */
8560 +#define _HWMOD_STATE_UNKNOWN 0
8561 +#define _HWMOD_STATE_REGISTERED 1
8562 +#define _HWMOD_STATE_CLKS_INITED 2
8563 +#define _HWMOD_STATE_INITIALIZED 3
8564 +#define _HWMOD_STATE_ENABLED 4
8565 +#define _HWMOD_STATE_IDLE 5
8566 +#define _HWMOD_STATE_DISABLED 6
8567 +
8568 +/**
8569 + * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
8570 + * @name: name of the hwmod
8571 + * @od: struct omap_device currently associated with this hwmod (internal use)
8572 + * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
8573 + * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt)
8574 + * @prcm: PRCM data pertaining to this hwmod
8575 + * @clkdev_dev_id: main clock: clkdev dev_id string
8576 + * @clkdev_con_id: main clock: clkdev con_id string
8577 + * @_clk: pointer to the main struct clk (filled in at runtime)
8578 + * @opt_clks: other device clocks that drivers can request (0..*)
8579 + * @masters: ptr to array of OCP ifs that this hwmod can initiate on
8580 + * @slaves: ptr to array of OCP ifs that this hwmod can respond on
8581 + * @sysconfig: device SYSCONFIG/SYSSTATUS register data
8582 + * @dev_attr: arbitrary device attributes that can be passed to the driver
8583 + * @_sysc_cache: internal-use hwmod flags
8584 + * @_rt_va: cached register target start address (internal use)
8585 + * @_mpu_port_index: cached MPU register target slave ID (internal use)
8586 + * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6)
8587 + * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift
8588 + * @mpu_irqs_cnt: number of @mpu_irqs
8589 + * @sdma_chs_cnt: number of @sdma_chs
8590 + * @opt_clks_cnt: number of @opt_clks
8591 + * @master_cnt: number of @master entries
8592 + * @slaves_cnt: number of @slave entries
8593 + * @response_lat: device OCP response latency (in interface clock cycles)
8594 + * @_int_flags: internal-use hwmod flags
8595 + * @_state: internal-use hwmod state
8596 + * @flags: hwmod flags (documented below)
8597 + * @omap_chip: OMAP chips this hwmod is present on
8598 + * @node: list node for hwmod list (internal use)
8599 + *
8600 + * @clkdev_dev_id, @clkdev_con_id, and @clk all refer to this module's "main
8601 + * clock," which for our purposes is defined as "the functional clock needed
8602 + * for register accesses to complete." Modules may not have a main clock if
8603 + * the interface clock also serves as a main clock.
8604 + *
8605 + * Parameter names beginning with an underscore are managed internally by
8606 + * the omap_hwmod code and should not be set during initialization.
8607 + */
8608 +struct omap_hwmod {
8609 + const char *name;
8610 + struct omap_device *od;
8611 + struct omap_hwmod_irq_info *mpu_irqs;
8612 + struct omap_hwmod_dma_info *sdma_chs;
8613 + union {
8614 + struct omap_hwmod_omap2_prcm omap2;
8615 + struct omap_hwmod_omap4_prcm omap4;
8616 + } prcm;
8617 + const char *clkdev_dev_id;
8618 + const char *clkdev_con_id;
8619 + struct clk *_clk;
8620 + struct omap_hwmod_opt_clk *opt_clks;
8621 + struct omap_hwmod_ocp_if **masters; /* connect to *_IA */
8622 + struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */
8623 + struct omap_hwmod_sysconfig *sysconfig;
8624 + void *dev_attr;
8625 + u32 _sysc_cache;
8626 + void __iomem *_rt_va;
8627 + struct list_head node;
8628 + u16 flags;
8629 + u8 _mpu_port_index;
8630 + u8 msuspendmux_reg_id;
8631 + u8 msuspendmux_shift;
8632 + u8 response_lat;
8633 + u8 mpu_irqs_cnt;
8634 + u8 sdma_chs_cnt;
8635 + u8 opt_clks_cnt;
8636 + u8 masters_cnt;
8637 + u8 slaves_cnt;
8638 + u8 hwmods_cnt;
8639 + u8 _int_flags;
8640 + u8 _state;
8641 + const struct omap_chip_id omap_chip;
8642 +};
8643 +
8644 +int omap_hwmod_init(struct omap_hwmod **ohs);
8645 +int omap_hwmod_register(struct omap_hwmod *oh);
8646 +int omap_hwmod_unregister(struct omap_hwmod *oh);
8647 +struct omap_hwmod *omap_hwmod_lookup(const char *name);
8648 +int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh));
8649 +int omap_hwmod_late_init(void);
8650 +
8651 +int omap_hwmod_enable(struct omap_hwmod *oh);
8652 +int omap_hwmod_idle(struct omap_hwmod *oh);
8653 +int omap_hwmod_shutdown(struct omap_hwmod *oh);
8654 +
8655 +int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
8656 +int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
8657 +
8658 +int omap_hwmod_reset(struct omap_hwmod *oh);
8659 +void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
8660 +
8661 +void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs);
8662 +u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs);
8663 +
8664 +int omap_hwmod_count_resources(struct omap_hwmod *oh);
8665 +int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
8666 +
8667 +struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
8668 +
8669 +int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
8670 + struct omap_hwmod *init_oh);
8671 +int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
8672 + struct omap_hwmod *init_oh);
8673 +
8674 +int omap_hwmod_set_clockact_both(struct omap_hwmod *oh);
8675 +int omap_hwmod_set_clockact_main(struct omap_hwmod *oh);
8676 +int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh);
8677 +int omap_hwmod_set_clockact_none(struct omap_hwmod *oh);
8678 +
8679 +int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
8680 +int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
8681 +
8682 +#endif
8683 --- /dev/null
8684 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap-pm.h
8685 @@ -0,0 +1,301 @@
8686 +/*
8687 + * omap-pm.h - OMAP power management interface
8688 + *
8689 + * Copyright (C) 2008-2009 Texas Instruments, Inc.
8690 + * Copyright (C) 2008-2009 Nokia Corporation
8691 + * Paul Walmsley
8692 + *
8693 + * Interface developed by (in alphabetical order): Karthik Dasu, Jouni
8694 + * Högander, Tony Lindgren, Rajendra Nayak, Sakari Poussa,
8695 + * Veeramanikandan Raju, Anand Sawant, Igor Stoppa, Paul Walmsley,
8696 + * Richard Woodruff
8697 + */
8698 +
8699 +#ifndef ASM_ARM_ARCH_OMAP_OMAP_PM_H
8700 +#define ASM_ARM_ARCH_OMAP_OMAP_PM_H
8701 +
8702 +#include <linux/device.h>
8703 +#include <linux/cpufreq.h>
8704 +
8705 +#include "powerdomain.h"
8706 +
8707 +/**
8708 + * struct omap_opp - clock frequency-to-OPP ID table for DSP, MPU
8709 + * @rate: target clock rate
8710 + * @opp_id: OPP ID
8711 + * @min_vdd: minimum VDD1 voltage (in millivolts) for this OPP
8712 + *
8713 + * Operating performance point data. Can vary by OMAP chip and board.
8714 + */
8715 +struct omap_opp {
8716 + unsigned long rate;
8717 + u8 opp_id;
8718 + u16 min_vdd;
8719 +};
8720 +
8721 +extern struct omap_opp *mpu_opps;
8722 +extern struct omap_opp *dsp_opps;
8723 +extern struct omap_opp *l3_opps;
8724 +
8725 +/*
8726 + * agent_id values for use with omap_pm_set_min_bus_tput():
8727 + *
8728 + * OCP_INITIATOR_AGENT is only valid for devices that can act as
8729 + * initiators -- it represents the device's L3 interconnect
8730 + * connection. OCP_TARGET_AGENT represents the device's L4
8731 + * interconnect connection.
8732 + */
8733 +#define OCP_TARGET_AGENT 1
8734 +#define OCP_INITIATOR_AGENT 2
8735 +
8736 +/**
8737 + * omap_pm_if_early_init - OMAP PM init code called before clock fw init
8738 + * @mpu_opp_table: array ptr to struct omap_opp for MPU
8739 + * @dsp_opp_table: array ptr to struct omap_opp for DSP
8740 + * @l3_opp_table : array ptr to struct omap_opp for CORE
8741 + *
8742 + * Initialize anything that must be configured before the clock
8743 + * framework starts. The "_if_" is to avoid name collisions with the
8744 + * PM idle-loop code.
8745 + */
8746 +int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
8747 + struct omap_opp *dsp_opp_table,
8748 + struct omap_opp *l3_opp_table);
8749 +
8750 +/**
8751 + * omap_pm_if_init - OMAP PM init code called after clock fw init
8752 + *
8753 + * The main initialization code. OPP tables are passed in here. The
8754 + * "_if_" is to avoid name collisions with the PM idle-loop code.
8755 + */
8756 +int __init omap_pm_if_init(void);
8757 +
8758 +/**
8759 + * omap_pm_if_exit - OMAP PM exit code
8760 + *
8761 + * Exit code; currently unused. The "_if_" is to avoid name
8762 + * collisions with the PM idle-loop code.
8763 + */
8764 +void omap_pm_if_exit(void);
8765 +
8766 +/*
8767 + * Device-driver-originated constraints (via board-*.c files, platform_data)
8768 + */
8769 +
8770 +
8771 +/**
8772 + * omap_pm_set_max_mpu_wakeup_lat - set the maximum MPU wakeup latency
8773 + * @dev: struct device * requesting the constraint
8774 + * @t: maximum MPU wakeup latency in microseconds
8775 + *
8776 + * Request that the maximum interrupt latency for the MPU to be no
8777 + * greater than 't' microseconds. "Interrupt latency" in this case is
8778 + * defined as the elapsed time from the occurrence of a hardware or
8779 + * timer interrupt to the time when the device driver's interrupt
8780 + * service routine has been entered by the MPU.
8781 + *
8782 + * It is intended that underlying PM code will use this information to
8783 + * determine what power state to put the MPU powerdomain into, and
8784 + * possibly the CORE powerdomain as well, since interrupt handling
8785 + * code currently runs from SDRAM. Advanced PM or board*.c code may
8786 + * also configure interrupt controller priorities, OCP bus priorities,
8787 + * CPU speed(s), etc.
8788 + *
8789 + * This function will not affect device wakeup latency, e.g., time
8790 + * elapsed from when a device driver enables a hardware device with
8791 + * clk_enable(), to when the device is ready for register access or
8792 + * other use. To control this device wakeup latency, use
8793 + * set_max_dev_wakeup_lat()
8794 + *
8795 + * Multiple calls to set_max_mpu_wakeup_lat() will replace the
8796 + * previous t value. To remove the latency target for the MPU, call
8797 + * with t = -1.
8798 + *
8799 + * No return value.
8800 + */
8801 +void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
8802 +
8803 +
8804 +/**
8805 + * omap_pm_set_min_bus_tput - set minimum bus throughput needed by device
8806 + * @dev: struct device * requesting the constraint
8807 + * @tbus_id: interconnect to operate on (OCP_{INITIATOR,TARGET}_AGENT)
8808 + * @r: minimum throughput (in KiB/s)
8809 + *
8810 + * Request that the minimum data throughput on the OCP interconnect
8811 + * attached to device 'dev' interconnect agent 'tbus_id' be no less
8812 + * than 'r' KiB/s.
8813 + *
8814 + * It is expected that the OMAP PM or bus code will use this
8815 + * information to set the interconnect clock to run at the lowest
8816 + * possible speed that satisfies all current system users. The PM or
8817 + * bus code will adjust the estimate based on its model of the bus, so
8818 + * device driver authors should attempt to specify an accurate
8819 + * quantity for their device use case, and let the PM or bus code
8820 + * overestimate the numbers as necessary to handle request/response
8821 + * latency, other competing users on the system, etc. On OMAP2/3, if
8822 + * a driver requests a minimum L4 interconnect speed constraint, the
8823 + * code will also need to add an minimum L3 interconnect speed
8824 + * constraint,
8825 + *
8826 + * Multiple calls to set_min_bus_tput() will replace the previous rate
8827 + * value for this device. To remove the interconnect throughput
8828 + * restriction for this device, call with r = 0.
8829 + *
8830 + * No return value.
8831 + */
8832 +void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r);
8833 +
8834 +
8835 +/**
8836 + * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency
8837 + * @dev: struct device *
8838 + * @t: maximum device wakeup latency in microseconds
8839 + *
8840 + * Request that the maximum amount of time necessary for a device to
8841 + * become accessible after its clocks are enabled should be no greater
8842 + * than 't' microseconds. Specifically, this represents the time from
8843 + * when a device driver enables device clocks with clk_enable(), to
8844 + * when the register reads and writes on the device will succeed.
8845 + * This function should be called before clk_disable() is called,
8846 + * since the power state transition decision may be made during
8847 + * clk_disable().
8848 + *
8849 + * It is intended that underlying PM code will use this information to
8850 + * determine what power state to put the powerdomain enclosing this
8851 + * device into.
8852 + *
8853 + * Multiple calls to set_max_dev_wakeup_lat() will replace the
8854 + * previous wakeup latency values for this device. To remove the wakeup
8855 + * latency restriction for this device, call with t = -1.
8856 + *
8857 + * No return value.
8858 + */
8859 +void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t);
8860 +
8861 +
8862 +/**
8863 + * omap_pm_set_max_sdma_lat - set the maximum system DMA transfer start latency
8864 + * @dev: struct device *
8865 + * @t: maximum DMA transfer start latency in microseconds
8866 + *
8867 + * Request that the maximum system DMA transfer start latency for this
8868 + * device 'dev' should be no greater than 't' microseconds. "DMA
8869 + * transfer start latency" here is defined as the elapsed time from
8870 + * when a device (e.g., McBSP) requests that a system DMA transfer
8871 + * start or continue, to the time at which data starts to flow into
8872 + * that device from the system DMA controller.
8873 + *
8874 + * It is intended that underlying PM code will use this information to
8875 + * determine what power state to put the CORE powerdomain into.
8876 + *
8877 + * Since system DMA transfers may not involve the MPU, this function
8878 + * will not affect MPU wakeup latency. Use set_max_cpu_lat() to do
8879 + * so. Similarly, this function will not affect device wakeup latency
8880 + * -- use set_max_dev_wakeup_lat() to affect that.
8881 + *
8882 + * Multiple calls to set_max_sdma_lat() will replace the previous t
8883 + * value for this device. To remove the maximum DMA latency for this
8884 + * device, call with t = -1.
8885 + *
8886 + * No return value.
8887 + */
8888 +void omap_pm_set_max_sdma_lat(struct device *dev, long t);
8889 +
8890 +
8891 +/*
8892 + * DSP Bridge-specific constraints
8893 + */
8894 +
8895 +/**
8896 + * omap_pm_dsp_get_opp_table - get OPP->DSP clock frequency table
8897 + *
8898 + * Intended for use by DSPBridge. Returns an array of OPP->DSP clock
8899 + * frequency entries. The final item in the array should have .rate =
8900 + * .opp_id = 0.
8901 + */
8902 +const struct omap_opp *omap_pm_dsp_get_opp_table(void);
8903 +
8904 +/**
8905 + * omap_pm_dsp_set_min_opp - receive desired OPP target ID from DSP Bridge
8906 + * @opp_id: target DSP OPP ID
8907 + *
8908 + * Set a minimum OPP ID for the DSP. This is intended to be called
8909 + * only from the DSP Bridge MPU-side driver. Unfortunately, the only
8910 + * information that code receives from the DSP/BIOS load estimator is the
8911 + * target OPP ID; hence, this interface. No return value.
8912 + */
8913 +void omap_pm_dsp_set_min_opp(u8 opp_id);
8914 +
8915 +/**
8916 + * omap_pm_dsp_get_opp - report the current DSP OPP ID
8917 + *
8918 + * Report the current OPP for the DSP. Since on OMAP3, the DSP and
8919 + * MPU share a single voltage domain, the OPP ID returned back may
8920 + * represent a higher DSP speed than the OPP requested via
8921 + * omap_pm_dsp_set_min_opp().
8922 + *
8923 + * Returns the current VDD1 OPP ID, or 0 upon error.
8924 + */
8925 +u8 omap_pm_dsp_get_opp(void);
8926 +
8927 +
8928 +/*
8929 + * CPUFreq-originated constraint
8930 + *
8931 + * In the future, this should be handled by custom OPP clocktype
8932 + * functions.
8933 + */
8934 +
8935 +/**
8936 + * omap_pm_cpu_get_freq_table - return a cpufreq_frequency_table array ptr
8937 + *
8938 + * Provide a frequency table usable by CPUFreq for the current chip/board.
8939 + * Returns a pointer to a struct cpufreq_frequency_table array or NULL
8940 + * upon error.
8941 + */
8942 +struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void);
8943 +
8944 +/**
8945 + * omap_pm_cpu_set_freq - set the current minimum MPU frequency
8946 + * @f: MPU frequency in Hz
8947 + *
8948 + * Set the current minimum CPU frequency. The actual CPU frequency
8949 + * used could end up higher if the DSP requested a higher OPP.
8950 + * Intended to be called by plat-omap/cpu_omap.c:omap_target(). No
8951 + * return value.
8952 + */
8953 +void omap_pm_cpu_set_freq(unsigned long f);
8954 +
8955 +/**
8956 + * omap_pm_cpu_get_freq - report the current CPU frequency
8957 + *
8958 + * Returns the current MPU frequency, or 0 upon error.
8959 + */
8960 +unsigned long omap_pm_cpu_get_freq(void);
8961 +
8962 +
8963 +/*
8964 + * Device context loss tracking
8965 + */
8966 +
8967 +/**
8968 + * omap_pm_get_dev_context_loss_count - return count of times dev has lost ctx
8969 + * @dev: struct device *
8970 + *
8971 + * This function returns the number of times that the device @dev has
8972 + * lost its internal context. This generally occurs on a powerdomain
8973 + * transition to OFF. Drivers use this as an optimization to avoid restoring
8974 + * context if the device hasn't lost it. To use, drivers should initially
8975 + * call this in their context save functions and store the result. Early in
8976 + * the driver's context restore function, the driver should call this function
8977 + * again, and compare the result to the stored counter. If they differ, the
8978 + * driver must restore device context. If the number of context losses
8979 + * exceeds the maximum positive integer, the function will wrap to 0 and
8980 + * continue counting. Returns the number of context losses for this device,
8981 + * or -EINVAL upon error.
8982 + */
8983 +int omap_pm_get_dev_context_loss_count(struct device *dev);
8984 +
8985 +
8986 +#endif
8987 --- /dev/null
8988 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/onenand.h
8989 @@ -0,0 +1,43 @@
8990 +/*
8991 + * arch/arm/plat-omap/include/mach/onenand.h
8992 + *
8993 + * Copyright (C) 2006 Nokia Corporation
8994 + * Author: Juha Yrjola
8995 + *
8996 + * This program is free software; you can redistribute it and/or modify
8997 + * it under the terms of the GNU General Public License version 2 as
8998 + * published by the Free Software Foundation.
8999 + */
9000 +
9001 +#include <linux/mtd/mtd.h>
9002 +#include <linux/mtd/partitions.h>
9003 +
9004 +#define ONENAND_SYNC_READ (1 << 0)
9005 +#define ONENAND_SYNC_READWRITE (1 << 1)
9006 +
9007 +struct omap_onenand_platform_data {
9008 + int cs;
9009 + int gpio_irq;
9010 + struct mtd_partition *parts;
9011 + int nr_parts;
9012 + int (*onenand_setup)(void __iomem *, int freq);
9013 + int dma_channel;
9014 + u8 flags;
9015 +};
9016 +
9017 +#define ONENAND_MAX_PARTITIONS 8
9018 +
9019 +#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
9020 + defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
9021 +
9022 +extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
9023 +
9024 +#else
9025 +
9026 +#define board_onenand_data NULL
9027 +
9028 +static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
9029 +{
9030 +}
9031 +
9032 +#endif
9033 --- /dev/null
9034 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/param.h
9035 @@ -0,0 +1,8 @@
9036 +/*
9037 + * arch/arm/plat-omap/include/mach/param.h
9038 + *
9039 + */
9040 +
9041 +#ifdef CONFIG_OMAP_32K_TIMER_HZ
9042 +#define HZ CONFIG_OMAP_32K_TIMER_HZ
9043 +#endif
9044 --- /dev/null
9045 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/powerdomain.h
9046 @@ -0,0 +1,187 @@
9047 +/*
9048 + * OMAP2/3 powerdomain control
9049 + *
9050 + * Copyright (C) 2007-8 Texas Instruments, Inc.
9051 + * Copyright (C) 2007-8 Nokia Corporation
9052 + *
9053 + * Written by Paul Walmsley
9054 + *
9055 + * This program is free software; you can redistribute it and/or modify
9056 + * it under the terms of the GNU General Public License version 2 as
9057 + * published by the Free Software Foundation.
9058 + */
9059 +
9060 +#ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
9061 +#define ASM_ARM_ARCH_OMAP_POWERDOMAIN
9062 +
9063 +#include <linux/types.h>
9064 +#include <linux/list.h>
9065 +
9066 +#include <asm/atomic.h>
9067 +
9068 +#include <plat/cpu.h>
9069 +
9070 +
9071 +/* Powerdomain basic power states */
9072 +#define PWRDM_POWER_OFF 0x0
9073 +#define PWRDM_POWER_RET 0x1
9074 +#define PWRDM_POWER_INACTIVE 0x2
9075 +#define PWRDM_POWER_ON 0x3
9076 +
9077 +#define PWRDM_MAX_PWRSTS 4
9078 +
9079 +/* Powerdomain allowable state bitfields */
9080 +#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
9081 + (1 << PWRDM_POWER_ON))
9082 +
9083 +#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
9084 + (1 << PWRDM_POWER_RET))
9085 +
9086 +#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
9087 +
9088 +
9089 +/* Powerdomain flags */
9090 +#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
9091 +#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
9092 + * in MEM bank 1 position. This is
9093 + * true for OMAP3430
9094 + */
9095 +
9096 +/*
9097 + * Number of memory banks that are power-controllable. On OMAP3430, the
9098 + * maximum is 4.
9099 + */
9100 +#define PWRDM_MAX_MEM_BANKS 4
9101 +
9102 +/*
9103 + * Maximum number of clockdomains that can be associated with a powerdomain.
9104 + * CORE powerdomain on OMAP3 is the worst case
9105 + */
9106 +#define PWRDM_MAX_CLKDMS 4
9107 +
9108 +/* XXX A completely arbitrary number. What is reasonable here? */
9109 +#define PWRDM_TRANSITION_BAILOUT 100000
9110 +
9111 +struct clockdomain;
9112 +struct powerdomain;
9113 +
9114 +/* Encodes dependencies between powerdomains - statically defined */
9115 +struct pwrdm_dep {
9116 +
9117 + /* Powerdomain name */
9118 + const char *pwrdm_name;
9119 +
9120 + /* Powerdomain pointer - resolved by the powerdomain code */
9121 + struct powerdomain *pwrdm;
9122 +
9123 + /* Flags to mark OMAP chip restrictions, etc. */
9124 + const struct omap_chip_id omap_chip;
9125 +
9126 +};
9127 +
9128 +struct powerdomain {
9129 +
9130 + /* Powerdomain name */
9131 + const char *name;
9132 +
9133 + /* the address offset from CM_BASE/PRM_BASE */
9134 + const s16 prcm_offs;
9135 +
9136 + /* Used to represent the OMAP chip types containing this pwrdm */
9137 + const struct omap_chip_id omap_chip;
9138 +
9139 + /* Powerdomains that can be told to wake this powerdomain up */
9140 + struct pwrdm_dep *wkdep_srcs;
9141 +
9142 + /* Powerdomains that can be told to keep this pwrdm from inactivity */
9143 + struct pwrdm_dep *sleepdep_srcs;
9144 +
9145 + /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
9146 + const u8 dep_bit;
9147 +
9148 + /* Possible powerdomain power states */
9149 + const u8 pwrsts;
9150 +
9151 + /* Possible logic power states when pwrdm in RETENTION */
9152 + const u8 pwrsts_logic_ret;
9153 +
9154 + /* Powerdomain flags */
9155 + const u8 flags;
9156 +
9157 + /* Number of software-controllable memory banks in this powerdomain */
9158 + const u8 banks;
9159 +
9160 + /* Possible memory bank pwrstates when pwrdm in RETENTION */
9161 + const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
9162 +
9163 + /* Possible memory bank pwrstates when pwrdm is ON */
9164 + const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
9165 +
9166 + /* Clockdomains in this powerdomain */
9167 + struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
9168 +
9169 + struct list_head node;
9170 +
9171 + int state;
9172 + unsigned state_counter[PWRDM_MAX_PWRSTS];
9173 +
9174 +#ifdef CONFIG_PM_DEBUG
9175 + s64 timer;
9176 + s64 state_timer[PWRDM_MAX_PWRSTS];
9177 +#endif
9178 +};
9179 +
9180 +
9181 +void pwrdm_init(struct powerdomain **pwrdm_list);
9182 +
9183 +int pwrdm_register(struct powerdomain *pwrdm);
9184 +int pwrdm_unregister(struct powerdomain *pwrdm);
9185 +struct powerdomain *pwrdm_lookup(const char *name);
9186 +
9187 +int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
9188 + void *user);
9189 +int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
9190 + void *user);
9191 +
9192 +int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
9193 +int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
9194 +int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
9195 + int (*fn)(struct powerdomain *pwrdm,
9196 + struct clockdomain *clkdm));
9197 +
9198 +int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9199 +int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9200 +int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9201 +int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9202 +int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9203 +int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9204 +
9205 +int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
9206 +
9207 +int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
9208 +int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
9209 +int pwrdm_read_pwrst(struct powerdomain *pwrdm);
9210 +int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
9211 +int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
9212 +
9213 +int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
9214 +int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
9215 +int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
9216 +
9217 +int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
9218 +int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
9219 +int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
9220 +int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
9221 +
9222 +int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
9223 +int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
9224 +bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
9225 +
9226 +int pwrdm_wait_transition(struct powerdomain *pwrdm);
9227 +
9228 +int pwrdm_state_switch(struct powerdomain *pwrdm);
9229 +int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
9230 +int pwrdm_pre_transition(void);
9231 +int pwrdm_post_transition(void);
9232 +
9233 +#endif
9234 --- /dev/null
9235 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/prcm.h
9236 @@ -0,0 +1,39 @@
9237 +/*
9238 + * arch/arm/plat-omap/include/mach/prcm.h
9239 + *
9240 + * Access definations for use in OMAP24XX clock and power management
9241 + *
9242 + * Copyright (C) 2005 Texas Instruments, Inc.
9243 + *
9244 + * This program is free software; you can redistribute it and/or modify
9245 + * it under the terms of the GNU General Public License as published by
9246 + * the Free Software Foundation; either version 2 of the License, or
9247 + * (at your option) any later version.
9248 + *
9249 + * This program is distributed in the hope that it will be useful,
9250 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
9251 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9252 + * GNU General Public License for more details.
9253 + *
9254 + * You should have received a copy of the GNU General Public License
9255 + * along with this program; if not, write to the Free Software
9256 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
9257 + */
9258 +
9259 +#ifndef __ASM_ARM_ARCH_OMAP_PRCM_H
9260 +#define __ASM_ARM_ARCH_OMAP_PRCM_H
9261 +
9262 +u32 omap_prcm_get_reset_sources(void);
9263 +void omap_prcm_arch_reset(char mode);
9264 +int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
9265 +
9266 +#define START_PADCONF_SAVE 0x2
9267 +#define PADCONF_SAVE_DONE 0x1
9268 +
9269 +void omap3_prcm_save_context(void);
9270 +void omap3_prcm_restore_context(void);
9271 +
9272 +#endif
9273 +
9274 +
9275 +
9276 --- /dev/null
9277 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/sdrc.h
9278 @@ -0,0 +1,158 @@
9279 +#ifndef ____ASM_ARCH_SDRC_H
9280 +#define ____ASM_ARCH_SDRC_H
9281 +
9282 +/*
9283 + * OMAP2/3 SDRC/SMS register definitions
9284 + *
9285 + * Copyright (C) 2007-2008 Texas Instruments, Inc.
9286 + * Copyright (C) 2007-2008 Nokia Corporation
9287 + *
9288 + * Tony Lindgren
9289 + * Paul Walmsley
9290 + * Richard Woodruff
9291 + *
9292 + * This program is free software; you can redistribute it and/or modify
9293 + * it under the terms of the GNU General Public License version 2 as
9294 + * published by the Free Software Foundation.
9295 + */
9296 +
9297 +#include <mach/io.h>
9298 +
9299 +/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
9300 +
9301 +#define SDRC_SYSCONFIG 0x010
9302 +#define SDRC_CS_CFG 0x040
9303 +#define SDRC_SHARING 0x044
9304 +#define SDRC_ERR_TYPE 0x04C
9305 +#define SDRC_DLLA_CTRL 0x060
9306 +#define SDRC_DLLA_STATUS 0x064
9307 +#define SDRC_DLLB_CTRL 0x068
9308 +#define SDRC_DLLB_STATUS 0x06C
9309 +#define SDRC_POWER 0x070
9310 +#define SDRC_MCFG_0 0x080
9311 +#define SDRC_MR_0 0x084
9312 +#define SDRC_EMR2_0 0x08c
9313 +#define SDRC_ACTIM_CTRL_A_0 0x09c
9314 +#define SDRC_ACTIM_CTRL_B_0 0x0a0
9315 +#define SDRC_RFR_CTRL_0 0x0a4
9316 +#define SDRC_MANUAL_0 0x0a8
9317 +#define SDRC_MCFG_1 0x0B0
9318 +#define SDRC_MR_1 0x0B4
9319 +#define SDRC_EMR2_1 0x0BC
9320 +#define SDRC_ACTIM_CTRL_A_1 0x0C4
9321 +#define SDRC_ACTIM_CTRL_B_1 0x0C8
9322 +#define SDRC_RFR_CTRL_1 0x0D4
9323 +#define SDRC_MANUAL_1 0x0D8
9324 +
9325 +#define SDRC_POWER_AUTOCOUNT_SHIFT 8
9326 +#define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
9327 +#define SDRC_POWER_CLKCTRL_SHIFT 4
9328 +#define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
9329 +#define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
9330 +
9331 +/*
9332 + * These values represent the number of memory clock cycles between
9333 + * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
9334 + * rows per device, and include a subtraction of a 50 cycle window in the
9335 + * event that the autorefresh command is delayed due to other SDRC activity.
9336 + * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
9337 + * counter reaches 0.
9338 + *
9339 + * These represent optimal values for common parts, it won't work for all.
9340 + * As long as you scale down, most parameters are still work, they just
9341 + * become sub-optimal. The RFR value goes in the opposite direction. If you
9342 + * don't adjust it down as your clock period increases the refresh interval
9343 + * will not be met. Setting all parameters for complete worst case may work,
9344 + * but may cut memory performance by 2x. Due to errata the DLLs need to be
9345 + * unlocked and their value needs run time calibration. A dynamic call is
9346 + * need for that as no single right value exists acorss production samples.
9347 + *
9348 + * Only the FULL speed values are given. Current code is such that rate
9349 + * changes must be made at DPLLoutx2. The actual value adjustment for low
9350 + * frequency operation will be handled by omap_set_performance()
9351 + *
9352 + * By having the boot loader boot up in the fastest L4 speed available likely
9353 + * will result in something which you can switch between.
9354 + */
9355 +#define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
9356 +#define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
9357 +#define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
9358 +#define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
9359 +#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
9360 +
9361 +
9362 +/*
9363 + * SMS register access
9364 + */
9365 +
9366 +#define OMAP242X_SMS_REGADDR(reg) \
9367 + (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
9368 +#define OMAP243X_SMS_REGADDR(reg) \
9369 + (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
9370 +#define OMAP343X_SMS_REGADDR(reg) \
9371 + (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
9372 +
9373 +/* SMS register offsets - read/write with sms_{read,write}_reg() */
9374 +
9375 +#define SMS_SYSCONFIG 0x010
9376 +#define SMS_ROT_CONTROL(context) (0x180 + 0x10 * context)
9377 +#define SMS_ROT_SIZE(context) (0x184 + 0x10 * context)
9378 +#define SMS_ROT_PHYSICAL_BA(context) (0x188 + 0x10 * context)
9379 +/* REVISIT: fill in other SMS registers here */
9380 +
9381 +
9382 +#ifndef __ASSEMBLER__
9383 +
9384 +/**
9385 + * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
9386 + * @rate: SDRC clock rate (in Hz)
9387 + * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
9388 + * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
9389 + * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
9390 + * @mr: Value to program to SDRC_MR for this rate
9391 + *
9392 + * This structure holds a pre-computed set of register values for the
9393 + * SDRC for a given SDRC clock rate and SDRAM chip. These are
9394 + * intended to be pre-computed and specified in an array in the board-*.c
9395 + * files. The structure is keyed off the 'rate' field.
9396 + */
9397 +struct omap_sdrc_params {
9398 + unsigned long rate;
9399 + u32 actim_ctrla;
9400 + u32 actim_ctrlb;
9401 + u32 rfr_ctrl;
9402 + u32 mr;
9403 +};
9404 +
9405 +void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
9406 + struct omap_sdrc_params *sdrc_cs1);
9407 +int omap2_sdrc_get_params(unsigned long r,
9408 + struct omap_sdrc_params **sdrc_cs0,
9409 + struct omap_sdrc_params **sdrc_cs1);
9410 +void omap2_sms_save_context(void);
9411 +void omap2_sms_restore_context(void);
9412 +
9413 +void omap2_sms_write_rot_control(u32 val, unsigned ctx);
9414 +void omap2_sms_write_rot_size(u32 val, unsigned ctx);
9415 +void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx);
9416 +
9417 +#ifdef CONFIG_ARCH_OMAP2
9418 +
9419 +struct memory_timings {
9420 + u32 m_type; /* ddr = 1, sdr = 0 */
9421 + u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
9422 + u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
9423 + u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
9424 + u32 base_cs; /* base chip select to use for calculations */
9425 +};
9426 +
9427 +extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
9428 +
9429 +u32 omap2xxx_sdrc_dll_is_unlocked(void);
9430 +u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
9431 +
9432 +#endif /* CONFIG_ARCH_OMAP2 */
9433 +
9434 +#endif /* __ASSEMBLER__ */
9435 +
9436 +#endif
9437 --- /dev/null
9438 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/serial.h
9439 @@ -0,0 +1,65 @@
9440 +/*
9441 + * arch/arm/plat-omap/include/mach/serial.h
9442 + *
9443 + * Copyright (C) 2009 Texas Instruments
9444 + * Addded OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
9445 + *
9446 + * This program is distributed in the hope that it will be useful,
9447 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
9448 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9449 + * GNU General Public License for more details.
9450 + */
9451 +
9452 +#ifndef __ASM_ARCH_SERIAL_H
9453 +#define __ASM_ARCH_SERIAL_H
9454 +
9455 +#include <linux/init.h>
9456 +
9457 +#if defined(CONFIG_ARCH_OMAP1)
9458 +/* OMAP1 serial ports */
9459 +#define OMAP_UART1_BASE 0xfffb0000
9460 +#define OMAP_UART2_BASE 0xfffb0800
9461 +#define OMAP_UART3_BASE 0xfffb9800
9462 +#elif defined(CONFIG_ARCH_OMAP2)
9463 +/* OMAP2 serial ports */
9464 +#define OMAP_UART1_BASE 0x4806a000
9465 +#define OMAP_UART2_BASE 0x4806c000
9466 +#define OMAP_UART3_BASE 0x4806e000
9467 +#elif defined(CONFIG_ARCH_OMAP3)
9468 +/* OMAP3 serial ports */
9469 +#define OMAP_UART1_BASE 0x4806a000
9470 +#define OMAP_UART2_BASE 0x4806c000
9471 +#define OMAP_UART3_BASE 0x49020000
9472 +#elif defined(CONFIG_ARCH_OMAP4)
9473 +/* OMAP4 serial ports */
9474 +#define OMAP_UART1_BASE 0x4806a000
9475 +#define OMAP_UART2_BASE 0x4806c000
9476 +#define OMAP_UART3_BASE 0x48020000
9477 +#define OMAP_UART4_BASE 0x4806e000
9478 +#endif
9479 +
9480 +#define OMAP1510_BASE_BAUD (12000000/16)
9481 +#define OMAP16XX_BASE_BAUD (48000000/16)
9482 +#define OMAP24XX_BASE_BAUD (48000000/16)
9483 +
9484 +#define is_omap_port(pt) ({int __ret = 0; \
9485 + if ((pt)->port.mapbase == OMAP_UART1_BASE || \
9486 + (pt)->port.mapbase == OMAP_UART2_BASE || \
9487 + (pt)->port.mapbase == OMAP_UART3_BASE) \
9488 + __ret = 1; \
9489 + __ret; \
9490 + })
9491 +
9492 +#ifndef __ASSEMBLER__
9493 +extern void __init omap_serial_early_init(void);
9494 +extern void omap_serial_init(void);
9495 +extern void omap_serial_init_port(int port);
9496 +extern int omap_uart_can_sleep(void);
9497 +extern void omap_uart_check_wakeup(void);
9498 +extern void omap_uart_prepare_suspend(void);
9499 +extern void omap_uart_prepare_idle(int num);
9500 +extern void omap_uart_resume_idle(int num);
9501 +extern void omap_uart_enable_irqs(int enable);
9502 +#endif
9503 +
9504 +#endif
9505 --- /dev/null
9506 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/smp.h
9507 @@ -0,0 +1,53 @@
9508 +/*
9509 + * OMAP4 machine specific smp.h
9510 + *
9511 + * Copyright (C) 2009 Texas Instruments, Inc.
9512 + *
9513 + * Author:
9514 + * Santosh Shilimkar <santosh.shilimkar@ti.com>
9515 + *
9516 + * Interface functions needed for the SMP. This file is based on arm
9517 + * realview smp platform.
9518 + * Copyright (c) 2003 ARM Limited.
9519 + *
9520 + * This program is free software; you can redistribute it and/or modify
9521 + * it under the terms of the GNU General Public License version 2 as
9522 + * published by the Free Software Foundation.
9523 + */
9524 +#ifndef OMAP_ARCH_SMP_H
9525 +#define OMAP_ARCH_SMP_H
9526 +
9527 +#include <asm/hardware/gic.h>
9528 +
9529 +/*
9530 + * set_event() is used to wake up secondary core from wfe using sev. ROM
9531 + * code puts the second core into wfe(standby).
9532 + *
9533 + */
9534 +#define set_event() __asm__ __volatile__ ("sev" : : : "memory")
9535 +
9536 +/* Needed for secondary core boot */
9537 +extern void omap_secondary_startup(void);
9538 +extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
9539 +extern void omap_auxcoreboot_addr(u32 cpu_addr);
9540 +
9541 +/*
9542 + * We use Soft IRQ1 as the IPI
9543 + */
9544 +static inline void smp_cross_call(const struct cpumask *mask)
9545 +{
9546 + gic_raise_softirq(mask, 1);
9547 +}
9548 +
9549 +/*
9550 + * Read MPIDR: Multiprocessor affinity register
9551 + */
9552 +#define hard_smp_processor_id() \
9553 + ({ \
9554 + unsigned int cpunum; \
9555 + __asm__("mrc p15, 0, %0, c0, c0, 5" \
9556 + : "=r" (cpunum)); \
9557 + cpunum &= 0x0F; \
9558 + })
9559 +
9560 +#endif
9561 --- /dev/null
9562 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/sram.h
9563 @@ -0,0 +1,78 @@
9564 +/*
9565 + * arch/arm/plat-omap/include/mach/sram.h
9566 + *
9567 + * Interface for functions that need to be run in internal SRAM
9568 + *
9569 + * This program is free software; you can redistribute it and/or modify
9570 + * it under the terms of the GNU General Public License version 2 as
9571 + * published by the Free Software Foundation.
9572 + */
9573 +
9574 +#ifndef __ARCH_ARM_OMAP_SRAM_H
9575 +#define __ARCH_ARM_OMAP_SRAM_H
9576 +
9577 +extern int __init omap_sram_init(void);
9578 +extern void * omap_sram_push(void * start, unsigned long size);
9579 +extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
9580 +
9581 +extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
9582 + u32 base_cs, u32 force_unlock);
9583 +extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
9584 + u32 mem_type);
9585 +extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
9586 +
9587 +extern u32 omap3_configure_core_dpll(
9588 + u32 m2, u32 unlock_dll, u32 f, u32 inc,
9589 + u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
9590 + u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
9591 + u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
9592 + u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
9593 +extern void omap3_sram_restore_context(void);
9594 +
9595 +/* Do not use these */
9596 +extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
9597 +extern unsigned long omap1_sram_reprogram_clock_sz;
9598 +
9599 +extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
9600 +extern unsigned long omap24xx_sram_reprogram_clock_sz;
9601 +
9602 +extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
9603 + u32 base_cs, u32 force_unlock);
9604 +extern unsigned long omap242x_sram_ddr_init_sz;
9605 +
9606 +extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
9607 + int bypass);
9608 +extern unsigned long omap242x_sram_set_prcm_sz;
9609 +
9610 +extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
9611 + u32 mem_type);
9612 +extern unsigned long omap242x_sram_reprogram_sdrc_sz;
9613 +
9614 +
9615 +extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
9616 + u32 base_cs, u32 force_unlock);
9617 +extern unsigned long omap243x_sram_ddr_init_sz;
9618 +
9619 +extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
9620 + int bypass);
9621 +extern unsigned long omap243x_sram_set_prcm_sz;
9622 +
9623 +extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
9624 + u32 mem_type);
9625 +extern unsigned long omap243x_sram_reprogram_sdrc_sz;
9626 +
9627 +extern u32 omap3_sram_configure_core_dpll(
9628 + u32 m2, u32 unlock_dll, u32 f, u32 inc,
9629 + u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
9630 + u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
9631 + u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
9632 + u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
9633 +extern unsigned long omap3_sram_configure_core_dpll_sz;
9634 +
9635 +#ifdef CONFIG_PM
9636 +extern void omap_push_sram_idle(void);
9637 +#else
9638 +static inline void omap_push_sram_idle(void) {}
9639 +#endif /* CONFIG_PM */
9640 +
9641 +#endif
9642 --- /dev/null
9643 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/system.h
9644 @@ -0,0 +1,51 @@
9645 +/*
9646 + * Copied from arch/arm/mach-sa1100/include/mach/system.h
9647 + * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
9648 + */
9649 +#ifndef __ASM_ARCH_SYSTEM_H
9650 +#define __ASM_ARCH_SYSTEM_H
9651 +#include <linux/clk.h>
9652 +
9653 +#include <asm/mach-types.h>
9654 +#include <mach/hardware.h>
9655 +
9656 +#include <plat/prcm.h>
9657 +
9658 +#ifndef CONFIG_MACH_VOICEBLUE
9659 +#define voiceblue_reset() do {} while (0)
9660 +#else
9661 +extern void voiceblue_reset(void);
9662 +#endif
9663 +
9664 +static inline void arch_idle(void)
9665 +{
9666 + cpu_do_idle();
9667 +}
9668 +
9669 +static inline void omap1_arch_reset(char mode)
9670 +{
9671 + /*
9672 + * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
9673 + * "Global Software Reset Affects Traffic Controller Frequency".
9674 + */
9675 + if (cpu_is_omap5912()) {
9676 + omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
9677 + DPLL_CTL);
9678 + omap_writew(0x8, ARM_RSTCT1);
9679 + }
9680 +
9681 + if (machine_is_voiceblue())
9682 + voiceblue_reset();
9683 + else
9684 + omap_writew(1, ARM_RSTCT1);
9685 +}
9686 +
9687 +static inline void arch_reset(char mode, const char *cmd)
9688 +{
9689 + if (!cpu_class_is_omap2())
9690 + omap1_arch_reset(mode);
9691 + else
9692 + omap_prcm_arch_reset(mode);
9693 +}
9694 +
9695 +#endif
9696 --- /dev/null
9697 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/tc.h
9698 @@ -0,0 +1,106 @@
9699 +/*
9700 + * arch/arm/plat-omap/include/mach/tc.h
9701 + *
9702 + * OMAP Traffic Controller
9703 + *
9704 + * Copyright (C) 2004 Nokia Corporation
9705 + * Author: Imre Deak <imre.deak@nokia.com>
9706 + *
9707 + * This program is free software; you can redistribute it and/or modify it
9708 + * under the terms of the GNU General Public License as published by the
9709 + * Free Software Foundation; either version 2 of the License, or (at your
9710 + * option) any later version.
9711 + *
9712 + * This program is distributed in the hope that it will be useful, but
9713 + * WITHOUT ANY WARRANTY; without even the implied warranty of
9714 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
9715 + * General Public License for more details.
9716 + *
9717 + * You should have received a copy of the GNU General Public License along
9718 + * with this program; if not, write to the Free Software Foundation, Inc.,
9719 + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
9720 + */
9721 +
9722 +#ifndef __ASM_ARCH_TC_H
9723 +#define __ASM_ARCH_TC_H
9724 +
9725 +#define TCMIF_BASE 0xfffecc00
9726 +#define OMAP_TC_OCPT1_PRIOR (TCMIF_BASE + 0x00)
9727 +#define OMAP_TC_EMIFS_PRIOR (TCMIF_BASE + 0x04)
9728 +#define OMAP_TC_EMIFF_PRIOR (TCMIF_BASE + 0x08)
9729 +#define EMIFS_CONFIG (TCMIF_BASE + 0x0c)
9730 +#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10)
9731 +#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14)
9732 +#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18)
9733 +#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c)
9734 +#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20)
9735 +#define EMIFF_MRS (TCMIF_BASE + 0x24)
9736 +#define TC_TIMEOUT1 (TCMIF_BASE + 0x28)
9737 +#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c)
9738 +#define TC_TIMEOUT3 (TCMIF_BASE + 0x30)
9739 +#define TC_ENDIANISM (TCMIF_BASE + 0x34)
9740 +#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c)
9741 +#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40)
9742 +#define EMIFS_ACS0 (TCMIF_BASE + 0x50)
9743 +#define EMIFS_ACS1 (TCMIF_BASE + 0x54)
9744 +#define EMIFS_ACS2 (TCMIF_BASE + 0x58)
9745 +#define EMIFS_ACS3 (TCMIF_BASE + 0x5c)
9746 +#define OMAP_TC_OCPT2_PRIOR (TCMIF_BASE + 0xd0)
9747 +
9748 +/* external EMIFS chipselect regions */
9749 +#define OMAP_CS0_PHYS 0x00000000
9750 +#define OMAP_CS0_SIZE SZ_64M
9751 +
9752 +#define OMAP_CS1_PHYS 0x04000000
9753 +#define OMAP_CS1_SIZE SZ_64M
9754 +
9755 +#define OMAP_CS1A_PHYS OMAP_CS1_PHYS
9756 +#define OMAP_CS1A_SIZE SZ_32M
9757 +
9758 +#define OMAP_CS1B_PHYS (OMAP_CS1A_PHYS + OMAP_CS1A_SIZE)
9759 +#define OMAP_CS1B_SIZE SZ_32M
9760 +
9761 +#define OMAP_CS2_PHYS 0x08000000
9762 +#define OMAP_CS2_SIZE SZ_64M
9763 +
9764 +#define OMAP_CS2A_PHYS OMAP_CS2_PHYS
9765 +#define OMAP_CS2A_SIZE SZ_32M
9766 +
9767 +#define OMAP_CS2B_PHYS (OMAP_CS2A_PHYS + OMAP_CS2A_SIZE)
9768 +#define OMAP_CS2B_SIZE SZ_32M
9769 +
9770 +#define OMAP_CS3_PHYS 0x0c000000
9771 +#define OMAP_CS3_SIZE SZ_64M
9772 +
9773 +#ifndef __ASSEMBLER__
9774 +
9775 +/* EMIF Slow Interface Configuration Register */
9776 +#define OMAP_EMIFS_CONFIG_FR (1 << 4)
9777 +#define OMAP_EMIFS_CONFIG_PDE (1 << 3)
9778 +#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2)
9779 +#define OMAP_EMIFS_CONFIG_BM (1 << 1)
9780 +#define OMAP_EMIFS_CONFIG_WP (1 << 0)
9781 +
9782 +#define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n)))
9783 +#define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n)))
9784 +
9785 +/* Almost all documentation for chip and board memory maps assumes
9786 + * BM is clear. Most devel boards have a switch to control booting
9787 + * from NOR flash (using external chipselect 3) rather than mask ROM,
9788 + * which uses BM to interchange the physical CS0 and CS3 addresses.
9789 + */
9790 +static inline u32 omap_cs0_phys(void)
9791 +{
9792 + return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
9793 + ? OMAP_CS3_PHYS : 0;
9794 +}
9795 +
9796 +static inline u32 omap_cs3_phys(void)
9797 +{
9798 + return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
9799 + ? 0 : OMAP_CS3_PHYS;
9800 +}
9801 +
9802 +#endif /* __ASSEMBLER__ */
9803 +
9804 +#endif /* __ASM_ARCH_TC_H */
9805 --- /dev/null
9806 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/timer-gp.h
9807 @@ -0,0 +1,17 @@
9808 +/*
9809 + * OMAP2/3 GPTIMER support.headers
9810 + *
9811 + * Copyright (C) 2009 Nokia Corporation
9812 + *
9813 + * This file is subject to the terms and conditions of the GNU General Public
9814 + * License. See the file "COPYING" in the main directory of this archive
9815 + * for more details.
9816 + */
9817 +
9818 +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
9819 +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
9820 +
9821 +int __init omap2_gp_clockevent_set_gptimer(u8 id);
9822 +
9823 +#endif
9824 +
9825 --- /dev/null
9826 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/timex.h
9827 @@ -0,0 +1,41 @@
9828 +/*
9829 + * arch/arm/plat-omap/include/mach/timex.h
9830 + *
9831 + * Copyright (C) 2000 RidgeRun, Inc.
9832 + * Author: Greg Lonnon <glonnon@ridgerun.com>
9833 + *
9834 + * This program is free software; you can redistribute it and/or modify it
9835 + * under the terms of the GNU General Public License as published by the
9836 + * Free Software Foundation; either version 2 of the License, or (at your
9837 + * option) any later version.
9838 + *
9839 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9840 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9841 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9842 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9843 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9844 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9845 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9846 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9847 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9848 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9849 + *
9850 + * You should have received a copy of the GNU General Public License along
9851 + * with this program; if not, write to the Free Software Foundation, Inc.,
9852 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9853 + */
9854 +
9855 +#if !defined(__ASM_ARCH_OMAP_TIMEX_H)
9856 +#define __ASM_ARCH_OMAP_TIMEX_H
9857 +
9858 +/*
9859 + * OMAP 32KHz timer updates time one jiffie at a time from a secondary timer,
9860 + * and that's why the CLOCK_TICK_RATE is not 32768.
9861 + */
9862 +#ifdef CONFIG_OMAP_32K_TIMER
9863 +#define CLOCK_TICK_RATE (CONFIG_OMAP_32K_TIMER_HZ)
9864 +#else
9865 +#define CLOCK_TICK_RATE (HZ * 100000UL)
9866 +#endif
9867 +
9868 +#endif /* __ASM_ARCH_OMAP_TIMEX_H */
9869 --- /dev/null
9870 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/uncompress.h
9871 @@ -0,0 +1,88 @@
9872 +/*
9873 + * arch/arm/plat-omap/include/mach/uncompress.h
9874 + *
9875 + * Serial port stubs for kernel decompress status messages
9876 + *
9877 + * Initially based on:
9878 + * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
9879 + * Copyright (C) 2000 RidgeRun, Inc.
9880 + * Author: Greg Lonnon <glonnon@ridgerun.com>
9881 + *
9882 + * Rewritten by:
9883 + * Author: <source@mvista.com>
9884 + * 2004 (c) MontaVista Software, Inc.
9885 + *
9886 + * This file is licensed under the terms of the GNU General Public License
9887 + * version 2. This program is licensed "as is" without any warranty of any
9888 + * kind, whether express or implied.
9889 + */
9890 +
9891 +#include <linux/types.h>
9892 +#include <linux/serial_reg.h>
9893 +#include <plat/serial.h>
9894 +
9895 +unsigned int system_rev;
9896 +
9897 +#define UART_OMAP_MDR1 0x08 /* mode definition register */
9898 +#define OMAP_ID_730 0x355F
9899 +#define OMAP_ID_850 0x362C
9900 +#define ID_MASK 0x7fff
9901 +#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
9902 +#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
9903 +
9904 +static void putc(int c)
9905 +{
9906 + volatile u8 * uart = 0;
9907 + int shift = 2;
9908 +
9909 +#ifdef CONFIG_MACH_OMAP_PALMTE
9910 + return;
9911 +#endif
9912 +
9913 +#ifdef CONFIG_ARCH_OMAP
9914 +#ifdef CONFIG_OMAP_LL_DEBUG_UART3
9915 + uart = (volatile u8 *)(OMAP_UART3_BASE);
9916 +#elif defined(CONFIG_OMAP_LL_DEBUG_UART2)
9917 + uart = (volatile u8 *)(OMAP_UART2_BASE);
9918 +#elif defined(CONFIG_OMAP_LL_DEBUG_UART1)
9919 + uart = (volatile u8 *)(OMAP_UART1_BASE);
9920 +#elif defined(CONFIG_OMAP_LL_DEBUG_NONE)
9921 + return;
9922 +#else
9923 + return;
9924 +#endif
9925 +
9926 +#ifdef CONFIG_ARCH_OMAP1
9927 + /* Determine which serial port to use */
9928 + do {
9929 + /* MMU is not on, so cpu_is_omapXXXX() won't work here */
9930 + unsigned int omap_id = omap_get_id();
9931 +
9932 + if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850)
9933 + shift = 0;
9934 +
9935 + if (check_port(uart, shift))
9936 + break;
9937 + /* Silent boot if no serial ports are enabled. */
9938 + return;
9939 + } while (0);
9940 +#endif /* CONFIG_ARCH_OMAP1 */
9941 +#endif
9942 +
9943 + /*
9944 + * Now, xmit each character
9945 + */
9946 + while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
9947 + barrier();
9948 + uart[UART_TX << shift] = c;
9949 +}
9950 +
9951 +static inline void flush(void)
9952 +{
9953 +}
9954 +
9955 +/*
9956 + * nothing to do
9957 + */
9958 +#define arch_decomp_setup()
9959 +#define arch_decomp_wdog()
9960 --- /dev/null
9961 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/usb.h
9962 @@ -0,0 +1,162 @@
9963 +// include/asm-arm/mach-omap/usb.h
9964 +
9965 +#ifndef __ASM_ARCH_OMAP_USB_H
9966 +#define __ASM_ARCH_OMAP_USB_H
9967 +
9968 +#include <plat/board.h>
9969 +
9970 +#define OMAP3_HS_USB_PORTS 3
9971 +enum ehci_hcd_omap_mode {
9972 + EHCI_HCD_OMAP_MODE_UNKNOWN,
9973 + EHCI_HCD_OMAP_MODE_PHY,
9974 + EHCI_HCD_OMAP_MODE_TLL,
9975 +};
9976 +
9977 +struct ehci_hcd_omap_platform_data {
9978 + enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS];
9979 + unsigned phy_reset:1;
9980 +
9981 + /* have to be valid if phy_reset is true and portx is in phy mode */
9982 + int reset_gpio_port[OMAP3_HS_USB_PORTS];
9983 +};
9984 +
9985 +/*-------------------------------------------------------------------------*/
9986 +
9987 +#define OMAP1_OTG_BASE 0xfffb0400
9988 +#define OMAP1_UDC_BASE 0xfffb4000
9989 +#define OMAP1_OHCI_BASE 0xfffba000
9990 +
9991 +#define OMAP2_OHCI_BASE 0x4805e000
9992 +#define OMAP2_UDC_BASE 0x4805e200
9993 +#define OMAP2_OTG_BASE 0x4805e300
9994 +
9995 +#ifdef CONFIG_ARCH_OMAP1
9996 +
9997 +#define OTG_BASE OMAP1_OTG_BASE
9998 +#define UDC_BASE OMAP1_UDC_BASE
9999 +#define OMAP_OHCI_BASE OMAP1_OHCI_BASE
10000 +
10001 +#else
10002 +
10003 +#define OTG_BASE OMAP2_OTG_BASE
10004 +#define UDC_BASE OMAP2_UDC_BASE
10005 +#define OMAP_OHCI_BASE OMAP2_OHCI_BASE
10006 +
10007 +extern void usb_musb_init(void);
10008 +
10009 +extern void usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata);
10010 +
10011 +#endif
10012 +
10013 +void omap_usb_init(struct omap_usb_config *pdata);
10014 +
10015 +/*-------------------------------------------------------------------------*/
10016 +
10017 +/*
10018 + * OTG and transceiver registers, for OMAPs starting with ARM926
10019 + */
10020 +#define OTG_REV (OTG_BASE + 0x00)
10021 +#define OTG_SYSCON_1 (OTG_BASE + 0x04)
10022 +# define USB2_TRX_MODE(w) (((w)>>24)&0x07)
10023 +# define USB1_TRX_MODE(w) (((w)>>20)&0x07)
10024 +# define USB0_TRX_MODE(w) (((w)>>16)&0x07)
10025 +# define OTG_IDLE_EN (1 << 15)
10026 +# define HST_IDLE_EN (1 << 14)
10027 +# define DEV_IDLE_EN (1 << 13)
10028 +# define OTG_RESET_DONE (1 << 2)
10029 +# define OTG_SOFT_RESET (1 << 1)
10030 +#define OTG_SYSCON_2 (OTG_BASE + 0x08)
10031 +# define OTG_EN (1 << 31)
10032 +# define USBX_SYNCHRO (1 << 30)
10033 +# define OTG_MST16 (1 << 29)
10034 +# define SRP_GPDATA (1 << 28)
10035 +# define SRP_GPDVBUS (1 << 27)
10036 +# define SRP_GPUVBUS(w) (((w)>>24)&0x07)
10037 +# define A_WAIT_VRISE(w) (((w)>>20)&0x07)
10038 +# define B_ASE_BRST(w) (((w)>>16)&0x07)
10039 +# define SRP_DPW (1 << 14)
10040 +# define SRP_DATA (1 << 13)
10041 +# define SRP_VBUS (1 << 12)
10042 +# define OTG_PADEN (1 << 10)
10043 +# define HMC_PADEN (1 << 9)
10044 +# define UHOST_EN (1 << 8)
10045 +# define HMC_TLLSPEED (1 << 7)
10046 +# define HMC_TLLATTACH (1 << 6)
10047 +# define OTG_HMC(w) (((w)>>0)&0x3f)
10048 +#define OTG_CTRL (OTG_BASE + 0x0c)
10049 +# define OTG_USB2_EN (1 << 29)
10050 +# define OTG_USB2_DP (1 << 28)
10051 +# define OTG_USB2_DM (1 << 27)
10052 +# define OTG_USB1_EN (1 << 26)
10053 +# define OTG_USB1_DP (1 << 25)
10054 +# define OTG_USB1_DM (1 << 24)
10055 +# define OTG_USB0_EN (1 << 23)
10056 +# define OTG_USB0_DP (1 << 22)
10057 +# define OTG_USB0_DM (1 << 21)
10058 +# define OTG_ASESSVLD (1 << 20)
10059 +# define OTG_BSESSEND (1 << 19)
10060 +# define OTG_BSESSVLD (1 << 18)
10061 +# define OTG_VBUSVLD (1 << 17)
10062 +# define OTG_ID (1 << 16)
10063 +# define OTG_DRIVER_SEL (1 << 15)
10064 +# define OTG_A_SETB_HNPEN (1 << 12)
10065 +# define OTG_A_BUSREQ (1 << 11)
10066 +# define OTG_B_HNPEN (1 << 9)
10067 +# define OTG_B_BUSREQ (1 << 8)
10068 +# define OTG_BUSDROP (1 << 7)
10069 +# define OTG_PULLDOWN (1 << 5)
10070 +# define OTG_PULLUP (1 << 4)
10071 +# define OTG_DRV_VBUS (1 << 3)
10072 +# define OTG_PD_VBUS (1 << 2)
10073 +# define OTG_PU_VBUS (1 << 1)
10074 +# define OTG_PU_ID (1 << 0)
10075 +#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
10076 +# define DRIVER_SWITCH (1 << 15)
10077 +# define A_VBUS_ERR (1 << 13)
10078 +# define A_REQ_TMROUT (1 << 12)
10079 +# define A_SRP_DETECT (1 << 11)
10080 +# define B_HNP_FAIL (1 << 10)
10081 +# define B_SRP_TMROUT (1 << 9)
10082 +# define B_SRP_DONE (1 << 8)
10083 +# define B_SRP_STARTED (1 << 7)
10084 +# define OPRT_CHG (1 << 0)
10085 +#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
10086 + // same bits as in IRQ_EN
10087 +#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
10088 +# define OTGVPD (1 << 14)
10089 +# define OTGVPU (1 << 13)
10090 +# define OTGPUID (1 << 12)
10091 +# define USB2VDR (1 << 10)
10092 +# define USB2PDEN (1 << 9)
10093 +# define USB2PUEN (1 << 8)
10094 +# define USB1VDR (1 << 6)
10095 +# define USB1PDEN (1 << 5)
10096 +# define USB1PUEN (1 << 4)
10097 +# define USB0VDR (1 << 2)
10098 +# define USB0PDEN (1 << 1)
10099 +# define USB0PUEN (1 << 0)
10100 +#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
10101 +#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
10102 +
10103 +/*-------------------------------------------------------------------------*/
10104 +
10105 +/* OMAP1 */
10106 +#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
10107 +# define CONF_USB2_UNI_R (1 << 8)
10108 +# define CONF_USB1_UNI_R (1 << 7)
10109 +# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
10110 +# define CONF_USB0_ISOLATE_R (1 << 3)
10111 +# define CONF_USB_PWRDN_DM_R (1 << 2)
10112 +# define CONF_USB_PWRDN_DP_R (1 << 1)
10113 +
10114 +/* OMAP2 */
10115 +# define USB_UNIDIR 0x0
10116 +# define USB_UNIDIR_TLL 0x1
10117 +# define USB_BIDIR 0x2
10118 +# define USB_BIDIR_TLL 0x3
10119 +# define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2)))
10120 +# define USBT2TLL5PI (1 << 17)
10121 +# define USB0PUENACTLOI (1 << 16)
10122 +# define USBSTANDBYCTRL (1 << 15)
10123 +
10124 +#endif /* __ASM_ARCH_OMAP_USB_H */
10125 --- /dev/null
10126 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/vram.h
10127 @@ -0,0 +1,62 @@
10128 +/*
10129 + * VRAM manager for OMAP
10130 + *
10131 + * Copyright (C) 2009 Nokia Corporation
10132 + * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
10133 + *
10134 + * This program is free software; you can redistribute it and/or modify
10135 + * it under the terms of the GNU General Public License version 2 as
10136 + * published by the Free Software Foundation.
10137 + *
10138 + * This program is distributed in the hope that it will be useful, but
10139 + * WITHOUT ANY WARRANTY; without even the implied warranty of
10140 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
10141 + * General Public License for more details.
10142 + *
10143 + * You should have received a copy of the GNU General Public License along
10144 + * with this program; if not, write to the Free Software Foundation, Inc.,
10145 + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
10146 + */
10147 +
10148 +#ifndef __OMAP_VRAM_H__
10149 +#define __OMAP_VRAM_H__
10150 +
10151 +#include <linux/types.h>
10152 +
10153 +#define OMAP_VRAM_MEMTYPE_SDRAM 0
10154 +#define OMAP_VRAM_MEMTYPE_SRAM 1
10155 +#define OMAP_VRAM_MEMTYPE_MAX 1
10156 +
10157 +extern int omap_vram_add_region(unsigned long paddr, size_t size);
10158 +extern int omap_vram_free(unsigned long paddr, size_t size);
10159 +extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr);
10160 +extern int omap_vram_reserve(unsigned long paddr, size_t size);
10161 +extern void omap_vram_get_info(unsigned long *vram, unsigned long *free_vram,
10162 + unsigned long *largest_free_block);
10163 +
10164 +#ifdef CONFIG_OMAP2_VRAM
10165 +extern void omap_vram_set_sdram_vram(u32 size, u32 start);
10166 +extern void omap_vram_set_sram_vram(u32 size, u32 start);
10167 +
10168 +extern void omap_vram_reserve_sdram(void);
10169 +extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
10170 + unsigned long sram_vstart,
10171 + unsigned long sram_size,
10172 + unsigned long pstart_avail,
10173 + unsigned long size_avail);
10174 +#else
10175 +static inline void omap_vram_set_sdram_vram(u32 size, u32 start) { }
10176 +static inline void omap_vram_set_sram_vram(u32 size, u32 start) { }
10177 +
10178 +static inline void omap_vram_reserve_sdram(void) { }
10179 +static inline unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
10180 + unsigned long sram_vstart,
10181 + unsigned long sram_size,
10182 + unsigned long pstart_avail,
10183 + unsigned long size_avail)
10184 +{
10185 + return 0;
10186 +}
10187 +#endif
10188 +
10189 +#endif
10190 --- /dev/null
10191 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/vrfb.h
10192 @@ -0,0 +1,50 @@
10193 +/*
10194 + * VRFB Rotation Engine
10195 + *
10196 + * Copyright (C) 2009 Nokia Corporation
10197 + * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
10198 + *
10199 + * This program is free software; you can redistribute it and/or modify
10200 + * it under the terms of the GNU General Public License version 2 as
10201 + * published by the Free Software Foundation.
10202 + *
10203 + * This program is distributed in the hope that it will be useful, but
10204 + * WITHOUT ANY WARRANTY; without even the implied warranty of
10205 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
10206 + * General Public License for more details.
10207 + *
10208 + * You should have received a copy of the GNU General Public License along
10209 + * with this program; if not, write to the Free Software Foundation, Inc.,
10210 + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
10211 + */
10212 +
10213 +#ifndef __OMAP_VRFB_H__
10214 +#define __OMAP_VRFB_H__
10215 +
10216 +#define OMAP_VRFB_LINE_LEN 2048
10217 +
10218 +struct vrfb {
10219 + u8 context;
10220 + void __iomem *vaddr[4];
10221 + unsigned long paddr[4];
10222 + u16 xres;
10223 + u16 yres;
10224 + u16 xoffset;
10225 + u16 yoffset;
10226 + u8 bytespp;
10227 + bool yuv_mode;
10228 +};
10229 +
10230 +extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
10231 +extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
10232 +extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
10233 + u8 bytespp);
10234 +extern u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp);
10235 +extern u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp);
10236 +extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
10237 + u16 width, u16 height,
10238 + unsigned bytespp, bool yuv_mode);
10239 +extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot);
10240 +extern void omap_vrfb_restore_context(void);
10241 +
10242 +#endif /* __VRFB_H */
10243 --- /dev/null
10244 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/plat/cbus.h
10245 @@ -0,0 +1,31 @@
10246 +/*
10247 + * cbus.h - CBUS platform_data definition
10248 + *
10249 + * Copyright (C) 2004 - 2009 Nokia Corporation
10250 + *
10251 + * Written by Felipe Balbi <felipe.balbi@nokia.com>
10252 + *
10253 + * This file is subject to the terms and conditions of the GNU General
10254 + * Public License. See the file "COPYING" in the main directory of this
10255 + * archive for more details.
10256 + *
10257 + * This program is distributed in the hope that it will be useful,
10258 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
10259 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10260 + * GNU General Public License for more details.
10261 + *
10262 + * You should have received a copy of the GNU General Public License
10263 + * along with this program; if not, write to the Free Software
10264 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
10265 + */
10266 +
10267 +#ifndef __PLAT_CBUS_H
10268 +#define __PLAT_CBUS_H
10269 +
10270 +struct cbus_host_platform_data {
10271 + int dat_gpio;
10272 + int clk_gpio;
10273 + int sel_gpio;
10274 +};
10275 +
10276 +#endif /* __PLAT_CBUS_H */
10277 --- linux-2.6.36-rc4.orig/arch/arm/plat-omap/Kconfig
10278 +++ linux-2.6.36-rc4/arch/arm/plat-omap/Kconfig
10279 @@ -47,6 +47,30 @@ config OMAP_RESET_CLOCKS
10280 probably do not want this option enabled until your
10281 device drivers work properly.
10282
10283 +config OMAP_BOOT_TAG
10284 + bool "OMAP bootloader information passing"
10285 + depends on ARCH_OMAP
10286 + default n
10287 + help
10288 + Say Y, if you have a bootloader which passes information
10289 + about your board and its peripheral configuration.
10290 +
10291 +config OMAP_BOOT_REASON
10292 + bool "Support for boot reason"
10293 + depends on OMAP_BOOT_TAG
10294 + default n
10295 + help
10296 + Say Y, if you want to have a procfs entry for reading the boot
10297 + reason in user-space.
10298 +
10299 +config OMAP_COMPONENT_VERSION
10300 + bool "Support for component version display"
10301 + depends on OMAP_BOOT_TAG && PROC_FS
10302 + default n
10303 + help
10304 + Say Y, if you want to have a procfs entry for reading component
10305 + versions (supplied by the bootloader) in user-space.
10306 +
10307 config OMAP_MUX
10308 bool "OMAP multiplexing support"
10309 depends on ARCH_OMAP
10310 --- linux-2.6.36-rc4.orig/arch/arm/plat-omap/Makefile
10311 +++ linux-2.6.36-rc4/arch/arm/plat-omap/Makefile
10312 @@ -23,6 +23,8 @@ obj-$(CONFIG_OMAP_IOMMU_DEBUG) += iommu-
10313
10314 obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
10315 obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
10316 +obj-$(CONFIG_OMAP_BOOT_REASON) += bootreason.o
10317 +obj-$(CONFIG_OMAP_COMPONENT_VERSION) += component-version.o
10318 obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
10319 obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
10320 i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
10321 --- linux-2.6.36-rc4.orig/arch/arm/include/asm/setup.h
10322 +++ linux-2.6.36-rc4/arch/arm/include/asm/setup.h
10323 @@ -136,6 +136,13 @@ struct tag_acorn {
10324 __u8 adfsdrives;
10325 };
10326
10327 +/* TI OMAP specific information */
10328 +#define ATAG_BOARD 0x414f4d50
10329 +
10330 +struct tag_omap {
10331 + u8 data[0];
10332 +};
10333 +
10334 /* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */
10335 #define ATAG_MEMCLK 0x41000402
10336
10337 @@ -162,6 +169,11 @@ struct tag {
10338 struct tag_acorn acorn;
10339
10340 /*
10341 + * OMAP specific
10342 + */
10343 + struct tag_omap omap;
10344 +
10345 + /*
10346 * DC21285 specific
10347 */
10348 struct tag_memclk memclk;
Personal OpenWRT clone
This page took 0.493163 seconds and 5 git commands to generate.