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[ar71xx] add AR913x specific GPIO function bit definitions
[openwrt.git] / target / linux / ps3 / patches-2.6.28 / 0007-mtd-ps3vram-Add-ps3vram-driver-for-accessing-video.patch
1 From cffb4add03b1fc83026b06dc3664279cfbf70155 Mon Sep 17 00:00:00 2001
2 From: Jim Paris <jim@jtan.com>
3 Date: Tue, 6 Jan 2009 11:32:10 +0000
4 Subject: [PATCH] mtd/ps3vram: Add ps3vram driver for accessing video RAM as MTD
5
6 Add ps3vram driver, which exposes unused video RAM on the PS3 as a MTD
7 device suitable for storage or swap. Fast data transfer is achieved
8 using a local cache in system RAM and DMA transfers via the GPU.
9
10 Signed-off-by: Vivien Chappelier <vivien.chappelier@free.fr>
11 Signed-off-by: Jim Paris <jim@jtan.com>
12 Acked-by: Geoff Levand <geoffrey.levand@am.sony.com>
13 Acked-by: David Woodhouse <David.Woodhouse@intel.com>
14 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
15 ---
16 MAINTAINERS | 6 +
17 arch/powerpc/include/asm/ps3.h | 1 +
18 arch/powerpc/platforms/ps3/device-init.c | 37 ++
19 drivers/mtd/devices/Kconfig | 7 +
20 drivers/mtd/devices/Makefile | 1 +
21 drivers/mtd/devices/ps3vram.c | 776 ++++++++++++++++++++++++++++++
22 6 files changed, 828 insertions(+), 0 deletions(-)
23 create mode 100644 drivers/mtd/devices/ps3vram.c
24
25 diff --git a/MAINTAINERS b/MAINTAINERS
26 index a018844..246878f 100644
27 --- a/MAINTAINERS
28 +++ b/MAINTAINERS
29 @@ -3484,6 +3484,12 @@ L: linuxppc-dev@ozlabs.org
30 L: cbe-oss-dev@ozlabs.org
31 S: Supported
32
33 +PS3VRAM DRIVER
34 +P: Jim Paris
35 +M: jim@jtan.com
36 +L: cbe-oss-dev@ozlabs.org
37 +S: Maintained
38 +
39 PVRUSB2 VIDEO4LINUX DRIVER
40 P: Mike Isely
41 M: isely@pobox.com
42 diff --git a/arch/powerpc/include/asm/ps3.h b/arch/powerpc/include/asm/ps3.h
43 index cff30c0..66b6505 100644
44 --- a/arch/powerpc/include/asm/ps3.h
45 +++ b/arch/powerpc/include/asm/ps3.h
46 @@ -320,6 +320,7 @@ enum ps3_match_id {
47
48 enum ps3_match_sub_id {
49 PS3_MATCH_SUB_ID_GPU_FB = 1,
50 + PS3_MATCH_SUB_ID_GPU_RAMDISK = 2,
51 };
52
53 #define PS3_MODULE_ALIAS_EHCI "ps3:1:0"
54 diff --git a/arch/powerpc/platforms/ps3/device-init.c b/arch/powerpc/platforms/ps3/device-init.c
55 index dbc124e..ca71a12 100644
56 --- a/arch/powerpc/platforms/ps3/device-init.c
57 +++ b/arch/powerpc/platforms/ps3/device-init.c
58 @@ -518,6 +518,41 @@ fail_device_register:
59 return result;
60 }
61
62 +static int __init ps3_register_ramdisk_device(void)
63 +{
64 + int result;
65 + struct layout {
66 + struct ps3_system_bus_device dev;
67 + } *p;
68 +
69 + pr_debug(" -> %s:%d\n", __func__, __LINE__);
70 +
71 + p = kzalloc(sizeof(struct layout), GFP_KERNEL);
72 +
73 + if (!p)
74 + return -ENOMEM;
75 +
76 + p->dev.match_id = PS3_MATCH_ID_GPU;
77 + p->dev.match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK;
78 + p->dev.dev_type = PS3_DEVICE_TYPE_IOC0;
79 +
80 + result = ps3_system_bus_device_register(&p->dev);
81 +
82 + if (result) {
83 + pr_debug("%s:%d ps3_system_bus_device_register failed\n",
84 + __func__, __LINE__);
85 + goto fail_device_register;
86 + }
87 +
88 + pr_debug(" <- %s:%d\n", __func__, __LINE__);
89 + return 0;
90 +
91 +fail_device_register:
92 + kfree(p);
93 + pr_debug(" <- %s:%d failed\n", __func__, __LINE__);
94 + return result;
95 +}
96 +
97 /**
98 * ps3_setup_dynamic_device - Setup a dynamic device from the repository
99 */
100 @@ -946,6 +981,8 @@ static int __init ps3_register_devices(void)
101
102 ps3_register_lpm_devices();
103
104 + ps3_register_ramdisk_device();
105 +
106 pr_debug(" <- %s:%d\n", __func__, __LINE__);
107 return 0;
108 }
109 diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig
110 index 6fde0a2..bc33200 100644
111 --- a/drivers/mtd/devices/Kconfig
112 +++ b/drivers/mtd/devices/Kconfig
113 @@ -120,6 +120,13 @@ config MTD_PHRAM
114 doesn't have access to, memory beyond the mem=xxx limit, nvram,
115 memory on the video card, etc...
116
117 +config MTD_PS3VRAM
118 + tristate "PS3 video RAM"
119 + depends on FB_PS3
120 + help
121 + This driver allows you to use excess PS3 video RAM as volatile
122 + storage or system swap.
123 +
124 config MTD_LART
125 tristate "28F160xx flash driver for LART"
126 depends on SA1100_LART
127 diff --git a/drivers/mtd/devices/Makefile b/drivers/mtd/devices/Makefile
128 index 0993d5c..e51521d 100644
129 --- a/drivers/mtd/devices/Makefile
130 +++ b/drivers/mtd/devices/Makefile
131 @@ -16,3 +16,4 @@ obj-$(CONFIG_MTD_LART) += lart.o
132 obj-$(CONFIG_MTD_BLOCK2MTD) += block2mtd.o
133 obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o
134 obj-$(CONFIG_MTD_M25P80) += m25p80.o
135 +obj-$(CONFIG_MTD_PS3VRAM) += ps3vram.o
136 diff --git a/drivers/mtd/devices/ps3vram.c b/drivers/mtd/devices/ps3vram.c
137 new file mode 100644
138 index 0000000..26a4b57
139 --- /dev/null
140 +++ b/drivers/mtd/devices/ps3vram.c
141 @@ -0,0 +1,776 @@
142 +/**
143 + * ps3vram - Use extra PS3 video ram as MTD block device.
144 + *
145 + * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com>
146 + * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr>
147 + */
148 +
149 +#include <linux/io.h>
150 +#include <linux/init.h>
151 +#include <linux/kernel.h>
152 +#include <linux/list.h>
153 +#include <linux/module.h>
154 +#include <linux/moduleparam.h>
155 +#include <linux/slab.h>
156 +#include <linux/version.h>
157 +#include <linux/gfp.h>
158 +#include <linux/delay.h>
159 +#include <linux/mtd/mtd.h>
160 +
161 +#include <asm/lv1call.h>
162 +#include <asm/ps3.h>
163 +
164 +#define DEVICE_NAME "ps3vram"
165 +
166 +#define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */
167 +#define XDR_IOIF 0x0c000000
168 +
169 +#define FIFO_BASE XDR_IOIF
170 +#define FIFO_SIZE (64 * 1024)
171 +
172 +#define DMA_PAGE_SIZE (4 * 1024)
173 +
174 +#define CACHE_PAGE_SIZE (256 * 1024)
175 +#define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE)
176 +
177 +#define CACHE_OFFSET CACHE_PAGE_SIZE
178 +#define FIFO_OFFSET 0
179 +
180 +#define CTRL_PUT 0x10
181 +#define CTRL_GET 0x11
182 +#define CTRL_TOP 0x15
183 +
184 +#define UPLOAD_SUBCH 1
185 +#define DOWNLOAD_SUBCH 2
186 +
187 +#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
188 +#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
189 +
190 +#define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601
191 +
192 +struct mtd_info ps3vram_mtd;
193 +
194 +#define CACHE_PAGE_PRESENT 1
195 +#define CACHE_PAGE_DIRTY 2
196 +
197 +#define dbg(fmt, args...) \
198 + pr_debug("%s:%d " fmt "\n", __func__, __LINE__, ## args)
199 +
200 +struct ps3vram_tag {
201 + unsigned int address;
202 + unsigned int flags;
203 +};
204 +
205 +struct ps3vram_cache {
206 + unsigned int page_count;
207 + unsigned int page_size;
208 + struct ps3vram_tag *tags;
209 +};
210 +
211 +struct ps3vram_priv {
212 + uint64_t memory_handle;
213 + uint64_t context_handle;
214 + uint8_t *base;
215 + uint32_t *ctrl;
216 + uint32_t *reports;
217 + uint8_t *xdr_buf;
218 +
219 + uint32_t *fifo_base;
220 + uint32_t *fifo_ptr;
221 +
222 + struct ps3vram_cache cache;
223 +
224 + /* Used to serialize cache/DMA operations */
225 + struct mutex lock;
226 +};
227 +
228 +#define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */
229 +#define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */
230 +#define DMA_NOTIFIER_SIZE 0x40
231 +
232 +#define NUM_NOTIFIERS 16
233 +
234 +#define NOTIFIER 7 /* notifier used for completion report */
235 +
236 +/* A trailing '-' means to subtract off ps3fb_videomemory.size */
237 +char *size = "256M-";
238 +module_param(size, charp, 0);
239 +MODULE_PARM_DESC(size, "memory size");
240 +
241 +static inline uint32_t *ps3vram_get_notifier(uint32_t *reports, int notifier)
242 +{
243 + return (void *) reports +
244 + DMA_NOTIFIER_OFFSET_BASE +
245 + DMA_NOTIFIER_SIZE * notifier;
246 +}
247 +
248 +static void ps3vram_notifier_reset(struct mtd_info *mtd)
249 +{
250 + int i;
251 + struct ps3vram_priv *priv = mtd->priv;
252 + uint32_t *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
253 + for (i = 0; i < 4; i++)
254 + notify[i] = 0xffffffff;
255 +}
256 +
257 +static int ps3vram_notifier_wait(struct mtd_info *mtd, int timeout_ms)
258 +{
259 + struct ps3vram_priv *priv = mtd->priv;
260 + uint32_t *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
261 +
262 + timeout_ms *= 1000;
263 +
264 + do {
265 + if (notify[3] == 0)
266 + return 0;
267 +
268 + if (timeout_ms)
269 + udelay(1);
270 + } while (timeout_ms--);
271 +
272 + return -1;
273 +}
274 +
275 +static void ps3vram_dump_ring(struct mtd_info *mtd)
276 +{
277 + struct ps3vram_priv *priv = mtd->priv;
278 + uint32_t *fifo;
279 +
280 + pr_info("PUT = %08x GET = %08x\n", priv->ctrl[CTRL_PUT],
281 + priv->ctrl[CTRL_GET]);
282 + for (fifo = priv->fifo_base; fifo < priv->fifo_ptr; fifo++)
283 + pr_info("%p: %08x\n", fifo, *fifo);
284 +}
285 +
286 +static void ps3vram_dump_reports(struct mtd_info *mtd)
287 +{
288 + struct ps3vram_priv *priv = mtd->priv;
289 + int i;
290 +
291 + for (i = 0; i < NUM_NOTIFIERS; i++) {
292 + uint32_t *n = ps3vram_get_notifier(priv->reports, i);
293 + pr_info("%p: %08x\n", n, *n);
294 + }
295 +}
296 +
297 +static void ps3vram_init_ring(struct mtd_info *mtd)
298 +{
299 + struct ps3vram_priv *priv = mtd->priv;
300 +
301 + priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
302 + priv->ctrl[CTRL_GET] = FIFO_BASE + FIFO_OFFSET;
303 +}
304 +
305 +static int ps3vram_wait_ring(struct mtd_info *mtd, int timeout)
306 +{
307 + struct ps3vram_priv *priv = mtd->priv;
308 +
309 + /* wait until setup commands are processed */
310 + timeout *= 1000;
311 + while (--timeout) {
312 + if (priv->ctrl[CTRL_PUT] == priv->ctrl[CTRL_GET])
313 + break;
314 + udelay(1);
315 + }
316 + if (timeout == 0) {
317 + pr_err("FIFO timeout (%08x/%08x/%08x)\n", priv->ctrl[CTRL_PUT],
318 + priv->ctrl[CTRL_GET], priv->ctrl[CTRL_TOP]);
319 + return -ETIMEDOUT;
320 + }
321 +
322 + return 0;
323 +}
324 +
325 +static inline void ps3vram_out_ring(struct ps3vram_priv *priv, uint32_t data)
326 +{
327 + *(priv->fifo_ptr)++ = data;
328 +}
329 +
330 +static inline void ps3vram_begin_ring(struct ps3vram_priv *priv, uint32_t chan,
331 + uint32_t tag, uint32_t size)
332 +{
333 + ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag);
334 +}
335 +
336 +static void ps3vram_rewind_ring(struct mtd_info *mtd)
337 +{
338 + struct ps3vram_priv *priv = mtd->priv;
339 + u64 status;
340 +
341 + ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET));
342 +
343 + priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
344 +
345 + /* asking the HV for a blit will kick the fifo */
346 + status = lv1_gpu_context_attribute(priv->context_handle,
347 + L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
348 + 0, 0, 0, 0);
349 + if (status)
350 + pr_err("ps3vram: lv1_gpu_context_attribute FB_BLIT failed\n");
351 +
352 + priv->fifo_ptr = priv->fifo_base;
353 +}
354 +
355 +static void ps3vram_fire_ring(struct mtd_info *mtd)
356 +{
357 + struct ps3vram_priv *priv = mtd->priv;
358 + u64 status;
359 +
360 + mutex_lock(&ps3_gpu_mutex);
361 +
362 + priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET +
363 + (priv->fifo_ptr - priv->fifo_base) * sizeof(uint32_t);
364 +
365 + /* asking the HV for a blit will kick the fifo */
366 + status = lv1_gpu_context_attribute(priv->context_handle,
367 + L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
368 + 0, 0, 0, 0);
369 + if (status)
370 + pr_err("ps3vram: lv1_gpu_context_attribute FB_BLIT failed\n");
371 +
372 + if ((priv->fifo_ptr - priv->fifo_base) * sizeof(uint32_t) >
373 + FIFO_SIZE - 1024) {
374 + dbg("fifo full, rewinding");
375 + ps3vram_wait_ring(mtd, 200);
376 + ps3vram_rewind_ring(mtd);
377 + }
378 +
379 + mutex_unlock(&ps3_gpu_mutex);
380 +}
381 +
382 +static void ps3vram_bind(struct mtd_info *mtd)
383 +{
384 + struct ps3vram_priv *priv = mtd->priv;
385 +
386 + ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1);
387 + ps3vram_out_ring(priv, 0x31337303);
388 + ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3);
389 + ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
390 + ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
391 + ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
392 +
393 + ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1);
394 + ps3vram_out_ring(priv, 0x3137c0de);
395 + ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3);
396 + ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
397 + ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
398 + ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
399 +
400 + ps3vram_fire_ring(mtd);
401 +}
402 +
403 +static int ps3vram_upload(struct mtd_info *mtd, unsigned int src_offset,
404 + unsigned int dst_offset, int len, int count)
405 +{
406 + struct ps3vram_priv *priv = mtd->priv;
407 +
408 + ps3vram_begin_ring(priv, UPLOAD_SUBCH,
409 + NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
410 + ps3vram_out_ring(priv, XDR_IOIF + src_offset);
411 + ps3vram_out_ring(priv, dst_offset);
412 + ps3vram_out_ring(priv, len);
413 + ps3vram_out_ring(priv, len);
414 + ps3vram_out_ring(priv, len);
415 + ps3vram_out_ring(priv, count);
416 + ps3vram_out_ring(priv, (1 << 8) | 1);
417 + ps3vram_out_ring(priv, 0);
418 +
419 + ps3vram_notifier_reset(mtd);
420 + ps3vram_begin_ring(priv, UPLOAD_SUBCH,
421 + NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
422 + ps3vram_out_ring(priv, 0);
423 + ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1);
424 + ps3vram_out_ring(priv, 0);
425 + ps3vram_fire_ring(mtd);
426 + if (ps3vram_notifier_wait(mtd, 200) < 0) {
427 + pr_err("notifier timeout\n");
428 + ps3vram_dump_ring(mtd);
429 + ps3vram_dump_reports(mtd);
430 + return -1;
431 + }
432 +
433 + return 0;
434 +}
435 +
436 +static int ps3vram_download(struct mtd_info *mtd, unsigned int src_offset,
437 + unsigned int dst_offset, int len, int count)
438 +{
439 + struct ps3vram_priv *priv = mtd->priv;
440 +
441 + ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
442 + NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
443 + ps3vram_out_ring(priv, src_offset);
444 + ps3vram_out_ring(priv, XDR_IOIF + dst_offset);
445 + ps3vram_out_ring(priv, len);
446 + ps3vram_out_ring(priv, len);
447 + ps3vram_out_ring(priv, len);
448 + ps3vram_out_ring(priv, count);
449 + ps3vram_out_ring(priv, (1 << 8) | 1);
450 + ps3vram_out_ring(priv, 0);
451 +
452 + ps3vram_notifier_reset(mtd);
453 + ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
454 + NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
455 + ps3vram_out_ring(priv, 0);
456 + ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1);
457 + ps3vram_out_ring(priv, 0);
458 + ps3vram_fire_ring(mtd);
459 + if (ps3vram_notifier_wait(mtd, 200) < 0) {
460 + pr_err("notifier timeout\n");
461 + ps3vram_dump_ring(mtd);
462 + ps3vram_dump_reports(mtd);
463 + return -1;
464 + }
465 +
466 + return 0;
467 +}
468 +
469 +static void ps3vram_cache_evict(struct mtd_info *mtd, int entry)
470 +{
471 + struct ps3vram_priv *priv = mtd->priv;
472 + struct ps3vram_cache *cache = &priv->cache;
473 +
474 + if (cache->tags[entry].flags & CACHE_PAGE_DIRTY) {
475 + dbg("flushing %d : 0x%08x", entry, cache->tags[entry].address);
476 + if (ps3vram_upload(mtd,
477 + CACHE_OFFSET + entry * cache->page_size,
478 + cache->tags[entry].address,
479 + DMA_PAGE_SIZE,
480 + cache->page_size / DMA_PAGE_SIZE) < 0) {
481 + pr_err("failed to upload from 0x%x to 0x%x size 0x%x\n",
482 + entry * cache->page_size,
483 + cache->tags[entry].address,
484 + cache->page_size);
485 + }
486 + cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY;
487 + }
488 +}
489 +
490 +static void ps3vram_cache_load(struct mtd_info *mtd, int entry,
491 + unsigned int address)
492 +{
493 + struct ps3vram_priv *priv = mtd->priv;
494 + struct ps3vram_cache *cache = &priv->cache;
495 +
496 + dbg("fetching %d : 0x%08x", entry, address);
497 + if (ps3vram_download(mtd,
498 + address,
499 + CACHE_OFFSET + entry * cache->page_size,
500 + DMA_PAGE_SIZE,
501 + cache->page_size / DMA_PAGE_SIZE) < 0) {
502 + pr_err("failed to download from 0x%x to 0x%x size 0x%x\n",
503 + address,
504 + entry * cache->page_size,
505 + cache->page_size);
506 + }
507 +
508 + cache->tags[entry].address = address;
509 + cache->tags[entry].flags |= CACHE_PAGE_PRESENT;
510 +}
511 +
512 +
513 +static void ps3vram_cache_flush(struct mtd_info *mtd)
514 +{
515 + struct ps3vram_priv *priv = mtd->priv;
516 + struct ps3vram_cache *cache = &priv->cache;
517 + int i;
518 +
519 + dbg("FLUSH");
520 + for (i = 0; i < cache->page_count; i++) {
521 + ps3vram_cache_evict(mtd, i);
522 + cache->tags[i].flags = 0;
523 + }
524 +}
525 +
526 +static unsigned int ps3vram_cache_match(struct mtd_info *mtd, loff_t address)
527 +{
528 + struct ps3vram_priv *priv = mtd->priv;
529 + struct ps3vram_cache *cache = &priv->cache;
530 + unsigned int base;
531 + unsigned int offset;
532 + int i;
533 + static int counter;
534 +
535 + offset = (unsigned int) (address & (cache->page_size - 1));
536 + base = (unsigned int) (address - offset);
537 +
538 + /* fully associative check */
539 + for (i = 0; i < cache->page_count; i++) {
540 + if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) &&
541 + cache->tags[i].address == base) {
542 + dbg("found entry %d : 0x%08x",
543 + i, cache->tags[i].address);
544 + return i;
545 + }
546 + }
547 +
548 + /* choose a random entry */
549 + i = (jiffies + (counter++)) % cache->page_count;
550 + dbg("using cache entry %d", i);
551 +
552 + ps3vram_cache_evict(mtd, i);
553 + ps3vram_cache_load(mtd, i, base);
554 +
555 + return i;
556 +}
557 +
558 +static int ps3vram_cache_init(struct mtd_info *mtd)
559 +{
560 + struct ps3vram_priv *priv = mtd->priv;
561 +
562 + pr_info("creating cache: %d entries, %d bytes pages\n",
563 + CACHE_PAGE_COUNT, CACHE_PAGE_SIZE);
564 +
565 + priv->cache.page_count = CACHE_PAGE_COUNT;
566 + priv->cache.page_size = CACHE_PAGE_SIZE;
567 + priv->cache.tags = kzalloc(sizeof(struct ps3vram_tag) *
568 + CACHE_PAGE_COUNT, GFP_KERNEL);
569 + if (priv->cache.tags == NULL) {
570 + pr_err("could not allocate cache tags\n");
571 + return -ENOMEM;
572 + }
573 +
574 + return 0;
575 +}
576 +
577 +static void ps3vram_cache_cleanup(struct mtd_info *mtd)
578 +{
579 + struct ps3vram_priv *priv = mtd->priv;
580 +
581 + ps3vram_cache_flush(mtd);
582 + kfree(priv->cache.tags);
583 +}
584 +
585 +static int ps3vram_erase(struct mtd_info *mtd, struct erase_info *instr)
586 +{
587 + struct ps3vram_priv *priv = mtd->priv;
588 +
589 + if (instr->addr + instr->len > mtd->size)
590 + return -EINVAL;
591 +
592 + mutex_lock(&priv->lock);
593 +
594 + ps3vram_cache_flush(mtd);
595 +
596 + /* Set bytes to 0xFF */
597 + memset(priv->base + instr->addr, 0xFF, instr->len);
598 +
599 + mutex_unlock(&priv->lock);
600 +
601 + instr->state = MTD_ERASE_DONE;
602 + mtd_erase_callback(instr);
603 +
604 + return 0;
605 +}
606 +
607 +
608 +static int ps3vram_read(struct mtd_info *mtd, loff_t from, size_t len,
609 + size_t *retlen, u_char *buf)
610 +{
611 + struct ps3vram_priv *priv = mtd->priv;
612 + unsigned int cached, count;
613 +
614 + dbg("from = 0x%08x len = 0x%zx", (unsigned int) from, len);
615 +
616 + if (from >= mtd->size)
617 + return -EINVAL;
618 +
619 + if (len > mtd->size - from)
620 + len = mtd->size - from;
621 +
622 + /* Copy from vram to buf */
623 + count = len;
624 + while (count) {
625 + unsigned int offset, avail;
626 + unsigned int entry;
627 +
628 + offset = (unsigned int) (from & (priv->cache.page_size - 1));
629 + avail = priv->cache.page_size - offset;
630 +
631 + mutex_lock(&priv->lock);
632 +
633 + entry = ps3vram_cache_match(mtd, from);
634 + cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
635 +
636 + dbg("from=%08x cached=%08x offset=%08x avail=%08x count=%08x",
637 + (unsigned)from, cached, offset, avail, count);
638 +
639 + if (avail > count)
640 + avail = count;
641 + memcpy(buf, priv->xdr_buf + cached, avail);
642 +
643 + mutex_unlock(&priv->lock);
644 +
645 + buf += avail;
646 + count -= avail;
647 + from += avail;
648 + }
649 +
650 + *retlen = len;
651 + return 0;
652 +}
653 +
654 +static int ps3vram_write(struct mtd_info *mtd, loff_t to, size_t len,
655 + size_t *retlen, const u_char *buf)
656 +{
657 + struct ps3vram_priv *priv = mtd->priv;
658 + unsigned int cached, count;
659 +
660 + if (to >= mtd->size)
661 + return -EINVAL;
662 +
663 + if (len > mtd->size - to)
664 + len = mtd->size - to;
665 +
666 + /* Copy from buf to vram */
667 + count = len;
668 + while (count) {
669 + unsigned int offset, avail;
670 + unsigned int entry;
671 +
672 + offset = (unsigned int) (to & (priv->cache.page_size - 1));
673 + avail = priv->cache.page_size - offset;
674 +
675 + mutex_lock(&priv->lock);
676 +
677 + entry = ps3vram_cache_match(mtd, to);
678 + cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
679 +
680 + dbg("to=%08x cached=%08x offset=%08x avail=%08x count=%08x",
681 + (unsigned) to, cached, offset, avail, count);
682 +
683 + if (avail > count)
684 + avail = count;
685 + memcpy(priv->xdr_buf + cached, buf, avail);
686 +
687 + priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY;
688 +
689 + mutex_unlock(&priv->lock);
690 +
691 + buf += avail;
692 + count -= avail;
693 + to += avail;
694 + }
695 +
696 + *retlen = len;
697 + return 0;
698 +}
699 +
700 +static int __devinit ps3vram_probe(struct ps3_system_bus_device *dev)
701 +{
702 + struct ps3vram_priv *priv;
703 + uint64_t status;
704 + uint64_t ddr_lpar, ctrl_lpar, info_lpar, reports_lpar;
705 + int64_t ddr_size;
706 + uint64_t reports_size;
707 + int ret = -ENOMEM;
708 + char *rest;
709 +
710 + ret = -EIO;
711 + ps3vram_mtd.priv = kzalloc(sizeof(struct ps3vram_priv), GFP_KERNEL);
712 + if (!ps3vram_mtd.priv)
713 + goto out;
714 + priv = ps3vram_mtd.priv;
715 +
716 + mutex_init(&priv->lock);
717 +
718 + /* Allocate XDR buffer (1MiB aligned) */
719 + priv->xdr_buf = (uint8_t *) __get_free_pages(GFP_KERNEL,
720 + get_order(XDR_BUF_SIZE));
721 + if (priv->xdr_buf == NULL) {
722 + pr_err("ps3vram: could not allocate XDR buffer\n");
723 + ret = -ENOMEM;
724 + goto out_free_priv;
725 + }
726 +
727 + /* Put FIFO at begginning of XDR buffer */
728 + priv->fifo_base = (uint32_t *) (priv->xdr_buf + FIFO_OFFSET);
729 + priv->fifo_ptr = priv->fifo_base;
730 +
731 + /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */
732 + if (ps3_open_hv_device(dev)) {
733 + pr_err("ps3vram: ps3_open_hv_device failed\n");
734 + ret = -EAGAIN;
735 + goto out_close_gpu;
736 + }
737 +
738 + /* Request memory */
739 + status = -1;
740 + ddr_size = memparse(size, &rest);
741 + if (*rest == '-')
742 + ddr_size -= ps3fb_videomemory.size;
743 + ddr_size = ALIGN(ddr_size, 1024*1024);
744 + if (ddr_size <= 0) {
745 + printk(KERN_ERR "ps3vram: specified size is too small\n");
746 + ret = -EINVAL;
747 + goto out_close_gpu;
748 + }
749 +
750 + while (ddr_size > 0) {
751 + status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0,
752 + &priv->memory_handle,
753 + &ddr_lpar);
754 + if (status == 0)
755 + break;
756 + ddr_size -= 1024*1024;
757 + }
758 + if (status != 0 || ddr_size <= 0) {
759 + pr_err("ps3vram: lv1_gpu_memory_allocate failed\n");
760 + ret = -ENOMEM;
761 + goto out_free_xdr_buf;
762 + }
763 + pr_info("ps3vram: allocated %u MiB of DDR memory\n",
764 + (unsigned int) (ddr_size / 1024 / 1024));
765 +
766 + /* Request context */
767 + status = lv1_gpu_context_allocate(priv->memory_handle,
768 + 0,
769 + &priv->context_handle,
770 + &ctrl_lpar,
771 + &info_lpar,
772 + &reports_lpar,
773 + &reports_size);
774 + if (status) {
775 + pr_err("ps3vram: lv1_gpu_context_allocate failed\n");
776 + ret = -ENOMEM;
777 + goto out_free_memory;
778 + }
779 +
780 + /* Map XDR buffer to RSX */
781 + status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
782 + ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)),
783 + XDR_BUF_SIZE, 0);
784 + if (status) {
785 + pr_err("ps3vram: lv1_gpu_context_iomap failed\n");
786 + ret = -ENOMEM;
787 + goto out_free_context;
788 + }
789 +
790 + priv->base = ioremap(ddr_lpar, ddr_size);
791 + if (!priv->base) {
792 + pr_err("ps3vram: ioremap failed\n");
793 + ret = -ENOMEM;
794 + goto out_free_context;
795 + }
796 +
797 + priv->ctrl = ioremap(ctrl_lpar, 64 * 1024);
798 + if (!priv->ctrl) {
799 + pr_err("ps3vram: ioremap failed\n");
800 + ret = -ENOMEM;
801 + goto out_unmap_vram;
802 + }
803 +
804 + priv->reports = ioremap(reports_lpar, reports_size);
805 + if (!priv->reports) {
806 + pr_err("ps3vram: ioremap failed\n");
807 + ret = -ENOMEM;
808 + goto out_unmap_ctrl;
809 + }
810 +
811 + mutex_lock(&ps3_gpu_mutex);
812 + ps3vram_init_ring(&ps3vram_mtd);
813 + mutex_unlock(&ps3_gpu_mutex);
814 +
815 + ps3vram_mtd.name = "ps3vram";
816 + ps3vram_mtd.size = ddr_size;
817 + ps3vram_mtd.flags = MTD_CAP_RAM;
818 + ps3vram_mtd.erase = ps3vram_erase;
819 + ps3vram_mtd.point = NULL;
820 + ps3vram_mtd.unpoint = NULL;
821 + ps3vram_mtd.read = ps3vram_read;
822 + ps3vram_mtd.write = ps3vram_write;
823 + ps3vram_mtd.owner = THIS_MODULE;
824 + ps3vram_mtd.type = MTD_RAM;
825 + ps3vram_mtd.erasesize = CACHE_PAGE_SIZE;
826 + ps3vram_mtd.writesize = 1;
827 +
828 + ps3vram_bind(&ps3vram_mtd);
829 +
830 + mutex_lock(&ps3_gpu_mutex);
831 + ret = ps3vram_wait_ring(&ps3vram_mtd, 100);
832 + mutex_unlock(&ps3_gpu_mutex);
833 + if (ret < 0) {
834 + pr_err("failed to initialize channels\n");
835 + ret = -ETIMEDOUT;
836 + goto out_unmap_reports;
837 + }
838 +
839 + ps3vram_cache_init(&ps3vram_mtd);
840 +
841 + if (add_mtd_device(&ps3vram_mtd)) {
842 + pr_err("ps3vram: failed to register device\n");
843 + ret = -EAGAIN;
844 + goto out_cache_cleanup;
845 + }
846 +
847 + pr_info("ps3vram mtd device registered, %lu bytes\n", ddr_size);
848 + return 0;
849 +
850 +out_cache_cleanup:
851 + ps3vram_cache_cleanup(&ps3vram_mtd);
852 +out_unmap_reports:
853 + iounmap(priv->reports);
854 +out_unmap_ctrl:
855 + iounmap(priv->ctrl);
856 +out_unmap_vram:
857 + iounmap(priv->base);
858 +out_free_context:
859 + lv1_gpu_context_free(priv->context_handle);
860 +out_free_memory:
861 + lv1_gpu_memory_free(priv->memory_handle);
862 +out_close_gpu:
863 + ps3_close_hv_device(dev);
864 +out_free_xdr_buf:
865 + free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
866 +out_free_priv:
867 + kfree(ps3vram_mtd.priv);
868 + ps3vram_mtd.priv = NULL;
869 +out:
870 + return ret;
871 +}
872 +
873 +static int ps3vram_shutdown(struct ps3_system_bus_device *dev)
874 +{
875 + struct ps3vram_priv *priv;
876 +
877 + priv = ps3vram_mtd.priv;
878 +
879 + del_mtd_device(&ps3vram_mtd);
880 + ps3vram_cache_cleanup(&ps3vram_mtd);
881 + iounmap(priv->reports);
882 + iounmap(priv->ctrl);
883 + iounmap(priv->base);
884 + lv1_gpu_context_free(priv->context_handle);
885 + lv1_gpu_memory_free(priv->memory_handle);
886 + ps3_close_hv_device(dev);
887 + free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
888 + kfree(priv);
889 + return 0;
890 +}
891 +
892 +static struct ps3_system_bus_driver ps3vram_driver = {
893 + .match_id = PS3_MATCH_ID_GPU,
894 + .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK,
895 + .core.name = DEVICE_NAME,
896 + .core.owner = THIS_MODULE,
897 + .probe = ps3vram_probe,
898 + .remove = ps3vram_shutdown,
899 + .shutdown = ps3vram_shutdown,
900 +};
901 +
902 +static int __init ps3vram_init(void)
903 +{
904 + return ps3_system_bus_driver_register(&ps3vram_driver);
905 +}
906 +
907 +static void __exit ps3vram_exit(void)
908 +{
909 + ps3_system_bus_driver_unregister(&ps3vram_driver);
910 +}
911 +
912 +module_init(ps3vram_init);
913 +module_exit(ps3vram_exit);
914 +
915 +MODULE_LICENSE("GPL");
916 +MODULE_AUTHOR("Jim Paris <jim@jtan.com>");
917 +MODULE_DESCRIPTION("MTD driver for PS3 video RAM");
918 --
919 1.6.0.4
920
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