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add pci latency timer workaround for atheros cards (from #1546)
[openwrt.git] / target / linux / brcm47xx-2.6 / files / drivers / ssb / core.c
1 /*
2 * Sonics Silicon Backplane
3 * Subsystem core
4 *
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11 #include "ssb_private.h"
12
13 #include <linux/delay.h>
14 #include <linux/ssb/ssb.h>
15 #include <linux/ssb/ssb_regs.h>
16
17 #ifdef CONFIG_SSB_PCIHOST
18 # include <linux/pci.h>
19 #endif
20
21 #ifdef CONFIG_SSB_PCMCIAHOST
22 # include <pcmcia/cs_types.h>
23 # include <pcmcia/cs.h>
24 # include <pcmcia/cistpl.h>
25 # include <pcmcia/ds.h>
26 #endif
27
28
29 MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
30 MODULE_LICENSE("GPL");
31
32
33 static LIST_HEAD(attach_queue);
34 static LIST_HEAD(buses);
35 static int nr_buses;
36 static DEFINE_MUTEX(buses_mutex);
37
38 #define ssb_buses_lock() do { \
39 if (!is_early_boot()) \
40 mutex_lock(&buses_mutex); \
41 } while (0)
42
43 #define ssb_buses_unlock() do { \
44 if (!is_early_boot()) \
45 mutex_unlock(&buses_mutex); \
46 } while (0)
47
48
49 static struct ssb_device * ssb_device_get(struct ssb_device *dev)
50 {
51 if (dev)
52 get_device(&dev->dev);
53 return dev;
54 }
55
56 static void ssb_device_put(struct ssb_device *dev)
57 {
58 if (dev)
59 put_device(&dev->dev);
60 }
61
62 static void ssb_bus_resume(struct ssb_bus *bus)
63 {
64 printk("SSB BUS RESUME\n");
65 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
66 ssb_chipco_resume(&bus->chipco);
67 }
68
69 static int ssb_device_resume(struct device *dev)
70 {
71 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
72 struct ssb_driver *ssb_drv;
73 struct ssb_bus *bus;
74 int err = 0;
75
76 printk("SSB DEV RESUME\n");
77 bus = ssb_dev->bus;
78 if (bus->suspend_cnt == bus->nr_devices)
79 ssb_bus_resume(bus);
80 bus->suspend_cnt--;
81 if (dev->driver) {
82 ssb_drv = drv_to_ssb_drv(dev->driver);
83 if (ssb_drv && ssb_drv->resume)
84 err = ssb_drv->resume(ssb_dev);
85 if (err)
86 goto out;
87 }
88 out:
89 return err;
90 }
91
92 static void ssb_bus_suspend(struct ssb_bus *bus, pm_message_t state)
93 {
94 printk("SSB BUS SUSPEND\n");
95 // ssb_chipco_suspend(&bus->chipco, state);
96 // ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
97 }
98
99 static int ssb_device_suspend(struct device *dev, pm_message_t state)
100 {
101 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
102 struct ssb_driver *ssb_drv;
103 struct ssb_bus *bus;
104 int err = 0;
105
106 printk("SSB DEV SUSPEND\n");
107 if (dev->driver) {
108 ssb_drv = drv_to_ssb_drv(dev->driver);
109 if (ssb_drv && ssb_drv->suspend)
110 err = ssb_drv->suspend(ssb_dev, state);
111 if (err)
112 goto out;
113 }
114
115 bus = ssb_dev->bus;
116 bus->suspend_cnt++;
117 if (bus->suspend_cnt == bus->nr_devices) {
118 /* All devices suspended. Shutdown the bus. */
119 ssb_bus_suspend(bus, state);
120 }
121
122 out:
123 return err;
124 }
125
126 static void ssb_device_shutdown(struct device *dev)
127 {
128 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
129 struct ssb_driver *ssb_drv;
130
131 if (!dev->driver)
132 return;
133 ssb_drv = drv_to_ssb_drv(dev->driver);
134 if (ssb_drv && ssb_drv->shutdown)
135 ssb_drv->shutdown(ssb_dev);
136 }
137
138 static int ssb_device_remove(struct device *dev)
139 {
140 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
141 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
142
143 if (ssb_drv && ssb_drv->remove)
144 ssb_drv->remove(ssb_dev);
145 ssb_device_put(ssb_dev);
146
147 return 0;
148 }
149
150 static int ssb_device_probe(struct device *dev)
151 {
152 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
153 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
154 int err = 0;
155
156 ssb_device_get(ssb_dev);
157 if (ssb_drv && ssb_drv->probe)
158 err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
159 if (err)
160 ssb_device_put(ssb_dev);
161
162 return err;
163 }
164
165 static int ssb_match_devid(const struct ssb_device_id *tabid,
166 const struct ssb_device_id *devid)
167 {
168 if ((tabid->vendor != devid->vendor) &&
169 tabid->vendor != SSB_ANY_VENDOR)
170 return 0;
171 if ((tabid->coreid != devid->coreid) &&
172 tabid->coreid != SSB_ANY_ID)
173 return 0;
174 if ((tabid->revision != devid->revision) &&
175 tabid->revision != SSB_ANY_REV)
176 return 0;
177 return 1;
178 }
179
180 static int ssb_bus_match(struct device *dev, struct device_driver *drv)
181 {
182 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
183 struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
184 const struct ssb_device_id *id;
185
186 for (id = ssb_drv->id_table;
187 id->vendor || id->coreid || id->revision;
188 id++) {
189 if (ssb_match_devid(id, &ssb_dev->id))
190 return 1; /* found */
191 }
192
193 return 0;
194 }
195
196 struct bus_type ssb_bustype = {
197 .name = NULL, /* Intentionally NULL to indicate early boot */
198 .match = ssb_bus_match,
199 .probe = ssb_device_probe,
200 .remove = ssb_device_remove,
201 .shutdown = ssb_device_shutdown,
202 .suspend = ssb_device_suspend,
203 .resume = ssb_device_resume,
204 };
205
206 #define is_early_boot() (ssb_bustype.name == NULL)
207
208 void ssb_bus_unregister(struct ssb_bus *bus)
209 {
210 struct ssb_device *dev;
211 int i;
212
213 ssb_buses_lock();
214 for (i = bus->nr_devices - 1; i >= 0; i--) {
215 dev = &(bus->devices[i]);
216 device_unregister(&dev->dev);
217 }
218 list_del(&bus->list);
219 ssb_buses_unlock();
220
221 ssb_iounmap(bus);
222 }
223 EXPORT_SYMBOL(ssb_bus_unregister);
224
225 static void ssb_release_dev(struct device *dev)
226 {
227 /* Nothing, devices are allocated together with struct ssb_bus. */
228 }
229
230 /* Needs ssb_buses_lock() */
231 static int ssb_attach_queued_buses(void)
232 {
233 struct ssb_bus *bus, *n;
234 struct ssb_device *dev;
235 int i, err;
236
237 list_for_each_entry_safe(bus, n, &attach_queue, list) {
238 ssb_pcicore_init(&bus->pcicore);
239 for (i = 0; i < bus->nr_devices; i++) {
240 dev = &(bus->devices[i]);
241
242 dev->dev.release = ssb_release_dev;
243 err = device_register(&dev->dev);
244 if (err) {
245 ssb_printk(KERN_ERR PFX
246 "Could not register %s\n",
247 dev->dev.bus_id);
248 }
249 }
250 list_move_tail(&bus->list, &buses);
251 }
252 return 0;
253 }
254
255 static void ssb_get_boardtype(struct ssb_bus *bus)
256 {//FIXME for pcmcia?
257 if (bus->bustype != SSB_BUSTYPE_PCI) {
258 /* Must set board_vendor, board_type and board_rev
259 * before calling ssb_bus_*_register() */
260 assert(bus->board_vendor && bus->board_type);
261 return;
262 }
263 ssb_pci_get_boardtype(bus);
264 }
265
266 static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
267 {
268 struct ssb_bus *bus = dev->bus;
269
270 offset += dev->core_index * SSB_CORE_SIZE;
271 return readw(bus->mmio + offset);
272 }
273
274 static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
275 {
276 struct ssb_bus *bus = dev->bus;
277
278 offset += dev->core_index * SSB_CORE_SIZE;
279 return readl(bus->mmio + offset);
280 }
281
282 static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
283 {
284 struct ssb_bus *bus = dev->bus;
285
286 offset += dev->core_index * SSB_CORE_SIZE;
287 writew(value, bus->mmio + offset);
288 }
289
290 static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
291 {
292 struct ssb_bus *bus = dev->bus;
293
294 offset += dev->core_index * SSB_CORE_SIZE;
295 writel(value, bus->mmio + offset);
296 }
297
298 static const struct ssb_bus_ops ssb_ssb_ops = {
299 .read16 = ssb_ssb_read16,
300 .read32 = ssb_ssb_read32,
301 .write16 = ssb_ssb_write16,
302 .write32 = ssb_ssb_write32,
303 };
304
305 static int ssb_bus_register(struct ssb_bus *bus,
306 unsigned long baseaddr)
307 {
308 int err;
309
310 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on ");
311 switch (bus->bustype) {
312 case SSB_BUSTYPE_SSB:
313 ssb_printk("address 0x%08lX\n", baseaddr);
314 break;
315 case SSB_BUSTYPE_PCI:
316 #ifdef CONFIG_SSB_PCIHOST
317 ssb_printk("PCI device %s\n", bus->host_pci->dev.bus_id);
318 #endif
319 break;
320 case SSB_BUSTYPE_PCMCIA:
321 #ifdef CONFIG_SSB_PCMCIAHOST
322 ssb_printk("PCMCIA device %s\n", bus->host_pcmcia->devname);
323 #endif
324 break;
325 }
326
327 spin_lock_init(&bus->bar_lock);
328 INIT_LIST_HEAD(&bus->list);
329
330 ssb_get_boardtype(bus);
331 /* Powerup the bus */
332 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
333 if (err)
334 goto out;
335 ssb_buses_lock();
336 bus->busnumber = nr_buses;
337 /* Scan for devices (cores) */
338 err = ssb_bus_scan(bus, baseaddr);
339 if (err)
340 goto err_disable_xtal;
341
342 /* Init PCI-host device (if any) */
343 err = ssb_pci_init(bus);
344 if (err)
345 goto err_unmap;
346 /* Init PCMCIA-host device (if any) */
347 err = ssb_pcmcia_init(bus);
348 if (err)
349 goto err_unmap;
350
351 /* Initialize basic system devices (if available) */
352 ssb_chipcommon_init(&bus->chipco);
353 ssb_mipscore_init(&bus->mipscore);
354
355 /* Queue it for attach */
356 list_add_tail(&bus->list, &attach_queue);
357 if (!is_early_boot()) {
358 /* This is not early boot, so we must attach the bus now */
359 err = ssb_attach_queued_buses();
360 if (err)
361 goto err_dequeue;
362 }
363 nr_buses++;
364 ssb_buses_unlock();
365
366 out:
367 return err;
368
369 err_dequeue:
370 list_del(&bus->list);
371 err_unmap:
372 ssb_iounmap(bus);
373 err_disable_xtal:
374 ssb_buses_unlock();
375 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
376 goto out;
377 }
378
379 #ifdef CONFIG_SSB_PCIHOST
380 int ssb_bus_pcibus_register(struct ssb_bus *bus,
381 struct pci_dev *host_pci)
382 {
383 int err;
384
385 bus->bustype = SSB_BUSTYPE_PCI;
386 bus->host_pci = host_pci;
387 bus->ops = &ssb_pci_ops;
388
389 err = ssb_bus_register(bus, 0);
390
391 return err;
392 }
393 EXPORT_SYMBOL(ssb_bus_pcibus_register);
394 #endif /* CONFIG_SSB_PCIHOST */
395
396 #ifdef CONFIG_SSB_PCMCIAHOST
397 int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
398 struct pcmcia_device *pcmcia_dev,
399 unsigned long baseaddr,
400 void (*fill_sprom)(struct ssb_sprom *sprom))
401 {
402 int err;
403
404 bus->bustype = SSB_BUSTYPE_PCMCIA;
405 bus->host_pcmcia = pcmcia_dev;
406 bus->ops = &ssb_pcmcia_ops;
407 fill_sprom(&bus->sprom);
408
409 err = ssb_bus_register(bus, baseaddr);
410
411 return err;
412 }
413 EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
414 #endif /* CONFIG_SSB_PCMCIAHOST */
415
416 int ssb_bus_ssbbus_register(struct ssb_bus *bus,
417 unsigned long baseaddr,
418 void (*fill_sprom)(struct ssb_sprom *sprom))
419 {
420 int err;
421
422 bus->bustype = SSB_BUSTYPE_SSB;
423 bus->ops = &ssb_ssb_ops;
424 fill_sprom(&bus->sprom);
425 err = ssb_bus_register(bus, baseaddr);
426
427 return err;
428 }
429
430 int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
431 {
432 drv->drv.name = drv->name;
433 drv->drv.bus = &ssb_bustype;
434 drv->drv.owner = owner;
435
436 return driver_register(&drv->drv);
437 }
438 EXPORT_SYMBOL(__ssb_driver_register);
439
440 void ssb_driver_unregister(struct ssb_driver *drv)
441 {
442 driver_unregister(&drv->drv);
443 }
444 EXPORT_SYMBOL(ssb_driver_unregister);
445
446 void ssb_set_devtypedata(struct ssb_device *dev, void *data)
447 {
448 struct ssb_bus *bus = dev->bus;
449 struct ssb_device *ent;
450 int i;
451
452 for (i = 0; i < bus->nr_devices; i++) {
453 ent = &(bus->devices[i]);
454 if (ent->id.vendor != dev->id.vendor)
455 continue;
456 if (ent->id.coreid != dev->id.coreid)
457 continue;
458
459 ent->devtypedata = data;
460 }
461 }
462 EXPORT_SYMBOL(ssb_set_devtypedata);
463
464 static u32 clkfactor_f6_resolve(u32 v)
465 {
466 /* map the magic values */
467 switch (v) {
468 case SSB_CHIPCO_CLK_F6_2:
469 return 2;
470 case SSB_CHIPCO_CLK_F6_3:
471 return 3;
472 case SSB_CHIPCO_CLK_F6_4:
473 return 4;
474 case SSB_CHIPCO_CLK_F6_5:
475 return 5;
476 case SSB_CHIPCO_CLK_F6_6:
477 return 6;
478 case SSB_CHIPCO_CLK_F6_7:
479 return 7;
480 }
481 return 0;
482 }
483
484 /* Calculate the speed the backplane would run at a given set of clockcontrol values */
485 u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
486 {
487 u32 n1, n2, clock, m1, m2, m3, mc;
488
489 n1 = (n & SSB_CHIPCO_CLK_N1);
490 n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
491
492 switch (plltype) {
493 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
494 if (m & SSB_CHIPCO_CLK_T6_MMASK)
495 return SSB_CHIPCO_CLK_T6_M0;
496 return SSB_CHIPCO_CLK_T6_M1;
497 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
498 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
499 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
500 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
501 n1 = clkfactor_f6_resolve(n1);
502 n2 += SSB_CHIPCO_CLK_F5_BIAS;
503 break;
504 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
505 n1 += SSB_CHIPCO_CLK_T2_BIAS;
506 n2 += SSB_CHIPCO_CLK_T2_BIAS;
507 assert((n1 >= 2) && (n1 <= 7));
508 assert((n2 >= 5) && (n2 <= 23));
509 break;
510 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
511 return 100000000;
512 default:
513 assert(0);
514 }
515
516 switch (plltype) {
517 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
518 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
519 clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
520 break;
521 default:
522 clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
523 }
524 if (!clock)
525 return 0;
526
527 m1 = (m & SSB_CHIPCO_CLK_M1);
528 m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
529 m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
530 mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
531
532 switch (plltype) {
533 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
534 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
535 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
536 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
537 m1 = clkfactor_f6_resolve(m1);
538 if ((plltype == SSB_PLLTYPE_1) ||
539 (plltype == SSB_PLLTYPE_3))
540 m2 += SSB_CHIPCO_CLK_F5_BIAS;
541 else
542 m2 = clkfactor_f6_resolve(m2);
543 m3 = clkfactor_f6_resolve(m3);
544
545 switch (mc) {
546 case SSB_CHIPCO_CLK_MC_BYPASS:
547 return clock;
548 case SSB_CHIPCO_CLK_MC_M1:
549 return (clock / m1);
550 case SSB_CHIPCO_CLK_MC_M1M2:
551 return (clock / (m1 * m2));
552 case SSB_CHIPCO_CLK_MC_M1M2M3:
553 return (clock / (m1 * m2 * m3));
554 case SSB_CHIPCO_CLK_MC_M1M3:
555 return (clock / (m1 * m3));
556 }
557 return 0;
558 case SSB_PLLTYPE_2:
559 m1 += SSB_CHIPCO_CLK_T2_BIAS;
560 m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
561 m3 += SSB_CHIPCO_CLK_T2_BIAS;
562 assert((m1 >= 2) && (m1 <= 7));
563 assert((m2 >= 3) && (m2 <= 10));
564 assert((m3 >= 2) && (m3 <= 7));
565
566 if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
567 clock /= m1;
568 if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
569 clock /= m2;
570 if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
571 clock /= m3;
572 return clock;
573 default:
574 assert(0);
575 }
576 return 0;
577 }
578
579 /* Get the current speed the backplane is running at */
580 u32 ssb_clockspeed(struct ssb_bus *bus)
581 {
582 u32 rate;
583 u32 plltype;
584 u32 clkctl_n, clkctl_m;
585
586 //TODO if EXTIF: PLLTYPE == 1, read n from clockcontrol_n, m from clockcontrol_sb
587
588 if (bus->chipco.dev) {
589 ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
590 &clkctl_n, &clkctl_m);
591 } else
592 return 0;
593
594 if (bus->chip_id == 0x5365) {
595 rate = 100000000;
596 } else {
597 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
598 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
599 rate /= 2;
600 }
601
602 return rate;
603 }
604 EXPORT_SYMBOL(ssb_clockspeed);
605
606 int ssb_device_is_enabled(struct ssb_device *dev)
607 {
608 u32 val;
609
610 val = ssb_read32(dev, SSB_TMSLOW);
611 val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT;
612
613 return (val == SSB_TMSLOW_CLOCK);
614 }
615 EXPORT_SYMBOL(ssb_device_is_enabled);
616
617 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
618 {
619 u32 val;
620
621 ssb_device_disable(dev, core_specific_flags);
622 ssb_write32(dev, SSB_TMSLOW,
623 SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
624 SSB_TMSLOW_FGC | core_specific_flags);
625 /* flush */
626 ssb_read32(dev, SSB_TMSLOW);
627 udelay(1);
628
629 /* Clear SERR if set. This is a hw bug workaround. */
630 if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
631 ssb_write32(dev, SSB_TMSHIGH, 0);
632
633 val = ssb_read32(dev, SSB_IMSTATE);
634 if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
635 val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
636 ssb_write32(dev, SSB_IMSTATE, val);
637 }
638
639 ssb_write32(dev, SSB_TMSLOW,
640 SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
641 core_specific_flags);
642 /* flush */
643 ssb_read32(dev, SSB_TMSLOW);
644 udelay(1);
645
646 ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
647 core_specific_flags);
648 /* flush */
649 ssb_read32(dev, SSB_TMSLOW);
650 udelay(1);
651 }
652 EXPORT_SYMBOL(ssb_device_enable);
653
654 static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
655 int timeout, int set)
656 {
657 int i;
658 u32 val;
659
660 for (i = 0; i < timeout; i++) {
661 val = ssb_read32(dev, reg);
662 if (set) {
663 if (val & bitmask)
664 return 0;
665 } else {
666 if (!(val & bitmask))
667 return 0;
668 }
669 udelay(10);
670 }
671 printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
672 "register %04X to %s.\n",
673 bitmask, reg, (set ? "set" : "clear"));
674
675 return -ETIMEDOUT;
676 }
677
678 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
679 {
680 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
681 return;
682
683 ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_REJECT | SSB_TMSLOW_CLOCK);
684 ssb_wait_bit(dev, SSB_TMSLOW, SSB_TMSLOW_REJECT, 1000, 1);
685 ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
686 ssb_write32(dev, SSB_TMSLOW,
687 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
688 SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET |
689 core_specific_flags);
690 /* flush */
691 ssb_read32(dev, SSB_TMSLOW);
692 udelay(1);
693
694 ssb_write32(dev, SSB_TMSLOW,
695 SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET |
696 core_specific_flags);
697 /* flush */
698 ssb_read32(dev, SSB_TMSLOW);
699 udelay(1);
700 }
701 EXPORT_SYMBOL(ssb_device_disable);
702
703 u32 ssb_dma_translation(struct ssb_device *dev)
704 {
705 switch(dev->bus->bustype) {
706 case SSB_BUSTYPE_SSB:
707 return 0;
708 case SSB_BUSTYPE_PCI:
709 case SSB_BUSTYPE_PCMCIA:
710 return SSB_PCI_DMA;
711 }
712 return 0;
713 }
714 EXPORT_SYMBOL(ssb_dma_translation);
715
716 int ssb_dma_set_mask(struct ssb_device *ssb_dev, u64 mask)
717 {
718 struct device *dev = &ssb_dev->dev;
719
720 #ifdef CONFIG_SSB_PCIHOST
721 if (ssb_dev->bus->bustype == SSB_BUSTYPE_PCI &&
722 !dma_supported(dev, mask))
723 return -EIO;
724 #endif
725 dev->coherent_dma_mask = mask;
726 dev->dma_mask = &dev->coherent_dma_mask;
727
728 return 0;
729 }
730 EXPORT_SYMBOL(ssb_dma_set_mask);
731
732 u32 ssb_admatch_base(u32 adm)
733 {
734 u32 base = 0;
735
736 switch (adm & SSB_ADM_TYPE) {
737 case SSB_ADM_TYPE0:
738 base = (adm & SSB_ADM_BASE0);
739 break;
740 case SSB_ADM_TYPE1:
741 assert(!(adm & SSB_ADM_NEG)); /* unsupported */
742 base = (adm & SSB_ADM_BASE1);
743 break;
744 case SSB_ADM_TYPE2:
745 assert(!(adm & SSB_ADM_NEG)); /* unsupported */
746 base = (adm & SSB_ADM_BASE2);
747 break;
748 default:
749 assert(0);
750 }
751
752 return base;
753 }
754 EXPORT_SYMBOL(ssb_admatch_base);
755
756 u32 ssb_admatch_size(u32 adm)
757 {
758 u32 size = 0;
759
760 switch (adm & SSB_ADM_TYPE) {
761 case SSB_ADM_TYPE0:
762 size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
763 break;
764 case SSB_ADM_TYPE1:
765 assert(!(adm & SSB_ADM_NEG)); /* unsupported */
766 size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
767 break;
768 case SSB_ADM_TYPE2:
769 assert(!(adm & SSB_ADM_NEG)); /* unsupported */
770 size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
771 break;
772 default:
773 assert(0);
774 }
775 size = (1 << (size + 1));
776
777 return size;
778 }
779 EXPORT_SYMBOL(ssb_admatch_size);
780
781 static int __init ssb_modinit(void)
782 {
783 int err;
784
785 ssb_bustype.name = "ssb";
786 err = bus_register(&ssb_bustype);
787 if (err)
788 return err;
789
790 /* Maybe we already registered some buses at early boot.
791 * Check for this and attach them
792 */
793 ssb_buses_lock();
794 err = ssb_attach_queued_buses();
795 ssb_buses_unlock();
796
797 return err;
798 }
799 subsys_initcall(ssb_modinit);
800
801 static void __exit ssb_modexit(void)
802 {
803 bus_unregister(&ssb_bustype);
804 }
805 module_exit(ssb_modexit)
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