target/linux/amazon-2.6/files/arch/mips/amazon/pci.c

   1 /*
   2  *  Carsten Langgaard, carstenl@mips.com
   3  *  Copyright (C) 1999, 2000 MIPS Technologies, Inc.  All rights reserved.
   4  *  Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
   5  *
   6  *  This program is free software; you can distribute it and/or modify it
   7  *  under the terms of the GNU General Public License (Version 2) as
   8  *  published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  *  for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License along
  16  *  with this program; if not, write to the Free Software Foundation, Inc.,
  17  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  18  */
  19
  20 /* FIXME: convert nasty volatile register derefs to readl/writel calls */
  21
  22 #include <linux/types.h>
  23 #include <linux/pci.h>
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <asm/io.h>
  29 #include <asm/paccess.h>
  30 #include <asm/amazon/irq.h>
  31 #include <asm/amazon/amazon.h>
  32
  33 #define AMAZON_PCI_REG32( addr )                  (*(volatile u32 *)(addr))
  34 #ifndef AMAZON_PCI_MEM_BASE
  35 #define AMAZON_PCI_MEM_BASE    0xb2000000
  36 #endif
  37 #define AMAZON_PCI_MEM_SIZE    0x00400000
  38 #define AMAZON_PCI_IO_BASE     0xb2400000
  39 #define AMAZON_PCI_IO_SIZE     0x00002000
  40
  41 #define AMAZON_PCI_CFG_BUSNUM_SHF 16
  42 #define AMAZON_PCI_CFG_DEVNUM_SHF 11
  43 #define AMAZON_PCI_CFG_FUNNUM_SHF 8
  44
  45 #define PCI_ACCESS_READ  0
  46 #define PCI_ACCESS_WRITE 1
  47
  48 static inline u32 amazon_r32(u32 addr)
  49 {
  50         u32 *ptr = (u32 *) addr;
  51         return __raw_readl(ptr);
  52 }
  53
  54 static inline void amazon_w32(u32 addr, u32 val)
  55 {
  56         u32 *ptr = (u32 *) addr;
  57         __raw_writel(val, ptr);
  58 }
  59
  60
  61 static struct resource pci_io_resource = {
  62         .name = "io pci IO space",
  63 #if 0
  64         .start = AMAZON_PCI_IO_BASE,
  65         .end = AMAZON_PCI_IO_BASE + AMAZON_PCI_IO_SIZE - 1,
  66 #endif
  67         .start = 0,
  68         .end = AMAZON_PCI_IO_SIZE - 1,
  69         .flags = IORESOURCE_IO
  70 };
  71
  72 static struct resource pci_mem_resource = {
  73         .name = "ext pci memory space",
  74         .start = AMAZON_PCI_MEM_BASE,
  75         .end = AMAZON_PCI_MEM_BASE + AMAZON_PCI_MEM_SIZE - 1,
  76         .flags = IORESOURCE_MEM
  77 };
  78
  79 static inline u32 amazon_pci_swap(u32 val)
  80 {
  81 #ifdef CONFIG_AMAZON_PCI_HW_SWAP
  82         return swab32(val);
  83 #else
  84         return val;
  85 #endif
  86 }
  87
  88 static int amazon_pci_config_access(unsigned char access_type,
  89         struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
  90 {
  91         unsigned long flags;
  92         u32 pci_addr;
  93         u32 val;
  94         int ret;
  95
  96         /* Amazon support slot from 0 to 15 */
  97         /* devfn 0 & 0x20 is itself */
  98         if ((bus != 0) || (devfn == 0) || (devfn == 0x20))
  99                 return 1;
 100
 101         pci_addr=AMAZON_PCI_CFG_BASE |
 102                 bus->number << AMAZON_PCI_CFG_BUSNUM_SHF |
 103                 devfn << AMAZON_PCI_CFG_FUNNUM_SHF |
 104                 (where & ~0x3);
 105
 106         local_irq_save(flags);
 107         if (access_type == PCI_ACCESS_WRITE) {
 108                 val = amazon_pci_swap(*data);
 109                 ret = put_dbe(val, (u32 *)pci_addr);
 110         } else {
 111                 ret = get_dbe(val, (u32 *)pci_addr);
 112                 *data = amazon_pci_swap(val);
 113         }
 114
 115         amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)));
 116         amazon_w32(STATUS_COMMAND_ADDR, amazon_r32(STATUS_COMMAND_ADDR));
 117         amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)));
 118         local_irq_restore(flags);
 119
 120         return ret;
 121 }
 122
 123
 124 static int amazon_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
 125 {
 126         u32 data = 0;
 127         int ret = PCIBIOS_SUCCESSFUL;
 128
 129         if (amazon_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) {
 130                 data = ~0;
 131                 ret = -1;
 132         }
 133
 134         switch (size) {
 135                 case 1:
 136                         *((u8 *) val) = (data >> ((where & 3) << 3)) & 0xff;
 137                         break;
 138                 case 2:
 139                         *((u16 *) val) = (data >> ((where & 3) << 3)) & 0xffff;
 140                         break;
 141                 case 4:
 142                         *val = data;
 143                         break;
 144                 default:
 145                         return -1;
 146         }
 147
 148         return ret;
 149 }
 150
 151
 152 static int amazon_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
 153 {
 154         if (size != 4) {
 155                 u32 data;
 156
 157                 if (amazon_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 158                         return -1;
 159
 160                 if (size == 1)
 161                         val = (data & ~(0xff << ((where & 3) << 3))) | (val << ((where & 3) << 3));
 162                 else if (size == 2)
 163                         val = (data & ~(0xffff << ((where & 3) << 3))) | (val << ((where & 3) << 3));
 164                 else
 165                         return -1;
 166         }
 167
 168         if (amazon_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
 169                return -1;
 170
 171         return PCIBIOS_SUCCESSFUL;
 172 }
 173
 174 static struct pci_ops amazon_pci_ops = {
 175         amazon_pci_read,
 176         amazon_pci_write
 177 };
 178
 179 static struct pci_controller amazon_pci_controller = {
 180         .pci_ops = &amazon_pci_ops,
 181         .mem_resource = &pci_mem_resource,
 182         .io_resource = &pci_io_resource
 183 };
 184
 185 int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 186 {
 187         switch (slot) {
 188                 case 13:
 189                         /* IDSEL = AD29 --> USB Host Controller */
 190                         return INT_NUM_IM2_IRL15;
 191                 case 14:
 192                         /* IDSEL = AD30 --> mini PCI connector */
 193                         return INT_NUM_IM2_IRL14;
 194                 default:
 195                         printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot, pin);
 196                         return 0;
 197         }
 198 }
 199
 200 int pcibios_plat_dev_init(struct pci_dev *dev)
 201 {
 202         switch(dev->irq) {
 203                 case INT_NUM_IM2_IRL15:
 204                         /*
 205                          * IDSEL = AD29 --> USB Host Controller
 206                          * PCI_INTA/B/C--GPIO Port0.2--EXIN3
 207                          * IN/ALT0:1 ALT1:0
 208                          * PULL UP
 209                          */
 210                         (*AMAZON_GPIO_P0_DIR) = (*AMAZON_GPIO_P0_DIR) & 0xfffffffb;
 211                         (*AMAZON_GPIO_P0_ALTSEL0) = (*AMAZON_GPIO_P0_ALTSEL0)| 4;
 212                         (*AMAZON_GPIO_P0_ALTSEL1) = (*AMAZON_GPIO_P0_ALTSEL1)& 0xfffffffb;
 213                         (*AMAZON_GPIO_P0_PUDSEL) =  (*AMAZON_GPIO_P0_PUDSEL) | 4;
 214                         (*AMAZON_GPIO_P0_PUDEN) = (*AMAZON_GPIO_P0_PUDEN) | 4;
 215                         //External Interrupt Node
 216                         (*AMAZON_ICU_EXTINTCR) = (*AMAZON_ICU_EXTINTCR)|0x6000; /* Low Level triggered */
 217                         (*AMAZON_ICU_IRNEN) = (*AMAZON_ICU_IRNEN)|0x8;
 218                         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 219                         break;
 220                 case INT_NUM_IM2_IRL14:
 221                         /*
 222                          * IDSEL = AD30 --> mini PCI connector
 223                          * PCI_INTA--GPIO Port0.1--EXIN2
 224                          * IN/ALT0:1 ALT1:0
 225                          * PULL UP
 226                          */
 227                         (*AMAZON_GPIO_P0_DIR) = (*AMAZON_GPIO_P0_DIR) & 0xfffffffd;
 228                         (*AMAZON_GPIO_P0_ALTSEL0) = (*AMAZON_GPIO_P0_ALTSEL0)| 2;
 229                         (*AMAZON_GPIO_P0_ALTSEL1) = (*AMAZON_GPIO_P0_ALTSEL1)& 0xfffffffd;
 230                         (*AMAZON_GPIO_P0_PUDSEL) =  (*AMAZON_GPIO_P0_PUDSEL) | 2;
 231                         (*AMAZON_GPIO_P0_PUDEN) = (*AMAZON_GPIO_P0_PUDEN) | 2;
 232                         //External Interrupt Node
 233                         (*AMAZON_ICU_EXTINTCR) = (*AMAZON_ICU_EXTINTCR)|0x600;
 234                         (*AMAZON_ICU_IRNEN) = (*AMAZON_ICU_IRNEN)|0x4;
 235                         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 236                         break;
 237                 default:
 238                         return 1;
 239         }
 240         return 0;
 241 }
 242
 243 int amazon_pci_init(void)
 244 {
 245         u32 temp_buffer;
 246
 247 #ifdef CONFIG_AMAZON_PCI_HW_SWAP
 248         AMAZON_PCI_REG32(IRM) = AMAZON_PCI_REG32(IRM) | (1<<27) | (1<<28);
 249         wmb();
 250 #endif
 251
 252         AMAZON_PCI_REG32(CLOCK_CONTROL) = AMAZON_PCI_REG32(CLOCK_CONTROL) | (1<<ARB_CTRL_bit);
 253         amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)));
 254
 255         AMAZON_PCI_REG32(STATUS_COMMAND_ADDR) = AMAZON_PCI_REG32(STATUS_COMMAND_ADDR) | (1<<BUS_MASTER_ENABLE_BIT) |(1<<MEM_SPACE_ENABLE_BIT);
 256
 257         temp_buffer = AMAZON_PCI_REG32(PCI_ARB_CTRL_STATUS_ADDR);
 258         temp_buffer = temp_buffer | (1<< INTERNAL_ARB_ENABLE_BIT);
 259         temp_buffer = temp_buffer & ~(3<< PCI_MASTER0_REQ_MASK_2BITS);
 260         temp_buffer = temp_buffer & ~(3<< PCI_MASTER0_GNT_MASK_2BITS);
 261
 262         /* flash */
 263         temp_buffer = temp_buffer & ~(3<< PCI_MASTER1_REQ_MASK_2BITS);
 264         temp_buffer = temp_buffer & ~(3<< PCI_MASTER1_GNT_MASK_2BITS);
 265
 266         /* external master */
 267         temp_buffer = temp_buffer & ~(3<< PCI_MASTER2_REQ_MASK_2BITS);
 268         temp_buffer = temp_buffer & ~(3<< PCI_MASTER2_GNT_MASK_2BITS);
 269
 270         AMAZON_PCI_REG32(PCI_ARB_CTRL_STATUS_ADDR) = temp_buffer;
 271         wmb();
 272
 273         AMAZON_PCI_REG32(FPI_ADDRESS_MAP_0) = 0xb2000000;
 274         AMAZON_PCI_REG32(FPI_ADDRESS_MAP_1) = 0xb2100000;
 275         AMAZON_PCI_REG32(FPI_ADDRESS_MAP_2) = 0xb2200000;
 276         AMAZON_PCI_REG32(FPI_ADDRESS_MAP_3) = 0xb2300000;
 277         AMAZON_PCI_REG32(FPI_ADDRESS_MAP_4) = 0xb2400000;
 278         AMAZON_PCI_REG32(FPI_ADDRESS_MAP_5) = 0xb2500000;
 279         AMAZON_PCI_REG32(FPI_ADDRESS_MAP_6) = 0xb2600000;
 280         AMAZON_PCI_REG32(FPI_ADDRESS_MAP_7) = 0xb2700000;
 281
 282         AMAZON_PCI_REG32(BAR11_MASK) = 0x0f000008;
 283         AMAZON_PCI_REG32(PCI_ADDRESS_MAP_11) = 0x0;
 284         AMAZON_PCI_REG32(BAR1_ADDR) = 0x0;
 285         amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)));
 286         //use 8 dw burse length
 287         AMAZON_PCI_REG32(FPI_BURST_LENGTH) = 0x303;
 288
 289         set_io_port_base(ioremap(AMAZON_PCI_IO_BASE, AMAZON_PCI_IO_SIZE));
 290         register_pci_controller(&amazon_pci_controller);
 291         return 0;
 292 }
 293 arch_initcall(amazon_pci_init);