target/linux/lantiq/patches-2.6.39/0003-MIPS-Lantiq-Add-PCI-controller-support.patch

   1 From 08127ed36bad367903591bbf0f244179683ccb28 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 30 Mar 2011 09:27:49 +0200
   4 Subject: [PATCH 03/13] MIPS: Lantiq: Add PCI controller support.
   5
   6 The Lantiq family of SoCs have a EBU (External Bus Unit). This patch adds
   7 the driver that allows us to use the EBU as a PCI controller. In order for
   8 PCI to work the EBU is set to endianess swap all the data. In addition we
   9 need to make use of SWAP_IO_SPACE for device->host DMA to work.
  10
  11 The clock of the PCI works in several modes (internal/external). If this
  12 is not configured correctly the SoC will hang.
  13
  14 Signed-off-by: John Crispin <blogic@openwrt.org>
  15 Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
  16 Cc: linux-mips@linux-mips.org
  17 Patchwork: https://patchwork.linux-mips.org/patch/2250/
  18 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  19 ---
  20  .../mips/include/asm/mach-lantiq/lantiq_platform.h |   46 +++
  21  arch/mips/pci/Makefile                             |    1 +
  22  arch/mips/pci/ops-lantiq.c                         |  116 ++++++++
  23  arch/mips/pci/pci-lantiq.c                         |  297 ++++++++++++++++++++
  24  arch/mips/pci/pci-lantiq.h                         |   18 ++
  25  5 files changed, 478 insertions(+), 0 deletions(-)
  26  create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_platform.h
  27  create mode 100644 arch/mips/pci/ops-lantiq.c
  28  create mode 100644 arch/mips/pci/pci-lantiq.c
  29  create mode 100644 arch/mips/pci/pci-lantiq.h
  30
  31 --- /dev/null
  32 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
  33 @@ -0,0 +1,46 @@
  34 +/*
  35 + *  This program is free software; you can redistribute it and/or modify it
  36 + *  under the terms of the GNU General Public License version 2 as published
  37 + *  by the Free Software Foundation.
  38 + *
  39 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
  40 + */
  41 +
  42 +#ifndef _LANTIQ_PLATFORM_H__
  43 +#define _LANTIQ_PLATFORM_H__
  44 +
  45 +#include <linux/mtd/partitions.h>
  46 +
  47 +/* struct used to pass info to the pci core */
  48 +enum {
  49 +       PCI_CLOCK_INT = 0,
  50 +       PCI_CLOCK_EXT
  51 +};
  52 +
  53 +#define PCI_EXIN0      0x0001
  54 +#define PCI_EXIN1      0x0002
  55 +#define PCI_EXIN2      0x0004
  56 +#define PCI_EXIN3      0x0008
  57 +#define PCI_EXIN4      0x0010
  58 +#define PCI_EXIN5      0x0020
  59 +#define PCI_EXIN_MAX   6
  60 +
  61 +#define PCI_GNT1       0x0040
  62 +#define PCI_GNT2       0x0080
  63 +#define PCI_GNT3       0x0100
  64 +#define PCI_GNT4       0x0200
  65 +
  66 +#define PCI_REQ1       0x0400
  67 +#define PCI_REQ2       0x0800
  68 +#define PCI_REQ3       0x1000
  69 +#define PCI_REQ4       0x2000
  70 +#define PCI_REQ_SHIFT  10
  71 +#define PCI_REQ_MASK   0xf
  72 +
  73 +struct ltq_pci_data {
  74 +       int clock;
  75 +       int gpio;
  76 +       int irq[16];
  77 +};
  78 +
  79 +#endif
  80 --- a/arch/mips/pci/Makefile
  81 +++ b/arch/mips/pci/Makefile
  82 @@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_SB1250)   += fixup-sb1
  83  obj-$(CONFIG_SIBYTE_BCM112X)   += fixup-sb1250.o pci-sb1250.o
  84  obj-$(CONFIG_SIBYTE_BCM1x80)   += pci-bcm1480.o pci-bcm1480ht.o
  85  obj-$(CONFIG_SNI_RM)           += fixup-sni.o ops-sni.o
  86 +obj-$(CONFIG_SOC_XWAY)         += pci-lantiq.o ops-lantiq.o
  87  obj-$(CONFIG_TANBAC_TB0219)    += fixup-tb0219.o
  88  obj-$(CONFIG_TANBAC_TB0226)    += fixup-tb0226.o
  89  obj-$(CONFIG_TANBAC_TB0287)    += fixup-tb0287.o
  90 --- /dev/null
  91 +++ b/arch/mips/pci/ops-lantiq.c
  92 @@ -0,0 +1,116 @@
  93 +/*
  94 + *  This program is free software; you can redistribute it and/or modify it
  95 + *  under the terms of the GNU General Public License version 2 as published
  96 + *  by the Free Software Foundation.
  97 + *
  98 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
  99 + */
 100 +
 101 +#include <linux/types.h>
 102 +#include <linux/pci.h>
 103 +#include <linux/kernel.h>
 104 +#include <linux/init.h>
 105 +#include <linux/delay.h>
 106 +#include <linux/mm.h>
 107 +#include <asm/addrspace.h>
 108 +#include <linux/vmalloc.h>
 109 +
 110 +#include <lantiq_soc.h>
 111 +
 112 +#include "pci-lantiq.h"
 113 +
 114 +#define LTQ_PCI_CFG_BUSNUM_SHF 16
 115 +#define LTQ_PCI_CFG_DEVNUM_SHF 11
 116 +#define LTQ_PCI_CFG_FUNNUM_SHF 8
 117 +
 118 +#define PCI_ACCESS_READ  0
 119 +#define PCI_ACCESS_WRITE 1
 120 +
 121 +static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus,
 122 +       unsigned int devfn, unsigned int where, u32 *data)
 123 +{
 124 +       unsigned long cfg_base;
 125 +       unsigned long flags;
 126 +       u32 temp;
 127 +
 128 +       /* we support slot from 0 to 15 dev_fn & 0x68 (AD29) is the
 129 +          SoC itself */
 130 +       if ((bus->number != 0) || ((devfn & 0xf8) > 0x78)
 131 +               || ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68))
 132 +               return 1;
 133 +
 134 +       spin_lock_irqsave(&ebu_lock, flags);
 135 +
 136 +       cfg_base = (unsigned long) ltq_pci_mapped_cfg;
 137 +       cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn <<
 138 +                       LTQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
 139 +
 140 +       /* Perform access */
 141 +       if (access_type == PCI_ACCESS_WRITE) {
 142 +               ltq_w32(swab32(*data), ((u32 *)cfg_base));
 143 +       } else {
 144 +               *data = ltq_r32(((u32 *)(cfg_base)));
 145 +               *data = swab32(*data);
 146 +       }
 147 +       wmb();
 148 +
 149 +       /* clean possible Master abort */
 150 +       cfg_base = (unsigned long) ltq_pci_mapped_cfg;
 151 +       cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
 152 +       temp = ltq_r32(((u32 *)(cfg_base)));
 153 +       temp = swab32(temp);
 154 +       cfg_base = (unsigned long) ltq_pci_mapped_cfg;
 155 +       cfg_base |= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
 156 +       ltq_w32(temp, ((u32 *)cfg_base));
 157 +
 158 +       spin_unlock_irqrestore(&ebu_lock, flags);
 159 +
 160 +       if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
 161 +               return 1;
 162 +
 163 +       return 0;
 164 +}
 165 +
 166 +int ltq_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
 167 +       int where, int size, u32 *val)
 168 +{
 169 +       u32 data = 0;
 170 +
 171 +       if (ltq_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 172 +               return PCIBIOS_DEVICE_NOT_FOUND;
 173 +
 174 +       if (size == 1)
 175 +               *val = (data >> ((where & 3) << 3)) & 0xff;
 176 +       else if (size == 2)
 177 +               *val = (data >> ((where & 3) << 3)) & 0xffff;
 178 +       else
 179 +               *val = data;
 180 +
 181 +       return PCIBIOS_SUCCESSFUL;
 182 +}
 183 +
 184 +int ltq_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
 185 +       int where, int size, u32 val)
 186 +{
 187 +       u32 data = 0;
 188 +
 189 +       if (size == 4) {
 190 +               data = val;
 191 +       } else {
 192 +               if (ltq_pci_config_access(PCI_ACCESS_READ, bus,
 193 +                               devfn, where, &data))
 194 +                       return PCIBIOS_DEVICE_NOT_FOUND;
 195 +
 196 +               if (size == 1)
 197 +                       data = (data & ~(0xff << ((where & 3) << 3))) |
 198 +                               (val << ((where & 3) << 3));
 199 +               else if (size == 2)
 200 +                       data = (data & ~(0xffff << ((where & 3) << 3))) |
 201 +                               (val << ((where & 3) << 3));
 202 +       }
 203 +
 204 +       if (ltq_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 205 +               return PCIBIOS_DEVICE_NOT_FOUND;
 206 +
 207 +       return PCIBIOS_SUCCESSFUL;
 208 +}
 209 --- /dev/null
 210 +++ b/arch/mips/pci/pci-lantiq.c
 211 @@ -0,0 +1,297 @@
 212 +/*
 213 + *  This program is free software; you can redistribute it and/or modify it
 214 + *  under the terms of the GNU General Public License version 2 as published
 215 + *  by the Free Software Foundation.
 216 + *
 217 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 218 + */
 219 +
 220 +#include <linux/types.h>
 221 +#include <linux/pci.h>
 222 +#include <linux/kernel.h>
 223 +#include <linux/init.h>
 224 +#include <linux/delay.h>
 225 +#include <linux/mm.h>
 226 +#include <linux/vmalloc.h>
 227 +#include <linux/platform_device.h>
 228 +
 229 +#include <asm/pci.h>
 230 +#include <asm/gpio.h>
 231 +#include <asm/addrspace.h>
 232 +
 233 +#include <lantiq_soc.h>
 234 +#include <lantiq_irq.h>
 235 +#include <lantiq_platform.h>
 236 +
 237 +#include "pci-lantiq.h"
 238 +
 239 +#define LTQ_PCI_CFG_BASE               0x17000000
 240 +#define LTQ_PCI_CFG_SIZE               0x00008000
 241 +#define LTQ_PCI_MEM_BASE               0x18000000
 242 +#define LTQ_PCI_MEM_SIZE               0x02000000
 243 +#define LTQ_PCI_IO_BASE                        0x1AE00000
 244 +#define LTQ_PCI_IO_SIZE                        0x00200000
 245 +
 246 +#define PCI_CR_FCI_ADDR_MAP0           0x00C0
 247 +#define PCI_CR_FCI_ADDR_MAP1           0x00C4
 248 +#define PCI_CR_FCI_ADDR_MAP2           0x00C8
 249 +#define PCI_CR_FCI_ADDR_MAP3           0x00CC
 250 +#define PCI_CR_FCI_ADDR_MAP4           0x00D0
 251 +#define PCI_CR_FCI_ADDR_MAP5           0x00D4
 252 +#define PCI_CR_FCI_ADDR_MAP6           0x00D8
 253 +#define PCI_CR_FCI_ADDR_MAP7           0x00DC
 254 +#define PCI_CR_CLK_CTRL                        0x0000
 255 +#define PCI_CR_PCI_MOD                 0x0030
 256 +#define PCI_CR_PC_ARB                  0x0080
 257 +#define PCI_CR_FCI_ADDR_MAP11hg                0x00E4
 258 +#define PCI_CR_BAR11MASK               0x0044
 259 +#define PCI_CR_BAR12MASK               0x0048
 260 +#define PCI_CR_BAR13MASK               0x004C
 261 +#define PCI_CS_BASE_ADDR1              0x0010
 262 +#define PCI_CR_PCI_ADDR_MAP11          0x0064
 263 +#define PCI_CR_FCI_BURST_LENGTH                0x00E8
 264 +#define PCI_CR_PCI_EOI                 0x002C
 265 +#define PCI_CS_STS_CMD                 0x0004
 266 +
 267 +#define PCI_MASTER0_REQ_MASK_2BITS     8
 268 +#define PCI_MASTER1_REQ_MASK_2BITS     10
 269 +#define PCI_MASTER2_REQ_MASK_2BITS     12
 270 +#define INTERNAL_ARB_ENABLE_BIT                0
 271 +
 272 +#define LTQ_CGU_IFCCR          0x0018
 273 +#define LTQ_CGU_PCICR          0x0034
 274 +
 275 +#define ltq_pci_w32(x, y)      ltq_w32((x), ltq_pci_membase + (y))
 276 +#define ltq_pci_r32(x)         ltq_r32(ltq_pci_membase + (x))
 277 +
 278 +#define ltq_pci_cfg_w32(x, y)  ltq_w32((x), ltq_pci_mapped_cfg + (y))
 279 +#define ltq_pci_cfg_r32(x)     ltq_r32(ltq_pci_mapped_cfg + (x))
 280 +
 281 +struct ltq_pci_gpio_map {
 282 +       int pin;
 283 +       int alt0;
 284 +       int alt1;
 285 +       int dir;
 286 +       char *name;
 287 +};
 288 +
 289 +/* the pci core can make use of the following gpios */
 290 +static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = {
 291 +       { 0, 1, 0, 0, "pci-exin0" },
 292 +       { 1, 1, 0, 0, "pci-exin1" },
 293 +       { 2, 1, 0, 0, "pci-exin2" },
 294 +       { 39, 1, 0, 0, "pci-exin3" },
 295 +       { 10, 1, 0, 0, "pci-exin4" },
 296 +       { 9, 1, 0, 0, "pci-exin5" },
 297 +       { 30, 1, 0, 1, "pci-gnt1" },
 298 +       { 23, 1, 0, 1, "pci-gnt2" },
 299 +       { 19, 1, 0, 1, "pci-gnt3" },
 300 +       { 38, 1, 0, 1, "pci-gnt4" },
 301 +       { 29, 1, 0, 0, "pci-req1" },
 302 +       { 31, 1, 0, 0, "pci-req2" },
 303 +       { 3, 1, 0, 0, "pci-req3" },
 304 +       { 37, 1, 0, 0, "pci-req4" },
 305 +};
 306 +
 307 +__iomem void *ltq_pci_mapped_cfg;
 308 +static __iomem void *ltq_pci_membase;
 309 +
 310 +int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL;
 311 +
 312 +/* Since the PCI REQ pins can be reused for other functionality, make it
 313 +   possible to exclude those from interpretation by the PCI controller */
 314 +static int ltq_pci_req_mask = 0xf;
 315 +
 316 +static int *ltq_pci_irq_map;
 317 +
 318 +struct pci_ops ltq_pci_ops = {
 319 +       .read   = ltq_pci_read_config_dword,
 320 +       .write  = ltq_pci_write_config_dword
 321 +};
 322 +
 323 +static struct resource pci_io_resource = {
 324 +       .name   = "pci io space",
 325 +       .start  = LTQ_PCI_IO_BASE,
 326 +       .end    = LTQ_PCI_IO_BASE + LTQ_PCI_IO_SIZE - 1,
 327 +       .flags  = IORESOURCE_IO
 328 +};
 329 +
 330 +static struct resource pci_mem_resource = {
 331 +       .name   = "pci memory space",
 332 +       .start  = LTQ_PCI_MEM_BASE,
 333 +       .end    = LTQ_PCI_MEM_BASE + LTQ_PCI_MEM_SIZE - 1,
 334 +       .flags  = IORESOURCE_MEM
 335 +};
 336 +
 337 +static struct pci_controller ltq_pci_controller = {
 338 +       .pci_ops        = &ltq_pci_ops,
 339 +       .mem_resource   = &pci_mem_resource,
 340 +       .mem_offset     = 0x00000000UL,
 341 +       .io_resource    = &pci_io_resource,
 342 +       .io_offset      = 0x00000000UL,
 343 +};
 344 +
 345 +int pcibios_plat_dev_init(struct pci_dev *dev)
 346 +{
 347 +       if (ltqpci_plat_dev_init)
 348 +               return ltqpci_plat_dev_init(dev);
 349 +
 350 +       return 0;
 351 +}
 352 +
 353 +static u32 ltq_calc_bar11mask(void)
 354 +{
 355 +       u32 mem, bar11mask;
 356 +
 357 +       /* BAR11MASK value depends on available memory on system. */
 358 +       mem = num_physpages * PAGE_SIZE;
 359 +       bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
 360 +
 361 +       return bar11mask;
 362 +}
 363 +
 364 +static void ltq_pci_setup_gpio(int gpio)
 365 +{
 366 +       int i;
 367 +       for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) {
 368 +               if (gpio & (1 << i)) {
 369 +                       ltq_gpio_request(ltq_pci_gpio_map[i].pin,
 370 +                               ltq_pci_gpio_map[i].alt0,
 371 +                               ltq_pci_gpio_map[i].alt1,
 372 +                               ltq_pci_gpio_map[i].dir,
 373 +                               ltq_pci_gpio_map[i].name);
 374 +               }
 375 +       }
 376 +       ltq_gpio_request(21, 0, 0, 1, "pci-reset");
 377 +       ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK;
 378 +}
 379 +
 380 +static int __devinit ltq_pci_startup(struct ltq_pci_data *conf)
 381 +{
 382 +       u32 temp_buffer;
 383 +
 384 +       /* set clock to 33Mhz */
 385 +       ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR);
 386 +       ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR);
 387 +
 388 +       /* external or internal clock ? */
 389 +       if (conf->clock) {
 390 +               ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~(1 << 16),
 391 +                       LTQ_CGU_IFCCR);
 392 +               ltq_cgu_w32((1 << 30), LTQ_CGU_PCICR);
 393 +       } else {
 394 +               ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | (1 << 16),
 395 +                       LTQ_CGU_IFCCR);
 396 +               ltq_cgu_w32((1 << 31) | (1 << 30), LTQ_CGU_PCICR);
 397 +       }
 398 +
 399 +       /* setup pci clock and gpis used by pci */
 400 +       ltq_pci_setup_gpio(conf->gpio);
 401 +
 402 +       /* enable auto-switching between PCI and EBU */
 403 +       ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
 404 +
 405 +       /* busy, i.e. configuration is not done, PCI access has to be retried */
 406 +       ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
 407 +       wmb();
 408 +       /* BUS Master/IO/MEM access */
 409 +       ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
 410 +
 411 +       /* enable external 2 PCI masters */
 412 +       temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB);
 413 +       temp_buffer &= (~(ltq_pci_req_mask << 16));
 414 +       /* enable internal arbiter */
 415 +       temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
 416 +       /* enable internal PCI master reqest */
 417 +       temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
 418 +
 419 +       /* enable EBU request */
 420 +       temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
 421 +
 422 +       /* enable all external masters request */
 423 +       temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
 424 +       ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB);
 425 +       wmb();
 426 +
 427 +       /* setup BAR memory regions */
 428 +       ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
 429 +       ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
 430 +       ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
 431 +       ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
 432 +       ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
 433 +       ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
 434 +       ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
 435 +       ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
 436 +       ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
 437 +       ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK);
 438 +       ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11);
 439 +       ltq_pci_w32(0, PCI_CS_BASE_ADDR1);
 440 +       /* both TX and RX endian swap are enabled */
 441 +       ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
 442 +       wmb();
 443 +       ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000,
 444 +               PCI_CR_BAR12MASK);
 445 +       ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000,
 446 +               PCI_CR_BAR13MASK);
 447 +       /*use 8 dw burst length */
 448 +       ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
 449 +       ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
 450 +       wmb();
 451 +
 452 +       /* setup irq line */
 453 +       ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON);
 454 +       ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);
 455 +
 456 +       /* toggle reset pin */
 457 +       __gpio_set_value(21, 0);
 458 +       wmb();
 459 +       mdelay(1);
 460 +       __gpio_set_value(21, 1);
 461 +       return 0;
 462 +}
 463 +
 464 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 465 +{
 466 +       if (ltq_pci_irq_map[slot])
 467 +               return ltq_pci_irq_map[slot];
 468 +       printk(KERN_ERR "ltq_pci: trying to map irq for unknown slot %d\n",
 469 +               slot);
 470 +
 471 +       return 0;
 472 +}
 473 +
 474 +static int __devinit ltq_pci_probe(struct platform_device *pdev)
 475 +{
 476 +       struct ltq_pci_data *ltq_pci_data =
 477 +               (struct ltq_pci_data *) pdev->dev.platform_data;
 478 +       pci_probe_only = 0;
 479 +       ltq_pci_irq_map = ltq_pci_data->irq;
 480 +       ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE);
 481 +       ltq_pci_mapped_cfg =
 482 +               ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE);
 483 +       ltq_pci_controller.io_map_base =
 484 +               (unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1);
 485 +       ltq_pci_startup(ltq_pci_data);
 486 +       register_pci_controller(&ltq_pci_controller);
 487 +
 488 +       return 0;
 489 +}
 490 +
 491 +static struct platform_driver
 492 +ltq_pci_driver = {
 493 +       .probe = ltq_pci_probe,
 494 +       .driver = {
 495 +               .name = "ltq_pci",
 496 +               .owner = THIS_MODULE,
 497 +       },
 498 +};
 499 +
 500 +int __init pcibios_init(void)
 501 +{
 502 +       int ret = platform_driver_register(&ltq_pci_driver);
 503 +       if (ret)
 504 +               printk(KERN_INFO "ltq_pci: Error registering platfom driver!");
 505 +       return ret;
 506 +}
 507 +
 508 +arch_initcall(pcibios_init);
 509 --- /dev/null
 510 +++ b/arch/mips/pci/pci-lantiq.h
 511 @@ -0,0 +1,18 @@
 512 +/*
 513 + *  This program is free software; you can redistribute it and/or modify it
 514 + *  under the terms of the GNU General Public License version 2 as published
 515 + *  by the Free Software Foundation.
 516 + *
 517 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 518 + */
 519 +
 520 +#ifndef _LTQ_PCI_H__
 521 +#define _LTQ_PCI_H__
 522 +
 523 +extern __iomem void *ltq_pci_mapped_cfg;
 524 +extern int ltq_pci_read_config_dword(struct pci_bus *bus,
 525 +       unsigned int devfn, int where, int size, u32 *val);
 526 +extern int ltq_pci_write_config_dword(struct pci_bus *bus,
 527 +       unsigned int devfn, int where, int size, u32 val);
 528 +
 529 +#endif