[package] 6in4, 6to4: prevent starting the tunnel if kmod-sit is not yet loaded ...
[openwrt.git] / target / linux / ubicom32 / files / drivers / mmc / host / ubicom32sd.c
1 /*
2 * drivers/mmc/host/ubicom32sd.c
3 * Ubicom32 Secure Digital Host Controller Interface driver
4 *
5 * (C) Copyright 2009, Ubicom, Inc.
6 *
7 * This file is part of the Ubicom32 Linux Kernel Port.
8 *
9 * The Ubicom32 Linux Kernel Port is free software: you can redistribute
10 * it and/or modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation, either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * The Ubicom32 Linux Kernel Port is distributed in the hope that it
15 * will be useful, but WITHOUT ANY WARRANTY; without even the implied
16 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
17 * the GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with the Ubicom32 Linux Kernel Port. If not,
21 * see <http://www.gnu.org/licenses/>.
22 */
23
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/delay.h>
27 #include <linux/scatterlist.h>
28 #include <linux/leds.h>
29 #include <linux/gpio.h>
30 #include <linux/mmc/host.h>
31
32 #include <asm/ubicom32sd.h>
33
34 #define DRIVER_NAME "ubicom32sd"
35
36 #define sd_printk(...)
37 //#define sd_printk printk
38
39 #define SDTIO_VP_VERSION 3
40
41 #define SDTIO_MAX_SG_BLOCKS 16
42
43 enum sdtio_commands {
44 SDTIO_COMMAND_NOP,
45 SDTIO_COMMAND_SETUP,
46 SDTIO_COMMAND_SETUP_SDIO,
47 SDTIO_COMMAND_EXECUTE,
48 SDTIO_COMMAND_RESET,
49 };
50
51 #define SDTIO_COMMAND_SHIFT 24
52 #define SDTIO_COMMAND_FLAG_STOP_RSP_CRC (1 << 10)
53 #define SDTIO_COMMAND_FLAG_STOP_RSP_136 (1 << 9)
54 #define SDTIO_COMMAND_FLAG_STOP_RSP (1 << 8)
55 #define SDTIO_COMMAND_FLAG_STOP_CMD (1 << 7)
56 #define SDTIO_COMMAND_FLAG_DATA_STREAM (1 << 6)
57 #define SDTIO_COMMAND_FLAG_DATA_RD (1 << 5)
58 #define SDTIO_COMMAND_FLAG_DATA_WR (1 << 4)
59 #define SDTIO_COMMAND_FLAG_CMD_RSP_CRC (1 << 3)
60 #define SDTIO_COMMAND_FLAG_CMD_RSP_136 (1 << 2)
61 #define SDTIO_COMMAND_FLAG_CMD_RSP (1 << 1)
62 #define SDTIO_COMMAND_FLAG_CMD (1 << 0)
63
64 /*
65 * SDTIO_COMMAND_SETUP_SDIO
66 */
67 #define SDTIO_COMMAND_FLAG_SDIO_INT_EN (1 << 0)
68
69 /*
70 * SDTIO_COMMAND_SETUP
71 * clock speed in arg
72 */
73 #define SDTIO_COMMAND_FLAG_4BIT (1 << 3)
74 #define SDTIO_COMMAND_FLAG_1BIT (1 << 2)
75 #define SDTIO_COMMAND_FLAG_SET_CLOCK (1 << 1)
76 #define SDTIO_COMMAND_FLAG_SET_WIDTH (1 << 0)
77
78 #define SDTIO_COMMAND_FLAG_CMD_RSP_MASK (SDTIO_COMMAND_FLAG_CMD_RSP | SDTIO_COMMAND_FLAG_CMD_RSP_136)
79 #define SDTIO_COMMAND_FLAG_STOP_RSP_MASK (SDTIO_COMMAND_FLAG_STOP_RSP | SDTIO_COMMAND_FLAG_STOP_RSP_136)
80 #define SDTIO_COMMAND_FLAG_RSP_MASK (SDTIO_COMMAND_FLAG_CMD_RSP_MASK | SDTIO_COMMAND_FLAG_STOP_RSP_MASK)
81
82 struct sdtio_vp_sg {
83 volatile void *addr;
84 volatile u32_t len;
85 };
86
87 #define SDTIO_VP_INT_STATUS_DONE (1 << 31)
88 #define SDTIO_VP_INT_STATUS_SDIO_INT (1 << 10)
89 #define SDTIO_VP_INT_STATUS_DATA_CRC_ERR (1 << 9)
90 #define SDTIO_VP_INT_STATUS_DATA_PROG_ERR (1 << 8)
91 #define SDTIO_VP_INT_STATUS_DATA_TIMEOUT (1 << 7)
92 #define SDTIO_VP_INT_STATUS_STOP_RSP_CRC (1 << 6)
93 #define SDTIO_VP_INT_STATUS_STOP_RSP_TIMEOUT (1 << 5)
94 #define SDTIO_VP_INT_STATUS_CMD_RSP_CRC (1 << 4)
95 #define SDTIO_VP_INT_STATUS_CMD_RSP_TIMEOUT (1 << 3)
96 #define SDTIO_VP_INT_STATUS_CMD_TIMEOUT (1 << 2)
97 #define SDTIO_VP_INT_STATUS_CARD1_INSERT (1 << 1)
98 #define SDTIO_VP_INT_STATUS_CARD0_INSERT (1 << 0)
99
100 struct sdtio_vp_regs {
101 u32_t version;
102 u32_t f_max;
103 u32_t f_min;
104
105 volatile u32_t int_status;
106
107 volatile u32_t command;
108 volatile u32_t arg;
109
110 volatile u32_t cmd_opcode;
111 volatile u32_t cmd_arg;
112 volatile u32_t cmd_rsp0;
113 volatile u32_t cmd_rsp1;
114 volatile u32_t cmd_rsp2;
115 volatile u32_t cmd_rsp3;
116
117 volatile u32_t stop_opcode;
118 volatile u32_t stop_arg;
119 volatile u32_t stop_rsp0;
120 volatile u32_t stop_rsp1;
121 volatile u32_t stop_rsp2;
122 volatile u32_t stop_rsp3;
123
124 volatile u32_t data_timeout_ns;
125 volatile u16_t data_blksz;
126 volatile u16_t data_blkct;
127 volatile u32_t data_bytes_transferred;
128 volatile u32_t sg_len;
129 struct sdtio_vp_sg sg[SDTIO_MAX_SG_BLOCKS];
130 };
131
132 struct ubicom32sd_data {
133 const struct ubicom32sd_platform_data *pdata;
134
135 struct mmc_host *mmc;
136
137 /*
138 * Lock used to protect the data structure
139 spinlock_t lock;
140 */
141 int int_en;
142 int int_pend;
143
144 /*
145 * Receive and transmit interrupts used for communicating
146 * with hardware
147 */
148 int irq_tx;
149 int irq_rx;
150
151 /*
152 * Current outstanding mmc request
153 */
154 struct mmc_request *mrq;
155
156 /*
157 * Hardware registers
158 */
159 struct sdtio_vp_regs *regs;
160 };
161
162 /*****************************************************************************\
163 * *
164 * Suspend/resume *
165 * *
166 \*****************************************************************************/
167
168 #if 0//def CONFIG_PM
169
170 int ubicom32sd_suspend_host(struct ubicom32sd_host *host, pm_message_t state)
171 {
172 int ret;
173
174 ret = mmc_suspend_host(host->mmc, state);
175 if (ret)
176 return ret;
177
178 free_irq(host->irq, host);
179
180 return 0;
181 }
182
183 EXPORT_SYMBOL_GPL(ubicom32sd_suspend_host);
184
185 int ubicom32sd_resume_host(struct ubicom32sd_host *host)
186 {
187 int ret;
188
189 if (host->flags & UBICOM32SD_USE_DMA) {
190 if (host->ops->enable_dma)
191 host->ops->enable_dma(host);
192 }
193
194 ret = request_irq(host->irq, ubicom32sd_irq, IRQF_SHARED,
195 mmc_hostname(host->mmc), host);
196 if (ret)
197 return ret;
198
199 ubicom32sd_init(host);
200 mmiowb();
201
202 ret = mmc_resume_host(host->mmc);
203 if (ret)
204 return ret;
205
206 return 0;
207 }
208
209 EXPORT_SYMBOL_GPL(ubicom32sd_resume_host);
210
211 #endif /* CONFIG_PM */
212
213 /*
214 * ubicom32sd_send_command_sync
215 */
216 static void ubicom32sd_send_command_sync(struct ubicom32sd_data *ud, u32_t command, u32_t arg)
217 {
218 ud->regs->command = command;
219 ud->regs->arg = arg;
220 ubicom32_set_interrupt(ud->irq_tx);
221 while (ud->regs->command) {
222 ndelay(100);
223 }
224 }
225
226 /*
227 * ubicom32sd_send_command
228 */
229 static void ubicom32sd_send_command(struct ubicom32sd_data *ud, u32_t command, u32_t arg)
230 {
231 ud->regs->command = command;
232 ud->regs->arg = arg;
233 ubicom32_set_interrupt(ud->irq_tx);
234 }
235
236 /*
237 * ubicom32sd_reset
238 */
239 static void ubicom32sd_reset(struct ubicom32sd_data *ud)
240 {
241 ubicom32sd_send_command_sync(ud, SDTIO_COMMAND_RESET << SDTIO_COMMAND_SHIFT, 0);
242 ud->regs->int_status = 0;
243 }
244
245 /*
246 * ubicom32sd_mmc_request
247 */
248 static void ubicom32sd_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
249 {
250 struct ubicom32sd_data *ud = (struct ubicom32sd_data *)mmc_priv(mmc);
251 u32_t command = SDTIO_COMMAND_EXECUTE << SDTIO_COMMAND_SHIFT;
252 int ret = 0;
253
254 WARN(ud->mrq != NULL, "ud->mrq still set to %p\n", ud->mrq);
255 //pr_debug("send cmd %08x arg %08x flags %08x\n", cmd->opcode, cmd->arg, cmd->flags);
256
257 if (mrq->cmd) {
258 struct mmc_command *cmd = mrq->cmd;
259
260 sd_printk("%s:\t\t\tsetup cmd %02d arg %08x flags %08x\n", mmc_hostname(mmc), cmd->opcode, cmd->arg, cmd->flags);
261
262 ud->regs->cmd_opcode = cmd->opcode;
263 ud->regs->cmd_arg = cmd->arg;
264
265 command |= SDTIO_COMMAND_FLAG_CMD;
266
267 if (cmd->flags & MMC_RSP_PRESENT) {
268 command |= SDTIO_COMMAND_FLAG_CMD_RSP;
269 }
270
271 if (cmd->flags & MMC_RSP_136) {
272 command |= SDTIO_COMMAND_FLAG_CMD_RSP_136;
273 }
274
275 if (cmd->flags & MMC_RSP_CRC) {
276 command |= SDTIO_COMMAND_FLAG_CMD_RSP_CRC;
277 }
278 }
279
280 if (mrq->data) {
281 struct mmc_data *data = mrq->data;
282 struct scatterlist *sg = data->sg;
283 int i;
284
285 printk("%s:\t\t\tsetup data blksz %d num %d sglen=%d fl=%08x Tns=%u\n", mmc_hostname(mmc), data->blksz, data->blocks, data->sg_len, data->flags, data->timeout_ns);
286
287 sd_printk("%s:\t\t\tsetup data blksz %d num %d sglen=%d fl=%08x Tns=%u\n",
288 mmc_hostname(mmc), data->blksz, data->blocks, data->sg_len,
289 data->flags, data->timeout_ns);
290
291 if (data->sg_len > SDTIO_MAX_SG_BLOCKS) {
292 ret = -EINVAL;
293 data->error = -EINVAL;
294 goto fail;
295 }
296
297 ud->regs->data_timeout_ns = data->timeout_ns;
298 ud->regs->data_blksz = data->blksz;
299 ud->regs->data_blkct = data->blocks;
300 ud->regs->sg_len = data->sg_len;
301
302 /*
303 * Load all of our sg list into the driver sg buffer
304 */
305 for (i = 0; i < data->sg_len; i++) {
306 sd_printk("%s: sg %d = %p %d\n", mmc_hostname(mmc), i, sg_virt(sg), sg->length);
307 ud->regs->sg[i].addr = sg_virt(sg);
308 ud->regs->sg[i].len = sg->length;
309 if (((u32_t)ud->regs->sg[i].addr & 0x03) || (sg->length & 0x03)) {
310 sd_printk("%s: Need aligned buffers\n", mmc_hostname(mmc));
311 ret = -EINVAL;
312 data->error = -EINVAL;
313 goto fail;
314 }
315 sg++;
316 }
317 if (data->flags & MMC_DATA_READ) {
318 command |= SDTIO_COMMAND_FLAG_DATA_RD;
319 } else if (data->flags & MMC_DATA_WRITE) {
320 command |= SDTIO_COMMAND_FLAG_DATA_WR;
321 } else if (data->flags & MMC_DATA_STREAM) {
322 command |= SDTIO_COMMAND_FLAG_DATA_STREAM;
323 }
324 }
325
326 if (mrq->stop) {
327 struct mmc_command *stop = mrq->stop;
328 sd_printk("%s: \t\t\tsetup stop %02d arg %08x flags %08x\n", mmc_hostname(mmc), stop->opcode, stop->arg, stop->flags);
329
330 ud->regs->stop_opcode = stop->opcode;
331 ud->regs->stop_arg = stop->arg;
332
333 command |= SDTIO_COMMAND_FLAG_STOP_CMD;
334
335 if (stop->flags & MMC_RSP_PRESENT) {
336 command |= SDTIO_COMMAND_FLAG_STOP_RSP;
337 }
338
339 if (stop->flags & MMC_RSP_136) {
340 command |= SDTIO_COMMAND_FLAG_STOP_RSP_136;
341 }
342
343 if (stop->flags & MMC_RSP_CRC) {
344 command |= SDTIO_COMMAND_FLAG_STOP_RSP_CRC;
345 }
346 }
347
348 ud->mrq = mrq;
349
350 sd_printk("%s: Sending command %08x\n", mmc_hostname(mmc), command);
351
352 ubicom32sd_send_command(ud, command, 0);
353
354 return;
355 fail:
356 sd_printk("%s: mmcreq ret = %d\n", mmc_hostname(mmc), ret);
357 mrq->cmd->error = ret;
358 mmc_request_done(mmc, mrq);
359 }
360
361 /*
362 * ubicom32sd_mmc_set_ios
363 */
364 static void ubicom32sd_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
365 {
366 struct ubicom32sd_data *ud = (struct ubicom32sd_data *)mmc_priv(mmc);
367 u32_t command = SDTIO_COMMAND_SETUP << SDTIO_COMMAND_SHIFT;
368 u32_t arg = 0;
369 sd_printk("%s: ios call bw:%u pm:%u clk:%u\n", mmc_hostname(mmc), 1 << ios->bus_width, ios->power_mode, ios->clock);
370
371 switch (ios->bus_width) {
372 case MMC_BUS_WIDTH_1:
373 command |= SDTIO_COMMAND_FLAG_SET_WIDTH | SDTIO_COMMAND_FLAG_1BIT;
374 break;
375
376 case MMC_BUS_WIDTH_4:
377 command |= SDTIO_COMMAND_FLAG_SET_WIDTH | SDTIO_COMMAND_FLAG_4BIT;
378 break;
379 }
380
381 if (ios->clock) {
382 arg = ios->clock;
383 command |= SDTIO_COMMAND_FLAG_SET_CLOCK;
384 }
385
386 switch (ios->power_mode) {
387
388 /*
389 * Turn off the SD bus (power + clock)
390 */
391 case MMC_POWER_OFF:
392 gpio_set_value(ud->pdata->cards[0].pin_pwr, !ud->pdata->cards[0].pwr_polarity);
393 command |= SDTIO_COMMAND_FLAG_SET_CLOCK;
394 break;
395
396 /*
397 * Turn on the power to the SD bus
398 */
399 case MMC_POWER_ON:
400 gpio_set_value(ud->pdata->cards[0].pin_pwr, ud->pdata->cards[0].pwr_polarity);
401 break;
402
403 /*
404 * Turn on the clock to the SD bus
405 */
406 case MMC_POWER_UP:
407 /*
408 * Done above
409 */
410 break;
411 }
412
413 ubicom32sd_send_command_sync(ud, command, arg);
414
415 /*
416 * Let the power settle down
417 */
418 udelay(500);
419 }
420
421 /*
422 * ubicom32sd_mmc_get_cd
423 */
424 static int ubicom32sd_mmc_get_cd(struct mmc_host *mmc)
425 {
426 struct ubicom32sd_data *ud = (struct ubicom32sd_data *)mmc_priv(mmc);
427 sd_printk("%s: get cd %u %u\n", mmc_hostname(mmc), ud->pdata->cards[0].pin_cd, gpio_get_value(ud->pdata->cards[0].pin_cd));
428
429 return gpio_get_value(ud->pdata->cards[0].pin_cd) ?
430 ud->pdata->cards[0].cd_polarity :
431 !ud->pdata->cards[0].cd_polarity;
432 }
433
434 /*
435 * ubicom32sd_mmc_get_ro
436 */
437 static int ubicom32sd_mmc_get_ro(struct mmc_host *mmc)
438 {
439 struct ubicom32sd_data *ud = (struct ubicom32sd_data *)mmc_priv(mmc);
440 sd_printk("%s: get ro %u %u\n", mmc_hostname(mmc), ud->pdata->cards[0].pin_wp, gpio_get_value(ud->pdata->cards[0].pin_wp));
441
442 return gpio_get_value(ud->pdata->cards[0].pin_wp) ?
443 ud->pdata->cards[0].wp_polarity :
444 !ud->pdata->cards[0].wp_polarity;
445 }
446
447 /*
448 * ubicom32sd_mmc_enable_sdio_irq
449 */
450 static void ubicom32sd_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
451 {
452 struct ubicom32sd_data *ud = (struct ubicom32sd_data *)mmc_priv(mmc);
453
454 ud->int_en = enable;
455 if (enable && ud->int_pend) {
456 ud->int_pend = 0;
457 mmc_signal_sdio_irq(mmc);
458 }
459 }
460
461 /*
462 * ubicom32sd_interrupt
463 */
464 static irqreturn_t ubicom32sd_interrupt(int irq, void *dev)
465 {
466 struct mmc_host *mmc = (struct mmc_host *)dev;
467 struct mmc_request *mrq;
468 struct ubicom32sd_data *ud;
469 u32_t int_status;
470
471 if (!mmc) {
472 return IRQ_HANDLED;
473 }
474
475 ud = (struct ubicom32sd_data *)mmc_priv(mmc);
476 if (!ud) {
477 return IRQ_HANDLED;
478 }
479
480 int_status = ud->regs->int_status;
481 ud->regs->int_status &= ~int_status;
482
483 if (int_status & SDTIO_VP_INT_STATUS_SDIO_INT) {
484 if (ud->int_en) {
485 ud->int_pend = 0;
486 mmc_signal_sdio_irq(mmc);
487 } else {
488 ud->int_pend++;
489 }
490 }
491
492 if (!(int_status & SDTIO_VP_INT_STATUS_DONE)) {
493 return IRQ_HANDLED;
494 }
495
496 mrq = ud->mrq;
497 if (!mrq) {
498 sd_printk("%s: Spurious interrupt", mmc_hostname(mmc));
499 return IRQ_HANDLED;
500 }
501 ud->mrq = NULL;
502
503 /*
504 * SDTIO_VP_INT_DONE
505 */
506 if (mrq->cmd->flags & MMC_RSP_PRESENT) {
507 struct mmc_command *cmd = mrq->cmd;
508 cmd->error = 0;
509
510 if ((cmd->flags & MMC_RSP_CRC) && (int_status & SDTIO_VP_INT_STATUS_CMD_RSP_CRC)) {
511 cmd->error = -EILSEQ;
512 } else if (int_status & SDTIO_VP_INT_STATUS_CMD_RSP_TIMEOUT) {
513 cmd->error = -ETIMEDOUT;
514 goto done;
515 } else if (cmd->flags & MMC_RSP_136) {
516 cmd->resp[0] = ud->regs->cmd_rsp0;
517 cmd->resp[1] = ud->regs->cmd_rsp1;
518 cmd->resp[2] = ud->regs->cmd_rsp2;
519 cmd->resp[3] = ud->regs->cmd_rsp3;
520 } else {
521 cmd->resp[0] = ud->regs->cmd_rsp0;
522 }
523 sd_printk("%s:\t\t\tResponse %08x %08x %08x %08x err=%d\n", mmc_hostname(mmc), cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], cmd->error);
524 }
525
526 if (mrq->data) {
527 struct mmc_data *data = mrq->data;
528
529 if (int_status & SDTIO_VP_INT_STATUS_DATA_TIMEOUT) {
530 data->error = -ETIMEDOUT;
531 sd_printk("%s:\t\t\tData Timeout\n", mmc_hostname(mmc));
532 goto done;
533 } else if (int_status & SDTIO_VP_INT_STATUS_DATA_CRC_ERR) {
534 data->error = -EILSEQ;
535 sd_printk("%s:\t\t\tData CRC\n", mmc_hostname(mmc));
536 goto done;
537 } else if (int_status & SDTIO_VP_INT_STATUS_DATA_PROG_ERR) {
538 data->error = -EILSEQ;
539 sd_printk("%s:\t\t\tData Program Error\n", mmc_hostname(mmc));
540 goto done;
541 } else {
542 data->error = 0;
543 data->bytes_xfered = ud->regs->data_bytes_transferred;
544 }
545 }
546
547 if (mrq->stop && (mrq->stop->flags & MMC_RSP_PRESENT)) {
548 struct mmc_command *stop = mrq->stop;
549 stop->error = 0;
550
551 if ((stop->flags & MMC_RSP_CRC) && (int_status & SDTIO_VP_INT_STATUS_STOP_RSP_CRC)) {
552 stop->error = -EILSEQ;
553 } else if (int_status & SDTIO_VP_INT_STATUS_STOP_RSP_TIMEOUT) {
554 stop->error = -ETIMEDOUT;
555 goto done;
556 } else if (stop->flags & MMC_RSP_136) {
557 stop->resp[0] = ud->regs->stop_rsp0;
558 stop->resp[1] = ud->regs->stop_rsp1;
559 stop->resp[2] = ud->regs->stop_rsp2;
560 stop->resp[3] = ud->regs->stop_rsp3;
561 } else {
562 stop->resp[0] = ud->regs->stop_rsp0;
563 }
564 sd_printk("%s:\t\t\tStop Response %08x %08x %08x %08x err=%d\n", mmc_hostname(mmc), stop->resp[0], stop->resp[1], stop->resp[2], stop->resp[3], stop->error);
565 }
566
567 done:
568 mmc_request_done(mmc, mrq);
569
570 return IRQ_HANDLED;
571 }
572
573 static struct mmc_host_ops ubicom32sd_ops = {
574 .request = ubicom32sd_mmc_request,
575 .set_ios = ubicom32sd_mmc_set_ios,
576 .get_ro = ubicom32sd_mmc_get_ro,
577 .get_cd = ubicom32sd_mmc_get_cd,
578 .enable_sdio_irq = ubicom32sd_mmc_enable_sdio_irq,
579 };
580
581 /*
582 * ubicom32sd_probe
583 */
584 static int __devinit ubicom32sd_probe(struct platform_device *pdev)
585 {
586 struct ubicom32sd_platform_data *pdata = (struct ubicom32sd_platform_data *)pdev->dev.platform_data;
587 struct mmc_host *mmc;
588 struct ubicom32sd_data *ud;
589 struct resource *res_regs;
590 struct resource *res_irq_tx;
591 struct resource *res_irq_rx;
592 int ret;
593
594 /*
595 * Get our resources, regs is the hardware driver base address
596 * and the tx and rx irqs are used to communicate with the
597 * hardware driver.
598 */
599 res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
600 res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
601 res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
602 if (!res_regs || !res_irq_tx || !res_irq_rx) {
603 ret = -EINVAL;
604 goto fail;
605 }
606
607 /*
608 * Reserve any gpios we need
609 */
610 ret = gpio_request(pdata->cards[0].pin_wp, "sd-wp");
611 if (ret) {
612 goto fail;
613 }
614 gpio_direction_input(pdata->cards[0].pin_wp);
615
616 ret = gpio_request(pdata->cards[0].pin_cd, "sd-cd");
617 if (ret) {
618 goto fail_cd;
619 }
620 gpio_direction_input(pdata->cards[0].pin_cd);
621
622 /*
623 * HACK: for the dual port controller on port F, we don't support the second port right now
624 */
625 if (pdata->ncards > 1) {
626 ret = gpio_request(pdata->cards[1].pin_pwr, "sd-pwr");
627 gpio_direction_output(pdata->cards[1].pin_pwr, !pdata->cards[1].pwr_polarity);
628 gpio_direction_output(pdata->cards[1].pin_pwr, pdata->cards[1].pwr_polarity);
629 }
630
631 ret = gpio_request(pdata->cards[0].pin_pwr, "sd-pwr");
632 if (ret) {
633 goto fail_pwr;
634 }
635 gpio_direction_output(pdata->cards[0].pin_pwr, !pdata->cards[0].pwr_polarity);
636
637 /*
638 * Allocate the MMC driver, it includes memory for our data.
639 */
640 mmc = mmc_alloc_host(sizeof(struct ubicom32sd_data), &pdev->dev);
641 if (!mmc) {
642 ret = -ENOMEM;
643 goto fail_mmc;
644 }
645 ud = (struct ubicom32sd_data *)mmc_priv(mmc);
646 ud->mmc = mmc;
647 ud->pdata = pdata;
648 ud->regs = (struct sdtio_vp_regs *)res_regs->start;
649 ud->irq_tx = res_irq_tx->start;
650 ud->irq_rx = res_irq_rx->start;
651 platform_set_drvdata(pdev, mmc);
652
653 ret = request_irq(ud->irq_rx, ubicom32sd_interrupt, IRQF_DISABLED, mmc_hostname(mmc), mmc);
654 if (ret) {
655 goto fail_mmc;
656 }
657
658 /*
659 * Fill in the mmc structure
660 */
661 mmc->ops = &ubicom32sd_ops;
662 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ |
663 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
664
665 mmc->f_min = ud->regs->f_min;
666 mmc->f_max = ud->regs->f_max;
667 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
668
669 /*
670 * Setup some restrictions on transfers
671 *
672 * We allow up to SDTIO_MAX_SG_BLOCKS of data to DMA into, there are
673 * not really any "max_seg_size", "max_req_size", or "max_blk_count"
674 * restrictions (must be less than U32_MAX though), pick
675 * something large?!...
676 *
677 * The hardware can do up to 4095 bytes per block, since the spec
678 * only requires 2048, we'll set it to that and not worry about
679 * potential weird blk lengths.
680 */
681 mmc->max_hw_segs = SDTIO_MAX_SG_BLOCKS;
682 mmc->max_phys_segs = SDTIO_MAX_SG_BLOCKS;
683 mmc->max_seg_size = 1024 * 1024;
684 mmc->max_req_size = 1024 * 1024;
685 mmc->max_blk_count = 1024;
686
687 mmc->max_blk_size = 2048;
688
689 ubicom32sd_reset(ud);
690
691 /*
692 * enable interrupts
693 */
694 ud->int_en = 0;
695 ubicom32sd_send_command_sync(ud, SDTIO_COMMAND_SETUP_SDIO << SDTIO_COMMAND_SHIFT | SDTIO_COMMAND_FLAG_SDIO_INT_EN, 0);
696
697 mmc_add_host(mmc);
698
699 printk(KERN_INFO "%s at %p, irq %d/%d\n", mmc_hostname(mmc),
700 ud->regs, ud->irq_tx, ud->irq_rx);
701 return 0;
702
703 fail_mmc:
704 gpio_free(pdata->cards[0].pin_pwr);
705 fail_pwr:
706 gpio_free(pdata->cards[0].pin_cd);
707 fail_cd:
708 gpio_free(pdata->cards[0].pin_wp);
709 fail:
710 return ret;
711 }
712
713 /*
714 * ubicom32sd_remove
715 */
716 static int __devexit ubicom32sd_remove(struct platform_device *pdev)
717 {
718 struct mmc_host *mmc = platform_get_drvdata(pdev);
719
720 platform_set_drvdata(pdev, NULL);
721
722 if (mmc) {
723 struct ubicom32sd_data *ud = (struct ubicom32sd_data *)mmc_priv(mmc);
724
725 gpio_free(ud->pdata->cards[0].pin_pwr);
726 gpio_free(ud->pdata->cards[0].pin_cd);
727 gpio_free(ud->pdata->cards[0].pin_wp);
728
729 mmc_remove_host(mmc);
730 mmc_free_host(mmc);
731 }
732
733 /*
734 * Note that our data is allocated as part of the mmc structure
735 * so we don't need to free it.
736 */
737 return 0;
738 }
739
740 static struct platform_driver ubicom32sd_driver = {
741 .driver = {
742 .name = DRIVER_NAME,
743 .owner = THIS_MODULE,
744 },
745 .probe = ubicom32sd_probe,
746 .remove = __devexit_p(ubicom32sd_remove),
747 #if 0
748 .suspend = ubicom32sd_suspend,
749 .resume = ubicom32sd_resume,
750 #endif
751 };
752
753 /*
754 * ubicom32sd_init
755 */
756 static int __init ubicom32sd_init(void)
757 {
758 return platform_driver_register(&ubicom32sd_driver);
759 }
760 module_init(ubicom32sd_init);
761
762 /*
763 * ubicom32sd_exit
764 */
765 static void __exit ubicom32sd_exit(void)
766 {
767 platform_driver_unregister(&ubicom32sd_driver);
768 }
769 module_exit(ubicom32sd_exit);
770
771 MODULE_AUTHOR("Patrick Tjin");
772 MODULE_DESCRIPTION("Ubicom32 Secure Digital Host Controller Interface driver");
773 MODULE_LICENSE("GPL");
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