target/linux/rb1xx-2.6/files/drivers/mtd/nand/rbmipsnand.c

   1 #include <linux/init.h>
   2 #include <linux/mtd/nand.h>
   3 #include <linux/mtd/mtd.h>
   4 #include <linux/mtd/partitions.h>
   5 #include <linux/delay.h>
   6 #include <asm/io.h>
   7 #include <asm/irq.h>
   8 #include <asm/bootinfo.h>
   9 #ifdef CONFIG_MIPS_ADM5120
  10 #include <asm/mach-adm5120/adm5120_defs.h>
  11 #endif
  12
  13 #define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
  14
  15 #define GPIOF 0x050000
  16 #define GPIOC 0x050004
  17 #define GPIOD 0x050008
  18
  19 #define GPIO_RDY (1 << 0x08)
  20 #define GPIO_WPX (1 << 0x09)
  21 #define GPIO_ALE (1 << 0x0a)
  22 #define GPIO_CLE (1 << 0x0b)
  23
  24 #define DEV2BASE 0x010020
  25
  26 #define LO_WPX   (1 << 0)
  27 #define LO_ALE   (1 << 1)
  28 #define LO_CLE   (1 << 2)
  29 #define LO_CEX   (1 << 3)
  30 #define LO_FOFF  (1 << 5)
  31 #define LO_SPICS (1 << 6)
  32 #define LO_ULED  (1 << 7)
  33
  34 #define MEM32(x) *((volatile unsigned *) (x))
  35
  36
  37 /* RouterBoard RB1xx specific definitions */
  38 #define SMEM1(x) (*((volatile unsigned char *) (KSEG1ADDR(ADM5120_SRAM1_BASE) + x)))
  39
  40 #define NAND_RW_REG     0x0     //data register
  41 #define NAND_SET_CEn    0x1     //CE# low
  42 #define NAND_CLR_CEn    0x2     //CE# high
  43 #define NAND_CLR_CLE    0x3     //CLE low
  44 #define NAND_SET_CLE    0x4     //CLE high
  45 #define NAND_CLR_ALE    0x5     //ALE low
  46 #define NAND_SET_ALE    0x6     //ALE high
  47 #define NAND_SET_SPn    0x7     //SP# low (use spare area)
  48 #define NAND_CLR_SPn    0x8     //SP# high (do not use spare area)
  49 #define NAND_SET_WPn    0x9     //WP# low
  50 #define NAND_CLR_WPn    0xA     //WP# high
  51 #define NAND_STS_REG    0xB     //Status register
  52
  53 static void __iomem *p_nand;
  54
  55 #ifdef CONFIG_MIKROTIK_RB500
  56 extern void changeLatchU5(unsigned char orMask, unsigned char nandMask);
  57
  58 static int rb500_dev_ready(struct mtd_info *mtd)
  59 {
  60         return MEM32(IDT434_REG_BASE + GPIOD) & GPIO_RDY;
  61 }
  62
  63 /*
  64  * hardware specific access to control-lines
  65  *
  66  * ctrl:
  67  *     NAND_CLE: bit 2 -> bit 3
  68  *     NAND_ALE: bit 3 -> bit 2
  69  */
  70 static void rbmips_hwcontrol500(struct mtd_info *mtd, int cmd,
  71                                 unsigned int ctrl)
  72 {
  73         struct nand_chip *chip = mtd->priv;
  74         unsigned char orbits, nandbits;
  75
  76         if (ctrl & NAND_CTRL_CHANGE) {
  77
  78                 orbits = (ctrl & NAND_CLE) << 1;
  79                 orbits |= (ctrl & NAND_ALE) >> 1;
  80
  81                 nandbits = (~ctrl & NAND_CLE) << 1;
  82                 nandbits |= (~ctrl & NAND_ALE) >> 1;
  83
  84                 changeLatchU5(orbits, nandbits);
  85         }
  86         if (cmd != NAND_CMD_NONE)
  87                 writeb(cmd, chip->IO_ADDR_W);
  88
  89 }
  90 #endif
  91
  92 #ifdef CONFIG_MIPS_ADM5120
  93 static int rb100_dev_ready(struct mtd_info *mtd)
  94 {
  95         return SMEM1(NAND_STS_REG) & 0x80; /* found out by experiment */
  96 }
  97
  98 static void rbmips_hwcontrol100(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  99 {
 100         struct nand_chip *chip = mtd->priv;
 101
 102         if (ctrl & NAND_CTRL_CHANGE)
 103                 SMEM1(ctrl) = 0x01;
 104         if (cmd != NAND_CMD_NONE)
 105                 writeb(cmd, chip->IO_ADDR_W);
 106 }
 107 #endif
 108
 109
 110 static struct mtd_partition partition_info[] = {
 111         {
 112               name:"RouterBoard NAND Boot",
 113               offset:0,
 114       size:4 * 1024 * 1024},
 115         {
 116               name:"RouterBoard NAND Main",
 117               offset:MTDPART_OFS_NXTBLK,
 118       size:MTDPART_SIZ_FULL}
 119 };
 120
 121 static struct mtd_info rmtd;
 122 static struct nand_chip rnand;
 123
 124 static unsigned init_ok = 0;
 125
 126 unsigned get_rbnand_block_size(void)
 127 {
 128         if (init_ok)
 129                 return rmtd.writesize;
 130         else
 131                 return 0;
 132 }
 133
 134 EXPORT_SYMBOL(get_rbnand_block_size);
 135
 136 int __init rbmips_init(void)
 137 {
 138         memset(&rmtd, 0, sizeof(rmtd));
 139         memset(&rnand, 0, sizeof(rnand));
 140
 141 #ifdef CONFIG_MIKROTIK_RB500
 142         printk("RB500 nand\n");
 143         changeLatchU5(LO_WPX | LO_FOFF | LO_CEX,
 144                       LO_ULED | LO_ALE | LO_CLE);
 145         rnand.cmd_ctrl = rbmips_hwcontrol500;
 146
 147         rnand.dev_ready = rb500_dev_ready;
 148         rnand.IO_ADDR_W = (unsigned char *)
 149             KSEG1ADDR(MEM32(IDT434_REG_BASE + DEV2BASE));
 150         rnand.IO_ADDR_R = rnand.IO_ADDR_W;
 151 #endif
 152
 153 #ifdef CONFIG_MIPS_ADM5120
 154         printk("RB100 nand\n");
 155         /* enable NAND flash */
 156         MEM32(0xB2000064) = 0x100;
 157         /* boot done */
 158         MEM32(0xB2000008) = 0x1;
 159         SMEM1(NAND_SET_SPn) = 0x01;
 160         SMEM1(NAND_CLR_WPn) = 0x01;
 161         rnand.IO_ADDR_R = (unsigned char *)KSEG1ADDR(ADM5120_SRAM1_BASE);
 162         rnand.IO_ADDR_W = rnand.IO_ADDR_R;
 163         rnand.cmd_ctrl = rbmips_hwcontrol100;
 164         rnand.dev_ready = rb100_dev_ready;
 165 #endif
 166         p_nand = (void __iomem *) ioremap((void *) 0x18a20000, 0x1000);
 167         if (!p_nand) {
 168                 printk("RBnand Unable ioremap buffer");
 169                 return -ENXIO;
 170         }
 171         rnand.ecc.mode = NAND_ECC_SOFT;
 172         rnand.chip_delay = 25;
 173         rnand.options |= NAND_NO_AUTOINCR;
 174         rmtd.priv = &rnand;
 175
 176 #ifdef CONFIG_MIKROTIK_RB500
 177         int *b;
 178
 179         b = (int *) KSEG1ADDR(0x18010020);
 180         printk("dev2base 0x%08x mask 0x%08x c 0x%08x tc 0x%08x\n", b[0],
 181                b[1], b[2], b[3]);
 182 #endif
 183
 184         if (nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1)
 185             && nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1)) {
 186                 printk("RBxxx nand device not found");
 187                 iounmap((void *) p_nand);
 188                 return -ENXIO;
 189         }
 190
 191         add_mtd_partitions(&rmtd, partition_info, 2);
 192         init_ok = 1;
 193         return 0;
 194 }
 195
 196 module_init(rbmips_init);