several fixes to ifxmips, getting ready for dsl driver merge
[openwrt.git] / target / linux / brcm47xx / patches-2.6.23 / 220-bcm5354.patch
1 --- files/drivers/ssb/driver_chipcommon.c 2007-10-24 16:57:38.000000000 -0700
2 +++ linux-2.6.23.1/drivers/ssb/driver_chipcommon.c 2007-10-27 13:27:06.000000000 -0700
3 @@ -268,6 +268,8 @@
4 void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
5 u32 *plltype, u32 *n, u32 *m)
6 {
7 + if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
8 + return;
9 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
10 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
11 switch (*plltype) {
12 @@ -291,6 +293,8 @@
13 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
14 u32 *plltype, u32 *n, u32 *m)
15 {
16 + if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
17 + return;
18 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
19 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
20 switch (*plltype) {
21 @@ -387,7 +376,14 @@
22 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
23 div = 1;
24 } else {
25 - if (cc->dev->id.revision >= 11) {
26 + if (cc->dev->id.revision == 20) {
27 + /* BCM5354 uses constant 25MHz clock */
28 + baud_base = 25000000;
29 + div = 48;
30 + /* Set the override bit so we don't divide it */
31 + chipco_write32(cc, SSB_CHIPCO_CORECTL,
32 + SSB_CHIPCO_CORECTL_UARTCLK0);
33 + } else if (cc->dev->id.revision >= 11) {
34 /* Fixed ALP clock */
35 baud_base = 20000000;
36 div = 1;
37 --- files/drivers/ssb/driver_mipscore.c 2007-10-24 16:57:38.000000000 -0700
38 +++ linux-2.6.23.1/drivers/ssb/driver_mipscore.c 2007-10-27 13:29:36.000000000 -0700
39 @@ -160,6 +160,8 @@
40
41 if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
42 rate = 200000000;
43 + } else if (bus->chip_id == 0x5354) {
44 + rate = 240000000;
45 } else {
46 rate = ssb_calc_clock_rate(pll_type, n, m);
47 }
48 --- files/drivers/ssb/main.c 2007-10-24 16:57:38.000000000 -0700
49 +++ linux-2.6.23.1/drivers/ssb/main.c 2007-10-27 13:30:59.000000000 -0700
50 @@ -864,6 +864,8 @@
51
52 if (bus->chip_id == 0x5365) {
53 rate = 100000000;
54 + } else if (bus->chip_id == 0x5354) {
55 + rate = 120000000;
56 } else {
57 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
58 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
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