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ar71xx: tplinkpart: allow to detect JFFS2 as well
[openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_ar7240.c
1 /*
2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
19 #include "ag71xx.h"
20
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
23
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
29
30 #define AR7240_REG_MAC_ADDR0 0x20
31 #define AR7240_REG_MAC_ADDR1 0x24
32
33 #define AR7240_REG_FLOOD_MASK 0x2c
34 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
35
36 #define AR7240_REG_GLOBAL_CTRL 0x30
37 #define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
38
39 #define AR7240_REG_VTU 0x0040
40 #define AR7240_VTU_OP BITM(3)
41 #define AR7240_VTU_OP_NOOP 0x0
42 #define AR7240_VTU_OP_FLUSH 0x1
43 #define AR7240_VTU_OP_LOAD 0x2
44 #define AR7240_VTU_OP_PURGE 0x3
45 #define AR7240_VTU_OP_REMOVE_PORT 0x4
46 #define AR7240_VTU_ACTIVE BIT(3)
47 #define AR7240_VTU_FULL BIT(4)
48 #define AR7240_VTU_PORT BITS(8, 4)
49 #define AR7240_VTU_PORT_S 8
50 #define AR7240_VTU_VID BITS(16, 12)
51 #define AR7240_VTU_VID_S 16
52 #define AR7240_VTU_PRIO BITS(28, 3)
53 #define AR7240_VTU_PRIO_S 28
54 #define AR7240_VTU_PRIO_EN BIT(31)
55
56 #define AR7240_REG_VTU_DATA 0x0044
57 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
58 #define AR7240_VTUDATA_VALID BIT(11)
59
60 #define AR7240_REG_ATU 0x50
61 #define AR7240_ATU_FLUSH_ALL 0x1
62
63 #define AR7240_REG_AT_CTRL 0x5c
64 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
65 #define AR7240_AT_CTRL_AGE_EN BIT(17)
66 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
67 #define AR7240_AT_CTRL_ARP_EN BIT(20)
68
69 #define AR7240_REG_TAG_PRIORITY 0x70
70
71 #define AR7240_REG_SERVICE_TAG 0x74
72 #define AR7240_SERVICE_TAG_M BITM(16)
73
74 #define AR7240_REG_CPU_PORT 0x78
75 #define AR7240_MIRROR_PORT_S 4
76 #define AR7240_CPU_PORT_EN BIT(8)
77
78 #define AR7240_REG_MIB_FUNCTION0 0x80
79 #define AR7240_MIB_TIMER_M BITM(16)
80 #define AR7240_MIB_AT_HALF_EN BIT(16)
81 #define AR7240_MIB_BUSY BIT(17)
82 #define AR7240_MIB_FUNC_S 24
83 #define AR7240_MIB_FUNC_NO_OP 0x0
84 #define AR7240_MIB_FUNC_FLUSH 0x1
85 #define AR7240_MIB_FUNC_CAPTURE 0x3
86
87 #define AR7240_REG_MDIO_CTRL 0x98
88 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
89 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
90 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
91 #define AR7240_MDIO_CTRL_CMD_WRITE 0
92 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
93 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
94 #define AR7240_MDIO_CTRL_BUSY BIT(31)
95
96 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
97
98 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
99 #define AR7240_PORT_STATUS_SPEED_S 0
100 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
101 #define AR7240_PORT_STATUS_SPEED_10 0
102 #define AR7240_PORT_STATUS_SPEED_100 1
103 #define AR7240_PORT_STATUS_SPEED_1000 2
104 #define AR7240_PORT_STATUS_TXMAC BIT(2)
105 #define AR7240_PORT_STATUS_RXMAC BIT(3)
106 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
107 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
108 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
109 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
110 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
111 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
112
113 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
114 #define AR7240_PORT_CTRL_STATE_M BITM(3)
115 #define AR7240_PORT_CTRL_STATE_DISABLED 0
116 #define AR7240_PORT_CTRL_STATE_BLOCK 1
117 #define AR7240_PORT_CTRL_STATE_LISTEN 2
118 #define AR7240_PORT_CTRL_STATE_LEARN 3
119 #define AR7240_PORT_CTRL_STATE_FORWARD 4
120 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
121 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
122 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
123 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
124 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
125 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
126 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
127 #define AR7240_PORT_CTRL_HEADER BIT(11)
128 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
129 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
130 #define AR7240_PORT_CTRL_LEARN BIT(14)
131 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
132 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
133 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
134
135 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
136
137 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
138 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
139 #define AR7240_PORT_VLAN_MODE_S 30
140 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
141 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
142 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
143 #define AR7240_PORT_VLAN_MODE_SECURE 3
144
145
146 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
147
148 #define AR7240_STATS_RXBROAD 0x00
149 #define AR7240_STATS_RXPAUSE 0x04
150 #define AR7240_STATS_RXMULTI 0x08
151 #define AR7240_STATS_RXFCSERR 0x0c
152 #define AR7240_STATS_RXALIGNERR 0x10
153 #define AR7240_STATS_RXRUNT 0x14
154 #define AR7240_STATS_RXFRAGMENT 0x18
155 #define AR7240_STATS_RX64BYTE 0x1c
156 #define AR7240_STATS_RX128BYTE 0x20
157 #define AR7240_STATS_RX256BYTE 0x24
158 #define AR7240_STATS_RX512BYTE 0x28
159 #define AR7240_STATS_RX1024BYTE 0x2c
160 #define AR7240_STATS_RX1518BYTE 0x30
161 #define AR7240_STATS_RXMAXBYTE 0x34
162 #define AR7240_STATS_RXTOOLONG 0x38
163 #define AR7240_STATS_RXGOODBYTE 0x3c
164 #define AR7240_STATS_RXBADBYTE 0x44
165 #define AR7240_STATS_RXOVERFLOW 0x4c
166 #define AR7240_STATS_FILTERED 0x50
167 #define AR7240_STATS_TXBROAD 0x54
168 #define AR7240_STATS_TXPAUSE 0x58
169 #define AR7240_STATS_TXMULTI 0x5c
170 #define AR7240_STATS_TXUNDERRUN 0x60
171 #define AR7240_STATS_TX64BYTE 0x64
172 #define AR7240_STATS_TX128BYTE 0x68
173 #define AR7240_STATS_TX256BYTE 0x6c
174 #define AR7240_STATS_TX512BYTE 0x70
175 #define AR7240_STATS_TX1024BYTE 0x74
176 #define AR7240_STATS_TX1518BYTE 0x78
177 #define AR7240_STATS_TXMAXBYTE 0x7c
178 #define AR7240_STATS_TXOVERSIZE 0x80
179 #define AR7240_STATS_TXBYTE 0x84
180 #define AR7240_STATS_TXCOLLISION 0x8c
181 #define AR7240_STATS_TXABORTCOL 0x90
182 #define AR7240_STATS_TXMULTICOL 0x94
183 #define AR7240_STATS_TXSINGLECOL 0x98
184 #define AR7240_STATS_TXEXCDEFER 0x9c
185 #define AR7240_STATS_TXDEFER 0xa0
186 #define AR7240_STATS_TXLATECOL 0xa4
187
188 #define AR7240_PORT_CPU 0
189 #define AR7240_NUM_PORTS 6
190 #define AR7240_NUM_PHYS 5
191
192 #define AR7240_PHY_ID1 0x004d
193 #define AR7240_PHY_ID2 0xd041
194
195 #define AR7240_MAX_VLANS 16
196
197 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
198
199 struct ar7240sw {
200 struct mii_bus *mii_bus;
201 struct switch_dev swdev;
202 int num_ports;
203 bool vlan;
204 u16 vlan_id[AR7240_MAX_VLANS];
205 u8 vlan_table[AR7240_MAX_VLANS];
206 u8 vlan_tagged;
207 u16 pvid[AR7240_NUM_PORTS];
208 char buf[80];
209 };
210
211 struct ar7240sw_hw_stat {
212 char string[ETH_GSTRING_LEN];
213 int sizeof_stat;
214 int reg;
215 };
216
217 static DEFINE_MUTEX(reg_mutex);
218
219 static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
220 {
221 return BIT(port);
222 }
223
224 static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
225 {
226 return BIT(as->swdev.ports) - 1;
227 }
228
229 static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
230 {
231 return ar7240sw_port_mask_all(as) & ~BIT(port);
232 }
233
234 static inline u16 mk_phy_addr(u32 reg)
235 {
236 return 0x17 & ((reg >> 4) | 0x10);
237 }
238
239 static inline u16 mk_phy_reg(u32 reg)
240 {
241 return (reg << 1) & 0x1e;
242 }
243
244 static inline u16 mk_high_addr(u32 reg)
245 {
246 return (reg >> 7) & 0x1ff;
247 }
248
249 static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
250 {
251 unsigned long flags;
252 u16 phy_addr;
253 u16 phy_reg;
254 u32 hi, lo;
255
256 reg = (reg & 0xfffffffc) >> 2;
257 phy_addr = mk_phy_addr(reg);
258 phy_reg = mk_phy_reg(reg);
259
260 local_irq_save(flags);
261 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
262 lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
263 hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
264 local_irq_restore(flags);
265
266 return (hi << 16) | lo;
267 }
268
269 static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
270 {
271 unsigned long flags;
272 u16 phy_addr;
273 u16 phy_reg;
274
275 reg = (reg & 0xfffffffc) >> 2;
276 phy_addr = mk_phy_addr(reg);
277 phy_reg = mk_phy_reg(reg);
278
279 local_irq_save(flags);
280 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
281 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
282 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
283 local_irq_restore(flags);
284 }
285
286 static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
287 {
288 u32 ret;
289
290 mutex_lock(&reg_mutex);
291 ret = __ar7240sw_reg_read(mii, reg_addr);
292 mutex_unlock(&reg_mutex);
293
294 return ret;
295 }
296
297 static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
298 {
299 mutex_lock(&reg_mutex);
300 __ar7240sw_reg_write(mii, reg_addr, reg_val);
301 mutex_unlock(&reg_mutex);
302 }
303
304 static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
305 {
306 u32 t;
307
308 mutex_lock(&reg_mutex);
309 t = __ar7240sw_reg_read(mii, reg);
310 t &= ~mask;
311 t |= val;
312 __ar7240sw_reg_write(mii, reg, t);
313 mutex_unlock(&reg_mutex);
314
315 return t;
316 }
317
318 static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
319 {
320 u32 t;
321
322 mutex_lock(&reg_mutex);
323 t = __ar7240sw_reg_read(mii, reg);
324 t |= val;
325 __ar7240sw_reg_write(mii, reg, t);
326 mutex_unlock(&reg_mutex);
327 }
328
329 static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
330 unsigned timeout)
331 {
332 int i;
333
334 for (i = 0; i < timeout; i++) {
335 u32 t;
336
337 t = __ar7240sw_reg_read(mii, reg);
338 if ((t & mask) == val)
339 return 0;
340
341 msleep(1);
342 }
343
344 return -ETIMEDOUT;
345 }
346
347 static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
348 unsigned timeout)
349 {
350 int ret;
351
352 mutex_lock(&reg_mutex);
353 ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
354 mutex_unlock(&reg_mutex);
355 return ret;
356 }
357
358 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
359 unsigned reg_addr)
360 {
361 u32 t, val = 0xffff;
362 int err;
363
364 if (phy_addr >= AR7240_NUM_PHYS)
365 return 0xffff;
366
367 mutex_lock(&reg_mutex);
368 t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
369 (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
370 AR7240_MDIO_CTRL_MASTER_EN |
371 AR7240_MDIO_CTRL_BUSY |
372 AR7240_MDIO_CTRL_CMD_READ;
373
374 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
375 err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
376 AR7240_MDIO_CTRL_BUSY, 0, 5);
377 if (!err)
378 val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
379 mutex_unlock(&reg_mutex);
380
381 return val & AR7240_MDIO_CTRL_DATA_M;
382 }
383
384 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
385 unsigned reg_addr, u16 reg_val)
386 {
387 u32 t;
388 int ret;
389
390 if (phy_addr >= AR7240_NUM_PHYS)
391 return -EINVAL;
392
393 mutex_lock(&reg_mutex);
394 t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
395 (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
396 AR7240_MDIO_CTRL_MASTER_EN |
397 AR7240_MDIO_CTRL_BUSY |
398 AR7240_MDIO_CTRL_CMD_WRITE |
399 reg_val;
400
401 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
402 ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
403 AR7240_MDIO_CTRL_BUSY, 0, 5);
404 mutex_unlock(&reg_mutex);
405
406 return ret;
407 }
408
409 static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
410 {
411 ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
412 AR7240_PORT_CTRL_STATE_DISABLED);
413 }
414
415 static void ar7240sw_setup(struct ar7240sw *as)
416 {
417 struct mii_bus *mii = as->mii_bus;
418
419 /* Enable CPU port, and disable mirror port */
420 ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
421 AR7240_CPU_PORT_EN |
422 (15 << AR7240_MIRROR_PORT_S));
423
424 /* Setup TAG priority mapping */
425 ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
426
427 /* Enable ARP frame acknowledge, aging, MAC replacing */
428 ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
429 0x2b /* 5 min age time */ |
430 AR7240_AT_CTRL_AGE_EN |
431 AR7240_AT_CTRL_ARP_EN |
432 AR7240_AT_CTRL_LEARN_CHANGE);
433
434 /* Enable Broadcast frames transmitted to the CPU */
435 ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
436 AR7240_FLOOD_MASK_BROAD_TO_CPU);
437
438 /* setup MTU */
439 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
440 1536);
441
442 /* setup Service TAG */
443 ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
444 }
445
446 static int ar7240sw_reset(struct ar7240sw *as)
447 {
448 struct mii_bus *mii = as->mii_bus;
449 int ret;
450 int i;
451
452 /* Set all ports to disabled state. */
453 for (i = 0; i < AR7240_NUM_PORTS; i++)
454 ar7240sw_disable_port(as, i);
455
456 /* Wait for transmit queues to drain. */
457 msleep(2);
458
459 /* Reset the switch. */
460 ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
461 AR7240_MASK_CTRL_SOFT_RESET);
462
463 ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
464 AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
465
466 ar7240sw_setup(as);
467 return ret;
468 }
469
470 static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
471 {
472 struct mii_bus *mii = as->mii_bus;
473 u32 ctrl;
474 u32 vlan;
475
476 ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
477 AR7240_PORT_CTRL_SINGLE_VLAN;
478
479 if (port == AR7240_PORT_CPU) {
480 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
481 AR7240_PORT_STATUS_SPEED_1000 |
482 AR7240_PORT_STATUS_TXFLOW |
483 AR7240_PORT_STATUS_RXFLOW |
484 AR7240_PORT_STATUS_TXMAC |
485 AR7240_PORT_STATUS_RXMAC |
486 AR7240_PORT_STATUS_DUPLEX);
487 } else {
488 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
489 AR7240_PORT_STATUS_LINK_AUTO);
490 }
491
492 /* Set the default VID for this port */
493 if (as->vlan) {
494 vlan = as->vlan_id[as->pvid[port]];
495 vlan |= AR7240_PORT_VLAN_MODE_SECURE <<
496 AR7240_PORT_VLAN_MODE_S;
497 } else {
498 vlan = port;
499 vlan |= AR7240_PORT_VLAN_MODE_PORT_ONLY <<
500 AR7240_PORT_VLAN_MODE_S;
501 }
502
503 if (as->vlan && (as->vlan_tagged & BIT(port))) {
504 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
505 AR7240_PORT_CTRL_VLAN_MODE_S;
506 } else {
507 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
508 AR7240_PORT_CTRL_VLAN_MODE_S;
509 }
510
511 if (!portmask) {
512 if (port == AR7240_PORT_CPU)
513 portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
514 else
515 portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
516 }
517
518 /* allow the port to talk to all other ports, but exclude its
519 * own ID to prevent frames from being reflected back to the
520 * port that they came from */
521 portmask &= ar7240sw_port_mask_but(as, port);
522
523 /* set default VID and and destination ports for this VLAN */
524 vlan |= (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
525
526 ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
527 ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
528 }
529
530 static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
531 {
532 struct mii_bus *mii = as->mii_bus;
533 u32 t;
534
535 t = (addr[4] << 8) | addr[5];
536 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
537
538 t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
539 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
540
541 return 0;
542 }
543
544 static int
545 ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
546 struct switch_val *val)
547 {
548 struct ar7240sw *as = sw_to_ar7240(dev);
549 as->vlan_id[val->port_vlan] = val->value.i;
550 return 0;
551 }
552
553 static int
554 ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
555 struct switch_val *val)
556 {
557 struct ar7240sw *as = sw_to_ar7240(dev);
558 val->value.i = as->vlan_id[val->port_vlan];
559 return 0;
560 }
561
562 static int
563 ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
564 {
565 struct ar7240sw *as = sw_to_ar7240(dev);
566
567 /* make sure no invalid PVIDs get set */
568
569 if (vlan >= dev->vlans)
570 return -EINVAL;
571
572 as->pvid[port] = vlan;
573 return 0;
574 }
575
576 static int
577 ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
578 {
579 struct ar7240sw *as = sw_to_ar7240(dev);
580 *vlan = as->pvid[port];
581 return 0;
582 }
583
584 static int
585 ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
586 {
587 struct ar7240sw *as = sw_to_ar7240(dev);
588 u8 ports = as->vlan_table[val->port_vlan];
589 int i;
590
591 val->len = 0;
592 for (i = 0; i < as->swdev.ports; i++) {
593 struct switch_port *p;
594
595 if (!(ports & (1 << i)))
596 continue;
597
598 p = &val->value.ports[val->len++];
599 p->id = i;
600 if (as->vlan_tagged & (1 << i))
601 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
602 else
603 p->flags = 0;
604 }
605 return 0;
606 }
607
608 static int
609 ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
610 {
611 struct ar7240sw *as = sw_to_ar7240(dev);
612 u8 *vt = &as->vlan_table[val->port_vlan];
613 int i, j;
614
615 *vt = 0;
616 for (i = 0; i < val->len; i++) {
617 struct switch_port *p = &val->value.ports[i];
618
619 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
620 as->vlan_tagged |= (1 << p->id);
621 else {
622 as->vlan_tagged &= ~(1 << p->id);
623 as->pvid[p->id] = val->port_vlan;
624
625 /* make sure that an untagged port does not
626 * appear in other vlans */
627 for (j = 0; j < AR7240_MAX_VLANS; j++) {
628 if (j == val->port_vlan)
629 continue;
630 as->vlan_table[j] &= ~(1 << p->id);
631 }
632 }
633
634 *vt |= 1 << p->id;
635 }
636 return 0;
637 }
638
639 static int
640 ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
641 struct switch_val *val)
642 {
643 struct ar7240sw *as = sw_to_ar7240(dev);
644 as->vlan = !!val->value.i;
645 return 0;
646 }
647
648 static int
649 ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
650 struct switch_val *val)
651 {
652 struct ar7240sw *as = sw_to_ar7240(dev);
653 val->value.i = as->vlan;
654 return 0;
655 }
656
657 static const char *
658 ar7240_speed_str(u32 status)
659 {
660 u32 speed;
661
662 speed = (status >> AR7240_PORT_STATUS_SPEED_S) &
663 AR7240_PORT_STATUS_SPEED_M;
664 switch (speed) {
665 case AR7240_PORT_STATUS_SPEED_10:
666 return "10baseT";
667 case AR7240_PORT_STATUS_SPEED_100:
668 return "100baseT";
669 case AR7240_PORT_STATUS_SPEED_1000:
670 return "1000baseT";
671 }
672
673 return "unknown";
674 }
675
676 static int
677 ar7240_port_get_link(struct switch_dev *dev, const struct switch_attr *attr,
678 struct switch_val *val)
679 {
680 struct ar7240sw *as = sw_to_ar7240(dev);
681 struct mii_bus *mii = as->mii_bus;
682 u32 len;
683 u32 status;
684 int port;
685
686 port = val->port_vlan;
687
688 memset(as->buf, '\0', sizeof(as->buf));
689 status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
690
691 if (status & AR7240_PORT_STATUS_LINK_UP) {
692 len = snprintf(as->buf, sizeof(as->buf),
693 "port:%d link:up speed:%s %s-duplex %s%s%s",
694 port,
695 ar7240_speed_str(status),
696 (status & AR7240_PORT_STATUS_DUPLEX) ?
697 "full" : "half",
698 (status & AR7240_PORT_STATUS_TXFLOW) ?
699 "txflow ": "",
700 (status & AR7240_PORT_STATUS_RXFLOW) ?
701 "rxflow " : "",
702 (status & AR7240_PORT_STATUS_LINK_AUTO) ?
703 "auto ": "");
704 } else {
705 len = snprintf(as->buf, sizeof(as->buf),
706 "port:%d link:down", port);
707 }
708
709 val->value.s = as->buf;
710 val->len = len;
711
712 return 0;
713 }
714
715 static void
716 ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
717 {
718 struct mii_bus *mii = as->mii_bus;
719
720 if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
721 return;
722
723 if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
724 val &= AR7240_VTUDATA_MEMBER;
725 val |= AR7240_VTUDATA_VALID;
726 ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
727 }
728 op |= AR7240_VTU_ACTIVE;
729 ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
730 }
731
732 static int
733 ar7240_hw_apply(struct switch_dev *dev)
734 {
735 struct ar7240sw *as = sw_to_ar7240(dev);
736 u8 portmask[AR7240_NUM_PORTS];
737 int i, j;
738
739 /* flush all vlan translation unit entries */
740 ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
741
742 memset(portmask, 0, sizeof(portmask));
743 if (as->vlan) {
744 /* calculate the port destination masks and load vlans
745 * into the vlan translation unit */
746 for (j = 0; j < AR7240_MAX_VLANS; j++) {
747 u8 vp = as->vlan_table[j];
748
749 if (!vp)
750 continue;
751
752 for (i = 0; i < as->swdev.ports; i++) {
753 u8 mask = (1 << i);
754 if (vp & mask)
755 portmask[i] |= vp & ~mask;
756 }
757
758 ar7240_vtu_op(as,
759 AR7240_VTU_OP_LOAD |
760 (as->vlan_id[j] << AR7240_VTU_VID_S),
761 as->vlan_table[j]);
762 }
763 } else {
764 /* vlan disabled:
765 * isolate all ports, but connect them to the cpu port */
766 for (i = 0; i < as->swdev.ports; i++) {
767 if (i == AR7240_PORT_CPU)
768 continue;
769
770 portmask[i] = 1 << AR7240_PORT_CPU;
771 portmask[AR7240_PORT_CPU] |= (1 << i);
772 }
773 }
774
775 /* update the port destination mask registers and tag settings */
776 for (i = 0; i < as->swdev.ports; i++)
777 ar7240sw_setup_port(as, i, portmask[i]);
778
779 return 0;
780 }
781
782 static int
783 ar7240_reset_switch(struct switch_dev *dev)
784 {
785 struct ar7240sw *as = sw_to_ar7240(dev);
786 ar7240sw_reset(as);
787 return 0;
788 }
789
790 static struct switch_attr ar7240_globals[] = {
791 {
792 .type = SWITCH_TYPE_INT,
793 .name = "enable_vlan",
794 .description = "Enable VLAN mode",
795 .set = ar7240_set_vlan,
796 .get = ar7240_get_vlan,
797 .max = 1
798 },
799 };
800
801 static struct switch_attr ar7240_port[] = {
802 {
803 .type = SWITCH_TYPE_STRING,
804 .name = "link",
805 .description = "Get port link information",
806 .max = 1,
807 .set = NULL,
808 .get = ar7240_port_get_link,
809 },
810 };
811
812 static struct switch_attr ar7240_vlan[] = {
813 {
814 .type = SWITCH_TYPE_INT,
815 .name = "vid",
816 .description = "VLAN ID",
817 .set = ar7240_set_vid,
818 .get = ar7240_get_vid,
819 .max = 4094,
820 },
821 };
822
823 static const struct switch_dev_ops ar7240_ops = {
824 .attr_global = {
825 .attr = ar7240_globals,
826 .n_attr = ARRAY_SIZE(ar7240_globals),
827 },
828 .attr_port = {
829 .attr = ar7240_port,
830 .n_attr = ARRAY_SIZE(ar7240_port),
831 },
832 .attr_vlan = {
833 .attr = ar7240_vlan,
834 .n_attr = ARRAY_SIZE(ar7240_vlan),
835 },
836 .get_port_pvid = ar7240_get_pvid,
837 .set_port_pvid = ar7240_set_pvid,
838 .get_vlan_ports = ar7240_get_ports,
839 .set_vlan_ports = ar7240_set_ports,
840 .apply_config = ar7240_hw_apply,
841 .reset_switch = ar7240_reset_switch,
842 };
843
844 static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
845 {
846 struct mii_bus *mii = ag->mii_bus;
847 struct ar7240sw *as;
848 struct switch_dev *swdev;
849 u32 ctrl;
850 u16 phy_id1;
851 u16 phy_id2;
852 u8 ver;
853 int i;
854
855 phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
856 phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
857 if (phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) {
858 pr_err("%s: unknown phy id '%04x:%04x'\n",
859 ag->dev->name, phy_id1, phy_id2);
860 return NULL;
861 }
862
863 as = kzalloc(sizeof(*as), GFP_KERNEL);
864 if (!as)
865 return NULL;
866
867 as->mii_bus = mii;
868
869 ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
870 ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) & AR7240_MASK_CTRL_VERSION_M;
871 if (ver != 1) {
872 pr_err("%s: unsupported chip, ctrl=%08x\n",
873 ag->dev->name, ctrl);
874 return NULL;
875 }
876
877 swdev = &as->swdev;
878 swdev->name = "AR7240 built-in switch";
879 swdev->ports = AR7240_NUM_PORTS - 1;
880 swdev->cpu_port = AR7240_PORT_CPU;
881 swdev->vlans = AR7240_MAX_VLANS;
882 swdev->ops = &ar7240_ops;
883
884 if (register_switch(&as->swdev, ag->dev) < 0) {
885 kfree(as);
886 return NULL;
887 }
888
889 pr_info("%s: Found an AR7240 built-in switch\n", ag->dev->name);
890
891 /* initialize defaults */
892 for (i = 0; i < AR7240_MAX_VLANS; i++)
893 as->vlan_id[i] = i;
894
895 as->vlan_table[0] = ar7240sw_port_mask_all(as);
896
897 return as;
898 }
899
900 static void link_function(struct work_struct *work) {
901 struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
902 unsigned long flags;
903 int i;
904 int status = 0;
905
906 for (i = 0; i < 4; i++) {
907 int link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
908 if(link & BMSR_LSTATUS) {
909 status = 1;
910 break;
911 }
912 }
913
914 spin_lock_irqsave(&ag->lock, flags);
915 if(status != ag->link) {
916 ag->link = status;
917 ag71xx_link_adjust(ag);
918 }
919 spin_unlock_irqrestore(&ag->lock, flags);
920
921 schedule_delayed_work(&ag->link_work, HZ / 2);
922 }
923
924 void ag71xx_ar7240_start(struct ag71xx *ag)
925 {
926 struct ar7240sw *as = ag->phy_priv;
927
928 ar7240sw_reset(as);
929
930 ag->speed = SPEED_1000;
931 ag->duplex = 1;
932
933 ar7240_set_addr(as, ag->dev->dev_addr);
934 ar7240_hw_apply(&as->swdev);
935
936 schedule_delayed_work(&ag->link_work, HZ / 10);
937 }
938
939 void ag71xx_ar7240_stop(struct ag71xx *ag)
940 {
941 cancel_delayed_work_sync(&ag->link_work);
942 }
943
944 int __devinit ag71xx_ar7240_init(struct ag71xx *ag)
945 {
946 struct ar7240sw *as;
947
948 as = ar7240_probe(ag);
949 if (!as)
950 return -ENODEV;
951
952 ag->phy_priv = as;
953 ar7240sw_reset(as);
954
955 INIT_DELAYED_WORK(&ag->link_work, link_function);
956
957 return 0;
958 }
959
960 void ag71xx_ar7240_cleanup(struct ag71xx *ag)
961 {
962 struct ar7240sw *as = ag->phy_priv;
963
964 if (!as)
965 return;
966
967 unregister_switch(&as->swdev);
968 kfree(as);
969 ag->phy_priv = NULL;
970 }
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