1 #ifndef __IDT_INTEG_H__
2 #define __IDT_INTEG_H__
4 /*******************************************************************************
6 * Copyright 2002 Integrated Device Technology, Inc.
9 * System Integrity register definition.
12 * Author : ryan.holmQVist@idt.com
16 * Revision 1.3 2002/06/06 18:34:04 astichte
17 * Added XXX_PhysicalAddress and XXX_VirtualAddress
19 * Revision 1.2 2002/06/05 18:32:33 astichte
22 * Revision 1.1 2002/05/29 17:33:22 sysarch
23 * jba File moved from vcode/include/idt/acacia
25 ******************************************************************************/
29 INTEG0_PhysicalAddress
= 0x18030000,
30 INTEG_PhysicalAddress
= INTEG0_PhysicalAddress
, // Default
32 INTEG0_VirtualAddress
= 0xb8030000,
33 INTEG_VirtualAddress
= INTEG0_VirtualAddress
, // Default
36 // if you are looing for CEA, try rst.h
39 u32 filler
[0xc] ; // 0x30 bytes unused.
40 u32 errcs
; // sticky use ERRCS_
41 u32 wtcount
; // Watchdog timer count reg.
42 u32 wtcompare
; // Watchdog timer timeout value.
43 u32 wtc
; // Watchdog timer control. use WTC_
48 ERRCS_wto_b
= 0, // In INTEG_t -> errcs
49 ERRCS_wto_m
= 0x00000001,
50 ERRCS_wne_b
= 1, // In INTEG_t -> errcs
51 ERRCS_wne_m
= 0x00000002,
52 ERRCS_ucw_b
= 2, // In INTEG_t -> errcs
53 ERRCS_ucw_m
= 0x00000004,
54 ERRCS_ucr_b
= 3, // In INTEG_t -> errcs
55 ERRCS_ucr_m
= 0x00000008,
56 ERRCS_upw_b
= 4, // In INTEG_t -> errcs
57 ERRCS_upw_m
= 0x00000010,
58 ERRCS_upr_b
= 5, // In INTEG_t -> errcs
59 ERRCS_upr_m
= 0x00000020,
60 ERRCS_udw_b
= 6, // In INTEG_t -> errcs
61 ERRCS_udw_m
= 0x00000040,
62 ERRCS_udr_b
= 7, // In INTEG_t -> errcs
63 ERRCS_udr_m
= 0x00000080,
64 ERRCS_sae_b
= 8, // In INTEG_t -> errcs
65 ERRCS_sae_m
= 0x00000100,
66 ERRCS_wre_b
= 9, // In INTEG_t -> errcs
67 ERRCS_wre_m
= 0x00000200,
69 WTC_en_b
= 0, // In INTEG_t -> wtc
70 WTC_en_m
= 0x00000001,
71 WTC_to_b
= 1, // In INTEG_t -> wtc
72 WTC_to_m
= 0x00000002,
75 #endif // __IDT_INTEG_H__
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