projects / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Cleanup glamo mmc driver.
[openwrt.git] / target / linux / gemini / patches / 001-git_sync.patch
1 --- a/arch/arm/boot/compressed/head.S
2 +++ b/arch/arm/boot/compressed/head.S
3 @@ -9,6 +9,7 @@
4 * published by the Free Software Foundation.
5 */
6 #include <linux/linkage.h>
7 +#include <asm/cache.h>
8
9 /*
10 * Debugging stuff
11 @@ -330,7 +331,7 @@ params: ldr r0, =params_phys
12 * This routine must preserve:
13 * r4, r5, r6, r7, r8
14 */
15 - .align 5
16 + .align L1_CACHE_SHIFT
17 cache_on: mov r3, #8 @ cache_on function
18 b call_cache_fn
19
20 @@ -499,7 +500,7 @@ __common_mmu_cache_on:
21 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
22 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
23 b 1f
24 - .align 5 @ cache line aligned
25 + .align L1_CACHE_SHIFT @ cache line aligned
26 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
27 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
28 sub pc, lr, r0, lsr #32 @ properly flush pipeline
29 @@ -518,7 +519,7 @@ __common_mmu_cache_on:
30 * r8 = atags pointer
31 * r9-r14 = corrupted
32 */
33 - .align 5
34 + .align L1_CACHE_SHIFT
35 reloc_start: add r9, r5, r0
36 sub r9, r9, #128 @ do not copy the stack
37 debug_reloc_start
38 @@ -722,7 +723,7 @@ proc_types:
39 * On exit, r0, r1, r2, r3, r12 corrupted
40 * This routine must preserve: r4, r6, r7
41 */
42 - .align 5
43 + .align L1_CACHE_SHIFT
44 cache_off: mov r3, #12 @ cache_off function
45 b call_cache_fn
46
47 @@ -791,7 +792,7 @@ __armv3_mmu_cache_off:
48 * This routine must preserve:
49 * r0, r4, r5, r6, r7
50 */
51 - .align 5
52 + .align L1_CACHE_SHIFT
53 cache_clean_flush:
54 mov r3, #16
55 b call_cache_fn
56 --- a/arch/arm/include/asm/cache.h
57 +++ b/arch/arm/include/asm/cache.h
58 @@ -4,7 +4,11 @@
59 #ifndef __ASMARM_CACHE_H
60 #define __ASMARM_CACHE_H
61
62 +#ifdef CONFIG_CPU_FA526
63 +#define L1_CACHE_SHIFT 4
64 +#else
65 #define L1_CACHE_SHIFT 5
66 +#endif
67 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
68
69 #endif
70 --- a/arch/arm/include/asm/dma-mapping.h
71 +++ b/arch/arm/include/asm/dma-mapping.h
72 @@ -98,7 +98,7 @@ static inline int dma_set_mask(struct de
73
74 static inline int dma_get_cache_alignment(void)
75 {
76 - return 32;
77 + return L1_CACHE_BYTES;
78 }
79
80 static inline int dma_is_consistent(struct device *dev, dma_addr_t handle)
81 --- a/arch/arm/Kconfig
82 +++ b/arch/arm/Kconfig
83 @@ -825,7 +825,7 @@ config ISA_DMA_API
84 bool
85
86 config PCI
87 - bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE
88 + bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_GEMINI
89 help
90 Find out whether you have a PCI motherboard. PCI is the name of a
91 bus system, i.e. the way the CPU talks to the other stuff inside
92 --- a/arch/arm/kernel/entry-armv.S
93 +++ b/arch/arm/kernel/entry-armv.S
94 @@ -21,6 +21,7 @@
95 #include <mach/entry-macro.S>
96 #include <asm/thread_notify.h>
97 #include <asm/unwind.h>
98 +#include <asm/cache.h>
99
100 #include "entry-header.S"
101
102 @@ -153,7 +154,7 @@ ENDPROC(__und_invalid)
103 stmia r5, {r0 - r4}
104 .endm
105
106 - .align 5
107 + .align L1_CACHE_SHIFT
108 __dabt_svc:
109 svc_entry
110
111 @@ -202,7 +203,7 @@ __dabt_svc:
112 UNWIND(.fnend )
113 ENDPROC(__dabt_svc)
114
115 - .align 5
116 + .align L1_CACHE_SHIFT
117 __irq_svc:
118 svc_entry
119
120 @@ -247,7 +248,7 @@ svc_preempt:
121 b 1b
122 #endif
123
124 - .align 5
125 + .align L1_CACHE_SHIFT
126 __und_svc:
127 #ifdef CONFIG_KPROBES
128 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
129 @@ -286,7 +287,7 @@ __und_svc:
130 UNWIND(.fnend )
131 ENDPROC(__und_svc)
132
133 - .align 5
134 + .align L1_CACHE_SHIFT
135 __pabt_svc:
136 svc_entry
137
138 @@ -329,7 +330,7 @@ __pabt_svc:
139 UNWIND(.fnend )
140 ENDPROC(__pabt_svc)
141
142 - .align 5
143 + .align L1_CACHE_SHIFT
144 .LCcralign:
145 .word cr_alignment
146 #ifdef MULTI_DABORT
147 @@ -400,7 +401,7 @@ ENDPROC(__pabt_svc)
148 #endif
149 .endm
150
151 - .align 5
152 + .align L1_CACHE_SHIFT
153 __dabt_usr:
154 usr_entry
155 kuser_cmpxchg_check
156 @@ -432,7 +433,7 @@ __dabt_usr:
157 UNWIND(.fnend )
158 ENDPROC(__dabt_usr)
159
160 - .align 5
161 + .align L1_CACHE_SHIFT
162 __irq_usr:
163 usr_entry
164 kuser_cmpxchg_check
165 @@ -465,7 +466,7 @@ ENDPROC(__irq_usr)
166
167 .ltorg
168
169 - .align 5
170 + .align L1_CACHE_SHIFT
171 __und_usr:
172 usr_entry
173
174 @@ -668,7 +669,7 @@ __und_usr_unknown:
175 b do_undefinstr
176 ENDPROC(__und_usr_unknown)
177
178 - .align 5
179 + .align L1_CACHE_SHIFT
180 __pabt_usr:
181 usr_entry
182
183 @@ -778,7 +779,7 @@ ENDPROC(__switch_to)
184 #endif
185 .endm
186
187 - .align 5
188 + .align L1_CACHE_SHIFT
189 .globl __kuser_helper_start
190 __kuser_helper_start:
191
192 @@ -818,7 +819,7 @@ __kuser_memory_barrier: @ 0xffff0fa0
193 smp_dmb
194 usr_ret lr
195
196 - .align 5
197 + .align L1_CACHE_SHIFT
198
199 /*
200 * Reference prototype:
201 @@ -950,7 +951,7 @@ kuser_cmpxchg_fixup:
202
203 #endif
204
205 - .align 5
206 + .align L1_CACHE_SHIFT
207
208 /*
209 * Reference prototype:
210 @@ -1032,7 +1033,7 @@ __kuser_helper_end:
211 * of which is copied into r0 for the mode specific abort handler.
212 */
213 .macro vector_stub, name, mode, correction=0
214 - .align 5
215 + .align L1_CACHE_SHIFT
216
217 vector_\name:
218 .if \correction
219 @@ -1157,7 +1158,7 @@ __stubs_start:
220 .long __und_invalid @ e
221 .long __und_invalid @ f
222
223 - .align 5
224 + .align L1_CACHE_SHIFT
225
226 /*=============================================================================
227 * Undefined FIQs
228 @@ -1187,7 +1188,7 @@ vector_addrexcptn:
229 * We group all the following data together to optimise
230 * for CPUs with separate I & D caches.
231 */
232 - .align 5
233 + .align L1_CACHE_SHIFT
234
235 .LCvswi:
236 .word vector_swi
237 --- a/arch/arm/kernel/entry-common.S
238 +++ b/arch/arm/kernel/entry-common.S
239 @@ -10,13 +10,14 @@
240
241 #include <asm/unistd.h>
242 #include <asm/ftrace.h>
243 +#include <asm/cache.h>
244 #include <mach/entry-macro.S>
245 #include <asm/unwind.h>
246
247 #include "entry-header.S"
248
249
250 - .align 5
251 + .align L1_CACHE_SHIFT
252 /*
253 * This is the fast syscall return path. We do as little as
254 * possible here, and this includes saving r0 back into the SVC
255 @@ -178,7 +179,7 @@ ftrace_stub:
256 #define A710(code...)
257 #endif
258
259 - .align 5
260 + .align L1_CACHE_SHIFT
261 ENTRY(vector_swi)
262 sub sp, sp, #S_FRAME_SIZE
263 stmia sp, {r0 - r12} @ Calling r0 - r12
264 @@ -306,7 +307,7 @@ __sys_trace_return:
265 bl syscall_trace
266 b ret_slow_syscall
267
268 - .align 5
269 + .align L1_CACHE_SHIFT
270 #ifdef CONFIG_ALIGNMENT_TRAP
271 .type __cr_alignment, #object
272 __cr_alignment:
273 --- a/arch/arm/kernel/head.S
274 +++ b/arch/arm/kernel/head.S
275 @@ -21,6 +21,7 @@
276 #include <asm/memory.h>
277 #include <asm/thread_info.h>
278 #include <asm/system.h>
279 +#include <asm/cache.h>
280
281 #if (PHYS_OFFSET & 0x001fffff)
282 #error "PHYS_OFFSET must be at an even 2MiB boundary!"
283 @@ -187,7 +188,7 @@ ENDPROC(__enable_mmu)
284 *
285 * other registers depend on the function called upon completion
286 */
287 - .align 5
288 + .align L1_CACHE_SHIFT
289 __turn_mmu_on:
290 mov r0, r0
291 mcr p15, 0, r0, c1, c0, 0 @ write control reg
292 --- a/arch/arm/kernel/vmlinux.lds.S
293 +++ b/arch/arm/kernel/vmlinux.lds.S
294 @@ -6,6 +6,7 @@
295 #include <asm-generic/vmlinux.lds.h>
296 #include <asm/thread_info.h>
297 #include <asm/memory.h>
298 +#include <asm/cache.h>
299
300 OUTPUT_ARCH(arm)
301 ENTRY(stext)
302 @@ -58,7 +59,7 @@ SECTIONS
303 *(.security_initcall.init)
304 __security_initcall_end = .;
305 #ifdef CONFIG_BLK_DEV_INITRD
306 - . = ALIGN(32);
307 + . = ALIGN(L1_CACHE_BYTES);
308 __initramfs_start = .;
309 usr/built-in.o(.init.ramfs)
310 __initramfs_end = .;
311 @@ -165,13 +166,13 @@ SECTIONS
312 /*
313 * then the cacheline aligned data
314 */
315 - . = ALIGN(32);
316 + . = ALIGN(L1_CACHE_BYTES);
317 *(.data.cacheline_aligned)
318
319 /*
320 * The exception fixup table (might need resorting at runtime)
321 */
322 - . = ALIGN(32);
323 + . = ALIGN(L1_CACHE_BYTES);
324 __start___ex_table = .;
325 #ifdef CONFIG_MMU
326 *(__ex_table)
327 --- a/arch/arm/lib/copy_page.S
328 +++ b/arch/arm/lib/copy_page.S
329 @@ -12,11 +12,12 @@
330 #include <linux/linkage.h>
331 #include <asm/assembler.h>
332 #include <asm/asm-offsets.h>
333 +#include <asm/cache.h>
334
335 #define COPY_COUNT (PAGE_SZ/64 PLD( -1 ))
336
337 .text
338 - .align 5
339 + .align L1_CACHE_SHIFT
340 /*
341 * StrongARM optimised copy_page routine
342 * now 1.78bytes/cycle, was 1.60 bytes/cycle (50MHz bus -> 89MB/s)
343 --- a/arch/arm/lib/memchr.S
344 +++ b/arch/arm/lib/memchr.S
345 @@ -11,9 +11,10 @@
346 */
347 #include <linux/linkage.h>
348 #include <asm/assembler.h>
349 +#include <asm/cache.h>
350
351 .text
352 - .align 5
353 + .align L1_CACHE_SHIFT
354 ENTRY(memchr)
355 1: subs r2, r2, #1
356 bmi 2f
357 --- a/arch/arm/lib/memset.S
358 +++ b/arch/arm/lib/memset.S
359 @@ -11,9 +11,10 @@
360 */
361 #include <linux/linkage.h>
362 #include <asm/assembler.h>
363 +#include <asm/cache.h>
364
365 .text
366 - .align 5
367 + .align L1_CACHE_SHIFT
368 .word 0
369
370 1: subs r2, r2, #4 @ 1 do we have enough
371 --- a/arch/arm/lib/memzero.S
372 +++ b/arch/arm/lib/memzero.S
373 @@ -9,9 +9,10 @@
374 */
375 #include <linux/linkage.h>
376 #include <asm/assembler.h>
377 +#include <asm/cache.h>
378
379 .text
380 - .align 5
381 + .align L1_CACHE_SHIFT
382 .word 0
383 /*
384 * Align the pointer in r0. r3 contains the number of bytes that we are
385 --- a/arch/arm/lib/strchr.S
386 +++ b/arch/arm/lib/strchr.S
387 @@ -11,9 +11,10 @@
388 */
389 #include <linux/linkage.h>
390 #include <asm/assembler.h>
391 +#include <asm/cache.h>
392
393 .text
394 - .align 5
395 + .align L1_CACHE_SHIFT
396 ENTRY(strchr)
397 and r1, r1, #0xff
398 1: ldrb r2, [r0], #1
399 --- a/arch/arm/lib/strncpy_from_user.S
400 +++ b/arch/arm/lib/strncpy_from_user.S
401 @@ -10,9 +10,10 @@
402 #include <linux/linkage.h>
403 #include <asm/assembler.h>
404 #include <asm/errno.h>
405 +#include <asm/cache.h>
406
407 .text
408 - .align 5
409 + .align L1_CACHE_SHIFT
410
411 /*
412 * Copy a string from user space to kernel space.
413 --- a/arch/arm/lib/strnlen_user.S
414 +++ b/arch/arm/lib/strnlen_user.S
415 @@ -10,9 +10,10 @@
416 #include <linux/linkage.h>
417 #include <asm/assembler.h>
418 #include <asm/errno.h>
419 +#include <asm/cache.h>
420
421 .text
422 - .align 5
423 + .align L1_CACHE_SHIFT
424
425 /* Prototype: unsigned long __strnlen_user(const char *str, long n)
426 * Purpose : get length of a string in user memory
427 --- a/arch/arm/lib/strrchr.S
428 +++ b/arch/arm/lib/strrchr.S
429 @@ -11,9 +11,10 @@
430 */
431 #include <linux/linkage.h>
432 #include <asm/assembler.h>
433 +#include <asm/cache.h>
434
435 .text
436 - .align 5
437 + .align L1_CACHE_SHIFT
438 ENTRY(strrchr)
439 mov r3, #0
440 1: ldrb r2, [r0], #1
441 --- /dev/null
442 +++ b/arch/arm/mach-gemini/board-nas4220b.c
443 @@ -0,0 +1,160 @@
444 +/*
445 + * Support for Raidsonic NAS-4220-B
446 + *
447 + * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
448 + *
449 + * based on rut1xx.c
450 + * Copyright (C) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
451 + *
452 + * This program is free software; you can redistribute it and/or modify
453 + * it under the terms of the GNU General Public License as published by
454 + * the Free Software Foundation; either version 2 of the License, or
455 + * (at your option) any later version.
456 + */
457 +
458 +#include <linux/kernel.h>
459 +#include <linux/init.h>
460 +#include <linux/platform_device.h>
461 +#include <linux/leds.h>
462 +#include <linux/input.h>
463 +#include <linux/gpio_keys.h>
464 +#include <linux/mdio-gpio.h>
465 +#include <linux/io.h>
466 +
467 +#include <asm/setup.h>
468 +#include <asm/mach-types.h>
469 +#include <asm/mach/arch.h>
470 +#include <asm/mach/time.h>
471 +
472 +#include <mach/gmac.h>
473 +#include <mach/hardware.h>
474 +#include <mach/global_reg.h>
475 +
476 +#include "common.h"
477 +
478 +static struct sys_timer ib4220b_timer = {
479 + .init = gemini_timer_init,
480 +};
481 +
482 +static struct gpio_led ib4220b_leds[] = {
483 + {
484 + .name = "nas4220b:orange:hdd",
485 + .default_trigger = "ide-disk",
486 + .gpio = 60,
487 + },
488 + {
489 + .name = "nas4220b:green:os",
490 + .default_trigger = "heartbeat",
491 + .gpio = 62,
492 + },
493 +};
494 +
495 +static struct gpio_led_platform_data ib4220b_leds_data = {
496 + .num_leds = ARRAY_SIZE(ib4220b_leds),
497 + .leds = ib4220b_leds,
498 +};
499 +
500 +static struct platform_device ib4220b_led_device = {
501 + .name = "leds-gpio",
502 + .id = -1,
503 + .dev = {
504 + .platform_data = &ib4220b_leds_data,
505 + },
506 +};
507 +
508 +static struct gpio_keys_button ib4220b_keys[] = {
509 + {
510 + .code = KEY_SETUP,
511 + .gpio = 61,
512 + .active_low = 1,
513 + .desc = "Backup Button",
514 + .type = EV_KEY,
515 + },
516 + {
517 + .code = KEY_RESTART,
518 + .gpio = 63,
519 + .active_low = 1,
520 + .desc = "Softreset Button",
521 + .type = EV_KEY,
522 + },
523 +};
524 +
525 +static struct gpio_keys_platform_data ib4220b_keys_data = {
526 + .buttons = ib4220b_keys,
527 + .nbuttons = ARRAY_SIZE(ib4220b_keys),
528 +};
529 +
530 +static struct platform_device ib4220b_key_device = {
531 + .name = "gpio-keys",
532 + .id = -1,
533 + .dev = {
534 + .platform_data = &ib4220b_keys_data,
535 + },
536 +};
537 +
538 +static struct mdio_gpio_platform_data ib4220b_mdio = {
539 + .mdc = 22,
540 + .mdio = 21,
541 + .phy_mask = ~(1 << 1),
542 +};
543 +
544 +static struct platform_device ib4220b_phy_device = {
545 + .name = "mdio-gpio",
546 + .id = 0,
547 + .dev = {
548 + .platform_data = &ib4220b_mdio,
549 + },
550 +};
551 +
552 +static struct gemini_gmac_platform_data ib4220b_gmac_data = {
553 + .bus_id[0] = "0:01",
554 + .interface[0] = PHY_INTERFACE_MODE_RGMII,
555 +};
556 +
557 +static void __init gmac_ib4220b_init(void)
558 +{
559 + unsigned int val;
560 +
561 + val = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
562 + GLOBAL_IO_DRIVING_CTRL);
563 + val |= (0x3 << GMAC0_PADS_SHIFT) | (0x3 << GMAC1_PADS_SHIFT);
564 + __raw_writel(val, IO_ADDRESS(GEMINI_GLOBAL_BASE) +
565 + GLOBAL_IO_DRIVING_CTRL);
566 +
567 + val = (0x0 << GMAC0_RXDV_SKEW_SHIFT) | (0xf << GMAC0_RXC_SKEW_SHIFT) |
568 + (0x7 << GMAC0_TXEN_SKEW_SHIFT) | (0xa << GMAC0_TXC_SKEW_SHIFT) |
569 + (0x0 << GMAC1_RXDV_SKEW_SHIFT) | (0xf << GMAC1_RXC_SKEW_SHIFT) |
570 + (0x7 << GMAC1_TXEN_SKEW_SHIFT) | (0xa << GMAC1_TXC_SKEW_SHIFT);
571 + __raw_writel(val, IO_ADDRESS(GEMINI_GLOBAL_BASE) +
572 + GLOBAL_GMAC_CTRL_SKEW_CTRL);
573 +
574 + val = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
575 + GLOBAL_ARBITRATION1_CTRL);
576 + val |= (0x20 << BURST_LENGTH_SHIFT);
577 + __raw_writel(val, IO_ADDRESS(GEMINI_GLOBAL_BASE) +
578 + GLOBAL_ARBITRATION1_CTRL);
579 +}
580 +
581 +static void __init ib4220b_init(void)
582 +{
583 + gemini_gpio_init();
584 + gmac_ib4220b_init();
585 + platform_register_uart();
586 + platform_register_usb(0);
587 + platform_register_usb(1);
588 + platform_register_pflash(SZ_16M, NULL, 0);
589 + platform_device_register(&ib4220b_led_device);
590 + platform_device_register(&ib4220b_key_device);
591 + platform_device_register(&ib4220b_phy_device);
592 + platform_register_ethernet(&ib4220b_gmac_data);
593 +}
594 +
595 +MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
596 + .phys_io = 0x7fffc000,
597 + .io_pg_offst = ((0xffffc000) >> 18) & 0xfffc,
598 + .boot_params = 0x100,
599 + .map_io = gemini_map_io,
600 + .init_irq = gemini_init_irq,
601 + .timer = &ib4220b_timer,
602 + .init_machine = ib4220b_init,
603 +MACHINE_END
604 --- a/arch/arm/mach-gemini/board-rut1xx.c
605 +++ b/arch/arm/mach-gemini/board-rut1xx.c
606 @@ -14,13 +14,35 @@
607 #include <linux/leds.h>
608 #include <linux/input.h>
609 #include <linux/gpio_keys.h>
610 +#include <linux/mdio-gpio.h>
611
612 #include <asm/mach-types.h>
613 #include <asm/mach/arch.h>
614 #include <asm/mach/time.h>
615
616 +#include <mach/gmac.h>
617 +
618 #include "common.h"
619
620 +static struct mdio_gpio_platform_data rut1xx_mdio = {
621 + .mdc = 22,
622 + .mdio = 21,
623 + .phy_mask = ~(1 << 1),
624 +};
625 +
626 +static struct platform_device rut1xx_phy_device = {
627 + .name = "mdio-gpio",
628 + .id = 0,
629 + .dev = {
630 + .platform_data = &rut1xx_mdio,
631 + },
632 +};
633 +
634 +static struct gemini_gmac_platform_data gmac_data = {
635 + .bus_id[0] = "0:01",
636 + .interface[0] = PHY_INTERFACE_MODE_MII,
637 +};
638 +
639 static struct gpio_keys_button rut1xx_keys[] = {
640 {
641 .code = KEY_SETUP,
642 @@ -79,9 +101,13 @@ static void __init rut1xx_init(void)
643 {
644 gemini_gpio_init();
645 platform_register_uart();
646 + platform_register_watchdog();
647 + platform_register_usb(0);
648 platform_register_pflash(SZ_8M, NULL, 0);
649 platform_device_register(&rut1xx_leds);
650 platform_device_register(&rut1xx_keys_device);
651 + platform_device_register(&rut1xx_phy_device);
652 + platform_register_ethernet(&gmac_data);
653 }
654
655 MACHINE_START(RUT100, "Teltonika RUT100")
656 --- a/arch/arm/mach-gemini/common.h
657 +++ b/arch/arm/mach-gemini/common.h
658 @@ -13,6 +13,7 @@
659 #define __GEMINI_COMMON_H__
660
661 struct mtd_partition;
662 +struct gemini_gmac_platform_data;
663
664 extern void gemini_map_io(void);
665 extern void gemini_init_irq(void);
666 @@ -21,8 +22,11 @@ extern void gemini_gpio_init(void);
667
668 /* Common platform devices registration functions */
669 extern int platform_register_uart(void);
670 +extern int platform_register_ethernet(struct gemini_gmac_platform_data *pdata);
671 extern int platform_register_pflash(unsigned int size,
672 struct mtd_partition *parts,
673 unsigned int nr_parts);
674 +extern int platform_register_usb(unsigned int i);
675 +extern int platform_register_watchdog(void);
676
677 #endif /* __GEMINI_COMMON_H__ */
678 --- a/arch/arm/mach-gemini/devices.c
679 +++ b/arch/arm/mach-gemini/devices.c
680 @@ -17,6 +17,7 @@
681 #include <mach/irqs.h>
682 #include <mach/hardware.h>
683 #include <mach/global_reg.h>
684 +#include <mach/gmac.h>
685
686 static struct plat_serial8250_port serial_platform_data[] = {
687 {
688 @@ -45,6 +46,116 @@ int platform_register_uart(void)
689 return platform_device_register(&serial_device);
690 }
691
692 +static struct resource usb0_resources[] = {
693 + {
694 + .start = 0x68000000,
695 + .end = 0x68000fff,
696 + .flags = IORESOURCE_MEM,
697 + },
698 + {
699 + .start = IRQ_USB0,
700 + .end = IRQ_USB0,
701 + .flags = IORESOURCE_IRQ,
702 + },
703 +};
704 +
705 +static struct resource usb1_resources[] = {
706 + {
707 + .start = 0x69000000,
708 + .end = 0x69000fff,
709 + .flags = IORESOURCE_MEM,
710 + },
711 + {
712 + .start = IRQ_USB1,
713 + .end = IRQ_USB1,
714 + .flags = IORESOURCE_IRQ,
715 + },
716 +};
717 +
718 +static u64 usb0_dmamask = 0xffffffffUL;
719 +
720 +static u64 usb1_dmamask = 0xffffffffUL;
721 +
722 +static struct platform_device usb_device[] = {
723 + {
724 + .name = "ehci-fotg2xx",
725 + .id = 0,
726 + .dev = {
727 + .dma_mask = &usb0_dmamask,
728 + .coherent_dma_mask = 0xffffffff,
729 + },
730 + .num_resources = ARRAY_SIZE(usb0_resources),
731 + .resource = usb0_resources,
732 + },
733 + {
734 + .name = "ehci-fotg2xx",
735 + .id = 1,
736 + .dev = {
737 + .dma_mask = &usb1_dmamask,
738 + .coherent_dma_mask = 0xffffffff,
739 + },
740 + .num_resources = ARRAY_SIZE(usb1_resources),
741 + .resource = usb1_resources,
742 + },
743 +};
744 +
745 +int platform_register_usb(unsigned int i)
746 +{
747 + if (i > 1)
748 + return -EINVAL;
749 +
750 + return platform_device_register(&usb_device[i]);
751 +}
752 +
753 +static struct resource gmac_resources[] = {
754 + {
755 + .start = 0x60000000,
756 + .end = 0x6000ffff,
757 + .flags = IORESOURCE_MEM,
758 + },
759 + {
760 + .start = IRQ_GMAC0,
761 + .end = IRQ_GMAC0,
762 + .flags = IORESOURCE_IRQ,
763 + },
764 + {
765 + .start = IRQ_GMAC1,
766 + .end = IRQ_GMAC1,
767 + .flags = IORESOURCE_IRQ,
768 + },
769 +};
770 +
771 +static u64 gmac_dmamask = 0xffffffffUL;
772 +
773 +static struct platform_device ethernet_device = {
774 + .name = "gemini-gmac",
775 + .id = 0,
776 + .dev = {
777 + .dma_mask = &gmac_dmamask,
778 + .coherent_dma_mask = 0xffffffff,
779 + },
780 + .num_resources = ARRAY_SIZE(gmac_resources),
781 + .resource = gmac_resources,
782 +};
783 +
784 +int platform_register_ethernet(struct gemini_gmac_platform_data *pdata)
785 +{
786 + unsigned int reg = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL);
787 +
788 + reg &= ~(GMAC_GMII | GMAC_1_ENABLE);
789 +
790 + if (pdata->bus_id[1])
791 + reg |= GMAC_1_ENABLE;
792 + else if (pdata->interface[0] == PHY_INTERFACE_MODE_GMII)
793 + reg |= GMAC_GMII;
794 +
795 + __raw_writel(reg, IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL);
796 +
797 + ethernet_device.dev.platform_data = pdata;
798 +
799 + return platform_device_register(&ethernet_device);
800 +}
801 +
802 static struct resource flash_resource = {
803 .start = GEMINI_FLASH_BASE,
804 .flags = IORESOURCE_MEM,
805 @@ -90,3 +201,21 @@ int platform_register_pflash(unsigned in
806
807 return platform_device_register(&pflash_device);
808 }
809 +
810 +static struct resource wdt_resource = {
811 + .start = GEMINI_WAQTCHDOG_BASE,
812 + .end = GEMINI_WAQTCHDOG_BASE + 0x18,
813 + .flags = IORESOURCE_MEM,
814 +};
815 +
816 +static struct platform_device wdt_device = {
817 + .name = "gemini-wdt",
818 + .id = 0,
819 + .resource = &wdt_resource,
820 + .num_resources = 1,
821 +};
822 +
823 +int platform_register_watchdog(void)
824 +{
825 + return platform_device_register(&wdt_device);
826 +}
827 --- /dev/null
828 +++ b/arch/arm/mach-gemini/include/mach/gmac.h
829 @@ -0,0 +1,21 @@
830 +/*
831 + * Gemini GMAC specific defines
832 + *
833 + * Copyright (C) 2008, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
834 + *
835 + * This program is free software; you can redistribute it and/or modify
836 + * it under the terms of the GNU General Public License as published by
837 + * the Free Software Foundation; either version 2 of the License, or
838 + * (at your option) any later version.
839 + */
840 +#ifndef __MACH_GMAC_H__
841 +#define __MACH_GMAC_H__
842 +
843 +#include <linux/phy.h>
844 +
845 +struct gemini_gmac_platform_data {
846 + char *bus_id[2]; /* NULL means that this port is not used */
847 + phy_interface_t interface[2];
848 +};
849 +
850 +#endif /* __MACH_GMAC_H__ */
851 --- a/arch/arm/mach-gemini/include/mach/hardware.h
852 +++ b/arch/arm/mach-gemini/include/mach/hardware.h
853 @@ -71,4 +71,12 @@
854 */
855 #define IO_ADDRESS(x) ((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000)
856
857 +/*
858 + * PCI subsystem macros
859 + */
860 +#define PCIBIOS_MIN_IO 0x00000100
861 +#define PCIBIOS_MIN_MEM 0x00000000
862 +
863 +#define pcibios_assign_all_busses() 1
864 +
865 #endif
866 --- a/arch/arm/mach-gemini/include/mach/irqs.h
867 +++ b/arch/arm/mach-gemini/include/mach/irqs.h
868 @@ -43,11 +43,14 @@
869
870 #define NORMAL_IRQ_NUM 32
871
872 -#define GPIO_IRQ_BASE NORMAL_IRQ_NUM
873 +#define PCI_IRQ_BASE NORMAL_IRQ_NUM
874 +#define PCI_IRQ_NUM 4
875 +
876 +#define GPIO_IRQ_BASE (NORMAL_IRQ_NUM + PCI_IRQ_NUM)
877 #define GPIO_IRQ_NUM (3 * 32)
878
879 #define ARCH_TIMER_IRQ IRQ_TIMER2
880
881 -#define NR_IRQS (NORMAL_IRQ_NUM + GPIO_IRQ_NUM)
882 +#define NR_IRQS (NORMAL_IRQ_NUM + PCI_IRQ_NUM + GPIO_IRQ_NUM)
883
884 #endif /* __MACH_IRQS_H__ */
885 --- a/arch/arm/mach-gemini/Kconfig
886 +++ b/arch/arm/mach-gemini/Kconfig
887 @@ -2,6 +2,13 @@ if ARCH_GEMINI
888
889 menu "Cortina Systems Gemini Implementations"
890
891 +config MACH_NAS4220B
892 + bool "Raidsonic NAS-4220-B"
893 + select GEMINI_MEM_SWAP
894 + help
895 + Say Y here if you intend to run this kernel on a
896 + Raidsonic NAS-4220-B.
897 +
898 config MACH_RUT100
899 bool "Teltonika RUT100"
900 select GEMINI_MEM_SWAP
901 --- a/arch/arm/mach-gemini/Makefile
902 +++ b/arch/arm/mach-gemini/Makefile
903 @@ -6,5 +6,8 @@
904
905 obj-y := irq.o mm.o time.o devices.o gpio.o
906
907 +obj-$(CONFIG_PCI) += pci.o
908 +
909 # Board-specific support
910 +obj-$(CONFIG_MACH_NAS4220B) += board-nas4220b.o
911 obj-$(CONFIG_MACH_RUT100) += board-rut1xx.o
912 --- a/arch/arm/mach-gemini/mm.c
913 +++ b/arch/arm/mach-gemini/mm.c
914 @@ -59,6 +59,11 @@ static struct map_desc gemini_io_desc[]
915 .length = SZ_512K,
916 .type = MT_DEVICE,
917 }, {
918 + .virtual = IO_ADDRESS(GEMINI_PCI_IO_BASE),
919 + .pfn = __phys_to_pfn(GEMINI_PCI_IO_BASE),
920 + .length = SZ_512K,
921 + .type = MT_DEVICE,
922 + }, {
923 .virtual = IO_ADDRESS(GEMINI_FLASH_CTRL_BASE),
924 .pfn = __phys_to_pfn(GEMINI_FLASH_CTRL_BASE),
925 .length = SZ_512K,
926 --- /dev/null
927 +++ b/arch/arm/mach-gemini/pci.c
928 @@ -0,0 +1,315 @@
929 +/*
930 + * Support for Gemini PCI Controller
931 + *
932 + * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
933 + * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
934 + *
935 + * based on SL2312 PCI controller code
936 + * Storlink (C) 2003
937 + *
938 + * This program is free software; you can redistribute it and/or modify
939 + * it under the terms of the GNU General Public License as published by
940 + * the Free Software Foundation; either version 2 of the License, or
941 + * (at your option) any later version.
942 + */
943 +
944 +#include <linux/kernel.h>
945 +#include <linux/pci.h>
946 +#include <linux/irq.h>
947 +
948 +#include <asm/mach/pci.h>
949 +#include <asm/gpio.h>
950 +
951 +#include <mach/irqs.h>
952 +
953 +#define GEMINI_PCI_IOSIZE_1M 0x0000
954 +
955 +#define GEMINI_PCI_PMC 0x40
956 +#define GEMINI_PCI_PMCSR 0x44
957 +#define GEMINI_PCI_CTRL1 0x48
958 +#define GEMINI_PCI_CTRL2 0x4C
959 +#define GEMINI_PCI_MEM1_BASE_SIZE 0x50
960 +#define GEMINI_PCI_MEM2_BASE_SIZE 0x54
961 +#define GEMINI_PCI_MEM3_BASE_SIZE 0x58
962 +
963 +#define PCI_CTRL2_INTSTS_OFFSET 28
964 +#define PCI_CTRL2_INTMASK_OFFSET 22
965 +
966 +#define GEMINI_PCI_DMA_MASK 0xFFF00000
967 +#define GEMINI_PCI_DMA_MEM1_BASE 0x00000000
968 +#define GEMINI_PCI_DMA_MEM2_BASE 0x00000000
969 +#define GEMINI_PCI_DMA_MEM3_BASE 0x00000000
970 +#define GEMINI_PCI_DMA_MEM1_SIZE 7
971 +#define GEMINI_PCI_DMA_MEM2_SIZE 6
972 +#define GEMINI_PCI_DMA_MEM3_SIZE 6
973 +
974 +#define PCI_CONF_ENABLE (1 << 31)
975 +#define PCI_CONF_WHERE(r) ((r) & 0xFC)
976 +#define PCI_CONF_BUS(b) (((b) & 0xFF) << 16)
977 +#define PCI_CONF_DEVICE(d) (((d) & 0x1F) << 11)
978 +#define PCI_CONF_FUNCTION(f) (((f) & 0x07) << 8)
979 +
980 +#define PCI_IOSIZE_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE))
981 +#define PCI_PROT_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x04)
982 +#define PCI_CTRL_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x08)
983 +#define PCI_SOFTRST_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x10)
984 +#define PCI_CONFIG_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x28)
985 +#define PCI_DATA_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x2C)
986 +
987 +
988 +static DEFINE_SPINLOCK(gemini_pci_lock);
989 +
990 +static struct resource gemini_pci_resource_io = {
991 + .name = "PCI I/O Space",
992 + .start = IO_ADDRESS(GEMINI_PCI_IO_BASE),
993 + .end = IO_ADDRESS(GEMINI_PCI_IO_BASE) + SZ_1M - 1,
994 + .flags = IORESOURCE_IO,
995 +};
996 +
997 +static struct resource gemini_pci_resource_mem = {
998 + .name = "PCI Memory Space",
999 + .start = GEMINI_PCI_MEM_BASE,
1000 + .end = GEMINI_PCI_MEM_BASE + SZ_128M - 1,
1001 + .flags = IORESOURCE_MEM,
1002 +};
1003 +
1004 +static int gemini_pci_read_config(struct pci_bus* bus, unsigned int fn,
1005 + int config, int size, u32* value)
1006 +{
1007 + unsigned long irq_flags;
1008 +
1009 + spin_lock_irqsave(&gemini_pci_lock, irq_flags);
1010 +
1011 + __raw_writel(PCI_CONF_BUS(bus->number) |
1012 + PCI_CONF_DEVICE(PCI_SLOT(fn)) |
1013 + PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
1014 + PCI_CONF_WHERE(config) |
1015 + PCI_CONF_ENABLE,
1016 + PCI_CONFIG_REG);
1017 +
1018 + *value = __raw_readl(PCI_DATA_REG);
1019 +
1020 + if (size == 1)
1021 + *value = (*value >> (8 * (config & 3))) & 0xFF;
1022 + else if (size == 2)
1023 + *value = (*value >> (8 * (config & 3))) & 0xFFFF;
1024 +
1025 + spin_unlock_irqrestore(&gemini_pci_lock, irq_flags);
1026 +
1027 + dev_dbg(&bus->dev,
1028 + "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
1029 + PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
1030 +
1031 + return PCIBIOS_SUCCESSFUL;
1032 +}
1033 +
1034 +static int gemini_pci_write_config(struct pci_bus* bus, unsigned int fn,
1035 + int config, int size, u32 value)
1036 +{
1037 + unsigned long irq_flags = 0;
1038 + int ret = PCIBIOS_SUCCESSFUL;
1039 +
1040 + dev_dbg(&bus->dev,
1041 + "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
1042 + PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
1043 +
1044 + spin_lock_irqsave(&gemini_pci_lock, irq_flags);
1045 +
1046 + __raw_writel(PCI_CONF_BUS(bus->number) |
1047 + PCI_CONF_DEVICE(PCI_SLOT(fn)) |
1048 + PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
1049 + PCI_CONF_WHERE(config) |
1050 + PCI_CONF_ENABLE,
1051 + PCI_CONFIG_REG);
1052 +
1053 + switch(size) {
1054 + case 4:
1055 + __raw_writel(value, PCI_DATA_REG);
1056 + break;
1057 + case 2:
1058 + __raw_writew(value, PCI_DATA_REG + (config & 3));
1059 + break;
1060 + case 1:
1061 + __raw_writeb(value, PCI_DATA_REG + (config & 3));
1062 + break;
1063 + default:
1064 + ret = PCIBIOS_BAD_REGISTER_NUMBER;
1065 + }
1066 +
1067 + spin_unlock_irqrestore(&gemini_pci_lock, irq_flags);
1068 +
1069 + return ret;
1070 +}
1071 +
1072 +static struct pci_ops gemini_pci_ops = {
1073 + .read = gemini_pci_read_config,
1074 + .write = gemini_pci_write_config,
1075 +};
1076 +
1077 +static int __init gemini_pci_request_resources(struct pci_sys_data *sys)
1078 +{
1079 + if (request_resource(&ioport_resource, &gemini_pci_resource_io))
1080 + goto bad_resources;
1081 + if (request_resource(&iomem_resource, &gemini_pci_resource_mem))
1082 + goto bad_resources;
1083 +
1084 + sys->resource[0] = &gemini_pci_resource_io;
1085 + sys->resource[1] = &gemini_pci_resource_mem;
1086 + sys->resource[2] = 0;
1087 +
1088 + return 0;
1089 +
1090 +bad_resources:
1091 + pr_err("Gemini PCI: request_resource() failed. "
1092 + "Abort PCI bus enumeration.\n");
1093 + return -1;
1094 +}
1095 +
1096 +static int __init gemini_pci_setup(int nr, struct pci_sys_data *sys)
1097 +{
1098 + unsigned int cmd;
1099 +
1100 + if ((nr > 0) || gemini_pci_request_resources(sys))
1101 + return 0;
1102 +
1103 + /* setup I/O space to 1MB size */
1104 + __raw_writel(GEMINI_PCI_IOSIZE_1M, PCI_IOSIZE_REG);
1105 +
1106 + /* setup hostbridge */
1107 + cmd = __raw_readl(PCI_CTRL_REG);
1108 + cmd |= PCI_COMMAND_IO;
1109 + cmd |= PCI_COMMAND_MEMORY;
1110 + cmd |= PCI_COMMAND_MASTER;
1111 + __raw_writel(cmd, PCI_CTRL_REG);
1112 +
1113 + return 1;
1114 +}
1115 +
1116 +static struct pci_bus* __init gemini_pci_scan_bus(int nr, struct pci_sys_data* sys)
1117 +{
1118 + unsigned int reg = 0;
1119 + struct pci_bus* bus = 0;
1120 +
1121 + bus = pci_scan_bus(nr, &gemini_pci_ops, sys);
1122 + if (bus) {
1123 + dev_dbg(&bus->dev, "setting up PCI DMA\n");
1124 + reg = (GEMINI_PCI_DMA_MEM1_BASE & GEMINI_PCI_DMA_MASK)
1125 + | (GEMINI_PCI_DMA_MEM1_SIZE << 16);
1126 + gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM1_BASE_SIZE, 4, reg);
1127 + reg = (GEMINI_PCI_DMA_MEM2_BASE & GEMINI_PCI_DMA_MASK)
1128 + | (GEMINI_PCI_DMA_MEM2_SIZE << 16);
1129 + gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM2_BASE_SIZE, 4, reg);
1130 + reg = (GEMINI_PCI_DMA_MEM3_BASE & GEMINI_PCI_DMA_MASK)
1131 + | (GEMINI_PCI_DMA_MEM3_SIZE << 16);
1132 + gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM3_BASE_SIZE, 4, reg);
1133 + }
1134 +
1135 + return bus;
1136 +}
1137 +
1138 +/* Should work with all boards based on original Storlink EVB */
1139 +static int __init gemini_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
1140 +{
1141 + if (slot < 9 || slot > 12)
1142 + return -1;
1143 +
1144 + return PCI_IRQ_BASE + (((slot - 9) + (pin - 1)) & 0x3);
1145 +}
1146 +
1147 +static struct hw_pci gemini_hw_pci __initdata = {
1148 + .nr_controllers = 1,
1149 + .setup = gemini_pci_setup,
1150 + .scan = gemini_pci_scan_bus,
1151 + .swizzle = pci_std_swizzle,
1152 + .map_irq = gemini_pci_map_irq,
1153 +};
1154 +
1155 +/* we need this for muxed PCI interrupts handling */
1156 +static struct pci_bus bogus_pci_bus;
1157 +
1158 +static void gemini_pci_ack_irq(unsigned int irq)
1159 +{
1160 + unsigned int reg;
1161 +
1162 + gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, &reg);
1163 + reg &= ~(0xF << PCI_CTRL2_INTSTS_OFFSET);
1164 + reg |= 1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTSTS_OFFSET);
1165 + gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
1166 +}
1167 +
1168 +static void gemini_pci_mask_irq(unsigned int irq)
1169 +{
1170 + unsigned int reg;
1171 +
1172 + gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, &reg);
1173 + reg &= ~((0xF << PCI_CTRL2_INTSTS_OFFSET)
1174 + | (1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTMASK_OFFSET)));
1175 + gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
1176 +}
1177 +
1178 +static void gemini_pci_unmask_irq(unsigned int irq)
1179 +{
1180 + unsigned int reg;
1181 +
1182 + gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, &reg);
1183 + reg &= ~(0xF << PCI_CTRL2_INTSTS_OFFSET);
1184 + reg |= 1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTMASK_OFFSET);
1185 + gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
1186 +}
1187 +
1188 +static void gemini_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
1189 +{
1190 + unsigned int pci_irq_no, irq_stat, reg, i;
1191 +
1192 + gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, &reg);
1193 + irq_stat = reg >> PCI_CTRL2_INTSTS_OFFSET;
1194 +
1195 + for (i = 0; i < 4; i++) {
1196 +
1197 + if ((irq_stat & (1 << i)) == 0)
1198 + continue;
1199 +
1200 + pci_irq_no = PCI_IRQ_BASE + i;
1201 +
1202 + BUG_ON(!(irq_desc[pci_irq_no].handle_irq));
1203 + irq_desc[pci_irq_no].handle_irq(pci_irq_no,
1204 + &irq_desc[pci_irq_no]);
1205 + }
1206 +}
1207 +
1208 +static struct irq_chip gemini_pci_irq_chip = {
1209 + .name = "PCI",
1210 + .ack = gemini_pci_ack_irq,
1211 + .mask = gemini_pci_mask_irq,
1212 + .unmask = gemini_pci_unmask_irq,
1213 +};
1214 +
1215 +static int __init gemini_pci_init(void)
1216 +{
1217 + int i;
1218 +
1219 + for (i = 72; i <= 95; i++)
1220 + gpio_request(i, "PCI");
1221 +
1222 + /* initialize our bogus bus */
1223 + dev_set_name(&bogus_pci_bus.dev, "PCI IRQ handler");
1224 + bogus_pci_bus.number = 0;
1225 +
1226 + /* mask and clear all interrupts */
1227 + gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2 + 2, 2,
1228 + 0xF000);
1229 +
1230 + for (i = PCI_IRQ_BASE; i < PCI_IRQ_BASE + 4; i++) {
1231 + set_irq_chip(i, &gemini_pci_irq_chip);
1232 + set_irq_handler(i, handle_level_irq);
1233 + set_irq_flags(i, IRQF_VALID);
1234 + }
1235 +
1236 + set_irq_chained_handler(IRQ_PCI, gemini_pci_irq_handler);
1237 +
1238 + pci_common_init(&gemini_hw_pci);
1239 +
1240 + return 0;
1241 +}
1242 +
1243 +subsys_initcall(gemini_pci_init);
1244 --- a/arch/arm/mm/abort-ev4.S
1245 +++ b/arch/arm/mm/abort-ev4.S
1246 @@ -1,5 +1,6 @@
1247 #include <linux/linkage.h>
1248 #include <asm/assembler.h>
1249 +#include <asm/cache.h>
1250 /*
1251 * Function: v4_early_abort
1252 *
1253 @@ -17,7 +18,7 @@
1254 * abort here if the I-TLB and D-TLB aren't seeing the same
1255 * picture. Unfortunately, this does happen. We live with it.
1256 */
1257 - .align 5
1258 + .align L1_CACHE_SHIFT
1259 ENTRY(v4_early_abort)
1260 mrc p15, 0, r1, c5, c0, 0 @ get FSR
1261 mrc p15, 0, r0, c6, c0, 0 @ get FAR
1262 --- a/arch/arm/mm/abort-nommu.S
1263 +++ b/arch/arm/mm/abort-nommu.S
1264 @@ -1,5 +1,6 @@
1265 #include <linux/linkage.h>
1266 #include <asm/assembler.h>
1267 +#include <asm/cache.h>
1268 /*
1269 * Function: nommu_early_abort
1270 *
1271 @@ -12,7 +13,7 @@
1272 * Note: There is no FSR/FAR on !CPU_CP15_MMU cores.
1273 * Just fill zero into the registers.
1274 */
1275 - .align 5
1276 + .align L1_CACHE_SHIFT
1277 ENTRY(nommu_early_abort)
1278 mov r0, #0 @ clear r0, r1 (no FSR/FAR)
1279 mov r1, #0
1280 --- /dev/null
1281 +++ b/drivers/net/gemini_negmac/gm_gmac.c
1282 @@ -0,0 +1,1350 @@
1283 +/*
1284 + * Ethernet device driver for Gemini SoC.
1285 + *
1286 + * Copyright (C) 2006, Storlink, Corp.
1287 + * Copyright (C) 2008-2009, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
1288 + *
1289 + * This program is free software; you can redistribute it and/or modify
1290 + * it under the terms of the GNU General Public License as published by
1291 + * the Free Software Foundation; either version 2 of the License, or
1292 + * (at your option) any later version.
1293 + */
1294 +#include <linux/module.h>
1295 +#include <linux/kernel.h>
1296 +#include <linux/platform_device.h>
1297 +#include <linux/slab.h>
1298 +#include <linux/mm.h>
1299 +#include <linux/compiler.h>
1300 +#include <linux/dma-mapping.h>
1301 +#include <linux/init.h>
1302 +#include <linux/ioport.h>
1303 +#include <linux/netdevice.h>
1304 +#include <linux/etherdevice.h>
1305 +#include <linux/rtnetlink.h>
1306 +#include <linux/delay.h>
1307 +#include <linux/ethtool.h>
1308 +#include <linux/mii.h>
1309 +#include <linux/phy.h>
1310 +#include <linux/completion.h>
1311 +#include <linux/kthread.h>
1312 +#include <linux/io.h>
1313 +#include <mach/hardware.h>
1314 +#include <asm/irq.h>
1315 +#include <linux/semaphore.h>
1316 +#include <mach/irqs.h>
1317 +#include <linux/skbuff.h>
1318 +#include <linux/in.h>
1319 +#include <linux/ip.h>
1320 +#include <linux/tcp.h>
1321 +#include <linux/udp.h>
1322 +#include <mach/gmac.h>
1323 +
1324 +#include "gm_gmac.h"
1325 +
1326 +/* #define GMAX_TX_INTR_DISABLED */
1327 +#define DO_HW_CHKSUM
1328 +/* #define ENABLE_TSO */
1329 +#define GMAC_USE_TXQ0
1330 +/* #define GMAC_LEN_1_2_ISSUE */
1331 +
1332 +#define DEFAULT_RXQ_MAX_CNT 256
1333 +
1334 +/* define chip information */
1335 +#define DRV_VERSION "0.2"
1336 +#define SL351x_DRIVER_NAME "Gemini Ethernet driver " DRV_VERSION
1337 +
1338 +#ifdef GMAC_LEN_1_2_ISSUE
1339 + #define _DEBUG_PREFETCH_NUM 256
1340 +static int _debug_prefetch_cnt;
1341 +static char _debug_prefetch_buf[_DEBUG_PREFETCH_NUM][4] __attribute__((aligned(4)));
1342 +#endif
1343 +
1344 +static inline void gmac_write_reg(unsigned int base, unsigned int offset, unsigned int data, unsigned int bit_mask)
1345 +{
1346 + unsigned int reg_val;
1347 +
1348 + reg_val = (__raw_readl(base + offset) & (~bit_mask)) | (data & bit_mask);
1349 + __raw_writel(reg_val, base + offset);
1350 +}
1351 +
1352 +/*----------------------------------------------------------------------
1353 +* toe_init_free_queue
1354 +* (1) Initialize the Free Queue Descriptor Base Address & size
1355 +* Register: TOE_GLOBAL_BASE + 0x0004
1356 +* (2) Initialize DMA Read/Write pointer for
1357 +* SW Free Queue and HW Free Queue
1358 +* (3) Initialize DMA Descriptors for
1359 +* SW Free Queue and HW Free Queue,
1360 +*----------------------------------------------------------------------*/
1361 +static void toe_init_free_queue(struct toe_private *toe)
1362 +{
1363 + int i;
1364 + DMA_RWPTR_T rwptr_reg;
1365 + void *desc_buf;
1366 + GMAC_RXDESC_T *sw_desc_ptr;
1367 + struct sk_buff *skb;
1368 +
1369 + desc_buf = dma_alloc_coherent(toe->dev, TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T),
1370 + &toe->sw_freeq_desc_base_dma, GFP_KERNEL);
1371 + sw_desc_ptr = (GMAC_RXDESC_T *)desc_buf;
1372 + if (!desc_buf) {
1373 + dev_err(toe->dev, "%s::DMA ALLOC fail\n", __func__);
1374 + return;
1375 + }
1376 + memset(desc_buf, 0, TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T));
1377 +
1378 + /* DMA Queue Base & Size */
1379 + __raw_writel((toe->sw_freeq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_SW_FREEQ_DESC_POWER,
1380 + toe->global_base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
1381 +
1382 + /* init descriptor base */
1383 + toe->swfq_desc_base = (unsigned int)desc_buf;
1384 +
1385 + /* SW Free Queue Descriptors */
1386 + for (i = 0; i < TOE_SW_FREEQ_DESC_NUM; i++) {
1387 + sw_desc_ptr->word0.bits.buffer_size = SW_RX_BUF_SIZE;
1388 + skb = dev_alloc_skb(SW_RX_BUF_SIZE); /* allocate socket buffer */
1389 + if (!skb) {
1390 + dev_err(toe->dev, "%s::skb buffer allocation fail\n", __func__);
1391 + return;
1392 + }
1393 + REG32(skb->data) = (unsigned int)skb;
1394 + skb_reserve(skb, SKB_RESERVE_BYTES);
1395 + sw_desc_ptr->word2.buf_adr = dma_map_single(toe->dev, skb->data,
1396 + SW_RX_BUF_SIZE - SKB_RESERVE_BYTES,
1397 + DMA_FROM_DEVICE);
1398 + sw_desc_ptr++;
1399 + }
1400 +
1401 + dma_sync_single_for_device(toe->dev, toe->sw_freeq_desc_base_dma,
1402 + TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T),
1403 + DMA_TO_DEVICE);
1404 +
1405 + /* SW Free Queue Read/Write Pointer */
1406 + rwptr_reg.bits.wptr = TOE_SW_FREEQ_DESC_NUM - 1;
1407 + rwptr_reg.bits.rptr = 0;
1408 + __raw_writel(rwptr_reg.bits32, toe->global_base + GLOBAL_SWFQ_RWPTR_REG);
1409 +
1410 + /* DMA Queue Base & Size */
1411 + __raw_writel(TOE_HW_FREEQ_DESC_POWER,
1412 + toe->global_base + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
1413 + rwptr_reg.bits.wptr = TOE_HW_FREEQ_DESC_NUM - 1;
1414 + rwptr_reg.bits.rptr = 0;
1415 + __raw_writel(rwptr_reg.bits32, toe->global_base + GLOBAL_HWFQ_RWPTR_REG);
1416 +}
1417 +
1418 +/*----------------------------------------------------------------------
1419 +* toe_init_swtx_queue
1420 +* (2) Initialize the GMAC 0/1 SW TXQ Queue Descriptor Base Address & sizeup
1421 +* GMAC_SW_TX_QUEUE_BASE_REG(0x0050)
1422 +* (2) Initialize DMA Read/Write pointer for
1423 +* GMAC 0/1 SW TX Q0-5
1424 +*----------------------------------------------------------------------*/
1425 +static void toe_init_swtx_queue(struct net_device *dev)
1426 +{
1427 + int i;
1428 + struct gmac_private *gmac = netdev_priv(dev);
1429 + struct toe_private *toe = dev->ml_priv;
1430 + DMA_RWPTR_T rwptr_reg;
1431 + unsigned int rwptr_addr;
1432 + void *desc_buf;
1433 + unsigned int offset;
1434 +
1435 + desc_buf = dma_alloc_coherent(toe->dev, TOE_GMAC_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T),
1436 + &gmac->swtxq_desc_base_dma, GFP_KERNEL);
1437 + gmac->swtxq_desc_base = (unsigned int)desc_buf;
1438 + if (!desc_buf) {
1439 + dev_err(toe->dev, "%s::DMA ALLOC fail\n", __func__);
1440 + return;
1441 + }
1442 + memset(desc_buf, 0, TOE_GMAC_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T));
1443 + dma_sync_single_for_device(toe->dev, gmac->swtxq_desc_base_dma,
1444 + TOE_GMAC_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T),
1445 + DMA_TO_DEVICE);
1446 + __raw_writel((gmac->swtxq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_GMAC_SWTXQ_DESC_POWER,
1447 + gmac->dma_base_addr + GMAC_SW_TX_QUEUE_BASE_REG);
1448 +
1449 + /* GMAC0 SW TX Q0-Q5 */
1450 + offset = 0;
1451 + rwptr_reg.bits.wptr = 0;
1452 + rwptr_reg.bits.rptr = 0;
1453 + rwptr_addr = gmac->dma_base_addr + GMAC_SW_TX_QUEUE0_PTR_REG;
1454 + for (i = 0; i < TOE_SW_TXQ_NUM; i++) {
1455 + gmac->swtxq[i].rwptr_reg = rwptr_addr;
1456 + gmac->swtxq[i].desc_base_dma = (unsigned int)gmac->swtxq_desc_base_dma + offset;
1457 + gmac->swtxq[i].desc_base = (unsigned int)desc_buf + offset;
1458 + offset += TOE_GMAC_SWTXQ_DESC_NUM * sizeof(GMAC_TXDESC_T);
1459 + __raw_writel(rwptr_reg.bits32, rwptr_addr);
1460 + rwptr_addr += 4;
1461 + }
1462 +}
1463 +
1464 +/*----------------------------------------------------------------------
1465 +* toe_init_default_queue
1466 +* (1) Initialize the default 0/1 Queue Header
1467 +* Register: TOE_DEFAULT_Q0_HDR_BASE (0x60002000)
1468 +* TOE_DEFAULT_Q1_HDR_BASE (0x60002008)
1469 +* (2) Initialize Descriptors of Default Queue 0/1
1470 +*----------------------------------------------------------------------*/
1471 +static void toe_init_default_queue(struct net_device *dev)
1472 +{
1473 + struct gmac_private *gmac = netdev_priv(dev);
1474 + struct toe_private *toe = dev->ml_priv;
1475 + volatile NONTOE_QHDR_T *qhdr;
1476 + GMAC_RXDESC_T *desc_ptr;
1477 +
1478 + desc_ptr = dma_alloc_coherent(toe->dev, TOE_DEFAULT_Q_DESC_NUM * sizeof(GMAC_RXDESC_T),
1479 + &gmac->default_desc_base_dma, GFP_KERNEL);
1480 + if (!desc_ptr) {
1481 + dev_err(toe->dev, "%s::DMA ALLOC fail\n", __func__);
1482 + return;
1483 + }
1484 + memset(desc_ptr, 0, TOE_DEFAULT_Q_DESC_NUM * sizeof(GMAC_RXDESC_T));
1485 + dma_sync_single_for_device(toe->dev, gmac->default_desc_base_dma,
1486 + TOE_DEFAULT_Q_DESC_NUM * sizeof(GMAC_RXDESC_T),
1487 + DMA_TO_DEVICE);
1488 + gmac->default_desc_base = (unsigned int)desc_ptr;
1489 + qhdr = (volatile NONTOE_QHDR_T *)(toe->global_base + TOE_DEFAULT_Q_HDR_BASE(gmac->port_id));
1490 + qhdr->word0.base_size = ((unsigned int)gmac->default_desc_base_dma & NONTOE_QHDR0_BASE_MASK) | TOE_DEFAULT_Q_DESC_POWER;
1491 + qhdr->word1.bits32 = 0;
1492 + gmac->default_qhdr = (NONTOE_QHDR_T *)qhdr;
1493 +}
1494 +
1495 +/*----------------------------------------------------------------------
1496 +* toe_init_interrupt_config
1497 +* Interrupt Select Registers are used to map interrupt to int0 or int1
1498 +* Int0 and int1 are wired to CPU 0/1 GMAC 0/1
1499 +* Interrupt Device Inteface data are used to pass device info to
1500 +* upper device driver or store status/statistics
1501 +* ISR handler
1502 +* (1) If status bit ON but masked, the prinf error message (bug issue)
1503 +* (2) If select bits are for me, handle it, else skip to let
1504 +* the other ISR handles it.
1505 +* Notes:
1506 +* GMACx init routine (for eCOS) or open routine (for Linux)
1507 +* enable the interrupt bits only which are selected for it.
1508 +*
1509 +* Default Setting:
1510 +* GMAC0 intr bits ------> int0 ----> eth0
1511 +* GMAC1 intr bits ------> int1 ----> eth1
1512 +* TOE intr -------------> int0 ----> eth0
1513 +* Classification Intr --> int0 ----> eth0
1514 +* Default Q0 -----------> int0 ----> eth0
1515 +* Default Q1 -----------> int1 ----> eth1
1516 +*----------------------------------------------------------------------*/
1517 +static void toe_init_interrupt_config(struct toe_private *toe)
1518 +{
1519 + /* clear all status bits */
1520 + __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_0_REG);
1521 + __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_1_REG);
1522 + __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_2_REG);
1523 + __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_3_REG);
1524 + __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_4_REG);
1525 +
1526 + /* Init select registers */
1527 + __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG);
1528 + __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG);
1529 + __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG);
1530 + __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG);
1531 + __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG);
1532 +
1533 + /* disable all interrupt */
1534 + __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1535 + __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1536 + __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_2_REG);
1537 + __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_3_REG);
1538 + __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1539 +}
1540 +
1541 +static void toe_gmac_hw_start(struct gmac_private *gmac)
1542 +{
1543 + GMAC_DMA_CTRL_T dma_ctrl;
1544 +
1545 + /* program dma control register */
1546 + dma_ctrl.bits32 = __raw_readl(gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
1547 + dma_ctrl.bits.rd_enable = 1;
1548 + dma_ctrl.bits.td_enable = 1;
1549 + dma_ctrl.bits.loopback = 0;
1550 + dma_ctrl.bits.drop_small_ack = 0;
1551 + dma_ctrl.bits.rd_prot = 0;
1552 + dma_ctrl.bits.rd_burst_size = 3;
1553 + dma_ctrl.bits.rd_insert_bytes = RX_INSERT_BYTES;
1554 + dma_ctrl.bits.rd_bus = 3;
1555 + dma_ctrl.bits.td_prot = 0;
1556 + dma_ctrl.bits.td_burst_size = 3;
1557 + dma_ctrl.bits.td_bus = 3;
1558 +
1559 + __raw_writel(dma_ctrl.bits32, gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
1560 +}
1561 +
1562 +static void toe_gmac_hw_stop(struct gmac_private *gmac)
1563 +{
1564 + GMAC_DMA_CTRL_T dma_ctrl;
1565 +
1566 + /* program dma control register */
1567 + dma_ctrl.bits32 = __raw_readl(gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
1568 + dma_ctrl.bits.rd_enable = 0;
1569 + dma_ctrl.bits.td_enable = 0;
1570 + __raw_writel(dma_ctrl.bits32, gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
1571 +}
1572 +
1573 +static void toe_gmac_init_chip(struct net_device *dev)
1574 +{
1575 + struct gmac_private *gmac = netdev_priv(dev);
1576 + GMAC_CONFIG2_T config2_val;
1577 + GMAC_CONFIG0_T config0;
1578 + GMAC_CONFIG1_T config1;
1579 + GMAC_STATUS_T status;
1580 + GMAC_TX_WCR0_T hw_weigh;
1581 + GMAC_TX_WCR1_T sw_weigh;
1582 + GMAC_RX_FLTR_T rx_filter;
1583 +
1584 + /* set RX_FLTR register to receive all multicast packet */
1585 + rx_filter.bits32 = __raw_readl(dev->base_addr + GMAC_RX_FLTR);
1586 + rx_filter.bits.unicast = 1;
1587 + rx_filter.bits.multicast = 1;
1588 + rx_filter.bits.broadcast = 1;
1589 + __raw_writel(rx_filter.bits32, dev->base_addr + GMAC_RX_FLTR);
1590 +
1591 + /* set flow control threshold */
1592 + config1.bits32 = 0;
1593 + config1.bits.set_threshold = 32 / 2;
1594 + config1.bits.rel_threshold = 32 / 4 * 3;
1595 + __raw_writel(config1.bits32, dev->base_addr + GMAC_CONFIG1);
1596 +
1597 + /* set flow control threshold */
1598 + config2_val.bits32 = 0;
1599 + config2_val.bits.set_threshold = TOE_SW_FREEQ_DESC_NUM / 4;
1600 + config2_val.bits.rel_threshold = TOE_SW_FREEQ_DESC_NUM / 2;
1601 + __raw_writel(config2_val.bits32, dev->base_addr + GMAC_CONFIG2);
1602 +
1603 + /* disable TX/RX and disable internal loop back */
1604 + config0.bits32 = __raw_readl(dev->base_addr + GMAC_CONFIG0);
1605 +
1606 + config0.bits.max_len = 2;
1607 +
1608 + gmac->flow_control_enable = 0;
1609 +
1610 + config0.bits.tx_fc_en = 0; /* disable tx flow control */
1611 + config0.bits.rx_fc_en = 0; /* disable rx flow control */
1612 + config0.bits.dis_rx = 1; /* disable rx */
1613 + config0.bits.dis_tx = 1; /* disable tx */
1614 + config0.bits.loop_back = 0; /* enable/disable GMAC loopback */
1615 + config0.bits.rx_err_detect = 1;
1616 + config0.bits.rgmii_en = 0;
1617 + config0.bits.rgmm_edge = 1;
1618 + config0.bits.rxc_inv = 0;
1619 + config0.bits.ipv4_rx_chksum = 1; /* enable H/W to check ip checksum */
1620 + config0.bits.ipv6_rx_chksum = 1; /* enable H/W to check ip checksum */
1621 + config0.bits.port0_chk_hwq = 1;
1622 + config0.bits.port1_chk_hwq = 1;
1623 + config0.bits.port0_chk_toeq = 1;
1624 + config0.bits.port1_chk_toeq = 1;
1625 + config0.bits.port0_chk_classq = 1;
1626 + config0.bits.port1_chk_classq = 1;
1627 +
1628 + __raw_writel(config0.bits32, dev->base_addr + GMAC_CONFIG0);
1629 +
1630 + hw_weigh.bits32 = 0;
1631 + hw_weigh.bits.hw_tq3 = 1;
1632 + hw_weigh.bits.hw_tq2 = 1;
1633 + hw_weigh.bits.hw_tq1 = 1;
1634 + hw_weigh.bits.hw_tq0 = 1;
1635 + __raw_writel(hw_weigh.bits32, gmac->dma_base_addr + GMAC_TX_WEIGHTING_CTRL_0_REG);
1636 +
1637 + sw_weigh.bits32 = 0;
1638 + sw_weigh.bits.sw_tq5 = 1;
1639 + sw_weigh.bits.sw_tq4 = 1;
1640 + sw_weigh.bits.sw_tq3 = 1;
1641 + sw_weigh.bits.sw_tq2 = 1;
1642 + sw_weigh.bits.sw_tq1 = 1;
1643 + sw_weigh.bits.sw_tq0 = 1;
1644 + __raw_writel(sw_weigh.bits32, gmac->dma_base_addr + GMAC_TX_WEIGHTING_CTRL_1_REG);
1645 +
1646 + /* set interface type */
1647 + status.bits32 = __raw_readl(dev->base_addr + GMAC_STATUS);
1648 +
1649 + switch (gmac->phydev->interface) {
1650 + case PHY_INTERFACE_MODE_MII:
1651 + status.bits.mii_rmii = GMAC_PHY_MII;
1652 + break;
1653 + case PHY_INTERFACE_MODE_GMII:
1654 + status.bits.mii_rmii = GMAC_PHY_GMII;
1655 + break;
1656 + case PHY_INTERFACE_MODE_RGMII:
1657 + status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
1658 + break;
1659 + default:
1660 + dev_err(&dev->dev, "Unsupported MII interface\n");
1661 + return;
1662 + }
1663 +
1664 + __raw_writel(status.bits32, dev->base_addr + GMAC_STATUS);
1665 +}
1666 +
1667 +static void toe_init_gmac(struct net_device *dev)
1668 +{
1669 + struct gmac_private *gmac = netdev_priv(dev);
1670 + struct toe_private *toe = dev->ml_priv;
1671 + u32 data;
1672 +
1673 + /* GMAC initialization */
1674 + toe_gmac_init_chip(dev);
1675 +
1676 + /* -----------------------------------------------------------
1677 + Enable GMAC interrupt & disable loopback
1678 + Notes:
1679 + GMACx init routine (for eCOS) or open routine (for Linux)
1680 + enable the interrupt bits only which are selected for him.
1681 + --------------------------------------------------------------*/
1682 +
1683 + /* Enable Interrupt Bits */
1684 + if (gmac->port_id == 0) {
1685 + gmac->intr0_selected = GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT |
1686 + GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT |
1687 + GMAC0_SWTQ05_FIN_INT_BIT | GMAC0_SWTQ05_EOF_INT_BIT |
1688 + GMAC0_SWTQ04_FIN_INT_BIT | GMAC0_SWTQ04_EOF_INT_BIT |
1689 + GMAC0_SWTQ03_FIN_INT_BIT | GMAC0_SWTQ03_EOF_INT_BIT |
1690 + GMAC0_SWTQ02_FIN_INT_BIT | GMAC0_SWTQ02_EOF_INT_BIT |
1691 + GMAC0_SWTQ01_FIN_INT_BIT | GMAC0_SWTQ01_EOF_INT_BIT |
1692 + GMAC0_SWTQ00_FIN_INT_BIT | GMAC0_SWTQ00_EOF_INT_BIT;
1693 +
1694 +#ifdef GMAX_TX_INTR_DISABLED
1695 + gmac->intr0_enabled = 0;
1696 +#else
1697 + gmac->intr0_enabled = GMAC0_SWTQ00_FIN_INT_BIT | GMAC0_SWTQ00_EOF_INT_BIT;
1698 +#endif
1699 +
1700 + gmac->intr1_selected = TOE_IQ_ALL_BITS | TOE_CLASS_RX_INT_BITS |
1701 + GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT |
1702 + GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT |
1703 + DEFAULT_Q0_INT_BIT;
1704 + gmac->intr1_enabled = DEFAULT_Q0_INT_BIT | TOE_IQ_ALL_BITS;
1705 + gmac->intr2_selected = 0xffffffff; /* TOE Queue 32-63 FUUL Intr */
1706 + gmac->intr2_enabled = 0xffffffff;
1707 + gmac->intr3_selected = 0xffffffff; /* TOE Queue 0-31 FUUL Intr */
1708 + gmac->intr3_enabled = 0xffffffff;
1709 + gmac->intr4_selected = GMAC0_INT_BITS | CLASS_RX_FULL_INT_BITS |
1710 + HWFQ_EMPTY_INT_BIT | SWFQ_EMPTY_INT_BIT;
1711 + gmac->intr4_enabled = GMAC0_INT_BITS | SWFQ_EMPTY_INT_BIT;
1712 +
1713 + data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG) & ~gmac->intr0_selected;
1714 + __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG);
1715 + data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG) & ~gmac->intr1_selected;
1716 + __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG);
1717 + data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG) & ~gmac->intr2_selected;
1718 + __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG);
1719 + data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG) & ~gmac->intr3_selected;
1720 + __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG);
1721 + data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG) & ~gmac->intr4_selected;
1722 + __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG);
1723 + } else {
1724 + gmac->intr0_selected = GMAC1_TXDERR_INT_BIT | GMAC1_TXPERR_INT_BIT |
1725 + GMAC1_RXDERR_INT_BIT | GMAC1_RXPERR_INT_BIT |
1726 + GMAC1_SWTQ15_FIN_INT_BIT | GMAC1_SWTQ15_EOF_INT_BIT |
1727 + GMAC1_SWTQ14_FIN_INT_BIT | GMAC1_SWTQ14_EOF_INT_BIT |
1728 + GMAC1_SWTQ13_FIN_INT_BIT | GMAC1_SWTQ13_EOF_INT_BIT |
1729 + GMAC1_SWTQ12_FIN_INT_BIT | GMAC1_SWTQ12_EOF_INT_BIT |
1730 + GMAC1_SWTQ11_FIN_INT_BIT | GMAC1_SWTQ11_EOF_INT_BIT |
1731 + GMAC1_SWTQ10_FIN_INT_BIT | GMAC1_SWTQ10_EOF_INT_BIT;
1732 +#ifdef GMAX_TX_INTR_DISABLED
1733 + gmac->intr0_enabled = 0;
1734 +#else
1735 + gmac->intr0_enabled = GMAC1_SWTQ10_FIN_INT_BIT | GMAC1_SWTQ10_EOF_INT_BIT;
1736 +#endif
1737 +
1738 + gmac->intr1_selected = DEFAULT_Q1_INT_BIT;
1739 + gmac->intr1_enabled = DEFAULT_Q1_INT_BIT | TOE_IQ_ALL_BITS;
1740 + gmac->intr2_selected = 0; /* TOE Queue 32-63 FUUL Intr */
1741 + gmac->intr2_enabled = 0;
1742 + gmac->intr3_selected = 0; /* TOE Queue 0-31 FUUL Intr */
1743 + gmac->intr3_enabled = 0;
1744 + gmac->intr4_selected = GMAC1_INT_BITS;
1745 + gmac->intr4_enabled = GMAC1_INT_BITS;
1746 +
1747 + data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG) | gmac->intr0_selected;
1748 + __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG);
1749 + data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG) | gmac->intr1_selected;
1750 + __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG);
1751 + data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG) | gmac->intr2_selected;
1752 + __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG);
1753 + data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG) | gmac->intr3_selected;
1754 + __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG);
1755 + data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG) | gmac->intr4_selected;
1756 + __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG);
1757 + }
1758 +
1759 + /* enable only selected bits */
1760 + gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_0_REG,
1761 + gmac->intr0_enabled, gmac->intr0_selected);
1762 + gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_1_REG,
1763 + gmac->intr1_enabled, gmac->intr1_selected);
1764 + gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_2_REG,
1765 + gmac->intr2_enabled, gmac->intr2_selected);
1766 + gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_3_REG,
1767 + gmac->intr3_enabled, gmac->intr3_selected);
1768 + gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_4_REG,
1769 + gmac->intr4_enabled, gmac->intr4_selected);
1770 +
1771 + /* start DMA process */
1772 + toe_gmac_hw_start(gmac);
1773 +}
1774 +
1775 +static void toe_gmac_enable_tx_rx(struct net_device *dev)
1776 +{
1777 + GMAC_CONFIG0_T config0;
1778 +
1779 + /* enable TX/RX */
1780 + config0.bits32 = __raw_readl(dev->base_addr + GMAC_CONFIG0);
1781 + config0.bits.dis_rx = 0; /* enable rx */
1782 + config0.bits.dis_tx = 0; /* enable tx */
1783 + __raw_writel(config0.bits32, dev->base_addr + GMAC_CONFIG0);
1784 +}
1785 +
1786 +static void toe_gmac_disable_tx_rx(struct net_device *dev)
1787 +{
1788 + GMAC_CONFIG0_T config0;
1789 +
1790 + /* enable TX/RX */
1791 + config0.bits32 = __raw_readl(dev->base_addr + GMAC_CONFIG0);
1792 + config0.bits.dis_rx = 1; /* disable rx */
1793 + config0.bits.dis_tx = 1; /* disable tx */
1794 + __raw_writel(config0.bits32, dev->base_addr + GMAC_CONFIG0);
1795 +}
1796 +
1797 +static void toe_gmac_tx_complete(struct net_device *dev, unsigned int tx_qid)
1798 +{
1799 + struct gmac_private *gmac = netdev_priv(dev);
1800 + struct toe_private *toe = dev->ml_priv;
1801 + GMAC_TXDESC_T *curr_desc;
1802 + GMAC_TXDESC_0_T word0;
1803 + GMAC_TXDESC_1_T word1;
1804 + unsigned int desc_count;
1805 + GMAC_SWTXQ_T *swtxq;
1806 + DMA_RWPTR_T rwptr;
1807 +
1808 + /* get tx H/W completed descriptor virtual address */
1809 + /* check tx status and accumulate tx statistics */
1810 + swtxq = &gmac->swtxq[tx_qid];
1811 + for (;;) {
1812 + rwptr.bits32 = __raw_readl(swtxq->rwptr_reg);
1813 + if (rwptr.bits.rptr == swtxq->finished_idx)
1814 + break;
1815 + curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
1816 + dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
1817 + swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
1818 + sizeof(GMAC_TXDESC_T),
1819 + DMA_FROM_DEVICE);
1820 + word0.bits32 = curr_desc->word0.bits32;
1821 + word1.bits32 = curr_desc->word1.bits32;
1822 +
1823 + if (word0.bits.status_tx_ok) {
1824 + dev->stats.tx_bytes += word1.bits.byte_count;
1825 + desc_count = word0.bits.desc_count;
1826 + if (desc_count == 0) {
1827 + dev_err(&dev->dev, "%s::Desc 0x%x = 0x%x, desc_count=%d\n", __func__, (u32)curr_desc, word0.bits32, desc_count);
1828 + BUG();
1829 + }
1830 + while (--desc_count) {
1831 + word0.bits.status_tx_ok = 0;
1832 + curr_desc->word0.bits32 = word0.bits32;
1833 + dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
1834 + swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
1835 + sizeof(GMAC_TXDESC_T),
1836 + DMA_TO_DEVICE);
1837 + swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, TOE_GMAC_SWTXQ_DESC_NUM);
1838 + curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
1839 + dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
1840 + swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
1841 + sizeof(GMAC_TXDESC_T),
1842 + DMA_FROM_DEVICE);
1843 + word0.bits32 = curr_desc->word0.bits32;
1844 + }
1845 +
1846 + word0.bits.status_tx_ok = 0;
1847 + dev_kfree_skb_any(swtxq->tx_skb[swtxq->finished_idx]);
1848 + swtxq->tx_skb[swtxq->finished_idx] = NULL;
1849 +
1850 + curr_desc->word0.bits32 = word0.bits32;
1851 + dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
1852 + swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
1853 + sizeof(GMAC_TXDESC_T),
1854 + DMA_TO_DEVICE);
1855 + dev->stats.tx_packets++;
1856 + swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, TOE_GMAC_SWTXQ_DESC_NUM);
1857 + } else {
1858 + break;
1859 + }
1860 + }
1861 +
1862 + if (netif_queue_stopped(dev))
1863 + netif_wake_queue(dev);
1864 +}
1865 +
1866 +static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
1867 +{
1868 + struct gmac_private *gmac = netdev_priv(dev);
1869 + struct toe_private *toe = dev->ml_priv;
1870 + DMA_RWPTR_T rwptr;
1871 + GMAC_TXDESC_T *curr_desc;
1872 + int snd_pages = skb_shinfo(skb)->nr_frags + 1; /* get number of descriptor */
1873 + int frag_id = 0;
1874 + int len, total_len = skb->len;
1875 + struct net_device_stats *isPtr = &dev->stats;
1876 + unsigned int free_desc;
1877 + GMAC_SWTXQ_T *swtxq;
1878 + register unsigned long word0, word1, word2, word3;
1879 + unsigned short wptr, rptr;
1880 +
1881 +#ifdef GMAC_LEN_1_2_ISSUE
1882 + int total_pages;
1883 + total_pages = snd_pages;
1884 +#endif
1885 +
1886 + if (skb->len >= 0x10000) {
1887 + isPtr->tx_dropped++;
1888 + dev_err(&dev->dev, "%s::skb->len %d >= 64K\n", __func__, skb->len);
1889 + netif_stop_queue(dev);
1890 + return 1;
1891 + }
1892 +
1893 +#ifdef GMAC_USE_TXQ0
1894 + #define tx_qid 0
1895 +#endif
1896 +
1897 + swtxq = &gmac->swtxq[tx_qid];
1898 +
1899 + rwptr.bits32 = __raw_readl(swtxq->rwptr_reg);
1900 + wptr = rwptr.bits.wptr;
1901 + rptr = rwptr.bits.rptr;
1902 +
1903 + /*
1904 + * check finished desc or empty BD
1905 + * cannot check by read ptr of RW PTR register,
1906 + * because the HW complete to send but the SW may NOT handle it
1907 + */
1908 +#ifdef GMAX_TX_INTR_DISABLED
1909 + toe_gmac_tx_complete(dev, tx_qid);
1910 +#endif
1911 + if (wptr >= swtxq->finished_idx)
1912 + free_desc = TOE_GMAC_SWTXQ_DESC_NUM - wptr + swtxq->finished_idx;
1913 + else
1914 + free_desc = swtxq->finished_idx - wptr;
1915 +
1916 + if (free_desc < snd_pages) {
1917 + isPtr->tx_dropped++;
1918 + netif_stop_queue(dev);
1919 + return 1;
1920 + }
1921 +
1922 + while (snd_pages) {
1923 + char *pkt_datap;
1924 +
1925 + curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + wptr;
1926 + if (frag_id == 0) {
1927 + len = skb_headlen(skb);
1928 + pkt_datap = dma_map_single(toe->dev, skb->data, len, DMA_TO_DEVICE);
1929 + } else {
1930 + skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_id - 1];
1931 + len = frag->size;
1932 + pkt_datap = dma_map_page(toe->dev, frag->page, frag->page_offset, len, DMA_TO_DEVICE);
1933 + }
1934 +
1935 + /* set TX descriptor */
1936 + word0 = len;
1937 + word3 = (dev->mtu + 14) | EOFIE_BIT;
1938 +
1939 +#ifdef DO_HW_CHKSUM
1940 + if (total_len <= 1514 && ip_hdr(skb) && (ip_hdr(skb)->frag_off & __constant_htons(0x3fff)))
1941 + word1 = total_len |
1942 + TSS_IP_CHKSUM_BIT |
1943 + TSS_IPV6_ENABLE_BIT |
1944 + TSS_MTU_ENABLE_BIT;
1945 + else
1946 + word1 = total_len |
1947 + TSS_UDP_CHKSUM_BIT |
1948 + TSS_TCP_CHKSUM_BIT |
1949 + TSS_IP_CHKSUM_BIT |
1950 + TSS_IPV6_ENABLE_BIT |
1951 + TSS_MTU_ENABLE_BIT;
1952 +#else
1953 + word1 = total_len | TSS_MTU_ENABLE_BIT;
1954 +#endif
1955 + word2 = pkt_datap;
1956 +
1957 + if (frag_id == 0)
1958 + word3 |= SOF_BIT;
1959 +
1960 + if (snd_pages == 1) {
1961 + word3 |= EOF_BIT;
1962 + swtxq->tx_skb[wptr] = skb;
1963 + } else
1964 + swtxq->tx_skb[wptr] = NULL;
1965 +
1966 +#ifdef GMAC_LEN_1_2_ISSUE
1967 + if ((total_pages != snd_pages) && (len == 1 || len == 2) && ((u32)pkt_datap & 0x03)) {
1968 + memcpy((void *)&_debug_prefetch_buf[_debug_prefetch_cnt][0], pkt_datap, len);
1969 + pkt_datap = (char *)&_debug_prefetch_buf[_debug_prefetch_cnt][0];
1970 + word2 = (unsigned long)__pa(pkt_datap);
1971 + _debug_prefetch_cnt++;
1972 + if (_debug_prefetch_cnt >= _DEBUG_PREFETCH_NUM)
1973 + _debug_prefetch_cnt = 0;
1974 + }
1975 +#endif
1976 + curr_desc->word0.bits32 = word0;
1977 + curr_desc->word1.bits32 = word1;
1978 + curr_desc->word2.bits32 = word2;
1979 + curr_desc->word3.bits32 = word3;
1980 + free_desc--;
1981 + dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
1982 + wptr * sizeof(GMAC_TXDESC_T),
1983 + sizeof(GMAC_TXDESC_T),
1984 + DMA_TO_DEVICE);
1985 + wptr = RWPTR_ADVANCE_ONE(wptr, TOE_GMAC_SWTXQ_DESC_NUM);
1986 + frag_id++;
1987 + snd_pages--;
1988 + }
1989 +
1990 + SET_WPTR(swtxq->rwptr_reg, wptr);
1991 + dev->trans_start = jiffies;
1992 +
1993 + return 0;
1994 +}
1995 +
1996 +static void __gmac_set_mac_address(struct net_device *dev)
1997 +{
1998 + unsigned int reg_val;
1999 +
2000 + reg_val = dev->dev_addr[0] + (dev->dev_addr[1] << 8) +
2001 + (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2002 + __raw_writel(reg_val, dev->base_addr + GMAC_STA_ADD0);
2003 + reg_val = (__raw_readl(dev->base_addr + GMAC_STA_ADD1) & 0xFFFF0000) +
2004 + dev->dev_addr[4] + (dev->dev_addr[5] << 8);
2005 + __raw_writel(reg_val, dev->base_addr + GMAC_STA_ADD1);
2006 +}
2007 +
2008 +static int gmac_set_mac_address(struct net_device *dev, void *addr)
2009 +{
2010 + struct sockaddr *sa = addr;
2011 +
2012 + memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
2013 +
2014 + __gmac_set_mac_address(dev);
2015 +
2016 + return 0;
2017 +}
2018 +
2019 +static void gmac_get_mac_address(struct net_device *dev)
2020 +{
2021 + unsigned int reg_val;
2022 +
2023 + reg_val = __raw_readl(dev->base_addr + GMAC_STA_ADD0);
2024 + dev->dev_addr[0] = reg_val & 0xFF;
2025 + dev->dev_addr[1] = (reg_val >> 8) & 0xFF;
2026 + dev->dev_addr[2] = (reg_val >> 16) & 0xFF;
2027 + dev->dev_addr[3] = (reg_val >> 24) & 0xFF;
2028 + reg_val = __raw_readl(dev->base_addr + GMAC_STA_ADD1);
2029 + dev->dev_addr[4] = reg_val & 0xFF;
2030 + dev->dev_addr[5] = (reg_val >> 8) & 0xFF;
2031 +
2032 + if (!is_valid_ether_addr(dev->dev_addr)) {
2033 + random_ether_addr(dev->dev_addr);
2034 + __gmac_set_mac_address(dev);
2035 + }
2036 +}
2037 +
2038 +struct net_device_stats *gmac_get_stats(struct net_device *dev)
2039 +{
2040 + if (netif_running(dev)) {
2041 + unsigned short multicast;
2042 +
2043 + multicast = __raw_readw(dev->base_addr + GMAC_IN_MCAST) +
2044 + __raw_readw(dev->base_addr + GMAC_IN_BCAST);
2045 +
2046 + dev->stats.rx_dropped += __raw_readw(dev->base_addr + GMAC_IN_DISCARDS);
2047 + dev->stats.rx_errors += __raw_readw(dev->base_addr + GMAC_IN_ERRORS);
2048 + dev->stats.rx_packets += __raw_readl(dev->base_addr + GMAC_IN_MAC1) + multicast;
2049 + dev->stats.multicast += multicast;
2050 + }
2051 +
2052 + return &dev->stats;
2053 +}
2054 +
2055 +/* TODO: If possible use crc32 from kernel lib */
2056 +static unsigned const ethernet_polynomial = 0x04c11db7U;
2057 +static unsigned int ether_crc(int length, unsigned char *data)
2058 +{
2059 + int crc = -1;
2060 + unsigned int i;
2061 + unsigned int crc_val = 0;
2062 +
2063 + while (--length >= 0) {
2064 + unsigned char current_octet = *data++;
2065 + int bit;
2066 + for (bit = 0; bit < 8; bit++, current_octet >>= 1)
2067 + crc = (crc << 1) ^ ((crc < 0) ^ (current_octet & 1) ?
2068 + ethernet_polynomial : 0);
2069 + }
2070 + crc = ~crc;
2071 + for (i = 0; i < 32; i++)
2072 + crc_val = crc_val + (((crc << i) & 0x80000000) >> (31 - i));
2073 +
2074 + return crc_val;
2075 +}
2076 +
2077 +/*----------------------------------------------------------------------
2078 +* toe_gmac_fill_free_q
2079 +* allocate buffers for free queue.
2080 +*----------------------------------------------------------------------*/
2081 +static void toe_gmac_fill_free_q(struct toe_private *toe)
2082 +{
2083 + struct sk_buff *skb;
2084 + DMA_RWPTR_T fq_rwptr;
2085 + GMAC_RXDESC_T *fq_desc;
2086 + unsigned long flags;
2087 +
2088 + spin_lock_irqsave(&toe->freeq_lock, flags);
2089 + fq_rwptr.bits32 = __raw_readl(toe->global_base + GLOBAL_SWFQ_RWPTR_REG);
2090 + while ((unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
2091 + TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
2092 + skb = dev_alloc_skb(SW_RX_BUF_SIZE);
2093 + if (skb == NULL) {
2094 + dev_err(toe->dev, "%s::skb allocation fail\n", __func__);
2095 + break;
2096 + }
2097 + REG32(skb->data) = (unsigned int)skb;
2098 + skb_reserve(skb, SKB_RESERVE_BYTES);
2099 + fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
2100 + TOE_SW_FREEQ_DESC_NUM);
2101 + fq_desc = (GMAC_RXDESC_T *)toe->swfq_desc_base + fq_rwptr.bits.wptr;
2102 + fq_desc->word2.buf_adr = dma_map_single(toe->dev, skb->data,
2103 + SW_RX_BUF_SIZE - SKB_RESERVE_BYTES,
2104 + DMA_FROM_DEVICE);
2105 + dma_sync_single_range_for_device(toe->dev,
2106 + toe->sw_freeq_desc_base_dma,
2107 + fq_rwptr.bits.wptr * sizeof(GMAC_RXDESC_T),
2108 + sizeof(GMAC_RXDESC_T),
2109 + DMA_TO_DEVICE);
2110 + SET_WPTR(toe->global_base + GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
2111 + }
2112 + spin_unlock_irqrestore(&toe->freeq_lock, flags);
2113 +}
2114 +
2115 +static void fill_free_q_worker(struct work_struct *work)
2116 +{
2117 + struct toe_private *toe = container_of(work, struct toe_private, freq_work);
2118 +
2119 + toe_gmac_fill_free_q(toe);
2120 +}
2121 +
2122 +/*----------------------------------------------------------------------
2123 +* toe_gmac_handle_default_rxq
2124 +* (1) Get rx Buffer for default Rx queue
2125 +* (2) notify or call upper-routine to handle it
2126 +* (3) get a new buffer and insert it into SW free queue
2127 +* (4) Note: The SW free queue Read-Write Pointer should be locked when accessing
2128 +*----------------------------------------------------------------------*/
2129 +static void toe_gmac_handle_default_rxq(struct net_device *dev)
2130 +{
2131 + struct gmac_private *gmac = netdev_priv(dev);
2132 + struct toe_private *toe = dev->ml_priv;
2133 + GMAC_RXDESC_T *curr_desc;
2134 + struct sk_buff *skb;
2135 + DMA_RWPTR_T rwptr;
2136 + unsigned int pkt_size;
2137 + int max_cnt;
2138 + unsigned int desc_count;
2139 + unsigned int chksum_status, rx_status;
2140 + struct net_device_stats *isPtr = &dev->stats;
2141 +
2142 + rwptr.bits32 = __raw_readl(&gmac->default_qhdr->word1);
2143 + max_cnt = DEFAULT_RXQ_MAX_CNT;
2144 + while ((--max_cnt) && rwptr.bits.rptr != rwptr.bits.wptr) {
2145 + curr_desc = (GMAC_RXDESC_T *)gmac->default_desc_base + rwptr.bits.rptr;
2146 + dma_sync_single_range_for_device(toe->dev,
2147 + gmac->default_desc_base_dma,
2148 + rwptr.bits.rptr * sizeof(GMAC_RXDESC_T),
2149 + sizeof(GMAC_RXDESC_T),
2150 + DMA_FROM_DEVICE);
2151 + rx_status = curr_desc->word0.bits.status;
2152 + chksum_status = curr_desc->word0.bits.chksum_status;
2153 + pkt_size = curr_desc->word1.bits.byte_count; /* total byte count in a frame */
2154 + desc_count = curr_desc->word0.bits.desc_count; /* get descriptor count per frame */
2155 + skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
2156 +
2157 + if ((curr_desc->word0.bits32 & (GMAC_RXDESC_0_T_derr | GMAC_RXDESC_0_T_perr))
2158 + || (pkt_size < 60) || (chksum_status & 0x4) || rx_status) {
2159 + if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_derr)
2160 + dev_err(&dev->dev, "%s::derr\n", __func__);
2161 + if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_perr)
2162 + dev_err(&dev->dev, "%s::perr\n", __func__);
2163 + if (rx_status && (rx_status == 4 || rx_status == 7))
2164 + isPtr->rx_crc_errors++;
2165 +
2166 + dev_kfree_skb_irq(skb);
2167 + goto bad_frame;
2168 + }
2169 +
2170 + if (curr_desc->word0.bits.drop)
2171 + dev_warn(&dev->dev, "%s::Drop\n", __func__);
2172 +
2173 + /* get frame information from the first descriptor of the frame */
2174 + skb_reserve(skb, RX_INSERT_BYTES); /* 16 byte align the IP fields. */
2175 + skb_put(skb, pkt_size);
2176 + skb->dev = dev;
2177 + skb->protocol = eth_type_trans(skb, dev);
2178 + if (chksum_status == RX_CHKSUM_IP_UDP_TCP_OK || chksum_status == RX_CHKSUM_IP_OK_ONLY)
2179 + skb->ip_summed = CHECKSUM_UNNECESSARY;
2180 +
2181 + netif_rx(skb); /* socket rx */
2182 + dev->last_rx = jiffies;
2183 +
2184 + isPtr->rx_bytes += pkt_size;
2185 +
2186 +bad_frame:
2187 + /* advance one for Rx default Q 0/1 */
2188 + rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, TOE_DEFAULT_Q_DESC_NUM);
2189 + SET_RPTR(&gmac->default_qhdr->word1, rwptr.bits.rptr);
2190 + }
2191 +
2192 + schedule_work(&toe->freq_work);
2193 +}
2194 +
2195 +static irqreturn_t toe_gmac_interrupt(int irq, void *dev_instance)
2196 +{
2197 + struct net_device *dev = dev_instance;
2198 + struct gmac_private *gmac = netdev_priv(dev);
2199 + struct toe_private *toe = dev->ml_priv;
2200 + unsigned int status0;
2201 + unsigned int status1;
2202 + unsigned int status2;
2203 + unsigned int status3;
2204 + unsigned int status4;
2205 + int handled = 0;
2206 +
2207 + /* read Interrupt status */
2208 + status0 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_0_REG);
2209 + status1 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_1_REG);
2210 + status2 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_2_REG);
2211 + status3 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_3_REG);
2212 + status4 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_4_REG);
2213 +
2214 + /* clear interrupts */
2215 + if (status0)
2216 + __raw_writel(status0, toe->global_base + GLOBAL_INTERRUPT_STATUS_0_REG);
2217 + if (status1)
2218 + __raw_writel(status1, toe->global_base + GLOBAL_INTERRUPT_STATUS_1_REG);
2219 + if (status2)
2220 + __raw_writel(status2, toe->global_base + GLOBAL_INTERRUPT_STATUS_2_REG);
2221 + if (status3)
2222 + __raw_writel(status3, toe->global_base + GLOBAL_INTERRUPT_STATUS_3_REG);
2223 + if (status4)
2224 + __raw_writel(status4, toe->global_base + GLOBAL_INTERRUPT_STATUS_4_REG);
2225 +
2226 + /* handle freeq interrupt first */
2227 + if (status4 & gmac->intr4_enabled) {
2228 + if ((status4 & SWFQ_EMPTY_INT_BIT) && (gmac->intr4_enabled & SWFQ_EMPTY_INT_BIT)) {
2229 + toe_gmac_fill_free_q(toe);
2230 + handled = 1;
2231 + }
2232 + }
2233 +
2234 + /* Interrupt Status 1 */
2235 + if (status1 & gmac->intr1_enabled) {
2236 + /*
2237 + * Handle GMAC 0/1 HW Tx queue 0-3 EOF events
2238 + * Only count
2239 + * TOE, Classification, and default queues interrupts are handled by ISR
2240 + * because they should pass packets to upper layer
2241 + */
2242 + if (gmac->port_id == 0) {
2243 + if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (gmac->intr1_enabled & DEFAULT_Q0_INT_BIT)) {
2244 + toe_gmac_handle_default_rxq(dev);
2245 + handled = 1;
2246 + }
2247 + } else if (gmac->port_id == 1) {
2248 + if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (gmac->intr1_enabled & DEFAULT_Q1_INT_BIT)) {
2249 + toe_gmac_handle_default_rxq(dev);
2250 + handled = 1;
2251 + }
2252 + }
2253 + }
2254 +
2255 + /* Interrupt Status 0 */
2256 + if (status0 & gmac->intr0_enabled) {
2257 +#ifndef GMAX_TX_INTR_DISABLED
2258 + if (gmac->port_id == 1 && netif_running(dev) &&
2259 + (((status0 & GMAC1_SWTQ10_FIN_INT_BIT) && (gmac->intr0_enabled & GMAC1_SWTQ10_FIN_INT_BIT))
2260 + ||
2261 + ((status0 & GMAC1_SWTQ10_EOF_INT_BIT) && (gmac->intr0_enabled & GMAC1_SWTQ10_EOF_INT_BIT)))) {
2262 + toe_gmac_tx_complete(dev, 0);
2263 + handled = 1;
2264 + }
2265 +
2266 + if (gmac->port_id == 0 && netif_running(dev) &&
2267 + (((status0 & GMAC0_SWTQ00_FIN_INT_BIT) && (gmac->intr0_enabled & GMAC0_SWTQ00_FIN_INT_BIT))
2268 + ||
2269 + ((status0 & GMAC0_SWTQ00_EOF_INT_BIT) && (gmac->intr0_enabled & GMAC0_SWTQ00_EOF_INT_BIT)))) {
2270 + toe_gmac_tx_complete(dev, 0);
2271 + handled = 1;
2272 + }
2273 +#endif
2274 + }
2275 +
2276 + return IRQ_RETVAL(handled);
2277 +}
2278 +
2279 +static int gmac_open(struct net_device *dev)
2280 +{
2281 + struct gmac_private *gmac = netdev_priv(dev);
2282 + int retval;
2283 +
2284 + /* hook ISR */
2285 + retval = request_irq(dev->irq, toe_gmac_interrupt, 0, dev->name, dev);
2286 + if (retval)
2287 + return retval;
2288 +
2289 + toe_init_gmac(dev);
2290 +
2291 + netif_carrier_off(dev);
2292 + phy_start(gmac->phydev);
2293 +
2294 + netif_start_queue(dev);
2295 +
2296 + return 0;
2297 +}
2298 +
2299 +static int gmac_close(struct net_device *dev)
2300 +{
2301 + struct gmac_private *gmac = netdev_priv(dev);
2302 +
2303 + netif_stop_queue(dev);
2304 + mdelay(20);
2305 +
2306 + if (gmac->phydev)
2307 + phy_stop(gmac->phydev);
2308 +
2309 + /* stop tx/rx packet */
2310 + toe_gmac_disable_tx_rx(dev);
2311 + mdelay(20);
2312 +
2313 + /* stop the chip's Tx and Rx DMA processes */
2314 + toe_gmac_hw_stop(gmac);
2315 +
2316 + disable_irq(dev->irq);
2317 + free_irq(dev->irq, dev);
2318 +
2319 + return 0;
2320 +}
2321 +
2322 +static void gmac_get_phy_status(struct net_device *dev)
2323 +{
2324 + struct gmac_private *gmac = netdev_priv(dev);
2325 + GMAC_CONFIG0_T config0;
2326 + GMAC_STATUS_T status, old_status;
2327 + struct phy_device *phydev = gmac->phydev;
2328 +
2329 + old_status.bits32 = status.bits32 = __raw_readl(dev->base_addr + GMAC_STATUS);
2330 +
2331 + status.bits.link = phydev->link;
2332 + status.bits.duplex = phydev->duplex;
2333 +
2334 + switch (phydev->speed) {
2335 + case 1000:
2336 + status.bits.speed = GMAC_SPEED_1000;
2337 + if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
2338 + status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
2339 + break;
2340 + case 100:
2341 + status.bits.speed = GMAC_SPEED_100;
2342 + if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
2343 + status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
2344 + break;
2345 + case 10:
2346 + status.bits.speed = GMAC_SPEED_10;
2347 + if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
2348 + status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
2349 + break;
2350 + default:
2351 + dev_warn(&dev->dev, "Not supported PHY speed (%d)\n", phydev->speed);
2352 + }
2353 +
2354 + if (phydev->pause) {
2355 + if (gmac->flow_control_enable == 0) {
2356 + config0.bits32 = __raw_readl(dev->base_addr + GMAC_CONFIG0);
2357 + config0.bits.tx_fc_en = 1; /* enable tx flow control */
2358 + config0.bits.rx_fc_en = 1; /* enable rx flow control */
2359 + __raw_writel(config0.bits32, dev->base_addr + GMAC_CONFIG0);
2360 + dev_info(&dev->dev, "MII flow control enabled\n");
2361 + }
2362 + gmac->flow_control_enable = 1;
2363 + } else {
2364 + if (gmac->flow_control_enable == 1) {
2365 + config0.bits32 = __raw_readl(dev->base_addr + GMAC_CONFIG0);
2366 + config0.bits.tx_fc_en = 0; /* disable tx flow control */
2367 + config0.bits.rx_fc_en = 0; /* disable rx flow control */
2368 + __raw_writel(config0.bits32, dev->base_addr + GMAC_CONFIG0);
2369 + dev_info(&dev->dev, "MII flow control disabled\n");
2370 + }
2371 + gmac->flow_control_enable = 0;
2372 + }
2373 +
2374 + if (old_status.bits32 != status.bits32) {
2375 + toe_gmac_disable_tx_rx(dev);
2376 + phy_print_status(phydev);
2377 + mdelay(10); /* let GMAC consume packet */
2378 + __raw_writel(status.bits32, dev->base_addr + GMAC_STATUS);
2379 + if (status.bits.link)
2380 + toe_gmac_enable_tx_rx(dev);
2381 + }
2382 +}
2383 +
2384 +static void gmac_set_rx_mode(struct net_device *dev)
2385 +{
2386 + GMAC_RX_FLTR_T filter;
2387 + unsigned int mc_filter[2]; /* Multicast hash filter */
2388 + int bit_nr;
2389 + unsigned int i;
2390 +
2391 + filter.bits32 = 0;
2392 + filter.bits.error = 0;
2393 + if (dev->flags & IFF_PROMISC) {
2394 + filter.bits.error = 1;
2395 + filter.bits.promiscuous = 1;
2396 + filter.bits.broadcast = 1;
2397 + filter.bits.multicast = 1;
2398 + filter.bits.unicast = 1;
2399 + mc_filter[1] = mc_filter[0] = 0xffffffff;
2400 + } else if (dev->flags & IFF_ALLMULTI) {
2401 + filter.bits.broadcast = 1;
2402 + filter.bits.multicast = 1;
2403 + filter.bits.unicast = 1;
2404 + mc_filter[1] = mc_filter[0] = 0xffffffff;
2405 + } else {
2406 + struct dev_mc_list *mclist;
2407 +
2408 + filter.bits.broadcast = 1;
2409 + filter.bits.multicast = 1;
2410 + filter.bits.unicast = 1;
2411 + mc_filter[1] = mc_filter[0] = 0;
2412 + for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; i++, mclist = mclist->next) {
2413 + bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3f;
2414 + if (bit_nr <= 32)
2415 + mc_filter[0] = mc_filter[0] | (1 << bit_nr);
2416 + else
2417 + mc_filter[1] = mc_filter[1] | (1 << (bit_nr - 32));
2418 + }
2419 + }
2420 + __raw_writel(filter.bits32, dev->base_addr + GMAC_RX_FLTR);
2421 + __raw_writel(mc_filter[0], dev->base_addr + GMAC_MCAST_FIL0);
2422 + __raw_writel(mc_filter[1], dev->base_addr + GMAC_MCAST_FIL1);
2423 +}
2424 +
2425 +static void gmac_tx_timeout(struct net_device *dev)
2426 +{
2427 + if (!netif_queue_stopped(dev))
2428 + netif_wake_queue(dev);
2429 +
2430 + dev_warn(&dev->dev, "TX timeout\n");
2431 +}
2432 +
2433 +const static struct net_device_ops gemini_gmac_ops = {
2434 + .ndo_open = gmac_open,
2435 + .ndo_stop = gmac_close,
2436 + .ndo_start_xmit = gmac_start_xmit,
2437 + .ndo_get_stats = gmac_get_stats,
2438 + .ndo_set_multicast_list = gmac_set_rx_mode,
2439 + .ndo_set_mac_address = gmac_set_mac_address,
2440 + .ndo_tx_timeout = gmac_tx_timeout,
2441 +};
2442 +
2443 +static void __init mac_init_drv(struct toe_private *toe)
2444 +{
2445 + QUEUE_THRESHOLD_T threshold;
2446 + DMA_SKB_SIZE_T skb_size;
2447 +
2448 + /* clear non TOE Queue Header Area */
2449 + memset(toe->global_base + TOE_NONTOE_QUE_HDR_BASE, 0,
2450 + NONTOE_Q_HDR_AREA_END - TOE_NONTOE_QUE_HDR_BASE);
2451 +
2452 + /* clear TOE Queue Header Area */
2453 + memset(toe->global_base + TOE_TOE_QUE_HDR_BASE, 0,
2454 + TOE_Q_HDR_AREA_END - TOE_TOE_QUE_HDR_BASE);
2455 +
2456 + /* Write GLOBAL_QUEUE_THRESHOLD_REG */
2457 + threshold.bits32 = 0;
2458 + threshold.bits.swfq_empty = (TOE_SW_FREEQ_DESC_NUM > 256) ? 255 :
2459 + TOE_SW_FREEQ_DESC_NUM / 2;
2460 + threshold.bits.hwfq_empty = (TOE_HW_FREEQ_DESC_NUM > 256) ? 256 / 4 :
2461 + TOE_HW_FREEQ_DESC_NUM / 4;
2462 + threshold.bits.toe_class = (TOE_TOE_DESC_NUM > 256) ? 256 / 4 :
2463 + TOE_TOE_DESC_NUM / 4;
2464 + threshold.bits.intrq = (TOE_INTR_DESC_NUM > 256) ? 256 / 4 :
2465 + TOE_INTR_DESC_NUM / 4;
2466 + __raw_writel(threshold.bits32, toe->global_base + GLOBAL_QUEUE_THRESHOLD_REG);
2467 +
2468 + /* Init skb size */
2469 + skb_size.bits.hw_skb_size = HW_RX_BUF_SIZE;
2470 + skb_size.bits.sw_skb_size = SW_RX_BUF_SIZE;
2471 + __raw_writel(skb_size.bits32, toe->global_base + GLOBAL_DMA_SKB_SIZE_REG);
2472 +
2473 + toe_init_free_queue(toe);
2474 + toe_init_interrupt_config(toe);
2475 +}
2476 +
2477 +static int __init gmac_init_eth(struct platform_device *pdev, unsigned int num)
2478 +{
2479 + struct gmac_private *gmac;
2480 + struct net_device *dev;
2481 + struct toe_private *toe = platform_get_drvdata(pdev);
2482 + struct gemini_gmac_platform_data *pdata = pdev->dev.platform_data;
2483 +
2484 + if (!pdata->bus_id[num])
2485 + return 0;
2486 +
2487 + dev = alloc_etherdev(sizeof(*gmac));
2488 + if (dev == NULL) {
2489 + dev_err(&pdev->dev, "Can't allocate ethernet device #%d\n", num);
2490 + return -ENOMEM;
2491 + }
2492 +
2493 + gmac = netdev_priv(dev);
2494 + dev->ml_priv = toe;
2495 + toe->net_dev[num] = dev;
2496 +
2497 + gmac->dma_base_addr = toe->global_base + TOE_GMAC_DMA_BASE(num);
2498 + gmac->port_id = num;
2499 +
2500 + dev->base_addr = toe->global_base + TOE_GMAC_BASE(num);
2501 + dev->irq = platform_get_irq(pdev, num);
2502 + dev->netdev_ops = &gemini_gmac_ops;
2503 + dev->watchdog_timeo = GMAC_DEV_TX_TIMEOUT;
2504 + dev->tx_queue_len = TOE_GMAC_SWTXQ_DESC_NUM;
2505 +
2506 +#ifdef DO_HW_CHKSUM
2507 + dev->features = NETIF_F_SG | NETIF_F_HW_CSUM;
2508 +#ifdef ENABLE_TSO
2509 + dev->features |= NETIF_F_TSO;
2510 +#endif
2511 +#endif
2512 +
2513 + toe_init_swtx_queue(dev);
2514 + toe_init_default_queue(dev);
2515 +
2516 + gmac_get_mac_address(dev);
2517 +
2518 + /* TODO: Do we need this? */
2519 + __raw_writel(0x55aa55aa, dev->base_addr + GMAC_STA_ADD2);
2520 +
2521 + if (register_netdev(dev))
2522 + return -1;
2523 +
2524 + gmac->phydev = phy_connect(dev, pdata->bus_id[num], &gmac_get_phy_status, 0,
2525 + pdata->interface[num]);
2526 + if (IS_ERR(gmac->phydev))
2527 + return PTR_ERR(gmac->phydev);
2528 +
2529 + gmac->phydev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause;
2530 + gmac->phydev->advertising = gmac->phydev->supported;
2531 +
2532 + return 0;
2533 +}
2534 +
2535 +static int __init gmac_probe(struct platform_device *pdev)
2536 +{
2537 + struct resource *res;
2538 + struct toe_private *toe;
2539 + int retval;
2540 +
2541 + if (!pdev->dev.platform_data)
2542 + return -EINVAL;
2543 +
2544 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2545 + if (!res) {
2546 + dev_err(&pdev->dev, "can't get device resources\n");
2547 + return -ENODEV;
2548 + }
2549 +
2550 + toe = kzalloc(sizeof(struct toe_private), GFP_KERNEL);
2551 + if (!toe)
2552 + return -ENOMEM;
2553 +
2554 + toe->dev = &pdev->dev;
2555 +
2556 + toe->global_base = ioremap(res->start, resource_size(res));
2557 + if (!toe->global_base) {
2558 + dev_err(toe->dev, "ioremap failed\n");
2559 + retval = -EIO;
2560 + goto err_data;
2561 + }
2562 +
2563 + platform_set_drvdata(pdev, toe);
2564 +
2565 + mac_init_drv(toe);
2566 +
2567 + INIT_WORK(&toe->freq_work, fill_free_q_worker);
2568 + spin_lock_init(&toe->freeq_lock);
2569 +
2570 + retval = gmac_init_eth(pdev, GMAC_PORT0);
2571 + if (retval)
2572 + goto err_unmap;
2573 + retval = gmac_init_eth(pdev, GMAC_PORT1);
2574 + if (retval)
2575 + goto err_unmap;
2576 +
2577 + dev_info(&pdev->dev, SL351x_DRIVER_NAME "\n");
2578 +
2579 + return 0;
2580 +
2581 +err_unmap:
2582 + iounmap(toe->global_base);
2583 +err_data:
2584 + kfree(toe);
2585 + return retval;
2586 +}
2587 +
2588 +static int __exit gmac_remove(struct platform_device *pdev)
2589 +{
2590 + struct toe_private *toe = platform_get_drvdata(pdev);
2591 + int i;
2592 +
2593 + for (i = 0; i < 2; i++)
2594 + if (toe->net_dev[i]) {
2595 + unregister_netdev(toe->net_dev[i]);
2596 + kfree(toe->net_dev[i]);
2597 + }
2598 +
2599 + iounmap(toe->global_base);
2600 +
2601 + kfree(toe);
2602 +
2603 + return 0;
2604 +}
2605 +
2606 +static struct platform_driver gemini_gmac_driver = {
2607 + .probe = gmac_probe,
2608 + .remove = __exit_p(gmac_remove),
2609 +
2610 + .driver = {
2611 + .name = "gemini-gmac",
2612 + .owner = THIS_MODULE,
2613 + },
2614 +};
2615 +
2616 +static int __init gemini_gmac_init(void)
2617 +{
2618 + return platform_driver_register(&gemini_gmac_driver);
2619 +}
2620 +
2621 +static void __exit gemini_gmac_exit(void)
2622 +{
2623 + platform_driver_unregister(&gemini_gmac_driver);
2624 +}
2625 +
2626 +module_init(gemini_gmac_init);
2627 +module_exit(gemini_gmac_exit);
2628 +
2629 +MODULE_AUTHOR("Paulius Zaleckas");
2630 +MODULE_DESCRIPTION("Ethernet device driver for Gemini SoC");
2631 +MODULE_LICENSE("GPL");
2632 +MODULE_ALIAS("platform:gemini-gmac");
2633 --- /dev/null
2634 +++ b/drivers/net/gemini_negmac/gm_gmac.h
2635 @@ -0,0 +1,1488 @@
2636 +/*
2637 + * Register definitions for Gemini Ethernet device driver.
2638 + *
2639 + * Copyright (C) 2006, Storlink, Corp.
2640 + * Copyright (C) 2008-2009, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
2641 + *
2642 + * This program is free software; you can redistribute it and/or modify
2643 + * it under the terms of the GNU General Public License as published by
2644 + * the Free Software Foundation; either version 2 of the License, or
2645 + * (at your option) any later version.
2646 + */
2647 +#ifndef _GMAC_SL351x_H
2648 +#define _GMAC_SL351x_H
2649 +#include <linux/skbuff.h>
2650 +
2651 +#define _PACKED_ __attribute__ ((aligned(1), packed))
2652 +
2653 +#ifndef BIT
2654 +#define BIT(x) (1 << (x))
2655 +#endif
2656 +
2657 +#define REG32(addr) (*(volatile unsigned long * const)(addr))
2658 +
2659 +/* Define frame size */
2660 +#define GMAC_MAX_ETH_FRAME_SIZE 1514
2661 +#define GMAC_TX_BUF_SIZE ((GMAC_MAX_ETH_FRAME_SIZE + 31) & (~31))
2662 +
2663 +#define SW_RX_BUF_SIZE 1536
2664 +#define HW_RX_BUF_SIZE 1536
2665 +
2666 +#define GMAC_DEV_TX_TIMEOUT (10*HZ)
2667 +#define SKB_RESERVE_BYTES 16
2668 +
2669 +/*
2670 + * Base Registers
2671 + */
2672 +#define TOE_NONTOE_QUE_HDR_BASE 0x2000
2673 +#define TOE_TOE_QUE_HDR_BASE 0x3000
2674 +#define TOE_V_BIT_BASE 0x4000
2675 +#define TOE_A_BIT_BASE 0x6000
2676 +#define TOE_GMAC_DMA_BASE(x) (0x8000 + 0x4000 * (x))
2677 +#define TOE_GMAC_BASE(x) (0xA000 + 0x4000 * (x))
2678 +
2679 +/*
2680 + * Queue ID
2681 + */
2682 +#define TOE_SW_FREE_QID 0x00
2683 +#define TOE_HW_FREE_QID 0x01
2684 +#define TOE_GMAC0_SW_TXQ0_QID 0x02
2685 +#define TOE_GMAC0_SW_TXQ1_QID 0x03
2686 +#define TOE_GMAC0_SW_TXQ2_QID 0x04
2687 +#define TOE_GMAC0_SW_TXQ3_QID 0x05
2688 +#define TOE_GMAC0_SW_TXQ4_QID 0x06
2689 +#define TOE_GMAC0_SW_TXQ5_QID 0x07
2690 +#define TOE_GMAC0_HW_TXQ0_QID 0x08
2691 +#define TOE_GMAC0_HW_TXQ1_QID 0x09
2692 +#define TOE_GMAC0_HW_TXQ2_QID 0x0A
2693 +#define TOE_GMAC0_HW_TXQ3_QID 0x0B
2694 +#define TOE_GMAC1_SW_TXQ0_QID 0x12
2695 +#define TOE_GMAC1_SW_TXQ1_QID 0x13
2696 +#define TOE_GMAC1_SW_TXQ2_QID 0x14
2697 +#define TOE_GMAC1_SW_TXQ3_QID 0x15
2698 +#define TOE_GMAC1_SW_TXQ4_QID 0x16
2699 +#define TOE_GMAC1_SW_TXQ5_QID 0x17
2700 +#define TOE_GMAC1_HW_TXQ0_QID 0x18
2701 +#define TOE_GMAC1_HW_TXQ1_QID 0x19
2702 +#define TOE_GMAC1_HW_TXQ2_QID 0x1A
2703 +#define TOE_GMAC1_HW_TXQ3_QID 0x1B
2704 +#define TOE_GMAC0_DEFAULT_QID 0x20
2705 +#define TOE_GMAC1_DEFAULT_QID 0x21
2706 +#define TOE_CLASSIFICATION_QID(x) (0x22 + x) // 0x22 ~ 0x2F
2707 +#define TOE_TOE_QID(x) (0x40 + x) // 0x40 ~ 0x7F
2708 +
2709 +/*
2710 + * TOE DMA Queue Number should be 2^n, n = 6...12
2711 + * TOE DMA Queues are the following queue types:
2712 + * SW Free Queue, HW Free Queue,
2713 + * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
2714 + * They have same descriptor numbers.
2715 + * The base address and descriptor number are configured at
2716 + * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
2717 + */
2718 +#define TOE_SW_FREEQ_DESC_POWER 8
2719 +#define TOE_SW_FREEQ_DESC_NUM (1<<TOE_SW_FREEQ_DESC_POWER)
2720 +#define TOE_HW_FREEQ_DESC_POWER 8
2721 +#define TOE_HW_FREEQ_DESC_NUM (1<<TOE_HW_FREEQ_DESC_POWER)
2722 +#define TOE_GMAC_SWTXQ_DESC_POWER 8
2723 +#define TOE_GMAC_SWTXQ_DESC_NUM (1<<TOE_GMAC_SWTXQ_DESC_POWER)
2724 +#define TOE_GMAC_HWTXQ_DESC_POWER 8
2725 +#define TOE_GMAC_HWTXQ_DESC_NUM (1<<TOE_GMAC_HWTXQ_DESC_POWER)
2726 +#define TOE_DEFAULT_Q_DESC_POWER 8
2727 +#define TOE_DEFAULT_Q_DESC_NUM (1<<TOE_DEFAULT_Q_DESC_POWER)
2728 +#define TOE_TOE_DESC_POWER 8
2729 +#define TOE_TOE_DESC_NUM (1<<TOE_TOE_DESC_POWER)
2730 +#define TOE_CLASS_DESC_POWER 8
2731 +#define TOE_CLASS_DESC_NUM (1<<TOE_CLASS_DESC_POWER)
2732 +#define TOE_INTR_DESC_POWER 8
2733 +#define TOE_INTR_DESC_NUM (1<<TOE_INTR_DESC_POWER)
2734 +
2735 +#define TOE_TOE_QUEUE_MAX 64
2736 +#define TOE_TOE_QUEUE_NUM 64
2737 +#define TOE_CLASS_QUEUE_MAX 14
2738 +#define TOE_CLASS_QUEUE_NUM 14
2739 +#define TOE_INTR_QUEUE_MAX 4
2740 +#define TOE_INTR_QUEUE_NUM 4
2741 +#define TOE_SW_TXQ_MAX 6
2742 +#define TOE_SW_TXQ_NUM 1
2743 +#define TOE_HW_TXQ_MAX 4
2744 +#define TOE_HW_TXQ_NUM 4
2745 +
2746 +#define RWPTR_ADVANCE_ONE(x, max) ((x == (max -1)) ? 0 : x+1)
2747 +#define RWPTR_RECEDE_ONE(x, max) ((x == 0) ? (max -1) : x-1)
2748 +#define SET_WPTR(addr, data) (*(volatile u16 * const)((u32)(addr) + 2) = (u16)data)
2749 +#define SET_RPTR(addr, data) (*(volatile u16 * const)((u32)(addr)) = (u16)data)
2750 +
2751 +/*
2752 + * Global registers
2753 + * #define TOE_GLOBAL_BASE (TOE_BASE + 0x0000)
2754 + * Base 0x60000000
2755 + */
2756 +#define GLOBAL_TOE_VERSION_REG 0x0000
2757 +#define GLOBAL_SW_FREEQ_BASE_SIZE_REG 0x0004
2758 +#define GLOBAL_HW_FREEQ_BASE_SIZE_REG 0x0008
2759 +#define GLOBAL_DMA_SKB_SIZE_REG 0x0010
2760 +#define GLOBAL_SWFQ_RWPTR_REG 0x0014
2761 +#define GLOBAL_HWFQ_RWPTR_REG 0x0018
2762 +#define GLOBAL_INTERRUPT_STATUS_0_REG 0x0020
2763 +#define GLOBAL_INTERRUPT_ENABLE_0_REG 0x0024
2764 +#define GLOBAL_INTERRUPT_SELECT_0_REG 0x0028
2765 +#define GLOBAL_INTERRUPT_STATUS_1_REG 0x0030
2766 +#define GLOBAL_INTERRUPT_ENABLE_1_REG 0x0034
2767 +#define GLOBAL_INTERRUPT_SELECT_1_REG 0x0038
2768 +#define GLOBAL_INTERRUPT_STATUS_2_REG 0x0040
2769 +#define GLOBAL_INTERRUPT_ENABLE_2_REG 0x0044
2770 +#define GLOBAL_INTERRUPT_SELECT_2_REG 0x0048
2771 +#define GLOBAL_INTERRUPT_STATUS_3_REG 0x0050
2772 +#define GLOBAL_INTERRUPT_ENABLE_3_REG 0x0054
2773 +#define GLOBAL_INTERRUPT_SELECT_3_REG 0x0058
2774 +#define GLOBAL_INTERRUPT_STATUS_4_REG 0x0060
2775 +#define GLOBAL_INTERRUPT_ENABLE_4_REG 0x0064
2776 +#define GLOBAL_INTERRUPT_SELECT_4_REG 0x0068
2777 +#define GLOBAL_HASH_TABLE_BASE_REG 0x006C
2778 +#define GLOBAL_QUEUE_THRESHOLD_REG 0x0070
2779 +
2780 +/*
2781 + * GMAC 0/1 DMA/TOE register
2782 + * #define TOE_GMAC0_DMA_BASE (TOE_BASE + 0x8000)
2783 + * #define TOE_GMAC1_DMA_BASE (TOE_BASE + 0xC000)
2784 + * Base 0x60008000 or 0x6000C000
2785 + */
2786 +#define GMAC_DMA_CTRL_REG 0x0000
2787 +#define GMAC_TX_WEIGHTING_CTRL_0_REG 0x0004
2788 +#define GMAC_TX_WEIGHTING_CTRL_1_REG 0x0008
2789 +#define GMAC_SW_TX_QUEUE0_PTR_REG 0x000C
2790 +#define GMAC_SW_TX_QUEUE1_PTR_REG 0x0010
2791 +#define GMAC_SW_TX_QUEUE2_PTR_REG 0x0014
2792 +#define GMAC_SW_TX_QUEUE3_PTR_REG 0x0018
2793 +#define GMAC_SW_TX_QUEUE4_PTR_REG 0x001C
2794 +#define GMAC_SW_TX_QUEUE5_PTR_REG 0x0020
2795 +#define GMAC_HW_TX_QUEUE0_PTR_REG 0x0024
2796 +#define GMAC_HW_TX_QUEUE1_PTR_REG 0x0028
2797 +#define GMAC_HW_TX_QUEUE2_PTR_REG 0x002C
2798 +#define GMAC_HW_TX_QUEUE3_PTR_REG 0x0030
2799 +#define GMAC_DMA_TX_FIRST_DESC_REG 0x0038
2800 +#define GMAC_DMA_TX_CURR_DESC_REG 0x003C
2801 +#define GMAC_DMA_TX_DESC_WORD0_REG 0x0040
2802 +#define GMAC_DMA_TX_DESC_WORD1_REG 0x0044
2803 +#define GMAC_DMA_TX_DESC_WORD2_REG 0x0048
2804 +#define GMAC_DMA_TX_DESC_WORD3_REG 0x004C
2805 +#define GMAC_SW_TX_QUEUE_BASE_REG 0x0050
2806 +#define GMAC_HW_TX_QUEUE_BASE_REG 0x0054
2807 +#define GMAC_DMA_RX_FIRST_DESC_REG 0x0058
2808 +#define GMAC_DMA_RX_CURR_DESC_REG 0x005C
2809 +#define GMAC_DMA_RX_DESC_WORD0_REG 0x0060
2810 +#define GMAC_DMA_RX_DESC_WORD1_REG 0x0064
2811 +#define GMAC_DMA_RX_DESC_WORD2_REG 0x0068
2812 +#define GMAC_DMA_RX_DESC_WORD3_REG 0x006C
2813 +#define GMAC_HASH_ENGINE_REG0 0x0070
2814 +#define GMAC_HASH_ENGINE_REG1 0x0074
2815 +/* matching rule 0 Control register 0 */
2816 +#define GMAC_MR0CR0 0x0078
2817 +#define GMAC_MR0CR1 0x007C
2818 +#define GMAC_MR0CR2 0x0080
2819 +#define GMAC_MR1CR0 0x0084
2820 +#define GMAC_MR1CR1 0x0088
2821 +#define GMAC_MR1CR2 0x008C
2822 +#define GMAC_MR2CR0 0x0090
2823 +#define GMAC_MR2CR1 0x0094
2824 +#define GMAC_MR2CR2 0x0098
2825 +#define GMAC_MR3CR0 0x009C
2826 +#define GMAC_MR3CR1 0x00A0
2827 +#define GMAC_MR3CR2 0x00A4
2828 +/* Support Protocol Regsister 0 */
2829 +#define GMAC_SPR0 0x00A8
2830 +#define GMAC_SPR1 0x00AC
2831 +#define GMAC_SPR2 0x00B0
2832 +#define GMAC_SPR3 0x00B4
2833 +#define GMAC_SPR4 0x00B8
2834 +#define GMAC_SPR5 0x00BC
2835 +#define GMAC_SPR6 0x00C0
2836 +#define GMAC_SPR7 0x00C4
2837 +/* GMAC Hash/Rx/Tx AHB Weighting register */
2838 +#define GMAC_AHB_WEIGHT_REG 0x00C8
2839 +
2840 +/*
2841 + * TOE GMAC 0/1 register
2842 + * #define TOE_GMAC0_BASE (TOE_BASE + 0xA000)
2843 + * #define TOE_GMAC1_BASE (TOE_BASE + 0xE000)
2844 + * Base 0x6000A000 or 0x6000E000
2845 + */
2846 +enum GMAC_REGISTER {
2847 + GMAC_STA_ADD0 = 0x0000,
2848 + GMAC_STA_ADD1 = 0x0004,
2849 + GMAC_STA_ADD2 = 0x0008,
2850 + GMAC_RX_FLTR = 0x000c,
2851 + GMAC_MCAST_FIL0 = 0x0010,
2852 + GMAC_MCAST_FIL1 = 0x0014,
2853 + GMAC_CONFIG0 = 0x0018,
2854 + GMAC_CONFIG1 = 0x001c,
2855 + GMAC_CONFIG2 = 0x0020,
2856 + GMAC_CONFIG3 = 0x0024,
2857 + GMAC_RESERVED = 0x0028,
2858 + GMAC_STATUS = 0x002c,
2859 + GMAC_IN_DISCARDS= 0x0030,
2860 + GMAC_IN_ERRORS = 0x0034,
2861 + GMAC_IN_MCAST = 0x0038,
2862 + GMAC_IN_BCAST = 0x003c,
2863 + GMAC_IN_MAC1 = 0x0040, /* for STA 1 MAC Address */
2864 + GMAC_IN_MAC2 = 0x0044 /* for STA 2 MAC Address */
2865 +};
2866 +
2867 +/*
2868 + * DMA Queues description Ring Base Address/Size Register (offset 0x0004)
2869 + */
2870 +typedef union {
2871 + unsigned int bits32;
2872 + unsigned int base_size;
2873 +} DMA_Q_BASE_SIZE_T;
2874 +#define DMA_Q_BASE_MASK (~0x0f)
2875 +
2876 +/*
2877 + * DMA SKB Buffer register (offset 0x0008)
2878 + */
2879 +typedef union {
2880 + unsigned int bits32;
2881 + struct bit_0008 {
2882 + unsigned int sw_skb_size : 16; /* SW Free poll SKB Size */
2883 + unsigned int hw_skb_size : 16; /* HW Free poll SKB Size */
2884 + } bits;
2885 +} DMA_SKB_SIZE_T;
2886 +
2887 +/*
2888 + * DMA SW Free Queue Read/Write Pointer Register (offset 0x000C)
2889 + */
2890 +typedef union {
2891 + unsigned int bits32;
2892 + struct bit_000c {
2893 + unsigned int rptr : 16; /* Read Ptr, RO */
2894 + unsigned int wptr : 16; /* Write Ptr, RW */
2895 + } bits;
2896 +} DMA_RWPTR_T;
2897 +
2898 +/*
2899 + * DMA HW Free Queue Read/Write Pointer Register (offset 0x0010)
2900 + * see DMA_RWPTR_T structure
2901 + */
2902 +
2903 +/*
2904 + * Interrupt Status Register 0 (offset 0x0020)
2905 + * Interrupt Mask Register 0 (offset 0x0024)
2906 + * Interrupt Select Register 0 (offset 0x0028)
2907 + */
2908 +typedef union {
2909 + unsigned int bits32;
2910 + struct bit_0020 {
2911 + /* GMAC0 SW Tx Queue 0 EOF Interrupt */
2912 + unsigned int swtq00_eof : 1;
2913 + unsigned int swtq01_eof : 1;
2914 + unsigned int swtq02_eof : 1;
2915 + unsigned int swtq03_eof : 1;
2916 + unsigned int swtq04_eof : 1;
2917 + unsigned int swtq05_eof : 1;
2918 + /* GMAC1 SW Tx Queue 0 EOF Interrupt */
2919 + unsigned int swtq10_eof : 1;
2920 + unsigned int swtq11_eof : 1;
2921 + unsigned int swtq12_eof : 1;
2922 + unsigned int swtq13_eof : 1;
2923 + unsigned int swtq14_eof : 1;
2924 + unsigned int swtq15_eof : 1;
2925 + /* GMAC0 SW Tx Queue 0 Finish Interrupt */
2926 + unsigned int swtq00_fin : 1;
2927 + unsigned int swtq01_fin : 1;
2928 + unsigned int swtq02_fin : 1;
2929 + unsigned int swtq03_fin : 1;
2930 + unsigned int swtq04_fin : 1;
2931 + unsigned int swtq05_fin : 1;
2932 + /* GMAC1 SW Tx Queue 0 Finish Interrupt */
2933 + unsigned int swtq10_fin : 1;
2934 + unsigned int swtq11_fin : 1;
2935 + unsigned int swtq12_fin : 1;
2936 + unsigned int swtq13_fin : 1;
2937 + unsigned int swtq14_fin : 1;
2938 + unsigned int swtq15_fin : 1;
2939 + /* GMAC0 Rx Descriptor Protocol Error */
2940 + unsigned int rxPerr0 : 1;
2941 + /* GMAC0 AHB Bus Error while Rx */
2942 + unsigned int rxDerr0 : 1;
2943 + /* GMAC1 Rx Descriptor Protocol Error */
2944 + unsigned int rxPerr1 : 1;
2945 + /* GMAC1 AHB Bus Error while Rx */
2946 + unsigned int rxDerr1 : 1;
2947 + /* GMAC0 Tx Descriptor Protocol Error */
2948 + unsigned int txPerr0 : 1;
2949 + /* GMAC0 AHB Bus Error while Tx */
2950 + unsigned int txDerr0 : 1;
2951 + /* GMAC1 Tx Descriptor Protocol Error */
2952 + unsigned int txPerr1 : 1;
2953 + /* GMAC1 AHB Bus Error while Tx */
2954 + unsigned int txDerr1 : 1;
2955 + } bits;
2956 +} INTR_REG0_T;
2957 +
2958 +#define GMAC1_TXDERR_INT_BIT BIT(31)
2959 +#define GMAC1_TXPERR_INT_BIT BIT(30)
2960 +#define GMAC0_TXDERR_INT_BIT BIT(29)
2961 +#define GMAC0_TXPERR_INT_BIT BIT(28)
2962 +#define GMAC1_RXDERR_INT_BIT BIT(27)
2963 +#define GMAC1_RXPERR_INT_BIT BIT(26)
2964 +#define GMAC0_RXDERR_INT_BIT BIT(25)
2965 +#define GMAC0_RXPERR_INT_BIT BIT(24)
2966 +#define GMAC1_SWTQ15_FIN_INT_BIT BIT(23)
2967 +#define GMAC1_SWTQ14_FIN_INT_BIT BIT(22)
2968 +#define GMAC1_SWTQ13_FIN_INT_BIT BIT(21)
2969 +#define GMAC1_SWTQ12_FIN_INT_BIT BIT(20)
2970 +#define GMAC1_SWTQ11_FIN_INT_BIT BIT(19)
2971 +#define GMAC1_SWTQ10_FIN_INT_BIT BIT(18)
2972 +#define GMAC0_SWTQ05_FIN_INT_BIT BIT(17)
2973 +#define GMAC0_SWTQ04_FIN_INT_BIT BIT(16)
2974 +#define GMAC0_SWTQ03_FIN_INT_BIT BIT(15)
2975 +#define GMAC0_SWTQ02_FIN_INT_BIT BIT(14)
2976 +#define GMAC0_SWTQ01_FIN_INT_BIT BIT(13)
2977 +#define GMAC0_SWTQ00_FIN_INT_BIT BIT(12)
2978 +#define GMAC1_SWTQ15_EOF_INT_BIT BIT(11)
2979 +#define GMAC1_SWTQ14_EOF_INT_BIT BIT(10)
2980 +#define GMAC1_SWTQ13_EOF_INT_BIT BIT(9)
2981 +#define GMAC1_SWTQ12_EOF_INT_BIT BIT(8)
2982 +#define GMAC1_SWTQ11_EOF_INT_BIT BIT(7)
2983 +#define GMAC1_SWTQ10_EOF_INT_BIT BIT(6)
2984 +#define GMAC0_SWTQ05_EOF_INT_BIT BIT(5)
2985 +#define GMAC0_SWTQ04_EOF_INT_BIT BIT(4)
2986 +#define GMAC0_SWTQ03_EOF_INT_BIT BIT(3)
2987 +#define GMAC0_SWTQ02_EOF_INT_BIT BIT(2)
2988 +#define GMAC0_SWTQ01_EOF_INT_BIT BIT(1)
2989 +#define GMAC0_SWTQ00_EOF_INT_BIT BIT(0)
2990 +
2991 +/*
2992 + * Interrupt Status Register 1 (offset 0x0030)
2993 + * Interrupt Mask Register 1 (offset 0x0034)
2994 + * Interrupt Select Register 1 (offset 0x0038)
2995 + */
2996 +typedef union {
2997 + unsigned int bits32;
2998 + struct bit_0030 {
2999 + unsigned int default_q0_eof : 1; /* Default Queue 0 EOF Interrupt */
3000 + unsigned int default_q1_eof : 1; /* Default Queue 1 EOF Interrupt */
3001 + unsigned int class_rx : 14; /* Classification Queue Rx Interrupt */
3002 + unsigned int hwtq00_eof : 1; /* GMAC0 HW Tx Queue0 EOF Interrupt */
3003 + unsigned int hwtq01_eof : 1; /* GMAC0 HW Tx Queue1 EOF Interrupt */
3004 + unsigned int hwtq02_eof : 1; /* GMAC0 HW Tx Queue2 EOF Interrupt */
3005 + unsigned int hwtq03_eof : 1; /* GMAC0 HW Tx Queue3 EOF Interrupt */
3006 + unsigned int hwtq10_eof : 1; /* GMAC1 HW Tx Queue0 EOF Interrupt */
3007 + unsigned int hwtq11_eof : 1; /* GMAC1 HW Tx Queue1 EOF Interrupt */
3008 + unsigned int hwtq12_eof : 1; /* GMAC1 HW Tx Queue2 EOF Interrupt */
3009 + unsigned int hwtq13_eof : 1; /* GMAC1 HW Tx Queue3 EOF Interrupt */
3010 + unsigned int toe_iq0_intr : 1; /* TOE Interrupt Queue 0 with Interrupts */
3011 + unsigned int toe_iq1_intr : 1; /* TOE Interrupt Queue 1 with Interrupts */
3012 + unsigned int toe_iq2_intr : 1; /* TOE Interrupt Queue 2 with Interrupts */
3013 + unsigned int toe_iq3_intr : 1; /* TOE Interrupt Queue 3 with Interrupts */
3014 + unsigned int toe_iq0_full : 1; /* TOE Interrupt Queue 0 Full Interrupt */
3015 + unsigned int toe_iq1_full : 1; /* TOE Interrupt Queue 1 Full Interrupt */
3016 + unsigned int toe_iq2_full : 1; /* TOE Interrupt Queue 2 Full Interrupt */
3017 + unsigned int toe_iq3_full : 1; /* TOE Interrupt Queue 3 Full Interrupt */
3018 + } bits;
3019 +} INTR_REG1_T;
3020 +
3021 +#define TOE_IQ3_FULL_INT_BIT BIT(31)
3022 +#define TOE_IQ2_FULL_INT_BIT BIT(30)
3023 +#define TOE_IQ1_FULL_INT_BIT BIT(29)
3024 +#define TOE_IQ0_FULL_INT_BIT BIT(28)
3025 +#define TOE_IQ3_INT_BIT BIT(27)
3026 +#define TOE_IQ2_INT_BIT BIT(26)
3027 +#define TOE_IQ1_INT_BIT BIT(25)
3028 +#define TOE_IQ0_INT_BIT BIT(24)
3029 +#define GMAC1_HWTQ13_EOF_INT_BIT BIT(23)
3030 +#define GMAC1_HWTQ12_EOF_INT_BIT BIT(22)
3031 +#define GMAC1_HWTQ11_EOF_INT_BIT BIT(21)
3032 +#define GMAC1_HWTQ10_EOF_INT_BIT BIT(20)
3033 +#define GMAC0_HWTQ03_EOF_INT_BIT BIT(19)
3034 +#define GMAC0_HWTQ02_EOF_INT_BIT BIT(18)
3035 +#define GMAC0_HWTQ01_EOF_INT_BIT BIT(17)
3036 +#define GMAC0_HWTQ00_EOF_INT_BIT BIT(16)
3037 +#define CLASS_RX_INT_BIT(x) BIT((x + 2))
3038 +#define DEFAULT_Q1_INT_BIT BIT(1)
3039 +#define DEFAULT_Q0_INT_BIT BIT(0)
3040 +
3041 +#define TOE_IQ_INT_BITS (TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \
3042 + TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT)
3043 +#define TOE_IQ_FULL_BITS (TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \
3044 + TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT)
3045 +#define TOE_IQ_ALL_BITS (TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS)
3046 +#define TOE_CLASS_RX_INT_BITS 0xfffc
3047 +
3048 +/*
3049 + * Interrupt Status Register 2 (offset 0x0040)
3050 + * Interrupt Mask Register 2 (offset 0x0044)
3051 + * Interrupt Select Register 2 (offset 0x0048)
3052 + */
3053 +typedef union {
3054 + unsigned int bits32;
3055 + struct bit_0040 {
3056 + unsigned int toe_q0_full : 1; // bit 0 TOE Queue 0 Full Interrupt
3057 + unsigned int toe_q1_full : 1; // bit 1 TOE Queue 1 Full Interrupt
3058 + unsigned int toe_q2_full : 1; // bit 2 TOE Queue 2 Full Interrupt
3059 + unsigned int toe_q3_full : 1; // bit 3 TOE Queue 3 Full Interrupt
3060 + unsigned int toe_q4_full : 1; // bit 4 TOE Queue 4 Full Interrupt
3061 + unsigned int toe_q5_full : 1; // bit 5 TOE Queue 5 Full Interrupt
3062 + unsigned int toe_q6_full : 1; // bit 6 TOE Queue 6 Full Interrupt
3063 + unsigned int toe_q7_full : 1; // bit 7 TOE Queue 7 Full Interrupt
3064 + unsigned int toe_q8_full : 1; // bit 8 TOE Queue 8 Full Interrupt
3065 + unsigned int toe_q9_full : 1; // bit 9 TOE Queue 9 Full Interrupt
3066 + unsigned int toe_q10_full : 1; // bit 10 TOE Queue 10 Full Interrupt
3067 + unsigned int toe_q11_full : 1; // bit 11 TOE Queue 11 Full Interrupt
3068 + unsigned int toe_q12_full : 1; // bit 12 TOE Queue 12 Full Interrupt
3069 + unsigned int toe_q13_full : 1; // bit 13 TOE Queue 13 Full Interrupt
3070 + unsigned int toe_q14_full : 1; // bit 14 TOE Queue 14 Full Interrupt
3071 + unsigned int toe_q15_full : 1; // bit 15 TOE Queue 15 Full Interrupt
3072 + unsigned int toe_q16_full : 1; // bit 16 TOE Queue 16 Full Interrupt
3073 + unsigned int toe_q17_full : 1; // bit 17 TOE Queue 17 Full Interrupt
3074 + unsigned int toe_q18_full : 1; // bit 18 TOE Queue 18 Full Interrupt
3075 + unsigned int toe_q19_full : 1; // bit 19 TOE Queue 19 Full Interrupt
3076 + unsigned int toe_q20_full : 1; // bit 20 TOE Queue 20 Full Interrupt
3077 + unsigned int toe_q21_full : 1; // bit 21 TOE Queue 21 Full Interrupt
3078 + unsigned int toe_q22_full : 1; // bit 22 TOE Queue 22 Full Interrupt
3079 + unsigned int toe_q23_full : 1; // bit 23 TOE Queue 23 Full Interrupt
3080 + unsigned int toe_q24_full : 1; // bit 24 TOE Queue 24 Full Interrupt
3081 + unsigned int toe_q25_full : 1; // bit 25 TOE Queue 25 Full Interrupt
3082 + unsigned int toe_q26_full : 1; // bit 26 TOE Queue 26 Full Interrupt
3083 + unsigned int toe_q27_full : 1; // bit 27 TOE Queue 27 Full Interrupt
3084 + unsigned int toe_q28_full : 1; // bit 28 TOE Queue 28 Full Interrupt
3085 + unsigned int toe_q29_full : 1; // bit 29 TOE Queue 29 Full Interrupt
3086 + unsigned int toe_q30_full : 1; // bit 30 TOE Queue 30 Full Interrupt
3087 + unsigned int toe_q31_full : 1; // bit 31 TOE Queue 31 Full Interrupt
3088 + } bits;
3089 +} INTR_REG2_T;
3090 +
3091 +#define TOE_QL_FULL_INT_BIT(x) BIT(x)
3092 +
3093 +/*
3094 + * Interrupt Status Register 3 (offset 0x0050)
3095 + * Interrupt Mask Register 3 (offset 0x0054)
3096 + * Interrupt Select Register 3 (offset 0x0058)
3097 + */
3098 +typedef union {
3099 + unsigned int bits32;
3100 + struct bit_0050 {
3101 + unsigned int toe_q32_full : 1; // bit 32 TOE Queue 32 Full Interrupt
3102 + unsigned int toe_q33_full : 1; // bit 33 TOE Queue 33 Full Interrupt
3103 + unsigned int toe_q34_full : 1; // bit 34 TOE Queue 34 Full Interrupt
3104 + unsigned int toe_q35_full : 1; // bit 35 TOE Queue 35 Full Interrupt
3105 + unsigned int toe_q36_full : 1; // bit 36 TOE Queue 36 Full Interrupt
3106 + unsigned int toe_q37_full : 1; // bit 37 TOE Queue 37 Full Interrupt
3107 + unsigned int toe_q38_full : 1; // bit 38 TOE Queue 38 Full Interrupt
3108 + unsigned int toe_q39_full : 1; // bit 39 TOE Queue 39 Full Interrupt
3109 + unsigned int toe_q40_full : 1; // bit 40 TOE Queue 40 Full Interrupt
3110 + unsigned int toe_q41_full : 1; // bit 41 TOE Queue 41 Full Interrupt
3111 + unsigned int toe_q42_full : 1; // bit 42 TOE Queue 42 Full Interrupt
3112 + unsigned int toe_q43_full : 1; // bit 43 TOE Queue 43 Full Interrupt
3113 + unsigned int toe_q44_full : 1; // bit 44 TOE Queue 44 Full Interrupt
3114 + unsigned int toe_q45_full : 1; // bit 45 TOE Queue 45 Full Interrupt
3115 + unsigned int toe_q46_full : 1; // bit 46 TOE Queue 46 Full Interrupt
3116 + unsigned int toe_q47_full : 1; // bit 47 TOE Queue 47 Full Interrupt
3117 + unsigned int toe_q48_full : 1; // bit 48 TOE Queue 48 Full Interrupt
3118 + unsigned int toe_q49_full : 1; // bit 49 TOE Queue 49 Full Interrupt
3119 + unsigned int toe_q50_full : 1; // bit 50 TOE Queue 50 Full Interrupt
3120 + unsigned int toe_q51_full : 1; // bit 51 TOE Queue 51 Full Interrupt
3121 + unsigned int toe_q52_full : 1; // bit 52 TOE Queue 52 Full Interrupt
3122 + unsigned int toe_q53_full : 1; // bit 53 TOE Queue 53 Full Interrupt
3123 + unsigned int toe_q54_full : 1; // bit 54 TOE Queue 54 Full Interrupt
3124 + unsigned int toe_q55_full : 1; // bit 55 TOE Queue 55 Full Interrupt
3125 + unsigned int toe_q56_full : 1; // bit 56 TOE Queue 56 Full Interrupt
3126 + unsigned int toe_q57_full : 1; // bit 57 TOE Queue 57 Full Interrupt
3127 + unsigned int toe_q58_full : 1; // bit 58 TOE Queue 58 Full Interrupt
3128 + unsigned int toe_q59_full : 1; // bit 59 TOE Queue 59 Full Interrupt
3129 + unsigned int toe_q60_full : 1; // bit 60 TOE Queue 60 Full Interrupt
3130 + unsigned int toe_q61_full : 1; // bit 61 TOE Queue 61 Full Interrupt
3131 + unsigned int toe_q62_full : 1; // bit 62 TOE Queue 62 Full Interrupt
3132 + unsigned int toe_q63_full : 1; // bit 63 TOE Queue 63 Full Interrupt
3133 + } bits;
3134 +} INTR_REG3_T;
3135 +
3136 +#define TOE_QH_FULL_INT_BIT(x) BIT(x-32)
3137 +
3138 +/*
3139 + * Interrupt Status Register 4 (offset 0x0060)
3140 + * Interrupt Mask Register 4 (offset 0x0064)
3141 + * Interrupt Select Register 4 (offset 0x0068)
3142 + */
3143 +typedef union {
3144 + unsigned char byte;
3145 + struct bit_0060 {
3146 + unsigned char status_changed : 1; // Status Changed Intr for RGMII Mode
3147 + unsigned char rx_overrun : 1; // GMAC Rx FIFO overrun interrupt
3148 + unsigned char tx_pause_off : 1; // received pause off frame interrupt
3149 + unsigned char rx_pause_off : 1; // received pause off frame interrupt
3150 + unsigned char tx_pause_on : 1; // transmit pause on frame interrupt
3151 + unsigned char rx_pause_on : 1; // received pause on frame interrupt
3152 + unsigned char cnt_full : 1; // MIB counters half full interrupt
3153 + unsigned char reserved : 1; //
3154 + } _PACKED_ bits;
3155 +} _PACKED_ GMAC_INTR_T;
3156 +
3157 +typedef union {
3158 + unsigned int bits32;
3159 + struct bit_0060_2 {
3160 + unsigned int swfq_empty : 1; // bit 0 Software Free Queue Empty Intr.
3161 + unsigned int hwfq_empty : 1; // bit 1 Hardware Free Queue Empty Intr.
3162 + unsigned int class_qf_int : 14; // bit 15:2 Classification Rx Queue13-0 Full Intr.
3163 + GMAC_INTR_T gmac0;
3164 + GMAC_INTR_T gmac1;
3165 + } bits;
3166 +} INTR_REG4_T;
3167 +
3168 +#define GMAC1_RESERVED_INT_BIT BIT(31)
3169 +#define GMAC1_MIB_INT_BIT BIT(30)
3170 +#define GMAC1_RX_PAUSE_ON_INT_BIT BIT(29)
3171 +#define GMAC1_TX_PAUSE_ON_INT_BIT BIT(28)
3172 +#define GMAC1_RX_PAUSE_OFF_INT_BIT BIT(27)
3173 +#define GMAC1_TX_PAUSE_OFF_INT_BIT BIT(26)
3174 +#define GMAC1_RX_OVERRUN_INT_BIT BIT(25)
3175 +#define GMAC1_STATUS_CHANGE_INT_BIT BIT(24)
3176 +#define GMAC0_RESERVED_INT_BIT BIT(23)
3177 +#define GMAC0_MIB_INT_BIT BIT(22)
3178 +#define GMAC0_RX_PAUSE_ON_INT_BIT BIT(21)
3179 +#define GMAC0_TX_PAUSE_ON_INT_BIT BIT(20)
3180 +#define GMAC0_RX_PAUSE_OFF_INT_BIT BIT(19)
3181 +#define GMAC0_TX_PAUSE_OFF_INT_BIT BIT(18)
3182 +#define GMAC0_RX_OVERRUN_INT_BIT BIT(17)
3183 +#define GMAC0_STATUS_CHANGE_INT_BIT BIT(16)
3184 +#define CLASS_RX_FULL_INT_BIT(x) BIT((x+2))
3185 +#define HWFQ_EMPTY_INT_BIT BIT(1)
3186 +#define SWFQ_EMPTY_INT_BIT BIT(0)
3187 +
3188 +#if 1
3189 +#define GMAC0_INT_BITS (GMAC0_MIB_INT_BIT)
3190 +#define GMAC1_INT_BITS (GMAC1_MIB_INT_BIT)
3191 +#else
3192 +#define GMAC0_INT_BITS (GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \
3193 + GMAC0_RX_PAUSE_ON_INT_BIT | GMAC0_TX_PAUSE_ON_INT_BIT | \
3194 + GMAC0_RX_PAUSE_OFF_INT_BIT | GMAC0_TX_PAUSE_OFF_INT_BIT | \
3195 + GMAC0_RX_OVERRUN_INT_BIT | GMAC0_STATUS_CHANGE_INT_BIT)
3196 +#define GMAC1_INT_BITS (GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \
3197 + GMAC1_RX_PAUSE_ON_INT_BIT | GMAC1_TX_PAUSE_ON_INT_BIT | \
3198 + GMAC1_RX_PAUSE_OFF_INT_BIT | GMAC1_TX_PAUSE_OFF_INT_BIT | \
3199 + GMAC1_RX_OVERRUN_INT_BIT | GMAC1_STATUS_CHANGE_INT_BIT)
3200 +#endif
3201 +
3202 +#define CLASS_RX_FULL_INT_BITS 0xfffc
3203 +
3204 +/*
3205 + * GLOBAL_QUEUE_THRESHOLD_REG (offset 0x0070)
3206 + */
3207 +typedef union {
3208 + unsigned int bits32;
3209 + struct bit_0070_2 {
3210 + unsigned int swfq_empty : 8; // 7:0 Software Free Queue Empty Threshold
3211 + unsigned int hwfq_empty : 8; // 15:8 Hardware Free Queue Empty Threshold
3212 + unsigned int intrq : 8; // 23:16
3213 + unsigned int toe_class : 8; // 31:24
3214 + } bits;
3215 +} QUEUE_THRESHOLD_T;
3216 +
3217 +
3218 +/*
3219 + * GMAC DMA Control Register
3220 + * GMAC0 offset 0x8000
3221 + * GMAC1 offset 0xC000
3222 + */
3223 +typedef union {
3224 + unsigned int bits32;
3225 + struct bit_8000 {
3226 + unsigned int td_bus : 2; // bit 1:0 Peripheral Bus Width
3227 + unsigned int td_burst_size : 2; // bit 3:2 TxDMA max burst size for every AHB request
3228 + unsigned int td_prot : 4; // bit 7:4 TxDMA protection control
3229 + unsigned int rd_bus : 2; // bit 9:8 Peripheral Bus Width
3230 + unsigned int rd_burst_size : 2; // bit 11:10 DMA max burst size for every AHB request
3231 + unsigned int rd_prot : 4; // bit 15:12 DMA Protection Control
3232 + unsigned int rd_insert_bytes : 2; // bit 17:16
3233 + unsigned int reserved : 10; // bit 27:18
3234 + unsigned int drop_small_ack : 1; // bit 28 1: Drop, 0: Accept
3235 + unsigned int loopback : 1; // bit 29 Loopback TxDMA to RxDMA
3236 + unsigned int td_enable : 1; // bit 30 Tx DMA Enable
3237 + unsigned int rd_enable : 1; // bit 31 Rx DMA Enable
3238 + } bits;
3239 +} GMAC_DMA_CTRL_T;
3240 +
3241 +/*
3242 + * GMAC Tx Weighting Control Register 0
3243 + * GMAC0 offset 0x8004
3244 + * GMAC1 offset 0xC004
3245 + */
3246 +typedef union {
3247 + unsigned int bits32;
3248 + struct bit_8004 {
3249 + unsigned int hw_tq0 : 6; // bit 5:0 HW TX Queue 3
3250 + unsigned int hw_tq1 : 6; // bit 11:6 HW TX Queue 2
3251 + unsigned int hw_tq2 : 6; // bit 17:12 HW TX Queue 1
3252 + unsigned int hw_tq3 : 6; // bit 23:18 HW TX Queue 0
3253 + unsigned int reserved : 8; // bit 31:24
3254 + } bits;
3255 +} GMAC_TX_WCR0_T; /* Weighting Control Register 0 */
3256 +
3257 +/*
3258 + * GMAC Tx Weighting Control Register 1
3259 + * GMAC0 offset 0x8008
3260 + * GMAC1 offset 0xC008
3261 + */
3262 +typedef union {
3263 + unsigned int bits32;
3264 + struct bit_8008 {
3265 + unsigned int sw_tq0 : 5; // bit 4:0 SW TX Queue 0
3266 + unsigned int sw_tq1 : 5; // bit 9:5 SW TX Queue 1
3267 + unsigned int sw_tq2 : 5; // bit 14:10 SW TX Queue 2
3268 + unsigned int sw_tq3 : 5; // bit 19:15 SW TX Queue 3
3269 + unsigned int sw_tq4 : 5; // bit 24:20 SW TX Queue 4
3270 + unsigned int sw_tq5 : 5; // bit 29:25 SW TX Queue 5
3271 + unsigned int reserved : 2; // bit 31:30
3272 + } bits;
3273 +} GMAC_TX_WCR1_T; /* Weighting Control Register 1 */
3274 +
3275 +/*
3276 + * Queue Read/Write Pointer
3277 + * GMAC SW TX Queue 0~5 Read/Write Pointer register
3278 + * GMAC0 offset 0x800C ~ 0x8020
3279 + * GMAC1 offset 0xC00C ~ 0xC020
3280 + * GMAC HW TX Queue 0~3 Read/Write Pointer register
3281 + * GMAC0 offset 0x8024 ~ 0x8030
3282 + * GMAC1 offset 0xC024 ~ 0xC030
3283 + *
3284 + * see DMA_RWPTR_T structure
3285 + */
3286 +
3287 +/*
3288 + * GMAC DMA Tx First Description Address Register
3289 + * GMAC0 offset 0x8038
3290 + * GMAC1 offset 0xC038
3291 + */
3292 +typedef union {
3293 + unsigned int bits32;
3294 + struct bit_8038 {
3295 + unsigned int reserved : 3;
3296 + unsigned int td_busy : 1; // bit 3 1: TxDMA busy; 0: TxDMA idle
3297 + unsigned int td_first_des_ptr : 28; // bit 31:4 first descriptor address
3298 + } bits;
3299 +} GMAC_TXDMA_FIRST_DESC_T;
3300 +
3301 +/*
3302 + * GMAC DMA Tx Current Description Address Register
3303 + * GMAC0 offset 0x803C
3304 + * GMAC1 offset 0xC03C
3305 + */
3306 +typedef union {
3307 + unsigned int bits32;
3308 + struct bit_803C {
3309 + unsigned int reserved : 4;
3310 + unsigned int td_curr_desc_ptr : 28; // bit 31:4 current descriptor address
3311 + } bits;
3312 +} GMAC_TXDMA_CURR_DESC_T;
3313 +
3314 +/*
3315 + * GMAC DMA Tx Description Word 0 Register
3316 + * GMAC0 offset 0x8040
3317 + * GMAC1 offset 0xC040
3318 + */
3319 +typedef union {
3320 + unsigned int bits32;
3321 + struct bit_8040 {
3322 + unsigned int buffer_size : 16; // bit 15:0 Transfer size
3323 + unsigned int desc_count : 6; // bit 21:16 number of descriptors used for the current frame
3324 + unsigned int status_tx_ok : 1; // bit 22 Tx Status, 1: Successful 0: Failed
3325 + unsigned int status_rvd : 6; // bit 28:23 Tx Status, Reserved bits
3326 + unsigned int perr : 1; // bit 29 protocol error during processing this descriptor
3327 + unsigned int derr : 1; // bit 30 data error during processing this descriptor
3328 + unsigned int reserved : 1; // bit 31
3329 + } bits;
3330 +} GMAC_TXDESC_0_T;
3331 +
3332 +/*
3333 + * GMAC DMA Tx Description Word 1 Register
3334 + * GMAC0 offset 0x8044
3335 + * GMAC1 offset 0xC044
3336 + */
3337 +typedef union {
3338 + unsigned int bits32;
3339 + struct txdesc_word1 {
3340 + unsigned int byte_count : 16; // bit 15: 0 Tx Frame Byte Count
3341 + unsigned int mtu_enable : 1; // bit 16 TSS segmentation use MTU setting
3342 + unsigned int ip_chksum : 1; // bit 17 IPV4 Header Checksum Enable
3343 + unsigned int ipv6_enable : 1; // bit 18 IPV6 Tx Enable
3344 + unsigned int tcp_chksum : 1; // bit 19 TCP Checksum Enable
3345 + unsigned int udp_chksum : 1; // bit 20 UDP Checksum Enable
3346 + unsigned int bypass_tss : 1; // bit 21
3347 + unsigned int ip_fixed_len : 1; // bit 22
3348 + unsigned int reserved : 9; // bit 31:23 Tx Flag, Reserved
3349 + } bits;
3350 +} GMAC_TXDESC_1_T;
3351 +
3352 +#define TSS_IP_FIXED_LEN_BIT BIT(22)
3353 +#define TSS_UDP_CHKSUM_BIT BIT(20)
3354 +#define TSS_TCP_CHKSUM_BIT BIT(19)
3355 +#define TSS_IPV6_ENABLE_BIT BIT(18)
3356 +#define TSS_IP_CHKSUM_BIT BIT(17)
3357 +#define TSS_MTU_ENABLE_BIT BIT(16)
3358 +
3359 +/*
3360 + * GMAC DMA Tx Description Word 2 Register
3361 + * GMAC0 offset 0x8048
3362 + * GMAC1 offset 0xC048
3363 + */
3364 +typedef union {
3365 + unsigned int bits32;
3366 + unsigned int buf_adr;
3367 +} GMAC_TXDESC_2_T;
3368 +
3369 +/*
3370 + * GMAC DMA Tx Description Word 3 Register
3371 + * GMAC0 offset 0x804C
3372 + * GMAC1 offset 0xC04C
3373 + */
3374 +typedef union {
3375 + unsigned int bits32;
3376 + struct txdesc_word3 {
3377 + unsigned int mtu_size : 11; // bit 10: 0 Tx Frame Byte Count
3378 + unsigned int reserved : 18; // bit 28:11
3379 + unsigned int eofie : 1; // bit 29 End of frame interrupt enable
3380 + unsigned int sof_eof : 2; // bit 31:30 11: only one, 10: first, 01: last, 00: linking
3381 + } bits;
3382 +} GMAC_TXDESC_3_T;
3383 +#define SOF_EOF_BIT_MASK 0x3fffffff
3384 +#define SOF_BIT 0x80000000
3385 +#define EOF_BIT 0x40000000
3386 +#define EOFIE_BIT BIT(29)
3387 +#define MTU_SIZE_BIT_MASK 0x7ff
3388 +
3389 +/*
3390 + * GMAC Tx Descriptor
3391 + */
3392 +typedef struct {
3393 + GMAC_TXDESC_0_T word0;
3394 + GMAC_TXDESC_1_T word1;
3395 + GMAC_TXDESC_2_T word2;
3396 + GMAC_TXDESC_3_T word3;
3397 +} GMAC_TXDESC_T;
3398 +
3399 +/*
3400 + * GMAC DMA Rx First Description Address Register
3401 + * GMAC0 offset 0x8058
3402 + * GMAC1 offset 0xC058
3403 + */
3404 +typedef union {
3405 + unsigned int bits32;
3406 + struct bit_8058 {
3407 + unsigned int reserved : 3; // bit 2:0
3408 + unsigned int rd_busy : 1; // bit 3 1-RxDMA busy; 0-RxDMA idle
3409 + unsigned int rd_first_des_ptr : 28; // bit 31:4 first descriptor address
3410 + } bits;
3411 +} GMAC_RXDMA_FIRST_DESC_T;
3412 +
3413 +/*
3414 + * GMAC DMA Rx Current Description Address Register
3415 + * GMAC0 offset 0x805C
3416 + * GMAC1 offset 0xC05C
3417 + */
3418 +typedef union {
3419 + unsigned int bits32;
3420 + struct bit_805C {
3421 + unsigned int reserved : 4; // bit 3:0
3422 + unsigned int rd_curr_des_ptr : 28; // bit 31:4 current descriptor address
3423 + } bits;
3424 +} GMAC_RXDMA_CURR_DESC_T;
3425 +
3426 +/*
3427 + * GMAC DMA Rx Description Word 0 Register
3428 + * GMAC0 offset 0x8060
3429 + * GMAC1 offset 0xC060
3430 + */
3431 +typedef union {
3432 + unsigned int bits32;
3433 + struct bit_8060 {
3434 + unsigned int buffer_size : 16; // bit 15:0 number of descriptors used for the current frame
3435 + unsigned int desc_count : 6; // bit 21:16 number of descriptors used for the current frame
3436 + unsigned int status : 4; // bit 24:22 Status of rx frame
3437 + unsigned int chksum_status : 3; // bit 28:26 Check Sum Status
3438 + unsigned int perr : 1; // bit 29 protocol error during processing this descriptor
3439 + unsigned int derr : 1; // bit 30 data error during processing this descriptor
3440 + unsigned int drop : 1; // bit 31 TOE/CIS Queue Full dropped packet to default queue
3441 + } bits;
3442 +} GMAC_RXDESC_0_T;
3443 +
3444 +#define GMAC_RXDESC_0_T_derr BIT(30)
3445 +#define GMAC_RXDESC_0_T_perr BIT(29)
3446 +#define GMAC_RXDESC_0_T_chksum_status(x) BIT((x+26))
3447 +#define GMAC_RXDESC_0_T_status(x) BIT((x+22))
3448 +#define GMAC_RXDESC_0_T_desc_count(x) BIT((x+16))
3449 +
3450 +#define RX_CHKSUM_IP_UDP_TCP_OK 0
3451 +#define RX_CHKSUM_IP_OK_ONLY 1
3452 +#define RX_CHKSUM_NONE 2
3453 +#define RX_CHKSUM_IP_ERR_UNKNOWN 4
3454 +#define RX_CHKSUM_IP_ERR 5
3455 +#define RX_CHKSUM_TCP_UDP_ERR 6
3456 +#define RX_CHKSUM_NUM 8
3457 +
3458 +#define RX_STATUS_GOOD_FRAME 0
3459 +#define RX_STATUS_TOO_LONG_GOOD_CRC 1
3460 +#define RX_STATUS_RUNT_FRAME 2
3461 +#define RX_STATUS_SFD_NOT_FOUND 3
3462 +#define RX_STATUS_CRC_ERROR 4
3463 +#define RX_STATUS_TOO_LONG_BAD_CRC 5
3464 +#define RX_STATUS_ALIGNMENT_ERROR 6
3465 +#define RX_STATUS_TOO_LONG_BAD_ALIGN 7
3466 +#define RX_STATUS_RX_ERR 8
3467 +#define RX_STATUS_DA_FILTERED 9
3468 +#define RX_STATUS_BUFFER_FULL 10
3469 +#define RX_STATUS_NUM 16
3470 +
3471 +
3472 +/*
3473 + * GMAC DMA Rx Description Word 1 Register
3474 + * GMAC0 offset 0x8064
3475 + * GMAC1 offset 0xC064
3476 + */
3477 +typedef union {
3478 + unsigned int bits32;
3479 + struct rxdesc_word1 {
3480 + unsigned int byte_count : 16; // bit 15: 0 Rx Frame Byte Count
3481 + unsigned int sw_id : 16; // bit 31:16 Software ID
3482 + } bits;
3483 +} GMAC_RXDESC_1_T;
3484 +
3485 +/*
3486 + * GMAC DMA Rx Description Word 2 Register
3487 + * GMAC0 offset 0x8068
3488 + * GMAC1 offset 0xC068
3489 + */
3490 +typedef union {
3491 + unsigned int bits32;
3492 + unsigned int buf_adr;
3493 +} GMAC_RXDESC_2_T;
3494 +
3495 +#define RX_INSERT_NONE 0
3496 +#define RX_INSERT_1_BYTE 1
3497 +#define RX_INSERT_2_BYTE 2
3498 +#define RX_INSERT_3_BYTE 3
3499 +
3500 +#define RX_INSERT_BYTES RX_INSERT_2_BYTE
3501 +/*
3502 + * GMAC DMA Rx Description Word 3 Register
3503 + * GMAC0 offset 0x806C
3504 + * GMAC1 offset 0xC06C
3505 + */
3506 +typedef union {
3507 + unsigned int bits32;
3508 + struct rxdesc_word3 {
3509 + unsigned int l3_offset : 8; // bit 7: 0 L3 data offset
3510 + unsigned int l4_offset : 8; // bit 15: 8 L4 data offset
3511 + unsigned int l7_offset : 8; // bit 23: 16 L7 data offset
3512 + unsigned int dup_ack : 1; // bit 24 Duplicated ACK detected
3513 + unsigned int abnormal : 1; // bit 25 abnormal case found
3514 + unsigned int option : 1; // bit 26 IPV4 option or IPV6 extension header
3515 + unsigned int out_of_seq : 1; // bit 27 Out of Sequence packet
3516 + unsigned int ctrl_flag : 1; // bit 28 Control Flag is present
3517 + unsigned int eofie : 1; // bit 29 End of frame interrupt enable
3518 + unsigned int sof_eof : 2; // bit 31:30 11: only one, 10: first, 01: last, 00: linking
3519 + } bits;
3520 +} GMAC_RXDESC_3_T;
3521 +
3522 +/*
3523 + * GMAC Rx Descriptor
3524 + */
3525 +typedef struct {
3526 + GMAC_RXDESC_0_T word0;
3527 + GMAC_RXDESC_1_T word1;
3528 + GMAC_RXDESC_2_T word2;
3529 + GMAC_RXDESC_3_T word3;
3530 +} GMAC_RXDESC_T;
3531 +
3532 +/*
3533 + * GMAC Hash Engine Enable/Action Register 0 Offset Register
3534 + * GMAC0 offset 0x8070
3535 + * GMAC1 offset 0xC070
3536 + */
3537 +typedef union {
3538 + unsigned int bits32;
3539 + struct bit_8070 {
3540 + unsigned int mr0hel : 6; // bit 5:0 match rule 0 hash entry size
3541 + unsigned int mr0_action : 5; // bit 10:6 Matching Rule 0 action offset
3542 + unsigned int reserved0 : 4; // bit 14:11
3543 + unsigned int mr0en : 1; // bit 15 Enable Matching Rule 0
3544 + unsigned int mr1hel : 6; // bit 21:16 match rule 1 hash entry size
3545 + unsigned int mr1_action : 5; // bit 26:22 Matching Rule 1 action offset
3546 + unsigned int timing : 3; // bit 29:27
3547 + unsigned int reserved1 : 1; // bit 30
3548 + unsigned int mr1en : 1; // bit 31 Enable Matching Rule 1
3549 + } bits;
3550 +} GMAC_HASH_ENABLE_REG0_T;
3551 +
3552 +/*
3553 + * GMAC Hash Engine Enable/Action Register 1 Offset Register
3554 + * GMAC0 offset 0x8074
3555 + * GMAC1 offset 0xC074
3556 + */
3557 +typedef union {
3558 + unsigned int bits32;
3559 + struct bit_8074 {
3560 + unsigned int mr2hel : 6; // bit 5:0 match rule 2 hash entry size
3561 + unsigned int mr2_action : 5; // bit 10:6 Matching Rule 2 action offset
3562 + unsigned int reserved2 : 4; // bit 14:11
3563 + unsigned int mr2en : 1; // bit 15 Enable Matching Rule 2
3564 + unsigned int mr3hel : 6; // bit 21:16 match rule 3 hash entry size
3565 + unsigned int mr3_action : 5; // bit 26:22 Matching Rule 3 action offset
3566 + unsigned int reserved1 : 4; // bit 30:27
3567 + unsigned int mr3en : 1; // bit 31 Enable Matching Rule 3
3568 + } bits;
3569 +} GMAC_HASH_ENABLE_REG1_T;
3570 +
3571 +/*
3572 + * GMAC Matching Rule Control Register 0
3573 + * GMAC0 offset 0x8078
3574 + * GMAC1 offset 0xC078
3575 + */
3576 +typedef union {
3577 + unsigned int bits32;
3578 + struct bit_8078 {
3579 + unsigned int sprx : 8; // bit 7:0 Support Protocol Register 7:0
3580 + unsigned int reserved2 : 4; // bit 11:8
3581 + unsigned int tos_traffic : 1; // bit 12 IPV4 TOS or IPV6 Traffice Class
3582 + unsigned int flow_lable : 1; // bit 13 IPV6 Flow label
3583 + unsigned int ip_hdr_len : 1; // bit 14 IPV4 Header length
3584 + unsigned int ip_version : 1; // bit 15 0: IPV4, 1: IPV6
3585 + unsigned int reserved1 : 3; // bit 18:16
3586 + unsigned int pppoe : 1; // bit 19 PPPoE Session ID enable
3587 + unsigned int vlan : 1; // bit 20 VLAN ID enable
3588 + unsigned int ether_type : 1; // bit 21 Ethernet type enable
3589 + unsigned int sa : 1; // bit 22 MAC SA enable
3590 + unsigned int da : 1; // bit 23 MAC DA enable
3591 + unsigned int priority : 3; // bit 26:24 priority if multi-rules matched
3592 + unsigned int port : 1; // bit 27 PORT ID matching enable
3593 + unsigned int l7 : 1; // bit 28 L7 matching enable
3594 + unsigned int l4 : 1; // bit 29 L4 matching enable
3595 + unsigned int l3 : 1; // bit 30 L3 matching enable
3596 + unsigned int l2 : 1; // bit 31 L2 matching enable
3597 + } bits;
3598 +} GMAC_MRxCR0_T;
3599 +
3600 +#define MR_L2_BIT BIT(31)
3601 +#define MR_L3_BIT BIT(30)
3602 +#define MR_L4_BIT BIT(29)
3603 +#define MR_L7_BIT BIT(28)
3604 +#define MR_PORT_BIT BIT(27)
3605 +#define MR_PRIORITY_BIT BIT(26)
3606 +#define MR_DA_BIT BIT(23)
3607 +#define MR_SA_BIT BIT(22)
3608 +#define MR_ETHER_TYPE_BIT BIT(21)
3609 +#define MR_VLAN_BIT BIT(20)
3610 +#define MR_PPPOE_BIT BIT(19)
3611 +#define MR_IP_VER_BIT BIT(15)
3612 +#define MR_IP_HDR_LEN_BIT BIT(14)
3613 +#define MR_FLOW_LABLE_BIT BIT(13)
3614 +#define MR_TOS_TRAFFIC_BIT BIT(12)
3615 +#define MR_SPR_BIT(x) BIT(x)
3616 +#define MR_SPR_BITS 0xff
3617 +
3618 +/*
3619 + * GMAC Matching Rule Control Register 1
3620 + * GMAC0 offset 0x807C
3621 + * GMAC1 offset 0xC07C
3622 + */
3623 +typedef union {
3624 + unsigned int bits32;
3625 + struct bit_807C {
3626 + unsigned int l4_byte0_15 : 16; // bit 15: 0
3627 + unsigned int dip_netmask : 7; // bit 22:16 Dest IP net mask, number of mask bits
3628 + unsigned int dip : 1; // bit 23 Dest IP
3629 + unsigned int sip_netmask : 7; // bit 30:24 Srce IP net mask, number of mask bits
3630 + unsigned int sip : 1; // bit 31 Srce IP
3631 + } bits;
3632 +} GMAC_MRxCR1_T;
3633 +
3634 +/*
3635 + * GMAC Matching Rule Control Register 2
3636 + * GMAC0 offset 0x8080
3637 + * GMAC1 offset 0xC080
3638 + */
3639 +typedef union {
3640 + unsigned int bits32;
3641 + struct bit_8080 {
3642 + unsigned int l7_byte0_23 : 24; // bit 23:0
3643 + unsigned int l4_byte16_24 : 8; // bit 31: 24
3644 + } bits;
3645 +} GMAC_MRxCR2_T;
3646 +
3647 +/*
3648 + * GMAC Support registers
3649 + * GMAC0 offset 0x80A8
3650 + * GMAC1 offset 0xC0A8
3651 + */
3652 +typedef union {
3653 + unsigned int bits32;
3654 + struct bit_80A8 {
3655 + unsigned int protocol : 8; // bit 7:0 Supported protocol
3656 + unsigned int swap : 3; // bit 10:8 Swap
3657 + unsigned int reserved : 21; // bit 31:11
3658 + } bits;
3659 +} GMAC_SPR_T;
3660 +
3661 +/*
3662 + * GMAC_AHB_WEIGHT registers
3663 + * GMAC0 offset 0x80C8
3664 + * GMAC1 offset 0xC0C8
3665 + */
3666 +typedef union {
3667 + unsigned int bits32;
3668 + struct bit_80C8 {
3669 + unsigned int hash_weight : 5; // 4:0
3670 + unsigned int rx_weight : 5; // 9:5
3671 + unsigned int tx_weight : 5; // 14:10
3672 + unsigned int pre_req : 5; // 19:15 Rx Data Pre Request FIFO Threshold
3673 + unsigned int tqDV_threshold : 5; // 24:20 DMA TqCtrl to Start tqDV FIFO Threshold
3674 + unsigned int reserved : 7; // 31:25
3675 + } bits;
3676 +} GMAC_AHB_WEIGHT_T;
3677 +
3678 +/*
3679 + * the register structure of GMAC
3680 + */
3681 +
3682 +/*
3683 + * GMAC RX FLTR
3684 + * GMAC0 Offset 0xA00C
3685 + * GMAC1 Offset 0xE00C
3686 + */
3687 +typedef union {
3688 + unsigned int bits32;
3689 + struct bit1_000c {
3690 + unsigned int unicast : 1; /* enable receive of unicast frames that are sent to STA address */
3691 + unsigned int multicast : 1; /* enable receive of multicast frames that pass multicast filter */
3692 + unsigned int broadcast : 1; /* enable receive of broadcast frames */
3693 + unsigned int promiscuous : 1; /* enable receive of all frames */
3694 + unsigned int error : 1; /* enable receive of all error frames */
3695 + unsigned int : 27;
3696 + } bits;
3697 +} GMAC_RX_FLTR_T;
3698 +
3699 +/*
3700 + * GMAC Configuration 0
3701 + * GMAC0 Offset 0xA018
3702 + * GMAC1 Offset 0xE018
3703 + */
3704 +typedef union {
3705 + unsigned int bits32;
3706 + struct bit1_0018 {
3707 + unsigned int dis_tx : 1; /* 0: disable transmit */
3708 + unsigned int dis_rx : 1; /* 1: disable receive */
3709 + unsigned int loop_back : 1; /* 2: transmit data loopback enable */
3710 + unsigned int flow_ctrl : 1; /* 3: flow control also trigged by Rx queues */
3711 + unsigned int adj_ifg : 4; /* 4-7: adjust IFG from 96+/-56 */
3712 + unsigned int max_len : 3; /* 8-10 maximum receive frame length allowed */
3713 + unsigned int dis_bkoff : 1; /* 11: disable back-off function */
3714 + unsigned int dis_col : 1; /* 12: disable 16 collisions abort function */
3715 + unsigned int sim_test : 1; /* 13: speed up timers in simulation */
3716 + unsigned int rx_fc_en : 1; /* 14: RX flow control enable */
3717 + unsigned int tx_fc_en : 1; /* 15: TX flow control enable */
3718 + unsigned int rgmii_en : 1; /* 16: RGMII in-band status enable */
3719 + unsigned int ipv4_rx_chksum : 1; /* 17: IPv4 RX Checksum enable */
3720 + unsigned int ipv6_rx_chksum : 1; /* 18: IPv6 RX Checksum enable */
3721 + unsigned int rx_tag_remove : 1; /* 19: Remove Rx VLAN tag */
3722 + unsigned int rgmm_edge : 1; // 20
3723 + unsigned int rxc_inv : 1; // 21
3724 + unsigned int ipv6_exthdr_order : 1; // 22
3725 + unsigned int rx_err_detect : 1; // 23
3726 + unsigned int port0_chk_hwq : 1; // 24
3727 + unsigned int port1_chk_hwq : 1; // 25
3728 + unsigned int port0_chk_toeq : 1; // 26
3729 + unsigned int port1_chk_toeq : 1; // 27
3730 + unsigned int port0_chk_classq : 1; // 28
3731 + unsigned int port1_chk_classq : 1; // 29
3732 + unsigned int reserved : 2; // 31
3733 + } bits;
3734 +} GMAC_CONFIG0_T;
3735 +
3736 +/*
3737 + * GMAC Configuration 1
3738 + * GMAC0 Offset 0xA01C
3739 + * GMAC1 Offset 0xE01C
3740 + */
3741 +typedef union {
3742 + unsigned int bits32;
3743 + struct bit1_001c {
3744 + unsigned int set_threshold : 8; /* flow control set threshold */
3745 + unsigned int rel_threshold : 8; /* flow control release threshold */
3746 + unsigned int reserved : 16;
3747 + } bits;
3748 +} GMAC_CONFIG1_T;
3749 +
3750 +#define GMAC_FLOWCTRL_SET_MAX 32
3751 +#define GMAC_FLOWCTRL_SET_MIN 0
3752 +#define GMAC_FLOWCTRL_RELEASE_MAX 32
3753 +#define GMAC_FLOWCTRL_RELEASE_MIN 0
3754 +
3755 +/*
3756 + * GMAC Configuration 2
3757 + * GMAC0 Offset 0xA020
3758 + * GMAC1 Offset 0xE020
3759 + */
3760 +typedef union {
3761 + unsigned int bits32;
3762 + struct bit1_0020 {
3763 + unsigned int set_threshold : 16; /* flow control set threshold */
3764 + unsigned int rel_threshold : 16; /* flow control release threshold */
3765 + } bits;
3766 +} GMAC_CONFIG2_T;
3767 +
3768 +/*
3769 + * GMAC Configuration 3
3770 + * GMAC0 Offset 0xA024
3771 + * GMAC1 Offset 0xE024
3772 + */
3773 +typedef union {
3774 + unsigned int bits32;
3775 + struct bit1_0024 {
3776 + unsigned int set_threshold : 16; /* flow control set threshold */
3777 + unsigned int rel_threshold : 16; /* flow control release threshold */
3778 + } bits;
3779 +} GMAC_CONFIG3_T;
3780 +
3781 +
3782 +/*
3783 + * GMAC STATUS
3784 + * GMAC0 Offset 0xA02C
3785 + * GMAC1 Offset 0xE02C
3786 + */
3787 +typedef union {
3788 + unsigned int bits32;
3789 + struct bit1_002c {
3790 + unsigned int link : 1; /* link status */
3791 + unsigned int speed : 2; /* link speed(00->2.5M 01->25M 10->125M) */
3792 + unsigned int duplex : 1; /* duplex mode */
3793 + unsigned int reserved : 1;
3794 + unsigned int mii_rmii : 2; /* PHY interface type */
3795 + unsigned int : 25;
3796 + } bits;
3797 +} GMAC_STATUS_T;
3798 +
3799 +#define GMAC_SPEED_10 0
3800 +#define GMAC_SPEED_100 1
3801 +#define GMAC_SPEED_1000 2
3802 +
3803 +#define GMAC_PHY_MII 0
3804 +#define GMAC_PHY_GMII 1
3805 +#define GMAC_PHY_RGMII_100_10 2
3806 +#define GMAC_PHY_RGMII_1000 3
3807 +
3808 +/*
3809 + * Queue Header
3810 + * (1) TOE Queue Header
3811 + * (2) Non-TOE Queue Header
3812 + * (3) Interrupt Queue Header
3813 + *
3814 + * memory Layout
3815 + * TOE Queue Header
3816 + * 0x60003000 +---------------------------+ 0x0000
3817 + * | TOE Queue 0 Header |
3818 + * | 8 * 4 Bytes |
3819 + * +---------------------------+ 0x0020
3820 + * | TOE Queue 1 Header |
3821 + * | 8 * 4 Bytes |
3822 + * +---------------------------+ 0x0040
3823 + * | ...... |
3824 + * | |
3825 + * +---------------------------+
3826 + *
3827 + * Non TOE Queue Header
3828 + * 0x60002000 +---------------------------+ 0x0000
3829 + * | Default Queue 0 Header |
3830 + * | 2 * 4 Bytes |
3831 + * +---------------------------+ 0x0008
3832 + * | Default Queue 1 Header |
3833 + * | 2 * 4 Bytes |
3834 + * +---------------------------+ 0x0010
3835 + * | Classification Queue 0 |
3836 + * | 2 * 4 Bytes |
3837 + * +---------------------------+
3838 + * | Classification Queue 1 |
3839 + * | 2 * 4 Bytes |
3840 + * +---------------------------+ (n * 8 + 0x10)
3841 + * | ... |
3842 + * | 2 * 4 Bytes |
3843 + * +---------------------------+ (13 * 8 + 0x10)
3844 + * | Classification Queue 13 |
3845 + * | 2 * 4 Bytes |
3846 + * +---------------------------+ 0x80
3847 + * | Interrupt Queue 0 |
3848 + * | 2 * 4 Bytes |
3849 + * +---------------------------+
3850 + * | Interrupt Queue 1 |
3851 + * | 2 * 4 Bytes |
3852 + * +---------------------------+
3853 + * | Interrupt Queue 2 |
3854 + * | 2 * 4 Bytes |
3855 + * +---------------------------+
3856 + * | Interrupt Queue 3 |
3857 + * | 2 * 4 Bytes |
3858 + * +---------------------------+
3859 + *
3860 + */
3861 +#define TOE_QUEUE_HDR_ADDR(n) (TOE_TOE_QUE_HDR_BASE + n * 32)
3862 +#define TOE_Q_HDR_AREA_END (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX + 1))
3863 +#define TOE_DEFAULT_Q_HDR_BASE(x) (TOE_NONTOE_QUE_HDR_BASE + 0x08 * (x))
3864 +#define TOE_CLASS_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x10)
3865 +#define TOE_INTR_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x80)
3866 +#define INTERRUPT_QUEUE_HDR_ADDR(n) (TOE_INTR_Q_HDR_BASE + n * 8)
3867 +#define NONTOE_Q_HDR_AREA_END (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX + 1))
3868 +/*
3869 + * TOE Queue Header Word 0
3870 + */
3871 +typedef union {
3872 + unsigned int bits32;
3873 + unsigned int base_size;
3874 +} TOE_QHDR0_T;
3875 +
3876 +#define TOE_QHDR0_BASE_MASK (~0x0f)
3877 +
3878 +/*
3879 + * TOE Queue Header Word 1
3880 + */
3881 +typedef union {
3882 + unsigned int bits32;
3883 + struct bit_qhdr1 {
3884 + unsigned int rptr : 16; // bit 15:0
3885 + unsigned int wptr : 16; // bit 31:16
3886 + } bits;
3887 +} TOE_QHDR1_T;
3888 +
3889 +/*
3890 + * TOE Queue Header Word 2
3891 + */
3892 +typedef union {
3893 + unsigned int bits32;
3894 + struct bit_qhdr2 {
3895 + unsigned int TotalPktSize : 17; // bit 16: 0 Total packet size
3896 + unsigned int reserved : 7; // bit 23:17
3897 + unsigned int dack : 1; // bit 24 1: Duplicated ACK
3898 + unsigned int abn : 1; // bit 25 1: Abnormal case Found
3899 + unsigned int tcp_opt : 1; // bit 26 1: Have TCP option
3900 + unsigned int ip_opt : 1; // bit 27 1: have IPV4 option or IPV6 Extension header
3901 + unsigned int sat : 1; // bit 28 1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
3902 + unsigned int osq : 1; // bit 29 1: out of sequence
3903 + unsigned int ctl : 1; // bit 30 1: have control flag bits (except ack)
3904 + unsigned int usd : 1; // bit 31 0: if no data assembled yet
3905 + } bits;
3906 +} TOE_QHDR2_T;
3907 +
3908 +/*
3909 + * TOE Queue Header Word 3
3910 + */
3911 +typedef union {
3912 + unsigned int bits32;
3913 + unsigned int seq_num;
3914 +} TOE_QHDR3_T;
3915 +
3916 +/*
3917 + * TOE Queue Header Word 4
3918 + */
3919 +typedef union {
3920 + unsigned int bits32;
3921 + unsigned int ack_num;
3922 +} TOE_QHDR4_T;
3923 +
3924 +/*
3925 + * TOE Queue Header Word 5
3926 + */
3927 +typedef union {
3928 + unsigned int bits32;
3929 + struct bit_qhdr5 {
3930 + unsigned int AckCnt : 16; // bit 15:0
3931 + unsigned int SeqCnt : 16; // bit 31:16
3932 + } bits;
3933 +} TOE_QHDR5_T;
3934 +
3935 +/*
3936 + * TOE Queue Header Word 6
3937 + */
3938 +typedef union {
3939 + unsigned int bits32;
3940 + struct bit_qhdr6 {
3941 + unsigned int WinSize : 16; // bit 15:0
3942 + unsigned int iq_num : 2; // bit 17:16
3943 + unsigned int MaxPktSize : 14; // bit 31:18
3944 + } bits;
3945 +} TOE_QHDR6_T;
3946 +
3947 +/*
3948 + * TOE Queue Header Word 7
3949 + */
3950 +typedef union {
3951 + unsigned int bits32;
3952 + struct bit_qhdr7 {
3953 + unsigned int AckThreshold : 16; // bit 15:0
3954 + unsigned int SeqThreshold : 16; // bit 31:16
3955 + } bits;
3956 +} TOE_QHDR7_T;
3957 +
3958 +/*
3959 + * TOE Queue Header
3960 + */
3961 +typedef struct {
3962 + TOE_QHDR0_T word0;
3963 + TOE_QHDR1_T word1;
3964 + TOE_QHDR2_T word2;
3965 + TOE_QHDR3_T word3;
3966 + TOE_QHDR4_T word4;
3967 + TOE_QHDR5_T word5;
3968 + TOE_QHDR6_T word6;
3969 + TOE_QHDR7_T word7;
3970 +} TOE_QHDR_T;
3971 +
3972 +/*
3973 + * NONTOE Queue Header Word 0
3974 + */
3975 +typedef union {
3976 + unsigned int bits32;
3977 + unsigned int base_size;
3978 +} NONTOE_QHDR0_T;
3979 +
3980 +#define NONTOE_QHDR0_BASE_MASK (~0x0f)
3981 +
3982 +/*
3983 + * NONTOE Queue Header Word 1
3984 + */
3985 +typedef union {
3986 + unsigned int bits32;
3987 + struct bit_nonqhdr1 {
3988 + unsigned int rptr : 16; // bit 15:0
3989 + unsigned int wptr : 16; // bit 31:16
3990 + } bits;
3991 +} NONTOE_QHDR1_T;
3992 +
3993 +/*
3994 + * Non-TOE Queue Header
3995 + */
3996 +typedef struct {
3997 + NONTOE_QHDR0_T word0;
3998 + NONTOE_QHDR1_T word1;
3999 +} NONTOE_QHDR_T;
4000 +
4001 +/*
4002 + * Interrupt Queue Header Word 0
4003 + */
4004 +typedef union {
4005 + unsigned int bits32;
4006 + struct bit_intrqhdr0 {
4007 + unsigned int win_size : 16; // bit 15:0 Descriptor Ring Size
4008 + unsigned int wptr : 16; // bit 31:16 Write Pointer where hw stopped
4009 + } bits;
4010 +} INTR_QHDR0_T;
4011 +
4012 +/*
4013 + * Interrupt Queue Header Word 1
4014 + */
4015 +typedef union {
4016 + unsigned int bits32;
4017 + struct bit_intrqhdr1 {
4018 + unsigned int TotalPktSize : 17; // bit 16: 0 Total packet size
4019 + unsigned int tcp_qid : 8; // bit 24:17 TCP Queue ID
4020 + unsigned int dack : 1; // bit 25 1: Duplicated ACK
4021 + unsigned int abn : 1; // bit 26 1: Abnormal case Found
4022 + unsigned int tcp_opt : 1; // bit 27 1: Have TCP option
4023 + unsigned int ip_opt : 1; // bit 28 1: have IPV4 option or IPV6 Extension header
4024 + unsigned int sat : 1; // bit 29 1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
4025 + unsigned int osq : 1; // bit 30 1: out of sequence
4026 + unsigned int ctl : 1; // bit 31 1: have control flag bits (except ack)
4027 + } bits;
4028 +} INTR_QHDR1_T;
4029 +
4030 +/*
4031 + * Interrupt Queue Header Word 2
4032 + */
4033 +typedef union {
4034 + unsigned int bits32;
4035 + unsigned int seq_num;
4036 +} INTR_QHDR2_T;
4037 +
4038 +/*
4039 + * Interrupt Queue Header Word 3
4040 + */
4041 +typedef union {
4042 + unsigned int bits32;
4043 + unsigned int ack_num;
4044 +} INTR_QHDR3_T;
4045 +
4046 +/*
4047 + * Interrupt Queue Header Word 4
4048 + */
4049 +typedef union {
4050 + unsigned int bits32;
4051 + struct bit_intrqhdr4 {
4052 + unsigned int AckCnt : 16; // bit 15:0 Ack# change since last ack# intr.
4053 + unsigned int SeqCnt : 16; // bit 31:16 Seq# change since last seq# intr.
4054 + } bits;
4055 +} INTR_QHDR4_T;
4056 +
4057 +/*
4058 + * Interrupt Queue Header
4059 + */
4060 +typedef struct {
4061 + INTR_QHDR0_T word0;
4062 + INTR_QHDR1_T word1;
4063 + INTR_QHDR2_T word2;
4064 + INTR_QHDR3_T word3;
4065 + INTR_QHDR4_T word4;
4066 + unsigned int word5;
4067 + unsigned int word6;
4068 + unsigned int word7;
4069 +} INTR_QHDR_T;
4070 +
4071 +/*
4072 + * GMAC private data
4073 + */
4074 +typedef struct {
4075 + unsigned int rwptr_reg;
4076 + unsigned int desc_base;
4077 + unsigned int desc_base_dma;
4078 + unsigned short finished_idx;
4079 + struct sk_buff *tx_skb[TOE_GMAC_SWTXQ_DESC_NUM];
4080 +} GMAC_SWTXQ_T;
4081 +
4082 +struct gmac_private {
4083 + struct phy_device *phydev;
4084 + unsigned int port_id;
4085 + unsigned int dma_base_addr;
4086 + unsigned int swtxq_desc_base;
4087 + GMAC_SWTXQ_T swtxq[TOE_SW_TXQ_NUM];
4088 + NONTOE_QHDR_T *default_qhdr;
4089 + unsigned int default_desc_base;
4090 + dma_addr_t default_desc_base_dma;
4091 + dma_addr_t swtxq_desc_base_dma;
4092 + unsigned int flow_control_enable;
4093 + unsigned int intr0_enabled;
4094 + unsigned int intr1_enabled;
4095 + unsigned int intr2_enabled;
4096 + unsigned int intr3_enabled;
4097 + unsigned int intr4_enabled;
4098 + unsigned int intr0_selected;
4099 + unsigned int intr1_selected;
4100 + unsigned int intr2_selected;
4101 + unsigned int intr3_selected;
4102 + unsigned int intr4_selected;
4103 +};
4104 +
4105 +struct toe_private {
4106 + void __iomem *global_base;
4107 + struct net_device *net_dev[2];
4108 + struct device *dev;
4109 + struct work_struct freq_work;
4110 + spinlock_t freeq_lock;
4111 + unsigned int swfq_desc_base;
4112 + unsigned int hwfq_desc_base;
4113 + unsigned int hwfq_buf_base;
4114 + dma_addr_t sw_freeq_desc_base_dma;
4115 + dma_addr_t hw_freeq_desc_base_dma;
4116 + dma_addr_t hwfq_buf_base_dma;
4117 + dma_addr_t hwfq_buf_end_dma;
4118 +};
4119 +
4120 +#define GMAC_PORT0 0
4121 +#define GMAC_PORT1 1
4122 +
4123 +#endif /* _GMAC_SL351x_H */
4124 --- /dev/null
4125 +++ b/drivers/net/gemini_negmac/Makefile
4126 @@ -0,0 +1,3 @@
4127 +obj-$(CONFIG_GEMINI_NET_ENGINE_GMAC)+= gemini_negmac.o
4128 +
4129 +gemini_negmac-objs := gm_gmac.o
4130 --- a/drivers/net/Kconfig
4131 +++ b/drivers/net/Kconfig
4132 @@ -2087,6 +2087,13 @@ config ACENIC_OMIT_TIGON_I
4133
4134 The safe and default value for this is N.
4135
4136 +config GEMINI_NET_ENGINE_GMAC
4137 + tristate "Gemini Gigabit Ethernet support"
4138 + depends on ARCH_GEMINI
4139 + select PHYLIB
4140 + help
4141 + This driver supports Gemini TOE and NAT dual Gigabit Ethernet.
4142 +
4143 config DL2K
4144 tristate "DL2000/TC902x-based Gigabit Ethernet support"
4145 depends on PCI
4146 --- a/drivers/net/Makefile
4147 +++ b/drivers/net/Makefile
4148 @@ -234,6 +234,7 @@ pasemi_mac_driver-objs := pasemi_mac.o p
4149 obj-$(CONFIG_MLX4_CORE) += mlx4/
4150 obj-$(CONFIG_ENC28J60) += enc28j60.o
4151 obj-$(CONFIG_ETHOC) += ethoc.o
4152 +obj-$(CONFIG_GEMINI_NET_ENGINE_GMAC) += gemini_negmac/
4153
4154 obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o
4155
4156 --- /dev/null
4157 +++ b/drivers/usb/host/ehci-fotg2xx.c
4158 @@ -0,0 +1,459 @@
4159 +/*
4160 + * EHCI Host Controller driver
4161 + *
4162 + * Copyright (C) 2006 Sony Computer Entertainment Inc.
4163 + * Copyright 2006 Sony Corp.
4164 + *
4165 + * This program is free software; you can redistribute it and/or modify
4166 + * it under the terms of the GNU General Public License as published by
4167 + * the Free Software Foundation; version 2 of the License.
4168 + */
4169 +
4170 +#include <linux/platform_device.h>
4171 +#include <mach/hardware.h>
4172 +
4173 +#define otg_set(port, bits) writel(readl(hcd->regs + port) | bits, hcd->regs + port)
4174 +
4175 +#define otg_clear(port, bits) writel(readl(hcd->regs + port) & ~bits, hcd->regs + port)
4176 +
4177 +#define GLOBAL_ISR 0xC0
4178 +#define GLOBAL_ICR 0xC4
4179 +
4180 +#define HCD_MISC 0x40
4181 +
4182 +#define OTGC_SCR 0x80
4183 +#define OTGC_INT_EN 0x88
4184 +
4185 +#define GLOBAL_INT_POLARITY (1 << 3)
4186 +#define GLOBAL_INT_MASK_HC (1 << 2)
4187 +#define GLOBAL_INT_MASK_OTG (1 << 1)
4188 +#define GLOBAL_INT_MASK_DEV (1 << 0)
4189 +
4190 +#define OTGC_SCR_ID (1 << 21)
4191 +#define OTGC_SCR_CROLE (1 << 20)
4192 +#define OTGC_SCR_VBUS_VLD (1 << 19)
4193 +#define OTGC_SCR_A_SRP_RESP_TYPE (1 << 8)
4194 +#define OTGC_SCR_A_SRP_DET_EN (1 << 7)
4195 +#define OTGC_SCR_A_SET_B_HNP_EN (1 << 6)
4196 +#define OTGC_SCR_A_BUS_DROP (1 << 5)
4197 +#define OTGC_SCR_A_BUS_REQ (1 << 4)
4198 +
4199 +#define OTGC_INT_APLGRMV (1 << 12)
4200 +#define OTGC_INT_BPLGRMV (1 << 11)
4201 +#define OTGC_INT_OVC (1 << 10)
4202 +#define OTGC_INT_IDCHG (1 << 9)
4203 +#define OTGC_INT_RLCHG (1 << 8)
4204 +#define OTGC_INT_AVBUSERR (1 << 5)
4205 +#define OTGC_INT_ASRPDET (1 << 4)
4206 +#define OTGC_INT_BSRPDN (1 << 0)
4207 +
4208 +#define OTGC_INT_A_TYPE (OTGC_INT_ASRPDET|OTGC_INT_AVBUSERR|OTGC_INT_OVC|OTGC_INT_RLCHG|OTGC_INT_IDCHG|OTGC_INT_APLGRMV)
4209 +#define OTGC_INT_B_TYPE (OTGC_INT_AVBUSERR|OTGC_INT_OVC|OTGC_INT_RLCHG|OTGC_INT_IDCHG)
4210 +
4211 +static void fotg2xx_otgc_role_change(struct usb_hcd *hcd);
4212 +
4213 +static void fotg2xx_otgc_init(struct usb_hcd *hcd)
4214 +{
4215 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
4216 + unsigned int reg;
4217 +
4218 + reg = __raw_readl(hcd->regs + OTGC_SCR);
4219 + ehci_info(ehci, "role detected: %s, ",
4220 + (reg & OTGC_SCR_CROLE) ? "Peripheral" : "Host");
4221 +
4222 + if (reg & OTGC_SCR_ID)
4223 + ehci_info(ehci, "B-Device (may be unsupported!)\n");
4224 + else
4225 + ehci_info(ehci, "A-Device\n");
4226 +
4227 + /* Enable the SRP detect */
4228 + reg &= ~OTGC_SCR_A_SRP_RESP_TYPE;
4229 + __raw_writel(reg, hcd->regs + OTGC_SCR);
4230 +
4231 + reg = __raw_readl(hcd->regs + OTGC_INT_EN);
4232 + /* clear INT B: bits AVBUSERR | OVC | RLCHG | IDCHG */
4233 + reg &= ~OTGC_INT_B_TYPE;
4234 + /* set INT A: bits ASRPDET | AVBUSERR | OVC | RLCHG | IDCHG | APLGRMV */
4235 + reg |= OTGC_INT_A_TYPE;
4236 + __raw_writel(reg, hcd->regs + OTGC_INT_EN);
4237 +
4238 + reg = __raw_readl(hcd->regs + GLOBAL_ICR);
4239 + reg &= ~GLOBAL_INT_MASK_OTG;
4240 + __raw_writel(reg, hcd->regs + GLOBAL_ICR);
4241 +
4242 + /* setup MISC register, fixes timing problems */
4243 + reg = __raw_readl(hcd->regs + HCD_MISC);
4244 + reg |= 0xD;
4245 + __raw_writel(reg, hcd->regs + HCD_MISC);
4246 +
4247 + fotg2xx_otgc_role_change(hcd);
4248 +}
4249 +
4250 +static void fotg2xx_otgh_close(struct usb_hcd *hcd)
4251 +{
4252 + unsigned int reg;
4253 +
4254 + /* <1>.Enable Interrupt Mask */
4255 + reg = __raw_readl(hcd->regs + GLOBAL_ICR);
4256 + reg |= GLOBAL_INT_MASK_HC;
4257 + __raw_writel(reg, hcd->regs + GLOBAL_ICR);
4258 +
4259 + /* <2>.Clear the Interrupt status */
4260 + reg = __raw_readl(hcd->regs + 0x18);
4261 + reg &= 0x0000003F;
4262 + __raw_writel(reg, hcd->regs + 0x14);
4263 +}
4264 +
4265 +static void fotg2xx_otgh_open(struct usb_hcd *hcd)
4266 +{
4267 + unsigned int reg;
4268 +
4269 + reg = __raw_readl(hcd->regs + OTGC_SCR);
4270 + reg &= ~OTGC_SCR_A_SRP_DET_EN;
4271 + __raw_writel(reg, hcd->regs + OTGC_SCR);
4272 +
4273 + reg = __raw_readl(hcd->regs + GLOBAL_ICR);
4274 + reg &= ~GLOBAL_INT_MASK_HC;
4275 + __raw_writel(reg, hcd->regs + GLOBAL_ICR);
4276 +}
4277 +
4278 +/* change to host role */
4279 +static void fotg2xx_otgc_role_change(struct usb_hcd *hcd)
4280 +{
4281 +
4282 + /* clear A_SET_B_HNP_EN */
4283 + otg_clear(0x80, BIT(6));
4284 +
4285 + /*** Enable VBUS driving */
4286 + if (readl(hcd->regs + 0x80) & BIT(19))
4287 + printk(KERN_INFO "VBUS already enabled\n");
4288 + else {
4289 + int cnt = 0;
4290 +
4291 + /* clear A_BUS_DROP */
4292 + otg_clear(0x80, BIT(5));
4293 +
4294 + /* set A_BUS_REQ */
4295 + otg_set(0x80, BIT(4));
4296 +
4297 + /* set global bus reg to VBUS on */
4298 + writel(readl(IO_ADDRESS(0x40000000) + 0x30) | ((BIT(21)|BIT(22))),
4299 + IO_ADDRESS(0x40000000) + 0x30);
4300 +
4301 + if (readl(hcd->regs + 0x80) & (1<<19)) {
4302 + printk(KERN_INFO "Waiting for VBus");
4303 + while (!(readl(hcd->regs + 0x80) & (1<<19)) && (cnt < 80)) {
4304 + printk(KERN_CONT ".");
4305 + cnt++;
4306 + }
4307 + printk(KERN_CONT "\n");
4308 + } else
4309 + printk(KERN_INFO "VBUS enabled.\n");
4310 +
4311 + mdelay(1);
4312 + }
4313 + fotg2xx_otgh_open(hcd);
4314 +}
4315 +
4316 +static int fotg2xx_ehci_hc_reset(struct usb_hcd *hcd)
4317 +{
4318 + int result;
4319 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
4320 +
4321 + ehci->caps = hcd->regs;
4322 + ehci->regs = hcd->regs + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
4323 +
4324 + dbg_hcs_params(ehci, "reset");
4325 + dbg_hcc_params(ehci, "reset");
4326 +
4327 + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
4328 + hcd->has_tt = 1;
4329 +
4330 + result = ehci_halt(ehci);
4331 + if (result)
4332 + return result;
4333 +
4334 + result = ehci_init(hcd);
4335 + if (result)
4336 + return result;
4337 +
4338 + ehci_port_power(ehci, 0);
4339 +
4340 + return result;
4341 +}
4342 +
4343 +/*
4344 + * Name: OTGC_INT_ISR
4345 + * Description:This interrupt service routine belongs to the OTG-Controller
4346 + * <1>.Check for ID_Change
4347 + * <2>.Check for RL_Change
4348 + * <3>.Error Detect
4349 + * Input: wINTStatus
4350 + * Output:void
4351 + */
4352 +void fotg2xx_int_isr(struct usb_hcd *hcd, u32 wINTStatus)
4353 +{
4354 + /* <1>.Check for ID_Change */
4355 + if (wINTStatus&OTGC_INT_IDCHG) {
4356 + if ((readl(hcd->regs + 0x80) & BIT(21)) != 0)
4357 + fotg2xx_otgc_init(hcd); /* Change to B Type */
4358 + else
4359 + fotg2xx_otgc_init(hcd); /* Change to A Type */
4360 +
4361 + return;
4362 + }
4363 +
4364 + /* <2>.Check for RL_Change */
4365 + if (wINTStatus&OTGC_INT_RLCHG)
4366 + fotg2xx_otgc_role_change(hcd);
4367 +
4368 + /* <3>.Error Detect */
4369 + if (wINTStatus&OTGC_INT_AVBUSERR)
4370 + printk(KERN_ERR "VBus error!\n");
4371 +
4372 + if (wINTStatus&OTGC_INT_OVC)
4373 + printk(KERN_WARNING "Overcurrent detected!\n");
4374 +
4375 + /* <3>.Check for Type-A/Type-B Interrupt */
4376 + if ((readl(hcd->regs + 0x80) & BIT(21)) == 0) { /*For Type-A Interrupt*/
4377 + if (wINTStatus & (OTGC_INT_A_TYPE | OTGC_INT_ASRPDET)) {
4378 + /* <1>.SRP detected => then set global variable */
4379 + printk(KERN_WARNING "SRP detected, but not implemented!\n");
4380 +
4381 +#if 0
4382 + u32 wTempCounter;
4383 + /* <2>.Turn on the V Bus */
4384 + pFTC_OTG->otg.state = OTG_STATE_A_WAIT_VRISE;
4385 + OTGC_enable_vbus_draw_storlink(1);
4386 + pFTC_OTG->otg.state = OTG_STATE_A_HOST;
4387 + /* <3>.Should waiting for Device-Connect Wait 300ms */
4388 + INFO(pFTC_OTG, ">>> OTG-A Waiting for OTG-B Connect,\n");
4389 + wTempCounter = 0;
4390 + while (mwHost20_PORTSC_ConnectStatus_Rd() == 0) {
4391 + mdelay(1);
4392 + wTempCounter++;
4393 + /* Waiting for 300 ms */
4394 + if (wTempCounter > 300) {
4395 + mdwOTGC_Control_A_SRP_DET_EN_Clr();
4396 + INFO(pFTC_OTG, ">>> OTG-B do not connect under 300 ms...\n");
4397 + break;
4398 + }
4399 + }
4400 + /* <4>.If Connect => issue quick Reset */
4401 + if (mwHost20_PORTSC_ConnectStatus_Rd() > 0) {
4402 + mdelay(300); /* For OPT-A Test */
4403 + OTGH_host_quick_Reset();
4404 + OTGH_Open();
4405 + pFTC_OTG->otg.host->A_Disable_Set_Feature_HNP = 0;
4406 + }
4407 +#endif
4408 + }
4409 + } else { /* For Type-B Interrupt */
4410 + BUG();
4411 + }
4412 +}
4413 +
4414 +static irqreturn_t fotg2xx_ehci_irq(int irq, void *devid)
4415 +{
4416 + struct usb_hcd *hcd = devid;
4417 + u32 val;
4418 +
4419 + /* OTG Interrupt Status Register */
4420 + val = readl(hcd->regs + 0x84);
4421 +
4422 + /* OTG stuff */
4423 + if (val) {
4424 + /* supposed to do "INT STS Clr" - XXX */
4425 + writel(readl(hcd->regs + 0x84) | val, hcd->regs + 0x84);
4426 +
4427 + fotg2xx_int_isr(hcd, val);
4428 +
4429 + /* supposed to do "INT STS Clr" - XXX */
4430 + writel(readl(hcd->regs + 0x84) | val, hcd->regs + 0x84);
4431 +
4432 + return IRQ_HANDLED;
4433 + }
4434 +
4435 + if ((readl(hcd->regs + 0x80) & BIT(20)) == 0) { /* Role is HOST */
4436 + if (readl(hcd->regs + 0xC0) & BIT(2)) { /* INT STS HOST */
4437 + /* leave this for ehci irq handler */
4438 + return IRQ_NONE;
4439 + }
4440 + } else
4441 + printk(KERN_WARNING
4442 + "received irq for peripheral - don't know what to do!\n");
4443 +
4444 + /* do not call the ehci irq handler */
4445 + return IRQ_HANDLED;
4446 +}
4447 +
4448 +static int fotg2xx_ehci_run(struct usb_hcd *hcd)
4449 +{
4450 + int retval;
4451 +
4452 + retval = ehci_run(hcd);
4453 +
4454 + fotg2xx_otgh_close(hcd);
4455 + fotg2xx_otgc_init(hcd);
4456 +
4457 + return retval;
4458 +}
4459 +
4460 +static const struct hc_driver fotg2xx_ehci_hc_driver = {
4461 + .description = hcd_name,
4462 + .product_desc = "FOTG2XX EHCI Host Controller",
4463 + .hcd_priv_size = sizeof(struct ehci_hcd),
4464 + .irq = ehci_irq,
4465 + .flags = HCD_MEMORY | HCD_USB2,
4466 + .reset = fotg2xx_ehci_hc_reset,
4467 + .start = fotg2xx_ehci_run,
4468 + .stop = ehci_stop,
4469 + .shutdown = ehci_shutdown,
4470 + .urb_enqueue = ehci_urb_enqueue,
4471 + .urb_dequeue = ehci_urb_dequeue,
4472 + .endpoint_disable = ehci_endpoint_disable,
4473 + .get_frame_number = ehci_get_frame,
4474 + .hub_status_data = ehci_hub_status_data,
4475 + .hub_control = ehci_hub_control,
4476 +#if defined(CONFIG_PM)
4477 + .bus_suspend = ehci_bus_suspend,
4478 + .bus_resume = ehci_bus_resume,
4479 +#endif
4480 + .relinquish_port = ehci_relinquish_port,
4481 + .port_handed_over = ehci_port_handed_over,
4482 +};
4483 +
4484 +static int fotg2xx_ehci_probe(struct platform_device *pdev)
4485 +{
4486 + const struct hc_driver *driver = &fotg2xx_ehci_hc_driver;
4487 + struct usb_hcd *hcd;
4488 + struct resource *res;
4489 + int irq;
4490 + int retval;
4491 +
4492 + pr_debug("initializing FOTG2XX-SOC USB Controller\n");
4493 +
4494 + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
4495 + if (!res) {
4496 + dev_err(&pdev->dev,
4497 + "Found HC with no IRQ. Check %s setup!\n",
4498 + dev_name(&pdev->dev));
4499 + return -ENODEV;
4500 + }
4501 +
4502 + irq = res->start;
4503 +
4504 + hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
4505 + if (!hcd) {
4506 + retval = -ENOMEM;
4507 + goto err1;
4508 + }
4509 +
4510 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4511 + if (!res) {
4512 + dev_err(&pdev->dev,
4513 + "Found HC with no register addr. Check %s setup!\n",
4514 + dev_name(&pdev->dev));
4515 + retval = -ENODEV;
4516 + goto err2;
4517 + }
4518 +
4519 + hcd->rsrc_start = res->start;
4520 + hcd->rsrc_len = res->end - res->start + 1;
4521 + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
4522 + driver->description)) {
4523 + dev_dbg(&pdev->dev, "controller already in use\n");
4524 + retval = -EBUSY;
4525 + goto err2;
4526 + }
4527 +
4528 + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
4529 + if (hcd->regs == NULL) {
4530 + dev_dbg(&pdev->dev, "error mapping memory\n");
4531 + retval = -EFAULT;
4532 + goto err3;
4533 + }
4534 +
4535 +
4536 + /* set global reg to mini-A host */
4537 + writel(readl(IO_ADDRESS(0x40000000) + 0x30) & ~(BIT(30)|BIT(29)),
4538 + IO_ADDRESS(0x40000000) + 0x30);
4539 +
4540 + /* USB0&USB1 - VBUS off */
4541 + writel(readl(IO_ADDRESS(0x40000000) + 0x30) & ~(BIT(21)|BIT(22)),
4542 + IO_ADDRESS(0x40000000) + 0x30);
4543 +
4544 + if ((readl(hcd->regs) == 0x01000010) &&
4545 + (readl(hcd->regs + 4) == 0x00000001) &&
4546 + (readl(hcd->regs + 8) == 0x00000006)) {
4547 + dev_info(&pdev->dev,
4548 + "Found Faraday OTG 2XX controller (base = 0x%08lX)\n",
4549 + (unsigned long) hcd->rsrc_start);
4550 + } else {
4551 + dev_err(&pdev->dev, "fotg2xx id mismatch: found %d.%d.%d\n",
4552 + readl(hcd->regs + 0x00),
4553 + readl(hcd->regs + 0x04),
4554 + readl(hcd->regs + 0x08));
4555 + retval = -ENODEV;
4556 + goto err4;
4557 + }
4558 +
4559 + platform_set_drvdata(pdev, hcd);
4560 +
4561 + /* mask interrupts - peripheral, otg, host, hi-active (bits 0,1,2,3) */
4562 + otg_set(0xc4, BIT(3)); /* hi active */
4563 +
4564 + otg_set(0xc4, BIT(2)); /* host */
4565 + otg_set(0xc4, BIT(1)); /* otg */
4566 + otg_set(0xc4, BIT(0)); /* peripheral */
4567 +
4568 + /* register additional interrupt - here we check otg status */
4569 + if ((request_irq(irq, &fotg2xx_ehci_irq, IRQF_SHARED | IRQF_DISABLED,
4570 + hcd->irq_descr, hcd)) != 0) {
4571 + dev_dbg(&pdev->dev, "error requesting irq %d\n", irq);
4572 + retval = -EFAULT;
4573 + goto err4;
4574 + }
4575 +
4576 + retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
4577 + if (retval != 0)
4578 + goto err4;
4579 + return retval;
4580 +
4581 +err4:
4582 + iounmap(hcd->regs);
4583 +err3:
4584 + release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
4585 +err2:
4586 + usb_put_hcd(hcd);
4587 +err1:
4588 + dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
4589 + return retval;
4590 +}
4591 +
4592 +/* may be called without controller electrically present */
4593 +/* may be called with controller, bus, and devices active */
4594 +
4595 +int fotg2xx_ehci_remove(struct platform_device *pdev)
4596 +{
4597 + struct usb_hcd *hcd =
4598 + (struct usb_hcd *)platform_get_drvdata(pdev);
4599 +
4600 + usb_remove_hcd(hcd);
4601 + release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
4602 + iounmap(hcd->regs);
4603 + usb_put_hcd(hcd);
4604 + platform_set_drvdata(pdev, NULL);
4605 +
4606 + return 0;
4607 +}
4608 +
4609 +MODULE_ALIAS("platform:ehci-fotg2xx");
4610 +
4611 +static struct platform_driver fotg2xx_ehci_driver = {
4612 + .probe = fotg2xx_ehci_probe,
4613 + .remove = fotg2xx_ehci_remove,
4614 + .driver = {
4615 + .name = "ehci-fotg2xx",
4616 + },
4617 +};
4618 --- a/drivers/usb/host/ehci.h
4619 +++ b/drivers/usb/host/ehci.h
4620 @@ -541,7 +541,12 @@ static inline unsigned int
4621 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
4622 {
4623 if (ehci_is_TDI(ehci)) {
4624 +#ifdef CONFIG_ARCH_GEMINI
4625 + portsc = readl(ehci_to_hcd(ehci)->regs + 0x80);
4626 + switch ((portsc>>22)&3) {
4627 +#else
4628 switch ((portsc>>26)&3) {
4629 +#endif
4630 case 0:
4631 return 0;
4632 case 1:
4633 --- a/drivers/usb/host/ehci-hcd.c
4634 +++ b/drivers/usb/host/ehci-hcd.c
4635 @@ -192,9 +192,11 @@ static int ehci_halt (struct ehci_hcd *e
4636 if ((temp & STS_HALT) != 0)
4637 return 0;
4638
4639 +#ifndef CONFIG_ARCH_GEMINI
4640 temp = ehci_readl(ehci, &ehci->regs->command);
4641 temp &= ~CMD_RUN;
4642 ehci_writel(ehci, temp, &ehci->regs->command);
4643 +#endif
4644 return handshake (ehci, &ehci->regs->status,
4645 STS_HALT, STS_HALT, 16 * 125);
4646 }
4647 @@ -250,8 +252,8 @@ static int ehci_reset (struct ehci_hcd *
4648 if (retval)
4649 return retval;
4650
4651 - if (ehci_is_TDI(ehci))
4652 - tdi_reset (ehci);
4653 +// if (ehci_is_TDI(ehci))
4654 +// tdi_reset (ehci);
4655
4656 return retval;
4657 }
4658 @@ -381,12 +383,13 @@ static void ehci_silence_controller(stru
4659 {
4660 ehci_halt(ehci);
4661 ehci_turn_off_all_ports(ehci);
4662 -
4663 +#ifndef CONFIG_ARCH_GEMINI
4664 /* make BIOS/etc use companion controller during reboot */
4665 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
4666
4667 /* unblock posted writes */
4668 ehci_readl(ehci, &ehci->regs->configured_flag);
4669 +#endif
4670 }
4671
4672 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
4673 @@ -631,7 +634,9 @@ static int ehci_run (struct usb_hcd *hcd
4674 // Philips, Intel, and maybe others need CMD_RUN before the
4675 // root hub will detect new devices (why?); NEC doesn't
4676 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
4677 +#ifndef CONFIG_ARCH_GEMINI
4678 ehci->command |= CMD_RUN;
4679 +#endif
4680 ehci_writel(ehci, ehci->command, &ehci->regs->command);
4681 dbg_cmd (ehci, "init", ehci->command);
4682
4683 @@ -651,9 +656,11 @@ static int ehci_run (struct usb_hcd *hcd
4684 */
4685 down_write(&ehci_cf_port_reset_rwsem);
4686 hcd->state = HC_STATE_RUNNING;
4687 +#ifndef CONFIG_ARCH_GEMINI
4688 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
4689 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
4690 msleep(5);
4691 +#endif
4692 up_write(&ehci_cf_port_reset_rwsem);
4693
4694 temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
4695 @@ -744,9 +751,10 @@ static irqreturn_t ehci_irq (struct usb_
4696 pcd_status = status;
4697
4698 /* resume root hub? */
4699 +#ifndef CONFIG_ARCH_GEMINI
4700 if (!(cmd & CMD_RUN))
4701 usb_hcd_resume_root_hub(hcd);
4702 -
4703 +#endif
4704 while (i--) {
4705 int pstatus = ehci_readl(ehci,
4706 &ehci->regs->port_status [i]);
4707 @@ -778,7 +786,9 @@ static irqreturn_t ehci_irq (struct usb_
4708 ehci_halt(ehci);
4709 dead:
4710 ehci_reset(ehci);
4711 +#ifndef CONFIG_ARCH_GEMINI
4712 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
4713 +#endif
4714 /* generic layer kills/unlinks all urbs, then
4715 * uses ehci_stop to clean up the rest
4716 */
4717 @@ -1042,6 +1052,11 @@ MODULE_LICENSE ("GPL");
4718 #define PCI_DRIVER ehci_pci_driver
4719 #endif
4720
4721 +#ifdef CONFIG_ARCH_GEMINI
4722 +#include "ehci-fotg2xx.c"
4723 +#define PLATFORM_DRIVER fotg2xx_ehci_driver
4724 +#endif
4725 +
4726 #ifdef CONFIG_USB_EHCI_FSL
4727 #include "ehci-fsl.c"
4728 #define PLATFORM_DRIVER ehci_fsl_driver
4729 --- a/drivers/usb/host/ehci-hub.c
4730 +++ b/drivers/usb/host/ehci-hub.c
4731 @@ -749,6 +749,12 @@ static int ehci_hub_control (
4732 /* see what we found out */
4733 temp = check_reset_complete (ehci, wIndex, status_reg,
4734 ehci_readl(ehci, status_reg));
4735 +#ifdef CONFIG_ARCH_GEMINI
4736 + /* restart schedule */
4737 + ehci_writel(ehci, ehci_readl(ehci, &ehci->regs->command) | CMD_RUN, &ehci->regs->command);
4738 +
4739 +// hcd->state = HC_STATE_RUNNING;
4740 +#endif
4741 }
4742
4743 if (!(temp & (PORT_RESUME|PORT_RESET)))
4744 --- a/drivers/usb/Kconfig
4745 +++ b/drivers/usb/Kconfig
4746 @@ -57,6 +57,7 @@ config USB_ARCH_HAS_EHCI
4747 default y if PPC_83xx
4748 default y if SOC_AU1200
4749 default y if ARCH_IXP4XX
4750 + default y if ARCH_GEMINI
4751 default PCI
4752
4753 # ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface.
4754 --- /dev/null
4755 +++ b/drivers/watchdog/gemini_wdt.c
4756 @@ -0,0 +1,368 @@
4757 +/*
4758 + * Watchdog driver for Cortina Systems Gemini SoC
4759 + *
4760 + * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
4761 + *
4762 + * This program is free software; you can redistribute it and/or modify
4763 + * it under the terms of the GNU General Public License version 2 as
4764 + * published by the Free Software Foundation.
4765 + */
4766 +
4767 +#include <linux/kernel.h>
4768 +#include <linux/init.h>
4769 +#include <linux/io.h>
4770 +#include <linux/fs.h>
4771 +#include <linux/uaccess.h>
4772 +#include <linux/miscdevice.h>
4773 +#include <linux/platform_device.h>
4774 +#include <linux/watchdog.h>
4775 +
4776 +#define GEMINI_WDCOUNTER 0x0
4777 +#define GEMINI_WDLOAD 0x4
4778 +#define GEMINI_WDRESTART 0x8
4779 +
4780 +#define WDRESTART_MAGIC 0x5AB9
4781 +
4782 +#define GEMINI_WDCR 0xC
4783 +
4784 +#define WDCR_CLOCK_5MHZ (1 << 4)
4785 +#define WDCR_SYS_RST (1 << 1)
4786 +#define WDCR_ENABLE (1 << 0)
4787 +
4788 +#define WDT_CLOCK 5000000 /* 5 MHz */
4789 +#define WDT_DEFAULT_TIMEOUT 13
4790 +#define WDT_MAX_TIMEOUT (0xFFFFFFFF / WDT_CLOCK)
4791 +
4792 +/* status bits */
4793 +#define WDT_ACTIVE 0
4794 +#define WDT_OK_TO_CLOSE 1
4795 +
4796 +static unsigned int timeout = WDT_DEFAULT_TIMEOUT;
4797 +static int nowayout = WATCHDOG_NOWAYOUT;
4798 +
4799 +static DEFINE_SPINLOCK(gemini_wdt_lock);
4800 +
4801 +static struct platform_device *gemini_wdt_dev;
4802 +
4803 +struct gemini_wdt_struct {
4804 + struct resource *res;
4805 + struct device *dev;
4806 + void __iomem *base;
4807 + unsigned long status;
4808 +};
4809 +
4810 +static struct watchdog_info gemini_wdt_info = {
4811 + .identity = "Gemini watchdog",
4812 + .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING |
4813 + WDIOF_SETTIMEOUT,
4814 +};
4815 +
4816 +/* Disable the watchdog. */
4817 +static void gemini_wdt_stop(struct gemini_wdt_struct *gemini_wdt)
4818 +{
4819 + spin_lock(&gemini_wdt_lock);
4820 +
4821 + __raw_writel(0, gemini_wdt->base + GEMINI_WDCR);
4822 +
4823 + clear_bit(WDT_ACTIVE, &gemini_wdt->status);
4824 +
4825 + spin_unlock(&gemini_wdt_lock);
4826 +}
4827 +
4828 +/* Service the watchdog */
4829 +static void gemini_wdt_service(struct gemini_wdt_struct *gemini_wdt)
4830 +{
4831 + __raw_writel(WDRESTART_MAGIC, gemini_wdt->base + GEMINI_WDRESTART);
4832 +}
4833 +
4834 +/* Enable and reset the watchdog. */
4835 +static void gemini_wdt_start(struct gemini_wdt_struct *gemini_wdt)
4836 +{
4837 + spin_lock(&gemini_wdt_lock);
4838 +
4839 + __raw_writel(timeout * WDT_CLOCK, gemini_wdt->base + GEMINI_WDLOAD);
4840 +
4841 + gemini_wdt_service(gemini_wdt);
4842 +
4843 + /* set clock before enabling */
4844 + __raw_writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST,
4845 + gemini_wdt->base + GEMINI_WDCR);
4846 +
4847 + __raw_writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST | WDCR_ENABLE,
4848 + gemini_wdt->base + GEMINI_WDCR);
4849 +
4850 + set_bit(WDT_ACTIVE, &gemini_wdt->status);
4851 +
4852 + spin_unlock(&gemini_wdt_lock);
4853 +}
4854 +
4855 +/* Watchdog device is opened, and watchdog starts running. */
4856 +static int gemini_wdt_open(struct inode *inode, struct file *file)
4857 +{
4858 + struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(gemini_wdt_dev);
4859 +
4860 + if (test_bit(WDT_ACTIVE, &gemini_wdt->status))
4861 + return -EBUSY;
4862 +
4863 + file->private_data = gemini_wdt;
4864 +
4865 + gemini_wdt_start(gemini_wdt);
4866 +
4867 + return nonseekable_open(inode, file);
4868 +}
4869 +
4870 +/* Close the watchdog device. */
4871 +static int gemini_wdt_close(struct inode *inode, struct file *file)
4872 +{
4873 + struct gemini_wdt_struct *gemini_wdt = file->private_data;
4874 +
4875 + /* Disable the watchdog if possible */
4876 + if (test_bit(WDT_OK_TO_CLOSE, &gemini_wdt->status))
4877 + gemini_wdt_stop(gemini_wdt);
4878 + else
4879 + dev_warn(gemini_wdt->dev, "Device closed unexpectedly - timer will not stop\n");
4880 +
4881 + return 0;
4882 +}
4883 +
4884 +/* Handle commands from user-space. */
4885 +static int gemini_wdt_ioctl(struct inode *inode, struct file *file,
4886 + unsigned int cmd, unsigned long arg)
4887 +{
4888 + struct gemini_wdt_struct *gemini_wdt = file->private_data;
4889 +
4890 + int value;
4891 +
4892 + switch (cmd) {
4893 + case WDIOC_KEEPALIVE:
4894 + gemini_wdt_service(gemini_wdt);
4895 + return 0;
4896 +
4897 + case WDIOC_GETSUPPORT:
4898 + return copy_to_user((struct watchdog_info *)arg, &gemini_wdt_info,
4899 + sizeof(gemini_wdt_info)) ? -EFAULT : 0;
4900 +
4901 + case WDIOC_SETTIMEOUT:
4902 + if (get_user(value, (int *)arg))
4903 + return -EFAULT;
4904 +
4905 + if ((value < 1) || (value > WDT_MAX_TIMEOUT))
4906 + return -EINVAL;
4907 +
4908 + timeout = value;
4909 +
4910 + /* restart wdt to use new timeout */
4911 + gemini_wdt_stop(gemini_wdt);
4912 + gemini_wdt_start(gemini_wdt);
4913 +
4914 + /* Fall through */
4915 + case WDIOC_GETTIMEOUT:
4916 + return put_user(timeout, (int *)arg);
4917 +
4918 + case WDIOC_GETTIMELEFT:
4919 + value = __raw_readl(gemini_wdt->base + GEMINI_WDCOUNTER);
4920 + return put_user(value / WDT_CLOCK, (int *)arg);
4921 +
4922 + default:
4923 + return -ENOTTY;
4924 + }
4925 +}
4926 +
4927 +/* Refresh the watchdog whenever device is written to. */
4928 +static ssize_t gemini_wdt_write(struct file *file, const char *data,
4929 + size_t len, loff_t *ppos)
4930 +{
4931 + struct gemini_wdt_struct *gemini_wdt = file->private_data;
4932 +
4933 + if (len) {
4934 + if (!nowayout) {
4935 + size_t i;
4936 +
4937 + clear_bit(WDT_OK_TO_CLOSE, &gemini_wdt->status);
4938 + for (i = 0; i != len; i++) {
4939 + char c;
4940 +
4941 + if (get_user(c, data + i))
4942 + return -EFAULT;
4943 + if (c == 'V')
4944 + set_bit(WDT_OK_TO_CLOSE,
4945 + &gemini_wdt->status);
4946 + }
4947 + }
4948 + gemini_wdt_service(gemini_wdt);
4949 + }
4950 +
4951 + return len;
4952 +}
4953 +
4954 +static const struct file_operations gemini_wdt_fops = {
4955 + .owner = THIS_MODULE,
4956 + .llseek = no_llseek,
4957 + .ioctl = gemini_wdt_ioctl,
4958 + .open = gemini_wdt_open,
4959 + .release = gemini_wdt_close,
4960 + .write = gemini_wdt_write,
4961 +};
4962 +
4963 +static struct miscdevice gemini_wdt_miscdev = {
4964 + .minor = WATCHDOG_MINOR,
4965 + .name = "watchdog",
4966 + .fops = &gemini_wdt_fops,
4967 +};
4968 +
4969 +static void gemini_wdt_shutdown(struct platform_device *pdev)
4970 +{
4971 + struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
4972 +
4973 + gemini_wdt_stop(gemini_wdt);
4974 +}
4975 +
4976 +static int __init gemini_wdt_probe(struct platform_device *pdev)
4977 +{
4978 + int ret;
4979 + int res_size;
4980 + struct resource *res;
4981 + void __iomem *base;
4982 + struct gemini_wdt_struct *gemini_wdt;
4983 +
4984 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4985 + if (!res) {
4986 + dev_err(&pdev->dev, "can't get device resources\n");
4987 + return -ENODEV;
4988 + }
4989 +
4990 + res_size = resource_size(res);
4991 + if (!request_mem_region(res->start, res_size, res->name)) {
4992 + dev_err(&pdev->dev, "can't allocate %d bytes at %d address\n",
4993 + res_size, res->start);
4994 + return -ENOMEM;
4995 + }
4996 +
4997 + base = ioremap(res->start, res_size);
4998 + if (!base) {
4999 + dev_err(&pdev->dev, "ioremap failed\n");
5000 + ret = -EIO;
5001 + goto fail0;
5002 + }
5003 +
5004 + gemini_wdt = kzalloc(sizeof(struct gemini_wdt_struct), GFP_KERNEL);
5005 + if (!gemini_wdt) {
5006 + dev_err(&pdev->dev, "can't allocate interface\n");
5007 + ret = -ENOMEM;
5008 + goto fail1;
5009 + }
5010 +
5011 + /* Setup gemini_wdt driver structure */
5012 + gemini_wdt->base = base;
5013 + gemini_wdt->res = res;
5014 +
5015 + /* Set up platform driver data */
5016 + platform_set_drvdata(pdev, gemini_wdt);
5017 + gemini_wdt_dev = pdev;
5018 +
5019 + if (gemini_wdt_miscdev.parent) {
5020 + ret = -EBUSY;
5021 + goto fail2;
5022 + }
5023 +
5024 + gemini_wdt_miscdev.parent = &pdev->dev;
5025 +
5026 + ret = misc_register(&gemini_wdt_miscdev);
5027 + if (ret)
5028 + goto fail2;
5029 +
5030 + return 0;
5031 +
5032 +fail2:
5033 + platform_set_drvdata(pdev, NULL);
5034 + kfree(gemini_wdt);
5035 +fail1:
5036 + iounmap(base);
5037 +fail0:
5038 + release_mem_region(res->start, res_size);
5039 +
5040 + return ret;
5041 +}
5042 +
5043 +static int __exit gemini_wdt_remove(struct platform_device *pdev)
5044 +{
5045 + struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
5046 +
5047 + platform_set_drvdata(pdev, NULL);
5048 + misc_deregister(&gemini_wdt_miscdev);
5049 + gemini_wdt_dev = NULL;
5050 + iounmap(gemini_wdt->base);
5051 + release_mem_region(gemini_wdt->res->start, resource_size(gemini_wdt->res));
5052 +
5053 + kfree(gemini_wdt);
5054 +
5055 + return 0;
5056 +}
5057 +
5058 +#ifdef CONFIG_PM
5059 +static int gemini_wdt_suspend(struct platform_device *pdev, pm_message_t message)
5060 +{
5061 + struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
5062 + unsigned int reg;
5063 +
5064 + reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR);
5065 + reg &= ~(WDCR_WDENABLE);
5066 + __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR);
5067 +
5068 + return 0;
5069 +}
5070 +
5071 +static int gemini_wdt_resume(struct platform_device *pdev)
5072 +{
5073 + struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
5074 + unsigned int reg;
5075 +
5076 + if (gemini_wdt->status) {
5077 + reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR);
5078 + reg |= WDCR_WDENABLE;
5079 + __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR);
5080 + }
5081 +
5082 + return 0;
5083 +}
5084 +#else
5085 +#define gemini_wdt_suspend NULL
5086 +#define gemini_wdt_resume NULL
5087 +#endif
5088 +
5089 +static struct platform_driver gemini_wdt_driver = {
5090 + .probe = gemini_wdt_probe,
5091 + .remove = __exit_p(gemini_wdt_remove),
5092 + .shutdown = gemini_wdt_shutdown,
5093 + .suspend = gemini_wdt_suspend,
5094 + .resume = gemini_wdt_resume,
5095 + .driver = {
5096 + .name = "gemini-wdt",
5097 + .owner = THIS_MODULE,
5098 + },
5099 +};
5100 +
5101 +static int __init gemini_wdt_init(void)
5102 +{
5103 + return platform_driver_probe(&gemini_wdt_driver, gemini_wdt_probe);
5104 +}
5105 +
5106 +static void __exit gemini_wdt_exit(void)
5107 +{
5108 + platform_driver_unregister(&gemini_wdt_driver);
5109 +}
5110 +
5111 +module_init(gemini_wdt_init);
5112 +module_exit(gemini_wdt_exit);
5113 +
5114 +module_param(timeout, uint, 0);
5115 +MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds");
5116 +
5117 +module_param(nowayout, int, 0);
5118 +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
5119 +
5120 +MODULE_AUTHOR("Paulius Zaleckas");
5121 +MODULE_DESCRIPTION("Watchdog driver for Gemini");
5122 +MODULE_LICENSE("GPL");
5123 +MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
5124 +MODULE_ALIAS("platform:gemini-wdt");
5125 --- a/drivers/watchdog/Kconfig
5126 +++ b/drivers/watchdog/Kconfig
5127 @@ -104,6 +104,16 @@ config 977_WATCHDOG
5128
5129 Not sure? It's safe to say N.
5130
5131 +config GEMINI_WATCHDOG
5132 + tristate "Gemini watchdog"
5133 + depends on ARCH_GEMINI
5134 + help
5135 + Say Y here if to include support for the watchdog timer
5136 + embedded in the Cortina Systems Gemini family of devices.
5137 +
5138 + To compile this driver as a module, choose M here: the
5139 + module will be called gemini_wdt.
5140 +
5141 config IXP2000_WATCHDOG
5142 tristate "IXP2000 Watchdog"
5143 depends on ARCH_IXP2000
5144 --- a/drivers/watchdog/Makefile
5145 +++ b/drivers/watchdog/Makefile
5146 @@ -30,6 +30,7 @@ obj-$(CONFIG_AT91SAM9X_WATCHDOG) += at91
5147 obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
5148 obj-$(CONFIG_21285_WATCHDOG) += wdt285.o
5149 obj-$(CONFIG_977_WATCHDOG) += wdt977.o
5150 +obj-$(CONFIG_GEMINI_WATCHDOG) += gemini_wdt.o
5151 obj-$(CONFIG_IXP2000_WATCHDOG) += ixp2000_wdt.o
5152 obj-$(CONFIG_IXP4XX_WATCHDOG) += ixp4xx_wdt.o
5153 obj-$(CONFIG_KS8695_WATCHDOG) += ks8695_wdt.o
5154 --- a/include/linux/usb/ehci_def.h
5155 +++ b/include/linux/usb/ehci_def.h
5156 @@ -91,9 +91,9 @@ struct ehci_regs {
5157 u32 frame_list; /* points to periodic list */
5158 /* ASYNCLISTADDR: offset 0x18 */
5159 u32 async_next; /* address of next async queue head */
5160 -
5161 +#ifndef CONFIG_ARCH_GEMINI
5162 u32 reserved [9];
5163 -
5164 +#endif
5165 /* CONFIGFLAG: offset 0x40 */
5166 u32 configured_flag;
5167 #define FLAG_CF (1<<0) /* true: we'll support "high speed" */
Personal OpenWRT clone
This page took 0.251605 seconds and 5 git commands to generate.