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ppc40x: move perwe fixup into a separate function
[openwrt.git] / target / linux / ppc40x / patches / 005-openrb.patch
1 --- /dev/null
2 +++ b/arch/powerpc/boot/cuboot-openrb.c
3 @@ -0,0 +1,77 @@
4 +/*
5 + * Old U-boot compatibility for OpenRB boards
6 + *
7 + * Author: Gabor Juhos <juhosg@openwrt.org>
8 + * Imre Kaloz <kaloz@openwrt.org>
9 + *
10 + * This program is free software; you can redistribute it and/or modify it
11 + * under the terms of the GNU General Public License version 2 as published
12 + * by the Free Software Foundation.
13 + */
14 +
15 +#include "ops.h"
16 +#include "io.h"
17 +#include "dcr.h"
18 +#include "stdio.h"
19 +#include "4xx.h"
20 +#include "44x.h"
21 +#include "cuboot.h"
22 +
23 +#define TARGET_4xx
24 +#define TARGET_405EP
25 +#include "ppcboot.h"
26 +
27 +static bd_t bd;
28 +
29 +static void fixup_perwe(void)
30 +{
31 +#define DCRN_CPC0_PCI_BASE 0xf9
32 +
33 + /* Turn on PerWE instead of PCIINT */
34 + mtdcr(DCRN_CPC0_PCI_BASE,
35 + mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27));
36 +
37 +#undef DCRN_CPC0_PCI_BASE
38 +}
39 +
40 +static void fixup_cf_card(void)
41 +{
42 +#define CF_CS0_BASE 0xff100000
43 +#define CF_CS1_BASE 0xff200000
44 +
45 + /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
46 + mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
47 + mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
48 + mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
49 + mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
50 +
51 + /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
52 + mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
53 + mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
54 + mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
55 + mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
56 +
57 +#undef CF_CS0_BASE
58 +#undef CF_CS1_BASE
59 +}
60 +
61 +static void openrb_fixups(void)
62 +{
63 + ibm405ep_fixup_clocks(bd.bi_procfreq / 8);
64 + ibm4xx_sdram_fixup_memsize();
65 +
66 + fixup_perwe();
67 + fixup_cf_card();
68 +
69 + dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
70 +}
71 +
72 +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
73 + unsigned long r6, unsigned long r7)
74 +{
75 + CUBOOT_INIT();
76 + platform_ops.fixups = openrb_fixups;
77 + platform_ops.exit = ibm40x_dbcr_reset;
78 + fdt_init(_dtb_start);
79 + serial_console_init();
80 +}
81 --- /dev/null
82 +++ b/arch/powerpc/boot/dts/openrb.dts
83 @@ -0,0 +1,280 @@
84 +/*
85 + * Device Tree Source for OpenRB boards
86 + *
87 + * Copyright 2009 Gabor Juhos <juhosg@openwrt.org>
88 + * Copyright 2009 Imre Kaloz <kaloz@openwrt.org>
89 + *
90 + * Based on walnut.dts
91 + *
92 + * This file is licensed under the terms of the GNU General Public
93 + * License version 2. This program is licensed "as is" without
94 + * any warranty of any kind, whether express or implied.
95 + */
96 +
97 +/dts-v1/;
98 +
99 +/ {
100 + #address-cells = <1>;
101 + #size-cells = <1>;
102 + model = "openrb";
103 + compatible = "openrb";
104 + dcr-parent = <&{/cpus/cpu@0}>;
105 +
106 + aliases {
107 + ethernet0 = &EMAC0;
108 + ethernet1 = &EMAC1;
109 + serial0 = &UART0;
110 + serial1 = &UART1;
111 + };
112 +
113 + cpus {
114 + #address-cells = <1>;
115 + #size-cells = <0>;
116 +
117 + cpu@0 {
118 + device_type = "cpu";
119 + model = "PowerPC,405EP";
120 + reg = <0x00000000>;
121 + clock-frequency = <0>; /* Filled in by zImage */
122 + timebase-frequency = <0>; /* Filled in by zImage */
123 + i-cache-line-size = <0x20>;
124 + d-cache-line-size = <0x20>;
125 + i-cache-size = <0x4000>;
126 + d-cache-size = <0x4000>;
127 + dcr-controller;
128 + dcr-access-method = "native";
129 + };
130 + };
131 +
132 + memory {
133 + device_type = "memory";
134 + reg = <0x00000000 0x00000000>; /* Filled in by zImage */
135 + };
136 +
137 + UIC0: interrupt-controller {
138 + compatible = "ibm,uic";
139 + interrupt-controller;
140 + cell-index = <0>;
141 + dcr-reg = <0x0c0 0x009>;
142 + #address-cells = <0>;
143 + #size-cells = <0>;
144 + #interrupt-cells = <2>;
145 + };
146 +
147 + plb {
148 + compatible = "ibm,plb3";
149 + #address-cells = <1>;
150 + #size-cells = <1>;
151 + ranges;
152 + clock-frequency = <0>; /* Filled in by zImage */
153 +
154 + SDRAM0: memory-controller {
155 + compatible = "ibm,sdram-405ep";
156 + dcr-reg = <0x010 0x002>;
157 + };
158 +
159 + MAL: mcmal {
160 + compatible = "ibm,mcmal-405ep", "ibm,mcmal";
161 + dcr-reg = <0x180 0x062>;
162 + num-tx-chans = <4>;
163 + num-rx-chans = <2>;
164 + interrupt-parent = <&UIC0>;
165 + interrupts = <
166 + 0xb 0x4 /* TXEOB */
167 + 0xc 0x4 /* RXEOB */
168 + 0xa 0x4 /* SERR */
169 + 0xd 0x4 /* TXDE */
170 + 0xe 0x4 /* RXDE */>;
171 + };
172 +
173 + POB0: opb {
174 + compatible = "ibm,opb-405ep", "ibm,opb";
175 + #address-cells = <1>;
176 + #size-cells = <1>;
177 + ranges = <0xef600000 0xef600000 0x00a00000>;
178 + dcr-reg = <0x0a0 0x005>;
179 + clock-frequency = <0>; /* Filled in by zImage */
180 +
181 + UART0: serial@ef600300 {
182 + device_type = "serial";
183 + compatible = "ns16550";
184 + reg = <0xef600300 0x00000008>;
185 + virtual-reg = <0xef600300>;
186 + clock-frequency = <0>; /* Filled in by zImage */
187 + current-speed = <115200>;
188 + interrupt-parent = <&UIC0>;
189 + interrupts = <0x0 0x4>;
190 + };
191 +
192 + UART1: serial@ef600400 {
193 + device_type = "serial";
194 + compatible = "ns16550";
195 + reg = <0xef600400 0x00000008>;
196 + virtual-reg = <0xef600400>;
197 + clock-frequency = <0>; /* Filled in by zImage */
198 + current-speed = <115200>;
199 + interrupt-parent = <&UIC0>;
200 + interrupts = <0x1 0x4>;
201 + };
202 +
203 + IIC: i2c@ef600500 {
204 + compatible = "ibm,iic-405ep", "ibm,iic";
205 + #address-cells = <1>;
206 + #size-cells = <0>;
207 + reg = <0xef600500 0x00000011>;
208 + interrupt-parent = <&UIC0>;
209 + interrupts = <0x2 0x4>;
210 +
211 + eeprom@50 {
212 + compatible = "at24,24c16";
213 + reg = <0x50>;
214 + };
215 + };
216 +
217 + GPIO0: gpio-controller@ef600700 {
218 + compatible = "ibm,ppc4xx-gpio";
219 + reg = <0xef600700 0x00000020>;
220 + #gpio-cells = <2>;
221 + gpio-controller;
222 + };
223 +
224 + EMAC0: ethernet@ef600800 {
225 + linux,network-index = <0x0>;
226 + device_type = "network";
227 + compatible = "ibm,emac-405ep", "ibm,emac";
228 + interrupt-parent = <&UIC0>;
229 + interrupts = <
230 + 0xf 0x4 /* Ethernet */
231 + 0x9 0x4 /* Ethernet Wake Up */>;
232 + local-mac-address = [000000000000]; /* Filled in by zImage */
233 + reg = <0xef600800 0x00000070>;
234 + mal-device = <&MAL>;
235 + mal-tx-channel = <0>;
236 + mal-rx-channel = <0>;
237 + cell-index = <0>;
238 + max-frame-size = <0x5dc>;
239 + rx-fifo-size = <0x1000>;
240 + tx-fifo-size = <0x800>;
241 + phy-mode = "mii";
242 + phy-map = <0x00000000>;
243 + };
244 +
245 + EMAC1: ethernet@ef600900 {
246 + linux,network-index = <0x1>;
247 + device_type = "network";
248 + compatible = "ibm,emac-405ep", "ibm,emac";
249 + interrupt-parent = <&UIC0>;
250 + interrupts = <
251 + 0x11 0x4 /* Ethernet */
252 + 0x09 0x4 /* Ethernet Wake Up */>;
253 + local-mac-address = [000000000000]; /* Filled in by zImage */
254 + reg = <0xef600900 0x00000070>;
255 + mal-device = <&MAL>;
256 + mal-tx-channel = <2>;
257 + mal-rx-channel = <1>;
258 + cell-index = <1>;
259 + max-frame-size = <0x5dc>;
260 + rx-fifo-size = <0x1000>;
261 + tx-fifo-size = <0x800>;
262 + mdio-device = <&EMAC0>;
263 + phy-mode = "mii";
264 + phy-map = <0x00000001>;
265 + };
266 +
267 + leds {
268 + compatible = "gpio-leds";
269 + user {
270 + label = "openrb:green:user";
271 + gpios = <&GPIO0 2 1>;
272 + };
273 + };
274 + };
275 +
276 + EBC0: ebc {
277 + compatible = "ibm,ebc-405ep", "ibm,ebc";
278 + dcr-reg = <0x012 0x002>;
279 + #address-cells = <2>;
280 + #size-cells = <1>;
281 + /* The ranges property is supplied by the bootwrapper
282 + * and is based on the firmware's configuration of the
283 + * EBC bridge
284 + */
285 + clock-frequency = <0>; /* Filled in by zImage */
286 +
287 + cf_card@ff100000 {
288 + compatible = "magicbox-cf", "pata-magicbox-cf";
289 + reg = <0x00000000 0xff100000 0x00001000
290 + 0x00000000 0xff200000 0x00001000>;
291 + interrupt-parent = <&UIC0>;
292 + interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >;
293 + };
294 +
295 + nor_flash@ff800000 {
296 + compatible = "cfi-flash";
297 + bank-width = <2>;
298 + reg = <0x00000000 0xff800000 0x00800000>;
299 + #address-cells = <1>;
300 + #size-cells = <1>;
301 + partition0@0 {
302 + label = "linux";
303 + reg = <0x0 0x140000>;
304 + };
305 + partition1@120000 {
306 + label = "rootfs";
307 + reg = <0x140000 0x680000>;
308 + };
309 + partition2@7c0000 {
310 + label = "u-boot";
311 + reg = <0x7c0000 0x30000>;
312 + read-only;
313 + };
314 + partition3@0 {
315 + label = "firmware";
316 + reg = <0x0 0x7c0000>;
317 + };
318 + };
319 + };
320 +
321 + PCI0: pci@ec000000 {
322 + device_type = "pci";
323 + #interrupt-cells = <1>;
324 + #size-cells = <2>;
325 + #address-cells = <3>;
326 + compatible = "ibm,plb405ep-pci", "ibm,plb-pci";
327 + primary;
328 + reg = <0xeec00000 0x00000008 /* Config space access */
329 + 0xeed80000 0x00000004 /* IACK */
330 + 0xeed80000 0x00000004 /* Special cycle */
331 + 0xef480000 0x00000040>; /* Internal registers */
332 +
333 + /* Outbound ranges, one memory and one IO,
334 + * later cannot be changed. Chip supports a second
335 + * IO range but we don't use it for now
336 + */
337 + ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
338 + 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
339 +
340 + /* Inbound 2GB range starting at 0 */
341 + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
342 +
343 + interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
344 + interrupt-map = <
345 + /* IDSEL 1 */
346 + 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
347 +
348 + /* IDSEL 2 */
349 + 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8
350 +
351 + /* IDSEL 3 */
352 + 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8
353 +
354 + /* IDSEL 4 */
355 + 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8
356 + >;
357 + };
358 + };
359 +
360 + chosen {
361 + linux,stdout-path = "/plb/opb/serial@ef600300";
362 + };
363 +};
364 --- a/arch/powerpc/boot/Makefile
365 +++ b/arch/powerpc/boot/Makefile
366 @@ -44,6 +44,7 @@ $(obj)/cuboot-taishan.o: BOOTCFLAGS += -
367 $(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=440
368 $(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
369 $(obj)/cuboot-magicbox.o: BOOTCFLAGS += -mcpu=405
370 +$(obj)/cuboot-openrb.o: BOOTCFLAGS += -mcpu=405
371 $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
372 $(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
373
374 @@ -78,7 +79,7 @@ src-plat := of.c cuboot-52xx.c cuboot-82
375 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
376 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
377 cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \
378 - cuboot-magicbox.c
379 + cuboot-magicbox.c cuboot-openrb.c
380 src-boot := $(src-wlib) $(src-plat) empty.c
381
382 src-boot := $(addprefix $(obj)/, $(src-boot))
383 @@ -197,6 +198,7 @@ image-$(CONFIG_HOTFOOT) += cuImage.hot
384 image-$(CONFIG_WALNUT) += treeImage.walnut
385 image-$(CONFIG_ACADIA) += cuImage.acadia
386 image-$(CONFIG_MAGICBOX) += cuImage.magicbox
387 +image-$(CONFIG_OPENRB) += cuImage.openrb
388
389 # Board ports in arch/powerpc/platform/44x/Kconfig
390 image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
391 --- a/arch/powerpc/platforms/40x/Kconfig
392 +++ b/arch/powerpc/platforms/40x/Kconfig
393 @@ -70,6 +70,16 @@ config MAGICBOX
394 help
395 This option enables support for the Magicbox boards.
396
397 +config OPENRB
398 + bool "OpenRB"
399 + depends on 40x
400 + default n
401 + select PPC40x_SIMPLE
402 + select 405EP
403 + select PCI
404 + help
405 + This option enables support for the OpenRB boards.
406 +
407 config MAKALU
408 bool "Makalu"
409 depends on 40x
410 --- a/arch/powerpc/platforms/40x/ppc40x_simple.c
411 +++ b/arch/powerpc/platforms/40x/ppc40x_simple.c
412 @@ -56,7 +56,8 @@ static char *board[] __initdata = {
413 "amcc,kilauea",
414 "amcc,makalu",
415 "est,hotfoot",
416 - "magicbox"
417 + "magicbox",
418 + "openrb"
419 };
420
421 static int __init ppc40x_probe(void)
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