target/linux/ramips/files/arch/mips/ralink/rt3883/clock.c

   1 /*
   2  *  Ralink RT3662/RT3883 clock API
   3  *
   4  *  Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms of the GNU General Public License version 2 as published
   8  *  by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/err.h>
  15 #include <linux/clk.h>
  16
  17 #include <asm/mach-ralink/common.h>
  18 #include <asm/mach-ralink/rt3883.h>
  19 #include <asm/mach-ralink/rt3883_regs.h>
  20 #include "common.h"
  21
  22 struct clk {
  23         unsigned long rate;
  24 };
  25
  26 static struct clk rt3883_cpu_clk;
  27 static struct clk rt3883_sys_clk;
  28 static struct clk rt3883_wdt_clk;
  29 static struct clk rt3883_uart_clk;
  30
  31 void __init rt3883_clocks_init(void)
  32 {
  33         u32 syscfg0;
  34         u32 clksel;
  35         u32 ddr2;
  36
  37         syscfg0 = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG0);
  38         clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
  39                   RT3883_SYSCFG0_CPUCLK_MASK);
  40         ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
  41
  42         switch (clksel) {
  43         case RT3883_SYSCFG0_CPUCLK_250:
  44                 rt3883_cpu_clk.rate = 250000000;
  45                 rt3883_sys_clk.rate = (ddr2) ? 125000000 : 83000000;
  46                 break;
  47         case RT3883_SYSCFG0_CPUCLK_384:
  48                 rt3883_cpu_clk.rate = 384000000;
  49                 rt3883_sys_clk.rate = (ddr2) ? 128000000 : 96000000;
  50                 break;
  51         case RT3883_SYSCFG0_CPUCLK_480:
  52                 rt3883_cpu_clk.rate = 480000000;
  53                 rt3883_sys_clk.rate = (ddr2) ? 160000000 : 120000000;
  54                 break;
  55         case RT3883_SYSCFG0_CPUCLK_500:
  56                 rt3883_cpu_clk.rate = 500000000;
  57                 rt3883_sys_clk.rate = (ddr2) ? 166000000 : 125000000;
  58                 break;
  59         }
  60
  61         rt3883_wdt_clk.rate = rt3883_sys_clk.rate;
  62         rt3883_uart_clk.rate = 40000000;
  63 }
  64
  65 struct clk *clk_get(struct device *dev, const char *id)
  66 {
  67         if (!strcmp(id, "sys"))
  68                 return &rt3883_sys_clk;
  69
  70         if (!strcmp(id, "cpu"))
  71                 return &rt3883_cpu_clk;
  72
  73         if (!strcmp(id, "wdt"))
  74                 return &rt3883_wdt_clk;
  75
  76         if (!strcmp(id, "uart"))
  77                 return &rt3883_uart_clk;
  78
  79         return ERR_PTR(-ENOENT);
  80 }
  81 EXPORT_SYMBOL(clk_get);
  82
  83 int clk_enable(struct clk *clk)
  84 {
  85         return 0;
  86 }
  87 EXPORT_SYMBOL(clk_enable);
  88
  89 void clk_disable(struct clk *clk)
  90 {
  91 }
  92 EXPORT_SYMBOL(clk_disable);
  93
  94 unsigned long clk_get_rate(struct clk *clk)
  95 {
  96         return clk->rate;
  97 }
  98 EXPORT_SYMBOL(clk_get_rate);
  99
 100 void clk_put(struct clk *clk)
 101 {
 102 }
 103 EXPORT_SYMBOL(clk_put);