2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/etherdevice.h>
18 #include <linux/platform_device.h>
19 #include <linux/serial_8250.h>
21 #include <asm/mach-ar71xx/ar71xx.h>
25 static u8 ar71xx_mac_base
[ETH_ALEN
] __initdata
;
27 static struct resource ar71xx_uart_resources
[] = {
29 .start
= AR71XX_UART_BASE
,
30 .end
= AR71XX_UART_BASE
+ AR71XX_UART_SIZE
- 1,
31 .flags
= IORESOURCE_MEM
,
35 #define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
36 static struct plat_serial8250_port ar71xx_uart_data
[] = {
38 .mapbase
= AR71XX_UART_BASE
,
39 .irq
= AR71XX_MISC_IRQ_UART
,
40 .flags
= AR71XX_UART_FLAGS
,
44 /* terminating entry */
48 static struct platform_device ar71xx_uart_device
= {
50 .id
= PLAT8250_DEV_PLATFORM
,
51 .resource
= ar71xx_uart_resources
,
52 .num_resources
= ARRAY_SIZE(ar71xx_uart_resources
),
54 .platform_data
= ar71xx_uart_data
58 void __init
ar71xx_add_device_uart(void)
60 ar71xx_uart_data
[0].uartclk
= ar71xx_ahb_freq
;
61 platform_device_register(&ar71xx_uart_device
);
64 static struct resource ar71xx_mdio_resources
[] = {
67 .flags
= IORESOURCE_MEM
,
68 .start
= AR71XX_GE0_BASE
,
69 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
73 static struct ag71xx_mdio_platform_data ar71xx_mdio_data
;
75 static struct platform_device ar71xx_mdio_device
= {
76 .name
= "ag71xx-mdio",
78 .resource
= ar71xx_mdio_resources
,
79 .num_resources
= ARRAY_SIZE(ar71xx_mdio_resources
),
81 .platform_data
= &ar71xx_mdio_data
,
85 void __init
ar71xx_add_device_mdio(u32 phy_mask
)
87 if (ar71xx_soc
== AR71XX_SOC_AR7240
)
88 ar71xx_mdio_data
.is_ar7240
= 1;
90 ar71xx_mdio_data
.phy_mask
= phy_mask
;
92 platform_device_register(&ar71xx_mdio_device
);
95 static void ar71xx_set_pll(u32 cfg_reg
, u32 pll_reg
, u32 pll_val
, u32 shift
)
100 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
102 t
= __raw_readl(base
+ cfg_reg
);
105 __raw_writel(t
, base
+ cfg_reg
);
108 __raw_writel(pll_val
, base
+ pll_reg
);
111 __raw_writel(t
, base
+ cfg_reg
);
115 __raw_writel(t
, base
+ cfg_reg
);
118 printk(KERN_DEBUG
"ar71xx: pll_reg %#x: %#x\n",
119 (unsigned int)(base
+ pll_reg
), __raw_readl(base
+ pll_reg
));
124 struct ar71xx_eth_pll_data ar71xx_eth0_pll_data
;
125 struct ar71xx_eth_pll_data ar71xx_eth1_pll_data
;
127 static u32
ar71xx_get_eth_pll(unsigned int mac
, int speed
)
129 struct ar71xx_eth_pll_data
*pll_data
;
134 pll_data
= &ar71xx_eth0_pll_data
;
137 pll_data
= &ar71xx_eth1_pll_data
;
145 pll_val
= pll_data
->pll_10
;
148 pll_val
= pll_data
->pll_100
;
151 pll_val
= pll_data
->pll_1000
;
160 static void ar71xx_set_pll_ge0(int speed
)
162 u32 val
= ar71xx_get_eth_pll(0, speed
);
164 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH0_INT_CLOCK
,
165 val
, AR71XX_ETH0_PLL_SHIFT
);
168 static void ar71xx_set_pll_ge1(int speed
)
170 u32 val
= ar71xx_get_eth_pll(1, speed
);
172 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH1_INT_CLOCK
,
173 val
, AR71XX_ETH1_PLL_SHIFT
);
176 static void ar724x_set_pll_ge0(int speed
)
181 static void ar724x_set_pll_ge1(int speed
)
186 static void ar91xx_set_pll_ge0(int speed
)
188 u32 val
= ar71xx_get_eth_pll(0, speed
);
190 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG
, AR91XX_PLL_REG_ETH0_INT_CLOCK
,
191 val
, AR91XX_ETH0_PLL_SHIFT
);
194 static void ar91xx_set_pll_ge1(int speed
)
196 u32 val
= ar71xx_get_eth_pll(1, speed
);
198 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG
, AR91XX_PLL_REG_ETH1_INT_CLOCK
,
199 val
, AR91XX_ETH1_PLL_SHIFT
);
202 static void ar71xx_ddr_flush_ge0(void)
204 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0
);
207 static void ar71xx_ddr_flush_ge1(void)
209 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1
);
212 static void ar724x_ddr_flush_ge0(void)
214 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0
);
217 static void ar724x_ddr_flush_ge1(void)
219 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1
);
222 static void ar91xx_ddr_flush_ge0(void)
224 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0
);
227 static void ar91xx_ddr_flush_ge1(void)
229 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1
);
232 static struct resource ar71xx_eth0_resources
[] = {
235 .flags
= IORESOURCE_MEM
,
236 .start
= AR71XX_GE0_BASE
,
237 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
240 .flags
= IORESOURCE_MEM
,
241 .start
= AR71XX_MII_BASE
+ MII_REG_MII0_CTRL
,
242 .end
= AR71XX_MII_BASE
+ MII_REG_MII0_CTRL
+ 3,
245 .flags
= IORESOURCE_IRQ
,
246 .start
= AR71XX_CPU_IRQ_GE0
,
247 .end
= AR71XX_CPU_IRQ_GE0
,
251 struct ag71xx_platform_data ar71xx_eth0_data
= {
252 .reset_bit
= RESET_MODULE_GE0_MAC
,
255 static struct platform_device ar71xx_eth0_device
= {
258 .resource
= ar71xx_eth0_resources
,
259 .num_resources
= ARRAY_SIZE(ar71xx_eth0_resources
),
261 .platform_data
= &ar71xx_eth0_data
,
265 static struct resource ar71xx_eth1_resources
[] = {
268 .flags
= IORESOURCE_MEM
,
269 .start
= AR71XX_GE1_BASE
,
270 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
273 .flags
= IORESOURCE_MEM
,
274 .start
= AR71XX_MII_BASE
+ MII_REG_MII1_CTRL
,
275 .end
= AR71XX_MII_BASE
+ MII_REG_MII1_CTRL
+ 3,
278 .flags
= IORESOURCE_IRQ
,
279 .start
= AR71XX_CPU_IRQ_GE1
,
280 .end
= AR71XX_CPU_IRQ_GE1
,
284 struct ag71xx_platform_data ar71xx_eth1_data
= {
285 .reset_bit
= RESET_MODULE_GE1_MAC
,
288 static struct platform_device ar71xx_eth1_device
= {
291 .resource
= ar71xx_eth1_resources
,
292 .num_resources
= ARRAY_SIZE(ar71xx_eth1_resources
),
294 .platform_data
= &ar71xx_eth1_data
,
298 #define AR71XX_PLL_VAL_1000 0x00110000
299 #define AR71XX_PLL_VAL_100 0x00001099
300 #define AR71XX_PLL_VAL_10 0x00991099
302 #define AR724X_PLL_VAL_1000 0x00110000
303 #define AR724X_PLL_VAL_100 0x00001099
304 #define AR724X_PLL_VAL_10 0x00991099
306 #define AR91XX_PLL_VAL_1000 0x1a000000
307 #define AR91XX_PLL_VAL_100 0x13000a44
308 #define AR91XX_PLL_VAL_10 0x00441099
310 static void __init
ar71xx_init_eth_pll_data(unsigned int id
)
312 struct ar71xx_eth_pll_data
*pll_data
;
313 u32 pll_10
, pll_100
, pll_1000
;
317 pll_data
= &ar71xx_eth0_pll_data
;
320 pll_data
= &ar71xx_eth1_pll_data
;
326 switch (ar71xx_soc
) {
327 case AR71XX_SOC_AR7130
:
328 case AR71XX_SOC_AR7141
:
329 case AR71XX_SOC_AR7161
:
330 pll_10
= AR71XX_PLL_VAL_10
;
331 pll_100
= AR71XX_PLL_VAL_100
;
332 pll_1000
= AR71XX_PLL_VAL_1000
;
335 case AR71XX_SOC_AR7240
:
336 pll_10
= AR724X_PLL_VAL_10
;
337 pll_100
= AR724X_PLL_VAL_100
;
338 pll_1000
= AR724X_PLL_VAL_1000
;
341 case AR71XX_SOC_AR9130
:
342 case AR71XX_SOC_AR9132
:
343 pll_10
= AR91XX_PLL_VAL_10
;
344 pll_100
= AR91XX_PLL_VAL_100
;
345 pll_1000
= AR91XX_PLL_VAL_1000
;
351 if (!pll_data
->pll_10
)
352 pll_data
->pll_10
= pll_10
;
354 if (!pll_data
->pll_100
)
355 pll_data
->pll_100
= pll_100
;
357 if (!pll_data
->pll_1000
)
358 pll_data
->pll_1000
= pll_1000
;
361 static int ar71xx_eth_instance __initdata
;
362 void __init
ar71xx_add_device_eth(unsigned int id
)
364 struct platform_device
*pdev
;
365 struct ag71xx_platform_data
*pdata
;
367 ar71xx_init_eth_pll_data(id
);
371 switch (ar71xx_eth0_data
.phy_if_mode
) {
372 case PHY_INTERFACE_MODE_MII
:
373 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_MII
;
375 case PHY_INTERFACE_MODE_GMII
:
376 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_GMII
;
378 case PHY_INTERFACE_MODE_RGMII
:
379 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_RGMII
;
381 case PHY_INTERFACE_MODE_RMII
:
382 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_RMII
;
385 printk(KERN_ERR
"ar71xx: invalid PHY interface mode "
389 pdev
= &ar71xx_eth0_device
;
392 switch (ar71xx_eth1_data
.phy_if_mode
) {
393 case PHY_INTERFACE_MODE_RMII
:
394 ar71xx_eth1_data
.mii_if
= MII1_CTRL_IF_RMII
;
396 case PHY_INTERFACE_MODE_RGMII
:
397 ar71xx_eth1_data
.mii_if
= MII1_CTRL_IF_RGMII
;
400 printk(KERN_ERR
"ar71xx: invalid PHY interface mode "
404 pdev
= &ar71xx_eth1_device
;
407 printk(KERN_ERR
"ar71xx: invalid ethernet id %d\n", id
);
411 pdata
= pdev
->dev
.platform_data
;
413 switch (ar71xx_soc
) {
414 case AR71XX_SOC_AR7130
:
415 pdata
->ddr_flush
= id
? ar71xx_ddr_flush_ge1
416 : ar71xx_ddr_flush_ge0
;
417 pdata
->set_pll
= id
? ar71xx_set_pll_ge1
418 : ar71xx_set_pll_ge0
;
421 case AR71XX_SOC_AR7141
:
422 case AR71XX_SOC_AR7161
:
423 pdata
->ddr_flush
= id
? ar71xx_ddr_flush_ge1
424 : ar71xx_ddr_flush_ge0
;
425 pdata
->set_pll
= id
? ar71xx_set_pll_ge1
426 : ar71xx_set_pll_ge0
;
430 case AR71XX_SOC_AR7240
:
431 pdata
->ddr_flush
= id
? ar724x_ddr_flush_ge1
432 : ar724x_ddr_flush_ge0
;
433 pdata
->set_pll
= id
? ar724x_set_pll_ge1
434 : ar724x_set_pll_ge0
;
435 pdata
->is_ar724x
= 1;
438 case AR71XX_SOC_AR9130
:
439 pdata
->ddr_flush
= id
? ar91xx_ddr_flush_ge1
440 : ar91xx_ddr_flush_ge0
;
441 pdata
->set_pll
= id
? ar91xx_set_pll_ge1
442 : ar91xx_set_pll_ge0
;
443 pdata
->is_ar91xx
= 1;
446 case AR71XX_SOC_AR9132
:
447 pdata
->ddr_flush
= id
? ar91xx_ddr_flush_ge1
448 : ar91xx_ddr_flush_ge0
;
449 pdata
->set_pll
= id
? ar91xx_set_pll_ge1
450 : ar91xx_set_pll_ge0
;
451 pdata
->is_ar91xx
= 1;
459 switch (pdata
->phy_if_mode
) {
460 case PHY_INTERFACE_MODE_GMII
:
461 case PHY_INTERFACE_MODE_RGMII
:
462 if (!pdata
->has_gbit
) {
463 printk(KERN_ERR
"ar71xx: no gbit available on eth%d\n",
472 if (is_valid_ether_addr(ar71xx_mac_base
)) {
473 memcpy(pdata
->mac_addr
, ar71xx_mac_base
, ETH_ALEN
);
474 pdata
->mac_addr
[5] += ar71xx_eth_instance
;
476 random_ether_addr(pdata
->mac_addr
);
478 "ar71xx: using random MAC address for eth%d\n",
479 ar71xx_eth_instance
);
482 if (pdata
->mii_bus_dev
== NULL
)
483 pdata
->mii_bus_dev
= &ar71xx_mdio_device
.dev
;
485 /* Reset the device */
486 ar71xx_device_stop(pdata
->reset_bit
);
489 ar71xx_device_start(pdata
->reset_bit
);
492 platform_device_register(pdev
);
493 ar71xx_eth_instance
++;
496 static struct resource ar71xx_spi_resources
[] = {
498 .start
= AR71XX_SPI_BASE
,
499 .end
= AR71XX_SPI_BASE
+ AR71XX_SPI_SIZE
- 1,
500 .flags
= IORESOURCE_MEM
,
504 static struct platform_device ar71xx_spi_device
= {
505 .name
= "ar71xx-spi",
507 .resource
= ar71xx_spi_resources
,
508 .num_resources
= ARRAY_SIZE(ar71xx_spi_resources
),
511 void __init
ar71xx_add_device_spi(struct ar71xx_spi_platform_data
*pdata
,
512 struct spi_board_info
const *info
,
515 spi_register_board_info(info
, n
);
516 ar71xx_spi_device
.dev
.platform_data
= pdata
;
517 platform_device_register(&ar71xx_spi_device
);
520 void __init
ar71xx_add_device_wdt(void)
522 platform_device_register_simple("ar71xx-wdt", -1, NULL
, 0);
525 void __init
ar71xx_set_mac_base(unsigned char *mac
)
527 memcpy(ar71xx_mac_base
, mac
, ETH_ALEN
);
530 void __init
ar71xx_parse_mac_addr(char *mac_str
)
535 t
= sscanf(mac_str
, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
536 &tmp
[0], &tmp
[1], &tmp
[2], &tmp
[3], &tmp
[4], &tmp
[5]);
539 t
= sscanf(mac_str
, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
540 &tmp
[0], &tmp
[1], &tmp
[2], &tmp
[3], &tmp
[4], &tmp
[5]);
543 ar71xx_set_mac_base(tmp
);
545 printk(KERN_DEBUG
"ar71xx: failed to parse mac address "
546 "\"%s\"\n", mac_str
);
549 static struct platform_device ar71xx_dsa_switch_device
= {
554 void __init
ar71xx_add_device_dsa(unsigned int id
,
555 struct dsa_platform_data
*d
)
561 d
->netdev
= &ar71xx_eth0_device
.dev
;
564 d
->netdev
= &ar71xx_eth1_device
.dev
;
568 "ar71xx: invalid ethernet id %d for DSA switch\n",
573 for (i
= 0; i
< d
->nr_chips
; i
++)
574 d
->chip
[i
].mii_bus
= &ar71xx_mdio_device
.dev
;
576 ar71xx_dsa_switch_device
.dev
.platform_data
= d
;
578 platform_device_register(&ar71xx_dsa_switch_device
);