package/fonera-mp3-drv/src/ar531x.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright © 2003 Atheros Communications, Inc.,  All Rights Reserved.
   7  */
   8
   9 #ifndef AR531X_H
  10 #define AR531X_H 1
  11
  12
  13 #ifndef CONFIG_AR531X_COBRA
  14
  15 #include <asm/addrspace.h>
  16
  17 /* Address Map */
  18 #define AR531X_WLAN0            0x18000000
  19 #define AR531X_WLAN1            0x18500000
  20 #define AR531X_ENET0            0x18100000
  21 #define AR531X_ENET1            0x18200000
  22 #define AR531X_SDRAMCTL         0x18300000
  23 #define AR531X_FLASHCTL         0x18400000
  24 #define AR531X_APBBASE          0x1c000000
  25 #define AR531X_FLASH            0x1e000000
  26
  27 /*
  28  * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that
  29  * should be considered available.  The AR5312 supports 2 enet MACS,
  30  * even though many reference boards only actually use 1 of them
  31  * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
  32  * The AR2312 supports 1 enet MAC.
  33  */
  34 #define AR531X_NUM_ENET_MAC             2
  35
  36 /*
  37  * Need these defines to determine true number of ethernet MACs
  38  */
  39 #define AR5212_AR5312_REV2      0x0052          /* AR5312 WMAC (AP31) */
  40 #define AR5212_AR5312_REV7      0x0057          /* AR5312 WMAC (AP30-040) */
  41 #define AR5212_AR2313_REV8      0x0058          /* AR2313 WMAC (AP43-030) */
  42 #define AR531X_RADIO_MASK_OFF  0xc8
  43 #define AR531X_RADIO0_MASK     0x0003
  44 #define AR531X_RADIO1_MASK     0x000c
  45 #define AR531X_RADIO1_S        2
  46
  47 /*
  48  * AR531X_NUM_WMAC defines the number of Wireless MACs that\
  49  * should be considered available.
  50  */
  51 #define AR531X_NUM_WMAC                 2
  52
  53 /* Reset/Timer Block Address Map */
  54 #define AR531X_RESETTMR         (AR531X_APBBASE  + 0x3000)
  55 #define AR531X_TIMER            (AR531X_RESETTMR + 0x0000) /* countdown timer */
  56 #define AR531X_WD_CTRL          (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
  57 #define AR531X_WD_TIMER         (AR531X_RESETTMR + 0x000c) /* watchdog timer */
  58 #define AR531X_ISR              (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */
  59 #define AR531X_IMR              (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */
  60 #define AR531X_RESET            (AR531X_RESETTMR + 0x0020)
  61 #define AR5312_CLOCKCTL1        (AR531X_RESETTMR + 0x0064)
  62 #define AR5312_SCRATCH          (AR531X_RESETTMR + 0x006c)
  63 #define AR531X_PROCADDR         (AR531X_RESETTMR + 0x0070)
  64 #define AR531X_PROC1            (AR531X_RESETTMR + 0x0074)
  65 #define AR531X_DMAADDR          (AR531X_RESETTMR + 0x0078)
  66 #define AR531X_DMA1             (AR531X_RESETTMR + 0x007c)
  67 #define AR531X_ENABLE           (AR531X_RESETTMR + 0x0080) /* interface enb */
  68 #define AR531X_REV              (AR531X_RESETTMR + 0x0090) /* revision */
  69
  70 /* AR531X_WD_CTRL register bit field definitions */
  71 #define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000
  72 #define AR531X_WD_CTRL_NMI               0x0001
  73 #define AR531X_WD_CTRL_RESET             0x0002
  74
  75 /* AR531X_ISR register bit field definitions */
  76 #define AR531X_ISR_NONE         0x0000
  77 #define AR531X_ISR_TIMER        0x0001
  78 #define AR531X_ISR_AHBPROC      0x0002
  79 #define AR531X_ISR_AHBDMA       0x0004
  80 #define AR531X_ISR_GPIO         0x0008
  81 #define AR531X_ISR_UART0        0x0010
  82 #define AR531X_ISR_UART0DMA     0x0020
  83 #define AR531X_ISR_WD           0x0040
  84 #define AR531X_ISR_LOCAL        0x0080
  85
  86 /* AR531X_RESET register bit field definitions */
  87 #define AR531X_RESET_SYSTEM     0x00000001  /* cold reset full system */
  88 #define AR531X_RESET_PROC       0x00000002  /* cold reset MIPS core */
  89 #define AR531X_RESET_WLAN0      0x00000004  /* cold reset WLAN MAC and BB */
  90 #define AR531X_RESET_EPHY0      0x00000008  /* cold reset ENET0 phy */
  91 #define AR531X_RESET_EPHY1      0x00000010  /* cold reset ENET1 phy */
  92 #define AR531X_RESET_ENET0      0x00000020  /* cold reset ENET0 mac */
  93 #define AR531X_RESET_ENET1      0x00000040  /* cold reset ENET1 mac */
  94 #define AR531X_RESET_UART0      0x00000100  /* cold reset UART0 (high speed) */
  95 #define AR531X_RESET_WLAN1      0x00000200  /* cold reset WLAN MAC/BB */
  96 #define AR531X_RESET_APB        0x00000400  /* cold reset APB (ar5312) */
  97 #define AR531X_RESET_WARM_PROC  0x00001000  /* warm reset MIPS core */
  98 #define AR531X_RESET_WARM_WLAN0_MAC 0x00002000  /* warm reset WLAN0 MAC */
  99 #define AR531X_RESET_WARM_WLAN0_BB  0x00004000  /* warm reset WLAN0 BaseBand */
 100 #define AR531X_RESET_NMI        0x00010000  /* send an NMI to the processor */
 101 #define AR531X_RESET_WARM_WLAN1_MAC 0x00020000  /* warm reset WLAN1 mac */
 102 #define AR531X_RESET_WARM_WLAN1_BB  0x00040000  /* warm reset WLAN1 baseband */
 103 #define AR531X_RESET_LOCAL_BUS  0x00080000  /* reset local bus */
 104 #define AR531X_RESET_WDOG       0x00100000  /* last reset was a watchdog */
 105
 106 #define AR531X_RESET_WMAC0_BITS \
 107         AR531X_RESET_WLAN0 |\
 108         AR531X_RESET_WARM_WLAN0_MAC |\
 109         AR531X_RESET_WARM_WLAN0_BB
 110
 111 #define AR531X_RESERT_WMAC1_BITS \
 112         AR531X_RESET_WLAN1 |\
 113         AR531X_RESET_WARM_WLAN1_MAC |\
 114         AR531X_RESET_WARM_WLAN1_BB
 115
 116 /* AR5312_CLOCKCTL1 register bit field definitions */
 117 #define AR5312_CLOCKCTL1_PREDIVIDE_MASK    0x00000030
 118 #define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT            4
 119 #define AR5312_CLOCKCTL1_MULTIPLIER_MASK   0x00001f00
 120 #define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT           8
 121 #define AR5312_CLOCKCTL1_DOUBLER_MASK      0x00010000
 122
 123 /* Valid for AR5312 and AR2312 */
 124 #define AR5312_CLOCKCTL1_PREDIVIDE_MASK    0x00000030
 125 #define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT            4
 126 #define AR5312_CLOCKCTL1_MULTIPLIER_MASK   0x00001f00
 127 #define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT           8
 128 #define AR5312_CLOCKCTL1_DOUBLER_MASK      0x00010000
 129
 130 /* Valid for AR2313 */
 131 #define AR2313_CLOCKCTL1_PREDIVIDE_MASK    0x00003000
 132 #define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT           12
 133 #define AR2313_CLOCKCTL1_MULTIPLIER_MASK   0x001f0000
 134 #define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT          16
 135 #define AR2313_CLOCKCTL1_DOUBLER_MASK      0x00000000
 136
 137
 138 /* AR531X_ENABLE register bit field definitions */
 139 #define AR531X_ENABLE_WLAN0              0x0001
 140 #define AR531X_ENABLE_ENET0              0x0002
 141 #define AR531X_ENABLE_ENET1              0x0004
 142 #define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008   /* UART, and WLAN1 PIOs */
 143 #define AR531X_ENABLE_WLAN1_DMA          0x0010   /* WLAN1 DMAs */
 144 #define AR531X_ENABLE_WLAN1 \
 145             (AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA)
 146
 147 /* AR531X_REV register bit field definitions */
 148 #define AR531X_REV_WMAC_MAJ    0xf000
 149 #define AR531X_REV_WMAC_MAJ_S  12
 150 #define AR531X_REV_WMAC_MIN    0x0f00
 151 #define AR531X_REV_WMAC_MIN_S  8
 152 #define AR531X_REV_MAJ         0x00f0
 153 #define AR531X_REV_MAJ_S       4
 154 #define AR531X_REV_MIN         0x000f
 155 #define AR531X_REV_MIN_S       0
 156 #define AR531X_REV_CHIP        (REV_MAJ|REV_MIN)
 157
 158 /* Major revision numbers, bits 7..4 of Revision ID register */
 159 #define AR531X_REV_MAJ_AR5312          0x4
 160 #define AR531X_REV_MAJ_AR2313          0x5
 161
 162 /* Minor revision numbers, bits 3..0 of Revision ID register */
 163 #define AR5312_REV_MIN_DUAL     0x0     /* Dual WLAN version */
 164 #define AR5312_REV_MIN_SINGLE   0x1     /* Single WLAN version */
 165
 166 /* AR531X_FLASHCTL register bit field definitions */
 167 #define FLASHCTL_IDCY   0x0000000f      /* Idle cycle turn around time */
 168 #define FLASHCTL_IDCY_S 0
 169 #define FLASHCTL_WST1   0x000003e0      /* Wait state 1 */
 170 #define FLASHCTL_WST1_S 5
 171 #define FLASHCTL_RBLE   0x00000400      /* Read byte lane enable */
 172 #define FLASHCTL_WST2   0x0000f800      /* Wait state 2 */
 173 #define FLASHCTL_WST2_S 11
 174 #define FLASHCTL_AC     0x00070000      /* Flash address check (added) */
 175 #define FLASHCTL_AC_S   16
 176 #define FLASHCTL_AC_128K 0x00000000
 177 #define FLASHCTL_AC_256K 0x00010000
 178 #define FLASHCTL_AC_512K 0x00020000
 179 #define FLASHCTL_AC_1M   0x00030000
 180 #define FLASHCTL_AC_2M   0x00040000
 181 #define FLASHCTL_AC_4M   0x00050000
 182 #define FLASHCTL_AC_8M   0x00060000
 183 #define FLASHCTL_AC_RES  0x00070000     /* 16MB is not supported */
 184 #define FLASHCTL_E      0x00080000      /* Flash bank enable (added) */
 185 #define FLASHCTL_BUSERR 0x01000000      /* Bus transfer error status flag */
 186 #define FLASHCTL_WPERR  0x02000000      /* Write protect error status flag */
 187 #define FLASHCTL_WP     0x04000000      /* Write protect */
 188 #define FLASHCTL_BM     0x08000000      /* Burst mode */
 189 #define FLASHCTL_MW     0x30000000      /* Memory width */
 190 #define FLASHCTL_MWx8   0x00000000      /* Memory width x8 */
 191 #define FLASHCTL_MWx16  0x10000000      /* Memory width x16 */
 192 #define FLASHCTL_MWx32  0x20000000      /* Memory width x32 (not supported) */
 193 #define FLASHCTL_ATNR   0x00000000      /* Access type == no retry */
 194 #define FLASHCTL_ATR    0x80000000      /* Access type == retry every */
 195 #define FLASHCTL_ATR4   0xc0000000      /* Access type == retry every 4 */
 196
 197 /* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices.  */
 198 #define AR531X_FLASHCTL0        (AR531X_FLASHCTL + 0x00)
 199 #define AR531X_FLASHCTL1        (AR531X_FLASHCTL + 0x04)
 200 #define AR531X_FLASHCTL2        (AR531X_FLASHCTL + 0x08)
 201
 202 /* ARM SDRAM Controller -- just enough to determine memory size */
 203 #define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04)
 204 #define MEM_CFG1_AC0    0x00000700      /* bank 0: SDRAM addr check (added) */
 205 #define MEM_CFG1_AC0_S  8
 206 #define MEM_CFG1_AC1    0x00007000      /* bank 1: SDRAM addr check (added) */
 207 #define MEM_CFG1_AC1_S  12
 208
 209 /* GPIO Address Map */
 210 #define AR531X_GPIO         (AR531X_APBBASE  + 0x2000)
 211 #define AR531X_GPIO_DO      (AR531X_GPIO + 0x00)        /* output register */
 212 #define AR531X_GPIO_DI      (AR531X_GPIO + 0x04)        /* intput register */
 213 #define AR531X_GPIO_CR      (AR531X_GPIO + 0x08)        /* control register */
 214
 215 /* GPIO Control Register bit field definitions */
 216 #define GPIO_CR_M(x)    (1 << (x))                      /* mask for i/o */
 217 #define GPIO_CR_O(x)    (0 << (x))                      /* mask for output */
 218 #define GPIO_CR_I(x)    (1 << (x))                      /* mask for input */
 219 #define GPIO_CR_INT(x)  (1 << ((x)+8))                  /* mask for interrupt */
 220 #define GPIO_CR_UART(x) (1 << ((x)+16))                 /* uart multiplex */
 221
 222
 223 typedef unsigned int AR531X_REG;
 224
 225 #define sysRegRead(phys)        \
 226         (*(volatile AR531X_REG *)PHYS_TO_K1(phys))
 227
 228 #define sysRegWrite(phys, val)  \
 229         ((*(volatile AR531X_REG *)PHYS_TO_K1(phys)) = (val))
 230
 231
 232 /*
 233  * This is board-specific data that is stored in a "fixed" location in flash.
 234  * It is shared across operating systems, so it should not be changed lightly.
 235  * The main reason we need it is in order to extract the ethernet MAC
 236  * address(es).
 237  */
 238 struct ar531x_boarddata {
 239     u32 magic;                       /* board data is valid */
 240 #define AR531X_BD_MAGIC 0x35333131   /* "5311", for all 531x platforms */
 241     u16 cksum;                       /* checksum (starting with BD_REV 2) */
 242     u16 rev;                         /* revision of this struct */
 243 #define BD_REV  4
 244     char   boardName[64];            /* Name of board */
 245     u16 major;                       /* Board major number */
 246     u16 minor;                       /* Board minor number */
 247     u32 config;                      /* Board configuration */
 248 #define BD_ENET0        0x00000001   /* ENET0 is stuffed */
 249 #define BD_ENET1        0x00000002   /* ENET1 is stuffed */
 250 #define BD_UART1        0x00000004   /* UART1 is stuffed */
 251 #define BD_UART0        0x00000008   /* UART0 is stuffed (dma) */
 252 #define BD_RSTFACTORY   0x00000010   /* Reset factory defaults stuffed */
 253 #define BD_SYSLED       0x00000020   /* System LED stuffed */
 254 #define BD_EXTUARTCLK   0x00000040   /* External UART clock */
 255 #define BD_CPUFREQ      0x00000080   /* cpu freq is valid in nvram */
 256 #define BD_SYSFREQ      0x00000100   /* sys freq is set in nvram */
 257 #define BD_WLAN0        0x00000200   /* Enable WLAN0 */
 258 #define BD_MEMCAP       0x00000400   /* CAP SDRAM @ memCap for testing */
 259 #define BD_DISWATCHDOG  0x00000800   /* disable system watchdog */
 260 #define BD_WLAN1        0x00001000   /* Enable WLAN1 (ar5212) */
 261 #define BD_ISCASPER     0x00002000   /* FLAG for AR2312 */
 262 #define BD_WLAN0_2G_EN  0x00004000   /* FLAG for radio0_2G */
 263 #define BD_WLAN0_5G_EN  0x00008000   /* FLAG for radio0_2G */
 264 #define BD_WLAN1_2G_EN  0x00020000   /* FLAG for radio0_2G */
 265 #define BD_WLAN1_5G_EN  0x00040000   /* FLAG for radio0_2G */
 266     u16 resetConfigGpio;             /* Reset factory GPIO pin */
 267     u16 sysLedGpio;                  /* System LED GPIO pin */
 268
 269     u32 cpuFreq;                     /* CPU core frequency in Hz */
 270     u32 sysFreq;                     /* System frequency in Hz */
 271     u32 cntFreq;                     /* Calculated C0_COUNT frequency */
 272
 273     u8  wlan0Mac[6];
 274     u8  enet0Mac[6];
 275     u8  enet1Mac[6];
 276
 277     u16 pciId;                       /* Pseudo PCIID for common code */
 278     u16 memCap;                      /* cap bank1 in MB */
 279
 280     /* version 3 */
 281     u8  wlan1Mac[6];                 /* (ar5212) */
 282 };
 283
 284 #else
 285
 286 /*
 287  * Add support for Cobra
 288  *
 289  * AR531XPLUSreg.h Register definitions for Atheros AR5311 and AR5312 chipsets.
 290  *   - WLAN registers are listed in
 291  *         hal/ar5211/ar5211Reg.h
 292  *         hal/ar5212/ar5212Reg.h
 293  *   - Ethernet registers are listed in ar531xenet.h
 294  *   - Standard UART is 16550 compatible.
 295  */
 296
 297
 298 /*
 299  * Address map
 300  */
 301 #define AR531XPLUS_SDRAM0           0x00000000      /* DRAM */
 302 #define AR531XPLUS_SPI_READ         0x08000000      /* SPI FLASH */
 303 #define AR531XPLUS_WLAN0            0xB0000000      /* Wireless MMR */
 304 #define AR531XPLUS_PCI              0xB0100000      /* PCI MMR */
 305 #define AR531XPLUS_SDRAMCTL         0xB0300000      /* SDRAM MMR */
 306 #define AR531XPLUS_LOCAL            0xB0400000      /* LOCAL BUS MMR */
 307 #define AR531XPLUS_ENET0            0xB0500000      /* ETHERNET MMR */
 308 #define AR531XPLUS_DSLBASE          0xB1000000      /* RESET CONTROL MMR */
 309 #define AR531XPLUS_UART0            0xB1100003      /* UART MMR */
 310 #define AR531XPLUS_SPI              0xB1300000      /* SPI FLASH MMR */
 311 #define AR531XPLUS_FLASHBT          0xBfc00000      /* ro boot alias to FLASH */
 312 #define AR531XPLUS_RAM1             0x40000000      /* ram alias */
 313 #define AR531XPLUS_PCIEXT           0x80000000      /* pci external */
 314 #define AR531XPLUS_RAM2             0xc0000000      /* ram alias */
 315 #define AR531XPLUS_RAM3             0xe0000000      /* ram alias */
 316
 317 #define AR531X_ENET0  AR531XPLUS_ENET0
 318 #define AR531X_ENET1  0
 319 /*
 320  * Reset Register
 321  */
 322 #define AR531XPLUS_COLD_RESET       (AR531XPLUS_DSLBASE + 0x0000)
 323
 324 /* Cold Reset */
 325 #define RESET_COLD_AHB              0x00000001
 326 #define RESET_COLD_APB              0x00000002
 327 #define RESET_COLD_CPU              0x00000004
 328 #define RESET_COLD_CPUWARM          0x00000008
 329 #define RESET_SYSTEM                (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB)      /* full system */
 330
 331 /* Warm Reset */
 332
 333 #define AR531XPLUS_RESET            (AR531XPLUS_DSLBASE + 0x0004)
 334 #define AR531X_RESET AR531XPLUS_RESET
 335
 336 #define RESET_WARM_WLAN0_MAC        0x00000001      /* warm reset WLAN0 MAC */
 337 #define RESET_WARM_WLAN0_BB         0x00000002      /* warm reset WLAN0 BaseBand */
 338 #define RESET_MPEGTS_RSVD           0x00000004      /* warm reset MPEG-TS */
 339 #define RESET_PCIDMA                0x00000008      /* warm reset PCI ahb/dma */
 340 #define RESET_MEMCTL                0x00000010      /* warm reset memory controller */
 341 #define RESET_LOCAL                 0x00000020      /* warm reset local bus */
 342 #define RESET_I2C_RSVD              0x00000040      /* warm reset I2C bus */
 343 #define RESET_SPI                   0x00000080      /* warm reset SPI interface */
 344 #define RESET_UART0                 0x00000100      /* warm reset UART0 */
 345 #define RESET_IR_RSVD               0x00000200      /* warm reset IR interface */
 346 #define RESET_EPHY0                 0x00000400      /* cold reset ENET0 phy */
 347 #define RESET_ENET0                 0x00000800      /* cold reset ENET0 mac */
 348
 349 #define AR531X_RESET_ENET0 RESET_ENET0
 350 #define AR531X_RESET_EPHY0 RESET_EPHY0
 351 #define AR531X_RESET_ENET1 0
 352 #define AR531X_RESET_EPHY1 0
 353
 354 /*
 355  * AHB master arbitration control
 356  */
 357 #define AR531XPLUS_AHB_ARB_CTL      (AR531XPLUS_DSLBASE + 0x0008)
 358
 359 #define ARB_CPU                     0x00000001      /* CPU, default */
 360 #define ARB_WLAN                    0x00000002      /* WLAN */
 361 #define ARB_MPEGTS_RSVD             0x00000004      /* MPEG-TS */
 362 #define ARB_LOCAL                   0x00000008      /* LOCAL */
 363 #define ARB_PCI                     0x00000010      /* PCI */
 364 #define ARB_ETHERNET                0x00000020      /* Ethernet */
 365 #define ARB_RETRY                   0x00000100      /* retry policy, debug only */
 366
 367 /*
 368  * Config Register
 369  */
 370 #define AR531XPLUS_ENDIAN_CTL       (AR531XPLUS_DSLBASE + 0x000c)
 371
 372 #define CONFIG_AHB                  0x00000001      /* EC - AHB bridge endianess */
 373 #define CONFIG_WLAN                 0x00000002      /* WLAN byteswap */
 374 #define CONFIG_MPEGTS_RSVD          0x00000004      /* MPEG-TS byteswap */
 375 #define CONFIG_PCI                  0x00000008      /* PCI byteswap */
 376 #define CONFIG_MEMCTL               0x00000010      /* Memory controller endianess */
 377 #define CONFIG_LOCAL                0x00000020      /* Local bus byteswap */
 378 #define CONFIG_ETHERNET             0x00000040      /* Ethernet byteswap */
 379
 380 #define CONFIG_MERGE                0x00000200      /* CPU write buffer merge */
 381 #define CONFIG_CPU                  0x00000400      /* CPU big endian */
 382 #define CONFIG_PCIAHB               0x00000800
 383 #define CONFIG_PCIAHB_BRIDGE        0x00001000
 384 #define CONFIG_SPI                  0x00008000      /* SPI byteswap */
 385 #define CONFIG_CPU_DRAM             0x00010000
 386 #define CONFIG_CPU_PCI              0x00020000
 387 #define CONFIG_CPU_MMR              0x00040000
 388 #define CONFIG_BIG                  0x00000400
 389
 390
 391 /*
 392  * NMI control
 393  */
 394 #define AR531XPLUS_NMI_CTL          (AR531XPLUS_DSLBASE + 0x0010)
 395
 396 #define NMI_EN  1
 397
 398 /*
 399  * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0).
 400  */
 401 #define AR531XPLUS_SREV             (AR531XPLUS_DSLBASE + 0x0014)
 402
 403 #define AR531X_REV  AR531XPLUS_SREV
 404
 405 #define REV_MAJ                     0x00f0
 406 #define REV_MAJ_S                   4
 407 #define REV_MIN                     0x000f
 408 #define REV_MIN_S                   0
 409 #define REV_CHIP                    (REV_MAJ|REV_MIN)
 410
 411 #define AR531X_REV_MAJ REV_MAJ
 412 #define AR531X_REV_MAJ_S REV_MAJ_S
 413 #define AR531X_REV_MIN REV_MIN
 414 #define AR531X_REV_MIN_S REV_MIN_S
 415 #define REV_CHIP                    (REV_MAJ|REV_MIN)
 416 /*
 417  * Need these defines to determine true number of ethernet MACs
 418  */
 419 #define AR5212_AR5312_REV2      0x0052          /* AR5312 WMAC (AP31) */
 420 #define AR5212_AR5312_REV7      0x0057          /* AR5312 WMAC (AP30-040) */
 421 #define AR5212_AR2313_REV8      0x0058          /* AR2313 WMAC (AP43-030) */
 422 #define AR531X_RADIO_MASK_OFF  0xc8
 423 #define AR531X_RADIO0_MASK     0x0003
 424 #define AR531X_RADIO1_MASK     0x000c
 425 #define AR531X_RADIO1_S        2
 426
 427 /* Major revision numbers, bits 7..4 of Revision ID register */
 428 #define AR531X_REV_MAJ_AR5312          0x4
 429 #define AR531X_REV_MAJ_AR2313          0x5
 430
 431 /*
 432  * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that
 433  * should be considered available.  The AR5312 supports 2 enet MACS,
 434  * even though many reference boards only actually use 1 of them
 435  * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
 436  * The AR2312 supports 1 enet MAC.
 437  */
 438 #define AR531X_NUM_ENET_MAC             1
 439
 440 /*
 441  * Interface Enable
 442  */
 443 #define AR531XPLUS_IF_CTL           (AR531XPLUS_DSLBASE + 0x0018)
 444
 445 #define IF_MASK                     0x00000007
 446 #define IF_DISABLED                 0
 447 #define IF_PCI                      1
 448 #define IF_TS_LOCAL                 2
 449 #define IF_ALL                      3   /* only for emulation with separate pins */
 450 #define IF_LOCAL_HOST               0x00000008
 451 #define IF_PCI_HOST                 0x00000010
 452 #define IF_PCI_INTR                 0x00000020
 453 #define IF_PCI_CLK_MASK             0x00030000
 454 #define IF_PCI_CLK_INPUT            0
 455 #define IF_PCI_CLK_OUTPUT_LOW       1
 456 #define IF_PCI_CLK_OUTPUT_CLK       2
 457 #define IF_PCI_CLK_OUTPUT_HIGH      3
 458 #define IF_PCI_CLK_SHIFT            16
 459
 460
 461 /* Major revision numbers, bits 7..4 of Revision ID register */
 462 #define REV_MAJ_AR5311              0x01
 463 #define REV_MAJ_AR5312              0x04
 464 #define REV_MAJ_AR5315              0x0B
 465
 466 /*
 467  * APB Interrupt control
 468  */
 469
 470 #define AR531XPLUS_ISR              (AR531XPLUS_DSLBASE + 0x0020)
 471 #define AR531XPLUS_IMR              (AR531XPLUS_DSLBASE + 0x0024)
 472 #define AR531XPLUS_GISR             (AR531XPLUS_DSLBASE + 0x0028)
 473
 474 #define ISR_UART0                   0x0001           /* high speed UART */
 475 #define ISR_I2C_RSVD                0x0002           /* I2C bus */
 476 #define ISR_SPI                     0x0004           /* SPI bus */
 477 #define ISR_AHB                     0x0008           /* AHB error */
 478 #define ISR_APB                     0x0010           /* APB error */
 479 #define ISR_TIMER                   0x0020           /* timer */
 480 #define ISR_GPIO                    0x0040           /* GPIO */
 481 #define ISR_WD                      0x0080           /* watchdog */
 482 #define ISR_IR_RSVD                 0x0100           /* IR */
 483
 484 #define IMR_UART0                   ISR_UART0
 485 #define IMR_I2C_RSVD                ISR_I2C_RSVD
 486 #define IMR_SPI                     ISR_SPI
 487 #define IMR_AHB                     ISR_AHB
 488 #define IMR_APB                     ISR_APB
 489 #define IMR_TIMER                   ISR_TIMER
 490 #define IMR_GPIO                    ISR_GPIO
 491 #define IMR_WD                      ISR_WD
 492 #define IMR_IR_RSVD                 ISR_IR_RSVD
 493
 494 #define GISR_MISC                   0x0001
 495 #define GISR_WLAN0                  0x0002
 496 #define GISR_MPEGTS_RSVD            0x0004
 497 #define GISR_LOCALPCI               0x0008
 498 #define GISR_WMACPOLL               0x0010
 499 #define GISR_TIMER                  0x0020
 500 #define GISR_ETHERNET               0x0040
 501
 502 /*
 503  * Interrupt routing from IO to the processor IP bits
 504  * Define our inter mask and level
 505  */
 506 #define AR531XPLUS_INTR_MISCIO      SR_IBIT3
 507 #define AR531XPLUS_INTR_WLAN0       SR_IBIT4
 508 #define AR531XPLUS_INTR_ENET0       SR_IBIT5
 509 #define AR531XPLUS_INTR_LOCALPCI    SR_IBIT6
 510 #define AR531XPLUS_INTR_WMACPOLL    SR_IBIT7
 511 #define AR531XPLUS_INTR_COMPARE     SR_IBIT8
 512
 513 /*
 514  * Timers
 515  */
 516 #define AR531XPLUS_TIMER            (AR531XPLUS_DSLBASE + 0x0030)
 517 #define AR531XPLUS_RELOAD           (AR531XPLUS_DSLBASE + 0x0034)
 518 #define AR531XPLUS_WD               (AR531XPLUS_DSLBASE + 0x0038)
 519 #define AR531XPLUS_WDC              (AR531XPLUS_DSLBASE + 0x003c)
 520
 521 #define WDC_RESET                   0x00000002               /* reset on watchdog */
 522 #define WDC_NMI                     0x00000001               /* NMI on watchdog */
 523 #define WDC_IGNORE_EXPIRATION       0x00000000
 524
 525 /*
 526  * Interface Debug
 527  */
 528 #define AR531X_FLASHDBG             (AR531X_RESETTMR + 0x0040)
 529 #define AR531X_MIIDBG               (AR531X_RESETTMR + 0x0044)
 530
 531
 532 /*
 533  * CPU Performance Counters
 534  */
 535 #define AR531XPLUS_PERFCNT0         (AR531XPLUS_DSLBASE + 0x0048)
 536 #define AR531XPLUS_PERFCNT1         (AR531XPLUS_DSLBASE + 0x004c)
 537
 538 #define PERF_DATAHIT                0x0001  /* Count Data Cache Hits */
 539 #define PERF_DATAMISS               0x0002  /* Count Data Cache Misses */
 540 #define PERF_INSTHIT                0x0004  /* Count Instruction Cache Hits */
 541 #define PERF_INSTMISS               0x0008  /* Count Instruction Cache Misses */
 542 #define PERF_ACTIVE                 0x0010  /* Count Active Processor Cycles */
 543 #define PERF_WBHIT                  0x0020  /* Count CPU Write Buffer Hits */
 544 #define PERF_WBMISS                 0x0040  /* Count CPU Write Buffer Misses */
 545
 546 #define PERF_EB_ARDY                0x0001  /* Count EB_ARdy signal */
 547 #define PERF_EB_AVALID              0x0002  /* Count EB_AValid signal */
 548 #define PERF_EB_WDRDY               0x0004  /* Count EB_WDRdy signal */
 549 #define PERF_EB_RDVAL               0x0008  /* Count EB_RdVal signal */
 550 #define PERF_VRADDR                 0x0010  /* Count valid read address cycles */
 551 #define PERF_VWADDR                 0x0020  /* Count valid write address cycles */
 552 #define PERF_VWDATA                 0x0040  /* Count valid write data cycles */
 553
 554 /*
 555  * AHB Error Reporting.
 556  */
 557 #define AR531XPLUS_AHB_ERR0         (AR531XPLUS_DSLBASE + 0x0050)  /* error  */
 558 #define AR531XPLUS_AHB_ERR1         (AR531XPLUS_DSLBASE + 0x0054)  /* haddr  */
 559 #define AR531XPLUS_AHB_ERR2         (AR531XPLUS_DSLBASE + 0x0058)  /* hwdata */
 560 #define AR531XPLUS_AHB_ERR3         (AR531XPLUS_DSLBASE + 0x005c)  /* hrdata */
 561 #define AR531XPLUS_AHB_ERR4         (AR531XPLUS_DSLBASE + 0x0060)  /* status */
 562
 563 #define AHB_ERROR_DET               1   /* AHB Error has been detected,          */
 564                                         /* write 1 to clear all bits in ERR0     */
 565 #define AHB_ERROR_OVR               2   /* AHB Error overflow has been detected  */
 566 #define AHB_ERROR_WDT               4   /* AHB Error due to wdt instead of hresp */
 567
 568 #define PROCERR_HMAST               0x0000000f
 569 #define PROCERR_HMAST_DFLT          0
 570 #define PROCERR_HMAST_WMAC          1
 571 #define PROCERR_HMAST_ENET          2
 572 #define PROCERR_HMAST_PCIENDPT      3
 573 #define PROCERR_HMAST_LOCAL         4
 574 #define PROCERR_HMAST_CPU           5
 575 #define PROCERR_HMAST_PCITGT        6
 576
 577 #define PROCERR_HMAST_S             0
 578 #define PROCERR_HWRITE              0x00000010
 579 #define PROCERR_HSIZE               0x00000060
 580 #define PROCERR_HSIZE_S             5
 581 #define PROCERR_HTRANS              0x00000180
 582 #define PROCERR_HTRANS_S            7
 583 #define PROCERR_HBURST              0x00000e00
 584 #define PROCERR_HBURST_S            9
 585
 586
 587
 588 /*
 589  * Clock Control
 590  */
 591 #define AR531XPLUS_PLLC_CTL         (AR531XPLUS_DSLBASE + 0x0064)
 592 #define AR531XPLUS_PLLV_CTL         (AR531XPLUS_DSLBASE + 0x0068)
 593 #define AR531XPLUS_CPUCLK           (AR531XPLUS_DSLBASE + 0x006c)
 594 #define AR531XPLUS_AMBACLK          (AR531XPLUS_DSLBASE + 0x0070)
 595 #define AR531XPLUS_SYNCCLK          (AR531XPLUS_DSLBASE + 0x0074)
 596 #define AR531XPLUS_DSL_SLEEP_CTL    (AR531XPLUS_DSLBASE + 0x0080)
 597 #define AR531XPLUS_DSL_SLEEP_DUR    (AR531XPLUS_DSLBASE + 0x0084)
 598
 599 /* PLLc Control fields */
 600 #define PLLC_REF_DIV_M              0x00000003
 601 #define PLLC_REF_DIV_S              0
 602 #define PLLC_FDBACK_DIV_M           0x0000007C
 603 #define PLLC_FDBACK_DIV_S           2
 604 #define PLLC_ADD_FDBACK_DIV_M       0x00000080
 605 #define PLLC_ADD_FDBACK_DIV_S       7
 606 #define PLLC_CLKC_DIV_M             0x0001c000
 607 #define PLLC_CLKC_DIV_S             14
 608 #define PLLC_CLKM_DIV_M             0x00700000
 609 #define PLLC_CLKM_DIV_S             20
 610
 611 /* CPU CLK Control fields */
 612 #define CPUCLK_CLK_SEL_M            0x00000003
 613 #define CPUCLK_CLK_SEL_S            0
 614 #define CPUCLK_CLK_DIV_M            0x0000000c
 615 #define CPUCLK_CLK_DIV_S            2
 616
 617 /* AMBA CLK Control fields */
 618 #define AMBACLK_CLK_SEL_M           0x00000003
 619 #define AMBACLK_CLK_SEL_S           0
 620 #define AMBACLK_CLK_DIV_M           0x0000000c
 621 #define AMBACLK_CLK_DIV_S           2
 622
 623 #if defined(COBRA_EMUL)
 624 #define AR531XPLUS_AMBA_CLOCK_RATE  20000000
 625 #define AR531XPLUS_CPU_CLOCK_RATE   40000000
 626 #else
 627 #if defined(DEFAULT_PLL)
 628 #define AR531XPLUS_AMBA_CLOCK_RATE  40000000
 629 #define AR531XPLUS_CPU_CLOCK_RATE   40000000
 630 #else
 631 #define AR531XPLUS_AMBA_CLOCK_RATE  92000000
 632 #define AR531XPLUS_CPU_CLOCK_RATE   184000000
 633 #endif /* ! DEFAULT_PLL */
 634 #endif /* ! COBRA_EMUL */
 635
 636 #define AR531XPLUS_UART_CLOCK_RATE  AR531XPLUS_AMBA_CLOCK_RATE
 637 #define AR531XPLUS_SDRAM_CLOCK_RATE AR531XPLUS_AMBA_CLOCK_RATE
 638
 639 /*
 640  * The UART computes baud rate as:
 641  *   baud = clock / (16 * divisor)
 642  * where divisor is specified as a High Byte (DLM) and a Low Byte (DLL).
 643  */
 644 #define DESIRED_BAUD_RATE           38400
 645
 646 /*
 647  * The WATCHDOG value is computed as
 648  *  10 seconds * AR531X_WATCHDOG_CLOCK_RATE
 649  */
 650 #define DESIRED_WATCHDOG_SECONDS    10
 651 #define AR531X_WATCHDOG_TIME \
 652         (DESIRED_WATCHDOG_SECONDS * AR531X_WATCHDOG_CLOCK_RATE)
 653
 654
 655 #define CLOCKCTL_UART0  0x0010  /* enable UART0 external clock */
 656
 657
 658  /*
 659  * Applicable "PCICFG" bits for WLAN(s).  Assoc status and LED mode.
 660  */
 661 #define AR531X_PCICFG               (AR531X_RESETTMR + 0x00b0)
 662 #define ASSOC_STATUS_M              0x00000003
 663 #define ASSOC_STATUS_NONE           0
 664 #define ASSOC_STATUS_PENDING        1
 665 #define ASSOC_STATUS_ASSOCIATED     2
 666 #define LED_MODE_M                  0x0000001c
 667 #define LED_BLINK_THRESHOLD_M       0x000000e0
 668 #define LED_SLOW_BLINK_MODE         0x00000100
 669
 670 /*
 671  * GPIO
 672  */
 673
 674 #define AR531XPLUS_GPIO_DI          (AR531XPLUS_DSLBASE + 0x0088)
 675 #define AR531XPLUS_GPIO_DO          (AR531XPLUS_DSLBASE + 0x0090)
 676 #define AR531XPLUS_GPIO_CR          (AR531XPLUS_DSLBASE + 0x0098)
 677 #define AR531XPLUS_GPIO_INT         (AR531XPLUS_DSLBASE + 0x00a0)
 678
 679 #define GPIO_CR_M(x)                (1 << (x))                  /* mask for i/o */
 680 #define GPIO_CR_O(x)                (1 << (x))                  /* output */
 681 #define GPIO_CR_I(x)                (0 << (x))                  /* input */
 682
 683 #define GPIO_INT(x,Y)               ((x) << (8 * (Y)))          /* interrupt enable */
 684 #define GPIO_INT_M(Y)               ((0x3F) << (8 * (Y)))       /* mask for int */
 685 #define GPIO_INT_LVL(x,Y)           ((x) << (8 * (Y) + 6))      /* interrupt level */
 686 #define GPIO_INT_LVL_M(Y)           ((0x3) << (8 * (Y) + 6))    /* mask for int level */
 687
 688 #define AR531XPLUS_RESET_GPIO       5
 689 #define AR531XPLUS_NUM_GPIO         22
 690
 691
 692 /*
 693  *  PCI Clock Control
 694  */
 695
 696 #define AR531XPLUS_PCICLK           (AR531XPLUS_DSLBASE + 0x00a4)
 697
 698 #define PCICLK_INPUT_M              0x3
 699 #define PCICLK_INPUT_S              0
 700
 701 #define PCICLK_PLLC_CLKM            0
 702 #define PCICLK_PLLC_CLKM1           1
 703 #define PCICLK_PLLC_CLKC            2
 704 #define PCICLK_REF_CLK              3
 705
 706 #define PCICLK_DIV_M                0xc
 707 #define PCICLK_DIV_S                2
 708
 709 #define PCICLK_IN_FREQ              0
 710 #define PCICLK_IN_FREQ_DIV_6        1
 711 #define PCICLK_IN_FREQ_DIV_8        2
 712 #define PCICLK_IN_FREQ_DIV_10       3
 713
 714 /*
 715  * Observation Control Register
 716  */
 717 #define AR531XPLUS_OCR              (AR531XPLUS_DSLBASE + 0x00b0)
 718 #define OCR_GPIO0_IRIN              0x0040
 719 #define OCR_GPIO1_IROUT             0x0080
 720 #define OCR_GPIO3_RXCLR             0x0200
 721
 722 /*
 723  *  General Clock Control
 724  */
 725
 726 #define AR531XPLUS_MISCCLK          (AR531XPLUS_DSLBASE + 0x00b4)
 727 #define MISCCLK_PLLBYPASS_EN        0x00000001
 728 #define MISCCLK_PROCREFCLK          0x00000002
 729
 730 /*
 731  * SDRAM Controller
 732  *   - No read or write buffers are included.
 733  */
 734 #define AR531XPLUS_MEM_CFG          (AR531XPLUS_SDRAMCTL + 0x00)
 735 #define AR531XPLUS_MEM_CTRL         (AR531XPLUS_SDRAMCTL + 0x0c)
 736 #define AR531XPLUS_MEM_REF          (AR531XPLUS_SDRAMCTL + 0x10)
 737
 738 #define SDRAM_DATA_WIDTH_M          0x00006000
 739 #define SDRAM_DATA_WIDTH_S          13
 740
 741 #define SDRAM_COL_WIDTH_M           0x00001E00
 742 #define SDRAM_COL_WIDTH_S           9
 743
 744 #define SDRAM_ROW_WIDTH_M           0x000001E0
 745 #define SDRAM_ROW_WIDTH_S           5
 746
 747 #define SDRAM_BANKADDR_BITS_M       0x00000018
 748 #define SDRAM_BANKADDR_BITS_S       3
 749
 750
 751 /*
 752  * SDRAM Memory Refresh (MEM_REF) value is computed as:
 753  * MEMCTL_SREFR = (Tr * hclk_freq) / R
 754  * where Tr is max. time of refresh of any single row
 755  * R is number of rows in the DRAM
 756  * For most 133MHz SDRAM parts, Tr=64ms, R=4096 or 8192
 757  */
 758 #if defined(COBRA_EMUL)
 759 #define AR531XPLUS_SDRAM_MEMORY_REFRESH_VALUE  0x96
 760 #else
 761 #if defined(DEFAULT_PLL)
 762 #define AR531XPLUS_SDRAM_MEMORY_REFRESH_VALUE  0x200
 763 #else
 764 #define AR531XPLUS_SDRAM_MEMORY_REFRESH_VALUE  0x61a
 765 #endif /* ! DEFAULT_PLL */
 766 #endif
 767
 768 #if defined(AR531XPLUS)
 769
 770 #define AR531XPLUS_SDRAM_DDR_SDRAM      0   /* Not DDR SDRAM */
 771 #define AR531XPLUS_SDRAM_DATA_WIDTH     16  /* bits */
 772 #define AR531XPLUS_SDRAM_COL_WIDTH      8
 773 #define AR531XPLUS_SDRAM_ROW_WIDTH      12
 774
 775 #else
 776
 777 #define AR531XPLUS_SDRAM_DDR_SDRAM      0   /* Not DDR SDRAM */
 778 #define AR531XPLUS_SDRAM_DATA_WIDTH     16
 779 #define AR531XPLUS_SDRAM_COL_WIDTH      8
 780 #define AR531XPLUS_SDRAM_ROW_WIDTH      12
 781
 782 #endif /* ! AR531XPLUS */
 783
 784 /*
 785  * SPI Flash Interface Registers
 786  */
 787
 788 #define AR531XPLUS_SPI_CTL      (AR531XPLUS_SPI + 0x00)
 789 #define AR531XPLUS_SPI_OPCODE   (AR531XPLUS_SPI + 0x04)
 790 #define AR531XPLUS_SPI_DATA     (AR531XPLUS_SPI + 0x08)
 791
 792 #define SPI_CTL_START           0x00000100
 793 #define SPI_CTL_BUSY            0x00010000
 794 #define SPI_CTL_TXCNT_MASK      0x0000000f
 795 #define SPI_CTL_RXCNT_MASK      0x000000f0
 796 #define SPI_CTL_TX_RX_CNT_MASK  0x000000ff
 797 #define SPI_CTL_SIZE_MASK       0x00060000
 798
 799 #define SPI_CTL_CLK_SEL_MASK    0x03000000
 800 #define SPI_OPCODE_MASK         0x000000ff
 801
 802 /*
 803  * PCI-MAC Configuration registers
 804  */
 805 #define PCI_MAC_RC              (AR531XPLUS_PCI + 0x4000)
 806 #define PCI_MAC_SCR             (AR531XPLUS_PCI + 0x4004)
 807 #define PCI_MAC_INTPEND         (AR531XPLUS_PCI + 0x4008)
 808 #define PCI_MAC_SFR             (AR531XPLUS_PCI + 0x400C)
 809 #define PCI_MAC_PCICFG          (AR531XPLUS_PCI + 0x4010)
 810 #define PCI_MAC_SREV            (AR531XPLUS_PCI + 0x4020)
 811
 812 #define PCI_MAC_RC_MAC          0x00000001
 813 #define PCI_MAC_RC_BB           0x00000002
 814
 815 #define PCI_MAC_SCR_SLMODE_M    0x00030000
 816 #define PCI_MAC_SCR_SLMODE_S    16
 817 #define PCI_MAC_SCR_SLM_FWAKE   0
 818 #define PCI_MAC_SCR_SLM_FSLEEP  1
 819 #define PCI_MAC_SCR_SLM_NORMAL  2
 820
 821 #define PCI_MAC_SFR_SLEEP       0x00000001
 822
 823 #define PCI_MAC_PCICFG_SPWR_DN  0x00010000
 824
 825
 826
 827
 828 /*
 829  * PCI Bus Interface Registers
 830  */
 831 #define AR531XPLUS_PCI_1MS_REG      (AR531XPLUS_PCI + 0x0008)
 832 #define AR531XPLUS_PCI_1MS_MASK     0x3FFFF         /* # of AHB clk cycles in 1ms */
 833
 834 #define AR531XPLUS_PCI_MISC_CONFIG  (AR531XPLUS_PCI + 0x000c)
 835 #define AR531XPLUS_PCIMISC_TXD_EN   0x00000001      /* Enable TXD for fragments */
 836 #define AR531XPLUS_PCIMISC_CFG_SEL  0x00000002      /* mem or config cycles */
 837 #define AR531XPLUS_PCIMISC_GIG_MASK 0x0000000C      /* bits 31-30 for pci req */
 838 #define AR531XPLUS_PCIMISC_RST_MODE 0x00000030
 839 #define AR531XPLUS_PCIRST_INPUT     0x00000000      /* 4:5=0 rst is input */
 840 #define AR531XPLUS_PCIRST_LOW       0x00000010      /* 4:5=1 rst to GND */
 841 #define AR531XPLUS_PCIRST_HIGH      0x00000020      /* 4:5=2 rst to VDD */
 842 #define AR531XPLUS_PCIGRANT_EN      0x00000000      /* 6:7=0 early grant en */
 843 #define AR531XPLUS_PCIGRANT_FRAME   0x00000040      /* 6:7=1 grant waits 4 frame */
 844 #define AR531XPLUS_PCIGRANT_IDLE    0x00000080      /* 6:7=2 grant waits 4 idle */
 845 #define AR531XPLUS_PCIGRANT_GAP     0x00000000      /* 6:7=2 grant waits 4 idle */
 846 #define AR531XPLUS_PCICACHE_DIS     0x00001000      /* PCI external access cache disable */
 847
 848 #define AR531XPLUS_PCI_OUT_TSTAMP   (AR531XPLUS_PCI + 0x0010)
 849
 850 #define AR531XPLUS_PCI_UNCACHE_CFG  (AR531XPLUS_PCI + 0x0014)
 851
 852 #define AR531XPLUS_PCI_IN_EN        (AR531XPLUS_PCI + 0x0100)
 853 #define AR531XPLUS_PCI_IN_EN0       0x01            /* Enable chain 0 */
 854 #define AR531XPLUS_PCI_IN_EN1       0x02            /* Enable chain 1 */
 855 #define AR531XPLUS_PCI_IN_EN2       0x04            /* Enable chain 2 */
 856 #define AR531XPLUS_PCI_IN_EN3       0x08            /* Enable chain 3 */
 857
 858 #define AR531XPLUS_PCI_IN_DIS       (AR531XPLUS_PCI + 0x0104)
 859 #define AR531XPLUS_PCI_IN_DIS0      0x01            /* Disable chain 0 */
 860 #define AR531XPLUS_PCI_IN_DIS1      0x02            /* Disable chain 1 */
 861 #define AR531XPLUS_PCI_IN_DIS2      0x04            /* Disable chain 2 */
 862 #define AR531XPLUS_PCI_IN_DIS3      0x08            /* Disable chain 3 */
 863
 864 #define AR531XPLUS_PCI_IN_PTR       (AR531XPLUS_PCI + 0x0200)
 865
 866 #define AR531XPLUS_PCI_OUT_EN       (AR531XPLUS_PCI + 0x0400)
 867 #define AR531XPLUS_PCI_OUT_EN0      0x01            /* Enable chain 0 */
 868
 869 #define AR531XPLUS_PCI_OUT_DIS      (AR531XPLUS_PCI + 0x0404)
 870 #define AR531XPLUS_PCI_OUT_DIS0     0x01            /* Disable chain 0 */
 871
 872 #define AR531XPLUS_PCI_OUT_PTR      (AR531XPLUS_PCI + 0x0408)
 873
 874 #define AR531XPLUS_PCI_INT_STATUS   (AR531XPLUS_PCI + 0x0500)   /* write one to clr */
 875 #define AR531XPLUS_PCI_TXINT        0x00000001      /* Desc In Completed */
 876 #define AR531XPLUS_PCI_TXOK         0x00000002      /* Desc In OK */
 877 #define AR531XPLUS_PCI_TXERR        0x00000004      /* Desc In ERR */
 878 #define AR531XPLUS_PCI_TXEOL        0x00000008      /* Desc In End-of-List */
 879 #define AR531XPLUS_PCI_RXINT        0x00000010      /* Desc Out Completed */
 880 #define AR531XPLUS_PCI_RXOK         0x00000020      /* Desc Out OK */
 881 #define AR531XPLUS_PCI_RXERR        0x00000040      /* Desc Out ERR */
 882 #define AR531XPLUS_PCI_RXEOL        0x00000080      /* Desc Out EOL */
 883 #define AR531XPLUS_PCI_TXOOD        0x00000200      /* Desc In Out-of-Desc */
 884 #define AR531XPLUS_PCI_MASK         0x0000FFFF      /* Desc Mask */
 885 #define AR531XPLUS_PCI_EXT_INT      0x02000000
 886 #define AR531XPLUS_PCI_ABORT_INT    0x04000000
 887
 888 #define AR531XPLUS_PCI_INT_MASK     (AR531XPLUS_PCI + 0x0504)   /* same as INT_STATUS */
 889
 890 #define AR531XPLUS_PCI_INTEN_REG    (AR531XPLUS_PCI + 0x0508)
 891 #define AR531XPLUS_PCI_INT_DISABLE  0x00            /* disable pci interrupts */
 892 #define AR531XPLUS_PCI_INT_ENABLE   0x01            /* enable pci interrupts */
 893
 894 #define AR531XPLUS_PCI_HOST_IN_EN   (AR531XPLUS_PCI + 0x0800)
 895 #define AR531XPLUS_PCI_HOST_IN_DIS  (AR531XPLUS_PCI + 0x0804)
 896 #define AR531XPLUS_PCI_HOST_IN_PTR  (AR531XPLUS_PCI + 0x0810)
 897 #define AR531XPLUS_PCI_HOST_OUT_EN  (AR531XPLUS_PCI + 0x0900)
 898 #define AR531XPLUS_PCI_HOST_OUT_DIS (AR531XPLUS_PCI + 0x0904)
 899 #define AR531XPLUS_PCI_HOST_OUT_PTR (AR531XPLUS_PCI + 0x0908)
 900
 901
 902 /*
 903  * Local Bus Interface Registers
 904  */
 905 #define AR531XPLUS_LB_CONFIG        (AR531XPLUS_LOCAL + 0x0000)
 906 #define AR531XPLUS_LBCONF_OE        0x00000001      /* =1 OE is low-true */
 907 #define AR531XPLUS_LBCONF_CS0       0x00000002      /* =1 first CS is low-true */
 908 #define AR531XPLUS_LBCONF_CS1       0x00000004      /* =1 2nd CS is low-true */
 909 #define AR531XPLUS_LBCONF_RDY       0x00000008      /* =1 RDY is low-true */
 910 #define AR531XPLUS_LBCONF_WE        0x00000010      /* =1 Write En is low-true */
 911 #define AR531XPLUS_LBCONF_WAIT      0x00000020      /* =1 WAIT is low-true */
 912 #define AR531XPLUS_LBCONF_ADS       0x00000040      /* =1 Adr Strobe is low-true */
 913 #define AR531XPLUS_LBCONF_MOT       0x00000080      /* =0 Intel, =1 Motorola */
 914 #define AR531XPLUS_LBCONF_8CS       0x00000100      /* =1 8 bits CS, 0= 16bits */
 915 #define AR531XPLUS_LBCONF_8DS       0x00000200      /* =1 8 bits Data S, 0=16bits */
 916 #define AR531XPLUS_LBCONF_ADS_EN    0x00000400      /* =1 Enable ADS */
 917 #define AR531XPLUS_LBCONF_ADR_OE    0x00000800      /* =1 Adr cap on OE, WE or DS */
 918 #define AR531XPLUS_LBCONF_ADDT_MUX  0x00001000      /* =1 Adr and Data share bus */
 919 #define AR531XPLUS_LBCONF_DATA_OE   0x00002000      /* =1 Data cap on OE, WE, DS */
 920 #define AR531XPLUS_LBCONF_16DATA    0x00004000      /* =1 Data is 16 bits wide */
 921 #define AR531XPLUS_LBCONF_SWAPDT    0x00008000      /* =1 Byte swap data */
 922 #define AR531XPLUS_LBCONF_SYNC      0x00010000      /* =1 Bus synchronous to clk */
 923 #define AR531XPLUS_LBCONF_INT       0x00020000      /* =1 Intr is low true */
 924 #define AR531XPLUS_LBCONF_INT_CTR0  0x00000000      /* GND high-Z, Vdd is high-Z */
 925 #define AR531XPLUS_LBCONF_INT_CTR1  0x00040000      /* GND drive, Vdd is high-Z */
 926 #define AR531XPLUS_LBCONF_INT_CTR2  0x00080000      /* GND high-Z, Vdd drive */
 927 #define AR531XPLUS_LBCONF_INT_CTR3  0x000C0000      /* GND drive, Vdd drive */
 928 #define AR531XPLUS_LBCONF_RDY_WAIT  0x00100000      /* =1 RDY is negative of WAIT */
 929 #define AR531XPLUS_LBCONF_INT_PULSE 0x00200000      /* =1 Interrupt is a pulse */
 930 #define AR531XPLUS_LBCONF_ENABLE    0x00400000      /* =1 Falcon respond to LB */
 931
 932 #define AR531XPLUS_LB_CLKSEL        (AR531XPLUS_LOCAL + 0x0004)
 933 #define AR531XPLUS_LBCLK_EXT        0x0001          /* use external clk for lb */
 934
 935 #define AR531XPLUS_LB_1MS           (AR531XPLUS_LOCAL + 0x0008)
 936 #define AR531XPLUS_LB1MS_MASK       0x3FFFF         /* # of AHB clk cycles in 1ms */
 937
 938 #define AR531XPLUS_LB_MISCCFG       (AR531XPLUS_LOCAL + 0x000C)
 939 #define AR531XPLUS_LBM_TXD_EN       0x00000001      /* Enable TXD for fragments */
 940 #define AR531XPLUS_LBM_RX_INTEN     0x00000002      /* Enable LB ints on RX ready */
 941 #define AR531XPLUS_LBM_MBOXWR_INTEN 0x00000004      /* Enable LB ints on mbox wr */
 942 #define AR531XPLUS_LBM_MBOXRD_INTEN 0x00000008      /* Enable LB ints on mbox rd */
 943 #define AR531XPLUS_LMB_DESCSWAP_EN  0x00000010      /* Byte swap desc enable */
 944 #define AR531XPLUS_LBM_TIMEOUT_MASK 0x00FFFF80
 945 #define AR531XPLUS_LBM_TIMEOUT_SHFT 7
 946 #define AR531XPLUS_LBM_PORTMUX      0x07000000
 947
 948
 949 #define AR531XPLUS_LB_RXTSOFF       (AR531XPLUS_LOCAL + 0x0010)
 950
 951 #define AR531XPLUS_LB_TX_CHAIN_EN   (AR531XPLUS_LOCAL + 0x0100)
 952 #define AR531XPLUS_LB_TXEN_0        0x01
 953 #define AR531XPLUS_LB_TXEN_1        0x02
 954 #define AR531XPLUS_LB_TXEN_2        0x04
 955 #define AR531XPLUS_LB_TXEN_3        0x08
 956
 957 #define AR531XPLUS_LB_TX_CHAIN_DIS  (AR531XPLUS_LOCAL + 0x0104)
 958 #define AR531XPLUS_LB_TX_DESC_PTR   (AR531XPLUS_LOCAL + 0x0200)
 959
 960 #define AR531XPLUS_LB_RX_CHAIN_EN   (AR531XPLUS_LOCAL + 0x0400)
 961 #define AR531XPLUS_LB_RXEN          0x01
 962
 963 #define AR531XPLUS_LB_RX_CHAIN_DIS  (AR531XPLUS_LOCAL + 0x0404)
 964 #define AR531XPLUS_LB_RX_DESC_PTR   (AR531XPLUS_LOCAL + 0x0408)
 965
 966 #define AR531XPLUS_LB_INT_STATUS    (AR531XPLUS_LOCAL + 0x0500)
 967 #define AR531XPLUS_INT_TX_DESC      0x0001
 968 #define AR531XPLUS_INT_TX_OK        0x0002
 969 #define AR531XPLUS_INT_TX_ERR       0x0004
 970 #define AR531XPLUS_INT_TX_EOF       0x0008
 971 #define AR531XPLUS_INT_RX_DESC      0x0010
 972 #define AR531XPLUS_INT_RX_OK        0x0020
 973 #define AR531XPLUS_INT_RX_ERR       0x0040
 974 #define AR531XPLUS_INT_RX_EOF       0x0080
 975 #define AR531XPLUS_INT_TX_TRUNC     0x0100
 976 #define AR531XPLUS_INT_TX_STARVE    0x0200
 977 #define AR531XPLUS_INT_LB_TIMEOUT   0x0400
 978 #define AR531XPLUS_INT_LB_ERR       0x0800
 979 #define AR531XPLUS_INT_MBOX_WR      0x1000
 980 #define AR531XPLUS_INT_MBOX_RD      0x2000
 981
 982 /* Bit definitions for INT MASK are the same as INT_STATUS */
 983 #define AR531XPLUS_LB_INT_MASK      (AR531XPLUS_LOCAL + 0x0504)
 984
 985 #define AR531XPLUS_LB_INT_EN        (AR531XPLUS_LOCAL + 0x0508)
 986 #define AR531XPLUS_LB_MBOX          (AR531XPLUS_LOCAL + 0x0600)
 987
 988
 989
 990 /*
 991  * IR Interface Registers
 992  */
 993 #define AR531XPLUS_IR_PKTDATA                   (AR531XPLUS_IR + 0x0000)
 994
 995 #define AR531XPLUS_IR_PKTLEN                    (AR531XPLUS_IR + 0x07fc) /* 0 - 63 */
 996
 997 #define AR531XPLUS_IR_CONTROL                   (AR531XPLUS_IR + 0x0800)
 998 #define AR531XPLUS_IRCTL_TX                     0x00000000  /* use as tranmitter */
 999 #define AR531XPLUS_IRCTL_RX                     0x00000001  /* use as receiver   */
1000 #define AR531XPLUS_IRCTL_SAMPLECLK_MASK         0x00003ffe  /* Sample clk divisor mask */
1001 #define AR531XPLUS_IRCTL_SAMPLECLK_SHFT                  1
1002 #define AR531XPLUS_IRCTL_OUTPUTCLK_MASK         0x03ffc000  /* Output clk divisor mask */
1003 #define AR531XPLUS_IRCTL_OUTPUTCLK_SHFT                 14
1004
1005 #define AR531XPLUS_IR_STATUS                    (AR531XPLUS_IR + 0x0804)
1006 #define AR531XPLUS_IRSTS_RX                     0x00000001  /* receive in progress */
1007 #define AR531XPLUS_IRSTS_TX                     0x00000002  /* transmit in progress */
1008
1009 #define AR531XPLUS_IR_CONFIG                    (AR531XPLUS_IR + 0x0808)
1010 #define AR531XPLUS_IRCFG_INVIN                  0x00000001  /* invert input polarity */
1011 #define AR531XPLUS_IRCFG_INVOUT                 0x00000002  /* invert output polarity */
1012 #define AR531XPLUS_IRCFG_SEQ_START_WIN_SEL      0x00000004  /* 1 => 28, 0 => 7 */
1013 #define AR531XPLUS_IRCFG_SEQ_START_THRESH       0x000000f0  /*  */
1014 #define AR531XPLUS_IRCFG_SEQ_END_UNIT_SEL       0x00000100  /*  */
1015 #define AR531XPLUS_IRCFG_SEQ_END_UNIT_THRESH    0x00007e00  /*  */
1016 #define AR531XPLUS_IRCFG_SEQ_END_WIN_SEL        0x00008000  /*  */
1017 #define AR531XPLUS_IRCFG_SEQ_END_WIN_THRESH     0x001f0000  /*  */
1018 #define AR531XPLUS_IRCFG_NUM_BACKOFF_WORDS      0x01e00000  /*  */
1019
1020 /*
1021  * PCI memory constants: Memory area 1 and 2 are the same size -
1022  * (twice the PCI_TLB_PAGE_SIZE). The definition of
1023  * CPU_TO_PCI_MEM_SIZE is coupled with the TLB setup routine
1024  * sysLib.c/sysTlbInit(), in that it assumes that 2 pages of size
1025  * PCI_TLB_PAGE_SIZE are set up in the TLB for each PCI memory space.
1026  */
1027
1028 #define CPU_TO_PCI_MEM_BASE1    0xE0000000
1029 #define CPU_TO_PCI_MEM_SIZE1    (2*PCI_TLB_PAGE_SIZE)
1030
1031
1032 /* TLB attributes for PCI transactions */
1033
1034 #define PCI_MMU_PAGEMASK        0x00003FFF
1035 #define MMU_PAGE_UNCACHED       0x00000010
1036 #define MMU_PAGE_DIRTY          0x00000004
1037 #define MMU_PAGE_VALID          0x00000002
1038 #define MMU_PAGE_GLOBAL         0x00000001
1039 #define PCI_MMU_PAGEATTRIB      (MMU_PAGE_UNCACHED|MMU_PAGE_DIRTY|\
1040                                  MMU_PAGE_VALID|MMU_PAGE_GLOBAL)
1041 #define PCI_MEMORY_SPACE1_VIRT  0xE0000000      /* Used for non-prefet  mem   */
1042 #define PCI_MEMORY_SPACE1_PHYS  0x80000000
1043 #define PCI_TLB_PAGE_SIZE       0x01000000
1044 #define TLB_HI_MASK             0xFFFFE000
1045 #define TLB_LO_MASK             0x3FFFFFFF
1046 #define PAGEMASK_SHIFT          11
1047 #define TLB_LO_SHIFT            6
1048
1049 #define PCI_MAX_LATENCY         0xFFF           /* Max PCI latency            */
1050
1051 #define HOST_PCI_DEV_ID         3
1052 #define HOST_PCI_MBAR0          0x10000000
1053 #define HOST_PCI_MBAR1          0x20000000
1054 #define HOST_PCI_MBAR2          0x30000000
1055
1056 #define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
1057 #define PCI_DEVICE_MEM_SPACE    0x800000
1058
1059
1060 typedef unsigned int AR531X_REG;
1061
1062 #define sysRegRead(phys)        \
1063         (*(volatile AR531X_REG *)PHYS_TO_K1(phys))
1064
1065 #define sysRegWrite(phys, val)  \
1066         ((*(volatile AR531X_REG *)PHYS_TO_K1(phys)) = (val))
1067
1068
1069
1070 /*
1071  * This is board-specific data that is stored in a "fixed" location in flash.
1072  * It is shared across operating systems, so it should not be changed lightly.
1073  * The main reason we need it is in order to extract the ethernet MAC
1074  * address(es).
1075  */
1076 struct ar531x_boarddata {
1077     u32 magic;                       /* board data is valid */
1078 #define AR531X_BD_MAGIC 0x35333131   /* "5311", for all 531x platforms */
1079     u16 cksum;                       /* checksum (starting with BD_REV 2) */
1080     u16 rev;                         /* revision of this struct */
1081 #define BD_REV  4
1082     char   boardName[64];            /* Name of board */
1083     u16 major;                       /* Board major number */
1084     u16 minor;                       /* Board minor number */
1085     u32 config;                      /* Board configuration */
1086 #define BD_ENET0        0x00000001   /* ENET0 is stuffed */
1087 #define BD_ENET1        0x00000002   /* ENET1 is stuffed */
1088 #define BD_UART1        0x00000004   /* UART1 is stuffed */
1089 #define BD_UART0        0x00000008   /* UART0 is stuffed (dma) */
1090 #define BD_RSTFACTORY   0x00000010   /* Reset factory defaults stuffed */
1091 #define BD_SYSLED       0x00000020   /* System LED stuffed */
1092 #define BD_EXTUARTCLK   0x00000040   /* External UART clock */
1093 #define BD_CPUFREQ      0x00000080   /* cpu freq is valid in nvram */
1094 #define BD_SYSFREQ      0x00000100   /* sys freq is set in nvram */
1095 #define BD_WLAN0        0x00000200   /* Enable WLAN0 */
1096 #define BD_MEMCAP       0x00000400   /* CAP SDRAM @ memCap for testing */
1097 #define BD_DISWATCHDOG  0x00000800   /* disable system watchdog */
1098 #define BD_WLAN1        0x00001000   /* Enable WLAN1 (ar5212) */
1099 #define BD_ISCASPER     0x00002000   /* FLAG for AR2312 */
1100 #define BD_WLAN0_2G_EN  0x00004000   /* FLAG for radio0_2G */
1101 #define BD_WLAN0_5G_EN  0x00008000   /* FLAG for radio0_2G */
1102 #define BD_WLAN1_2G_EN  0x00020000   /* FLAG for radio0_2G */
1103 #define BD_WLAN1_5G_EN  0x00040000   /* FLAG for radio0_2G */
1104     u16 resetConfigGpio;             /* Reset factory GPIO pin */
1105     u16 sysLedGpio;                  /* System LED GPIO pin */
1106
1107     u32 cpuFreq;                     /* CPU core frequency in Hz */
1108     u32 sysFreq;                     /* System frequency in Hz */
1109     u32 cntFreq;                     /* Calculated C0_COUNT frequency */
1110
1111     u8  wlan0Mac[6];
1112     u8  enet0Mac[6];
1113     u8  enet1Mac[6];
1114
1115     u16 pciId;                       /* Pseudo PCIID for common code */
1116     u16 memCap;                      /* cap bank1 in MB */
1117
1118     /* version 3 */
1119     u8  wlan1Mac[6];                 /* (ar5212) */
1120 };
1121
1122 #endif
1123
1124 #endif /* AR531X_H */