target/linux/lantiq/patches-2.6.39/0008-MIPS-Lantiq-Add-more-gpio-drivers.patch

   1 From f9391211e47cdcc31f341d710efef4b3b46c333d Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 30 Mar 2011 09:27:56 +0200
   4 Subject: [PATCH 08/13] MIPS: Lantiq: Add more gpio drivers
   5
   6 The XWAY family allows to extend the number of gpios by using shift registers or latches. This patch adds the 2 drivers needed for this. The extended gpios are output only.
   7
   8 [ralf@linux-mips.org: Fixed ltq_stp_probe section() attributes.]
   9
  10 Signed-off-by: John Crispin <blogic@openwrt.org>
  11 Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
  12 Cc: linux-mips@linux-mips.org
  13 Patchwork: https://patchwork.linux-mips.org/patch/2258/
  14 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  15 ---
  16  arch/mips/lantiq/xway/Makefile   |    2 +-
  17  arch/mips/lantiq/xway/gpio_ebu.c |  126 ++++++++++++++++++++++++++++++
  18  arch/mips/lantiq/xway/gpio_stp.c |  157 ++++++++++++++++++++++++++++++++++++++
  19  3 files changed, 284 insertions(+), 1 deletions(-)
  20  create mode 100644 arch/mips/lantiq/xway/gpio_ebu.c
  21  create mode 100644 arch/mips/lantiq/xway/gpio_stp.c
  22
  23 --- a/arch/mips/lantiq/xway/Makefile
  24 +++ b/arch/mips/lantiq/xway/Makefile
  25 @@ -1,4 +1,4 @@
  26 -obj-y := pmu.o ebu.o reset.o gpio.o devices.o
  27 +obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o
  28
  29  obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o
  30  obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o
  31 --- /dev/null
  32 +++ b/arch/mips/lantiq/xway/gpio_ebu.c
  33 @@ -0,0 +1,126 @@
  34 +/*
  35 + *  This program is free software; you can redistribute it and/or modify it
  36 + *  under the terms of the GNU General Public License version 2 as published
  37 + *  by the Free Software Foundation.
  38 + *
  39 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
  40 + */
  41 +
  42 +#include <linux/init.h>
  43 +#include <linux/module.h>
  44 +#include <linux/types.h>
  45 +#include <linux/platform_device.h>
  46 +#include <linux/mutex.h>
  47 +#include <linux/gpio.h>
  48 +#include <linux/io.h>
  49 +
  50 +#include <lantiq_soc.h>
  51 +
  52 +/*
  53 + * By attaching hardware latches to the EBU it is possible to create output
  54 + * only gpios. This driver configures a special memory address, which when
  55 + * written to outputs 16 bit to the latches.
  56 + */
  57 +
  58 +#define LTQ_EBU_BUSCON 0x1e7ff         /* 16 bit access, slowest timing */
  59 +#define LTQ_EBU_WP     0x80000000      /* write protect bit */
  60 +
  61 +/* we keep a shadow value of the last value written to the ebu */
  62 +static int ltq_ebu_gpio_shadow = 0x0;
  63 +static void __iomem *ltq_ebu_gpio_membase;
  64 +
  65 +static void ltq_ebu_apply(void)
  66 +{
  67 +       unsigned long flags;
  68 +
  69 +       spin_lock_irqsave(&ebu_lock, flags);
  70 +       ltq_ebu_w32(LTQ_EBU_BUSCON, LTQ_EBU_BUSCON1);
  71 +       *((__u16 *)ltq_ebu_gpio_membase) = ltq_ebu_gpio_shadow;
  72 +       ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1);
  73 +       spin_unlock_irqrestore(&ebu_lock, flags);
  74 +}
  75 +
  76 +static void ltq_ebu_set(struct gpio_chip *chip, unsigned offset, int value)
  77 +{
  78 +       if (value)
  79 +               ltq_ebu_gpio_shadow |= (1 << offset);
  80 +       else
  81 +               ltq_ebu_gpio_shadow &= ~(1 << offset);
  82 +       ltq_ebu_apply();
  83 +}
  84 +
  85 +static int ltq_ebu_direction_output(struct gpio_chip *chip, unsigned offset,
  86 +       int value)
  87 +{
  88 +       ltq_ebu_set(chip, offset, value);
  89 +
  90 +       return 0;
  91 +}
  92 +
  93 +static struct gpio_chip ltq_ebu_chip = {
  94 +       .label = "ltq_ebu",
  95 +       .direction_output = ltq_ebu_direction_output,
  96 +       .set = ltq_ebu_set,
  97 +       .base = 72,
  98 +       .ngpio = 16,
  99 +       .can_sleep = 1,
 100 +       .owner = THIS_MODULE,
 101 +};
 102 +
 103 +static int ltq_ebu_probe(struct platform_device *pdev)
 104 +{
 105 +       int ret = 0;
 106 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 107 +
 108 +       if (!res) {
 109 +               dev_err(&pdev->dev, "failed to get memory resource\n");
 110 +               return -ENOENT;
 111 +       }
 112 +
 113 +       res = devm_request_mem_region(&pdev->dev, res->start,
 114 +               resource_size(res), dev_name(&pdev->dev));
 115 +       if (!res) {
 116 +               dev_err(&pdev->dev, "failed to request memory resource\n");
 117 +               return -EBUSY;
 118 +       }
 119 +
 120 +       ltq_ebu_gpio_membase = devm_ioremap_nocache(&pdev->dev, res->start,
 121 +               resource_size(res));
 122 +       if (!ltq_ebu_gpio_membase) {
 123 +               dev_err(&pdev->dev, "Failed to ioremap mem region\n");
 124 +               return -ENOMEM;
 125 +       }
 126 +
 127 +       /* grab the default shadow value passed form the platform code */
 128 +       ltq_ebu_gpio_shadow = (unsigned int) pdev->dev.platform_data;
 129 +
 130 +       /* tell the ebu controller which memory address we will be using */
 131 +       ltq_ebu_w32(pdev->resource->start | 0x1, LTQ_EBU_ADDRSEL1);
 132 +
 133 +       /* write protect the region */
 134 +       ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1);
 135 +
 136 +       ret = gpiochip_add(&ltq_ebu_chip);
 137 +       if (!ret)
 138 +               ltq_ebu_apply();
 139 +       return ret;
 140 +}
 141 +
 142 +static struct platform_driver ltq_ebu_driver = {
 143 +       .probe = ltq_ebu_probe,
 144 +       .driver = {
 145 +               .name = "ltq_ebu",
 146 +               .owner = THIS_MODULE,
 147 +       },
 148 +};
 149 +
 150 +static int __init ltq_ebu_init(void)
 151 +{
 152 +       int ret = platform_driver_register(&ltq_ebu_driver);
 153 +
 154 +       if (ret)
 155 +               pr_info("ltq_ebu : Error registering platfom driver!");
 156 +       return ret;
 157 +}
 158 +
 159 +postcore_initcall(ltq_ebu_init);
 160 --- /dev/null
 161 +++ b/arch/mips/lantiq/xway/gpio_stp.c
 162 @@ -0,0 +1,157 @@
 163 +/*
 164 + *  This program is free software; you can redistribute it and/or modify it
 165 + *  under the terms of the GNU General Public License version 2 as published
 166 + *  by the Free Software Foundation.
 167 + *
 168 + *  Copyright (C) 2007 John Crispin <blogic@openwrt.org>
 169 + *
 170 + */
 171 +
 172 +#include <linux/slab.h>
 173 +#include <linux/init.h>
 174 +#include <linux/module.h>
 175 +#include <linux/types.h>
 176 +#include <linux/platform_device.h>
 177 +#include <linux/mutex.h>
 178 +#include <linux/io.h>
 179 +#include <linux/gpio.h>
 180 +
 181 +#include <lantiq_soc.h>
 182 +
 183 +#define LTQ_STP_CON0           0x00
 184 +#define LTQ_STP_CON1           0x04
 185 +#define LTQ_STP_CPU0           0x08
 186 +#define LTQ_STP_CPU1           0x0C
 187 +#define LTQ_STP_AR             0x10
 188 +
 189 +#define LTQ_STP_CON_SWU                (1 << 31)
 190 +#define LTQ_STP_2HZ            0
 191 +#define LTQ_STP_4HZ            (1 << 23)
 192 +#define LTQ_STP_8HZ            (2 << 23)
 193 +#define LTQ_STP_10HZ           (3 << 23)
 194 +#define LTQ_STP_SPEED_MASK     (0xf << 23)
 195 +#define LTQ_STP_UPD_FPI                (1 << 31)
 196 +#define LTQ_STP_UPD_MASK       (3 << 30)
 197 +#define LTQ_STP_ADSL_SRC       (3 << 24)
 198 +
 199 +#define LTQ_STP_GROUP0         (1 << 0)
 200 +
 201 +#define LTQ_STP_RISING         0
 202 +#define LTQ_STP_FALLING                (1 << 26)
 203 +#define LTQ_STP_EDGE_MASK      (1 << 26)
 204 +
 205 +#define ltq_stp_r32(reg)       __raw_readl(ltq_stp_membase + reg)
 206 +#define ltq_stp_w32(val, reg)  __raw_writel(val, ltq_stp_membase + reg)
 207 +#define ltq_stp_w32_mask(clear, set, reg) \
 208 +               ltq_w32((ltq_r32(ltq_stp_membase + reg) & ~(clear)) | (set), \
 209 +               ltq_stp_membase + (reg))
 210 +
 211 +static int ltq_stp_shadow = 0xffff;
 212 +static void __iomem *ltq_stp_membase;
 213 +
 214 +static void ltq_stp_set(struct gpio_chip *chip, unsigned offset, int value)
 215 +{
 216 +       if (value)
 217 +               ltq_stp_shadow |= (1 << offset);
 218 +       else
 219 +               ltq_stp_shadow &= ~(1 << offset);
 220 +       ltq_stp_w32(ltq_stp_shadow, LTQ_STP_CPU0);
 221 +}
 222 +
 223 +static int ltq_stp_direction_output(struct gpio_chip *chip, unsigned offset,
 224 +       int value)
 225 +{
 226 +       ltq_stp_set(chip, offset, value);
 227 +
 228 +       return 0;
 229 +}
 230 +
 231 +static struct gpio_chip ltq_stp_chip = {
 232 +       .label = "ltq_stp",
 233 +       .direction_output = ltq_stp_direction_output,
 234 +       .set = ltq_stp_set,
 235 +       .base = 48,
 236 +       .ngpio = 24,
 237 +       .can_sleep = 1,
 238 +       .owner = THIS_MODULE,
 239 +};
 240 +
 241 +static int ltq_stp_hw_init(void)
 242 +{
 243 +       /* the 3 pins used to control the external stp */
 244 +       ltq_gpio_request(4, 1, 0, 1, "stp-st");
 245 +       ltq_gpio_request(5, 1, 0, 1, "stp-d");
 246 +       ltq_gpio_request(6, 1, 0, 1, "stp-sh");
 247 +
 248 +       /* sane defaults */
 249 +       ltq_stp_w32(0, LTQ_STP_AR);
 250 +       ltq_stp_w32(0, LTQ_STP_CPU0);
 251 +       ltq_stp_w32(0, LTQ_STP_CPU1);
 252 +       ltq_stp_w32(LTQ_STP_CON_SWU, LTQ_STP_CON0);
 253 +       ltq_stp_w32(0, LTQ_STP_CON1);
 254 +
 255 +       /* rising or falling edge */
 256 +       ltq_stp_w32_mask(LTQ_STP_EDGE_MASK, LTQ_STP_FALLING, LTQ_STP_CON0);
 257 +
 258 +       /* per default stp 15-0 are set */
 259 +       ltq_stp_w32_mask(0, LTQ_STP_GROUP0, LTQ_STP_CON1);
 260 +
 261 +       /* stp are update periodically by the FPI bus */
 262 +       ltq_stp_w32_mask(LTQ_STP_UPD_MASK, LTQ_STP_UPD_FPI, LTQ_STP_CON1);
 263 +
 264 +       /* set stp update speed */
 265 +       ltq_stp_w32_mask(LTQ_STP_SPEED_MASK, LTQ_STP_8HZ, LTQ_STP_CON1);
 266 +
 267 +       /* tell the hardware that pin (led) 0 and 1 are controlled
 268 +        *  by the dsl arc
 269 +        */
 270 +       ltq_stp_w32_mask(0, LTQ_STP_ADSL_SRC, LTQ_STP_CON0);
 271 +
 272 +       ltq_pmu_enable(PMU_LED);
 273 +       return 0;
 274 +}
 275 +
 276 +static int __devinit ltq_stp_probe(struct platform_device *pdev)
 277 +{
 278 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 279 +       int ret = 0;
 280 +
 281 +       if (!res)
 282 +               return -ENOENT;
 283 +       res = devm_request_mem_region(&pdev->dev, res->start,
 284 +               resource_size(res), dev_name(&pdev->dev));
 285 +       if (!res) {
 286 +               dev_err(&pdev->dev, "failed to request STP memory\n");
 287 +               return -EBUSY;
 288 +       }
 289 +       ltq_stp_membase = devm_ioremap_nocache(&pdev->dev, res->start,
 290 +               resource_size(res));
 291 +       if (!ltq_stp_membase) {
 292 +               dev_err(&pdev->dev, "failed to remap STP memory\n");
 293 +               return -ENOMEM;
 294 +       }
 295 +       ret = gpiochip_add(&ltq_stp_chip);
 296 +       if (!ret)
 297 +               ret = ltq_stp_hw_init();
 298 +
 299 +       return ret;
 300 +}
 301 +
 302 +static struct platform_driver ltq_stp_driver = {
 303 +       .probe = ltq_stp_probe,
 304 +       .driver = {
 305 +               .name = "ltq_stp",
 306 +               .owner = THIS_MODULE,
 307 +       },
 308 +};
 309 +
 310 +int __init ltq_stp_init(void)
 311 +{
 312 +       int ret = platform_driver_register(&ltq_stp_driver);
 313 +
 314 +       if (ret)
 315 +               pr_info("ltq_stp: error registering platfom driver");
 316 +       return ret;
 317 +}
 318 +
 319 +postcore_initcall(ltq_stp_init);