package/rt2x00/src/rt2400pci.h

   1 /*
   2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2400pci
  23         Abstract: Data structures and registers for the rt2400pci module.
  24         Supported chipsets: RT2460.
  25  */
  26
  27 #ifndef RT2400PCI_H
  28 #define RT2400PCI_H
  29
  30 /*
  31  * RF chip defines.
  32  */
  33 #define RF2420                          0x0000
  34 #define RF2421                          0x0001
  35
  36 /*
  37  * Signal information.
  38  */
  39 #define MAX_RX_SSI                      -1
  40 #define MAX_RX_NOISE                    -110
  41 #define DEFAULT_RSSI_OFFSET             100
  42
  43 /*
  44  * Register layout information.
  45  */
  46 #define CSR_REG_BASE                    0x0000
  47 #define CSR_REG_SIZE                    0x014c
  48 #define EEPROM_BASE                     0x0000
  49 #define EEPROM_SIZE                     0x0100
  50 #define BBP_SIZE                        0x0020
  51
  52 /*
  53  * Control/Status Registers(CSR).
  54  * Some values are set in TU, whereas 1 TU == 1024 us.
  55  */
  56
  57 /*
  58  * CSR0: ASIC revision number.
  59  */
  60 #define CSR0                            0x0000
  61
  62 /*
  63  * CSR1: System control register.
  64  * SOFT_RESET: Software reset, 1: reset, 0: normal.
  65  * BBP_RESET: Hardware reset, 1: reset, 0, release.
  66  * HOST_READY: Host ready after initialization.
  67  */
  68 #define CSR1                            0x0004
  69 #define CSR1_SOFT_RESET                 FIELD32(0x00000001)
  70 #define CSR1_BBP_RESET                  FIELD32(0x00000002)
  71 #define CSR1_HOST_READY                 FIELD32(0x00000004)
  72
  73 /*
  74  * CSR2: System admin status register (invalid).
  75  */
  76 #define CSR2                            0x0008
  77
  78 /*
  79  * CSR3: STA MAC address register 0.
  80  */
  81 #define CSR3                            0x000c
  82 #define CSR3_BYTE0                      FIELD32(0x000000ff)
  83 #define CSR3_BYTE1                      FIELD32(0x0000ff00)
  84 #define CSR3_BYTE2                      FIELD32(0x00ff0000)
  85 #define CSR3_BYTE3                      FIELD32(0xff000000)
  86
  87 /*
  88  * CSR4: STA MAC address register 1.
  89  */
  90 #define CSR4                            0x0010
  91 #define CSR4_BYTE4                      FIELD32(0x000000ff)
  92 #define CSR4_BYTE5                      FIELD32(0x0000ff00)
  93
  94 /*
  95  * CSR5: BSSID register 0.
  96  */
  97 #define CSR5                            0x0014
  98 #define CSR5_BYTE0                      FIELD32(0x000000ff)
  99 #define CSR5_BYTE1                      FIELD32(0x0000ff00)
 100 #define CSR5_BYTE2                      FIELD32(0x00ff0000)
 101 #define CSR5_BYTE3                      FIELD32(0xff000000)
 102
 103 /*
 104  * CSR6: BSSID register 1.
 105  */
 106 #define CSR6                            0x0018
 107 #define CSR6_BYTE4                      FIELD32(0x000000ff)
 108 #define CSR6_BYTE5                      FIELD32(0x0000ff00)
 109
 110 /*
 111  * CSR7: Interrupt source register.
 112  * Write 1 to clear interrupt.
 113  * TBCN_EXPIRE: Beacon timer expired interrupt.
 114  * TWAKE_EXPIRE: Wakeup timer expired interrupt.
 115  * TATIMW_EXPIRE: Timer of atim window expired interrupt.
 116  * TXDONE_TXRING: Tx ring transmit done interrupt.
 117  * TXDONE_ATIMRING: Atim ring transmit done interrupt.
 118  * TXDONE_PRIORING: Priority ring transmit done interrupt.
 119  * RXDONE: Receive done interrupt.
 120  */
 121 #define CSR7                            0x001c
 122 #define CSR7_TBCN_EXPIRE                FIELD32(0x00000001)
 123 #define CSR7_TWAKE_EXPIRE               FIELD32(0x00000002)
 124 #define CSR7_TATIMW_EXPIRE              FIELD32(0x00000004)
 125 #define CSR7_TXDONE_TXRING              FIELD32(0x00000008)
 126 #define CSR7_TXDONE_ATIMRING            FIELD32(0x00000010)
 127 #define CSR7_TXDONE_PRIORING            FIELD32(0x00000020)
 128 #define CSR7_RXDONE                     FIELD32(0x00000040)
 129
 130 /*
 131  * CSR8: Interrupt mask register.
 132  * Write 1 to mask interrupt.
 133  * TBCN_EXPIRE: Beacon timer expired interrupt.
 134  * TWAKE_EXPIRE: Wakeup timer expired interrupt.
 135  * TATIMW_EXPIRE: Timer of atim window expired interrupt.
 136  * TXDONE_TXRING: Tx ring transmit done interrupt.
 137  * TXDONE_ATIMRING: Atim ring transmit done interrupt.
 138  * TXDONE_PRIORING: Priority ring transmit done interrupt.
 139  * RXDONE: Receive done interrupt.
 140  */
 141 #define CSR8                            0x0020
 142 #define CSR8_TBCN_EXPIRE                FIELD32(0x00000001)
 143 #define CSR8_TWAKE_EXPIRE               FIELD32(0x00000002)
 144 #define CSR8_TATIMW_EXPIRE              FIELD32(0x00000004)
 145 #define CSR8_TXDONE_TXRING              FIELD32(0x00000008)
 146 #define CSR8_TXDONE_ATIMRING            FIELD32(0x00000010)
 147 #define CSR8_TXDONE_PRIORING            FIELD32(0x00000020)
 148 #define CSR8_RXDONE                     FIELD32(0x00000040)
 149
 150 /*
 151  * CSR9: Maximum frame length register.
 152  * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12.
 153  */
 154 #define CSR9                            0x0024
 155 #define CSR9_MAX_FRAME_UNIT             FIELD32(0x00000f80)
 156
 157 /*
 158  * CSR11: Back-off control register.
 159  * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
 160  * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
 161  * SLOT_TIME: Slot time, default is 20us for 802.11b.
 162  * LONG_RETRY: Long retry count.
 163  * SHORT_RETRY: Short retry count.
 164  */
 165 #define CSR11                           0x002c
 166 #define CSR11_CWMIN                     FIELD32(0x0000000f)
 167 #define CSR11_CWMAX                     FIELD32(0x000000f0)
 168 #define CSR11_SLOT_TIME                 FIELD32(0x00001f00)
 169 #define CSR11_LONG_RETRY                FIELD32(0x00ff0000)
 170 #define CSR11_SHORT_RETRY               FIELD32(0xff000000)
 171
 172 /*
 173  * CSR12: Synchronization configuration register 0.
 174  * All units in 1/16 TU.
 175  * BEACON_INTERVAL: Beacon interval, default is 100 TU.
 176  * CFPMAX_DURATION: Cfp maximum duration, default is 100 TU.
 177  */
 178 #define CSR12                           0x0030
 179 #define CSR12_BEACON_INTERVAL           FIELD32(0x0000ffff)
 180 #define CSR12_CFP_MAX_DURATION          FIELD32(0xffff0000)
 181
 182 /*
 183  * CSR13: Synchronization configuration register 1.
 184  * All units in 1/16 TU.
 185  * ATIMW_DURATION: Atim window duration.
 186  * CFP_PERIOD: Cfp period, default is 0 TU.
 187  */
 188 #define CSR13                           0x0034
 189 #define CSR13_ATIMW_DURATION            FIELD32(0x0000ffff)
 190 #define CSR13_CFP_PERIOD                FIELD32(0x00ff0000)
 191
 192 /*
 193  * CSR14: Synchronization control register.
 194  * TSF_COUNT: Enable tsf auto counting.
 195  * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
 196  * TBCN: Enable tbcn with reload value.
 197  * TCFP: Enable tcfp & cfp / cp switching.
 198  * TATIMW: Enable tatimw & atim window switching.
 199  * BEACON_GEN: Enable beacon generator.
 200  * CFP_COUNT_PRELOAD: Cfp count preload value.
 201  * TBCM_PRELOAD: Tbcn preload value in units of 64us.
 202  */
 203 #define CSR14                           0x0038
 204 #define CSR14_TSF_COUNT                 FIELD32(0x00000001)
 205 #define CSR14_TSF_SYNC                  FIELD32(0x00000006)
 206 #define CSR14_TBCN                      FIELD32(0x00000008)
 207 #define CSR14_TCFP                      FIELD32(0x00000010)
 208 #define CSR14_TATIMW                    FIELD32(0x00000020)
 209 #define CSR14_BEACON_GEN                FIELD32(0x00000040)
 210 #define CSR14_CFP_COUNT_PRELOAD         FIELD32(0x0000ff00)
 211 #define CSR14_TBCM_PRELOAD              FIELD32(0xffff0000)
 212
 213 /*
 214  * CSR15: Synchronization status register.
 215  * CFP: ASIC is in contention-free period.
 216  * ATIMW: ASIC is in ATIM window.
 217  * BEACON_SENT: Beacon is send.
 218  */
 219 #define CSR15                           0x003c
 220 #define CSR15_CFP                       FIELD32(0x00000001)
 221 #define CSR15_ATIMW                     FIELD32(0x00000002)
 222 #define CSR15_BEACON_SENT               FIELD32(0x00000004)
 223
 224 /*
 225  * CSR16: TSF timer register 0.
 226  */
 227 #define CSR16                           0x0040
 228 #define CSR16_LOW_TSFTIMER              FIELD32(0xffffffff)
 229
 230 /*
 231  * CSR17: TSF timer register 1.
 232  */
 233 #define CSR17                           0x0044
 234 #define CSR17_HIGH_TSFTIMER             FIELD32(0xffffffff)
 235
 236 /*
 237  * CSR18: IFS timer register 0.
 238  * SIFS: Sifs, default is 10 us.
 239  * PIFS: Pifs, default is 30 us.
 240  */
 241 #define CSR18                           0x0048
 242 #define CSR18_SIFS                      FIELD32(0x0000ffff)
 243 #define CSR18_PIFS                      FIELD32(0xffff0000)
 244
 245 /*
 246  * CSR19: IFS timer register 1.
 247  * DIFS: Difs, default is 50 us.
 248  * EIFS: Eifs, default is 364 us.
 249  */
 250 #define CSR19                           0x004c
 251 #define CSR19_DIFS                      FIELD32(0x0000ffff)
 252 #define CSR19_EIFS                      FIELD32(0xffff0000)
 253
 254 /*
 255  * CSR20: Wakeup timer register.
 256  * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU.
 257  * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
 258  * AUTOWAKE: Enable auto wakeup / sleep mechanism.
 259  */
 260 #define CSR20                           0x0050
 261 #define CSR20_DELAY_AFTER_TBCN          FIELD32(0x0000ffff)
 262 #define CSR20_TBCN_BEFORE_WAKEUP        FIELD32(0x00ff0000)
 263 #define CSR20_AUTOWAKE                  FIELD32(0x01000000)
 264
 265 /*
 266  * CSR21: EEPROM control register.
 267  * RELOAD: Write 1 to reload eeprom content.
 268  * TYPE_93C46: 1: 93c46, 0:93c66.
 269  */
 270 #define CSR21                           0x0054
 271 #define CSR21_RELOAD                    FIELD32(0x00000001)
 272 #define CSR21_EEPROM_DATA_CLOCK         FIELD32(0x00000002)
 273 #define CSR21_EEPROM_CHIP_SELECT        FIELD32(0x00000004)
 274 #define CSR21_EEPROM_DATA_IN            FIELD32(0x00000008)
 275 #define CSR21_EEPROM_DATA_OUT           FIELD32(0x00000010)
 276 #define CSR21_TYPE_93C46                FIELD32(0x00000020)
 277
 278 /*
 279  * CSR22: CFP control register.
 280  * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU.
 281  * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain.
 282  */
 283 #define CSR22                           0x0058
 284 #define CSR22_CFP_DURATION_REMAIN       FIELD32(0x0000ffff)
 285 #define CSR22_RELOAD_CFP_DURATION       FIELD32(0x00010000)
 286
 287 /*
 288  * Transmit related CSRs.
 289  * Some values are set in TU, whereas 1 TU == 1024 us.
 290  */
 291
 292 /*
 293  * TXCSR0: TX Control Register.
 294  * KICK_TX: Kick tx ring.
 295  * KICK_ATIM: Kick atim ring.
 296  * KICK_PRIO: Kick priority ring.
 297  * ABORT: Abort all transmit related ring operation.
 298  */
 299 #define TXCSR0                          0x0060
 300 #define TXCSR0_KICK_TX                  FIELD32(0x00000001)
 301 #define TXCSR0_KICK_ATIM                FIELD32(0x00000002)
 302 #define TXCSR0_KICK_PRIO                FIELD32(0x00000004)
 303 #define TXCSR0_ABORT                    FIELD32(0x00000008)
 304
 305 /*
 306  * TXCSR1: TX Configuration Register.
 307  * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps.
 308  * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps.
 309  * TSF_OFFSET: Insert tsf offset.
 310  * AUTORESPONDER: Enable auto responder which include ack & cts.
 311  */
 312 #define TXCSR1                          0x0064
 313 #define TXCSR1_ACK_TIMEOUT              FIELD32(0x000001ff)
 314 #define TXCSR1_ACK_CONSUME_TIME         FIELD32(0x0003fe00)
 315 #define TXCSR1_TSF_OFFSET               FIELD32(0x00fc0000)
 316 #define TXCSR1_AUTORESPONDER            FIELD32(0x01000000)
 317
 318 /*
 319  * TXCSR2: Tx descriptor configuration register.
 320  * TXD_SIZE: Tx descriptor size, default is 48.
 321  * NUM_TXD: Number of tx entries in ring.
 322  * NUM_ATIM: Number of atim entries in ring.
 323  * NUM_PRIO: Number of priority entries in ring.
 324  */
 325 #define TXCSR2                          0x0068
 326 #define TXCSR2_TXD_SIZE                 FIELD32(0x000000ff)
 327 #define TXCSR2_NUM_TXD                  FIELD32(0x0000ff00)
 328 #define TXCSR2_NUM_ATIM                 FIELD32(0x00ff0000)
 329 #define TXCSR2_NUM_PRIO                 FIELD32(0xff000000)
 330
 331 /*
 332  * TXCSR3: TX Ring Base address register.
 333  */
 334 #define TXCSR3                          0x006c
 335 #define TXCSR3_TX_RING_REGISTER         FIELD32(0xffffffff)
 336
 337 /*
 338  * TXCSR4: TX Atim Ring Base address register.
 339  */
 340 #define TXCSR4                          0x0070
 341 #define TXCSR4_ATIM_RING_REGISTER       FIELD32(0xffffffff)
 342
 343 /*
 344  * TXCSR5: TX Prio Ring Base address register.
 345  */
 346 #define TXCSR5                          0x0074
 347 #define TXCSR5_PRIO_RING_REGISTER       FIELD32(0xffffffff)
 348
 349 /*
 350  * TXCSR6: Beacon Base address register.
 351  */
 352 #define TXCSR6                          0x0078
 353 #define TXCSR6_BEACON_RING_REGISTER     FIELD32(0xffffffff)
 354
 355 /*
 356  * TXCSR7: Auto responder control register.
 357  * AR_POWERMANAGEMENT: Auto responder power management bit.
 358  */
 359 #define TXCSR7                          0x007c
 360 #define TXCSR7_AR_POWERMANAGEMENT       FIELD32(0x00000001)
 361
 362 /*
 363  * Receive related CSRs.
 364  * Some values are set in TU, whereas 1 TU == 1024 us.
 365  */
 366
 367 /*
 368  * RXCSR0: RX Control Register.
 369  * DISABLE_RX: Disable rx engine.
 370  * DROP_CRC: Drop crc error.
 371  * DROP_PHYSICAL: Drop physical error.
 372  * DROP_CONTROL: Drop control frame.
 373  * DROP_NOT_TO_ME: Drop not to me unicast frame.
 374  * DROP_TODS: Drop frame tods bit is true.
 375  * DROP_VERSION_ERROR: Drop version error frame.
 376  * PASS_CRC: Pass all packets with crc attached.
 377  */
 378 #define RXCSR0                          0x0080
 379 #define RXCSR0_DISABLE_RX               FIELD32(0x00000001)
 380 #define RXCSR0_DROP_CRC                 FIELD32(0x00000002)
 381 #define RXCSR0_DROP_PHYSICAL            FIELD32(0x00000004)
 382 #define RXCSR0_DROP_CONTROL             FIELD32(0x00000008)
 383 #define RXCSR0_DROP_NOT_TO_ME           FIELD32(0x00000010)
 384 #define RXCSR0_DROP_TODS                FIELD32(0x00000020)
 385 #define RXCSR0_DROP_VERSION_ERROR       FIELD32(0x00000040)
 386 #define RXCSR0_PASS_CRC                 FIELD32(0x00000080)
 387
 388 /*
 389  * RXCSR1: RX descriptor configuration register.
 390  * RXD_SIZE: Rx descriptor size, default is 32b.
 391  * NUM_RXD: Number of rx entries in ring.
 392  */
 393 #define RXCSR1                          0x0084
 394 #define RXCSR1_RXD_SIZE                 FIELD32(0x000000ff)
 395 #define RXCSR1_NUM_RXD                  FIELD32(0x0000ff00)
 396
 397 /*
 398  * RXCSR2: RX Ring base address register.
 399  */
 400 #define RXCSR2                          0x0088
 401 #define RXCSR2_RX_RING_REGISTER         FIELD32(0xffffffff)
 402
 403 /*
 404  * RXCSR3: BBP ID register for Rx operation.
 405  * BBP_ID#: BBP register # id.
 406  * BBP_ID#_VALID: BBP register # id is valid or not.
 407  */
 408 #define RXCSR3                          0x0090
 409 #define RXCSR3_BBP_ID0                  FIELD32(0x0000007f)
 410 #define RXCSR3_BBP_ID0_VALID            FIELD32(0x00000080)
 411 #define RXCSR3_BBP_ID1                  FIELD32(0x00007f00)
 412 #define RXCSR3_BBP_ID1_VALID            FIELD32(0x00008000)
 413 #define RXCSR3_BBP_ID2                  FIELD32(0x007f0000)
 414 #define RXCSR3_BBP_ID2_VALID            FIELD32(0x00800000)
 415 #define RXCSR3_BBP_ID3                  FIELD32(0x7f000000)
 416 #define RXCSR3_BBP_ID3_VALID            FIELD32(0x80000000)
 417
 418 /*
 419  * RXCSR4: BBP ID register for Rx operation.
 420  * BBP_ID#: BBP register # id.
 421  * BBP_ID#_VALID: BBP register # id is valid or not.
 422  */
 423 #define RXCSR4                          0x0094
 424 #define RXCSR4_BBP_ID4                  FIELD32(0x0000007f)
 425 #define RXCSR4_BBP_ID4_VALID            FIELD32(0x00000080)
 426 #define RXCSR4_BBP_ID5                  FIELD32(0x00007f00)
 427 #define RXCSR4_BBP_ID5_VALID            FIELD32(0x00008000)
 428
 429 /*
 430  * ARCSR0: Auto Responder PLCP config register 0.
 431  * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
 432  * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
 433  */
 434 #define ARCSR0                          0x0098
 435 #define ARCSR0_AR_BBP_DATA0             FIELD32(0x000000ff)
 436 #define ARCSR0_AR_BBP_ID0               FIELD32(0x0000ff00)
 437 #define ARCSR0_AR_BBP_DATA1             FIELD32(0x00ff0000)
 438 #define ARCSR0_AR_BBP_ID1               FIELD32(0xff000000)
 439
 440 /*
 441  * ARCSR1: Auto Responder PLCP config register 1.
 442  * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
 443  * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
 444  */
 445 #define ARCSR1                          0x009c
 446 #define ARCSR1_AR_BBP_DATA2             FIELD32(0x000000ff)
 447 #define ARCSR1_AR_BBP_ID2               FIELD32(0x0000ff00)
 448 #define ARCSR1_AR_BBP_DATA3             FIELD32(0x00ff0000)
 449 #define ARCSR1_AR_BBP_ID3               FIELD32(0xff000000)
 450
 451 /*
 452  * Miscellaneous Registers.
 453  * Some values are set in TU, whereas 1 TU == 1024 us.
 454  */
 455
 456 /*
 457  * PCICSR: PCI control register.
 458  * BIG_ENDIAN: 1: big endian, 0: little endian.
 459  * RX_TRESHOLD: Rx threshold in dw to start pci access
 460  * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
 461  * TX_TRESHOLD: Tx threshold in dw to start pci access
 462  * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
 463  * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
 464  * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
 465  */
 466 #define PCICSR                          0x008c
 467 #define PCICSR_BIG_ENDIAN               FIELD32(0x00000001)
 468 #define PCICSR_RX_TRESHOLD              FIELD32(0x00000006)
 469 #define PCICSR_TX_TRESHOLD              FIELD32(0x00000018)
 470 #define PCICSR_BURST_LENTH              FIELD32(0x00000060)
 471 #define PCICSR_ENABLE_CLK               FIELD32(0x00000080)
 472
 473 /*
 474  * CNT0: FCS error count.
 475  * FCS_ERROR: FCS error count, cleared when read.
 476  */
 477 #define CNT0                            0x00a0
 478 #define CNT0_FCS_ERROR                  FIELD32(0x0000ffff)
 479
 480 /*
 481  * Statistic Register.
 482  * CNT1: PLCP error count.
 483  * CNT2: Long error count.
 484  * CNT3: CCA false alarm count.
 485  * CNT4: Rx FIFO overflow count.
 486  * CNT5: Tx FIFO underrun count.
 487  */
 488 #define TIMECSR2                        0x00a8
 489 #define CNT1                            0x00ac
 490 #define CNT2                            0x00b0
 491 #define TIMECSR3                        0x00b4
 492 #define CNT3                            0x00b8
 493 #define CNT4                            0x00bc
 494 #define CNT5                            0x00c0
 495
 496 /*
 497  * Baseband Control Register.
 498  */
 499
 500 /*
 501  * PWRCSR0: Power mode configuration register.
 502  */
 503 #define PWRCSR0                         0x00c4
 504
 505 /*
 506  * Power state transition time registers.
 507  */
 508 #define PSCSR0                          0x00c8
 509 #define PSCSR1                          0x00cc
 510 #define PSCSR2                          0x00d0
 511 #define PSCSR3                          0x00d4
 512
 513 /*
 514  * PWRCSR1: Manual power control / status register.
 515  * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
 516  * SET_STATE: Set state. Write 1 to trigger, self cleared.
 517  * BBP_DESIRE_STATE: BBP desired state.
 518  * RF_DESIRE_STATE: RF desired state.
 519  * BBP_CURR_STATE: BBP current state.
 520  * RF_CURR_STATE: RF current state.
 521  * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
 522  */
 523 #define PWRCSR1                         0x00d8
 524 #define PWRCSR1_SET_STATE               FIELD32(0x00000001)
 525 #define PWRCSR1_BBP_DESIRE_STATE        FIELD32(0x00000006)
 526 #define PWRCSR1_RF_DESIRE_STATE         FIELD32(0x00000018)
 527 #define PWRCSR1_BBP_CURR_STATE          FIELD32(0x00000060)
 528 #define PWRCSR1_RF_CURR_STATE           FIELD32(0x00000180)
 529 #define PWRCSR1_PUT_TO_SLEEP            FIELD32(0x00000200)
 530
 531 /*
 532  * TIMECSR: Timer control register.
 533  * US_COUNT: 1 us timer count in units of clock cycles.
 534  * US_64_COUNT: 64 us timer count in units of 1 us timer.
 535  * BEACON_EXPECT: Beacon expect window.
 536  */
 537 #define TIMECSR                         0x00dc
 538 #define TIMECSR_US_COUNT                FIELD32(0x000000ff)
 539 #define TIMECSR_US_64_COUNT             FIELD32(0x0000ff00)
 540 #define TIMECSR_BEACON_EXPECT           FIELD32(0x00070000)
 541
 542 /*
 543  * MACCSR0: MAC configuration register 0.
 544  */
 545 #define MACCSR0                         0x00e0
 546
 547
 548 /*
 549  * MACCSR1: MAC configuration register 1.
 550  * KICK_RX: Kick one-shot rx in one-shot rx mode.
 551  * ONESHOT_RXMODE: Enable one-shot rx mode for debugging.
 552  * BBPRX_RESET_MODE: Ralink bbp rx reset mode.
 553  * AUTO_TXBBP: Auto tx logic access bbp control register.
 554  * AUTO_RXBBP: Auto rx logic access bbp control register.
 555  * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
 556  * INTERSIL_IF: Intersil if calibration pin.
 557  */
 558 #define MACCSR1                         0x00e4
 559 #define MACCSR1_KICK_RX                 FIELD32(0x00000001)
 560 #define MACCSR1_ONESHOT_RXMODE          FIELD32(0x00000002)
 561 #define MACCSR1_BBPRX_RESET_MODE        FIELD32(0x00000004)
 562 #define MACCSR1_AUTO_TXBBP              FIELD32(0x00000008)
 563 #define MACCSR1_AUTO_RXBBP              FIELD32(0x00000010)
 564 #define MACCSR1_LOOPBACK                FIELD32(0x00000060)
 565 #define MACCSR1_INTERSIL_IF             FIELD32(0x00000080)
 566
 567 /*
 568  * RALINKCSR: Ralink Rx auto-reset BBCR.
 569  * AR_BBP_DATA#: Auto reset BBP register # data.
 570  * AR_BBP_ID#: Auto reset BBP register # id.
 571  */
 572 #define RALINKCSR                       0x00e8
 573 #define RALINKCSR_AR_BBP_DATA0          FIELD32(0x000000ff)
 574 #define RALINKCSR_AR_BBP_ID0            FIELD32(0x0000ff00)
 575 #define RALINKCSR_AR_BBP_DATA1          FIELD32(0x00ff0000)
 576 #define RALINKCSR_AR_BBP_ID1            FIELD32(0xff000000)
 577
 578 /*
 579  * BCNCSR: Beacon interval control register.
 580  * CHANGE: Write one to change beacon interval.
 581  * DELTATIME: The delta time value.
 582  * NUM_BEACON: Number of beacon according to mode.
 583  * MODE: Please refer to asic specs.
 584  * PLUS: Plus or minus delta time value.
 585  */
 586 #define BCNCSR                          0x00ec
 587 #define BCNCSR_CHANGE                   FIELD32(0x00000001)
 588 #define BCNCSR_DELTATIME                FIELD32(0x0000001e)
 589 #define BCNCSR_NUM_BEACON               FIELD32(0x00001fe0)
 590 #define BCNCSR_MODE                     FIELD32(0x00006000)
 591 #define BCNCSR_PLUS                     FIELD32(0x00008000)
 592
 593 /*
 594  * BBP / RF / IF Control Register.
 595  */
 596
 597 /*
 598  * BBPCSR: BBP serial control register.
 599  * VALUE: Register value to program into BBP.
 600  * REGNUM: Selected BBP register.
 601  * BUSY: 1: asic is busy execute BBP programming.
 602  * WRITE_CONTROL: 1: write BBP, 0: read BBP.
 603  */
 604 #define BBPCSR                          0x00f0
 605 #define BBPCSR_VALUE                    FIELD32(0x000000ff)
 606 #define BBPCSR_REGNUM                   FIELD32(0x00007f00)
 607 #define BBPCSR_BUSY                     FIELD32(0x00008000)
 608 #define BBPCSR_WRITE_CONTROL            FIELD32(0x00010000)
 609
 610 /*
 611  * RFCSR: RF serial control register.
 612  * VALUE: Register value + id to program into rf/if.
 613  * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
 614  * IF_SELECT: Chip to program: 0: rf, 1: if.
 615  * PLL_LD: Rf pll_ld status.
 616  * BUSY: 1: asic is busy execute rf programming.
 617  */
 618 #define RFCSR                           0x00f4
 619 #define RFCSR_VALUE                     FIELD32(0x00ffffff)
 620 #define RFCSR_NUMBER_OF_BITS            FIELD32(0x1f000000)
 621 #define RFCSR_IF_SELECT                 FIELD32(0x20000000)
 622 #define RFCSR_PLL_LD                    FIELD32(0x40000000)
 623 #define RFCSR_BUSY                      FIELD32(0x80000000)
 624
 625 /*
 626  * LEDCSR: LED control register.
 627  * ON_PERIOD: On period, default 70ms.
 628  * OFF_PERIOD: Off period, default 30ms.
 629  * LINK: 0: linkoff, 1: linkup.
 630  * ACTIVITY: 0: idle, 1: active.
 631  */
 632 #define LEDCSR                          0x00f8
 633 #define LEDCSR_ON_PERIOD                FIELD32(0x000000ff)
 634 #define LEDCSR_OFF_PERIOD               FIELD32(0x0000ff00)
 635 #define LEDCSR_LINK                     FIELD32(0x00010000)
 636 #define LEDCSR_ACTIVITY                 FIELD32(0x00020000)
 637
 638 /*
 639  * ASIC pointer information.
 640  * RXPTR: Current RX ring address.
 641  * TXPTR: Current Tx ring address.
 642  * PRIPTR: Current Priority ring address.
 643  * ATIMPTR: Current ATIM ring address.
 644  */
 645 #define RXPTR                           0x0100
 646 #define TXPTR                           0x0104
 647 #define PRIPTR                          0x0108
 648 #define ATIMPTR                         0x010c
 649
 650 /*
 651  * GPIO and others.
 652  */
 653
 654 /*
 655  * GPIOCSR: GPIO control register.
 656  */
 657 #define GPIOCSR                         0x0120
 658 #define GPIOCSR_BIT0                    FIELD32(0x00000001)
 659 #define GPIOCSR_BIT1                    FIELD32(0x00000002)
 660 #define GPIOCSR_BIT2                    FIELD32(0x00000004)
 661 #define GPIOCSR_BIT3                    FIELD32(0x00000008)
 662 #define GPIOCSR_BIT4                    FIELD32(0x00000010)
 663 #define GPIOCSR_BIT5                    FIELD32(0x00000020)
 664 #define GPIOCSR_BIT6                    FIELD32(0x00000040)
 665 #define GPIOCSR_BIT7                    FIELD32(0x00000080)
 666
 667 /*
 668  * BBPPCSR: BBP Pin control register.
 669  */
 670 #define BBPPCSR                         0x0124
 671
 672 /*
 673  * BCNCSR1: Tx BEACON offset time control register.
 674  * PRELOAD: Beacon timer offset in units of usec.
 675  */
 676 #define BCNCSR1                         0x0130
 677 #define BCNCSR1_PRELOAD                 FIELD32(0x0000ffff)
 678
 679 /*
 680  * MACCSR2: TX_PE to RX_PE turn-around time control register
 681  * DELAY: RX_PE low width, in units of pci clock cycle.
 682  */
 683 #define MACCSR2                         0x0134
 684 #define MACCSR2_DELAY                   FIELD32(0x000000ff)
 685
 686 /*
 687  * ARCSR2: 1 Mbps ACK/CTS PLCP.
 688  */
 689 #define ARCSR2                          0x013c
 690 #define ARCSR2_SIGNAL                   FIELD32(0x000000ff)
 691 #define ARCSR2_SERVICE                  FIELD32(0x0000ff00)
 692 #define ARCSR2_LENGTH_LOW               FIELD32(0x00ff0000)
 693 #define ARCSR2_LENGTH                   FIELD32(0xffff0000)
 694
 695 /*
 696  * ARCSR3: 2 Mbps ACK/CTS PLCP.
 697  */
 698 #define ARCSR3                          0x0140
 699 #define ARCSR3_SIGNAL                   FIELD32(0x000000ff)
 700 #define ARCSR3_SERVICE                  FIELD32(0x0000ff00)
 701 #define ARCSR3_LENGTH                   FIELD32(0xffff0000)
 702
 703 /*
 704  * ARCSR4: 5.5 Mbps ACK/CTS PLCP.
 705  */
 706 #define ARCSR4                          0x0144
 707 #define ARCSR4_SIGNAL                   FIELD32(0x000000ff)
 708 #define ARCSR4_SERVICE                  FIELD32(0x0000ff00)
 709 #define ARCSR4_LENGTH                   FIELD32(0xffff0000)
 710
 711 /*
 712  * ARCSR5: 11 Mbps ACK/CTS PLCP.
 713  */
 714 #define ARCSR5                          0x0148
 715 #define ARCSR5_SIGNAL                   FIELD32(0x000000ff)
 716 #define ARCSR5_SERVICE                  FIELD32(0x0000ff00)
 717 #define ARCSR5_LENGTH                   FIELD32(0xffff0000)
 718
 719 /*
 720  * RF registers
 721  */
 722 #define RF1_TUNER                       FIELD32(0x00020000)
 723 #define RF3_TUNER                       FIELD32(0x00000100)
 724 #define RF3_TXPOWER                     FIELD32(0x00003e00)
 725
 726 /*
 727  * EEPROM content.
 728  * The wordsize of the EEPROM is 16 bits.
 729  */
 730
 731 /*
 732  * HW MAC address.
 733  */
 734 #define EEPROM_MAC_ADDR_0               0x0002
 735 #define EEPROM_MAC_ADDR_BYTE0           FIELD16(0x00ff)
 736 #define EEPROM_MAC_ADDR_BYTE1           FIELD16(0xff00)
 737 #define EEPROM_MAC_ADDR1                0x0003
 738 #define EEPROM_MAC_ADDR_BYTE2           FIELD16(0x00ff)
 739 #define EEPROM_MAC_ADDR_BYTE3           FIELD16(0xff00)
 740 #define EEPROM_MAC_ADDR_2               0x0004
 741 #define EEPROM_MAC_ADDR_BYTE4           FIELD16(0x00ff)
 742 #define EEPROM_MAC_ADDR_BYTE5           FIELD16(0xff00)
 743
 744 /*
 745  * EEPROM antenna.
 746  * ANTENNA_NUM: Number of antenna's.
 747  * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
 748  * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
 749  * RF_TYPE: Rf_type of this adapter.
 750  * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
 751  * RX_AGCVGC: 0: disable, 1:enable BBP R13 tuning.
 752  * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
 753  */
 754 #define EEPROM_ANTENNA                  0x0b
 755 #define EEPROM_ANTENNA_NUM              FIELD16(0x0003)
 756 #define EEPROM_ANTENNA_TX_DEFAULT       FIELD16(0x000c)
 757 #define EEPROM_ANTENNA_RX_DEFAULT       FIELD16(0x0030)
 758 #define EEPROM_ANTENNA_RF_TYPE          FIELD16(0x0040)
 759 #define EEPROM_ANTENNA_LED_MODE         FIELD16(0x0180)
 760 #define EEPROM_ANTENNA_RX_AGCVGC_TUNING FIELD16(0x0200)
 761 #define EEPROM_ANTENNA_HARDWARE_RADIO   FIELD16(0x0400)
 762
 763 /*
 764  * EEPROM BBP.
 765  */
 766 #define EEPROM_BBP_START                0x0c
 767 #define EEPROM_BBP_SIZE                 7
 768 #define EEPROM_BBP_VALUE                FIELD16(0x00ff)
 769 #define EEPROM_BBP_REG_ID               FIELD16(0xff00)
 770
 771 /*
 772  * EEPROM TXPOWER
 773  */
 774 #define EEPROM_TXPOWER_START            0x13
 775 #define EEPROM_TXPOWER_SIZE             7
 776 #define EEPROM_TXPOWER_1                FIELD16(0x00ff)
 777 #define EEPROM_TXPOWER_2                FIELD16(0xff00)
 778
 779 /*
 780  * BBP content.
 781  * The wordsize of the BBP is 8 bits.
 782  */
 783
 784 /*
 785  * BBP_R1: TX antenna control
 786  */
 787 #define BBP_R1_TX_ANTENNA               FIELD8(0x03)
 788
 789 /*
 790  * BBP_R4: RX antenna control
 791  */
 792 #define BBP_R4_RX_ANTENNA               FIELD8(0x06)
 793
 794 /*
 795  * DMA descriptor defines.
 796  */
 797 #define TXD_DESC_SIZE                   ( 8 * sizeof(struct data_desc) )
 798 #define RXD_DESC_SIZE                   ( 8 * sizeof(struct data_desc) )
 799
 800 /*
 801  * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
 802  */
 803
 804 /*
 805  * Word0
 806  */
 807 #define TXD_W0_OWNER_NIC                FIELD32(0x00000001)
 808 #define TXD_W0_VALID                    FIELD32(0x00000002)
 809 #define TXD_W0_RESULT                   FIELD32(0x0000001c)
 810 #define TXD_W0_RETRY_COUNT              FIELD32(0x000000e0)
 811 #define TXD_W0_MORE_FRAG                FIELD32(0x00000100)
 812 #define TXD_W0_ACK                      FIELD32(0x00000200)
 813 #define TXD_W0_TIMESTAMP                FIELD32(0x00000400)
 814 #define TXD_W0_RTS                      FIELD32(0x00000800)
 815 #define TXD_W0_IFS                      FIELD32(0x00006000)
 816 #define TXD_W0_RETRY_MODE               FIELD32(0x00008000)
 817 #define TXD_W0_AGC                      FIELD32(0x00ff0000)
 818 #define TXD_W0_R2                       FIELD32(0xff000000)
 819
 820 /*
 821  * Word1
 822  */
 823 #define TXD_W1_BUFFER_ADDRESS           FIELD32(0xffffffff)
 824
 825 /*
 826  * Word2
 827  */
 828 #define TXD_W2_BUFFER_LENGTH            FIELD32(0x0000ffff)
 829 #define TXD_W2_DATABYTE_COUNT           FIELD32(0xffff0000)
 830
 831 /*
 832  * Word3 & 4: PLCP information
 833  */
 834 #define TXD_W3_PLCP_SIGNAL              FIELD32(0x0000ffff)
 835 #define TXD_W3_PLCP_SERVICE             FIELD32(0xffff0000)
 836 #define TXD_W4_PLCP_LENGTH_LOW          FIELD32(0x0000ffff)
 837 #define TXD_W4_PLCP_LENGTH_HIGH         FIELD32(0xffff0000)
 838
 839 /*
 840  * Word5
 841  */
 842 #define TXD_W5_BBCR4                    FIELD32(0x0000ffff)
 843 #define TXD_W5_AGC_REG                  FIELD32(0x007f0000)
 844 #define TXD_W5_AGC_REG_VALID            FIELD32(0x00800000)
 845 #define TXD_W5_XXX_REG                  FIELD32(0x7f000000)
 846 #define TXD_W5_XXX_REG_VALID            FIELD32(0x80000000)
 847
 848 /*
 849  * Word6
 850  */
 851 #define TXD_W6_SK_BUFF                  FIELD32(0xffffffff)
 852
 853 /*
 854  * Word7
 855  */
 856 #define TXD_W7_RESERVED                 FIELD32(0xffffffff)
 857
 858 /*
 859  * RX descriptor format for RX Ring.
 860  */
 861
 862 /*
 863  * Word0
 864  */
 865 #define RXD_W0_OWNER_NIC                FIELD32(0x00000001)
 866 #define RXD_W0_UNICAST_TO_ME            FIELD32(0x00000002)
 867 #define RXD_W0_MULTICAST                FIELD32(0x00000004)
 868 #define RXD_W0_BROADCAST                FIELD32(0x00000008)
 869 #define RXD_W0_MY_BSS                   FIELD32(0x00000010)
 870 #define RXD_W0_CRC                      FIELD32(0x00000020)
 871 #define RXD_W0_PHYSICAL_ERROR           FIELD32(0x00000080)
 872 #define RXD_W0_DATABYTE_COUNT           FIELD32(0xffff0000)
 873
 874 /*
 875  * Word1
 876  */
 877 #define RXD_W1_BUFFER_ADDRESS           FIELD32(0xffffffff)
 878
 879 /*
 880  * Word2
 881  */
 882 #define RXD_W2_BUFFER_LENGTH            FIELD32(0x0000ffff)
 883 #define RXD_W2_SIGNAL                   FIELD32(0x00ff0000)
 884 #define RXD_W2_RSSI                     FIELD32(0xff000000)
 885
 886 /*
 887  * Word3
 888  */
 889 #define RXD_W3_BBR2                     FIELD32(0x000000ff)
 890 #define RXD_W3_BBR3                     FIELD32(0x0000ff00)
 891 #define RXD_W3_BBR4                     FIELD32(0x00ff0000)
 892 #define RXD_W3_BBR5                     FIELD32(0xff000000)
 893
 894 /*
 895  * Word4
 896  */
 897 #define RXD_W4_RX_END_TIME              FIELD32(0xffffffff)
 898
 899 /*
 900  * Word5 & 6 & 7: Reserved
 901  */
 902 #define RXD_W5_RESERVED                 FIELD32(0xffffffff)
 903 #define RXD_W6_RESERVED                 FIELD32(0xffffffff)
 904 #define RXD_W7_RESERVED                 FIELD32(0xffffffff)
 905
 906 /*
 907  * Macro's for converting txpower from EEPROM to dscape value
 908  * and from dscape value to register value.
 909  * NOTE: Logics in rt2400pci for txpower are reversed
 910  * compared to the other rt2x00 drivers. A higher txpower
 911  * value means that the txpower must be lowered. This is
 912  * important when converting the value coming from the
 913  * dscape stack to the rt2400 acceptable value.
 914  */
 915 #define MIN_TXPOWER     31
 916 #define MAX_TXPOWER     62
 917 #define DEFAULT_TXPOWER 39
 918
 919 #define TXPOWER_FROM_DEV(__txpower)                                     \
 920 ({                                                                      \
 921         ((__txpower) > MAX_TXPOWER) ? DEFAULT_TXPOWER - MIN_TXPOWER :   \
 922         ((__txpower) < MIN_TXPOWER) ? DEFAULT_TXPOWER - MIN_TXPOWER :   \
 923         (((__txpower) - MAX_TXPOWER) + MIN_TXPOWER);                    \
 924 })
 925
 926 #define TXPOWER_TO_DEV(__txpower)                       \
 927 ({                                                      \
 928         (__txpower) += MIN_TXPOWER;                     \
 929         ((__txpower) <= MIN_TXPOWER) ? MAX_TXPOWER :    \
 930         (((__txpower) >= MAX_TXPOWER) ? MIN_TXPOWER :   \
 931         (MAX_TXPOWER - ((__txpower) - MIN_TXPOWER)));   \
 932 })
 933
 934 #endif /* RT2400PCI_H */