target/linux/ep93xx/patches-2.6.30/007-ep93xx-eth.patch

   1 --- /dev/null
   2 +++ b/drivers/net/arm/ep93xx_eth.h
   3 @@ -0,0 +1,402 @@
   4 +/*------------------------------------------------------------------------
   5 + * ep93xx_eth.h
   6 + * : header file of Ethernet Device Driver for Cirrus Logic EP93xx.
   7 + *
   8 + * Copyright (C) 2003 by Cirrus Logic www.cirrus.com
   9 + * This software may be used and distributed according to the terms
  10 + * of the GNU Public License.
  11 + *
  12 + * This file contains device related information like register info
  13 + * and register access method macros for the Ethernet device
  14 + * embedded within Cirrus Logic's EP93xx SOC chip.
  15 + *
  16 + * Information contained in this file was obtained from
  17 + * the EP9312 Manual Revision 0.12 and 0.14 from Cirrus Logic.
  18 + *
  19 + * History
  20 + * 05/18/01  Sungwook Kim  Initial release
  21 + * 03/25/2003  Melody Modified for EP92xx
  22 + *--------------------------------------------------------------------------*/
  23 +
  24 +
  25 +#ifndef _EP9213_ETH_H_
  26 +#define _EP9213_ETH_H_
  27 +
  28 +
  29 +/*---------------------------------------------------------------
  30 + *  Definition of H/W Defects and Their Workarounds
  31 + *-------------------------------------------------------------*/
  32 +
  33 +
  34 +
  35 +/*---------------------------------------------------------------
  36 + *  Data types used in this driver
  37 + *-------------------------------------------------------------*/
  38 +typedef  unsigned char   U8;
  39 +typedef  unsigned short  U16;
  40 +typedef  unsigned long   U32;
  41 +typedef  unsigned int    UINT;
  42 +
  43 +
  44 +
  45 +/*---------------------------------------------------------------
  46 + * Definition of the registers.
  47 + * For details, refer to the datasheet  .
  48 + *
  49 + * Basically, most registers are 32 bits width register.
  50 + * But some are 16 bits and some are 6 or 8 bytes long.
  51 + *-------------------------------------------------------------*/
  52 +
  53 +#define  REG_RxCTL  0x0000  /*offset to Receiver Control Reg*/
  54 +#define  RxCTL_PauseA  (1<<20)
  55 +#define  RxCTL_RxFCE1  (1<<19)
  56 +#define  RxCTL_RxFCE0  (1<<18)
  57 +#define  RxCTL_BCRC    (1<<17)
  58 +#define  RxCTL_SRxON   (1<<16)
  59 +#define  RxCTL_RCRCA   (1<<13)
  60 +#define  RxCTL_RA      (1<<12)
  61 +#define  RxCTL_PA      (1<<11)
  62 +#define  RxCTL_BA      (1<<10)
  63 +#define  RxCTL_MA      (1<<9)
  64 +#define  RxCTL_IAHA    (1<<8)
  65 +#define  RxCTL_IA3     (1<<3)
  66 +#define  RxCTL_IA2     (1<<2)
  67 +#define  RxCTL_IA1     (1<<1)
  68 +#define  RxCTL_IA0     (1<<0)
  69 +
  70 +#define  REG_TxCTL  0x0004  /*offset to Transmit Control Reg*/
  71 +#define  TxCTL_DefDis  (1<<7)
  72 +#define  TxCTL_MBE     (1<<6)
  73 +#define  TxCTL_ICRC    (1<<5)
  74 +#define  TxCTL_TxPD    (1<<5)
  75 +#define  TxCTL_OColl   (1<<3)
  76 +#define  TxCTL_SP      (1<<2)
  77 +#define  TxCTL_PB      (1<<1)
  78 +#define  TxCTL_STxON   (1<<0)
  79 +
  80 +#define  REG_TestCTL   0x0008  /*Test Control Reg, R/W*/
  81 +#define  TestCTL_MACF  (1<<7)
  82 +#define  TestCTL_MFDX  (1<<6)
  83 +#define  TestCTL_DB    (1<<5)
  84 +#define  TestCTL_MIIF  (1<<4)
  85 +
  86 +#define  REG_MIICmd  0x0010  /*offset to MII Command Reg, R/W*/
  87 +#define  MIICmd_OP     (0x03<<14)
  88 +#define  MIICmd_OP_RD  (2<<14)
  89 +#define  MIICmd_OP_WR  (1<<14)
  90 +#define  MIICmd_PHYAD  (0x1f<<5)
  91 +#define  MIICmd_REGAD  (0x1f<<0)
  92 +
  93 +#define  REG_MIIData  0x0014  /*offset to MII Data Reg, R/W*/
  94 +#define  MIIData_MIIData  (0xffff<<0)
  95 +
  96 +#define  REG_MIISts  0x0018  /*offset to MII Status Reg, R*/
  97 +#define  MIISts_Busy  (1<<0)
  98 +
  99 +#define  REG_SelfCTL  0x0020  /*offset to Self Control Reg*/
 100 +#define  SelfCTL_RWP    (1<<7)    /*Remote Wake Pin*/
 101 +#define  SelfCTL_GPO0   (1<<5)
 102 +#define  SelfCTL_PUWE   (1<<4)
 103 +#define  SelfCTL_PDWE   (1<<3)
 104 +#define  SelfCTL_MIIL   (1<<2)
 105 +#define  SelfCTL_RESET  (1<<0)
 106 +
 107 +#define  REG_IntEn   0x0024  /*Interrupt Enable Reg, R/W*/
 108 +#define  IntEn_RWIE    (1<<30)
 109 +#define  IntEn_RxMIE   (1<<29)
 110 +#define  IntEn_RxBIE   (1<<28)
 111 +#define  IntEn_RxSQIE  (1<<27)
 112 +#define  IntEn_TxLEIE  (1<<26)
 113 +#define  IntEn_ECIE    (1<<25)
 114 +#define  IntEn_TxUHIE  (1<<24)
 115 +#define  IntEn_MOIE    (1<<18)
 116 +#define  IntEn_TxCOIE  (1<<17)
 117 +#define  IntEn_RxROIE  (1<<16)
 118 +#define  IntEn_MIIIE   (1<<12)
 119 +#define  IntEn_PHYSIE  (1<<11)
 120 +#define  IntEn_TIE     (1<<10)
 121 +#define  IntEn_SWIE    (1<<8)
 122 +#define  IntEn_TxSQIE   (1<<3)
 123 +#define  IntEn_RxEOFIE  (1<<2)
 124 +#define  IntEn_RxEOBIE  (1<<1)
 125 +#define  IntEn_RxHDRIE  (1<<0)
 126 +
 127 +#define  REG_IntStsP  0x0028  /*offset to Interrupt Status Preserve Reg, R/W*/
 128 +#define  REG_IntStsC  0x002c  /*offset to Interrupt Status Clear Reg, R*/
 129 +#define  IntSts_RWI    (1<<30)
 130 +#define  IntSts_RxMI   (1<<29)
 131 +#define  IntSts_RxBI   (1<<28)
 132 +#define  IntSts_RxSQI  (1<<27)
 133 +#define  IntSts_TxLEI  (1<<26)
 134 +#define  IntSts_ECI    (1<<25)
 135 +#define  IntSts_TxUHI  (1<<24)
 136 +#define  IntSts_MOI    (1<<18)
 137 +#define  IntSts_TxCOI  (1<<17)
 138 +#define  IntSts_RxROI  (1<<16)
 139 +#define  IntSts_MIII   (1<<12)
 140 +#define  IntSts_PHYSI  (1<<11)
 141 +#define  IntSts_TI     (1<<10)
 142 +#define  IntSts_AHBE   (1<<9)
 143 +#define  IntSts_SWI    (1<<8)
 144 +#define  IntSts_OTHER  (1<<4)
 145 +#define  IntSts_TxSQ   (1<<3)
 146 +#define  IntSts_RxSQ   (1<<2)
 147 +
 148 +#define  REG_GT  0x0040  /*offset to General Timer Reg*/
 149 +#define  GT_GTC  (0xffff<<16)
 150 +#define  GT_GTP  (0xffff<<0)
 151 +
 152 +#define  REG_FCT  0x0044  /*offset to Flow Control Timer Reg*/
 153 +#define  FCT_FCT  (0x00ffffff<<0)
 154 +
 155 +#define  REG_FCF  0x0048  /*offset to Flow Control Format Reg*/
 156 +#define  FCF_MACCT  (0xffff<<16)
 157 +#define  FCF_TPT    (0xffff<<0)
 158 +
 159 +#define  REG_AFP  0x004c  /*offset to Address Filter Pointer Reg*/
 160 +#define  AFP_AFP  (0x07<<0)  /*Address Filter Pointer (bank control for REG_IndAD)*/
 161 +#define  AFP_AFP_IA0   0       /*Primary Individual Address (MAC Addr)*/
 162 +#define  AFP_AFP_IA1   1       /*Individual Address 1*/
 163 +#define  AFP_AFP_IA2   2       /*Individual Address 2*/
 164 +#define  AFP_AFP_IA3   3       /*Individual Address 3*/
 165 +#define  AFP_AFP_DTxP  6       /*Destination Address of Tx Pause Frame*/
 166 +#define  AFP_AFP_HASH  7       /*Hash Table*/
 167 +
 168 +#define  REG_IndAD      0x0050  /*offset to Individual Address Reg, n bytes, R/W*/
 169 +
 170 +#define  REG_GIntSts    0x0060  /*offset to Global Interrupt Status Reg (writing 1 will clear)*/
 171 +#define  REG_GIntROS    0x0068  /*offset to Global Interrupt Status Read Only Reg*/
 172 +#define  GIntSts_INT  (1<<15)     /*Global Interrupt Request Status*/
 173 +
 174 +#define  REG_GIntMsk    0x0064  /*offset to Global Interrupt Mask Reg*/
 175 +#define  GIntMsk_IntEn  (1<<15)   /*Global Interrupt Enable*/
 176 +
 177 +#define  REG_GIntFrc    0x006c  /*offset to Global Interrupt Force Reg*/
 178 +#define  GIntFrc_INT  (1<<15)     /*Force to set GIntSts*/
 179 +
 180 +#define  REG_TxCollCnt  0x0070  /*Transmit Collision Count Reg, R*/
 181 +#define  REG_RxMissCnt  0x0074  /*Receive Miss Count Reg, R*/
 182 +#define  REG_RxRntCnt   0x0078  /*Receive Runt Count Reg, R*/
 183 +
 184 +#define  REG_BMCtl  0x0080  /*offset to Bus Master Control Reg, R/W*/
 185 +#define  BMCtl_MT     (1<<13)
 186 +#define  BMCtl_TT     (1<<12)
 187 +#define  BMCtl_UnH    (1<<11)
 188 +#define  BMCtl_TxChR  (1<<10)
 189 +#define  BMCtl_TxDis  (1<<9)
 190 +#define  BMCtl_TxEn   (1<<8)
 191 +#define  BMCtl_EH2    (1<<6)
 192 +#define  BMCtl_EH1    (1<<5)
 193 +#define  BMCtl_EEOB   (1<<4)
 194 +#define  BMCtl_RxChR  (1<<2)
 195 +#define  BMCtl_RxDis  (1<<1)
 196 +#define  BMCtl_RxEn   (1<<0)
 197 +
 198 +#define  REG_BMSts  0x0084  /*offset to Bus Master Status Reg, R*/
 199 +#define  BMSts_TxAct  (1<<7)
 200 +#define  BMSts_TP     (1<<4)
 201 +#define  BMSts_RxAct  (1<<3)
 202 +#define  BMSts_QID    (0x07<<0)
 203 +#define  BMSts_QID_RxDt   (0<<0)
 204 +#define  BMSts_QID_TxDt   (1<<0)
 205 +#define  BMSts_QID_RxSts  (2<<0)
 206 +#define  BMSts_QID_TxSts  (3<<0)
 207 +#define  BMSts_QID_RxDesc (4<<0)
 208 +#define  BMSts_QID_TxDesc (5<<0)
 209 +
 210 +#define  REG_RBCA   0x0088  /*offset to Receive Buffer Current Address Reg, R*/
 211 +#define  REG_TBCA   0x008c  /*offset to Transmit Buffer Current Address Reg, R*/
 212 +
 213 +#define  REG_RxDBA  0x0090  /*offset to Receive Descriptor Queue Base Address Reg, R/W*/
 214 +#define  REG_RxDBL  0x0094  /*offset to Receive Descriptor Queue Base Length Reg, R/W, 16bits*/
 215 +#define  REG_RxDCL  0x0096  /*offset to Receive Descriptor Queue Current Length Reg, R/W, 16bits*/
 216 +#define  REG_RxDCA  0x0098  /*offset to Receive Descriptor Queue Current Address Reg, R/W*/
 217 +
 218 +#define  REG_RxDEQ  0x009c  /*offset to Receive Descriptor Enqueue Reg, R/W*/
 219 +#define  RxDEQ_RDV  (0xffff<<16)  /*R 16bit; Receive Descriptor Value*/
 220 +#define  RxDEQ_RDI  (0xff<<0)     /*W 8bit; Receive Descriptor Increment*/
 221 +
 222 +#define  REG_RxSBA  0x00a0  /*offset to Receive Status Queue Base Address Reg, R/W*/
 223 +#define  REG_RxSBL  0x00a4  /*offset to Receive Status Queue Base Length Reg, R/W, 16bits*/
 224 +#define  REG_RxSCL  0x00a6  /*offset to Receive Status Queue Current Length Reg, R/W, 16bits*/
 225 +#define  REG_RxSCA  0x00a8  /*offset to Receive Status Queue Current Address Reg, R/W*/
 226 +
 227 +#define  REG_RxSEQ  0x00ac  /*offset to Receive Status Queue Current Address Reg, R/W*/
 228 +#define  RxSEQ_RSV  (0xffff<<16)
 229 +#define  RxSEQ_RSI  (0xff<<0)
 230 +
 231 +#define  REG_TxDBA  0x00b0  /*offset to Transmit Descriptor Queue Base Address Reg, R/W*/
 232 +#define  REG_TxDBL  0x00b4  /*offset to Transmit Descriptor Queue Base Length Reg, R/W, 16bits*/
 233 +#define  REG_TxDCL  0x00b6  /*offset to Transmit Descriptor Queue Current Length Reg, R/W, 16bits*/
 234 +#define  REG_TxDCA  0x00b8  /*offset to Transmit Descriptor Queue Current Address Reg, R/W*/
 235 +
 236 +#define  REG_TxDEQ  0x00bc  /*offset to Transmit Descriptor Queue Current Address Reg, R/W*/
 237 +#define  TxDEQ_TDV  (0xffff<<16)
 238 +#define  TxDEQ_TDI  (0xff<<0)
 239 +
 240 +#define  REG_TxSBA  0x00c0  /*offset to Transmit Status Queue Base Address Reg, R/W*/
 241 +#define  REG_TxSBL  0x00c4  /*offset to Transmit Status Queue Base Length Reg, R/W, 16bits*/
 242 +#define  REG_TxSCL  0x00c6  /*offset to Transmit Status Queue Current Length Reg, R/W, 16bits*/
 243 +#define  REG_TxSCA  0x00c8  /*offset to Transmit Status Queue Current Address Reg, R/W*/
 244 +
 245 +#define  REG_RxBTH  0x00d0  /*offset to Receive Buffer Threshold Reg, R/W*/
 246 +#define  RxBTH_RDHT  (0x03ff<<16)
 247 +#define  RxBTH_RDST  (0x03ff<<0)
 248 +
 249 +#define  REG_TxBTH  0x00d4  /*offset to Transmit Buffer Threshold Reg, R/W*/
 250 +#define  TxBTH_TDHT  (0x03ff<<16)
 251 +#define  TxBTH_TDST  (0x03ff<<0)
 252 +
 253 +#define  REG_RxSTH  0x00d8  /*offset to Receive Status Threshold Reg, R/W*/
 254 +#define  RxSTH_RSHT  (0x003f<<16)
 255 +#define  RxSTH_RSST  (0x003f<<0)
 256 +
 257 +#define  REG_TxSTH  0x00dc  /*offset to Transmit Status Threshold Reg, R/W*/
 258 +#define  TxSTH_TSHT  (0x003f<<16)
 259 +#define  TxSTH_TSST  (0x003f<<0)
 260 +
 261 +#define  REG_RxDTH  0x00e0  /*offset to Receive Descriptor Threshold Reg, R/W*/
 262 +#define  RxDTH_RDHT  (0x003f<<16)
 263 +#define  RxDTH_RDST  (0x003f<<0)
 264 +
 265 +#define  REG_TxDTH  0x00e4  /*offset to Transmit Descriptor Threshold Reg, R/W*/
 266 +#define  TxDTH_TDHT  (0x003f<<16)
 267 +#define  TxDTH_TDST  (0x003f<<0)
 268 +
 269 +#define  REG_MaxFL  0x00e8  /*offset to Max Frame Length Reg, R/W*/
 270 +#define  MaxFL_MFL  (0x07ff<<16)
 271 +#define  MaxFL_TST  (0x07ff<<0)
 272 +
 273 +#define  REG_RxHL  0x00ec  /*offset to Receive Header Length Reg, R/W*/
 274 +#define  RxHL_RHL2  (0x07ff<<16)
 275 +#define  RxHL_RHL1  (0x03ff<<0)
 276 +
 277 +#define  REG_MACCFG0  0x0100  /*offset to Test Reg #0, R/W*/
 278 +#define  MACCFG0_DbgSel  (1<<7)
 279 +#define  MACCFG0_LCKEN   (1<<6)
 280 +#define  MACCFG0_LRATE   (1<<5)
 281 +#define  MACCFG0_RXERR   (1<<4)
 282 +#define  MACCFG0_BIT33   (1<<2)
 283 +#define  MACCFG0_PMEEN   (1<<1)
 284 +#define  MACCFG0_PMEST   (1<<0)
 285 +
 286 +#define  REG_MACCFG1  0x0104  /*offset to Test Reg #1, R/W*/
 287 +#define  REG_MACCFG2  0x0108  /*offset to Test Reg #2, R*/
 288 +#define  REG_MACCFG3  0x010c  /*offset to Test Reg #3, R*/
 289 +
 290 +
 291 +
 292 +/*---------------------------------------------------------------
 293 + * Definition of Descriptor/Status Queue Entry
 294 + *-------------------------------------------------------------*/
 295 +
 296 +typedef  union receiveDescriptor  {  /*data structure of Receive Descriptor Queue Entry*/
 297 +    struct {        /*whole value*/
 298 +        U32  e0,      /*1st dword entry*/
 299 +             e1;      /*2nd dword entry*/
 300 +    }  w;
 301 +    struct {        /*bit field definitions*/
 302 +        U32  ba:32,   /*Buffer Address (keep in mind this is physical address)*/
 303 +             bl:16,   /*b15-0; Buffer Length*/
 304 +             bi:15,   /*b30-16; Buffer Index*/
 305 +             nsof:1;  /*b31; Not Start Of Frame*/
 306 +    }  f;
 307 +}  receiveDescriptor;
 308 +
 309 +
 310 +typedef  union receiveStatus  {  /*data structure of Receive Status Queue Entry*/
 311 +    struct {         /*whole word*/
 312 +        U32  e0,       /*1st dword entry*/
 313 +             e1;       /*2nd dword entry*/
 314 +    }  w;
 315 +    struct {         /*bit field*/
 316 +        U32  rsrv1:8,  /*b7-0: reserved*/
 317 +             hti:6,    /*b13-8: Hash Table Index*/
 318 +             rsrv2:1,  /*b14: reserved*/
 319 +             crci:1,   /*b15: CRC Included*/
 320 +             crce:1,   /*b16: CRC Error*/
 321 +             edata:1,  /*b17: Extra Data*/
 322 +             runt:1,   /*b18: Runt Frame*/
 323 +             fe:1,     /*b19: Framing Error*/
 324 +             oe:1,     /*b20: Overrun Error*/
 325 +             rxerr:1,  /*b21: Rx Error*/
 326 +             am:2,     /*b23-22: Address Match*/
 327 +             rsrv3:4,  /*b27-24: reserved*/
 328 +             eob:1,    /*b28: End Of Buffer*/
 329 +             eof:1,    /*b29: End Of Frame*/
 330 +             rwe:1,    /*b30: Received Without Error*/
 331 +             rfp:1,    /*b31: Receive Frame Processed*/
 332 +             fl:16,    /*b15-0: frame length*/
 333 +             bi:15,    /*b30-16: Buffer Index*/
 334 +             rfp2:1;   /*b31: Receive Frame Processed at 2nd word*/
 335 +    }  f;
 336 +}  receiveStatus;
 337 +
 338 +
 339 +typedef  union transmitDescriptor  {  /*data structure of Transmit Descriptor Queue Entry*/
 340 +    struct {         /*whole value*/
 341 +        U32  e0,       /*1st dword entry*/
 342 +             e1;       /*2nd dword entry*/
 343 +    }  w;
 344 +    struct {         /*bit field*/
 345 +        U32  ba:32,    /*b31-0: Buffer Address (keep in mind this is physical address)*/
 346 +             bl:12,    /*b11-0: Buffer Length*/
 347 +             rsrv1:3,  /*b14-12: reserved*/
 348 +             af:1,     /*b15: Abort Frame*/
 349 +             bi:15,    /*b30-16: Buffer Index*/
 350 +             eof:1;    /*b31: End Of Frame*/
 351 +
 352 +    }  f;
 353 +}  transmitDescriptor;
 354 +
 355 +
 356 +typedef  union transmitStatus  {  /*data structure of Transmit Status Queue Entry*/
 357 +    struct {         /*whole word*/
 358 +        U32  e0;       /*1st dword entry*/
 359 +    }  w;
 360 +    struct {         /*bit field*/
 361 +        U32  bi:15,    /*b14-0: Buffer Index*/
 362 +             rsrv3:1,  /*b15: reserved*/
 363 +             ncoll:5,  /*b20-16: Number of Collisions*/
 364 +             rsrv2:3,  /*b23-21: reserved*/
 365 +             ecoll:1,  /*b24: Excess Collisions*/
 366 +             txu:1,    /*b25: Tx Underrun*/
 367 +             ow:1,     /*b26: Out of Window*/
 368 +             rsrv1:1,  /*b27: reserved*/
 369 +             lcrs:1,   /*b28: Loss of CRS*/
 370 +             fa:1,     /*b29: Frame Abort*/
 371 +             txwe:1,   /*b30: Transmitted Without Error*/
 372 +             txfp:1;   /*b31: Transmit Frame Processed*/
 373 +    }  f;
 374 +}  transmitStatus;
 375 +
 376 +
 377 +
 378 +/*---------------------------------------------------------------
 379 + *  Size of device registers occupied in memory/IO address map
 380 + *-------------------------------------------------------------*/
 381 +#define  DEV_REG_SPACE  0x00010000
 382 +
 383 +/*
 384 +#define U8 unsigned char
 385 +#define U16 unsigned short
 386 +#define U32 unsigned long
 387 +*/
 388 +
 389 +/*---------------------------------------------------------------
 390 + * A definition of register access macros
 391 + *-------------------------------------------------------------*/
 392 +#define  _RegRd(type,ofs)     (*(volatile type*)(ofs))
 393 +#define  _RegWr(type,ofs,dt)  *(volatile type*)(ofs)=((type)(dt))
 394 +
 395 +#define  RegRd8(ofs)   _RegRd(U8,(char*)pD->base_addr+(ofs))
 396 +#define  RegRd16(ofs)  _RegRd(U16,(char*)pD->base_addr+(ofs))
 397 +#define  RegRd32(ofs)  _RegRd(U32,(char*)pD->base_addr+(ofs))
 398 +#define  RegWr8(ofs,dt)   _RegWr(U8,(char*)pD->base_addr+(ofs),(dt))
 399 +#define  RegWr16(ofs,dt)  _RegWr(U16,(char*)pD->base_addr+(ofs),(dt))
 400 +#define  RegWr32(ofs,dt)  _RegWr(U32,(char*)pD->base_addr+(ofs),(dt))
 401 +
 402 +
 403 +
 404 +#endif  /* _EP9213_ETH_H_ */
 405 +