package/ltq-dsl/src/ifxmips_atm_danube.c

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_atm_danube.c
   4 ** PROJECT      : UEIP
   5 ** MODULES      : ATM
   6 **
   7 ** DATE         : 7 Jul 2009
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : ATM driver common source file (core functions)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 ** 07 JUL 2009  Xu Liang        Init Version
  22 *******************************************************************************/
  23
  24
  25
  26 /*
  27  * ####################################
  28  *              Head File
  29  * ####################################
  30  */
  31
  32 /*
  33  *  Common Head File
  34  */
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/version.h>
  38 #include <linux/types.h>
  39 #include <linux/errno.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/init.h>
  42 #include <linux/ioctl.h>
  43 #include <asm/delay.h>
  44
  45 /*
  46  *  Chip Specific Head File
  47  */
  48 #include <lantiq_soc.h>
  49 #include "ifxmips_compat.h"
  50 #include "ifxmips_atm_core.h"
  51 #include "ifxmips_atm_fw_danube.h"
  52
  53
  54
  55 /*
  56  * ####################################
  57  *              Definition
  58  * ####################################
  59  */
  60
  61 /*
  62  *  EMA Settings
  63  */
  64 #define EMA_CMD_BUF_LEN      0x0040
  65 #define EMA_CMD_BASE_ADDR    (0x00001580 << 2)
  66 #define EMA_DATA_BUF_LEN     0x0100
  67 #define EMA_DATA_BASE_ADDR   (0x00001900 << 2)
  68 #define EMA_WRITE_BURST      0x2
  69 #define EMA_READ_BURST       0x2
  70
  71
  72
  73 /*
  74  * ####################################
  75  *             Declaration
  76  * ####################################
  77  */
  78
  79 /*
  80  *  Hardware Init/Uninit Functions
  81  */
  82 static inline void init_pmu(void);
  83 static inline void uninit_pmu(void);
  84 static inline void init_ema(void);
  85 static inline void init_mailbox(void);
  86 static inline void init_atm_tc(void);
  87 static inline void clear_share_buffer(void);
  88
  89
  90
  91 /*
  92  * ####################################
  93  *            Local Variable
  94  * ####################################
  95  */
  96
  97
  98
  99 /*
 100  * ####################################
 101  *            Local Function
 102  * ####################################
 103  */
 104
 105 static inline void init_pmu(void)
 106 {
 107     //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
 108     PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
 109     PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
 110     PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
 111     PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
 112     PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
 113     PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
 114     DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);
 115 }
 116
 117 static inline void uninit_pmu(void)
 118 {
 119     PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
 120     PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
 121     PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
 122     PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
 123     PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
 124     DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
 125     PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
 126 }
 127
 128 static inline void init_ema(void)
 129 {
 130     IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
 131     IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
 132     IFX_REG_W32(0x000000FF, EMA_IER);
 133     IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
 134 }
 135
 136 static inline void init_mailbox(void)
 137 {
 138     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
 139     IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
 140     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
 141     IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
 142 }
 143
 144 static inline void init_atm_tc(void)
 145 {
 146     //  for ReTX expansion in future
 147     //*FFSM_CFG0 = SET_BITS(*FFSM_CFG0, 5, 0, 6); //  pnum = 6
 148     //*FFSM_CFG1 = SET_BITS(*FFSM_CFG1, 5, 0, 6); //  pnum = 6
 149 }
 150
 151 static inline void clear_share_buffer(void)
 152 {
 153     volatile u32 *p = SB_RAM0_ADDR(0);
 154     unsigned int i;
 155
 156     for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
 157         IFX_REG_W32(0, p++);
 158 }
 159
 160 /*
 161  *  Description:
 162  *    Download PPE firmware binary code.
 163  *  Input:
 164  *    src       --- u32 *, binary code buffer
 165  *    dword_len --- unsigned int, binary code length in DWORD (32-bit)
 166  *  Output:
 167  *    int       --- IFX_SUCCESS:    Success
 168  *                  else:           Error Code
 169  */
 170 static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
 171 {
 172     volatile u32 *dest;
 173
 174     if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
 175         || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
 176         return IFX_ERROR;
 177
 178     if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
 179         IFX_REG_W32(0x00, CDM_CFG);
 180     else
 181         IFX_REG_W32(0x02, CDM_CFG);
 182
 183     /*  copy code   */
 184     dest = CDM_CODE_MEMORY(0, 0);
 185     while ( code_dword_len-- > 0 )
 186         IFX_REG_W32(*code_src++, dest++);
 187
 188     /*  copy data   */
 189     dest = CDM_DATA_MEMORY(0, 0);
 190     while ( data_dword_len-- > 0 )
 191         IFX_REG_W32(*data_src++, dest++);
 192
 193     return IFX_SUCCESS;
 194 }
 195
 196
 197
 198 /*
 199  * ####################################
 200  *           Global Function
 201  * ####################################
 202  */
 203
 204 extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor)
 205 {
 206     ASSERT(major != NULL, "pointer is NULL");
 207     ASSERT(minor != NULL, "pointer is NULL");
 208
 209     *major = ATM_FW_VER_MAJOR;
 210     *minor = ATM_FW_VER_MINOR;
 211 }
 212
 213 void ifx_atm_init_chip(void)
 214 {
 215     init_pmu();
 216
 217     init_ema();
 218
 219     init_mailbox();
 220
 221     init_atm_tc();
 222
 223     clear_share_buffer();
 224 }
 225
 226 void ifx_atm_uninit_chip(void)
 227 {
 228     uninit_pmu();
 229 }
 230
 231 /*
 232  *  Description:
 233  *    Initialize and start up PP32.
 234  *  Input:
 235  *    none
 236  *  Output:
 237  *    int  --- IFX_SUCCESS: Success
 238  *             else:        Error Code
 239  */
 240 int ifx_pp32_start(int pp32)
 241 {
 242     int ret;
 243
 244     /*  download firmware   */
 245     ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
 246     if ( ret != IFX_SUCCESS )
 247         return ret;
 248
 249     /*  run PP32    */
 250     IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);
 251
 252     /*  idle for a while to let PP32 init itself    */
 253     udelay(10);
 254
 255     return IFX_SUCCESS;
 256 }
 257
 258 /*
 259  *  Description:
 260  *    Halt PP32.
 261  *  Input:
 262  *    none
 263  *  Output:
 264  *    none
 265  */
 266 void ifx_pp32_stop(int pp32)
 267 {
 268     /*  halt PP32   */
 269     IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);
 270 }