target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   7  *               2009 Florian Fainelli <florian@openwrt.org>
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/cpu.h>
  13 #include <bcm63xx_cpu.h>
  14 #include <bcm63xx_regs.h>
  15 #include <bcm63xx_io.h>
  16 #include <bcm63xx_irq.h>
  17
  18 const unsigned long *bcm63xx_regs_base;
  19 EXPORT_SYMBOL(bcm63xx_regs_base);
  20
  21 const int *bcm63xx_irqs;
  22 EXPORT_SYMBOL(bcm63xx_irqs);
  23
  24 const unsigned long *bcm63xx_regs_spi;
  25 EXPORT_SYMBOL(bcm63xx_regs_spi);
  26
  27 static u16 bcm63xx_cpu_id;
  28 static u16 bcm63xx_cpu_rev;
  29 static unsigned int bcm63xx_cpu_freq;
  30 static unsigned int bcm63xx_memory_size;
  31
  32 /*
  33  * 6338 register sets and irqs
  34  */
  35
  36 static const unsigned long bcm96338_regs_base[] = {
  37         [RSET_PERF]             = BCM_6338_PERF_BASE,
  38         [RSET_TIMER]            = BCM_6338_TIMER_BASE,
  39         [RSET_WDT]              = BCM_6338_WDT_BASE,
  40         [RSET_UDC0]             = BCM_6338_UDC0_BASE,
  41         [RSET_UART0]            = BCM_6338_UART0_BASE,
  42         [RSET_GPIO]             = BCM_6338_GPIO_BASE,
  43         [RSET_SPI]              = BCM_6338_SPI_BASE,
  44         [RSET_MEMC]             = BCM_6338_MEMC_BASE,
  45 };
  46
  47 static const int bcm96338_irqs[] = {
  48         [IRQ_TIMER]             = BCM_6338_TIMER_IRQ,
  49         [IRQ_SPI]               = BCM_6338_SPI_IRQ,
  50         [IRQ_UART0]             = BCM_6338_UART0_IRQ,
  51         [IRQ_DSL]               = BCM_6338_DSL_IRQ,
  52         [IRQ_UDC0]              = BCM_6338_UDC0_IRQ,
  53         [IRQ_ENET0]             = BCM_6338_ENET0_IRQ,
  54         [IRQ_ENET_PHY]          = BCM_6338_ENET_PHY_IRQ,
  55         [IRQ_ENET0_RXDMA]       = BCM_6338_ENET0_RXDMA_IRQ,
  56         [IRQ_ENET0_TXDMA]       = BCM_6338_ENET0_TXDMA_IRQ,
  57 };
  58
  59 static const unsigned long bcm96338_regs_spi[] = {
  60         [SPI_CMD]               = SPI_BCM_6338_SPI_CMD,
  61         [SPI_INT_STATUS]        = SPI_BCM_6338_SPI_INT_STATUS,
  62         [SPI_INT_MASK_ST]       = SPI_BCM_6338_SPI_MASK_INT_ST,
  63         [SPI_INT_MASK]          = SPI_BCM_6338_SPI_INT_MASK,
  64         [SPI_ST]                = SPI_BCM_6338_SPI_ST,
  65         [SPI_CLK_CFG]           = SPI_BCM_6338_SPI_CLK_CFG,
  66         [SPI_FILL_BYTE]         = SPI_BCM_6338_SPI_FILL_BYTE,
  67         [SPI_MSG_TAIL]          = SPI_BCM_6338_SPI_MSG_TAIL,
  68         [SPI_RX_TAIL]           = SPI_BCM_6338_SPI_RX_TAIL,
  69         [SPI_MSG_CTL]           = SPI_BCM_6338_SPI_MSG_CTL,
  70         [SPI_MSG_DATA]          = SPI_BCM_6338_SPI_MSG_DATA,
  71         [SPI_RX_DATA]           = SPI_BCM_6338_SPI_RX_DATA,
  72 };
  73
  74 /*
  75  * 6348 register sets and irqs
  76  */
  77 static const unsigned long bcm96348_regs_base[] = {
  78         [RSET_DSL_LMEM]         = BCM_6348_DSL_LMEM_BASE,
  79         [RSET_PERF]             = BCM_6348_PERF_BASE,
  80         [RSET_TIMER]            = BCM_6348_TIMER_BASE,
  81         [RSET_WDT]              = BCM_6348_WDT_BASE,
  82         [RSET_UART0]            = BCM_6348_UART0_BASE,
  83         [RSET_GPIO]             = BCM_6348_GPIO_BASE,
  84         [RSET_SPI]              = BCM_6348_SPI_BASE,
  85         [RSET_OHCI0]            = BCM_6348_OHCI0_BASE,
  86         [RSET_OHCI_PRIV]        = BCM_6348_OHCI_PRIV_BASE,
  87         [RSET_USBH_PRIV]        = BCM_6348_USBH_PRIV_BASE,
  88         [RSET_UDC0]             = BCM_6348_UDC0_BASE,
  89         [RSET_MPI]              = BCM_6348_MPI_BASE,
  90         [RSET_PCMCIA]           = BCM_6348_PCMCIA_BASE,
  91         [RSET_SDRAM]            = BCM_6348_SDRAM_BASE,
  92         [RSET_DSL]              = BCM_6348_DSL_BASE,
  93         [RSET_ENET0]            = BCM_6348_ENET0_BASE,
  94         [RSET_ENET1]            = BCM_6348_ENET1_BASE,
  95         [RSET_ENETDMA]          = BCM_6348_ENETDMA_BASE,
  96         [RSET_MEMC]             = BCM_6348_MEMC_BASE,
  97         [RSET_DDR]              = BCM_6348_DDR_BASE,
  98 };
  99
 100 static const int bcm96348_irqs[] = {
 101         [IRQ_TIMER]             = BCM_6348_TIMER_IRQ,
 102         [IRQ_SPI]               = BCM_6348_SPI_IRQ,
 103         [IRQ_UART0]             = BCM_6348_UART0_IRQ,
 104         [IRQ_DSL]               = BCM_6348_DSL_IRQ,
 105         [IRQ_UDC0]              = BCM_6348_UDC0_IRQ,
 106         [IRQ_ENET0]             = BCM_6348_ENET0_IRQ,
 107         [IRQ_ENET1]             = BCM_6348_ENET1_IRQ,
 108         [IRQ_ENET_PHY]          = BCM_6348_ENET_PHY_IRQ,
 109         [IRQ_OHCI0]             = BCM_6348_OHCI0_IRQ,
 110         [IRQ_PCMCIA]            = BCM_6348_PCMCIA_IRQ,
 111         [IRQ_ENET0_RXDMA]       = BCM_6348_ENET0_RXDMA_IRQ,
 112         [IRQ_ENET0_TXDMA]       = BCM_6348_ENET0_TXDMA_IRQ,
 113         [IRQ_ENET1_RXDMA]       = BCM_6348_ENET1_RXDMA_IRQ,
 114         [IRQ_ENET1_TXDMA]       = BCM_6348_ENET1_TXDMA_IRQ,
 115         [IRQ_PCI]               = BCM_6348_PCI_IRQ,
 116 };
 117
 118 static const unsigned long bcm96348_regs_spi[] = {
 119         [SPI_CMD]               = SPI_BCM_6348_SPI_CMD,
 120         [SPI_INT_STATUS]        = SPI_BCM_6348_SPI_INT_STATUS,
 121         [SPI_INT_MASK_ST]       = SPI_BCM_6348_SPI_MASK_INT_ST,
 122         [SPI_INT_MASK]          = SPI_BCM_6348_SPI_INT_MASK,
 123         [SPI_ST]                = SPI_BCM_6348_SPI_ST,
 124         [SPI_CLK_CFG]           = SPI_BCM_6348_SPI_CLK_CFG,
 125         [SPI_FILL_BYTE]         = SPI_BCM_6348_SPI_FILL_BYTE,
 126         [SPI_MSG_TAIL]          = SPI_BCM_6348_SPI_MSG_TAIL,
 127         [SPI_RX_TAIL]           = SPI_BCM_6348_SPI_RX_TAIL,
 128         [SPI_MSG_CTL]           = SPI_BCM_6348_SPI_MSG_CTL,
 129         [SPI_MSG_DATA]          = SPI_BCM_6348_SPI_MSG_DATA,
 130         [SPI_RX_DATA]           = SPI_BCM_6348_SPI_RX_DATA,
 131 };
 132
 133 /*
 134  * 6358 register sets and irqs
 135  */
 136 static const unsigned long bcm96358_regs_base[] = {
 137         [RSET_DSL_LMEM]         = BCM_6358_DSL_LMEM_BASE,
 138         [RSET_PERF]             = BCM_6358_PERF_BASE,
 139         [RSET_TIMER]            = BCM_6358_TIMER_BASE,
 140         [RSET_WDT]              = BCM_6358_WDT_BASE,
 141         [RSET_UART0]            = BCM_6358_UART0_BASE,
 142         [RSET_GPIO]             = BCM_6358_GPIO_BASE,
 143         [RSET_SPI]              = BCM_6358_SPI_BASE,
 144         [RSET_OHCI0]            = BCM_6358_OHCI0_BASE,
 145         [RSET_EHCI0]            = BCM_6358_EHCI0_BASE,
 146         [RSET_OHCI_PRIV]        = BCM_6358_OHCI_PRIV_BASE,
 147         [RSET_USBH_PRIV]        = BCM_6358_USBH_PRIV_BASE,
 148         [RSET_MPI]              = BCM_6358_MPI_BASE,
 149         [RSET_PCMCIA]           = BCM_6358_PCMCIA_BASE,
 150         [RSET_SDRAM]            = BCM_6358_SDRAM_BASE,
 151         [RSET_DSL]              = BCM_6358_DSL_BASE,
 152         [RSET_ENET0]            = BCM_6358_ENET0_BASE,
 153         [RSET_ENET1]            = BCM_6358_ENET1_BASE,
 154         [RSET_ENETDMA]          = BCM_6358_ENETDMA_BASE,
 155         [RSET_MEMC]             = BCM_6358_MEMC_BASE,
 156         [RSET_DDR]              = BCM_6358_DDR_BASE,
 157 };
 158
 159 static const int bcm96358_irqs[] = {
 160         [IRQ_TIMER]             = BCM_6358_TIMER_IRQ,
 161         [IRQ_SPI]               = BCM_6358_SPI_IRQ,
 162         [IRQ_UART0]             = BCM_6358_UART0_IRQ,
 163         [IRQ_DSL]               = BCM_6358_DSL_IRQ,
 164         [IRQ_ENET0]             = BCM_6358_ENET0_IRQ,
 165         [IRQ_ENET1]             = BCM_6358_ENET1_IRQ,
 166         [IRQ_ENET_PHY]          = BCM_6358_ENET_PHY_IRQ,
 167         [IRQ_OHCI0]             = BCM_6358_OHCI0_IRQ,
 168         [IRQ_EHCI0]             = BCM_6358_EHCI0_IRQ,
 169         [IRQ_PCMCIA]            = BCM_6358_PCMCIA_IRQ,
 170         [IRQ_ENET0_RXDMA]       = BCM_6358_ENET0_RXDMA_IRQ,
 171         [IRQ_ENET0_TXDMA]       = BCM_6358_ENET0_TXDMA_IRQ,
 172         [IRQ_ENET1_RXDMA]       = BCM_6358_ENET1_RXDMA_IRQ,
 173         [IRQ_ENET1_TXDMA]       = BCM_6358_ENET1_TXDMA_IRQ,
 174         [IRQ_PCI]               = BCM_6358_PCI_IRQ,
 175 };
 176
 177 static const unsigned long bcm96358_regs_spi[] = {
 178         [SPI_CMD]               = SPI_BCM_6358_SPI_CMD,
 179         [SPI_INT_STATUS]        = SPI_BCM_6358_SPI_INT_STATUS,
 180         [SPI_INT_MASK_ST]       = SPI_BCM_6358_SPI_MASK_INT_ST,
 181         [SPI_INT_MASK]          = SPI_BCM_6358_SPI_INT_MASK,
 182         [SPI_ST]                = SPI_BCM_6358_SPI_STATUS,
 183         [SPI_CLK_CFG]           = SPI_BCM_6358_SPI_CLK_CFG,
 184         [SPI_FILL_BYTE]         = SPI_BCM_6358_SPI_FILL_BYTE,
 185         [SPI_MSG_TAIL]          = SPI_BCM_6358_SPI_MSG_TAIL,
 186         [SPI_RX_TAIL]           = SPI_BCM_6358_SPI_RX_TAIL,
 187         [SPI_MSG_CTL]           = SPI_BCM_6358_MSG_CTL,
 188         [SPI_MSG_DATA]          = SPI_BCM_6358_SPI_MSG_DATA,
 189         [SPI_RX_DATA]           = SPI_BCM_6358_SPI_RX_DATA,
 190 };
 191
 192 u16 __bcm63xx_get_cpu_id(void)
 193 {
 194         return bcm63xx_cpu_id;
 195 }
 196
 197 EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
 198
 199 u16 bcm63xx_get_cpu_rev(void)
 200 {
 201         return bcm63xx_cpu_rev;
 202 }
 203
 204 EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
 205
 206 unsigned int bcm63xx_get_cpu_freq(void)
 207 {
 208         return bcm63xx_cpu_freq;
 209 }
 210
 211 unsigned int bcm63xx_get_memory_size(void)
 212 {
 213         return bcm63xx_memory_size;
 214 }
 215
 216 static unsigned int detect_cpu_clock(void)
 217 {
 218         unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
 219
 220         if (BCMCPU_IS_6338()) {
 221                 return 240000000;
 222         }
 223
 224         /*
 225          * frequency depends on PLL configuration:
 226          */
 227         if (BCMCPU_IS_6348()) {
 228                 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
 229                 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
 230                 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
 231                 n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
 232                 m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
 233                 n1 += 1;
 234                 n2 += 2;
 235                 m1 += 1;
 236         }
 237
 238         if (BCMCPU_IS_6358()) {
 239                 /* 16MHz * N1 * N2 / M1_CPU */
 240                 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
 241                 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
 242                 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
 243                 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
 244         }
 245
 246         return (16 * 1000000 * n1 * n2) / m1;
 247 }
 248
 249 /*
 250  * attempt to detect the amount of memory installed
 251  */
 252 static unsigned int detect_memory_size(void)
 253 {
 254         unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
 255         u32 val;
 256
 257         if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
 258                 val = bcm_sdram_readl(SDRAM_CFG_REG);
 259                 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
 260                 cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
 261                 is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
 262                 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
 263         }
 264
 265         if (BCMCPU_IS_6358()) {
 266                 val = bcm_memc_readl(MEMC_CFG_REG);
 267                 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
 268                 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
 269                 is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
 270                 banks = 2;
 271         }
 272
 273         /* 0 => 11 address bits ... 2 => 13 address bits */
 274         rows += 11;
 275
 276         /* 0 => 8 address bits ... 2 => 10 address bits */
 277         cols += 8;
 278
 279         return 1 << (cols + rows + (is_32bits + 1) + banks);
 280 }
 281
 282 void __init bcm63xx_cpu_init(void)
 283 {
 284         unsigned int tmp, expected_cpu_id;
 285         struct cpuinfo_mips *c = &current_cpu_data;
 286
 287         /* soc registers location depends on cpu type */
 288         expected_cpu_id = 0;
 289
 290         switch (c->cputype) {
 291         case CPU_BCM6338:
 292                 expected_cpu_id = BCM6338_CPU_ID;
 293                 bcm63xx_regs_base = bcm96338_regs_base;
 294                 bcm63xx_irqs = bcm96338_irqs;
 295                 bcm63xx_regs_spi = bcm96338_regs_spi;
 296                 break;
 297         case CPU_BCM6348:
 298                 expected_cpu_id = BCM6348_CPU_ID;
 299                 bcm63xx_regs_base = bcm96348_regs_base;
 300                 bcm63xx_irqs = bcm96348_irqs;
 301                 bcm63xx_regs_spi = bcm96348_regs_spi;
 302                 break;
 303         case CPU_BCM6358:
 304                 expected_cpu_id = BCM6358_CPU_ID;
 305                 bcm63xx_regs_base = bcm96358_regs_base;
 306                 bcm63xx_irqs = bcm96358_irqs;
 307                 bcm63xx_regs_spi = bcm96358_regs_spi;
 308                 break;
 309         }
 310
 311         /* really early to panic, but delaying panic would not help
 312          * since we will never get any working console */
 313         if (!expected_cpu_id)
 314                 panic("unsupported Broadcom CPU");
 315
 316         /*
 317          * bcm63xx_regs_base is set, we can access soc registers
 318          */
 319
 320         /* double check CPU type */
 321         tmp = bcm_perf_readl(PERF_REV_REG);
 322         bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
 323         bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
 324
 325         if (bcm63xx_cpu_id != expected_cpu_id)
 326                 panic("bcm63xx CPU id mismatch");
 327
 328         bcm63xx_cpu_freq = detect_cpu_clock();
 329         bcm63xx_memory_size = detect_memory_size();
 330
 331         printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
 332                bcm63xx_cpu_id, bcm63xx_cpu_rev);
 333         printk(KERN_INFO "CPU frequency is %u Hz\n",
 334                bcm63xx_cpu_freq);
 335         printk(KERN_INFO "%uMB of RAM installed\n",
 336                bcm63xx_memory_size >> 20);
 337 }