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rtl8366_smi: rename rtl8366s specific functions and definitions
[openwrt.git] / target / linux / ar71xx / files / drivers / net / phy / rtl8366_smi.c
1 /*
2 * Platform driver for the Realtek RTL8366 ethernet switch
3 *
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio.h>
18 #include <linux/spinlock.h>
19 #include <linux/skbuff.h>
20 #include <linux/switch.h>
21 #include <linux/phy.h>
22 #include <linux/rtl8366_smi.h>
23
24 #ifdef CONFIG_RTL8366_SMI_DEBUG_FS
25 #include <linux/debugfs.h>
26 #endif
27
28 #define RTL8366S_DRIVER_NAME "rtl8366-smi"
29 #define RTL8366S_DRIVER_DESC "Realtek RTL8366 switch driver"
30 #define RTL8366S_DRIVER_VER "0.1.1"
31
32 #define RTL8366S_PHY_NO_MAX 4
33 #define RTL8366S_PHY_PAGE_MAX 7
34 #define RTL8366S_PHY_ADDR_MAX 31
35
36 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
37 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
38
39 #define RTL8366_RESET_CTRL_REG 0x0100
40 #define RTL8366_CHIP_CTRL_RESET_HW 1
41 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
42
43 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
44 #define RTL8366S_CHIP_VERSION_MASK 0xf
45 #define RTL8366S_CHIP_ID_REG 0x0105
46 #define RTL8366S_CHIP_ID_8366 0x8366
47
48 /* PHY registers control */
49 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
50 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
51
52 #define RTL8366S_PHY_CTRL_READ 1
53 #define RTL8366S_PHY_CTRL_WRITE 0
54
55 #define RTL8366S_PHY_REG_MASK 0x1f
56 #define RTL8366S_PHY_PAGE_OFFSET 5
57 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
58 #define RTL8366S_PHY_NO_OFFSET 9
59 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
60
61 #define RTL8366_SMI_ACK_RETRY_COUNT 5
62 #define RTL8366_SMI_CLK_DELAY 10 /* nsec */
63
64 /* LED control registers */
65 #define RTL8366_LED_BLINKRATE_REG 0x0420
66 #define RTL8366_LED_BLINKRATE_BIT 0
67 #define RTL8366_LED_BLINKRATE_MASK 0x0007
68
69 #define RTL8366_LED_CTRL_REG 0x0421
70 #define RTL8366_LED_0_1_CTRL_REG 0x0422
71 #define RTL8366_LED_2_3_CTRL_REG 0x0423
72
73 #define RTL8366S_MIB_COUNT 33
74 #define RTL8366S_GLOBAL_MIB_COUNT 1
75 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
76 #define RTL8366S_MIB_COUNTER_BASE 0x1000
77 #define RTL8366S_MIB_CTRL_REG 0x11F0
78 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
79 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
80 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
81
82 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
83 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
84 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
85
86
87 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
88 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
89 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
90 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
91 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
92
93
94 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
95 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
96
97 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
98
99 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
100 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
101 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
102
103 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
104
105
106 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
107 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
108 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
109 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
110 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
111 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
112 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
113
114
115 #define RTL8366_PORT_NUM_CPU 5
116 #define RTL8366_NUM_PORTS 6
117 #define RTL8366_NUM_VLANS 16
118 #define RTL8366_NUM_LEDGROUPS 4
119 #define RTL8366_NUM_VIDS 4096
120 #define RTL8366S_PRIORITYMAX 7
121 #define RTL8366S_FIDMAX 7
122
123
124 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
125 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
126 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
127 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
128
129 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
130 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
131
132 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
133 RTL8366_PORT_2 | \
134 RTL8366_PORT_3 | \
135 RTL8366_PORT_4 | \
136 RTL8366_PORT_UNKNOWN | \
137 RTL8366_PORT_CPU)
138
139 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
140 RTL8366_PORT_2 | \
141 RTL8366_PORT_3 | \
142 RTL8366_PORT_4 | \
143 RTL8366_PORT_UNKNOWN)
144
145 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
146 RTL8366_PORT_2 | \
147 RTL8366_PORT_3 | \
148 RTL8366_PORT_4)
149
150 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
151 RTL8366_PORT_CPU)
152
153 struct rtl8366s_vlanconfig {
154 u16 reserved2:1;
155 u16 priority:3;
156 u16 vid:12;
157
158 u16 reserved1:1;
159 u16 fid:3;
160 u16 untag:6;
161 u16 member:6;
162 };
163
164 struct rtl8366s_vlan4kentry {
165 u16 reserved1:4;
166 u16 vid:12;
167
168 u16 reserved2:1;
169 u16 fid:3;
170 u16 untag:6;
171 u16 member:6;
172 };
173
174 static const char *MIBCOUNTERS[] = {
175 "IfInOctets ",
176 "EtherStatsOctets ",
177 "EtherStatsUnderSizePkts ",
178 "EtherFregament ",
179 "EtherStatsPkts64Octets ",
180 "EtherStatsPkts65to127Octets ",
181 "EtherStatsPkts128to255Octets ",
182 "EtherStatsPkts256to511Octets ",
183 "EtherStatsPkts512to1023Octets ",
184 "EtherStatsPkts1024to1518Octets ",
185 "EtherOversizeStats ",
186 "EtherStatsJabbers ",
187 "IfInUcastPkts ",
188 "EtherStatsMulticastPkts ",
189 "EtherStatsBroadcastPkts ",
190 "EtherStatsDropEvents ",
191 "Dot3StatsFCSErrors ",
192 "Dot3StatsSymbolErrors ",
193 "Dot3InPauseFrames ",
194 "Dot3ControlInUnknownOpcodes ",
195 "IfOutOctets ",
196 "Dot3StatsSingleCollisionFrames ",
197 "Dot3StatMultipleCollisionFrames ",
198 "Dot3sDeferredTransmissions ",
199 "Dot3StatsLateCollisions ",
200 "EtherStatsCollisions ",
201 "Dot3StatsExcessiveCollisions ",
202 "Dot3OutPauseFrames ",
203 "Dot1dBasePortDelayExceededDiscards",
204 "Dot1dTpPortInDiscards ",
205 "IfOutUcastPkts ",
206 "IfOutMulticastPkts ",
207 "IfOutBroadcastPkts ",
208 NULL,
209 };
210
211 struct rtl8366_smi {
212 struct device *parent;
213 unsigned int gpio_sda;
214 unsigned int gpio_sck;
215 spinlock_t lock;
216 };
217
218 struct rtl8366s {
219 struct device *parent;
220 struct rtl8366_smi smi;
221 struct mii_bus *mii_bus;
222 int mii_irq[PHY_MAX_ADDR];
223 struct switch_dev dev;
224 char buf[4096];
225 #ifdef CONFIG_RTL8366_SMI_DEBUG_FS
226 struct dentry *debugfs_root;
227 #endif
228 };
229
230 #ifdef CONFIG_RTL8366_SMI_DEBUG_FS
231 u16 g_dbg_reg;
232 #endif
233
234 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
235 {
236 return container_of(sw, struct rtl8366s, dev);
237 }
238
239 static inline void rtl8366_smi_clk_delay(struct rtl8366_smi *smi)
240 {
241 ndelay(RTL8366_SMI_CLK_DELAY);
242 }
243
244 static void rtl8366_smi_start(struct rtl8366_smi *smi)
245 {
246 unsigned int sda = smi->gpio_sda;
247 unsigned int sck = smi->gpio_sck;
248
249 /*
250 * Set GPIO pins to output mode, with initial state:
251 * SCK = 0, SDA = 1
252 */
253 gpio_direction_output(sck, 0);
254 gpio_direction_output(sda, 1);
255 rtl8366_smi_clk_delay(smi);
256
257 /* CLK 1: 0 -> 1, 1 -> 0 */
258 gpio_set_value(sck, 1);
259 rtl8366_smi_clk_delay(smi);
260 gpio_set_value(sck, 0);
261 rtl8366_smi_clk_delay(smi);
262
263 /* CLK 2: */
264 gpio_set_value(sck, 1);
265 rtl8366_smi_clk_delay(smi);
266 gpio_set_value(sda, 0);
267 rtl8366_smi_clk_delay(smi);
268 gpio_set_value(sck, 0);
269 rtl8366_smi_clk_delay(smi);
270 gpio_set_value(sda, 1);
271 }
272
273 static void rtl8366_smi_stop(struct rtl8366_smi *smi)
274 {
275 unsigned int sda = smi->gpio_sda;
276 unsigned int sck = smi->gpio_sck;
277
278 rtl8366_smi_clk_delay(smi);
279 gpio_set_value(sda, 0);
280 gpio_set_value(sck, 1);
281 rtl8366_smi_clk_delay(smi);
282 gpio_set_value(sda, 1);
283 rtl8366_smi_clk_delay(smi);
284 gpio_set_value(sck, 1);
285 rtl8366_smi_clk_delay(smi);
286 gpio_set_value(sck, 0);
287 rtl8366_smi_clk_delay(smi);
288 gpio_set_value(sck, 1);
289
290 /* add a click */
291 rtl8366_smi_clk_delay(smi);
292 gpio_set_value(sck, 0);
293 rtl8366_smi_clk_delay(smi);
294 gpio_set_value(sck, 1);
295
296 /* set GPIO pins to input mode */
297 gpio_direction_input(sda);
298 gpio_direction_input(sck);
299 }
300
301 static void rtl8366_smi_write_bits(struct rtl8366_smi *smi, u32 data, u32 len)
302 {
303 unsigned int sda = smi->gpio_sda;
304 unsigned int sck = smi->gpio_sck;
305
306 for (; len > 0; len--) {
307 rtl8366_smi_clk_delay(smi);
308
309 /* prepare data */
310 if ( data & ( 1 << (len - 1)) )
311 gpio_set_value(sda, 1);
312 else
313 gpio_set_value(sda, 0);
314 rtl8366_smi_clk_delay(smi);
315
316 /* clocking */
317 gpio_set_value(sck, 1);
318 rtl8366_smi_clk_delay(smi);
319 gpio_set_value(sck, 0);
320 }
321 }
322
323 static void rtl8366_smi_read_bits(struct rtl8366_smi *smi, u32 len, u32 *data)
324 {
325 unsigned int sda = smi->gpio_sda;
326 unsigned int sck = smi->gpio_sck;
327
328 gpio_direction_input(sda);
329
330 for (*data = 0; len > 0; len--) {
331 u32 u;
332
333 rtl8366_smi_clk_delay(smi);
334
335 /* clocking */
336 gpio_set_value(sck, 1);
337 rtl8366_smi_clk_delay(smi);
338 u = gpio_get_value(sda);
339 gpio_set_value(sck, 0);
340
341 *data |= (u << (len - 1));
342 }
343
344 gpio_direction_output(sda, 0);
345 }
346
347 static int rtl8366_smi_wait_for_ack(struct rtl8366_smi *smi)
348 {
349 int retry_cnt;
350
351 retry_cnt = 0;
352 do {
353 u32 ack;
354
355 rtl8366_smi_read_bits(smi, 1, &ack);
356 if (ack == 0)
357 break;
358
359 if (++retry_cnt > RTL8366_SMI_ACK_RETRY_COUNT)
360 return -EIO;
361 } while (1);
362
363 return 0;
364 }
365
366 static int rtl8366_smi_write_byte(struct rtl8366_smi *smi, u8 data)
367 {
368 rtl8366_smi_write_bits(smi, data, 8);
369 return rtl8366_smi_wait_for_ack(smi);
370 }
371
372 static int rtl8366_smi_read_byte0(struct rtl8366_smi *smi, u8 *data)
373 {
374 u32 t;
375
376 /* read data */
377 rtl8366_smi_read_bits(smi, 8, &t);
378 *data = (t & 0xff);
379
380 /* send an ACK */
381 rtl8366_smi_write_bits(smi, 0x00, 1);
382
383 return 0;
384 }
385
386 static int rtl8366_smi_read_byte1(struct rtl8366_smi *smi, u8 *data)
387 {
388 u32 t;
389
390 /* read data */
391 rtl8366_smi_read_bits(smi, 8, &t);
392 *data = (t & 0xff);
393
394 /* send an ACK */
395 rtl8366_smi_write_bits(smi, 0x01, 1);
396
397 return 0;
398 }
399
400 static int rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
401 {
402 unsigned long flags;
403 u8 lo = 0;
404 u8 hi = 0;
405 int ret;
406
407 spin_lock_irqsave(&smi->lock, flags);
408
409 rtl8366_smi_start(smi);
410
411 /* send READ command */
412 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x01);
413 if (ret)
414 goto out;
415
416 /* set ADDR[7:0] */
417 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
418 if (ret)
419 goto out;
420
421 /* set ADDR[15:8] */
422 ret = rtl8366_smi_write_byte(smi, addr >> 8);
423 if (ret)
424 goto out;
425
426 /* read DATA[7:0] */
427 rtl8366_smi_read_byte0(smi, &lo);
428 /* read DATA[15:8] */
429 rtl8366_smi_read_byte1(smi, &hi);
430
431 *data = ((u32) lo) | (((u32) hi) << 8);
432
433 ret = 0;
434
435 out:
436 rtl8366_smi_stop(smi);
437 spin_unlock_irqrestore(&smi->lock, flags);
438
439 return ret;
440 }
441
442 static int rtl8366_smi_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data)
443 {
444 unsigned long flags;
445 int ret;
446
447 spin_lock_irqsave(&smi->lock, flags);
448
449 rtl8366_smi_start(smi);
450
451 /* send WRITE command */
452 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x00);
453 if (ret)
454 goto out;
455
456 /* set ADDR[7:0] */
457 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
458 if (ret)
459 goto out;
460
461 /* set ADDR[15:8] */
462 ret = rtl8366_smi_write_byte(smi, addr >> 8);
463 if (ret)
464 goto out;
465
466 /* write DATA[7:0] */
467 ret = rtl8366_smi_write_byte(smi, data & 0xff);
468 if (ret)
469 goto out;
470
471 /* write DATA[15:8] */
472 ret = rtl8366_smi_write_byte(smi, data >> 8);
473 if (ret)
474 goto out;
475
476 ret = 0;
477
478 out:
479 rtl8366_smi_stop(smi);
480 spin_unlock_irqrestore(&smi->lock, flags);
481
482 return ret;
483 }
484
485 static int rtl8366s_read_phy_reg(struct rtl8366s *rtl,
486 u32 phy_no, u32 page, u32 addr, u32 *data)
487 {
488 struct rtl8366_smi *smi = &rtl->smi;
489 u32 reg;
490 int ret;
491
492 if (phy_no > RTL8366S_PHY_NO_MAX)
493 return -EINVAL;
494
495 if (page > RTL8366S_PHY_PAGE_MAX)
496 return -EINVAL;
497
498 if (addr > RTL8366S_PHY_ADDR_MAX)
499 return -EINVAL;
500
501 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
502 RTL8366S_PHY_CTRL_READ);
503 if (ret)
504 return ret;
505
506 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
507 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
508 (addr & RTL8366S_PHY_REG_MASK);
509
510 ret = rtl8366_smi_write_reg(smi, reg, 0);
511 if (ret)
512 return ret;
513
514 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
515 if (ret)
516 return ret;
517
518 return 0;
519 }
520
521 static int rtl8366s_write_phy_reg(struct rtl8366s *rtl,
522 u32 phy_no, u32 page, u32 addr, u32 data)
523 {
524 struct rtl8366_smi *smi = &rtl->smi;
525 u32 reg;
526 int ret;
527
528 if (phy_no > RTL8366S_PHY_NO_MAX)
529 return -EINVAL;
530
531 if (page > RTL8366S_PHY_PAGE_MAX)
532 return -EINVAL;
533
534 if (addr > RTL8366S_PHY_ADDR_MAX)
535 return -EINVAL;
536
537 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
538 RTL8366S_PHY_CTRL_WRITE);
539 if (ret)
540 return ret;
541
542 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
543 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
544 (addr & RTL8366S_PHY_REG_MASK);
545
546 ret = rtl8366_smi_write_reg(smi, reg, data);
547 if (ret)
548 return ret;
549
550 return 0;
551 }
552
553 static int rtl8366_get_mib_counter(struct rtl8366s *rtl, int counter,
554 int port, unsigned long long *val)
555 {
556 struct rtl8366_smi *smi = &rtl->smi;
557 int i;
558 int err;
559 u32 addr, data, regoffset;
560 u64 mibvalue;
561
562 /* address offset to MIBs counter */
563 const u16 mibLength[RTL8366S_MIB_COUNT] = {4, 4, 2, 2, 2, 2, 2, 2, 2,
564 2, 2, 2, 2, 2, 2, 2, 2, 2,
565 2, 2, 4, 2, 2, 2, 2, 2, 2,
566 2, 2, 2, 2, 2, 2};
567
568 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
569 return -EINVAL;
570
571 regoffset = RTL8366S_MIB_COUNTER_PORT_OFFSET * (port);
572
573 for (i = 0; i < counter; i++)
574 regoffset += mibLength[i];
575
576 addr = RTL8366S_MIB_COUNTER_BASE + regoffset;
577
578 /*
579 * Writing access counter address first
580 * then ASIC will prepare 64bits counter wait for being retrived
581 */
582 data = 0; /* writing data will be discard by ASIC */
583 err = rtl8366_smi_write_reg(smi, addr, data);
584 if (err)
585 return err;
586
587 /* read MIB control register */
588 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
589 if (err)
590 return err;
591
592 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
593 return -EBUSY;
594
595 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
596 return -EIO;
597
598 mibvalue = 0;
599 addr = addr + mibLength[counter] - 1;
600 i = mibLength[counter];
601
602 while (i) {
603 err = rtl8366_smi_read_reg(smi, addr, &data);
604 if (err)
605 return err;
606
607 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
608
609 addr--;
610 i--;
611 }
612
613 *val = mibvalue;
614 return 0;
615 }
616
617 static int rtl8366s_get_vlan_4k_entry(struct rtl8366s *rtl, u32 vid,
618 struct rtl8366s_vlan4kentry *vlan4k)
619 {
620 struct rtl8366_smi *smi = &rtl->smi;
621 int err;
622 u32 data;
623 u16 *tableaddr;
624
625 memset(vlan4k, '\0', sizeof(struct rtl8366s_vlan4kentry));
626 vlan4k->vid = vid;
627
628 if (vid >= RTL8366_NUM_VIDS)
629 return -EINVAL;
630
631 tableaddr = (u16 *)vlan4k;
632
633 /* write VID */
634 data = *tableaddr;
635 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
636 if (err)
637 return err;
638
639 /* write table access control word */
640 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
641 RTL8366S_TABLE_VLAN_READ_CTRL);
642 if (err)
643 return err;
644
645 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
646 if (err)
647 return err;
648
649 *tableaddr = data;
650 tableaddr++;
651
652 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
653 &data);
654 if (err)
655 return err;
656
657 *tableaddr = data;
658 vlan4k->vid = vid;
659
660 return 0;
661 }
662
663 static int rtl8366s_set_vlan_4k_entry(struct rtl8366s *rtl,
664 const struct rtl8366s_vlan4kentry *vlan4k)
665 {
666 struct rtl8366_smi *smi = &rtl->smi;
667 int err;
668 u32 data;
669 u16 *tableaddr;
670
671 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
672 vlan4k->member > RTL8366_PORT_ALL ||
673 vlan4k->untag > RTL8366_PORT_ALL ||
674 vlan4k->fid > RTL8366S_FIDMAX)
675 return -EINVAL;
676
677 tableaddr = (u16 *)vlan4k;
678
679 data = *tableaddr;
680
681 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
682 if (err)
683 return err;
684
685 tableaddr++;
686
687 data = *tableaddr;
688
689 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
690 data);
691 if (err)
692 return err;
693
694 /* write table access control word */
695 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
696 RTL8366S_TABLE_VLAN_WRITE_CTRL);
697
698 return err;
699 }
700
701 static int rtl8366s_get_vlan_member_config(struct rtl8366s *rtl, u32 index,
702 struct rtl8366s_vlanconfig *vlanmc)
703 {
704 struct rtl8366_smi *smi = &rtl->smi;
705 int err;
706 u32 addr;
707 u32 data;
708 u16 *tableaddr;
709
710 memset(vlanmc, '\0', sizeof(struct rtl8366s_vlanconfig));
711
712 if (index >= RTL8366_NUM_VLANS)
713 return -EINVAL;
714
715 tableaddr = (u16 *)vlanmc;
716
717 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
718 err = rtl8366_smi_read_reg(smi, addr, &data);
719 if (err)
720 return err;
721
722 *tableaddr = data;
723 tableaddr++;
724
725 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
726 err = rtl8366_smi_read_reg(smi, addr, &data);
727 if (err)
728 return err;
729
730 *tableaddr = data;
731
732 return 0;
733 }
734
735 static int rtl8366s_set_vlan_member_config(struct rtl8366s *rtl, u32 index,
736 const struct rtl8366s_vlanconfig
737 *vlanmc)
738 {
739 struct rtl8366_smi *smi = &rtl->smi;
740 int err;
741 u32 addr;
742 u32 data;
743 u16 *tableaddr;
744
745 if (index >= RTL8366_NUM_VLANS ||
746 vlanmc->vid >= RTL8366_NUM_VIDS ||
747 vlanmc->priority > RTL8366S_PRIORITYMAX ||
748 vlanmc->member > RTL8366_PORT_ALL ||
749 vlanmc->untag > RTL8366_PORT_ALL ||
750 vlanmc->fid > RTL8366S_FIDMAX)
751 return -EINVAL;
752
753 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
754
755 tableaddr = (u16 *)vlanmc;
756 data = *tableaddr;
757
758 err = rtl8366_smi_write_reg(smi, addr, data);
759 if (err)
760 return err;
761
762 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
763
764 tableaddr++;
765 data = *tableaddr;
766
767 err = rtl8366_smi_write_reg(smi, addr, data);
768 if (err)
769 return err;
770
771 return 0;
772 }
773
774 static int rtl8366s_get_port_vlan_index(struct rtl8366s *rtl, int port,
775 int *val)
776 {
777 struct rtl8366_smi *smi = &rtl->smi;
778 u32 data;
779 int err;
780
781 if (port >= RTL8366_NUM_PORTS)
782 return -EINVAL;
783
784 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
785 &data);
786 if (err)
787 return err;
788
789 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
790 RTL8366S_PORT_VLAN_CTRL_MASK;
791
792 return 0;
793
794 }
795
796 static int rtl8366s_get_vlan_port_pvid(struct rtl8366s *rtl, int port,
797 int *val)
798 {
799 struct rtl8366s_vlanconfig vlanmc;
800 int err;
801 int index;
802
803 err = rtl8366s_get_port_vlan_index(rtl, port, &index);
804 if (err)
805 return err;
806
807 err = rtl8366s_get_vlan_member_config(rtl, index, &vlanmc);
808 if (err)
809 return err;
810
811 *val = vlanmc.vid;
812 return 0;
813 }
814
815 static int rtl8366s_set_port_vlan_index(struct rtl8366s *rtl, int port,
816 int index)
817 {
818 struct rtl8366_smi *smi = &rtl->smi;
819 u32 data;
820 int err;
821
822 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
823 return -EINVAL;
824
825 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
826 &data);
827 if (err)
828 return err;
829
830 data &= ~(RTL8366S_PORT_VLAN_CTRL_MASK <<
831 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
832 data |= (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
833 RTL8366S_PORT_VLAN_CTRL_SHIFT(port);
834
835 err = rtl8366_smi_write_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
836 data);
837 return err;
838 }
839
840 static int rtl8366s_set_vlan_port_pvid(struct rtl8366s *rtl, int port, int val)
841 {
842 int i;
843 struct rtl8366s_vlanconfig vlanmc;
844 struct rtl8366s_vlan4kentry vlan4k;
845
846 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
847 return -EINVAL;
848
849 /* Updating the 4K entry; lookup it and change the port member set */
850 rtl8366s_get_vlan_4k_entry(rtl, val, &vlan4k);
851 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
852 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
853 rtl8366s_set_vlan_4k_entry(rtl, &vlan4k);
854
855 /*
856 * For the 16 entries more work needs to be done. First see if such
857 * VID is already there and change it
858 */
859 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
860 rtl8366s_get_vlan_member_config(rtl, i, &vlanmc);
861
862 /* Try to find an existing vid and update port member set */
863 if (val == vlanmc.vid) {
864 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
865 rtl8366s_set_vlan_member_config(rtl, i, &vlanmc);
866
867 /* Now update PVID register settings */
868 rtl8366s_set_port_vlan_index(rtl, port, i);
869
870 return 0;
871 }
872 }
873
874 /*
875 * PVID could not be found from vlan table. Replace unused (one that
876 * has no member ports) with new one
877 */
878 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
879 rtl8366s_get_vlan_member_config(rtl, i, &vlanmc);
880
881 /*
882 * See if this vlan member configuration is unused. It is
883 * unused if member set contains no ports or CPU port only
884 */
885 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
886 vlanmc.vid = val;
887 vlanmc.priority = 0;
888 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
889 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
890 vlanmc.fid = 0;
891
892 rtl8366s_set_vlan_member_config(rtl, i, &vlanmc);
893
894 /* Now update PVID register settings */
895 rtl8366s_set_port_vlan_index(rtl, port, i);
896
897 return 0;
898 }
899 }
900
901 dev_err(rtl->parent,
902 "All 16 vlan member configurations are in use\n");
903
904 return -EINVAL;
905 }
906
907
908 static int rtl8366s_vlan_set_vlan(struct rtl8366s *rtl, int enable)
909 {
910 struct rtl8366_smi *smi = &rtl->smi;
911 u32 data = 0;
912
913 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
914
915 if (enable)
916 data |= RTL8366_CHIP_CTRL_VLAN;
917 else
918 data &= ~RTL8366_CHIP_CTRL_VLAN;
919
920 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
921 }
922
923 static int rtl8366s_vlan_set_4ktable(struct rtl8366s *rtl, int enable)
924 {
925 struct rtl8366_smi *smi = &rtl->smi;
926 u32 data = 0;
927
928 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
929
930 if (enable)
931 data |= 1;
932 else
933 data &= ~1;
934
935 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
936 }
937
938 static int rtl8366s_reset_vlan(struct rtl8366s *rtl)
939 {
940 struct rtl8366s_vlan4kentry vlan4k;
941 struct rtl8366s_vlanconfig vlanmc;
942 int err;
943 int i;
944
945 /* clear 16 VLAN member configuration */
946 vlanmc.vid = 0;
947 vlanmc.priority = 0;
948 vlanmc.member = 0;
949 vlanmc.untag = 0;
950 vlanmc.fid = 0;
951 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
952 err = rtl8366s_set_vlan_member_config(rtl, i, &vlanmc);
953 if (err)
954 return err;
955 }
956
957 /* Set a default VLAN with vid 1 to 4K table for all ports */
958 vlan4k.vid = 1;
959 vlan4k.member = RTL8366_PORT_ALL;
960 vlan4k.untag = RTL8366_PORT_ALL;
961 vlan4k.fid = 0;
962 err = rtl8366s_set_vlan_4k_entry(rtl, &vlan4k);
963 if (err)
964 return err;
965
966 /* Set all ports PVID to default VLAN */
967 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
968 err = rtl8366s_set_vlan_port_pvid(rtl, i, 0);
969 if (err)
970 return err;
971 }
972
973 return 0;
974 }
975
976 #ifdef CONFIG_RTL8366_SMI_DEBUG_FS
977 static int rtl8366s_debugfs_open(struct inode *inode, struct file *file)
978 {
979 file->private_data = inode->i_private;
980 return 0;
981 }
982
983 static ssize_t rtl8366s_read_debugfs_mibs(struct file *file,
984 char __user *user_buf,
985 size_t count, loff_t *ppos)
986 {
987 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
988 int i, j, len = 0;
989 char *buf = rtl->buf;
990
991 len += snprintf(buf + len, sizeof(rtl->buf) - len, "MIB Counters:\n");
992 len += snprintf(buf + len, sizeof(rtl->buf) - len, "Counter"
993 " "
994 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
995 "Port 4\n");
996
997 for (i = 0; i < 33; ++i) {
998 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%d:%s ",
999 i, MIBCOUNTERS[i]);
1000 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
1001 unsigned long long counter = 0;
1002
1003 if (!rtl8366_get_mib_counter(rtl, i, j, &counter))
1004 len += snprintf(buf + len,
1005 sizeof(rtl->buf) - len,
1006 "[%llu]", counter);
1007 else
1008 len += snprintf(buf + len,
1009 sizeof(rtl->buf) - len,
1010 "[error]");
1011
1012 if (j != RTL8366_NUM_PORTS - 1) {
1013 if (counter < 100000)
1014 len += snprintf(buf + len,
1015 sizeof(rtl->buf) - len,
1016 "\t");
1017
1018 len += snprintf(buf + len,
1019 sizeof(rtl->buf) - len,
1020 "\t");
1021 }
1022 }
1023 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1024 }
1025
1026 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1027
1028 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1029 }
1030
1031 static ssize_t rtl8366s_read_debugfs_vlan(struct file *file,
1032 char __user *user_buf,
1033 size_t count, loff_t *ppos)
1034 {
1035 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
1036 int i, j, len = 0;
1037 char *buf = rtl->buf;
1038
1039 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1040 "VLAN Member Config:\n");
1041 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1042 "\t id \t vid \t prio \t member \t untag \t fid "
1043 "\tports\n");
1044
1045 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
1046 struct rtl8366s_vlanconfig vlanmc;
1047
1048 rtl8366s_get_vlan_member_config(rtl, i, &vlanmc);
1049
1050 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1051 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
1052 "\t", i, vlanmc.vid, vlanmc.priority,
1053 vlanmc.member, vlanmc.untag, vlanmc.fid);
1054
1055 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
1056 int index = 0;
1057 if (!rtl8366s_get_port_vlan_index(rtl, j, &index)) {
1058 if (index == i)
1059 len += snprintf(buf + len,
1060 sizeof(rtl->buf) - len,
1061 "%d", j);
1062 }
1063 }
1064 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1065 }
1066
1067 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1068 }
1069
1070 static ssize_t rtl8366s_read_debugfs_reg(struct file *file,
1071 char __user *user_buf,
1072 size_t count, loff_t *ppos)
1073 {
1074 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
1075 struct rtl8366_smi *smi = &rtl->smi;
1076 u32 t, reg = g_dbg_reg;
1077 int err, len = 0;
1078 char *buf = rtl->buf;
1079
1080 memset(buf, '\0', sizeof(rtl->buf));
1081
1082 err = rtl8366_smi_read_reg(smi, reg, &t);
1083 if (err) {
1084 len += snprintf(buf, sizeof(rtl->buf),
1085 "Read failed (reg: 0x%04x)\n", reg);
1086 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1087 }
1088
1089 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
1090 reg, t);
1091
1092 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1093 }
1094
1095 static ssize_t rtl8366s_write_debugfs_reg(struct file *file,
1096 const char __user *user_buf,
1097 size_t count, loff_t *ppos)
1098 {
1099 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
1100 struct rtl8366_smi *smi = &rtl->smi;
1101 unsigned long data;
1102 u32 reg = g_dbg_reg;
1103 int err;
1104 size_t len;
1105 char *buf = rtl->buf;
1106
1107 len = min(count, sizeof(rtl->buf) - 1);
1108 if (copy_from_user(buf, user_buf, len)) {
1109 dev_err(rtl->parent, "copy from user failed\n");
1110 return -EFAULT;
1111 }
1112
1113 buf[len] = '\0';
1114 if (len > 0 && buf[len - 1] == '\n')
1115 buf[len - 1] = '\0';
1116
1117
1118 if (strict_strtoul(buf, 16, &data)) {
1119 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
1120 } else {
1121 err = rtl8366_smi_write_reg(smi, reg, data);
1122 if (err) {
1123 dev_err(rtl->parent,
1124 "writing reg 0x%04x val 0x%04lx failed\n",
1125 reg, data);
1126 }
1127 }
1128
1129 return count;
1130 }
1131
1132 static const struct file_operations fops_rtl8366s_regs = {
1133 .read = rtl8366s_read_debugfs_reg,
1134 .write = rtl8366s_write_debugfs_reg,
1135 .open = rtl8366s_debugfs_open,
1136 .owner = THIS_MODULE
1137 };
1138
1139 static const struct file_operations fops_rtl8366s_vlan = {
1140 .read = rtl8366s_read_debugfs_vlan,
1141 .open = rtl8366s_debugfs_open,
1142 .owner = THIS_MODULE
1143 };
1144
1145 static const struct file_operations fops_rtl8366s_mibs = {
1146 .read = rtl8366s_read_debugfs_mibs,
1147 .open = rtl8366s_debugfs_open,
1148 .owner = THIS_MODULE
1149 };
1150
1151 static void rtl8366s_debugfs_init(struct rtl8366s *rtl)
1152 {
1153 struct dentry *node;
1154 struct dentry *root;
1155
1156 if (!rtl->debugfs_root)
1157 rtl->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
1158
1159 if (!rtl->debugfs_root) {
1160 dev_err(rtl->parent, "Unable to create debugfs dir\n");
1161 return;
1162 }
1163 root = rtl->debugfs_root;
1164
1165 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
1166 if (!node) {
1167 dev_err(rtl->parent, "Creating debugfs file reg failed\n");
1168 return;
1169 }
1170
1171 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
1172 &fops_rtl8366s_regs);
1173 if (!node) {
1174 dev_err(rtl->parent, "Creating debugfs file val failed\n");
1175 return;
1176 }
1177
1178 node = debugfs_create_file("vlan", S_IRUSR, root, rtl,
1179 &fops_rtl8366s_vlan);
1180 if (!node) {
1181 dev_err(rtl->parent,
1182 "Creating debugfs file vlan failed\n");
1183 return;
1184 }
1185
1186 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
1187 &fops_rtl8366s_mibs);
1188 if (!node) {
1189 dev_err(rtl->parent,
1190 "Creating debugfs file mibs failed\n");
1191 return;
1192 }
1193 }
1194
1195 static void rtl8366s_debugfs_remove(struct rtl8366s *rtl)
1196 {
1197 if (rtl->debugfs_root) {
1198 debugfs_remove_recursive(rtl->debugfs_root);
1199 rtl->debugfs_root = NULL;
1200 }
1201 }
1202
1203 #else
1204 static inline void rtl8366s_debugfs_init(struct rtl8366s *rtl) {}
1205 static inline void rtl8366s_debugfs_remove(struct rtl8366s *rtl) {}
1206 #endif /* CONFIG_RTL8366_SMI_DEBUG_FS */
1207
1208 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
1209 const struct switch_attr *attr,
1210 struct switch_val *val)
1211 {
1212 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1213 struct rtl8366_smi *smi = &rtl->smi;
1214 u32 data = 0;
1215
1216 if (val->value.i == 1) {
1217 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1218 data |= (1 << 2);
1219 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1220 }
1221
1222 return 0;
1223 }
1224
1225 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
1226 const struct switch_attr *attr,
1227 struct switch_val *val)
1228 {
1229 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1230 struct rtl8366_smi *smi = &rtl->smi;
1231 u32 data;
1232
1233 if (attr->ofs == 1) {
1234 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1235
1236 if (data & RTL8366_CHIP_CTRL_VLAN)
1237 val->value.i = 1;
1238 else
1239 val->value.i = 0;
1240 } else if (attr->ofs == 2) {
1241 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1242
1243 if (data & 0x0001)
1244 val->value.i = 1;
1245 else
1246 val->value.i = 0;
1247 }
1248
1249 return 0;
1250 }
1251
1252 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
1253 const struct switch_attr *attr,
1254 struct switch_val *val)
1255 {
1256 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1257 struct rtl8366_smi *smi = &rtl->smi;
1258 u32 data;
1259
1260 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1261
1262 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1263
1264 return 0;
1265 }
1266
1267 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
1268 const struct switch_attr *attr,
1269 struct switch_val *val)
1270 {
1271 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1272 struct rtl8366_smi *smi = &rtl->smi;
1273 u32 data;
1274
1275 if (val->value.i >= 6)
1276 return -EINVAL;
1277
1278 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1279
1280 data &= ~RTL8366_LED_BLINKRATE_MASK;
1281 data |= val->value.i;
1282
1283 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1284
1285 return 0;
1286 }
1287
1288 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
1289 const struct switch_attr *attr,
1290 struct switch_val *val)
1291 {
1292 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1293
1294 if (attr->ofs == 1)
1295 return rtl8366s_vlan_set_vlan(rtl, val->value.i);
1296 else
1297 return rtl8366s_vlan_set_4ktable(rtl, val->value.i);
1298 }
1299
1300 static const char *rtl8366s_speed_str(unsigned speed)
1301 {
1302 switch (speed) {
1303 case 0:
1304 return "10baseT";
1305 case 1:
1306 return "100baseT";
1307 case 2:
1308 return "1000baseT";
1309 }
1310
1311 return "unknown";
1312 }
1313
1314 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
1315 const struct switch_attr *attr,
1316 struct switch_val *val)
1317 {
1318 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1319 struct rtl8366_smi *smi = &rtl->smi;
1320 u32 len = 0, data = 0;
1321
1322 if (val->port_vlan >= RTL8366_NUM_PORTS)
1323 return -EINVAL;
1324
1325 memset(rtl->buf, '\0', sizeof(rtl->buf));
1326 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1327 (val->port_vlan / 2), &data);
1328
1329 if (val->port_vlan % 2)
1330 data = data >> 8;
1331
1332 len = snprintf(rtl->buf, sizeof(rtl->buf),
1333 "port:%d link:%s speed:%s %s-duplex %s%s%s",
1334 val->port_vlan,
1335 (data & RTL8366S_PORT_STATUS_LINK_MASK) ? "up" : "down",
1336 rtl8366s_speed_str(data &
1337 RTL8366S_PORT_STATUS_SPEED_MASK),
1338 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1339 "full" : "half",
1340 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1341 "tx-pause ": "",
1342 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1343 "rx-pause " : "",
1344 (data & RTL8366S_PORT_STATUS_AN_MASK) ? "nway ": "");
1345
1346 val->value.s = rtl->buf;
1347 val->len = len;
1348
1349 return 0;
1350 }
1351
1352 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
1353 const struct switch_attr *attr,
1354 struct switch_val *val)
1355 {
1356 int i;
1357 u32 len = 0;
1358 struct rtl8366s_vlanconfig vlanmc;
1359 struct rtl8366s_vlan4kentry vlan4k;
1360 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1361 char *buf = rtl->buf;
1362
1363 if (val->port_vlan >= RTL8366_NUM_VLANS)
1364 return -EINVAL;
1365
1366 memset(buf, '\0', sizeof(rtl->buf));
1367
1368 rtl8366s_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1369 rtl8366s_get_vlan_4k_entry(rtl, vlanmc.vid, &vlan4k);
1370
1371 len += snprintf(buf + len, sizeof(rtl->buf) - len, "VLAN %d: Ports: ",
1372 val->port_vlan);
1373
1374 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1375 int index = 0;
1376 if (!rtl8366s_get_port_vlan_index(rtl, i, &index) &&
1377 index == val->port_vlan)
1378 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1379 "%d", i);
1380 }
1381 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1382
1383 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1384 "\t\t vid \t prio \t member \t untag \t fid\n");
1385 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\tMC:\t");
1386 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1387 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1388 vlanmc.vid, vlanmc.priority, vlanmc.member,
1389 vlanmc.untag, vlanmc.fid);
1390 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\t4K:\t");
1391 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1392 "%d \t \t 0x%04x \t 0x%04x \t %d",
1393 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1394
1395 val->value.s = buf;
1396 val->len = len;
1397
1398 return 0;
1399 }
1400
1401 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
1402 const struct switch_attr *attr,
1403 struct switch_val *val)
1404 {
1405 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1406 struct rtl8366_smi *smi = &rtl->smi;
1407 u32 data = 0;
1408
1409 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1410 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1411 return -EINVAL;
1412
1413 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1414 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1415 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1416 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1417 } else {
1418 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1419 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1420 (val->value.i << (val->port_vlan * 4));
1421 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1422 }
1423
1424 return 0;
1425 }
1426
1427 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
1428 const struct switch_attr *attr,
1429 struct switch_val *val)
1430 {
1431 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1432 struct rtl8366_smi *smi = &rtl->smi;
1433 u32 data = 0;
1434
1435 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1436 return -EINVAL;
1437
1438 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1439 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1440
1441 return 0;
1442 }
1443
1444 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
1445 const struct switch_attr *attr,
1446 struct switch_val *val)
1447 {
1448 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1449 struct rtl8366_smi *smi = &rtl->smi;
1450 u32 data = 0;
1451
1452 if (val->port_vlan >= RTL8366_NUM_PORTS)
1453 return -EINVAL;
1454
1455 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1456 data |= (1 << (val->port_vlan + 3));
1457 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1458
1459 return 0;
1460 }
1461
1462 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
1463 const struct switch_attr *attr,
1464 struct switch_val *val)
1465 {
1466 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1467 int i, len = 0;
1468 unsigned long long counter = 0;
1469 char *buf = rtl->buf;
1470
1471 if (val->port_vlan >= RTL8366_NUM_PORTS)
1472 return -EINVAL;
1473
1474 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1475 "Port %d MIB counters\n",
1476 val->port_vlan);
1477
1478 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1479 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1480 "%d:%s\t", i, MIBCOUNTERS[i]);
1481 if (!rtl8366_get_mib_counter(rtl, i, val->port_vlan, &counter))
1482 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1483 "[%llu]\n", counter);
1484 else
1485 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1486 "[error]\n");
1487 }
1488
1489 val->value.s = buf;
1490 val->len = len;
1491 return 0;
1492 }
1493
1494 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
1495 struct switch_val *val)
1496 {
1497 struct rtl8366s_vlanconfig vlanmc;
1498 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1499 struct switch_port *port;
1500 int i;
1501
1502 if (val->port_vlan >= RTL8366_NUM_VLANS)
1503 return -EINVAL;
1504
1505 rtl8366s_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1506
1507 port = &val->value.ports[0];
1508 val->len = 0;
1509 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1510 if (!(vlanmc.member & BIT(i)))
1511 continue;
1512
1513 port->id = i;
1514 port->flags = (vlanmc.untag & BIT(i)) ?
1515 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1516 val->len++;
1517 port++;
1518 }
1519 return 0;
1520 }
1521
1522 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
1523 struct switch_val *val)
1524 {
1525 struct rtl8366s_vlanconfig vlanmc;
1526 struct rtl8366s_vlan4kentry vlan4k;
1527 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1528 struct switch_port *port;
1529 int i;
1530
1531 if (val->port_vlan >= RTL8366_NUM_VLANS)
1532 return -EINVAL;
1533
1534 rtl8366s_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1535 rtl8366s_get_vlan_4k_entry(rtl, vlanmc.vid, &vlan4k);
1536
1537 vlanmc.untag = 0;
1538 vlanmc.member = 0;
1539
1540 port = &val->value.ports[0];
1541 for (i = 0; i < val->len; i++, port++) {
1542 vlanmc.member |= BIT(port->id);
1543
1544 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1545 vlanmc.untag |= BIT(port->id);
1546 }
1547
1548 vlan4k.member = vlanmc.member;
1549 vlan4k.untag = vlanmc.untag;
1550
1551 rtl8366s_set_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1552 rtl8366s_set_vlan_4k_entry(rtl, &vlan4k);
1553 return 0;
1554 }
1555
1556 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1557 {
1558 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1559 return rtl8366s_get_vlan_port_pvid(rtl, port, val);
1560 }
1561
1562 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1563 {
1564 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1565 return rtl8366s_set_vlan_port_pvid(rtl, port, val);
1566 }
1567
1568 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
1569 {
1570 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1571 struct rtl8366_smi *smi = &rtl->smi;
1572 int timeout = 10;
1573 u32 data;
1574
1575 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
1576 RTL8366_CHIP_CTRL_RESET_HW);
1577 do {
1578 msleep(1);
1579 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
1580 return -EIO;
1581
1582 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
1583 break;
1584 } while (--timeout);
1585
1586 if (!timeout) {
1587 printk("Timeout waiting for the switch to reset\n");
1588 return -EIO;
1589 }
1590
1591 return rtl8366s_reset_vlan(rtl);
1592 }
1593
1594 static struct switch_attr rtl8366s_globals[] = {
1595 {
1596 .type = SWITCH_TYPE_INT,
1597 .name = "enable_vlan",
1598 .description = "Enable VLAN mode",
1599 .set = rtl8366s_sw_set_vlan_enable,
1600 .get = rtl8366s_sw_get_vlan_enable,
1601 .max = 1,
1602 .ofs = 1
1603 }, {
1604 .type = SWITCH_TYPE_INT,
1605 .name = "enable_vlan4k",
1606 .description = "Enable VLAN 4K mode",
1607 .set = rtl8366s_sw_set_vlan_enable,
1608 .get = rtl8366s_sw_get_vlan_enable,
1609 .max = 1,
1610 .ofs = 2
1611 }, {
1612 .type = SWITCH_TYPE_INT,
1613 .name = "reset_mibs",
1614 .description = "Reset all MIB counters",
1615 .set = rtl8366s_sw_reset_mibs,
1616 .get = NULL,
1617 .max = 1
1618 }, {
1619 .type = SWITCH_TYPE_INT,
1620 .name = "blinkrate",
1621 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1622 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1623 .set = rtl8366s_sw_set_blinkrate,
1624 .get = rtl8366s_sw_get_blinkrate,
1625 .max = 5
1626 },
1627 };
1628
1629 static struct switch_attr rtl8366s_port[] = {
1630 {
1631 .type = SWITCH_TYPE_STRING,
1632 .name = "link",
1633 .description = "Get port link information",
1634 .max = 1,
1635 .set = NULL,
1636 .get = rtl8366s_sw_get_port_link,
1637 }, {
1638 .type = SWITCH_TYPE_INT,
1639 .name = "reset_mib",
1640 .description = "Reset single port MIB counters",
1641 .max = 1,
1642 .set = rtl8366s_sw_reset_port_mibs,
1643 .get = NULL,
1644 }, {
1645 .type = SWITCH_TYPE_STRING,
1646 .name = "mib",
1647 .description = "Get MIB counters for port",
1648 .max = 33,
1649 .set = NULL,
1650 .get = rtl8366s_sw_get_port_mib,
1651 }, {
1652 .type = SWITCH_TYPE_INT,
1653 .name = "led",
1654 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1655 .max = 15,
1656 .set = rtl8366s_sw_set_port_led,
1657 .get = rtl8366s_sw_get_port_led,
1658 },
1659 };
1660
1661 static struct switch_attr rtl8366s_vlan[] = {
1662 {
1663 .type = SWITCH_TYPE_STRING,
1664 .name = "info",
1665 .description = "Get vlan information",
1666 .max = 1,
1667 .set = NULL,
1668 .get = rtl8366s_sw_get_vlan_info,
1669 },
1670 };
1671
1672
1673 /* template */
1674 static struct switch_dev rtl8366_switch_dev = {
1675 .name = "RTL8366S",
1676 .cpu_port = RTL8366_PORT_NUM_CPU,
1677 .ports = RTL8366_NUM_PORTS,
1678 .vlans = RTL8366_NUM_VLANS,
1679 .attr_global = {
1680 .attr = rtl8366s_globals,
1681 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1682 },
1683 .attr_port = {
1684 .attr = rtl8366s_port,
1685 .n_attr = ARRAY_SIZE(rtl8366s_port),
1686 },
1687 .attr_vlan = {
1688 .attr = rtl8366s_vlan,
1689 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1690 },
1691
1692 .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1693 .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1694 .get_port_pvid = rtl8366s_sw_get_port_pvid,
1695 .set_port_pvid = rtl8366s_sw_set_port_pvid,
1696 .reset_switch = rtl8366s_sw_reset_switch,
1697 };
1698
1699 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1700 {
1701 struct switch_dev *dev = &rtl->dev;
1702 int err;
1703
1704 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1705 dev->priv = rtl;
1706 dev->devname = dev_name(rtl->parent);
1707
1708 err = register_switch(dev, NULL);
1709 if (err)
1710 dev_err(rtl->parent, "switch registration failed\n");
1711
1712 return err;
1713 }
1714
1715 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1716 {
1717 unregister_switch(&rtl->dev);
1718 }
1719
1720 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1721 {
1722 struct rtl8366s *rtl = bus->priv;
1723 u32 val = 0;
1724 int err;
1725
1726 err = rtl8366s_read_phy_reg(rtl, addr, 0, reg, &val);
1727 if (err)
1728 return 0xffff;
1729
1730 return val;
1731 }
1732
1733 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1734 {
1735 struct rtl8366s *rtl = bus->priv;
1736 u32 t;
1737 int err;
1738
1739 err = rtl8366s_write_phy_reg(rtl, addr, 0, reg, val);
1740 /* flush write */
1741 (void) rtl8366s_read_phy_reg(rtl, addr, 0, reg, &t);
1742
1743 return err;
1744 }
1745
1746 static int rtl8366s_mii_init(struct rtl8366s *rtl)
1747 {
1748 int ret;
1749 int i;
1750
1751 rtl->mii_bus = mdiobus_alloc();
1752 if (rtl->mii_bus == NULL) {
1753 ret = -ENOMEM;
1754 goto err;
1755 }
1756
1757 rtl->mii_bus->priv = (void *) rtl;
1758 rtl->mii_bus->name = "rtl8366-rtl";
1759 rtl->mii_bus->read = rtl8366s_mii_read;
1760 rtl->mii_bus->write = rtl8366s_mii_write;
1761 snprintf(rtl->mii_bus->id, MII_BUS_ID_SIZE, "%s",
1762 dev_name(rtl->parent));
1763 rtl->mii_bus->parent = rtl->parent;
1764 rtl->mii_bus->phy_mask = ~(0x1f);
1765 rtl->mii_bus->irq = rtl->mii_irq;
1766 for (i = 0; i < PHY_MAX_ADDR; i++)
1767 rtl->mii_irq[i] = PHY_POLL;
1768
1769 ret = mdiobus_register(rtl->mii_bus);
1770 if (ret)
1771 goto err_free;
1772
1773 return 0;
1774
1775 err_free:
1776 mdiobus_free(rtl->mii_bus);
1777 err:
1778 return ret;
1779 }
1780
1781 static void rtl8366s_mii_cleanup(struct rtl8366s *rtl)
1782 {
1783 mdiobus_unregister(rtl->mii_bus);
1784 mdiobus_free(rtl->mii_bus);
1785 }
1786
1787 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1788 {
1789 return (bus->read == rtl8366s_mii_read &&
1790 bus->write == rtl8366s_mii_write);
1791 }
1792
1793 static int rtl8366s_setup(struct rtl8366s *rtl)
1794 {
1795 struct rtl8366_smi *smi = &rtl->smi;
1796 u32 chip_id = 0;
1797 u32 chip_ver = 0;
1798 int ret;
1799
1800 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1801 if (ret) {
1802 dev_err(rtl->parent, "unable to read chip id\n");
1803 return ret;
1804 }
1805
1806 switch (chip_id) {
1807 case RTL8366S_CHIP_ID_8366:
1808 break;
1809 default:
1810 dev_err(rtl->parent, "unknown chip id (%04x)\n", chip_id);
1811 return -ENODEV;
1812 }
1813
1814 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1815 &chip_ver);
1816 if (ret) {
1817 dev_err(rtl->parent, "unable to read chip version\n");
1818 return ret;
1819 }
1820
1821 dev_info(rtl->parent, "RTL%04x ver. %u chip found\n",
1822 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1823
1824 rtl8366s_debugfs_init(rtl);
1825
1826 return 0;
1827 }
1828
1829 static int __init rtl8366_smi_init(struct rtl8366_smi *smi)
1830 {
1831 int err;
1832
1833 if (!smi->parent)
1834 return -EINVAL;
1835
1836 err = gpio_request(smi->gpio_sda, dev_name(smi->parent));
1837 if (err) {
1838 dev_err(smi->parent, "gpio_request failed for %u, err=%d\n",
1839 smi->gpio_sda, err);
1840 goto err_out;
1841 }
1842
1843 err = gpio_request(smi->gpio_sck, dev_name(smi->parent));
1844 if (err) {
1845 dev_err(smi->parent, "gpio_request failed for %u, err=%d\n",
1846 smi->gpio_sck, err);
1847 goto err_free_sda;
1848 }
1849
1850 spin_lock_init(&smi->lock);
1851
1852 dev_info(smi->parent, "using GPIO pins %u (SDA) and %u (SCK)\n",
1853 smi->gpio_sda, smi->gpio_sck);
1854
1855 return 0;
1856
1857 err_free_sda:
1858 gpio_free(smi->gpio_sda);
1859 err_out:
1860 return err;
1861 }
1862
1863 static void rtl8366_smi_cleanup(struct rtl8366_smi *smi)
1864 {
1865 gpio_free(smi->gpio_sck);
1866 gpio_free(smi->gpio_sda);
1867 }
1868
1869 static int __init rtl8366s_probe(struct platform_device *pdev)
1870 {
1871 static int rtl8366_smi_version_printed;
1872 struct rtl8366_smi_platform_data *pdata;
1873 struct rtl8366s *rtl;
1874 struct rtl8366_smi *smi;
1875 int err;
1876
1877 if (!rtl8366_smi_version_printed++)
1878 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1879 " version " RTL8366S_DRIVER_VER"\n");
1880
1881 pdata = pdev->dev.platform_data;
1882 if (!pdata) {
1883 dev_err(&pdev->dev, "no platform data specified\n");
1884 err = -EINVAL;
1885 goto err_out;
1886 }
1887
1888 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1889 if (!rtl) {
1890 dev_err(&pdev->dev, "no memory for private data\n");
1891 err = -ENOMEM;
1892 goto err_out;
1893 }
1894
1895 rtl->parent = &pdev->dev;
1896
1897 smi = &rtl->smi;
1898 smi->parent = &pdev->dev;
1899 smi->gpio_sda = pdata->gpio_sda;
1900 smi->gpio_sck = pdata->gpio_sck;
1901
1902 err = rtl8366_smi_init(smi);
1903 if (err)
1904 goto err_free_rtl;
1905
1906 platform_set_drvdata(pdev, rtl);
1907
1908 err = rtl8366s_setup(rtl);
1909 if (err)
1910 goto err_clear_drvdata;
1911
1912 err = rtl8366s_mii_init(rtl);
1913 if (err)
1914 goto err_clear_drvdata;
1915
1916 err = rtl8366s_switch_init(rtl);
1917 if (err)
1918 goto err_mii_cleanup;
1919
1920 return 0;
1921
1922 err_mii_cleanup:
1923 rtl8366s_mii_cleanup(rtl);
1924 err_clear_drvdata:
1925 platform_set_drvdata(pdev, NULL);
1926 rtl8366_smi_cleanup(smi);
1927 err_free_rtl:
1928 kfree(rtl);
1929 err_out:
1930 return err;
1931 }
1932
1933 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1934 {
1935 if (!rtl8366s_mii_bus_match(phydev->bus))
1936 return -EINVAL;
1937
1938 return 0;
1939 }
1940
1941 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1942 {
1943 return 0;
1944 }
1945
1946 static struct phy_driver rtl8366s_phy_driver = {
1947 .phy_id = 0x001cc960,
1948 .name = "Realtek RTL8366",
1949 .phy_id_mask = 0x1ffffff0,
1950 .features = PHY_GBIT_FEATURES,
1951 .config_aneg = rtl8366s_phy_config_aneg,
1952 .config_init = rtl8366s_phy_config_init,
1953 .read_status = genphy_read_status,
1954 .driver = {
1955 .owner = THIS_MODULE,
1956 },
1957 };
1958
1959 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1960 {
1961 struct rtl8366s *rtl = platform_get_drvdata(pdev);
1962
1963 if (rtl) {
1964 rtl8366s_switch_cleanup(rtl);
1965 rtl8366s_debugfs_remove(rtl);
1966 rtl8366s_mii_cleanup(rtl);
1967 platform_set_drvdata(pdev, NULL);
1968 rtl8366_smi_cleanup(&rtl->smi);
1969 kfree(rtl);
1970 }
1971
1972 return 0;
1973 }
1974
1975 static struct platform_driver rtl8366s_driver = {
1976 .driver = {
1977 .name = RTL8366S_DRIVER_NAME,
1978 .owner = THIS_MODULE,
1979 },
1980 .probe = rtl8366s_probe,
1981 .remove = __devexit_p(rtl8366s_remove),
1982 };
1983
1984 static int __init rtl8366s_module_init(void)
1985 {
1986 int ret;
1987 ret = platform_driver_register(&rtl8366s_driver);
1988 if (ret)
1989 return ret;
1990
1991 ret = phy_driver_register(&rtl8366s_phy_driver);
1992 if (ret)
1993 goto err_platform_unregister;
1994
1995 return 0;
1996
1997 err_platform_unregister:
1998 platform_driver_unregister(&rtl8366s_driver);
1999 return ret;
2000 }
2001 module_init(rtl8366s_module_init);
2002
2003 static void __exit rtl8366s_module_exit(void)
2004 {
2005 phy_driver_unregister(&rtl8366s_phy_driver);
2006 platform_driver_unregister(&rtl8366s_driver);
2007 }
2008 module_exit(rtl8366s_module_exit);
2009
2010 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
2011 MODULE_VERSION(RTL8366S_DRIVER_VER);
2012 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
2013 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
2014 MODULE_LICENSE("GPL v2");
2015 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);
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