package/uboot-ifxmips/files/board/ifx/danube/lowlevel_init.S

   1
   2 /*
   3  *  Memory sub-system initialization code for INCA-IP2 development board.
   4  *  Andre Messerschmidt
   5  *  Copyright (c) 2005  Infineon Technologies AG
   6  *
   7  *  Based on Inca-IP code
   8  *  Copyright (c) 2003  Wolfgang Denk <wd@denx.de>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28 /* History:
  29       peng liu May 25, 2006, for PLL setting after reset, 05252006
  30  */
  31 #include <config.h>
  32 #include <version.h>
  33 #include <asm/regdef.h>
  34 #include <configs/danube.h>
  35
  36
  37 #ifdef USE_REFERENCE_BOARD
  38 #ifdef DANUBE_DDR_RAM_111M
  39 #include "ddr_settings_r111.h"
  40 #elif defined(PROMOSDDR400)
  41 #include "ddr_settings_PROMOSDDR400.h"
  42 #elif defined(DDR_SAMSUNG_166M)
  43 #include "ddr_settings_Samsung_166.h"
  44 #elif defined(DDR_PSC_166M)
  45 #include "ddr_settings_psc_166.h"
  46 #else
  47 #include "ddr_settings_r166.h"
  48 #endif
  49 #endif
  50
  51 #ifdef USE_EVALUATION_BOARD
  52 #ifdef DANUBE_DDR_RAM_111M
  53 #include "ddr_settings_e111.h"
  54 #else
  55 #include "ddr_settings_e166.h"
  56 #endif
  57 #endif
  58
  59
  60
  61 /*TODO: liupeng check !!! */
  62 #define EBU_MODUL_BASE          0xB4102000
  63 #define EBU_CLC(value)          0x0000(value)
  64 #define EBU_CON(value)          0x0010(value)
  65 #define EBU_ADDSEL0(value)      0x0020(value)
  66 #define EBU_ADDSEL1(value)      0x0024(value)
  67 #define EBU_ADDSEL2(value)      0x0028(value)
  68 #define EBU_ADDSEL3(value)      0x002C(value)
  69 #define EBU_BUSCON0(value)      0x0060(value)
  70 #define EBU_BUSCON1(value)      0x0064(value)
  71 #define EBU_BUSCON2(value)      0x0068(value)
  72 #define EBU_BUSCON3(value)      0x006C(value)
  73
  74 #define MC_MODUL_BASE           0xBF800000
  75 #define MC_ERRCAUSE(value)      0x0010(value)
  76 #define MC_ERRADDR(value)       0x0020(value)
  77 #define MC_CON(value)           0x0060(value)
  78
  79 #define MC_SRAM_ENABLE          0x00000004
  80 #define MC_SDRAM_ENABLE         0x00000002
  81 #define MC_DDRRAM_ENABLE        0x00000001
  82
  83 #define MC_SDR_MODUL_BASE       0xBF800200
  84 #define MC_IOGP(value)          0x0000(value)
  85 #define MC_CTRLENA(value)       0x0010(value)
  86 #define MC_MRSCODE(value)       0x0020(value)
  87 #define MC_CFGDW(value)         0x0030(value)
  88 #define MC_CFGPB0(value)        0x0040(value)
  89 #define MC_LATENCY(value)       0x0080(value)
  90 #define MC_TREFRESH(value)      0x0090(value)
  91 #define MC_SELFRFSH(value)      0x00A0(value)
  92
  93 #define MC_DDR_MODUL_BASE       0xBF801000
  94 #define MC_DC00(value)          0x0000(value)
  95 #define MC_DC01(value)          0x0010(value)
  96 #define MC_DC02(value)          0x0020(value)
  97 #define MC_DC03(value)          0x0030(value)
  98 #define MC_DC04(value)          0x0040(value)
  99 #define MC_DC05(value)          0x0050(value)
 100 #define MC_DC06(value)          0x0060(value)
 101 #define MC_DC07(value)          0x0070(value)
 102 #define MC_DC08(value)          0x0080(value)
 103 #define MC_DC09(value)          0x0090(value)
 104 #define MC_DC10(value)          0x00A0(value)
 105 #define MC_DC11(value)          0x00B0(value)
 106 #define MC_DC12(value)          0x00C0(value)
 107 #define MC_DC13(value)          0x00D0(value)
 108 #define MC_DC14(value)          0x00E0(value)
 109 #define MC_DC15(value)          0x00F0(value)
 110 #define MC_DC16(value)          0x0100(value)
 111 #define MC_DC17(value)          0x0110(value)
 112 #define MC_DC18(value)          0x0120(value)
 113 #define MC_DC19(value)          0x0130(value)
 114 #define MC_DC20(value)          0x0140(value)
 115 #define MC_DC21(value)          0x0150(value)
 116 #define MC_DC22(value)          0x0160(value)
 117 #define MC_DC23(value)          0x0170(value)
 118 #define MC_DC24(value)          0x0180(value)
 119 #define MC_DC25(value)          0x0190(value)
 120 #define MC_DC26(value)          0x01A0(value)
 121 #define MC_DC27(value)          0x01B0(value)
 122 #define MC_DC28(value)          0x01C0(value)
 123 #define MC_DC29(value)          0x01D0(value)
 124 #define MC_DC30(value)          0x01E0(value)
 125 #define MC_DC31(value)          0x01F0(value)
 126 #define MC_DC32(value)          0x0200(value)
 127 #define MC_DC33(value)          0x0210(value)
 128 #define MC_DC34(value)          0x0220(value)
 129 #define MC_DC35(value)          0x0230(value)
 130 #define MC_DC36(value)          0x0240(value)
 131 #define MC_DC37(value)          0x0250(value)
 132 #define MC_DC38(value)          0x0260(value)
 133 #define MC_DC39(value)          0x0270(value)
 134 #define MC_DC40(value)          0x0280(value)
 135 #define MC_DC41(value)          0x0290(value)
 136 #define MC_DC42(value)          0x02A0(value)
 137 #define MC_DC43(value)          0x02B0(value)
 138 #define MC_DC44(value)          0x02C0(value)
 139 #define MC_DC45(value)          0x02D0(value)
 140 #define MC_DC46(value)          0x02E0(value)
 141
 142 #define RCU_OFFSET  0xBF203000
 143 #define RCU_RST_REQ      (RCU_OFFSET + 0x0010)
 144 #define RCU_STS          (RCU_OFFSET + 0x0014)
 145
 146 #define CGU_OFFSET  0xBF103000
 147 #define  PLL0_CFG     (CGU_OFFSET + 0x0004)
 148 #define  PLL1_CFG     (CGU_OFFSET + 0x0008)
 149 #define  PLL2_CFG     (CGU_OFFSET + 0x000C)
 150 #define  CGU_SYS      (CGU_OFFSET + 0x0010)
 151 #define  CGU_UPDATE   (CGU_OFFSET + 0x0014)
 152 #define  IF_CLK       (CGU_OFFSET + 0x0018)
 153 #define  CGU_SMD      (CGU_OFFSET + 0x0020)
 154 #define  CGU_CT1SR    (CGU_OFFSET + 0x0028)
 155 #define  CGU_CT2SR    (CGU_OFFSET + 0x002C)
 156 #define  CGU_PCMCR    (CGU_OFFSET + 0x0030)
 157 #define  PCI_CR_PCI   (CGU_OFFSET + 0x0034)
 158 #define  CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
 159 #define  CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
 160 #define  CLK_MEASURE  (CGU_OFFSET + 0x003C)
 161
 162 //05252006
 163 #define  pll0_35MHz_CONFIG 0x9D861059
 164 #define  pll1_35MHz_CONFIG 0x1A260CD9
 165 #define  pll2_35MHz_CONFIG 0x8000f1e5
 166 #define  pll0_36MHz_CONFIG 0x1000125D
 167 #define  pll1_36MHz_CONFIG 0x1B1E0C99
 168 #define  pll2_36MHz_CONFIG 0x8002f2a1
 169 //05252006
 170
 171 //06063001-joelin disable the PCI CFRAME mask -start
 172 /*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
 173 But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
 174
 175 The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
 176 The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
 177 */
 178 #define PCI_CR_PR_OFFSET  0xBE105400
 179 #define PCI_CR_PCI_MOD_REG          (PCI_CR_PR_OFFSET + 0x0030)
 180 #define PCI_CONFIG_SPACE  0xB7000000
 181 #define CS_CFM          (PCI_CONFIG_SPACE + 0x6C)
 182 //06063001-joelin disable the PCI CFRAME mask -end
 183         .set    noreorder
 184
 185
 186 /*
 187  * void ebu_init(long)
 188  *
 189  * a0 has the clock value we are going to run at
 190  */
 191         .globl  ebu_init
 192         .ent    ebu_init
 193 ebu_init:
 194 /*TODO:liupeng */
 195         j       ra
 196         nop
 197
 198         .end    ebu_init
 199
 200
 201 /*
 202  * void cgu_init(long)
 203  *
 204  * a0 has the clock value
 205  */
 206         .globl  cgu_init
 207         .ent    cgu_init
 208 cgu_init:
 209         li  t2, CGU_SYS
 210   lw  t2,0(t2)
 211   beq t2,a0,freq_up2date
 212   nop
 213
 214         li  t2, RCU_STS
 215         lw  t2, 0(t2)
 216         and t2,0x00020000
 217         beq t2,0x00020000,boot_36MHZ
 218   nop
 219 //05252006
 220         li  t1, PLL0_CFG
 221         li  t2, pll0_35MHz_CONFIG
 222         sw      t2,0(t1)
 223         li  t1, PLL1_CFG
 224         li  t2, pll1_35MHz_CONFIG
 225         sw      t2,0(t1)
 226         li  t1, PLL2_CFG
 227         li  t2, pll2_35MHz_CONFIG
 228         sw      t2,0(t1)
 229         li  t1, CGU_SYS
 230         sw      a0,0(t1)
 231         li  t1, RCU_RST_REQ
 232         li  t2, 0x40000008
 233         sw      t2,0(t1)
 234         b   wait_reset
 235         nop
 236 boot_36MHZ:
 237         li  t1, PLL0_CFG
 238         li  t2, pll0_36MHz_CONFIG
 239         sw      t2,0(t1)
 240         li  t1, PLL1_CFG
 241         li  t2, pll1_36MHz_CONFIG
 242         sw      t2,0(t1)
 243         li  t1, PLL2_CFG
 244         li  t2, pll2_36MHz_CONFIG
 245         sw      t2,0(t1)
 246         li  t1, CGU_SYS
 247         sw      a0,0(t1)
 248         li  t1, RCU_RST_REQ
 249         li  t2, 0x40000008
 250         sw      t2,0(t1)
 251 //05252006
 252
 253 wait_reset:
 254     b   wait_reset
 255     nop
 256 freq_up2date:
 257     j ra
 258     nop
 259         .end    cgu_init
 260
 261
 262 /*
 263  * void sdram_init(long)
 264  *
 265  * a0 has the clock value
 266  */
 267         .globl  sdram_init
 268         .ent    sdram_init
 269 sdram_init:
 270
 271         /* SDRAM Initialization
 272          */
 273         li      t1, MC_MODUL_BASE
 274
 275         /* Clear Error log registers */
 276         sw      zero, MC_ERRCAUSE(t1)
 277         sw      zero, MC_ERRADDR(t1)
 278
 279         /* Enable SDRAM module in memory controller */
 280         li      t3, MC_SDRAM_ENABLE
 281         lw      t2, MC_CON(t1)
 282         or      t3, t2, t3
 283         sw      t3, MC_CON(t1)
 284
 285         li      t1, MC_SDR_MODUL_BASE
 286
 287         /* disable the controller */
 288         li      t2, 0
 289         sw      t2, MC_CTRLENA(t1)
 290
 291         li      t2, 0x822
 292         sw      t2, MC_IOGP(t1)
 293
 294         li      t2, 0x2
 295         sw      t2, MC_CFGDW(t1)
 296
 297         /* Set CAS Latency */
 298         li      t2, 0x00000020
 299         sw      t2, MC_MRSCODE(t1)
 300
 301         /* Set CS0 to SDRAM parameters */
 302         li      t2, 0x000014d8
 303         sw      t2, MC_CFGPB0(t1)
 304
 305         /* Set SDRAM latency parameters */
 306         li      t2, 0x00036325;   /* BC PC100 */
 307         sw      t2, MC_LATENCY(t1)
 308
 309         /* Set SDRAM refresh rate */
 310         li      t2, 0x00000C30
 311         sw      t2, MC_TREFRESH(t1)
 312
 313         /* Clear Power-down registers */
 314         sw      zero, MC_SELFRFSH(t1)
 315
 316         /* Finally enable the controller */
 317         li      t2, 1
 318         sw      t2, MC_CTRLENA(t1)
 319
 320
 321         j       ra
 322         nop
 323
 324
 325         .end    sdram_init
 326
 327 /*
 328  * void ddrram_init(long)
 329  *
 330  * a0 has the clock value
 331  */
 332         .globl  ddrram_init
 333         .ent    ddrram_init
 334 ddrram_init:
 335
 336         /* DDR-DRAM Initialization
 337          */
 338         li      t1, MC_MODUL_BASE
 339
 340         /* Clear Error log registers */
 341         sw      zero, MC_ERRCAUSE(t1)
 342         sw      zero, MC_ERRADDR(t1)
 343
 344         /* Enable DDR module in memory controller */
 345         li      t3, MC_DDRRAM_ENABLE
 346         lw      t2, MC_CON(t1)
 347         or      t3, t2, t3
 348         sw      t3, MC_CON(t1)
 349
 350         li      t1, MC_DDR_MODUL_BASE
 351
 352     /* Write configuration to DDR controller registers */
 353         li      t2, MC_DC0_VALUE
 354         sw      t2, MC_DC00(t1)
 355
 356         li      t2, MC_DC1_VALUE
 357         sw      t2, MC_DC01(t1)
 358
 359         li      t2, MC_DC2_VALUE
 360         sw      t2, MC_DC02(t1)
 361
 362         li      t2, MC_DC3_VALUE
 363         sw      t2, MC_DC03(t1)
 364
 365         li      t2, MC_DC4_VALUE
 366         sw      t2, MC_DC04(t1)
 367
 368         li      t2, MC_DC5_VALUE
 369         sw      t2, MC_DC05(t1)
 370
 371         li      t2, MC_DC6_VALUE
 372         sw      t2, MC_DC06(t1)
 373
 374         li      t2, MC_DC7_VALUE
 375         sw      t2, MC_DC07(t1)
 376
 377         li      t2, MC_DC8_VALUE
 378         sw      t2, MC_DC08(t1)
 379
 380         li      t2, MC_DC9_VALUE
 381         sw      t2, MC_DC09(t1)
 382
 383         li      t2, MC_DC10_VALUE
 384         sw      t2, MC_DC10(t1)
 385
 386         li      t2, MC_DC11_VALUE
 387         sw      t2, MC_DC11(t1)
 388
 389         li      t2, MC_DC12_VALUE
 390         sw      t2, MC_DC12(t1)
 391
 392         li      t2, MC_DC13_VALUE
 393         sw      t2, MC_DC13(t1)
 394
 395         li      t2, MC_DC14_VALUE
 396         sw      t2, MC_DC14(t1)
 397
 398         li      t2, MC_DC15_VALUE
 399         sw      t2, MC_DC15(t1)
 400
 401         li      t2, MC_DC16_VALUE
 402         sw      t2, MC_DC16(t1)
 403
 404         li      t2, MC_DC17_VALUE
 405         sw      t2, MC_DC17(t1)
 406
 407         li      t2, MC_DC18_VALUE
 408         sw      t2, MC_DC18(t1)
 409
 410         li      t2, MC_DC19_VALUE
 411         sw      t2, MC_DC19(t1)
 412
 413         li      t2, MC_DC20_VALUE
 414         sw      t2, MC_DC20(t1)
 415
 416         li      t2, MC_DC21_VALUE
 417         sw      t2, MC_DC21(t1)
 418
 419         li      t2, MC_DC22_VALUE
 420         sw      t2, MC_DC22(t1)
 421
 422         li      t2, MC_DC23_VALUE
 423         sw      t2, MC_DC23(t1)
 424
 425         li      t2, MC_DC24_VALUE
 426         sw      t2, MC_DC24(t1)
 427
 428         li      t2, MC_DC25_VALUE
 429         sw      t2, MC_DC25(t1)
 430
 431         li      t2, MC_DC26_VALUE
 432         sw      t2, MC_DC26(t1)
 433
 434         li      t2, MC_DC27_VALUE
 435         sw      t2, MC_DC27(t1)
 436
 437         li      t2, MC_DC28_VALUE
 438         sw      t2, MC_DC28(t1)
 439
 440         li      t2, MC_DC29_VALUE
 441         sw      t2, MC_DC29(t1)
 442
 443         li      t2, MC_DC30_VALUE
 444         sw      t2, MC_DC30(t1)
 445
 446         li      t2, MC_DC31_VALUE
 447         sw      t2, MC_DC31(t1)
 448
 449         li      t2, MC_DC32_VALUE
 450         sw      t2, MC_DC32(t1)
 451
 452         li      t2, MC_DC33_VALUE
 453         sw      t2, MC_DC33(t1)
 454
 455         li      t2, MC_DC34_VALUE
 456         sw      t2, MC_DC34(t1)
 457
 458         li      t2, MC_DC35_VALUE
 459         sw      t2, MC_DC35(t1)
 460
 461         li      t2, MC_DC36_VALUE
 462         sw      t2, MC_DC36(t1)
 463
 464         li      t2, MC_DC37_VALUE
 465         sw      t2, MC_DC37(t1)
 466
 467         li      t2, MC_DC38_VALUE
 468         sw      t2, MC_DC38(t1)
 469
 470         li      t2, MC_DC39_VALUE
 471         sw      t2, MC_DC39(t1)
 472
 473         li      t2, MC_DC40_VALUE
 474         sw      t2, MC_DC40(t1)
 475
 476         li      t2, MC_DC41_VALUE
 477         sw      t2, MC_DC41(t1)
 478
 479         li      t2, MC_DC42_VALUE
 480         sw      t2, MC_DC42(t1)
 481
 482         li      t2, MC_DC43_VALUE
 483         sw      t2, MC_DC43(t1)
 484
 485         li      t2, MC_DC44_VALUE
 486         sw      t2, MC_DC44(t1)
 487
 488         li      t2, MC_DC45_VALUE
 489         sw      t2, MC_DC45(t1)
 490
 491         li      t2, MC_DC46_VALUE
 492         sw      t2, MC_DC46(t1)
 493
 494         li      t2, 0x00000100
 495         sw      t2, MC_DC03(t1)
 496
 497         j       ra
 498         nop
 499
 500
 501         .end    ddrram_init
 502
 503         .globl  lowlevel_init
 504         .ent    lowlevel_init
 505 lowlevel_init:
 506         /* EBU, CGU and SDRAM/DDR-RAM Initialization.
 507          */
 508         move    t0, ra
 509         /* We rely on the fact that neither cgu_init() nor sdram_init()
 510          * modify t0
 511          */
 512 #ifdef DANUBE_BOOT_FROM_EBU
 513 #ifdef DANUBE_DDR_RAM_166M
 514 //05252006
 515   /* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
 516         li  a0,0xe8
 517         bal cgu_init
 518         nop
 519 #endif
 520 #ifdef PROMOSDDR400
 521         li  a0,0xe8
 522         bal cgu_init
 523         nop
 524 #endif
 525 #ifdef DDR_SAMSUNG_166M
 526         li  a0,0xe8
 527         bal cgu_init
 528         nop
 529 #endif
 530 #ifdef DDR_PSC_166M
 531         li  a0,0xe8
 532         bal cgu_init
 533         nop
 534 #endif
 535 #ifdef  DANUBE_DDR_RAM_133M
 536         li  a0,0xe9
 537 //05252006
 538         bal     cgu_init
 539         nop
 540 #endif
 541 #endif
 542 /*TODO:liupeng add this define !!!! */
 543 /*
 544   #define DANUBE_BOOT_FROM_EBU
 545   #define DANUBE_USE_DDR_RAM
 546 */
 547
 548 //06063001-joelin disable the PCI CFRAME mask-start
 549 #ifdef DISABLE_CFRAME
 550         li  t1, PCI_CR_PCI      //mw bf103034 80000000
 551         li  t2, 0x80000000
 552         sw      t2,0(t1)
 553
 554         li  t1, PCI_CR_PCI_MOD_REG      //mw be105430 103
 555         li  t2, 0x103
 556         sw  t2,0(t1)
 557
 558         li  t1, CS_CFM                  //mw b700006c 0
 559         li  t2, 0x00
 560         sw  t2, 0(t1)
 561
 562         li  t1, PCI_CR_PCI_MOD_REG      //mw be105430 103
 563         li  t2, 0x1000103
 564         sw  t2, 0(t1)
 565 #endif
 566 //06063001-joelin disable the PCI CFRAME mask-end
 567
 568 #ifdef DANUBE_BOOT_FROM_EBU
 569 #ifdef DANUBE_USE_DDR_RAM
 570         bal     ddrram_init
 571         nop
 572 #else
 573         bal     sdram_init
 574         nop
 575 #endif
 576 #endif
 577
 578         move    ra, t0
 579         j       ra
 580         nop
 581
 582         .end    lowlevel_init